Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.81 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2851
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T2760 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2601725546 Jul 14 07:03:45 PM PDT 24 Jul 14 07:03:49 PM PDT 24 291657304 ps
T258 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1927737115 Jul 14 07:03:45 PM PDT 24 Jul 14 07:03:48 PM PDT 24 176076358 ps
T284 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1687033062 Jul 14 07:04:29 PM PDT 24 Jul 14 07:04:30 PM PDT 24 59373163 ps
T2761 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3165878463 Jul 14 07:03:45 PM PDT 24 Jul 14 07:03:46 PM PDT 24 63646629 ps
T2762 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1283482906 Jul 14 07:03:37 PM PDT 24 Jul 14 07:03:41 PM PDT 24 295148091 ps
T259 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2454030833 Jul 14 07:04:19 PM PDT 24 Jul 14 07:04:20 PM PDT 24 90309125 ps
T2763 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1172102774 Jul 14 07:03:48 PM PDT 24 Jul 14 07:03:50 PM PDT 24 36741257 ps
T2764 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2088746600 Jul 14 07:04:07 PM PDT 24 Jul 14 07:04:11 PM PDT 24 279297962 ps
T2765 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2661912159 Jul 14 07:03:38 PM PDT 24 Jul 14 07:03:40 PM PDT 24 68356162 ps
T2766 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1807588879 Jul 14 07:04:27 PM PDT 24 Jul 14 07:04:29 PM PDT 24 111180577 ps
T2767 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3638583860 Jul 14 07:04:22 PM PDT 24 Jul 14 07:04:24 PM PDT 24 81186378 ps
T2768 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.109701751 Jul 14 07:04:28 PM PDT 24 Jul 14 07:04:31 PM PDT 24 188326660 ps
T2769 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.373486539 Jul 14 07:04:24 PM PDT 24 Jul 14 07:04:28 PM PDT 24 380147920 ps
T2770 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4278479317 Jul 14 07:04:32 PM PDT 24 Jul 14 07:04:34 PM PDT 24 113321417 ps
T2771 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1888097572 Jul 14 07:03:43 PM PDT 24 Jul 14 07:03:45 PM PDT 24 62027449 ps
T2772 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.786002176 Jul 14 07:04:25 PM PDT 24 Jul 14 07:04:26 PM PDT 24 137757118 ps
T2773 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.633479157 Jul 14 07:03:29 PM PDT 24 Jul 14 07:03:31 PM PDT 24 153139761 ps
T2774 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4272886570 Jul 14 07:03:49 PM PDT 24 Jul 14 07:03:50 PM PDT 24 51174128 ps
T2775 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3561398865 Jul 14 07:04:21 PM PDT 24 Jul 14 07:04:23 PM PDT 24 89664573 ps
T2776 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.552158429 Jul 14 07:04:20 PM PDT 24 Jul 14 07:04:22 PM PDT 24 174223149 ps
T2777 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.134239808 Jul 14 07:04:32 PM PDT 24 Jul 14 07:04:34 PM PDT 24 100232366 ps
T2778 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1484125362 Jul 14 07:03:26 PM PDT 24 Jul 14 07:03:27 PM PDT 24 98401403 ps
T2779 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2730237673 Jul 14 07:04:28 PM PDT 24 Jul 14 07:04:29 PM PDT 24 36179303 ps
T2780 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3335156857 Jul 14 07:04:32 PM PDT 24 Jul 14 07:04:34 PM PDT 24 36403715 ps
T2781 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1334102120 Jul 14 07:03:55 PM PDT 24 Jul 14 07:03:58 PM PDT 24 114489051 ps
T2782 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3072969703 Jul 14 07:04:00 PM PDT 24 Jul 14 07:04:03 PM PDT 24 181764668 ps
T2783 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.716240990 Jul 14 07:03:44 PM PDT 24 Jul 14 07:03:49 PM PDT 24 788245545 ps
T2784 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2249153940 Jul 14 07:04:21 PM PDT 24 Jul 14 07:04:22 PM PDT 24 44206667 ps
T2785 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2286902718 Jul 14 07:04:26 PM PDT 24 Jul 14 07:04:27 PM PDT 24 73020427 ps
T2786 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.177458269 Jul 14 07:04:23 PM PDT 24 Jul 14 07:04:26 PM PDT 24 123728390 ps
T2787 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1502437589 Jul 14 07:03:49 PM PDT 24 Jul 14 07:03:51 PM PDT 24 97453136 ps
T2788 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4266023692 Jul 14 07:04:06 PM PDT 24 Jul 14 07:04:09 PM PDT 24 305609114 ps
T2789 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1100139770 Jul 14 07:04:00 PM PDT 24 Jul 14 07:04:02 PM PDT 24 244908097 ps
T292 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2754096636 Jul 14 07:04:21 PM PDT 24 Jul 14 07:04:24 PM PDT 24 522994138 ps
T289 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2418156392 Jul 14 07:03:45 PM PDT 24 Jul 14 07:03:50 PM PDT 24 808190677 ps
T2790 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4187441253 Jul 14 07:04:26 PM PDT 24 Jul 14 07:04:27 PM PDT 24 37792436 ps
T296 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3979108270 Jul 14 07:03:32 PM PDT 24 Jul 14 07:03:38 PM PDT 24 974670387 ps
T2791 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1746793163 Jul 14 07:03:30 PM PDT 24 Jul 14 07:03:38 PM PDT 24 1041192245 ps
T293 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2751156041 Jul 14 07:04:06 PM PDT 24 Jul 14 07:04:10 PM PDT 24 459256871 ps
T2792 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3777342213 Jul 14 07:04:27 PM PDT 24 Jul 14 07:04:29 PM PDT 24 126113296 ps
T297 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.833744938 Jul 14 07:04:02 PM PDT 24 Jul 14 07:04:07 PM PDT 24 720426873 ps
T2793 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1118943387 Jul 14 07:03:38 PM PDT 24 Jul 14 07:03:41 PM PDT 24 203047813 ps
T2794 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4157815999 Jul 14 07:03:32 PM PDT 24 Jul 14 07:03:34 PM PDT 24 67459680 ps
T2795 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1426544975 Jul 14 07:03:59 PM PDT 24 Jul 14 07:04:01 PM PDT 24 141248472 ps
T2796 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3809173994 Jul 14 07:04:14 PM PDT 24 Jul 14 07:04:17 PM PDT 24 269406061 ps
T2797 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.887182231 Jul 14 07:03:55 PM PDT 24 Jul 14 07:03:57 PM PDT 24 63958447 ps
T2798 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2151164443 Jul 14 07:03:57 PM PDT 24 Jul 14 07:03:59 PM PDT 24 112646102 ps
T2799 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2401724990 Jul 14 07:03:49 PM PDT 24 Jul 14 07:03:51 PM PDT 24 58193474 ps
T2800 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.882135328 Jul 14 07:04:22 PM PDT 24 Jul 14 07:04:26 PM PDT 24 395551097 ps
T2801 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3049023624 Jul 14 07:04:28 PM PDT 24 Jul 14 07:04:30 PM PDT 24 71492504 ps
T2802 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3488744298 Jul 14 07:04:07 PM PDT 24 Jul 14 07:04:08 PM PDT 24 91836757 ps
T2803 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3425813409 Jul 14 07:04:13 PM PDT 24 Jul 14 07:04:14 PM PDT 24 45340313 ps
T2804 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2529387355 Jul 14 07:03:54 PM PDT 24 Jul 14 07:03:55 PM PDT 24 56070640 ps
T2805 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1037035979 Jul 14 07:03:26 PM PDT 24 Jul 14 07:03:28 PM PDT 24 102341260 ps
T2806 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3394090182 Jul 14 07:04:07 PM PDT 24 Jul 14 07:04:08 PM PDT 24 55507913 ps
T2807 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2688366294 Jul 14 07:04:24 PM PDT 24 Jul 14 07:04:25 PM PDT 24 38211561 ps
T2808 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2612213290 Jul 14 07:03:44 PM PDT 24 Jul 14 07:03:46 PM PDT 24 106110511 ps
T2809 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3203508772 Jul 14 07:04:31 PM PDT 24 Jul 14 07:04:32 PM PDT 24 39173184 ps
T2810 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1746273310 Jul 14 07:03:24 PM PDT 24 Jul 14 07:03:25 PM PDT 24 72985204 ps
T2811 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3226897379 Jul 14 07:04:23 PM PDT 24 Jul 14 07:04:25 PM PDT 24 37284349 ps
T2812 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3283456958 Jul 14 07:04:07 PM PDT 24 Jul 14 07:04:09 PM PDT 24 78598809 ps
T2813 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1067643302 Jul 14 07:04:34 PM PDT 24 Jul 14 07:04:35 PM PDT 24 63354004 ps
T2814 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1720365735 Jul 14 07:04:32 PM PDT 24 Jul 14 07:04:33 PM PDT 24 36358258 ps
T2815 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.891611611 Jul 14 07:03:45 PM PDT 24 Jul 14 07:03:55 PM PDT 24 886363565 ps
T2816 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1641359634 Jul 14 07:04:05 PM PDT 24 Jul 14 07:04:07 PM PDT 24 119112305 ps
T2817 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.60262801 Jul 14 07:03:24 PM PDT 24 Jul 14 07:03:26 PM PDT 24 190915465 ps
T2818 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1494571031 Jul 14 07:03:38 PM PDT 24 Jul 14 07:03:44 PM PDT 24 608953688 ps
T2819 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3837777962 Jul 14 07:04:25 PM PDT 24 Jul 14 07:04:27 PM PDT 24 191064134 ps
T2820 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1612742773 Jul 14 07:03:23 PM PDT 24 Jul 14 07:03:25 PM PDT 24 93240140 ps
T2821 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1735689750 Jul 14 07:04:15 PM PDT 24 Jul 14 07:04:16 PM PDT 24 75249631 ps
T294 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3638980734 Jul 14 07:04:20 PM PDT 24 Jul 14 07:04:25 PM PDT 24 1316809066 ps
T2822 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4255853829 Jul 14 07:04:06 PM PDT 24 Jul 14 07:04:12 PM PDT 24 804975802 ps
T2823 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1890128933 Jul 14 07:03:50 PM PDT 24 Jul 14 07:03:52 PM PDT 24 163416278 ps
T2824 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.446057599 Jul 14 07:03:39 PM PDT 24 Jul 14 07:03:41 PM PDT 24 167687269 ps
T2825 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.122534302 Jul 14 07:04:22 PM PDT 24 Jul 14 07:04:25 PM PDT 24 153160193 ps
T2826 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.94342123 Jul 14 07:03:26 PM PDT 24 Jul 14 07:03:28 PM PDT 24 177264335 ps
T2827 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2881703970 Jul 14 07:04:22 PM PDT 24 Jul 14 07:04:25 PM PDT 24 188647832 ps
T2828 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1747445214 Jul 14 07:03:42 PM PDT 24 Jul 14 07:03:44 PM PDT 24 39823221 ps
T2829 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1788367250 Jul 14 07:03:45 PM PDT 24 Jul 14 07:03:47 PM PDT 24 128621196 ps
T2830 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1923549634 Jul 14 07:04:35 PM PDT 24 Jul 14 07:04:36 PM PDT 24 81974687 ps
T2831 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1273773894 Jul 14 07:03:43 PM PDT 24 Jul 14 07:03:45 PM PDT 24 28106606 ps
T2832 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1195327663 Jul 14 07:04:06 PM PDT 24 Jul 14 07:04:07 PM PDT 24 41693424 ps
T2833 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2206321029 Jul 14 07:03:59 PM PDT 24 Jul 14 07:04:00 PM PDT 24 96641450 ps
T2834 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2447510118 Jul 14 07:04:05 PM PDT 24 Jul 14 07:04:07 PM PDT 24 107847041 ps
T2835 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3181597466 Jul 14 07:04:26 PM PDT 24 Jul 14 07:04:28 PM PDT 24 44447373 ps
T2836 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2638029855 Jul 14 07:03:59 PM PDT 24 Jul 14 07:04:01 PM PDT 24 74663905 ps
T2837 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.655632678 Jul 14 07:03:24 PM PDT 24 Jul 14 07:03:28 PM PDT 24 127292335 ps
T2838 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1096335288 Jul 14 07:04:00 PM PDT 24 Jul 14 07:04:02 PM PDT 24 213203198 ps
T2839 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2968607537 Jul 14 07:03:24 PM PDT 24 Jul 14 07:03:30 PM PDT 24 885975254 ps
T2840 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4081647607 Jul 14 07:03:38 PM PDT 24 Jul 14 07:03:42 PM PDT 24 138293776 ps
T2841 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2709217967 Jul 14 07:04:20 PM PDT 24 Jul 14 07:04:22 PM PDT 24 68988983 ps
T2842 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.571481389 Jul 14 07:03:23 PM PDT 24 Jul 14 07:03:25 PM PDT 24 44585494 ps
T2843 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3236199215 Jul 14 07:04:28 PM PDT 24 Jul 14 07:04:29 PM PDT 24 44368853 ps
T2844 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1666664739 Jul 14 07:03:25 PM PDT 24 Jul 14 07:03:27 PM PDT 24 215328923 ps
T2845 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2026792704 Jul 14 07:03:26 PM PDT 24 Jul 14 07:03:29 PM PDT 24 247065090 ps
T2846 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.385131358 Jul 14 07:04:01 PM PDT 24 Jul 14 07:04:02 PM PDT 24 88874410 ps
T2847 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3431091600 Jul 14 07:04:02 PM PDT 24 Jul 14 07:04:04 PM PDT 24 44917106 ps
T2848 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1126421271 Jul 14 07:04:08 PM PDT 24 Jul 14 07:04:10 PM PDT 24 97114873 ps
T2849 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.561978323 Jul 14 07:03:26 PM PDT 24 Jul 14 07:03:27 PM PDT 24 75875211 ps
T2850 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3322912838 Jul 14 07:04:28 PM PDT 24 Jul 14 07:04:30 PM PDT 24 65122709 ps
T2851 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2103921007 Jul 14 07:03:43 PM PDT 24 Jul 14 07:03:47 PM PDT 24 168617912 ps

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3614919623
Short name T28
Test name
Test status
Simulation time 226353411 ps
CPU time 0.9 seconds
Started Jul 14 07:12:30 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206856 kb
Host smart-147f3a7d-952b-4996-9752-89c12bd2833c
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3614919623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3614919623
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/30.usbdev_device_address.4292495854
Short name T85
Test name
Test status
Simulation time 6726935586 ps
CPU time 12.61 seconds
Started Jul 14 07:19:15 PM PDT 24
Finished Jul 14 07:19:38 PM PDT 24
Peak memory 207096 kb
Host smart-ce483190-708c-48e8-a5ca-dda78078b1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42924
95854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.4292495854
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3036935180
Short name T205
Test name
Test status
Simulation time 33779634 ps
CPU time 0.68 seconds
Started Jul 14 07:04:30 PM PDT 24
Finished Jul 14 07:04:31 PM PDT 24
Peak memory 206228 kb
Host smart-5825741f-f4bb-4a44-afae-19e8476e1b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3036935180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3036935180
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3330620039
Short name T7
Test name
Test status
Simulation time 23330907760 ps
CPU time 22.19 seconds
Started Jul 14 07:15:56 PM PDT 24
Finished Jul 14 07:18:03 PM PDT 24
Peak memory 207132 kb
Host smart-6bb9478b-8880-47f7-bba3-2f05b68c68d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3330620039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3330620039
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2494044532
Short name T196
Test name
Test status
Simulation time 851937002 ps
CPU time 5.14 seconds
Started Jul 14 07:04:20 PM PDT 24
Finished Jul 14 07:04:26 PM PDT 24
Peak memory 206604 kb
Host smart-bb3b9cbc-594f-4811-9d83-e5cf776cdf9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2494044532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2494044532
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3929672905
Short name T4
Test name
Test status
Simulation time 4648383342 ps
CPU time 13.82 seconds
Started Jul 14 07:12:47 PM PDT 24
Finished Jul 14 07:13:19 PM PDT 24
Peak memory 207156 kb
Host smart-c7c9fe00-edf6-438c-beb5-adeffcd124b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39296
72905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3929672905
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.779033904
Short name T89
Test name
Test status
Simulation time 198917567 ps
CPU time 0.91 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 206860 kb
Host smart-4c34f143-2c6c-4cf2-bddb-bd3b8dd7c62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77903
3904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.779033904
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.195085114
Short name T70
Test name
Test status
Simulation time 5886408420 ps
CPU time 54.54 seconds
Started Jul 14 07:16:07 PM PDT 24
Finished Jul 14 07:18:42 PM PDT 24
Peak memory 207076 kb
Host smart-a0ef46d6-4412-4b8c-b9ee-16e9b4fedbc0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=195085114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.195085114
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2324275402
Short name T209
Test name
Test status
Simulation time 116985975 ps
CPU time 0.79 seconds
Started Jul 14 07:03:30 PM PDT 24
Finished Jul 14 07:03:31 PM PDT 24
Peak memory 206400 kb
Host smart-491e1a72-3735-4fc4-9031-670d869e40ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2324275402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2324275402
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2278479359
Short name T11
Test name
Test status
Simulation time 13304425655 ps
CPU time 13.1 seconds
Started Jul 14 07:17:04 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206932 kb
Host smart-2669927e-c4cd-4e4b-b266-7aee849f1378
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2278479359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2278479359
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.70389331
Short name T34
Test name
Test status
Simulation time 147577127 ps
CPU time 0.76 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:36 PM PDT 24
Peak memory 206856 kb
Host smart-827e0d28-4736-47f1-a327-7e1120c0217a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70389
331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.70389331
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1784753537
Short name T194
Test name
Test status
Simulation time 607959595 ps
CPU time 1.53 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:12:47 PM PDT 24
Peak memory 224564 kb
Host smart-746e25dc-8482-418e-ae48-1f4238c3cacc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1784753537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1784753537
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1979230400
Short name T27
Test name
Test status
Simulation time 446081016 ps
CPU time 1.35 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:13:57 PM PDT 24
Peak memory 206876 kb
Host smart-a01a45c9-c2ea-4890-96b4-e4ecda586f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19792
30400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1979230400
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1415347713
Short name T224
Test name
Test status
Simulation time 319544048 ps
CPU time 3.23 seconds
Started Jul 14 07:04:19 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 214852 kb
Host smart-053abe3f-e2fc-4870-9f38-0888c906dd8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1415347713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1415347713
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2402633973
Short name T93
Test name
Test status
Simulation time 200468447 ps
CPU time 0.87 seconds
Started Jul 14 07:15:51 PM PDT 24
Finished Jul 14 07:17:40 PM PDT 24
Peak memory 206892 kb
Host smart-301e4a23-3849-4e8c-a0d8-21bd62c1359a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24026
33973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2402633973
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3542121774
Short name T24
Test name
Test status
Simulation time 47176198 ps
CPU time 0.69 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:01 PM PDT 24
Peak memory 206888 kb
Host smart-0440516b-8524-4996-ac8e-99f0864f8151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35421
21774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3542121774
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2268895958
Short name T208
Test name
Test status
Simulation time 54350534 ps
CPU time 0.67 seconds
Started Jul 14 07:04:22 PM PDT 24
Finished Jul 14 07:04:24 PM PDT 24
Peak memory 206348 kb
Host smart-dcc2a9a7-755d-4e39-bf00-ebfdd8d5716a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2268895958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2268895958
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3449018551
Short name T74
Test name
Test status
Simulation time 309249555 ps
CPU time 0.96 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:12:44 PM PDT 24
Peak memory 206864 kb
Host smart-fec24a57-ae82-41df-8c7d-4b6470dc036e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34490
18551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3449018551
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.1638786127
Short name T47
Test name
Test status
Simulation time 20170666488 ps
CPU time 18.78 seconds
Started Jul 14 07:12:29 PM PDT 24
Finished Jul 14 07:12:53 PM PDT 24
Peak memory 206908 kb
Host smart-903078e0-e900-4fe6-a0af-bc0c1842868e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16387
86127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1638786127
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4051234340
Short name T252
Test name
Test status
Simulation time 76823976 ps
CPU time 1 seconds
Started Jul 14 07:04:26 PM PDT 24
Finished Jul 14 07:04:28 PM PDT 24
Peak memory 206488 kb
Host smart-6096b1e2-6089-4182-ade6-ae1ffc47938a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4051234340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4051234340
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2376880109
Short name T548
Test name
Test status
Simulation time 141416036 ps
CPU time 0.76 seconds
Started Jul 14 07:20:57 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 206856 kb
Host smart-1ef91ca5-171f-465f-9df7-6c5f57d8d4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23768
80109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2376880109
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3402750260
Short name T222
Test name
Test status
Simulation time 13591250235 ps
CPU time 28.71 seconds
Started Jul 14 07:16:39 PM PDT 24
Finished Jul 14 07:18:40 PM PDT 24
Peak memory 207124 kb
Host smart-9ef0a994-f8db-4aef-9915-6ef6cef8fe0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34027
50260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3402750260
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3074461937
Short name T288
Test name
Test status
Simulation time 1002516063 ps
CPU time 4.84 seconds
Started Jul 14 07:03:55 PM PDT 24
Finished Jul 14 07:04:01 PM PDT 24
Peak memory 206544 kb
Host smart-179cebef-1a8c-4f45-89d6-473a72cc36a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3074461937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3074461937
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3638583860
Short name T2767
Test name
Test status
Simulation time 81186378 ps
CPU time 0.71 seconds
Started Jul 14 07:04:22 PM PDT 24
Finished Jul 14 07:04:24 PM PDT 24
Peak memory 206368 kb
Host smart-9dca4883-a46a-40f4-8f78-cc527c2a01ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3638583860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3638583860
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1578307989
Short name T556
Test name
Test status
Simulation time 151891137 ps
CPU time 0.79 seconds
Started Jul 14 07:14:48 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206872 kb
Host smart-66cbdb79-edf0-4bbe-9011-a0ea41e76df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15783
07989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1578307989
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.496924199
Short name T347
Test name
Test status
Simulation time 154033834 ps
CPU time 0.79 seconds
Started Jul 14 07:16:30 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206900 kb
Host smart-4138db18-8540-4596-953b-ea4aedc26c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49692
4199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.496924199
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.833744938
Short name T297
Test name
Test status
Simulation time 720426873 ps
CPU time 4.37 seconds
Started Jul 14 07:04:02 PM PDT 24
Finished Jul 14 07:04:07 PM PDT 24
Peak memory 206572 kb
Host smart-9801bbde-3378-4f4b-b76b-26964ad0b003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=833744938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.833744938
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.33579830
Short name T66
Test name
Test status
Simulation time 463525643 ps
CPU time 1.28 seconds
Started Jul 14 07:12:24 PM PDT 24
Finished Jul 14 07:12:30 PM PDT 24
Peak memory 206840 kb
Host smart-213b1b86-eb9e-4fcc-8d9f-c421f394fb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33579
830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.33579830
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1101822326
Short name T2751
Test name
Test status
Simulation time 96476173 ps
CPU time 0.7 seconds
Started Jul 14 07:04:25 PM PDT 24
Finished Jul 14 07:04:26 PM PDT 24
Peak memory 206404 kb
Host smart-af052c0f-53a2-4df5-93cb-21996de0e738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1101822326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1101822326
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1585988456
Short name T190
Test name
Test status
Simulation time 61843617 ps
CPU time 0.66 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206924 kb
Host smart-65f18cc2-38d2-4a98-9da7-ba88d7e83ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1585988456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1585988456
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3210684412
Short name T156
Test name
Test status
Simulation time 13268119379 ps
CPU time 90.86 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:14:40 PM PDT 24
Peak memory 207124 kb
Host smart-65eab3dc-561a-4bad-b441-b21e2a9b0218
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3210684412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3210684412
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.1445361241
Short name T44
Test name
Test status
Simulation time 10237037816 ps
CPU time 90.11 seconds
Started Jul 14 07:18:41 PM PDT 24
Finished Jul 14 07:20:28 PM PDT 24
Peak memory 207136 kb
Host smart-38760c3f-80a0-4208-8402-3d6a97df3426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14453
61241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.1445361241
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2843441940
Short name T466
Test name
Test status
Simulation time 4439967995 ps
CPU time 4.78 seconds
Started Jul 14 07:12:25 PM PDT 24
Finished Jul 14 07:12:34 PM PDT 24
Peak memory 207148 kb
Host smart-09a3455b-ba07-48d7-bafe-10a1cb029366
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2843441940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2843441940
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1187831590
Short name T99
Test name
Test status
Simulation time 1447962387 ps
CPU time 3.1 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:14:00 PM PDT 24
Peak memory 206988 kb
Host smart-f3cc2cf9-4058-473e-b739-239e650ab93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11878
31590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1187831590
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3927779370
Short name T53
Test name
Test status
Simulation time 248506966 ps
CPU time 0.98 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:12:39 PM PDT 24
Peak memory 206900 kb
Host smart-1738d919-b9d3-4a76-8e99-1399db7ac5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39277
79370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3927779370
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.2821954437
Short name T61
Test name
Test status
Simulation time 151958283 ps
CPU time 0.8 seconds
Started Jul 14 07:12:22 PM PDT 24
Finished Jul 14 07:12:25 PM PDT 24
Peak memory 206884 kb
Host smart-37e5b122-1578-4f8b-9d23-81a344872d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28219
54437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.2821954437
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1687033062
Short name T284
Test name
Test status
Simulation time 59373163 ps
CPU time 0.72 seconds
Started Jul 14 07:04:29 PM PDT 24
Finished Jul 14 07:04:30 PM PDT 24
Peak memory 206388 kb
Host smart-81a50e05-78fb-470f-9b67-d1dd82e1b4d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1687033062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1687033062
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3863323156
Short name T2752
Test name
Test status
Simulation time 39357444 ps
CPU time 0.64 seconds
Started Jul 14 07:04:27 PM PDT 24
Finished Jul 14 07:04:28 PM PDT 24
Peak memory 206364 kb
Host smart-36325670-ca3e-42de-be60-f3739c93e860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3863323156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3863323156
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1878720137
Short name T149
Test name
Test status
Simulation time 23630358548 ps
CPU time 530.06 seconds
Started Jul 14 07:13:10 PM PDT 24
Finished Jul 14 07:22:16 PM PDT 24
Peak memory 207108 kb
Host smart-f49d4001-8e1e-48d9-99e7-2fefbd6c482b
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1878720137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1878720137
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1609883056
Short name T226
Test name
Test status
Simulation time 81054033 ps
CPU time 1.45 seconds
Started Jul 14 07:04:06 PM PDT 24
Finished Jul 14 07:04:09 PM PDT 24
Peak memory 206628 kb
Host smart-90fb45e8-a553-4367-9b70-4c1e89959746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609883056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1609883056
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.4183443721
Short name T145
Test name
Test status
Simulation time 6648139997 ps
CPU time 24.48 seconds
Started Jul 14 07:13:49 PM PDT 24
Finished Jul 14 07:14:15 PM PDT 24
Peak memory 207128 kb
Host smart-a96c6663-75f5-4574-bcc7-7d483dca1d7c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4183443721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.4183443721
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3479368775
Short name T157
Test name
Test status
Simulation time 7514216959 ps
CPU time 29.79 seconds
Started Jul 14 07:12:49 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 207092 kb
Host smart-d9b64b67-cb7f-479e-80f1-33a908348d1f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3479368775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3479368775
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2687165050
Short name T193
Test name
Test status
Simulation time 153615023 ps
CPU time 0.79 seconds
Started Jul 14 07:12:31 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206868 kb
Host smart-8a556ca5-be19-4ca9-8de5-38c8842f835a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
65050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2687165050
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3147717517
Short name T639
Test name
Test status
Simulation time 181071261 ps
CPU time 2.09 seconds
Started Jul 14 07:14:12 PM PDT 24
Finished Jul 14 07:15:24 PM PDT 24
Peak memory 207056 kb
Host smart-532b2416-fc51-4085-a9e4-5fc1c3a11b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31477
17517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3147717517
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2197227377
Short name T63
Test name
Test status
Simulation time 142603623 ps
CPU time 0.78 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:11 PM PDT 24
Peak memory 206880 kb
Host smart-324a60cd-a517-4333-995a-5da5b2783408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972
27377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2197227377
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3662527960
Short name T54
Test name
Test status
Simulation time 149204245 ps
CPU time 0.84 seconds
Started Jul 14 07:12:25 PM PDT 24
Finished Jul 14 07:12:31 PM PDT 24
Peak memory 206868 kb
Host smart-1f816e87-d267-4a92-ad84-8653f1c104bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36625
27960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3662527960
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.4288750553
Short name T64
Test name
Test status
Simulation time 4167932216 ps
CPU time 9.4 seconds
Started Jul 14 07:12:23 PM PDT 24
Finished Jul 14 07:12:34 PM PDT 24
Peak memory 207032 kb
Host smart-2dc67498-8cef-4933-9998-2d7e848c9130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42887
50553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.4288750553
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3610637889
Short name T65
Test name
Test status
Simulation time 197131030 ps
CPU time 0.85 seconds
Started Jul 14 07:12:24 PM PDT 24
Finished Jul 14 07:12:28 PM PDT 24
Peak memory 206868 kb
Host smart-5d16cc00-0766-4078-8ed5-3961046f4cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36106
37889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3610637889
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3418372337
Short name T38
Test name
Test status
Simulation time 45325932 ps
CPU time 0.64 seconds
Started Jul 14 07:12:33 PM PDT 24
Finished Jul 14 07:12:40 PM PDT 24
Peak memory 206824 kb
Host smart-890f7064-d3cd-4f99-b03f-c86c98141b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34183
72337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3418372337
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1710604411
Short name T71
Test name
Test status
Simulation time 166933575 ps
CPU time 0.82 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:12:45 PM PDT 24
Peak memory 206868 kb
Host smart-1902bb07-7218-4626-a7de-a313cf5e5b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106
04411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1710604411
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.163973205
Short name T49
Test name
Test status
Simulation time 155488362 ps
CPU time 0.82 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:44 PM PDT 24
Peak memory 206832 kb
Host smart-920fad12-213c-441e-b346-26e8a062dc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16397
3205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.163973205
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1824483652
Short name T251
Test name
Test status
Simulation time 78219426 ps
CPU time 0.93 seconds
Started Jul 14 07:03:30 PM PDT 24
Finished Jul 14 07:03:32 PM PDT 24
Peak memory 206544 kb
Host smart-026d7940-84d0-41a4-818e-7b74e349f305
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1824483652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1824483652
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1675523907
Short name T83
Test name
Test status
Simulation time 11220798922 ps
CPU time 101.01 seconds
Started Jul 14 07:12:23 PM PDT 24
Finished Jul 14 07:14:06 PM PDT 24
Peak memory 207124 kb
Host smart-c7080088-2971-43dc-b612-9a49ce4b4e96
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1675523907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1675523907
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3471337807
Short name T51
Test name
Test status
Simulation time 405869221 ps
CPU time 1.31 seconds
Started Jul 14 07:12:31 PM PDT 24
Finished Jul 14 07:12:38 PM PDT 24
Peak memory 207040 kb
Host smart-97b98b2c-ba33-4ff4-9fbf-3fe0766554b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34713
37807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3471337807
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3476340147
Short name T2598
Test name
Test status
Simulation time 222294317 ps
CPU time 0.87 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:13:03 PM PDT 24
Peak memory 206928 kb
Host smart-c949ef9e-63e0-46ff-80c8-d27eb48f11d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34763
40147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3476340147
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2571199642
Short name T114
Test name
Test status
Simulation time 198656124 ps
CPU time 0.81 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:00 PM PDT 24
Peak memory 206844 kb
Host smart-5f60e0e3-7260-40dc-8372-d9cae8f146e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25711
99642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2571199642
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1101103919
Short name T102
Test name
Test status
Simulation time 8896722595 ps
CPU time 81.78 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:16:55 PM PDT 24
Peak memory 207044 kb
Host smart-35ce2c7f-612f-4336-a94b-c4a8aec6a937
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1101103919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1101103919
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1384002021
Short name T111
Test name
Test status
Simulation time 258383428 ps
CPU time 0.87 seconds
Started Jul 14 07:14:16 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206872 kb
Host smart-8de4b635-8fd9-4dfe-baef-0c3c15da4ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13840
02021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1384002021
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2018455195
Short name T121
Test name
Test status
Simulation time 187421346 ps
CPU time 0.82 seconds
Started Jul 14 07:14:32 PM PDT 24
Finished Jul 14 07:16:38 PM PDT 24
Peak memory 206876 kb
Host smart-4b5d7cc1-c3b9-4f1d-9fac-1a2d631d054d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20184
55195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2018455195
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1108888447
Short name T127
Test name
Test status
Simulation time 182858574 ps
CPU time 0.84 seconds
Started Jul 14 07:14:48 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 206820 kb
Host smart-d47c60dd-2c44-4e36-ab45-35ed7233c203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11088
88447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1108888447
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.240485449
Short name T109
Test name
Test status
Simulation time 225334525 ps
CPU time 0.93 seconds
Started Jul 14 07:16:31 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206860 kb
Host smart-7989c113-13c0-4cd1-8b7a-c9e2a6dae4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24048
5449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.240485449
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3646150332
Short name T2177
Test name
Test status
Simulation time 233871602 ps
CPU time 0.87 seconds
Started Jul 14 07:16:40 PM PDT 24
Finished Jul 14 07:18:06 PM PDT 24
Peak memory 206860 kb
Host smart-e4af2d61-d5dd-4b34-83d2-b11fe5fb6b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
50332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3646150332
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.626343289
Short name T123
Test name
Test status
Simulation time 250515756 ps
CPU time 0.9 seconds
Started Jul 14 07:17:21 PM PDT 24
Finished Jul 14 07:18:24 PM PDT 24
Peak memory 206844 kb
Host smart-fa768ec8-2445-4485-bd52-e98caa4304f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62634
3289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.626343289
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1023140885
Short name T106
Test name
Test status
Simulation time 227193300 ps
CPU time 0.88 seconds
Started Jul 14 07:17:57 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206832 kb
Host smart-7249003a-a5ff-4dd6-a8a7-905800a0b383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10231
40885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1023140885
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.1193378661
Short name T2712
Test name
Test status
Simulation time 6886108273 ps
CPU time 47.96 seconds
Started Jul 14 07:18:25 PM PDT 24
Finished Jul 14 07:19:35 PM PDT 24
Peak memory 207136 kb
Host smart-5ec4e482-3b72-46c3-a149-adec5dd47cb9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1193378661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1193378661
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2470472183
Short name T132
Test name
Test status
Simulation time 198129714 ps
CPU time 0.87 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:11 PM PDT 24
Peak memory 206880 kb
Host smart-f9e637b9-3e43-41e8-a731-fe91402f4fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24704
72183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2470472183
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.170268950
Short name T126
Test name
Test status
Simulation time 160590868 ps
CPU time 0.82 seconds
Started Jul 14 07:21:08 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206828 kb
Host smart-7c2ded72-9619-4c57-bcc9-e40d79f854c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17026
8950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.170268950
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.655632678
Short name T2837
Test name
Test status
Simulation time 127292335 ps
CPU time 3.12 seconds
Started Jul 14 07:03:24 PM PDT 24
Finished Jul 14 07:03:28 PM PDT 24
Peak memory 206512 kb
Host smart-2f3ddfd2-3599-4d75-aa30-47d60ab9b7ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=655632678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.655632678
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.758440442
Short name T253
Test name
Test status
Simulation time 958414568 ps
CPU time 7.67 seconds
Started Jul 14 07:03:23 PM PDT 24
Finished Jul 14 07:03:31 PM PDT 24
Peak memory 206464 kb
Host smart-23f7a424-1337-4d60-a788-2770fe99b7ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=758440442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.758440442
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1746273310
Short name T2810
Test name
Test status
Simulation time 72985204 ps
CPU time 0.86 seconds
Started Jul 14 07:03:24 PM PDT 24
Finished Jul 14 07:03:25 PM PDT 24
Peak memory 206400 kb
Host smart-18c0aa2c-81ae-4ab9-966b-48e87c771dd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1746273310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1746273310
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2026792704
Short name T2845
Test name
Test status
Simulation time 247065090 ps
CPU time 1.95 seconds
Started Jul 14 07:03:26 PM PDT 24
Finished Jul 14 07:03:29 PM PDT 24
Peak memory 214800 kb
Host smart-9cf3fb7e-45f7-40f4-9171-20112a98c2a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026792704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2026792704
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.571481389
Short name T2842
Test name
Test status
Simulation time 44585494 ps
CPU time 0.87 seconds
Started Jul 14 07:03:23 PM PDT 24
Finished Jul 14 07:03:25 PM PDT 24
Peak memory 206512 kb
Host smart-7c967092-5965-4c7d-904c-f451c7336e4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=571481389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.571481389
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1612742773
Short name T2820
Test name
Test status
Simulation time 93240140 ps
CPU time 0.71 seconds
Started Jul 14 07:03:23 PM PDT 24
Finished Jul 14 07:03:25 PM PDT 24
Peak memory 206352 kb
Host smart-e61c8550-d16d-4b72-b2bc-9dc1bb1807fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1612742773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1612742773
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.130165972
Short name T254
Test name
Test status
Simulation time 222542771 ps
CPU time 2.23 seconds
Started Jul 14 07:03:24 PM PDT 24
Finished Jul 14 07:03:27 PM PDT 24
Peak memory 214776 kb
Host smart-e4925e80-84b1-4dcf-affd-2e63ba62e76d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=130165972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.130165972
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3175979536
Short name T2743
Test name
Test status
Simulation time 191705369 ps
CPU time 3.81 seconds
Started Jul 14 07:03:23 PM PDT 24
Finished Jul 14 07:03:27 PM PDT 24
Peak memory 206500 kb
Host smart-8829d678-b079-4e50-a714-54719b4f67e4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3175979536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3175979536
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.60262801
Short name T2817
Test name
Test status
Simulation time 190915465 ps
CPU time 1.44 seconds
Started Jul 14 07:03:24 PM PDT 24
Finished Jul 14 07:03:26 PM PDT 24
Peak memory 206660 kb
Host smart-b5353619-481c-4f1a-bfcf-0cf0391948cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=60262801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.60262801
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4128604601
Short name T198
Test name
Test status
Simulation time 207714846 ps
CPU time 2.43 seconds
Started Jul 14 07:03:23 PM PDT 24
Finished Jul 14 07:03:26 PM PDT 24
Peak memory 206628 kb
Host smart-97c2e3d5-525a-4bdd-bc0a-fdcfb3aebfc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4128604601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.4128604601
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2968607537
Short name T2839
Test name
Test status
Simulation time 885975254 ps
CPU time 5.01 seconds
Started Jul 14 07:03:24 PM PDT 24
Finished Jul 14 07:03:30 PM PDT 24
Peak memory 206640 kb
Host smart-abaa2798-1e6c-444f-9fd6-9be486101540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2968607537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2968607537
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2264393275
Short name T260
Test name
Test status
Simulation time 193049276 ps
CPU time 2.08 seconds
Started Jul 14 07:03:31 PM PDT 24
Finished Jul 14 07:03:34 PM PDT 24
Peak memory 206544 kb
Host smart-e82a14b6-63e2-42cc-96e8-eacb4fc8cf92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2264393275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2264393275
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1746793163
Short name T2791
Test name
Test status
Simulation time 1041192245 ps
CPU time 7.98 seconds
Started Jul 14 07:03:30 PM PDT 24
Finished Jul 14 07:03:38 PM PDT 24
Peak memory 206460 kb
Host smart-3fcaf364-3432-402b-88c2-1c572afa2ac1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1746793163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1746793163
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.561978323
Short name T2849
Test name
Test status
Simulation time 75875211 ps
CPU time 0.82 seconds
Started Jul 14 07:03:26 PM PDT 24
Finished Jul 14 07:03:27 PM PDT 24
Peak memory 206364 kb
Host smart-676c70c8-c85f-40b5-9216-46f25af0459f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=561978323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.561978323
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.633479157
Short name T2773
Test name
Test status
Simulation time 153139761 ps
CPU time 1.86 seconds
Started Jul 14 07:03:29 PM PDT 24
Finished Jul 14 07:03:31 PM PDT 24
Peak memory 214856 kb
Host smart-86964530-d7f5-4d77-9606-46f41dde55c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633479157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.633479157
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1484125362
Short name T2778
Test name
Test status
Simulation time 98401403 ps
CPU time 0.71 seconds
Started Jul 14 07:03:26 PM PDT 24
Finished Jul 14 07:03:27 PM PDT 24
Peak memory 206352 kb
Host smart-044e0790-ab2a-47ba-be49-c73c518676ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1484125362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1484125362
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1666664739
Short name T2844
Test name
Test status
Simulation time 215328923 ps
CPU time 2.16 seconds
Started Jul 14 07:03:25 PM PDT 24
Finished Jul 14 07:03:27 PM PDT 24
Peak memory 215984 kb
Host smart-32d5b046-035a-46eb-9d0e-1efd39be7d6f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1666664739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1666664739
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1037035979
Short name T2805
Test name
Test status
Simulation time 102341260 ps
CPU time 2.29 seconds
Started Jul 14 07:03:26 PM PDT 24
Finished Jul 14 07:03:28 PM PDT 24
Peak memory 206404 kb
Host smart-87d0d5aa-c75b-446c-bb88-1f7daf7dd67f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1037035979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1037035979
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2880069080
Short name T262
Test name
Test status
Simulation time 111093761 ps
CPU time 1.16 seconds
Started Jul 14 07:03:32 PM PDT 24
Finished Jul 14 07:03:34 PM PDT 24
Peak memory 206600 kb
Host smart-d9c2850c-bf69-4098-ac0e-25a848958377
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2880069080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2880069080
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.94342123
Short name T2826
Test name
Test status
Simulation time 177264335 ps
CPU time 1.64 seconds
Started Jul 14 07:03:26 PM PDT 24
Finished Jul 14 07:03:28 PM PDT 24
Peak memory 222432 kb
Host smart-2ed1baa6-d43f-49ac-b8a2-80c56ae05a04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=94342123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.94342123
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1318024444
Short name T290
Test name
Test status
Simulation time 800149186 ps
CPU time 2.98 seconds
Started Jul 14 07:03:27 PM PDT 24
Finished Jul 14 07:03:31 PM PDT 24
Peak memory 206620 kb
Host smart-50e2f050-125a-434c-bdf4-809d61bb18af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1318024444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1318024444
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1426544975
Short name T2795
Test name
Test status
Simulation time 141248472 ps
CPU time 1.61 seconds
Started Jul 14 07:03:59 PM PDT 24
Finished Jul 14 07:04:01 PM PDT 24
Peak memory 214816 kb
Host smart-fd558f36-02ff-4f38-a4b7-8a0d4317d1a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426544975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1426544975
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.385131358
Short name T2846
Test name
Test status
Simulation time 88874410 ps
CPU time 1.03 seconds
Started Jul 14 07:04:01 PM PDT 24
Finished Jul 14 07:04:02 PM PDT 24
Peak memory 206584 kb
Host smart-0a60681d-6848-4eb2-8519-02562ff8682a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=385131358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.385131358
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2092207047
Short name T276
Test name
Test status
Simulation time 32027769 ps
CPU time 0.68 seconds
Started Jul 14 07:03:59 PM PDT 24
Finished Jul 14 07:04:00 PM PDT 24
Peak memory 206392 kb
Host smart-95b9dcc8-61ae-4a48-a313-4e02d118e6c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2092207047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2092207047
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1096335288
Short name T2838
Test name
Test status
Simulation time 213203198 ps
CPU time 1.61 seconds
Started Jul 14 07:04:00 PM PDT 24
Finished Jul 14 07:04:02 PM PDT 24
Peak memory 206576 kb
Host smart-f5c6dc7b-4f68-4426-9787-3b983cdca71c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1096335288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1096335288
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2149599778
Short name T2753
Test name
Test status
Simulation time 129324319 ps
CPU time 3.14 seconds
Started Jul 14 07:04:00 PM PDT 24
Finished Jul 14 07:04:04 PM PDT 24
Peak memory 222256 kb
Host smart-56a4abfd-7b34-4fd9-9e29-9487ad25d2be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2149599778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2149599778
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.590724199
Short name T220
Test name
Test status
Simulation time 448187795 ps
CPU time 2.67 seconds
Started Jul 14 07:04:03 PM PDT 24
Finished Jul 14 07:04:06 PM PDT 24
Peak memory 206560 kb
Host smart-a53acf2e-e93e-49a5-bcac-df9bcb9d4803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=590724199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.590724199
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2447510118
Short name T2834
Test name
Test status
Simulation time 107847041 ps
CPU time 1.23 seconds
Started Jul 14 07:04:05 PM PDT 24
Finished Jul 14 07:04:07 PM PDT 24
Peak memory 223032 kb
Host smart-1b38ba42-a5e7-482e-9fb2-1647bbda1e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447510118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2447510118
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3394090182
Short name T2806
Test name
Test status
Simulation time 55507913 ps
CPU time 0.82 seconds
Started Jul 14 07:04:07 PM PDT 24
Finished Jul 14 07:04:08 PM PDT 24
Peak memory 206428 kb
Host smart-3d0d2d39-f061-4853-9578-522ca4ddcfd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3394090182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3394090182
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1195327663
Short name T2832
Test name
Test status
Simulation time 41693424 ps
CPU time 0.66 seconds
Started Jul 14 07:04:06 PM PDT 24
Finished Jul 14 07:04:07 PM PDT 24
Peak memory 206400 kb
Host smart-77358839-5089-4142-a58b-b92a5069df38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1195327663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1195327663
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3488744298
Short name T2802
Test name
Test status
Simulation time 91836757 ps
CPU time 1.08 seconds
Started Jul 14 07:04:07 PM PDT 24
Finished Jul 14 07:04:08 PM PDT 24
Peak memory 206636 kb
Host smart-3186072e-36c4-438d-bf33-d2996f928d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3488744298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3488744298
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2751156041
Short name T293
Test name
Test status
Simulation time 459256871 ps
CPU time 4.11 seconds
Started Jul 14 07:04:06 PM PDT 24
Finished Jul 14 07:04:10 PM PDT 24
Peak memory 206616 kb
Host smart-b35fda77-1005-4305-aff0-69df3fc89867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2751156041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2751156041
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1641359634
Short name T2816
Test name
Test status
Simulation time 119112305 ps
CPU time 1.33 seconds
Started Jul 14 07:04:05 PM PDT 24
Finished Jul 14 07:04:07 PM PDT 24
Peak memory 214832 kb
Host smart-40d85d50-aebd-4926-9407-8cab2535c081
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641359634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1641359634
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1126421271
Short name T2848
Test name
Test status
Simulation time 97114873 ps
CPU time 1.16 seconds
Started Jul 14 07:04:08 PM PDT 24
Finished Jul 14 07:04:10 PM PDT 24
Peak memory 206552 kb
Host smart-5c90c172-5ec6-4081-904b-f5eeea0db1a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1126421271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1126421271
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2180292718
Short name T286
Test name
Test status
Simulation time 56543016 ps
CPU time 0.68 seconds
Started Jul 14 07:04:07 PM PDT 24
Finished Jul 14 07:04:08 PM PDT 24
Peak memory 206416 kb
Host smart-f4918261-805b-4390-afed-2d3c6779bef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2180292718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2180292718
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3283456958
Short name T2812
Test name
Test status
Simulation time 78598809 ps
CPU time 1.06 seconds
Started Jul 14 07:04:07 PM PDT 24
Finished Jul 14 07:04:09 PM PDT 24
Peak memory 206524 kb
Host smart-abb73f4a-e3ad-47be-aa4e-9527e2865988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3283456958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3283456958
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2088746600
Short name T2764
Test name
Test status
Simulation time 279297962 ps
CPU time 3.15 seconds
Started Jul 14 07:04:07 PM PDT 24
Finished Jul 14 07:04:11 PM PDT 24
Peak memory 206676 kb
Host smart-01d3a2ba-a717-45ce-9727-cc6b722b7d17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2088746600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2088746600
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4266023692
Short name T2788
Test name
Test status
Simulation time 305609114 ps
CPU time 2.46 seconds
Started Jul 14 07:04:06 PM PDT 24
Finished Jul 14 07:04:09 PM PDT 24
Peak memory 206560 kb
Host smart-eac11b14-1690-4925-a8ee-41d71ded4ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4266023692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.4266023692
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4288825260
Short name T234
Test name
Test status
Simulation time 158017431 ps
CPU time 1.87 seconds
Started Jul 14 07:04:12 PM PDT 24
Finished Jul 14 07:04:15 PM PDT 24
Peak memory 214852 kb
Host smart-824c07da-6bc2-4ed3-8166-661951d92c8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288825260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.4288825260
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1003268751
Short name T263
Test name
Test status
Simulation time 71748975 ps
CPU time 0.79 seconds
Started Jul 14 07:04:13 PM PDT 24
Finished Jul 14 07:04:14 PM PDT 24
Peak memory 206348 kb
Host smart-d0a4ec89-300c-44b3-98be-50049b370f10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1003268751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1003268751
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3425813409
Short name T2803
Test name
Test status
Simulation time 45340313 ps
CPU time 0.69 seconds
Started Jul 14 07:04:13 PM PDT 24
Finished Jul 14 07:04:14 PM PDT 24
Peak memory 206356 kb
Host smart-3f8bad12-3a4e-402e-b1e0-b0748b3e8581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3425813409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3425813409
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3188322955
Short name T199
Test name
Test status
Simulation time 182284250 ps
CPU time 1.59 seconds
Started Jul 14 07:04:15 PM PDT 24
Finished Jul 14 07:04:17 PM PDT 24
Peak memory 206524 kb
Host smart-d47dbf21-d768-4456-accf-2271ddc1f1cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3188322955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3188322955
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3509475313
Short name T215
Test name
Test status
Simulation time 233530205 ps
CPU time 2.39 seconds
Started Jul 14 07:04:04 PM PDT 24
Finished Jul 14 07:04:07 PM PDT 24
Peak memory 222336 kb
Host smart-b8fd7397-4c25-487d-a52f-607d80525f73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3509475313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3509475313
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4255853829
Short name T2822
Test name
Test status
Simulation time 804975802 ps
CPU time 4.98 seconds
Started Jul 14 07:04:06 PM PDT 24
Finished Jul 14 07:04:12 PM PDT 24
Peak memory 206560 kb
Host smart-7a11e148-8ec6-46f9-88e2-994d76f5290a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4255853829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4255853829
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4017966243
Short name T2750
Test name
Test status
Simulation time 118678415 ps
CPU time 1.41 seconds
Started Jul 14 07:04:13 PM PDT 24
Finished Jul 14 07:04:14 PM PDT 24
Peak memory 214856 kb
Host smart-1d38519f-40a0-48b5-96c4-e4a68d17d70a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017966243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.4017966243
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1735689750
Short name T2821
Test name
Test status
Simulation time 75249631 ps
CPU time 0.86 seconds
Started Jul 14 07:04:15 PM PDT 24
Finished Jul 14 07:04:16 PM PDT 24
Peak memory 206372 kb
Host smart-869e703c-5bb7-4956-a777-3c3d9028ed5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1735689750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1735689750
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.4230823963
Short name T207
Test name
Test status
Simulation time 81281510 ps
CPU time 0.69 seconds
Started Jul 14 07:04:14 PM PDT 24
Finished Jul 14 07:04:15 PM PDT 24
Peak memory 206396 kb
Host smart-d8b5d5f8-5263-405d-89c3-b8fb5144a1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4230823963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.4230823963
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.660050439
Short name T2756
Test name
Test status
Simulation time 238501386 ps
CPU time 1.79 seconds
Started Jul 14 07:04:15 PM PDT 24
Finished Jul 14 07:04:17 PM PDT 24
Peak memory 206604 kb
Host smart-63bee4b0-706f-4f11-861a-022bf66d46fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=660050439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.660050439
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3809173994
Short name T2796
Test name
Test status
Simulation time 269406061 ps
CPU time 2.83 seconds
Started Jul 14 07:04:14 PM PDT 24
Finished Jul 14 07:04:17 PM PDT 24
Peak memory 206700 kb
Host smart-e30ce4fe-7623-447b-b1f0-543c44ba63fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3809173994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3809173994
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1914284970
Short name T291
Test name
Test status
Simulation time 372762716 ps
CPU time 2.57 seconds
Started Jul 14 07:04:15 PM PDT 24
Finished Jul 14 07:04:18 PM PDT 24
Peak memory 206532 kb
Host smart-dffd1d3b-dbaf-4f38-8d34-c1172fbf6502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1914284970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1914284970
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.177458269
Short name T2786
Test name
Test status
Simulation time 123728390 ps
CPU time 2.07 seconds
Started Jul 14 07:04:23 PM PDT 24
Finished Jul 14 07:04:26 PM PDT 24
Peak memory 214792 kb
Host smart-c013a2f5-cc15-4062-8e1f-47a5374e9884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177458269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.177458269
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.121984804
Short name T255
Test name
Test status
Simulation time 66160686 ps
CPU time 0.82 seconds
Started Jul 14 07:04:22 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 206340 kb
Host smart-205d7f6c-ab8d-4da2-9adb-7a99e36babed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=121984804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.121984804
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3226897379
Short name T2811
Test name
Test status
Simulation time 37284349 ps
CPU time 0.65 seconds
Started Jul 14 07:04:23 PM PDT 24
Finished Jul 14 07:04:25 PM PDT 24
Peak memory 206376 kb
Host smart-24f67d6d-bcd0-46ac-8a05-c48e16d8d6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3226897379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3226897379
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.552158429
Short name T2776
Test name
Test status
Simulation time 174223149 ps
CPU time 1.68 seconds
Started Jul 14 07:04:20 PM PDT 24
Finished Jul 14 07:04:22 PM PDT 24
Peak memory 206572 kb
Host smart-54b7d340-9bac-4623-900f-5bdcf8268e79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=552158429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.552158429
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4227197870
Short name T2749
Test name
Test status
Simulation time 160078403 ps
CPU time 1.69 seconds
Started Jul 14 07:04:22 PM PDT 24
Finished Jul 14 07:04:24 PM PDT 24
Peak memory 214820 kb
Host smart-76f30a69-ad44-46b7-a733-056f2e119954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4227197870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4227197870
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.122534302
Short name T2825
Test name
Test status
Simulation time 153160193 ps
CPU time 1.77 seconds
Started Jul 14 07:04:22 PM PDT 24
Finished Jul 14 07:04:25 PM PDT 24
Peak memory 214880 kb
Host smart-dc5892f0-4700-4ca2-939e-e3be1bbe1071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122534302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.122534302
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2454030833
Short name T259
Test name
Test status
Simulation time 90309125 ps
CPU time 0.94 seconds
Started Jul 14 07:04:19 PM PDT 24
Finished Jul 14 07:04:20 PM PDT 24
Peak memory 206572 kb
Host smart-37b5d7f6-73f8-4aa3-aca5-3b41b79952c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2454030833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2454030833
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3841382489
Short name T2745
Test name
Test status
Simulation time 112835331 ps
CPU time 1.53 seconds
Started Jul 14 07:04:20 PM PDT 24
Finished Jul 14 07:04:22 PM PDT 24
Peak memory 206528 kb
Host smart-c3c6209b-dd11-4b39-bd3c-8fc147f7cc79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3841382489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3841382489
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3325557412
Short name T227
Test name
Test status
Simulation time 202756728 ps
CPU time 2.7 seconds
Started Jul 14 07:04:20 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 222816 kb
Host smart-de9b8833-55f2-4b9e-a48b-0c6d17b9c572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3325557412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3325557412
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.882135328
Short name T2800
Test name
Test status
Simulation time 395551097 ps
CPU time 2.53 seconds
Started Jul 14 07:04:22 PM PDT 24
Finished Jul 14 07:04:26 PM PDT 24
Peak memory 206592 kb
Host smart-4d09fed0-2151-40ea-98e6-4b82556514a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=882135328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.882135328
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2881703970
Short name T2827
Test name
Test status
Simulation time 188647832 ps
CPU time 2.35 seconds
Started Jul 14 07:04:22 PM PDT 24
Finished Jul 14 07:04:25 PM PDT 24
Peak memory 214784 kb
Host smart-c01e522e-597b-426d-ab9c-30fd52c12b02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881703970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2881703970
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2709217967
Short name T2841
Test name
Test status
Simulation time 68988983 ps
CPU time 0.83 seconds
Started Jul 14 07:04:20 PM PDT 24
Finished Jul 14 07:04:22 PM PDT 24
Peak memory 206376 kb
Host smart-e06e880f-a5e6-461a-af67-5514664bdca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2709217967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2709217967
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3860093069
Short name T265
Test name
Test status
Simulation time 523578058 ps
CPU time 1.83 seconds
Started Jul 14 07:04:22 PM PDT 24
Finished Jul 14 07:04:24 PM PDT 24
Peak memory 206596 kb
Host smart-a8dd636c-fb38-479b-9d28-997a968a5bc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3860093069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3860093069
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.373486539
Short name T2769
Test name
Test status
Simulation time 380147920 ps
CPU time 3.25 seconds
Started Jul 14 07:04:24 PM PDT 24
Finished Jul 14 07:04:28 PM PDT 24
Peak memory 215032 kb
Host smart-43c79000-aed2-4766-b0ea-00dece78e26d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=373486539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.373486539
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3638980734
Short name T294
Test name
Test status
Simulation time 1316809066 ps
CPU time 3.54 seconds
Started Jul 14 07:04:20 PM PDT 24
Finished Jul 14 07:04:25 PM PDT 24
Peak memory 206536 kb
Host smart-79cd4afc-5c5c-4896-a5ff-853cf8dfaad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3638980734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3638980734
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2944844871
Short name T197
Test name
Test status
Simulation time 169879296 ps
CPU time 1.61 seconds
Started Jul 14 07:04:26 PM PDT 24
Finished Jul 14 07:04:28 PM PDT 24
Peak memory 214788 kb
Host smart-d335aefa-c452-4547-89a5-4726f8b1d42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944844871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2944844871
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3561398865
Short name T2775
Test name
Test status
Simulation time 89664573 ps
CPU time 0.99 seconds
Started Jul 14 07:04:21 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 206480 kb
Host smart-5b585f24-fe67-48d2-bcc4-f8c6c86c36bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3561398865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3561398865
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2249153940
Short name T2784
Test name
Test status
Simulation time 44206667 ps
CPU time 0.64 seconds
Started Jul 14 07:04:21 PM PDT 24
Finished Jul 14 07:04:22 PM PDT 24
Peak memory 206372 kb
Host smart-3383fa0d-168c-4ead-8fe2-7ac702340f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2249153940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2249153940
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3837777962
Short name T2819
Test name
Test status
Simulation time 191064134 ps
CPU time 1.5 seconds
Started Jul 14 07:04:25 PM PDT 24
Finished Jul 14 07:04:27 PM PDT 24
Peak memory 206572 kb
Host smart-9c9c46bb-03ab-4bd1-9de1-a5f2192e216b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3837777962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3837777962
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2754096636
Short name T292
Test name
Test status
Simulation time 522994138 ps
CPU time 2.89 seconds
Started Jul 14 07:04:21 PM PDT 24
Finished Jul 14 07:04:24 PM PDT 24
Peak memory 206544 kb
Host smart-241355dc-193e-462e-b389-528c521d674f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2754096636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2754096636
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.109701751
Short name T2768
Test name
Test status
Simulation time 188326660 ps
CPU time 1.8 seconds
Started Jul 14 07:04:28 PM PDT 24
Finished Jul 14 07:04:31 PM PDT 24
Peak memory 214808 kb
Host smart-c9d124b5-2e1d-4afd-9139-fd7e8a40f219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109701751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.109701751
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3181597466
Short name T2835
Test name
Test status
Simulation time 44447373 ps
CPU time 0.7 seconds
Started Jul 14 07:04:26 PM PDT 24
Finished Jul 14 07:04:28 PM PDT 24
Peak memory 206508 kb
Host smart-b66c5833-9863-45f7-b1ea-480fd69cfdd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3181597466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3181597466
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2459924790
Short name T266
Test name
Test status
Simulation time 166827497 ps
CPU time 1.17 seconds
Started Jul 14 07:04:25 PM PDT 24
Finished Jul 14 07:04:27 PM PDT 24
Peak memory 206572 kb
Host smart-056030bb-e1bd-48a8-8749-38bd1d164c3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2459924790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2459924790
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3777342213
Short name T2792
Test name
Test status
Simulation time 126113296 ps
CPU time 1.42 seconds
Started Jul 14 07:04:27 PM PDT 24
Finished Jul 14 07:04:29 PM PDT 24
Peak memory 206588 kb
Host smart-bd8be2e4-c194-4901-bbdc-0063558daa50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3777342213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3777342213
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.601129667
Short name T2748
Test name
Test status
Simulation time 1045336825 ps
CPU time 5.35 seconds
Started Jul 14 07:04:29 PM PDT 24
Finished Jul 14 07:04:35 PM PDT 24
Peak memory 206528 kb
Host smart-23154dd0-51ac-4e4a-90de-e2e56954a6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=601129667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.601129667
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4081647607
Short name T2840
Test name
Test status
Simulation time 138293776 ps
CPU time 3.27 seconds
Started Jul 14 07:03:38 PM PDT 24
Finished Jul 14 07:03:42 PM PDT 24
Peak memory 206620 kb
Host smart-1ecf01d6-7c7f-4040-993c-89f87574c5d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4081647607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.4081647607
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2609653074
Short name T257
Test name
Test status
Simulation time 1350075505 ps
CPU time 8.39 seconds
Started Jul 14 07:03:37 PM PDT 24
Finished Jul 14 07:03:45 PM PDT 24
Peak memory 206480 kb
Host smart-04cf96b1-68b4-4a2f-8dd4-c3f6085f79f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2609653074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2609653074
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3848662134
Short name T2744
Test name
Test status
Simulation time 172635458 ps
CPU time 1.07 seconds
Started Jul 14 07:03:39 PM PDT 24
Finished Jul 14 07:03:41 PM PDT 24
Peak memory 206348 kb
Host smart-d144ac8b-5c2a-4445-a3c7-2ef2d0550d3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3848662134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3848662134
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.446057599
Short name T2824
Test name
Test status
Simulation time 167687269 ps
CPU time 1.7 seconds
Started Jul 14 07:03:39 PM PDT 24
Finished Jul 14 07:03:41 PM PDT 24
Peak memory 214796 kb
Host smart-66c472ea-6224-4045-9df1-53568921b7f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446057599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.446057599
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1747445214
Short name T2828
Test name
Test status
Simulation time 39823221 ps
CPU time 0.79 seconds
Started Jul 14 07:03:42 PM PDT 24
Finished Jul 14 07:03:44 PM PDT 24
Peak memory 206408 kb
Host smart-98a53989-ba81-4bcb-b00e-f53a3d15b9ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1747445214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1747445214
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3377395716
Short name T249
Test name
Test status
Simulation time 102982274 ps
CPU time 1.47 seconds
Started Jul 14 07:03:31 PM PDT 24
Finished Jul 14 07:03:33 PM PDT 24
Peak memory 215972 kb
Host smart-4b0014cd-9e52-4a85-8a7a-5194652448d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3377395716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3377395716
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.527298202
Short name T2747
Test name
Test status
Simulation time 101201209 ps
CPU time 2.29 seconds
Started Jul 14 07:03:30 PM PDT 24
Finished Jul 14 07:03:32 PM PDT 24
Peak memory 206460 kb
Host smart-34ea3744-fb92-4ba4-a749-c9047ab73628
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=527298202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.527298202
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2859551695
Short name T261
Test name
Test status
Simulation time 257789541 ps
CPU time 1.74 seconds
Started Jul 14 07:03:38 PM PDT 24
Finished Jul 14 07:03:40 PM PDT 24
Peak memory 206588 kb
Host smart-2d1d01ff-386d-4157-9979-cca36bc53be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2859551695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2859551695
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4157815999
Short name T2794
Test name
Test status
Simulation time 67459680 ps
CPU time 1.42 seconds
Started Jul 14 07:03:32 PM PDT 24
Finished Jul 14 07:03:34 PM PDT 24
Peak memory 222288 kb
Host smart-249beabb-b9bc-4efa-bdae-e80a08423c44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4157815999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4157815999
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3979108270
Short name T296
Test name
Test status
Simulation time 974670387 ps
CPU time 5.3 seconds
Started Jul 14 07:03:32 PM PDT 24
Finished Jul 14 07:03:38 PM PDT 24
Peak memory 206568 kb
Host smart-4a1d30f9-4656-4f70-b1db-27a549817420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3979108270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3979108270
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3236199215
Short name T2843
Test name
Test status
Simulation time 44368853 ps
CPU time 0.67 seconds
Started Jul 14 07:04:28 PM PDT 24
Finished Jul 14 07:04:29 PM PDT 24
Peak memory 206420 kb
Host smart-bb9e5999-9a35-473a-a778-9cfbcc083668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3236199215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3236199215
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3049023624
Short name T2801
Test name
Test status
Simulation time 71492504 ps
CPU time 0.72 seconds
Started Jul 14 07:04:28 PM PDT 24
Finished Jul 14 07:04:30 PM PDT 24
Peak memory 206364 kb
Host smart-761e89de-dd73-4cff-a6af-5252e755dce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3049023624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3049023624
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.786002176
Short name T2772
Test name
Test status
Simulation time 137757118 ps
CPU time 0.74 seconds
Started Jul 14 07:04:25 PM PDT 24
Finished Jul 14 07:04:26 PM PDT 24
Peak memory 206384 kb
Host smart-fe9bc3e0-ef31-4493-9165-0c88be802d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=786002176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.786002176
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2730237673
Short name T2779
Test name
Test status
Simulation time 36179303 ps
CPU time 0.66 seconds
Started Jul 14 07:04:28 PM PDT 24
Finished Jul 14 07:04:29 PM PDT 24
Peak memory 206344 kb
Host smart-f86289f4-b369-4f29-8f5d-b6600084facd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2730237673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2730237673
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4142938063
Short name T281
Test name
Test status
Simulation time 34951460 ps
CPU time 0.65 seconds
Started Jul 14 07:04:29 PM PDT 24
Finished Jul 14 07:04:31 PM PDT 24
Peak memory 206356 kb
Host smart-8cc0125d-450f-4b5f-835c-ba02faf9b7e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4142938063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4142938063
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2601561615
Short name T275
Test name
Test status
Simulation time 58815520 ps
CPU time 0.73 seconds
Started Jul 14 07:04:31 PM PDT 24
Finished Jul 14 07:04:32 PM PDT 24
Peak memory 206424 kb
Host smart-3186cda8-6489-4700-a70c-3814989ede96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2601561615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2601561615
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.717750466
Short name T285
Test name
Test status
Simulation time 50822325 ps
CPU time 0.66 seconds
Started Jul 14 07:04:26 PM PDT 24
Finished Jul 14 07:04:28 PM PDT 24
Peak memory 206372 kb
Host smart-eaba6a85-1ede-41c9-87b8-25965c1a53ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=717750466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.717750466
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.678741264
Short name T250
Test name
Test status
Simulation time 372412073 ps
CPU time 3.63 seconds
Started Jul 14 07:03:43 PM PDT 24
Finished Jul 14 07:03:48 PM PDT 24
Peak memory 206516 kb
Host smart-b008f3a4-9544-4cb0-903f-611ce3022f38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=678741264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.678741264
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1494571031
Short name T2818
Test name
Test status
Simulation time 608953688 ps
CPU time 5.14 seconds
Started Jul 14 07:03:38 PM PDT 24
Finished Jul 14 07:03:44 PM PDT 24
Peak memory 206484 kb
Host smart-ca029cb3-cb52-409c-b26e-8d68baf2289d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1494571031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1494571031
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1888097572
Short name T2771
Test name
Test status
Simulation time 62027449 ps
CPU time 0.85 seconds
Started Jul 14 07:03:43 PM PDT 24
Finished Jul 14 07:03:45 PM PDT 24
Peak memory 206376 kb
Host smart-b0ba9195-9632-487a-a182-f281416c75b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1888097572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1888097572
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.192862483
Short name T221
Test name
Test status
Simulation time 167963412 ps
CPU time 1.26 seconds
Started Jul 14 07:03:44 PM PDT 24
Finished Jul 14 07:03:46 PM PDT 24
Peak memory 214836 kb
Host smart-4f831ec1-8fa2-4ee5-8f6f-823ac876c02b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192862483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.192862483
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2661912159
Short name T2765
Test name
Test status
Simulation time 68356162 ps
CPU time 1.04 seconds
Started Jul 14 07:03:38 PM PDT 24
Finished Jul 14 07:03:40 PM PDT 24
Peak memory 206568 kb
Host smart-7ec168c1-39c6-47ed-816d-c2d2137efb6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2661912159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2661912159
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1273773894
Short name T2831
Test name
Test status
Simulation time 28106606 ps
CPU time 0.62 seconds
Started Jul 14 07:03:43 PM PDT 24
Finished Jul 14 07:03:45 PM PDT 24
Peak memory 206404 kb
Host smart-77eceb0f-0394-4a1e-88a3-17d7a1b49df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1273773894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1273773894
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1118943387
Short name T2793
Test name
Test status
Simulation time 203047813 ps
CPU time 2.36 seconds
Started Jul 14 07:03:38 PM PDT 24
Finished Jul 14 07:03:41 PM PDT 24
Peak memory 214856 kb
Host smart-91d87d12-2ec3-41e0-9d19-64b8a9c9d643
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1118943387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1118943387
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.716240990
Short name T2783
Test name
Test status
Simulation time 788245545 ps
CPU time 4.65 seconds
Started Jul 14 07:03:44 PM PDT 24
Finished Jul 14 07:03:49 PM PDT 24
Peak memory 206460 kb
Host smart-e1768adf-4cf6-4d97-a94a-c6bd0e7df637
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=716240990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.716240990
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3228490414
Short name T2746
Test name
Test status
Simulation time 100194966 ps
CPU time 1.01 seconds
Started Jul 14 07:03:44 PM PDT 24
Finished Jul 14 07:03:46 PM PDT 24
Peak memory 206620 kb
Host smart-040ac387-0baf-462d-82cb-190fd1f7b050
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3228490414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3228490414
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1283482906
Short name T2762
Test name
Test status
Simulation time 295148091 ps
CPU time 3.03 seconds
Started Jul 14 07:03:37 PM PDT 24
Finished Jul 14 07:03:41 PM PDT 24
Peak memory 206600 kb
Host smart-21a80f63-5b76-4a29-8386-1e912dfc97a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1283482906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1283482906
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2015018044
Short name T232
Test name
Test status
Simulation time 717070941 ps
CPU time 2.69 seconds
Started Jul 14 07:03:38 PM PDT 24
Finished Jul 14 07:03:41 PM PDT 24
Peak memory 206552 kb
Host smart-a16b8a97-20cb-4705-84f1-1a77a7c34949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2015018044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2015018044
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2637493411
Short name T206
Test name
Test status
Simulation time 39850141 ps
CPU time 0.66 seconds
Started Jul 14 07:04:28 PM PDT 24
Finished Jul 14 07:04:29 PM PDT 24
Peak memory 206400 kb
Host smart-10097149-7429-46b1-b03d-26138896c7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2637493411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2637493411
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.101355426
Short name T204
Test name
Test status
Simulation time 62877572 ps
CPU time 0.66 seconds
Started Jul 14 07:04:29 PM PDT 24
Finished Jul 14 07:04:30 PM PDT 24
Peak memory 206248 kb
Host smart-49168540-49cf-4035-9db1-88a46fedd5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=101355426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.101355426
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2286902718
Short name T2785
Test name
Test status
Simulation time 73020427 ps
CPU time 0.69 seconds
Started Jul 14 07:04:26 PM PDT 24
Finished Jul 14 07:04:27 PM PDT 24
Peak memory 206424 kb
Host smart-5829542e-12bc-4d91-96af-f2f820ee4b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2286902718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2286902718
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3825344708
Short name T274
Test name
Test status
Simulation time 43516671 ps
CPU time 0.68 seconds
Started Jul 14 07:04:27 PM PDT 24
Finished Jul 14 07:04:29 PM PDT 24
Peak memory 206376 kb
Host smart-e7327d54-4207-41f1-85e3-0186f9394d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3825344708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3825344708
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2688366294
Short name T2807
Test name
Test status
Simulation time 38211561 ps
CPU time 0.64 seconds
Started Jul 14 07:04:24 PM PDT 24
Finished Jul 14 07:04:25 PM PDT 24
Peak memory 206328 kb
Host smart-84788157-be7e-4448-a91a-5bc60ea9d8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2688366294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2688366294
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1807588879
Short name T2766
Test name
Test status
Simulation time 111180577 ps
CPU time 0.71 seconds
Started Jul 14 07:04:27 PM PDT 24
Finished Jul 14 07:04:29 PM PDT 24
Peak memory 206356 kb
Host smart-4dcddcdf-81ee-45fc-87ac-fd8d460ff4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1807588879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1807588879
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2295295896
Short name T287
Test name
Test status
Simulation time 29995994 ps
CPU time 0.66 seconds
Started Jul 14 07:04:31 PM PDT 24
Finished Jul 14 07:04:33 PM PDT 24
Peak memory 206352 kb
Host smart-47462fae-5c3f-4ee1-be5f-cdd0d35ee6e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2295295896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2295295896
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4090249963
Short name T283
Test name
Test status
Simulation time 39930025 ps
CPU time 0.71 seconds
Started Jul 14 07:04:29 PM PDT 24
Finished Jul 14 07:04:31 PM PDT 24
Peak memory 206352 kb
Host smart-59892b31-b807-433f-9907-e37051273c45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4090249963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4090249963
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3322912838
Short name T2850
Test name
Test status
Simulation time 65122709 ps
CPU time 0.69 seconds
Started Jul 14 07:04:28 PM PDT 24
Finished Jul 14 07:04:30 PM PDT 24
Peak memory 206256 kb
Host smart-808121e1-2d9c-49c2-9098-ed72d5c58c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3322912838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3322912838
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2103921007
Short name T2851
Test name
Test status
Simulation time 168617912 ps
CPU time 3.08 seconds
Started Jul 14 07:03:43 PM PDT 24
Finished Jul 14 07:03:47 PM PDT 24
Peak memory 206436 kb
Host smart-d515cc55-8726-4874-854a-79ba95f98e81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2103921007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2103921007
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.891611611
Short name T2815
Test name
Test status
Simulation time 886363565 ps
CPU time 9.12 seconds
Started Jul 14 07:03:45 PM PDT 24
Finished Jul 14 07:03:55 PM PDT 24
Peak memory 206512 kb
Host smart-1d580f07-a179-4024-a047-69aa3cba3709
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=891611611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.891611611
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2612213290
Short name T2808
Test name
Test status
Simulation time 106110511 ps
CPU time 0.93 seconds
Started Jul 14 07:03:44 PM PDT 24
Finished Jul 14 07:03:46 PM PDT 24
Peak memory 206380 kb
Host smart-5f9d9a3e-5e94-46f9-ade5-e60b6b05f559
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2612213290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2612213290
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1890128933
Short name T2823
Test name
Test status
Simulation time 163416278 ps
CPU time 1.89 seconds
Started Jul 14 07:03:50 PM PDT 24
Finished Jul 14 07:03:52 PM PDT 24
Peak memory 214876 kb
Host smart-16aa729a-7050-427f-8098-0e14f0498b30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890128933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1890128933
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1788367250
Short name T2829
Test name
Test status
Simulation time 128621196 ps
CPU time 1.14 seconds
Started Jul 14 07:03:45 PM PDT 24
Finished Jul 14 07:03:47 PM PDT 24
Peak memory 206488 kb
Host smart-60fde956-1914-4f22-b69d-5158f19920bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1788367250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1788367250
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3165878463
Short name T2761
Test name
Test status
Simulation time 63646629 ps
CPU time 0.69 seconds
Started Jul 14 07:03:45 PM PDT 24
Finished Jul 14 07:03:46 PM PDT 24
Peak memory 206340 kb
Host smart-82b66d13-1880-4865-a18c-8f3b02afaa80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3165878463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3165878463
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1927737115
Short name T258
Test name
Test status
Simulation time 176076358 ps
CPU time 2.3 seconds
Started Jul 14 07:03:45 PM PDT 24
Finished Jul 14 07:03:48 PM PDT 24
Peak memory 214900 kb
Host smart-fb0bfadc-3810-425a-927c-e5a6f4832e53
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1927737115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1927737115
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.865640176
Short name T2757
Test name
Test status
Simulation time 172955924 ps
CPU time 3.91 seconds
Started Jul 14 07:03:48 PM PDT 24
Finished Jul 14 07:03:52 PM PDT 24
Peak memory 206516 kb
Host smart-43e36df4-254e-488c-bf78-48dcb31f609e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=865640176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.865640176
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.827615985
Short name T264
Test name
Test status
Simulation time 196517947 ps
CPU time 1.44 seconds
Started Jul 14 07:03:47 PM PDT 24
Finished Jul 14 07:03:49 PM PDT 24
Peak memory 206624 kb
Host smart-b7c937b3-5501-4b0f-a2bc-37da9bddf6cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=827615985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.827615985
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2601725546
Short name T2760
Test name
Test status
Simulation time 291657304 ps
CPU time 3.08 seconds
Started Jul 14 07:03:45 PM PDT 24
Finished Jul 14 07:03:49 PM PDT 24
Peak memory 222452 kb
Host smart-6ac6d6ef-6a13-4be9-a491-ca81226b1ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2601725546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2601725546
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2418156392
Short name T289
Test name
Test status
Simulation time 808190677 ps
CPU time 4.56 seconds
Started Jul 14 07:03:45 PM PDT 24
Finished Jul 14 07:03:50 PM PDT 24
Peak memory 206568 kb
Host smart-ea200ee8-e90b-43a2-8847-577cf537a621
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2418156392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2418156392
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4187441253
Short name T2790
Test name
Test status
Simulation time 37792436 ps
CPU time 0.63 seconds
Started Jul 14 07:04:26 PM PDT 24
Finished Jul 14 07:04:27 PM PDT 24
Peak memory 206372 kb
Host smart-d26b8bcc-5155-49b8-803f-6b1f3ce9bae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4187441253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.4187441253
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3335156857
Short name T2780
Test name
Test status
Simulation time 36403715 ps
CPU time 0.65 seconds
Started Jul 14 07:04:32 PM PDT 24
Finished Jul 14 07:04:34 PM PDT 24
Peak memory 206328 kb
Host smart-9cbb5fdc-e6a9-4981-ba7a-5dca8e0f2fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3335156857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3335156857
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1923549634
Short name T2830
Test name
Test status
Simulation time 81974687 ps
CPU time 0.71 seconds
Started Jul 14 07:04:35 PM PDT 24
Finished Jul 14 07:04:36 PM PDT 24
Peak memory 206352 kb
Host smart-d3f48725-2947-49c7-8030-ba32c02134c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1923549634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1923549634
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.134239808
Short name T2777
Test name
Test status
Simulation time 100232366 ps
CPU time 0.7 seconds
Started Jul 14 07:04:32 PM PDT 24
Finished Jul 14 07:04:34 PM PDT 24
Peak memory 206408 kb
Host smart-78adff57-d8b7-4513-8eca-9fdb6e5acf86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=134239808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.134239808
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2140176684
Short name T203
Test name
Test status
Simulation time 41032641 ps
CPU time 0.66 seconds
Started Jul 14 07:04:31 PM PDT 24
Finished Jul 14 07:04:32 PM PDT 24
Peak memory 206376 kb
Host smart-9091864b-3fdf-456f-8ae6-053f326c685f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2140176684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2140176684
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2306382957
Short name T282
Test name
Test status
Simulation time 78856592 ps
CPU time 0.69 seconds
Started Jul 14 07:04:31 PM PDT 24
Finished Jul 14 07:04:32 PM PDT 24
Peak memory 206384 kb
Host smart-8ab87ba7-edc9-4a05-86de-d16c343681ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2306382957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2306382957
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4278479317
Short name T2770
Test name
Test status
Simulation time 113321417 ps
CPU time 0.78 seconds
Started Jul 14 07:04:32 PM PDT 24
Finished Jul 14 07:04:34 PM PDT 24
Peak memory 206384 kb
Host smart-14209571-2e6d-494a-9292-915494946b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4278479317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4278479317
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1067643302
Short name T2813
Test name
Test status
Simulation time 63354004 ps
CPU time 0.68 seconds
Started Jul 14 07:04:34 PM PDT 24
Finished Jul 14 07:04:35 PM PDT 24
Peak memory 206344 kb
Host smart-bc622338-c7d9-40a9-b3ac-d922528e0dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1067643302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1067643302
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1720365735
Short name T2814
Test name
Test status
Simulation time 36358258 ps
CPU time 0.67 seconds
Started Jul 14 07:04:32 PM PDT 24
Finished Jul 14 07:04:33 PM PDT 24
Peak memory 206352 kb
Host smart-5806135a-a769-4d70-9a06-b6abd9b10335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1720365735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1720365735
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3203508772
Short name T2809
Test name
Test status
Simulation time 39173184 ps
CPU time 0.66 seconds
Started Jul 14 07:04:31 PM PDT 24
Finished Jul 14 07:04:32 PM PDT 24
Peak memory 206392 kb
Host smart-3cd72e86-731a-49a7-aa67-4c54b2f9b678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3203508772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3203508772
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1502437589
Short name T2787
Test name
Test status
Simulation time 97453136 ps
CPU time 1.29 seconds
Started Jul 14 07:03:49 PM PDT 24
Finished Jul 14 07:03:51 PM PDT 24
Peak memory 214860 kb
Host smart-9301a2fb-aa8e-4807-972a-e707fb7e4e06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502437589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1502437589
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2613606969
Short name T256
Test name
Test status
Simulation time 54545559 ps
CPU time 0.8 seconds
Started Jul 14 07:03:51 PM PDT 24
Finished Jul 14 07:03:52 PM PDT 24
Peak memory 206232 kb
Host smart-68815699-6213-4592-aa9a-10fee4996578
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2613606969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2613606969
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.4272886570
Short name T2774
Test name
Test status
Simulation time 51174128 ps
CPU time 0.65 seconds
Started Jul 14 07:03:49 PM PDT 24
Finished Jul 14 07:03:50 PM PDT 24
Peak memory 206344 kb
Host smart-5ce19a52-ac94-4574-8ee9-8ab18827832d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4272886570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.4272886570
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.887182231
Short name T2797
Test name
Test status
Simulation time 63958447 ps
CPU time 1.03 seconds
Started Jul 14 07:03:55 PM PDT 24
Finished Jul 14 07:03:57 PM PDT 24
Peak memory 206464 kb
Host smart-9f47e82c-a734-4cab-b396-7e69c4593ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=887182231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.887182231
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.994196101
Short name T229
Test name
Test status
Simulation time 94698187 ps
CPU time 2.45 seconds
Started Jul 14 07:03:48 PM PDT 24
Finished Jul 14 07:03:51 PM PDT 24
Peak memory 206656 kb
Host smart-494e7607-37a3-41ff-a4a9-42fe97054b89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=994196101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.994196101
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3861177050
Short name T216
Test name
Test status
Simulation time 2177960965 ps
CPU time 6.16 seconds
Started Jul 14 07:03:51 PM PDT 24
Finished Jul 14 07:03:58 PM PDT 24
Peak memory 206692 kb
Host smart-dbfff805-c601-48f0-8a84-1b7531a27422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3861177050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3861177050
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2753491917
Short name T233
Test name
Test status
Simulation time 162671288 ps
CPU time 1.61 seconds
Started Jul 14 07:03:55 PM PDT 24
Finished Jul 14 07:03:57 PM PDT 24
Peak memory 214796 kb
Host smart-e9658e45-396b-45df-843e-a8db464b3560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753491917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2753491917
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1066882345
Short name T248
Test name
Test status
Simulation time 61268009 ps
CPU time 0.81 seconds
Started Jul 14 07:03:51 PM PDT 24
Finished Jul 14 07:03:52 PM PDT 24
Peak memory 206232 kb
Host smart-61c8d90a-a44f-46ed-9fec-3a0c150a20e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1066882345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1066882345
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1172102774
Short name T2763
Test name
Test status
Simulation time 36741257 ps
CPU time 0.66 seconds
Started Jul 14 07:03:48 PM PDT 24
Finished Jul 14 07:03:50 PM PDT 24
Peak memory 206372 kb
Host smart-d8072a8d-234d-4152-8150-cf54cc4873fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1172102774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1172102774
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3461699075
Short name T2755
Test name
Test status
Simulation time 197405635 ps
CPU time 1.27 seconds
Started Jul 14 07:03:55 PM PDT 24
Finished Jul 14 07:03:57 PM PDT 24
Peak memory 206584 kb
Host smart-011840db-e61c-4248-afff-7edab95466f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3461699075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3461699075
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2401724990
Short name T2799
Test name
Test status
Simulation time 58193474 ps
CPU time 1.28 seconds
Started Jul 14 07:03:49 PM PDT 24
Finished Jul 14 07:03:51 PM PDT 24
Peak memory 206596 kb
Host smart-45ca3e86-7353-42c5-bcc8-54709b930085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2401724990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2401724990
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3925045805
Short name T295
Test name
Test status
Simulation time 547607858 ps
CPU time 4.1 seconds
Started Jul 14 07:03:48 PM PDT 24
Finished Jul 14 07:03:52 PM PDT 24
Peak memory 206672 kb
Host smart-93ba18f5-fe43-4feb-9214-5331c545ee8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3925045805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3925045805
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2245666914
Short name T2758
Test name
Test status
Simulation time 89797470 ps
CPU time 2.25 seconds
Started Jul 14 07:04:00 PM PDT 24
Finished Jul 14 07:04:03 PM PDT 24
Peak memory 214820 kb
Host smart-f9b9b4e8-0de4-4a1b-8b72-dfb0137ab4ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245666914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2245666914
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2151164443
Short name T2798
Test name
Test status
Simulation time 112646102 ps
CPU time 1.02 seconds
Started Jul 14 07:03:57 PM PDT 24
Finished Jul 14 07:03:59 PM PDT 24
Peak memory 206560 kb
Host smart-33692cb0-9ee1-4adc-90ab-6707cc4da2be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2151164443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2151164443
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.675990370
Short name T277
Test name
Test status
Simulation time 46500771 ps
CPU time 0.68 seconds
Started Jul 14 07:03:53 PM PDT 24
Finished Jul 14 07:03:54 PM PDT 24
Peak memory 206372 kb
Host smart-05260205-c6cf-4717-b583-f91db08e126c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=675990370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.675990370
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2529387355
Short name T2804
Test name
Test status
Simulation time 56070640 ps
CPU time 1 seconds
Started Jul 14 07:03:54 PM PDT 24
Finished Jul 14 07:03:55 PM PDT 24
Peak memory 206504 kb
Host smart-e1c7e2da-32a9-4c23-9b69-a585682b4cd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2529387355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2529387355
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1334102120
Short name T2781
Test name
Test status
Simulation time 114489051 ps
CPU time 2.18 seconds
Started Jul 14 07:03:55 PM PDT 24
Finished Jul 14 07:03:58 PM PDT 24
Peak memory 222340 kb
Host smart-1002efaa-1be5-41ce-a289-5ed0c21a7039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1334102120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1334102120
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3919562052
Short name T2754
Test name
Test status
Simulation time 81982568 ps
CPU time 1.63 seconds
Started Jul 14 07:04:01 PM PDT 24
Finished Jul 14 07:04:03 PM PDT 24
Peak memory 214952 kb
Host smart-a0b94bab-3b24-4dfe-92da-cf7ac366044f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919562052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3919562052
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2206321029
Short name T2833
Test name
Test status
Simulation time 96641450 ps
CPU time 1.01 seconds
Started Jul 14 07:03:59 PM PDT 24
Finished Jul 14 07:04:00 PM PDT 24
Peak memory 206520 kb
Host smart-29453462-9378-495e-a7c7-2168ff782cdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2206321029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2206321029
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2644542442
Short name T2759
Test name
Test status
Simulation time 42146512 ps
CPU time 0.7 seconds
Started Jul 14 07:04:01 PM PDT 24
Finished Jul 14 07:04:02 PM PDT 24
Peak memory 206356 kb
Host smart-4ab09b34-3f3b-4e59-81f3-d3dcea18dea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2644542442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2644542442
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1100139770
Short name T2789
Test name
Test status
Simulation time 244908097 ps
CPU time 1.82 seconds
Started Jul 14 07:04:00 PM PDT 24
Finished Jul 14 07:04:02 PM PDT 24
Peak memory 206628 kb
Host smart-3c0284f3-1973-4f25-a9d6-1e8d7260c4e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1100139770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1100139770
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.671212779
Short name T225
Test name
Test status
Simulation time 105503876 ps
CPU time 3.01 seconds
Started Jul 14 07:04:01 PM PDT 24
Finished Jul 14 07:04:05 PM PDT 24
Peak memory 214820 kb
Host smart-ecf94f37-e334-4b10-abd2-e31953aa0784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=671212779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.671212779
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.752081217
Short name T231
Test name
Test status
Simulation time 117696202 ps
CPU time 1.23 seconds
Started Jul 14 07:04:02 PM PDT 24
Finished Jul 14 07:04:04 PM PDT 24
Peak memory 214812 kb
Host smart-0b658f67-ad6e-43c9-8e97-5d8d1aa7ef5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752081217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.752081217
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2638029855
Short name T2836
Test name
Test status
Simulation time 74663905 ps
CPU time 1.01 seconds
Started Jul 14 07:03:59 PM PDT 24
Finished Jul 14 07:04:01 PM PDT 24
Peak memory 206516 kb
Host smart-c34c8dc8-0e9f-42d8-9eee-024c544a9db6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2638029855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2638029855
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3431091600
Short name T2847
Test name
Test status
Simulation time 44917106 ps
CPU time 0.69 seconds
Started Jul 14 07:04:02 PM PDT 24
Finished Jul 14 07:04:04 PM PDT 24
Peak memory 206424 kb
Host smart-d5757b90-908a-4e69-b2ac-cbcfd9420e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3431091600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3431091600
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3072969703
Short name T2782
Test name
Test status
Simulation time 181764668 ps
CPU time 1.6 seconds
Started Jul 14 07:04:00 PM PDT 24
Finished Jul 14 07:04:03 PM PDT 24
Peak memory 206652 kb
Host smart-c533a72f-3e2b-47d3-a6cc-cf116dd70c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3072969703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3072969703
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1389475584
Short name T228
Test name
Test status
Simulation time 199799382 ps
CPU time 2.31 seconds
Started Jul 14 07:04:01 PM PDT 24
Finished Jul 14 07:04:04 PM PDT 24
Peak memory 206624 kb
Host smart-de6a8168-7f20-43bf-a1d3-a4a60707f86a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1389475584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1389475584
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1668967565
Short name T235
Test name
Test status
Simulation time 450937932 ps
CPU time 3.05 seconds
Started Jul 14 07:04:02 PM PDT 24
Finished Jul 14 07:04:06 PM PDT 24
Peak memory 206576 kb
Host smart-5a86d911-f3b1-4d53-b10f-f2be9037f99a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1668967565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1668967565
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2248954680
Short name T1624
Test name
Test status
Simulation time 62657590 ps
CPU time 0.71 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:12:46 PM PDT 24
Peak memory 206936 kb
Host smart-8f891682-cf39-4139-ad59-37d1872c0f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2248954680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2248954680
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.932028926
Short name T1588
Test name
Test status
Simulation time 13377243073 ps
CPU time 13.22 seconds
Started Jul 14 07:12:21 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206876 kb
Host smart-41864b06-cade-4369-ae3c-a35b7c9a7850
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=932028926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.932028926
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3779401466
Short name T2470
Test name
Test status
Simulation time 23368360715 ps
CPU time 26.83 seconds
Started Jul 14 07:12:21 PM PDT 24
Finished Jul 14 07:12:50 PM PDT 24
Peak memory 207124 kb
Host smart-f912dd4b-fbb8-439a-be29-f6589bd49041
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3779401466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3779401466
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4213512163
Short name T1487
Test name
Test status
Simulation time 141368902 ps
CPU time 0.81 seconds
Started Jul 14 07:12:25 PM PDT 24
Finished Jul 14 07:12:29 PM PDT 24
Peak memory 206880 kb
Host smart-5973fee0-a45f-4311-94f5-c1bc7984a0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
12163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4213512163
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2428328318
Short name T2067
Test name
Test status
Simulation time 147422646 ps
CPU time 0.86 seconds
Started Jul 14 07:12:24 PM PDT 24
Finished Jul 14 07:12:28 PM PDT 24
Peak memory 206876 kb
Host smart-6b71b051-a64b-4738-87fa-1078aa008ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24283
28318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2428328318
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3103016689
Short name T356
Test name
Test status
Simulation time 471629871 ps
CPU time 1.44 seconds
Started Jul 14 07:12:24 PM PDT 24
Finished Jul 14 07:12:28 PM PDT 24
Peak memory 207028 kb
Host smart-47fbce28-0cf9-4b8b-be0a-e06d979feb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31030
16689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3103016689
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.360075803
Short name T1287
Test name
Test status
Simulation time 1002408125 ps
CPU time 2.33 seconds
Started Jul 14 07:12:22 PM PDT 24
Finished Jul 14 07:12:26 PM PDT 24
Peak memory 207004 kb
Host smart-e946d5fc-25b4-4e75-bed0-e6b65c2366ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36007
5803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.360075803
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.603328276
Short name T1188
Test name
Test status
Simulation time 8976834828 ps
CPU time 16.87 seconds
Started Jul 14 07:12:31 PM PDT 24
Finished Jul 14 07:12:53 PM PDT 24
Peak memory 207096 kb
Host smart-70a5f02b-a342-4e97-99d1-243db835a9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60332
8276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.603328276
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2546708050
Short name T1264
Test name
Test status
Simulation time 333975765 ps
CPU time 1.15 seconds
Started Jul 14 07:12:24 PM PDT 24
Finished Jul 14 07:12:27 PM PDT 24
Peak memory 206848 kb
Host smart-b34d1499-af73-4f8b-9643-20afbea4a270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25467
08050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2546708050
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.406181186
Short name T1323
Test name
Test status
Simulation time 196876870 ps
CPU time 0.83 seconds
Started Jul 14 07:12:30 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206872 kb
Host smart-1a09599e-c2b1-4f36-84b2-501f1a0c2e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40618
1186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.406181186
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1290035521
Short name T2564
Test name
Test status
Simulation time 5188001846 ps
CPU time 33.37 seconds
Started Jul 14 07:12:30 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 207064 kb
Host smart-1116d921-8d27-4975-b39b-1ac38bf4185f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12900
35521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1290035521
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1279783052
Short name T315
Test name
Test status
Simulation time 101406189 ps
CPU time 0.74 seconds
Started Jul 14 07:12:23 PM PDT 24
Finished Jul 14 07:12:26 PM PDT 24
Peak memory 206852 kb
Host smart-590f219c-7df0-4df0-915b-90fa923fdb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12797
83052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1279783052
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3072171454
Short name T857
Test name
Test status
Simulation time 865780735 ps
CPU time 1.96 seconds
Started Jul 14 07:12:26 PM PDT 24
Finished Jul 14 07:12:32 PM PDT 24
Peak memory 207028 kb
Host smart-058b72ca-e1d8-48cf-8826-00a8f71d0122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30721
71454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3072171454
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.428939972
Short name T1459
Test name
Test status
Simulation time 387714592 ps
CPU time 2.32 seconds
Started Jul 14 07:12:28 PM PDT 24
Finished Jul 14 07:12:35 PM PDT 24
Peak memory 207032 kb
Host smart-eb6022b3-8191-4554-a32b-31f656907550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42893
9972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.428939972
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.271211920
Short name T893
Test name
Test status
Simulation time 110197586873 ps
CPU time 143.4 seconds
Started Jul 14 07:12:23 PM PDT 24
Finished Jul 14 07:14:48 PM PDT 24
Peak memory 207156 kb
Host smart-da4583b4-66cf-44c5-9f03-c90407afcf87
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=271211920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.271211920
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2218254110
Short name T2456
Test name
Test status
Simulation time 91124162539 ps
CPU time 128.3 seconds
Started Jul 14 07:12:28 PM PDT 24
Finished Jul 14 07:14:41 PM PDT 24
Peak memory 207072 kb
Host smart-03301454-8d47-4347-9f8d-38d45f675530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218254110 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2218254110
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1952510135
Short name T553
Test name
Test status
Simulation time 87169822915 ps
CPU time 128.26 seconds
Started Jul 14 07:12:24 PM PDT 24
Finished Jul 14 07:14:35 PM PDT 24
Peak memory 207048 kb
Host smart-37e4da98-0799-4889-98fe-f4290cc741f7
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1952510135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1952510135
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3903896628
Short name T587
Test name
Test status
Simulation time 97129643326 ps
CPU time 131.7 seconds
Started Jul 14 07:12:24 PM PDT 24
Finished Jul 14 07:14:39 PM PDT 24
Peak memory 207112 kb
Host smart-bd830d6e-f6fb-4e88-a461-6dcc500006eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903896628 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3903896628
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.2033403001
Short name T314
Test name
Test status
Simulation time 116135110116 ps
CPU time 164.95 seconds
Started Jul 14 07:12:21 PM PDT 24
Finished Jul 14 07:15:09 PM PDT 24
Peak memory 207100 kb
Host smart-7dbb05bc-87d4-4e7b-9cde-25b6b3b17b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
03001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2033403001
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2938670977
Short name T927
Test name
Test status
Simulation time 215864829 ps
CPU time 0.9 seconds
Started Jul 14 07:12:22 PM PDT 24
Finished Jul 14 07:12:25 PM PDT 24
Peak memory 206860 kb
Host smart-84f45bb2-0a78-4385-b87b-d8a08c144f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29386
70977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2938670977
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.924013816
Short name T2057
Test name
Test status
Simulation time 160028464 ps
CPU time 0.75 seconds
Started Jul 14 07:12:26 PM PDT 24
Finished Jul 14 07:12:32 PM PDT 24
Peak memory 206832 kb
Host smart-7403ae4c-19d1-418f-a34d-e8ed0d45709f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92401
3816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.924013816
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.401922003
Short name T139
Test name
Test status
Simulation time 181330576 ps
CPU time 0.84 seconds
Started Jul 14 07:12:26 PM PDT 24
Finished Jul 14 07:12:32 PM PDT 24
Peak memory 206880 kb
Host smart-2c65ee93-51f1-4c2b-a492-94d513cda781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40192
2003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.401922003
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1405960209
Short name T2347
Test name
Test status
Simulation time 5615697894 ps
CPU time 20.17 seconds
Started Jul 14 07:12:21 PM PDT 24
Finished Jul 14 07:12:43 PM PDT 24
Peak memory 207088 kb
Host smart-82441192-ac4e-4ed3-b499-3ebda4c7168d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
60209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1405960209
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2082099137
Short name T2277
Test name
Test status
Simulation time 163384972 ps
CPU time 0.78 seconds
Started Jul 14 07:12:25 PM PDT 24
Finished Jul 14 07:12:30 PM PDT 24
Peak memory 206852 kb
Host smart-569f2d6d-d75c-43fe-a4dc-e42775cd6534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20820
99137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2082099137
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.839093965
Short name T67
Test name
Test status
Simulation time 476649751 ps
CPU time 1.47 seconds
Started Jul 14 07:12:26 PM PDT 24
Finished Jul 14 07:12:32 PM PDT 24
Peak memory 206876 kb
Host smart-f165cdee-7875-49fc-8972-008de426115b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83909
3965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.839093965
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2687531545
Short name T664
Test name
Test status
Simulation time 23320398756 ps
CPU time 23.96 seconds
Started Jul 14 07:12:28 PM PDT 24
Finished Jul 14 07:12:57 PM PDT 24
Peak memory 206916 kb
Host smart-61eb3e9f-1125-4fc0-b6d5-7233fdff5f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26875
31545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2687531545
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1600995524
Short name T406
Test name
Test status
Simulation time 3292254987 ps
CPU time 3.9 seconds
Started Jul 14 07:12:26 PM PDT 24
Finished Jul 14 07:12:35 PM PDT 24
Peak memory 206932 kb
Host smart-6cad402e-8b58-41b2-b9f6-5327847517c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
95524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1600995524
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.954306279
Short name T1563
Test name
Test status
Simulation time 7450180288 ps
CPU time 71.08 seconds
Started Jul 14 07:12:29 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 207152 kb
Host smart-4746d929-595d-4fa2-bc8c-2c39a987193e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95430
6279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.954306279
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2512242585
Short name T175
Test name
Test status
Simulation time 4376480959 ps
CPU time 32.75 seconds
Started Jul 14 07:12:30 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 207100 kb
Host smart-0e3f3b8d-ceed-4caf-9afd-2724225755c3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2512242585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2512242585
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2196549804
Short name T437
Test name
Test status
Simulation time 236078290 ps
CPU time 0.91 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:12:44 PM PDT 24
Peak memory 206836 kb
Host smart-661cd239-f0e5-47fb-b82c-d5f52771f83b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2196549804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2196549804
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2731385024
Short name T792
Test name
Test status
Simulation time 187885861 ps
CPU time 0.87 seconds
Started Jul 14 07:12:29 PM PDT 24
Finished Jul 14 07:12:36 PM PDT 24
Peak memory 206860 kb
Host smart-057e9ab0-22db-48b3-b1be-da52dc5e1cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27313
85024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2731385024
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.403996019
Short name T2214
Test name
Test status
Simulation time 4089875536 ps
CPU time 36.24 seconds
Started Jul 14 07:12:28 PM PDT 24
Finished Jul 14 07:13:10 PM PDT 24
Peak memory 207096 kb
Host smart-54e88792-1b8d-4b9f-b3c5-5060824234f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40399
6019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.403996019
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1269157094
Short name T1641
Test name
Test status
Simulation time 2945208576 ps
CPU time 77.1 seconds
Started Jul 14 07:12:29 PM PDT 24
Finished Jul 14 07:13:52 PM PDT 24
Peak memory 207104 kb
Host smart-0ddce8f1-7c83-44c0-8993-2b25732cf052
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1269157094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1269157094
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1160047955
Short name T2381
Test name
Test status
Simulation time 179188188 ps
CPU time 0.83 seconds
Started Jul 14 07:12:30 PM PDT 24
Finished Jul 14 07:12:36 PM PDT 24
Peak memory 206856 kb
Host smart-267b40fe-d287-45bc-99f9-1cbfba6bc190
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1160047955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1160047955
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.975726164
Short name T453
Test name
Test status
Simulation time 197268593 ps
CPU time 0.87 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:12:40 PM PDT 24
Peak memory 206304 kb
Host smart-51396c0c-f419-4d09-8f63-00385e0901f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97572
6164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.975726164
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.4238208468
Short name T68
Test name
Test status
Simulation time 403227604 ps
CPU time 1.4 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:45 PM PDT 24
Peak memory 206460 kb
Host smart-99b83ff2-226d-4ffb-bdf1-6037feda612d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42382
08468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.4238208468
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.4117215599
Short name T21
Test name
Test status
Simulation time 196232903 ps
CPU time 0.89 seconds
Started Jul 14 07:12:33 PM PDT 24
Finished Jul 14 07:12:40 PM PDT 24
Peak memory 206876 kb
Host smart-cf51a9a5-37ca-4575-ac12-41506148de77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41172
15599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.4117215599
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.959342392
Short name T768
Test name
Test status
Simulation time 172220088 ps
CPU time 0.85 seconds
Started Jul 14 07:12:33 PM PDT 24
Finished Jul 14 07:12:41 PM PDT 24
Peak memory 206804 kb
Host smart-49ff20f2-254a-4d38-ab0c-358b8ebfc742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95934
2392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.959342392
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3186487981
Short name T415
Test name
Test status
Simulation time 180884861 ps
CPU time 0.83 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:12:39 PM PDT 24
Peak memory 206856 kb
Host smart-278f92e5-a284-4323-9f6a-4ee101942e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31864
87981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3186487981
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1078461618
Short name T1913
Test name
Test status
Simulation time 197869038 ps
CPU time 0.83 seconds
Started Jul 14 07:12:29 PM PDT 24
Finished Jul 14 07:12:36 PM PDT 24
Peak memory 206856 kb
Host smart-10141882-8b73-4b2e-a2e2-507780f9d0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10784
61618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1078461618
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.552430149
Short name T162
Test name
Test status
Simulation time 148023883 ps
CPU time 0.76 seconds
Started Jul 14 07:12:29 PM PDT 24
Finished Jul 14 07:12:35 PM PDT 24
Peak memory 206844 kb
Host smart-b1101187-73f6-4300-b478-9bd161611d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55243
0149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.552430149
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.4145017427
Short name T510
Test name
Test status
Simulation time 210782465 ps
CPU time 0.92 seconds
Started Jul 14 07:12:28 PM PDT 24
Finished Jul 14 07:12:34 PM PDT 24
Peak memory 206868 kb
Host smart-cc9d9399-c766-476b-96cb-7467c1733b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41450
17427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.4145017427
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2143495408
Short name T138
Test name
Test status
Simulation time 250575716 ps
CPU time 1.01 seconds
Started Jul 14 07:12:29 PM PDT 24
Finished Jul 14 07:12:35 PM PDT 24
Peak memory 206868 kb
Host smart-9920c432-43da-4ea6-a4eb-f9da53a32408
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2143495408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2143495408
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3470431147
Short name T201
Test name
Test status
Simulation time 234894663 ps
CPU time 0.97 seconds
Started Jul 14 07:12:31 PM PDT 24
Finished Jul 14 07:12:39 PM PDT 24
Peak memory 206852 kb
Host smart-48a09671-1ac1-4dd9-9863-8c9f19330086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
31147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3470431147
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.9038983
Short name T200
Test name
Test status
Simulation time 176198024 ps
CPU time 0.85 seconds
Started Jul 14 07:12:29 PM PDT 24
Finished Jul 14 07:12:35 PM PDT 24
Peak memory 206844 kb
Host smart-657f7b6e-1513-42c6-b5a0-2d8b6fb51472
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=9038983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.9038983
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2931265460
Short name T271
Test name
Test status
Simulation time 14065306195 ps
CPU time 31.96 seconds
Started Jul 14 07:12:27 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 215268 kb
Host smart-5a179930-4a03-4fbd-a12a-85f15a00236a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312
65460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2931265460
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2687196211
Short name T879
Test name
Test status
Simulation time 174837881 ps
CPU time 0.82 seconds
Started Jul 14 07:12:30 PM PDT 24
Finished Jul 14 07:12:36 PM PDT 24
Peak memory 206888 kb
Host smart-b7b7da4e-d4d4-4687-82f9-0106a2007657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
96211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2687196211
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.4256958703
Short name T1011
Test name
Test status
Simulation time 218869257 ps
CPU time 0.9 seconds
Started Jul 14 07:12:31 PM PDT 24
Finished Jul 14 07:12:38 PM PDT 24
Peak memory 206828 kb
Host smart-ade8a2db-2a39-4e2a-ae58-228a326d7d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42569
58703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.4256958703
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1205077649
Short name T151
Test name
Test status
Simulation time 7414328359 ps
CPU time 61.61 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:13:40 PM PDT 24
Peak memory 207128 kb
Host smart-847b9465-0529-422d-8962-674f25b38de6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1205077649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1205077649
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2164593757
Short name T1949
Test name
Test status
Simulation time 13914721258 ps
CPU time 275.45 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:17:19 PM PDT 24
Peak memory 207172 kb
Host smart-621f7399-138b-4496-9f43-899120848e75
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2164593757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2164593757
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1215956683
Short name T1783
Test name
Test status
Simulation time 8120117327 ps
CPU time 114.26 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:14:32 PM PDT 24
Peak memory 207112 kb
Host smart-12876271-d55b-4272-9b3e-7d6ed804028e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1215956683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1215956683
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.2292453844
Short name T1093
Test name
Test status
Simulation time 241210378 ps
CPU time 0.95 seconds
Started Jul 14 07:12:31 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206860 kb
Host smart-720f05d1-879c-474c-9d58-7b52dbe22926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22924
53844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.2292453844
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.291458530
Short name T488
Test name
Test status
Simulation time 203874760 ps
CPU time 0.88 seconds
Started Jul 14 07:12:30 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206884 kb
Host smart-b2f47682-8ba8-4f19-a1ab-9f6b1e6a5802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29145
8530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.291458530
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1320785343
Short name T417
Test name
Test status
Simulation time 178847293 ps
CPU time 0.8 seconds
Started Jul 14 07:12:30 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206860 kb
Host smart-68f00bbb-3fc8-4131-bd51-60acba4ac7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
85343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1320785343
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3166930534
Short name T1522
Test name
Test status
Simulation time 195634232 ps
CPU time 0.87 seconds
Started Jul 14 07:12:31 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206812 kb
Host smart-b0dd5f23-5e32-4abd-ab86-4d50242f8c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669
30534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3166930534
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1464994953
Short name T2547
Test name
Test status
Simulation time 171073995 ps
CPU time 0.8 seconds
Started Jul 14 07:12:31 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 206840 kb
Host smart-4907cbbd-027a-4136-909c-e965f2de94f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14649
94953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1464994953
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3634326738
Short name T617
Test name
Test status
Simulation time 191151057 ps
CPU time 0.85 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:12:40 PM PDT 24
Peak memory 206880 kb
Host smart-389d3b49-db03-4a3c-993c-631bcfec07f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36343
26738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3634326738
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3037467029
Short name T2361
Test name
Test status
Simulation time 287852472 ps
CPU time 0.99 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:44 PM PDT 24
Peak memory 206788 kb
Host smart-1f618442-2837-4a91-b662-cab8456d6117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30374
67029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3037467029
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1976501957
Short name T2627
Test name
Test status
Simulation time 4469575169 ps
CPU time 120.39 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:14:39 PM PDT 24
Peak memory 206504 kb
Host smart-58c2d4f1-9ff7-40a2-aeb0-2e96d57f4b35
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1976501957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1976501957
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.270205254
Short name T2630
Test name
Test status
Simulation time 187577931 ps
CPU time 0.91 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:12:43 PM PDT 24
Peak memory 206868 kb
Host smart-f6fe085f-d5fd-4430-9788-8bf80bd8d903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020
5254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.270205254
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.356000638
Short name T816
Test name
Test status
Simulation time 196920094 ps
CPU time 0.95 seconds
Started Jul 14 07:12:33 PM PDT 24
Finished Jul 14 07:12:40 PM PDT 24
Peak memory 206872 kb
Host smart-c29d4d0a-9461-46a0-a685-16c21fca5529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35600
0638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.356000638
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.4041227188
Short name T236
Test name
Test status
Simulation time 317175508 ps
CPU time 1.08 seconds
Started Jul 14 07:12:33 PM PDT 24
Finished Jul 14 07:12:41 PM PDT 24
Peak memory 206872 kb
Host smart-d53c8359-7603-4064-9835-cdbc0efb3802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40412
27188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.4041227188
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3313560474
Short name T2387
Test name
Test status
Simulation time 3698920731 ps
CPU time 101.87 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:14:20 PM PDT 24
Peak memory 207068 kb
Host smart-ad02278c-b1c5-4e27-abd9-8d3eb50d903a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33135
60474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3313560474
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3703489797
Short name T1890
Test name
Test status
Simulation time 23117594962 ps
CPU time 195.8 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:16:01 PM PDT 24
Peak memory 207124 kb
Host smart-5c9e8de3-ba2e-42de-b0b3-ab35d860cf40
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3703489797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3703489797
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1644742005
Short name T767
Test name
Test status
Simulation time 58525408 ps
CPU time 0.68 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206908 kb
Host smart-9d793053-fd09-4c65-87c1-bcf33732af78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1644742005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1644742005
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.967131639
Short name T1582
Test name
Test status
Simulation time 4089836436 ps
CPU time 4.5 seconds
Started Jul 14 07:12:27 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 207164 kb
Host smart-b1fa79a6-6349-409c-a349-dcde44043dc6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=967131639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.967131639
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3154632606
Short name T965
Test name
Test status
Simulation time 13394276122 ps
CPU time 16.54 seconds
Started Jul 14 07:12:32 PM PDT 24
Finished Jul 14 07:12:55 PM PDT 24
Peak memory 206888 kb
Host smart-964cfc40-8cf0-4269-9dd0-e81923eaa804
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3154632606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3154632606
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.903454266
Short name T1437
Test name
Test status
Simulation time 23391304981 ps
CPU time 24.07 seconds
Started Jul 14 07:12:34 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206952 kb
Host smart-17b63acf-4617-4f76-8492-3fe50da89fcf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=903454266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.903454266
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3550407996
Short name T2567
Test name
Test status
Simulation time 205554892 ps
CPU time 0.9 seconds
Started Jul 14 07:12:33 PM PDT 24
Finished Jul 14 07:12:42 PM PDT 24
Peak memory 206840 kb
Host smart-724ff9a0-3b31-40c9-b36a-acbb4cf92c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35504
07996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3550407996
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2682945472
Short name T79
Test name
Test status
Simulation time 169282201 ps
CPU time 0.82 seconds
Started Jul 14 07:12:34 PM PDT 24
Finished Jul 14 07:12:42 PM PDT 24
Peak memory 206852 kb
Host smart-bd955444-59d9-45bc-9cc5-c9f3162a5b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26829
45472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2682945472
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.353927562
Short name T1134
Test name
Test status
Simulation time 143859309 ps
CPU time 0.79 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206852 kb
Host smart-ba6aa65a-c2d3-4daf-bd78-704ec8104190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35392
7562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.353927562
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1069189004
Short name T1365
Test name
Test status
Simulation time 198712862 ps
CPU time 0.87 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:12:48 PM PDT 24
Peak memory 206888 kb
Host smart-c6450178-935c-48fe-a377-d9fe9f0ed3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10691
89004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1069189004
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.879391
Short name T1393
Test name
Test status
Simulation time 788488585 ps
CPU time 1.98 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:46 PM PDT 24
Peak memory 207044 kb
Host smart-b706de7e-7a9c-4103-8995-a27f85ef5adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87939
1 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.879391
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.1585588413
Short name T971
Test name
Test status
Simulation time 14035909777 ps
CPU time 25.51 seconds
Started Jul 14 07:12:39 PM PDT 24
Finished Jul 14 07:13:14 PM PDT 24
Peak memory 207076 kb
Host smart-a0fd428f-aac7-4c66-90c2-69d9324b7e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15855
88413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1585588413
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1627243240
Short name T911
Test name
Test status
Simulation time 357501921 ps
CPU time 1.19 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:12:46 PM PDT 24
Peak memory 206872 kb
Host smart-eea6928f-60b5-4c4b-b3bc-8589133b17b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16272
43240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1627243240
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2927868428
Short name T1953
Test name
Test status
Simulation time 144641696 ps
CPU time 0.75 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:12:48 PM PDT 24
Peak memory 206812 kb
Host smart-ae203178-ef7a-4f3a-b296-5bc2734850d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29278
68428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2927868428
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1050603501
Short name T1756
Test name
Test status
Simulation time 48797156 ps
CPU time 0.67 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:45 PM PDT 24
Peak memory 206844 kb
Host smart-761d3032-1c41-4e14-82ff-f83580f54170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
03501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1050603501
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.666687581
Short name T945
Test name
Test status
Simulation time 788661768 ps
CPU time 2.17 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:12:48 PM PDT 24
Peak memory 207080 kb
Host smart-701bc58b-c26d-434a-a04a-60100ebdb83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66668
7581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.666687581
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3166469345
Short name T1100
Test name
Test status
Simulation time 288017800 ps
CPU time 2.2 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:12:59 PM PDT 24
Peak memory 207004 kb
Host smart-9f758829-8f88-4903-9568-c74945c704f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31664
69345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3166469345
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2055553528
Short name T862
Test name
Test status
Simulation time 91179034212 ps
CPU time 120.66 seconds
Started Jul 14 07:12:40 PM PDT 24
Finished Jul 14 07:14:50 PM PDT 24
Peak memory 207052 kb
Host smart-38e4b95f-c895-4929-8a7f-17066b5e1043
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2055553528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2055553528
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.2780809110
Short name T1826
Test name
Test status
Simulation time 110300409663 ps
CPU time 176.99 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:15:41 PM PDT 24
Peak memory 207060 kb
Host smart-f01b469f-808e-4c79-9865-fcb5f8a7fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780809110 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.2780809110
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2080249409
Short name T1833
Test name
Test status
Simulation time 83120012661 ps
CPU time 115.53 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:14:39 PM PDT 24
Peak memory 207056 kb
Host smart-0faba384-62e2-422a-bc63-848006391652
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2080249409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2080249409
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.1341841513
Short name T2336
Test name
Test status
Simulation time 101209836820 ps
CPU time 130.82 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206684 kb
Host smart-c21fd78c-6abe-431c-9bae-a1baa747bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341841513 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1341841513
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3668806345
Short name T1768
Test name
Test status
Simulation time 106149619029 ps
CPU time 139.57 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:15:07 PM PDT 24
Peak memory 207156 kb
Host smart-ed7e7a17-38c8-4051-b830-584f8db506b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36688
06345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3668806345
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1514600299
Short name T2364
Test name
Test status
Simulation time 188925174 ps
CPU time 0.94 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:45 PM PDT 24
Peak memory 206872 kb
Host smart-7a5274e6-55e4-4687-8363-3ac1fa27fef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
00299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1514600299
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1421976992
Short name T1742
Test name
Test status
Simulation time 138278547 ps
CPU time 0.75 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:12:43 PM PDT 24
Peak memory 206844 kb
Host smart-b832b61b-bc55-4cb0-9463-854dce9ecdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
76992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1421976992
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2260655375
Short name T1681
Test name
Test status
Simulation time 207501130 ps
CPU time 0.94 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:44 PM PDT 24
Peak memory 206584 kb
Host smart-d6207412-ed2a-49b1-8b54-d9c00ae8a164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606
55375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2260655375
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2496225732
Short name T5
Test name
Test status
Simulation time 10394435398 ps
CPU time 283.77 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:17:26 PM PDT 24
Peak memory 207076 kb
Host smart-b3ae8c08-8165-4373-bfb4-bb045d2abf4d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2496225732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2496225732
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.1687814746
Short name T2644
Test name
Test status
Simulation time 13555962152 ps
CPU time 48.32 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:13:50 PM PDT 24
Peak memory 207112 kb
Host smart-8ef5b7f5-4ae3-4828-8d55-3b2365bf74e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16878
14746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.1687814746
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3996069415
Short name T2178
Test name
Test status
Simulation time 173253823 ps
CPU time 0.82 seconds
Started Jul 14 07:12:40 PM PDT 24
Finished Jul 14 07:12:50 PM PDT 24
Peak memory 206808 kb
Host smart-f6438e97-fba7-43b2-91d9-dcb68dca52f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39960
69415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3996069415
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.47930152
Short name T40
Test name
Test status
Simulation time 23295521109 ps
CPU time 24.96 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:13:12 PM PDT 24
Peak memory 206928 kb
Host smart-b2f25d5a-8630-45b4-b822-adbdcc6c1a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47930
152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.47930152
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1798925203
Short name T819
Test name
Test status
Simulation time 3319051973 ps
CPU time 4.34 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:12:48 PM PDT 24
Peak memory 206932 kb
Host smart-8944c08e-a45f-4ce2-8282-3eddad8d2cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17989
25203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1798925203
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2179319797
Short name T1920
Test name
Test status
Simulation time 6140719810 ps
CPU time 44.55 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:13:30 PM PDT 24
Peak memory 207116 kb
Host smart-a39dc863-24f0-4024-9ac2-a26a8b48658c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21793
19797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2179319797
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.409266412
Short name T1800
Test name
Test status
Simulation time 4153052612 ps
CPU time 38.06 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 207128 kb
Host smart-07a70ffd-deca-4c0c-a633-f3d337b41df4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=409266412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.409266412
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.831537401
Short name T1578
Test name
Test status
Simulation time 247084558 ps
CPU time 0.97 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:45 PM PDT 24
Peak memory 206852 kb
Host smart-ecac50ec-32c7-45e4-8bc7-da8bf1ae5981
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=831537401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.831537401
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1459109528
Short name T1377
Test name
Test status
Simulation time 190045151 ps
CPU time 0.86 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:45 PM PDT 24
Peak memory 206840 kb
Host smart-8e056520-6029-449a-8395-6d91999382a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14591
09528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1459109528
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1484640723
Short name T513
Test name
Test status
Simulation time 5128570933 ps
CPU time 47.46 seconds
Started Jul 14 07:12:40 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 207108 kb
Host smart-49f8281f-0584-4d6a-9386-46029327fc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14846
40723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1484640723
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.855699586
Short name T1201
Test name
Test status
Simulation time 3896959286 ps
CPU time 37.74 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 207148 kb
Host smart-9fda36e5-ad6a-41c9-a3a9-80b458e461b8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=855699586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.855699586
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3652875567
Short name T863
Test name
Test status
Simulation time 157542621 ps
CPU time 0.76 seconds
Started Jul 14 07:12:39 PM PDT 24
Finished Jul 14 07:12:49 PM PDT 24
Peak memory 206872 kb
Host smart-216f701b-da5b-4936-a771-f4391842e33e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3652875567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3652875567
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2419744285
Short name T2376
Test name
Test status
Simulation time 153328642 ps
CPU time 0.84 seconds
Started Jul 14 07:12:39 PM PDT 24
Finished Jul 14 07:12:49 PM PDT 24
Peak memory 206888 kb
Host smart-5e577f49-5c53-46ba-b597-d2208dc4a322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24197
44285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2419744285
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.467499366
Short name T2494
Test name
Test status
Simulation time 182681385 ps
CPU time 0.85 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206928 kb
Host smart-223e4ff7-dc03-495f-aae8-17607b9357de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46749
9366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.467499366
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1131685154
Short name T1623
Test name
Test status
Simulation time 187386339 ps
CPU time 0.88 seconds
Started Jul 14 07:12:35 PM PDT 24
Finished Jul 14 07:12:44 PM PDT 24
Peak memory 206872 kb
Host smart-a0b8fcce-b378-444a-9ca7-67009dee8228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11316
85154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1131685154
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2873595324
Short name T384
Test name
Test status
Simulation time 182708642 ps
CPU time 0.89 seconds
Started Jul 14 07:12:39 PM PDT 24
Finished Jul 14 07:12:49 PM PDT 24
Peak memory 206868 kb
Host smart-7481df26-119f-48d3-980d-99758628cc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28735
95324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2873595324
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.448981563
Short name T730
Test name
Test status
Simulation time 169141918 ps
CPU time 0.89 seconds
Started Jul 14 07:12:40 PM PDT 24
Finished Jul 14 07:12:50 PM PDT 24
Peak memory 206840 kb
Host smart-3729bda9-0e07-40bb-b41c-41ce8d35fe0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44898
1563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.448981563
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1923099094
Short name T2702
Test name
Test status
Simulation time 170428060 ps
CPU time 0.86 seconds
Started Jul 14 07:12:40 PM PDT 24
Finished Jul 14 07:12:50 PM PDT 24
Peak memory 206896 kb
Host smart-06fa076b-c692-4c2e-9071-48439e0bc765
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1923099094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1923099094
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.710009317
Short name T1446
Test name
Test status
Simulation time 260699363 ps
CPU time 1.03 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:12:44 PM PDT 24
Peak memory 206860 kb
Host smart-2347fa10-e05b-4772-8a9c-6f4a1536bd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71000
9317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.710009317
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2609269681
Short name T1754
Test name
Test status
Simulation time 151898838 ps
CPU time 0.8 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:12:46 PM PDT 24
Peak memory 207044 kb
Host smart-9ee3fd45-e8a1-4ded-924d-1ec922405bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26092
69681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2609269681
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.63656206
Short name T2018
Test name
Test status
Simulation time 39404236 ps
CPU time 0.66 seconds
Started Jul 14 07:12:42 PM PDT 24
Finished Jul 14 07:12:53 PM PDT 24
Peak memory 206852 kb
Host smart-e6ba6905-6ae3-4e71-ba10-35441808bb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63656
206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.63656206
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.4293656067
Short name T1963
Test name
Test status
Simulation time 13373025595 ps
CPU time 28.78 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 215324 kb
Host smart-5fb911d0-e47a-4495-a62e-32257e4c7e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936
56067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.4293656067
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.4251149808
Short name T1995
Test name
Test status
Simulation time 189741239 ps
CPU time 0.81 seconds
Started Jul 14 07:12:39 PM PDT 24
Finished Jul 14 07:12:49 PM PDT 24
Peak memory 206876 kb
Host smart-8da860c9-6c9d-4249-b528-74c27efe11c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42511
49808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.4251149808
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1798179769
Short name T382
Test name
Test status
Simulation time 169305629 ps
CPU time 0.79 seconds
Started Jul 14 07:12:39 PM PDT 24
Finished Jul 14 07:12:49 PM PDT 24
Peak memory 206868 kb
Host smart-73f7af0f-a9bb-4bd0-a0ff-a30eee873dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
79769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1798179769
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.932160888
Short name T150
Test name
Test status
Simulation time 8587819554 ps
CPU time 36.44 seconds
Started Jul 14 07:12:36 PM PDT 24
Finished Jul 14 07:13:20 PM PDT 24
Peak memory 207136 kb
Host smart-54a255b3-be1b-454f-8e2b-e1366b0ed004
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=932160888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.932160888
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1321053801
Short name T2206
Test name
Test status
Simulation time 9991963479 ps
CPU time 90.85 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:14:18 PM PDT 24
Peak memory 207068 kb
Host smart-fc62e7cd-e6a1-4c30-8655-1793a285308b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1321053801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1321053801
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.2352624776
Short name T1001
Test name
Test status
Simulation time 19473191255 ps
CPU time 447.87 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:20:25 PM PDT 24
Peak memory 207100 kb
Host smart-bf34b5d1-3da7-452c-ae18-1a48747efc54
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2352624776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2352624776
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.1710438426
Short name T1916
Test name
Test status
Simulation time 160021425 ps
CPU time 0.8 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:12:45 PM PDT 24
Peak memory 207048 kb
Host smart-460d089f-b745-40eb-8d7b-06de59024055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17104
38426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.1710438426
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.3811161796
Short name T1863
Test name
Test status
Simulation time 181490586 ps
CPU time 0.88 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206856 kb
Host smart-d0262cd3-bc2f-40bb-a4c1-a999c25688c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38111
61796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.3811161796
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1926115727
Short name T1440
Test name
Test status
Simulation time 181208415 ps
CPU time 0.88 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:12:46 PM PDT 24
Peak memory 206856 kb
Host smart-6655c4e9-efbc-4527-b3b7-7aa5ac06b1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19261
15727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1926115727
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1999038738
Short name T73
Test name
Test status
Simulation time 174285404 ps
CPU time 0.87 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:12:46 PM PDT 24
Peak memory 206876 kb
Host smart-1a72b048-3b62-4134-a75d-31888fa7fd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19990
38738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1999038738
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1405041554
Short name T210
Test name
Test status
Simulation time 381424318 ps
CPU time 1.23 seconds
Started Jul 14 07:12:47 PM PDT 24
Finished Jul 14 07:13:06 PM PDT 24
Peak memory 224604 kb
Host smart-ae8abfaa-9c02-4c1d-8383-eadb4a7419f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1405041554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1405041554
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.3423611031
Short name T52
Test name
Test status
Simulation time 482795007 ps
CPU time 1.43 seconds
Started Jul 14 07:12:41 PM PDT 24
Finished Jul 14 07:12:53 PM PDT 24
Peak memory 206892 kb
Host smart-66aa0a32-d214-41fb-bd5d-169c79aef8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34236
11031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.3423611031
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.746493591
Short name T957
Test name
Test status
Simulation time 217146462 ps
CPU time 0.98 seconds
Started Jul 14 07:12:39 PM PDT 24
Finished Jul 14 07:12:48 PM PDT 24
Peak memory 206880 kb
Host smart-2aa2a6c2-8e54-4981-ac1b-7e02df131d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74649
3591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.746493591
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1070479737
Short name T332
Test name
Test status
Simulation time 227980488 ps
CPU time 0.83 seconds
Started Jul 14 07:12:38 PM PDT 24
Finished Jul 14 07:12:48 PM PDT 24
Peak memory 206848 kb
Host smart-ac544f89-a80c-4fd3-a168-8ce21b073a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10704
79737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1070479737
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1423286782
Short name T1552
Test name
Test status
Simulation time 194554268 ps
CPU time 0.77 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206472 kb
Host smart-b39b9903-955f-4d45-9196-894c804505b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14232
86782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1423286782
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1407954077
Short name T2510
Test name
Test status
Simulation time 227019518 ps
CPU time 0.97 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206852 kb
Host smart-d4b32d22-4b2c-475d-b12c-744bde8f948e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14079
54077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1407954077
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.1395782834
Short name T1640
Test name
Test status
Simulation time 4682345729 ps
CPU time 42.86 seconds
Started Jul 14 07:12:39 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 207080 kb
Host smart-4a2d6ba5-6583-4f10-b2c7-657ab8b42874
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1395782834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.1395782834
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.567492259
Short name T428
Test name
Test status
Simulation time 173937427 ps
CPU time 0.78 seconds
Started Jul 14 07:12:37 PM PDT 24
Finished Jul 14 07:12:46 PM PDT 24
Peak memory 206900 kb
Host smart-026b141c-f4fb-4270-867c-68bef0e83cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56749
2259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.567492259
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3760449467
Short name T1661
Test name
Test status
Simulation time 167833450 ps
CPU time 0.77 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206852 kb
Host smart-d7ac3b99-2aab-4ca5-8fab-44b41852819c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37604
49467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3760449467
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1039298088
Short name T1633
Test name
Test status
Simulation time 248400255 ps
CPU time 0.92 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206872 kb
Host smart-f9893224-f169-4d3b-9842-9b5eaf1486d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10392
98088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1039298088
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.4253057135
Short name T2505
Test name
Test status
Simulation time 5558497311 ps
CPU time 148.18 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:15:29 PM PDT 24
Peak memory 207016 kb
Host smart-354c422c-21f6-43f5-bafd-155a36888285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42530
57135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.4253057135
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.305206654
Short name T2331
Test name
Test status
Simulation time 19303408636 ps
CPU time 144.72 seconds
Started Jul 14 07:12:48 PM PDT 24
Finished Jul 14 07:15:31 PM PDT 24
Peak memory 206920 kb
Host smart-b4701155-c1e8-4643-b153-743915935606
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=305206654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.305206654
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3060819527
Short name T2616
Test name
Test status
Simulation time 89613536 ps
CPU time 0.7 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206920 kb
Host smart-5bf11d53-c1b6-42ee-ab76-9f7f1b6728c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3060819527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3060819527
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1290452027
Short name T856
Test name
Test status
Simulation time 3937336421 ps
CPU time 4.48 seconds
Started Jul 14 07:13:58 PM PDT 24
Finished Jul 14 07:14:11 PM PDT 24
Peak memory 207156 kb
Host smart-a9f35693-573f-4b7a-a453-dfab8ef5520e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1290452027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1290452027
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2414428448
Short name T434
Test name
Test status
Simulation time 13386695312 ps
CPU time 12.23 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:30 PM PDT 24
Peak memory 206916 kb
Host smart-bb2be92b-5786-4efa-924f-9e8745845a55
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2414428448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2414428448
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1517657246
Short name T1966
Test name
Test status
Simulation time 23449798552 ps
CPU time 22.49 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:33 PM PDT 24
Peak memory 207096 kb
Host smart-24275839-fd83-4a98-a93c-3a6e1c666a65
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1517657246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1517657246
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2238467015
Short name T493
Test name
Test status
Simulation time 155754531 ps
CPU time 0.8 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206860 kb
Host smart-c7cb0053-9a1c-4bd2-8cb5-f073e57bc2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22384
67015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2238467015
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2793159747
Short name T777
Test name
Test status
Simulation time 149631639 ps
CPU time 0.75 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:14 PM PDT 24
Peak memory 206868 kb
Host smart-810c3fa7-d103-4c7c-8496-80db68ec734b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27931
59747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2793159747
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2510607685
Short name T1781
Test name
Test status
Simulation time 375894636 ps
CPU time 1.18 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:12 PM PDT 24
Peak memory 206836 kb
Host smart-19ea290b-8650-410a-8ba2-9640d0da5838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25106
07685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2510607685
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3141862479
Short name T970
Test name
Test status
Simulation time 524280418 ps
CPU time 1.46 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:13 PM PDT 24
Peak memory 206864 kb
Host smart-5e6098d2-87d6-40f1-84a0-9ac7346dd29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31418
62479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3141862479
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3927876132
Short name T1678
Test name
Test status
Simulation time 17595042204 ps
CPU time 39.9 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:14:56 PM PDT 24
Peak memory 207304 kb
Host smart-93f74ea6-4c31-4523-ac7d-9d529155f07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39278
76132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3927876132
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3253769568
Short name T2389
Test name
Test status
Simulation time 437526385 ps
CPU time 1.44 seconds
Started Jul 14 07:13:58 PM PDT 24
Finished Jul 14 07:14:08 PM PDT 24
Peak memory 206896 kb
Host smart-39190162-9acb-46dc-8039-48a30e0a256d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32537
69568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3253769568
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_enable.753844128
Short name T2638
Test name
Test status
Simulation time 44328367 ps
CPU time 0.66 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206856 kb
Host smart-2b2331e1-be6c-41aa-a2d4-c1caeb1530f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75384
4128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.753844128
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3277043465
Short name T1900
Test name
Test status
Simulation time 961801579 ps
CPU time 2.19 seconds
Started Jul 14 07:14:08 PM PDT 24
Finished Jul 14 07:15:01 PM PDT 24
Peak memory 206956 kb
Host smart-cba85215-46f2-425d-b3fc-a5608eb6dc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32770
43465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3277043465
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1422497548
Short name T2134
Test name
Test status
Simulation time 258194457 ps
CPU time 0.92 seconds
Started Jul 14 07:14:08 PM PDT 24
Finished Jul 14 07:14:50 PM PDT 24
Peak memory 206868 kb
Host smart-7ae81d68-5b3c-4d18-83b4-709da78fe7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
97548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1422497548
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.788343584
Short name T2742
Test name
Test status
Simulation time 153368917 ps
CPU time 0.76 seconds
Started Jul 14 07:14:12 PM PDT 24
Finished Jul 14 07:15:22 PM PDT 24
Peak memory 206872 kb
Host smart-543184e4-aecc-4deb-9337-0be2a787c77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78834
3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.788343584
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3095377001
Short name T631
Test name
Test status
Simulation time 190694934 ps
CPU time 0.83 seconds
Started Jul 14 07:14:08 PM PDT 24
Finished Jul 14 07:14:50 PM PDT 24
Peak memory 207044 kb
Host smart-9ff9a144-607f-470b-be83-8f224c7eda3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30953
77001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3095377001
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.968861988
Short name T92
Test name
Test status
Simulation time 8815053339 ps
CPU time 249.87 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:19:19 PM PDT 24
Peak memory 207108 kb
Host smart-e99c931d-ef1b-499b-b439-f639655939f1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=968861988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.968861988
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1336807710
Short name T718
Test name
Test status
Simulation time 10613292467 ps
CPU time 35.51 seconds
Started Jul 14 07:14:08 PM PDT 24
Finished Jul 14 07:15:24 PM PDT 24
Peak memory 207064 kb
Host smart-4ccbdd66-b3bf-412b-bb42-0e2d4ce3c740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13368
07710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1336807710
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3090687711
Short name T2727
Test name
Test status
Simulation time 163606556 ps
CPU time 0.78 seconds
Started Jul 14 07:14:12 PM PDT 24
Finished Jul 14 07:15:22 PM PDT 24
Peak memory 206776 kb
Host smart-2d1e0bb1-2485-4ff9-976c-f43d94caa226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30906
87711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3090687711
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3998820514
Short name T680
Test name
Test status
Simulation time 23336457828 ps
CPU time 23.85 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:33 PM PDT 24
Peak memory 206932 kb
Host smart-53052024-1122-4e80-8d7b-be16a7c98724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39988
20514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3998820514
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.280936882
Short name T728
Test name
Test status
Simulation time 3333123753 ps
CPU time 3.68 seconds
Started Jul 14 07:14:12 PM PDT 24
Finished Jul 14 07:15:25 PM PDT 24
Peak memory 206856 kb
Host smart-88ada015-3eb3-4c0a-aeba-15f80b1da268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28093
6882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.280936882
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.1970705642
Short name T495
Test name
Test status
Simulation time 12085073164 ps
CPU time 114.07 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:17:27 PM PDT 24
Peak memory 207116 kb
Host smart-2d863bca-e21c-4560-90cf-05936f203eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
05642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.1970705642
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.997968631
Short name T163
Test name
Test status
Simulation time 4786111441 ps
CPU time 133.87 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:17:36 PM PDT 24
Peak memory 207048 kb
Host smart-3b4968df-09e7-4cb4-9a85-d0b62a97bb68
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=997968631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.997968631
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.3635953371
Short name T732
Test name
Test status
Simulation time 245022244 ps
CPU time 0.88 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:37 PM PDT 24
Peak memory 206856 kb
Host smart-54fcc5dd-7a43-4b5e-897c-27b8ec14f06c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3635953371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.3635953371
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.401501121
Short name T2338
Test name
Test status
Simulation time 190995333 ps
CPU time 0.85 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:37 PM PDT 24
Peak memory 206884 kb
Host smart-eadbc18c-d70c-4cda-81c4-f6a3bceb0b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40150
1121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.401501121
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3080309490
Short name T774
Test name
Test status
Simulation time 4146871844 ps
CPU time 106.73 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:16:46 PM PDT 24
Peak memory 207032 kb
Host smart-24f159bb-a641-427a-901d-85f3f7d37815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30803
09490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3080309490
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2776068296
Short name T1650
Test name
Test status
Simulation time 3534181469 ps
CPU time 32.35 seconds
Started Jul 14 07:14:11 PM PDT 24
Finished Jul 14 07:15:50 PM PDT 24
Peak memory 207072 kb
Host smart-bae277bc-2865-4c8f-8f88-6401f3bff133
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2776068296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2776068296
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2640443573
Short name T348
Test name
Test status
Simulation time 167162863 ps
CPU time 0.79 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206848 kb
Host smart-78374e4c-1f96-4357-a0cd-08eb69522c10
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2640443573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2640443573
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.966210806
Short name T1945
Test name
Test status
Simulation time 150369986 ps
CPU time 0.79 seconds
Started Jul 14 07:14:08 PM PDT 24
Finished Jul 14 07:14:59 PM PDT 24
Peak memory 206896 kb
Host smart-5d053b85-4dd6-48f5-a9ba-16b5beaa8673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96621
0806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.966210806
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2967370244
Short name T1169
Test name
Test status
Simulation time 179276922 ps
CPU time 0.83 seconds
Started Jul 14 07:14:19 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206848 kb
Host smart-00546c49-e415-43c7-a67e-a27d248cb900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29673
70244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2967370244
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2135986072
Short name T2368
Test name
Test status
Simulation time 174814166 ps
CPU time 0.76 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206824 kb
Host smart-4f9ef302-db72-4e14-ace2-5ba813d5bd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21359
86072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2135986072
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1025625987
Short name T2201
Test name
Test status
Simulation time 164700650 ps
CPU time 0.79 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:37 PM PDT 24
Peak memory 206832 kb
Host smart-5dd41ee3-3bac-4b85-b420-e8f5037cf9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10256
25987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1025625987
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3513384244
Short name T1412
Test name
Test status
Simulation time 221485364 ps
CPU time 0.93 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:37 PM PDT 24
Peak memory 206876 kb
Host smart-7e8ee7ae-8ad2-48e0-b34b-fb6f695ae5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35133
84244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3513384244
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.2296897191
Short name T2146
Test name
Test status
Simulation time 229799244 ps
CPU time 0.93 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:41 PM PDT 24
Peak memory 206884 kb
Host smart-3d2d0f8d-34ac-4c10-bb40-892131a5df95
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2296897191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.2296897191
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2375430143
Short name T2735
Test name
Test status
Simulation time 213966095 ps
CPU time 0.81 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206836 kb
Host smart-656baf13-6e08-4883-91dc-82290b78129a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754
30143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2375430143
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3200331286
Short name T2069
Test name
Test status
Simulation time 39226547 ps
CPU time 0.62 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:36 PM PDT 24
Peak memory 206864 kb
Host smart-b0b268fe-c9be-4ca5-bd54-8e569ce2243e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32003
31286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3200331286
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1290630347
Short name T2024
Test name
Test status
Simulation time 6895171930 ps
CPU time 16.96 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:15:27 PM PDT 24
Peak memory 207096 kb
Host smart-fbb895d1-efc6-4198-8fc2-c38f1e67babf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12906
30347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1290630347
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1380723364
Short name T874
Test name
Test status
Simulation time 192431242 ps
CPU time 0.84 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206876 kb
Host smart-53de8752-11c1-4e4d-9269-0b947427393f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13807
23364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1380723364
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.28505875
Short name T2350
Test name
Test status
Simulation time 205439750 ps
CPU time 0.83 seconds
Started Jul 14 07:14:19 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206844 kb
Host smart-36868aa5-5613-42a7-868f-d5a2a4f123d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28505
875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.28505875
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2857672586
Short name T1525
Test name
Test status
Simulation time 165287953 ps
CPU time 0.8 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:37 PM PDT 24
Peak memory 206868 kb
Host smart-ff7276ae-43c2-4033-b1b8-9008d23878d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28576
72586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2857672586
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1322279326
Short name T579
Test name
Test status
Simulation time 213478652 ps
CPU time 0.87 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206888 kb
Host smart-65d4d7ce-1f17-485e-b46a-eb0b7699fd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13222
79326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1322279326
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.50893914
Short name T1608
Test name
Test status
Simulation time 180712102 ps
CPU time 0.77 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:15:33 PM PDT 24
Peak memory 206876 kb
Host smart-4a8f404a-1689-4b3e-91fb-bf20c301e2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50893
914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.50893914
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.4287079095
Short name T2636
Test name
Test status
Simulation time 146510790 ps
CPU time 0.76 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206876 kb
Host smart-309a8f63-9d91-4c49-bb88-b858d985fa7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42870
79095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.4287079095
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.325918723
Short name T1735
Test name
Test status
Simulation time 149815952 ps
CPU time 0.76 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:14:36 PM PDT 24
Peak memory 206848 kb
Host smart-06e2190e-9e44-4a63-8bd1-1f24748069b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32591
8723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.325918723
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.487835073
Short name T2014
Test name
Test status
Simulation time 200768608 ps
CPU time 0.85 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206860 kb
Host smart-bdf83e1d-188c-4fb2-a639-d9c3042c8bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48783
5073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.487835073
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2545451726
Short name T1103
Test name
Test status
Simulation time 3820900932 ps
CPU time 106.17 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:16:22 PM PDT 24
Peak memory 207092 kb
Host smart-21dfc00f-42e1-4120-8c57-4b799d015d19
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2545451726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2545451726
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.989335695
Short name T2117
Test name
Test status
Simulation time 184204889 ps
CPU time 0.81 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:15:18 PM PDT 24
Peak memory 206872 kb
Host smart-61ec965a-03bd-4c8a-80fa-072790c037e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98933
5695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.989335695
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1232137854
Short name T834
Test name
Test status
Simulation time 167109903 ps
CPU time 0.76 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:15:18 PM PDT 24
Peak memory 206888 kb
Host smart-1d7c08c4-39c7-4cf8-8e4b-76717fad5f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
37854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1232137854
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.485659478
Short name T920
Test name
Test status
Simulation time 1002604193 ps
CPU time 2.25 seconds
Started Jul 14 07:14:11 PM PDT 24
Finished Jul 14 07:15:20 PM PDT 24
Peak memory 207036 kb
Host smart-715ada66-a3df-463d-bb9b-462bd669caa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48565
9478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.485659478
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1133253722
Short name T1094
Test name
Test status
Simulation time 7437647559 ps
CPU time 198.47 seconds
Started Jul 14 07:14:11 PM PDT 24
Finished Jul 14 07:18:37 PM PDT 24
Peak memory 207048 kb
Host smart-7f2991db-21b1-4298-9ee4-92936b0e429a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332
53722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1133253722
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3339144625
Short name T1467
Test name
Test status
Simulation time 3827141486 ps
CPU time 4.35 seconds
Started Jul 14 07:14:08 PM PDT 24
Finished Jul 14 07:14:53 PM PDT 24
Peak memory 206936 kb
Host smart-02105ac0-f957-4e4f-83cf-d5cb42de9025
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3339144625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3339144625
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2763363235
Short name T2234
Test name
Test status
Simulation time 13331818929 ps
CPU time 14.69 seconds
Started Jul 14 07:14:08 PM PDT 24
Finished Jul 14 07:15:14 PM PDT 24
Peak memory 206940 kb
Host smart-2aac7254-64d6-4606-bb09-84bab0dff537
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2763363235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2763363235
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3520007777
Short name T2722
Test name
Test status
Simulation time 23383241410 ps
CPU time 26.28 seconds
Started Jul 14 07:14:07 PM PDT 24
Finished Jul 14 07:15:02 PM PDT 24
Peak memory 206924 kb
Host smart-9856157a-85b0-4e1c-a80e-5859168d1cbb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3520007777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3520007777
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2690871970
Short name T2005
Test name
Test status
Simulation time 143412986 ps
CPU time 0.76 seconds
Started Jul 14 07:14:10 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206860 kb
Host smart-37ae0dfb-541f-4523-b25a-92d4d5d34c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26908
71970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2690871970
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.4108574717
Short name T773
Test name
Test status
Simulation time 169196678 ps
CPU time 0.81 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206884 kb
Host smart-9cbe848e-ef50-43c0-bc29-27491c647970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085
74717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.4108574717
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.188481756
Short name T966
Test name
Test status
Simulation time 580487196 ps
CPU time 1.67 seconds
Started Jul 14 07:14:19 PM PDT 24
Finished Jul 14 07:16:25 PM PDT 24
Peak memory 207048 kb
Host smart-1e5cc244-3be9-4279-9b48-db8311aeb7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18848
1756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.188481756
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.866983952
Short name T1791
Test name
Test status
Simulation time 680964762 ps
CPU time 1.5 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:01 PM PDT 24
Peak memory 206948 kb
Host smart-6e8a9767-02ce-4025-a207-f0a4f792bc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86698
3952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.866983952
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3796529688
Short name T177
Test name
Test status
Simulation time 10289668166 ps
CPU time 18.63 seconds
Started Jul 14 07:14:08 PM PDT 24
Finished Jul 14 07:15:07 PM PDT 24
Peak memory 207016 kb
Host smart-151407bc-9325-41b4-8c2d-d5e59e5cfdd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
29688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3796529688
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1429741818
Short name T2080
Test name
Test status
Simulation time 373873327 ps
CPU time 1.13 seconds
Started Jul 14 07:14:12 PM PDT 24
Finished Jul 14 07:15:23 PM PDT 24
Peak memory 206868 kb
Host smart-1566ec98-acbc-4df0-9b5d-aa19eee1dc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14297
41818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1429741818
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1435309523
Short name T2646
Test name
Test status
Simulation time 165645252 ps
CPU time 0.78 seconds
Started Jul 14 07:14:11 PM PDT 24
Finished Jul 14 07:15:18 PM PDT 24
Peak memory 206872 kb
Host smart-971f129e-85cb-4cd5-950a-2e52d1c9cf35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
09523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1435309523
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2883820983
Short name T1620
Test name
Test status
Simulation time 61982736 ps
CPU time 0.67 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206832 kb
Host smart-8f20af60-8fac-4bf5-9fd1-7ef5bed655c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28838
20983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2883820983
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1781108875
Short name T1210
Test name
Test status
Simulation time 879641636 ps
CPU time 2.27 seconds
Started Jul 14 07:14:16 PM PDT 24
Finished Jul 14 07:16:07 PM PDT 24
Peak memory 207036 kb
Host smart-11d4b331-c1bc-4d34-b05e-1143ae474714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17811
08875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1781108875
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3802070659
Short name T506
Test name
Test status
Simulation time 432528527 ps
CPU time 2.64 seconds
Started Jul 14 07:14:17 PM PDT 24
Finished Jul 14 07:16:00 PM PDT 24
Peak memory 207048 kb
Host smart-7ab8ee59-bf74-43c0-8d79-c04c52ff2bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38020
70659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3802070659
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1517962622
Short name T1648
Test name
Test status
Simulation time 194412548 ps
CPU time 0.87 seconds
Started Jul 14 07:14:17 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206856 kb
Host smart-f16cdaed-b215-49e8-8369-d50859b7121d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15179
62622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1517962622
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.502528901
Short name T2284
Test name
Test status
Simulation time 193536580 ps
CPU time 0.79 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 206856 kb
Host smart-cd1233c8-ab6f-42f6-8c34-6e131a43bd6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50252
8901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.502528901
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.23939282
Short name T599
Test name
Test status
Simulation time 252315657 ps
CPU time 0.95 seconds
Started Jul 14 07:14:17 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206872 kb
Host smart-82dcc08e-c3ee-4cbb-8a28-edf77d910a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23939
282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.23939282
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.1546205794
Short name T1543
Test name
Test status
Simulation time 4820495636 ps
CPU time 39.36 seconds
Started Jul 14 07:14:12 PM PDT 24
Finished Jul 14 07:16:01 PM PDT 24
Peak memory 207148 kb
Host smart-480078c7-4fa8-48a2-95ba-27338a90814f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15462
05794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.1546205794
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.355231593
Short name T480
Test name
Test status
Simulation time 172564746 ps
CPU time 0.77 seconds
Started Jul 14 07:14:17 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206876 kb
Host smart-6af46671-952f-4229-8b80-37c6dacedc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35523
1593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.355231593
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3926532563
Short name T1303
Test name
Test status
Simulation time 23342815080 ps
CPU time 24.28 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:27 PM PDT 24
Peak memory 206144 kb
Host smart-9ad776e9-0d16-458e-a327-ee34fb5070b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
32563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3926532563
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2890670015
Short name T1064
Test name
Test status
Simulation time 3328516316 ps
CPU time 3.5 seconds
Started Jul 14 07:14:12 PM PDT 24
Finished Jul 14 07:15:25 PM PDT 24
Peak memory 206952 kb
Host smart-eed53a7b-ec33-4adb-9007-d04e9b7497fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28906
70015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2890670015
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2798694032
Short name T2538
Test name
Test status
Simulation time 11533985217 ps
CPU time 105.8 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:17:18 PM PDT 24
Peak memory 207144 kb
Host smart-c869da0b-3f8e-4fd6-a505-24b2782218bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27986
94032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2798694032
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.1856574553
Short name T1548
Test name
Test status
Simulation time 6967991997 ps
CPU time 62.23 seconds
Started Jul 14 07:14:15 PM PDT 24
Finished Jul 14 07:16:39 PM PDT 24
Peak memory 207056 kb
Host smart-4db7b588-021d-42b5-870e-65553ff25a6e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1856574553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.1856574553
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1068144097
Short name T2158
Test name
Test status
Simulation time 233345423 ps
CPU time 0.94 seconds
Started Jul 14 07:14:18 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206876 kb
Host smart-1204f880-3e06-4f26-b679-f2acd08dcd35
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1068144097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1068144097
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2416841519
Short name T1579
Test name
Test status
Simulation time 188318451 ps
CPU time 0.87 seconds
Started Jul 14 07:14:18 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206860 kb
Host smart-230b0163-0871-49e5-91ae-dc6552579483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24168
41519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2416841519
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1932450399
Short name T881
Test name
Test status
Simulation time 3466397304 ps
CPU time 23 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:15:55 PM PDT 24
Peak memory 207128 kb
Host smart-ac6b60c8-faf7-4f76-b9ae-7c65453c539a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19324
50399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1932450399
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.542205656
Short name T1053
Test name
Test status
Simulation time 3177655780 ps
CPU time 87.36 seconds
Started Jul 14 07:14:15 PM PDT 24
Finished Jul 14 07:17:00 PM PDT 24
Peak memory 207104 kb
Host smart-31a10b18-f2a2-4410-948c-e651e4c21b3b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=542205656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.542205656
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3407946285
Short name T1420
Test name
Test status
Simulation time 149546859 ps
CPU time 0.78 seconds
Started Jul 14 07:14:18 PM PDT 24
Finished Jul 14 07:16:33 PM PDT 24
Peak memory 206864 kb
Host smart-c9980727-5ee8-4987-8e4a-ffec8b448aa2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3407946285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3407946285
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1233637682
Short name T308
Test name
Test status
Simulation time 148366483 ps
CPU time 0.78 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:15:23 PM PDT 24
Peak memory 206888 kb
Host smart-23e58fc8-23a5-4e31-9006-d7f95a6e59e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12336
37682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1233637682
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1675715483
Short name T1269
Test name
Test status
Simulation time 179766748 ps
CPU time 0.81 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:17:01 PM PDT 24
Peak memory 206904 kb
Host smart-59eca5cf-a969-41d7-aa90-92131928cb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16757
15483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1675715483
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1723960160
Short name T2345
Test name
Test status
Simulation time 179193673 ps
CPU time 0.86 seconds
Started Jul 14 07:14:17 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206872 kb
Host smart-0be9c1d4-c29d-4588-ac4d-6f0b3e889983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17239
60160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1723960160
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1167895269
Short name T397
Test name
Test status
Simulation time 156020411 ps
CPU time 0.77 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:15:23 PM PDT 24
Peak memory 206836 kb
Host smart-5b2ce823-f6e6-4291-bbc4-bb9cbd9d2cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11678
95269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1167895269
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.4049538124
Short name T1444
Test name
Test status
Simulation time 154997760 ps
CPU time 0.79 seconds
Started Jul 14 07:14:16 PM PDT 24
Finished Jul 14 07:16:03 PM PDT 24
Peak memory 206860 kb
Host smart-856531ce-32c7-4e84-bd97-39c71903c649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40495
38124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.4049538124
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.264875316
Short name T1261
Test name
Test status
Simulation time 197759733 ps
CPU time 0.95 seconds
Started Jul 14 07:14:15 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206812 kb
Host smart-b80bcf61-5890-4acc-9f6f-b7e29454009b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=264875316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.264875316
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.4244277809
Short name T1395
Test name
Test status
Simulation time 174802451 ps
CPU time 0.8 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206856 kb
Host smart-900f33ce-e22a-4103-9143-8735bd4fa031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42442
77809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.4244277809
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3772335868
Short name T1886
Test name
Test status
Simulation time 39955536 ps
CPU time 0.69 seconds
Started Jul 14 07:14:15 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206820 kb
Host smart-ce4c13fc-5148-4f22-b01b-013d5410a1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37723
35868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3772335868
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.526218424
Short name T2580
Test name
Test status
Simulation time 17641918639 ps
CPU time 37.86 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:16:10 PM PDT 24
Peak memory 207160 kb
Host smart-e4e604cf-a1fe-41cf-b6a5-1a0435b8ad1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52621
8424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.526218424
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.4085590742
Short name T1765
Test name
Test status
Simulation time 153411708 ps
CPU time 0.77 seconds
Started Jul 14 07:14:22 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206856 kb
Host smart-c05fe8ca-8ed8-4488-9c98-1b838d242ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40855
90742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.4085590742
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2951946348
Short name T1810
Test name
Test status
Simulation time 162455520 ps
CPU time 0.77 seconds
Started Jul 14 07:14:18 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206888 kb
Host smart-1e31a6d6-235d-4ce4-9530-a5b929595fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29519
46348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2951946348
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.861446864
Short name T1818
Test name
Test status
Simulation time 207589974 ps
CPU time 0.83 seconds
Started Jul 14 07:14:12 PM PDT 24
Finished Jul 14 07:15:23 PM PDT 24
Peak memory 206860 kb
Host smart-a5b325cc-958c-4906-b727-14b91e2f73b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86144
6864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.861446864
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1728587451
Short name T1891
Test name
Test status
Simulation time 166802691 ps
CPU time 0.79 seconds
Started Jul 14 07:14:18 PM PDT 24
Finished Jul 14 07:16:03 PM PDT 24
Peak memory 206852 kb
Host smart-ef815b48-40cd-41f7-895e-b577179478f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17285
87451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1728587451
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1605167903
Short name T1517
Test name
Test status
Simulation time 142923021 ps
CPU time 0.78 seconds
Started Jul 14 07:14:17 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206852 kb
Host smart-5a2e0147-443d-448c-b6c4-a4af80f8743a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16051
67903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1605167903
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1486291694
Short name T2525
Test name
Test status
Simulation time 153126463 ps
CPU time 0.77 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206180 kb
Host smart-f156a315-6a78-475a-a5df-6f28ee2a97f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14862
91694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1486291694
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2497677779
Short name T1985
Test name
Test status
Simulation time 182107705 ps
CPU time 0.78 seconds
Started Jul 14 07:14:15 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206864 kb
Host smart-8cb95ffc-3ec0-4d66-8d74-fb498c91cc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976
77779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2497677779
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2401468803
Short name T2607
Test name
Test status
Simulation time 201561320 ps
CPU time 0.91 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206860 kb
Host smart-cff67417-d361-4e41-8004-ab478a3d44bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
68803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2401468803
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3669553375
Short name T1534
Test name
Test status
Simulation time 4949290495 ps
CPU time 132.89 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:18:11 PM PDT 24
Peak memory 207076 kb
Host smart-d866f063-77eb-4d12-892a-d2966456863d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3669553375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3669553375
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.673421465
Short name T1050
Test name
Test status
Simulation time 159483680 ps
CPU time 0.78 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 206864 kb
Host smart-badafd63-5d4b-4aac-963b-9985aaf0e23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67342
1465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.673421465
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.326012568
Short name T2302
Test name
Test status
Simulation time 144173215 ps
CPU time 0.77 seconds
Started Jul 14 07:14:13 PM PDT 24
Finished Jul 14 07:15:33 PM PDT 24
Peak memory 206872 kb
Host smart-907c3fc7-c9ac-43a5-be79-9a2e950644af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32601
2568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.326012568
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.625594662
Short name T2279
Test name
Test status
Simulation time 994939329 ps
CPU time 2.35 seconds
Started Jul 14 07:14:17 PM PDT 24
Finished Jul 14 07:16:05 PM PDT 24
Peak memory 207052 kb
Host smart-dff0a018-027d-4817-b535-4cd1e63fc243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62559
4662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.625594662
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2392532835
Short name T1313
Test name
Test status
Simulation time 7744763157 ps
CPU time 214.41 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:19:53 PM PDT 24
Peak memory 207076 kb
Host smart-1215625d-503e-4bc6-af8f-90c46b1bfad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23925
32835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2392532835
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.1210105447
Short name T2576
Test name
Test status
Simulation time 45654621 ps
CPU time 0.65 seconds
Started Jul 14 07:14:27 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206912 kb
Host smart-79468a1b-aaae-43ce-9305-d3b02c821073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1210105447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.1210105447
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.496673089
Short name T1785
Test name
Test status
Simulation time 4121217038 ps
CPU time 4.5 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:15:37 PM PDT 24
Peak memory 206956 kb
Host smart-1202e9da-f838-462f-bfa3-cd280d6ae166
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=496673089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.496673089
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2864678012
Short name T2235
Test name
Test status
Simulation time 13383034563 ps
CPU time 15.46 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:15:48 PM PDT 24
Peak memory 206952 kb
Host smart-fae09b19-4ecc-4cd6-b368-7994e4da8c2b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2864678012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2864678012
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2215333277
Short name T219
Test name
Test status
Simulation time 23382430878 ps
CPU time 22.78 seconds
Started Jul 14 07:14:15 PM PDT 24
Finished Jul 14 07:15:56 PM PDT 24
Peak memory 207156 kb
Host smart-b17557c2-874f-46fa-843c-2472b41effef
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2215333277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2215333277
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3394319626
Short name T2150
Test name
Test status
Simulation time 186864322 ps
CPU time 0.85 seconds
Started Jul 14 07:14:18 PM PDT 24
Finished Jul 14 07:16:33 PM PDT 24
Peak memory 206848 kb
Host smart-07cfff6d-b6fa-4b53-8613-ec168606c315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
19626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3394319626
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1366367813
Short name T1660
Test name
Test status
Simulation time 178059760 ps
CPU time 0.82 seconds
Started Jul 14 07:14:14 PM PDT 24
Finished Jul 14 07:15:34 PM PDT 24
Peak memory 206856 kb
Host smart-d85aeae6-c82f-49ab-b985-0248fa13d950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13663
67813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1366367813
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3441979606
Short name T1151
Test name
Test status
Simulation time 260751454 ps
CPU time 1.05 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:17:01 PM PDT 24
Peak memory 206864 kb
Host smart-4b6634ce-37f0-496c-b694-2c6d2c4b0f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34419
79606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3441979606
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3509443625
Short name T2097
Test name
Test status
Simulation time 757607733 ps
CPU time 1.72 seconds
Started Jul 14 07:14:17 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 207008 kb
Host smart-b731079a-00b4-490b-bdc6-996e2866ab40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35094
43625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3509443625
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3229150619
Short name T1986
Test name
Test status
Simulation time 17941613382 ps
CPU time 35.44 seconds
Started Jul 14 07:14:16 PM PDT 24
Finished Jul 14 07:16:38 PM PDT 24
Peak memory 207024 kb
Host smart-d4de1144-ce47-4e3b-8640-337475d10dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32291
50619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3229150619
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3619189438
Short name T703
Test name
Test status
Simulation time 385380146 ps
CPU time 1.22 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:16:20 PM PDT 24
Peak memory 206872 kb
Host smart-de5bef39-3dec-4b4b-83cc-1203372b31cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36191
89438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3619189438
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.639913653
Short name T1401
Test name
Test status
Simulation time 141903157 ps
CPU time 0.72 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206884 kb
Host smart-44b3c3a7-4026-4eeb-851b-914c48455779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63991
3653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.639913653
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2120402734
Short name T1604
Test name
Test status
Simulation time 35697712 ps
CPU time 0.64 seconds
Started Jul 14 07:14:19 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206796 kb
Host smart-844b07e7-3b67-43c6-a41a-a30fdfd853c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21204
02734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2120402734
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3629836054
Short name T1056
Test name
Test status
Simulation time 994426451 ps
CPU time 2.16 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:20 PM PDT 24
Peak memory 207024 kb
Host smart-ffd9c93d-3317-499c-ac19-b23ef42aaad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36298
36054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3629836054
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3636898107
Short name T2119
Test name
Test status
Simulation time 196151900 ps
CPU time 1.93 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:20 PM PDT 24
Peak memory 207024 kb
Host smart-33ab8eac-7868-4328-8f4d-9b8cf23ee121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368
98107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3636898107
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.4223565257
Short name T818
Test name
Test status
Simulation time 255697382 ps
CPU time 0.87 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 206876 kb
Host smart-bf1c9da0-5ae3-4beb-a96f-a3b3b5973421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42235
65257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.4223565257
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.227133476
Short name T490
Test name
Test status
Simulation time 200186506 ps
CPU time 0.77 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 206876 kb
Host smart-95910eff-733a-434c-ad13-9d7928909486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713
3476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.227133476
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.997797711
Short name T786
Test name
Test status
Simulation time 163329999 ps
CPU time 0.82 seconds
Started Jul 14 07:14:26 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206840 kb
Host smart-f7b2db1c-736a-4784-b30a-f81d9357e176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99779
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.997797711
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.3030671052
Short name T1806
Test name
Test status
Simulation time 7074889950 ps
CPU time 26.67 seconds
Started Jul 14 07:14:24 PM PDT 24
Finished Jul 14 07:17:27 PM PDT 24
Peak memory 207100 kb
Host smart-30437f69-f09d-43fe-b631-78ccb7f067b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30306
71052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.3030671052
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2308610656
Short name T2023
Test name
Test status
Simulation time 168122889 ps
CPU time 0.79 seconds
Started Jul 14 07:14:21 PM PDT 24
Finished Jul 14 07:16:09 PM PDT 24
Peak memory 206824 kb
Host smart-75b3477d-fb46-4ad4-9ca6-34927b120981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
10656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2308610656
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.997729385
Short name T2224
Test name
Test status
Simulation time 23318209327 ps
CPU time 22.84 seconds
Started Jul 14 07:14:22 PM PDT 24
Finished Jul 14 07:16:41 PM PDT 24
Peak memory 206896 kb
Host smart-23bcaba9-bc56-4b7b-9613-d2a60515b89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99772
9385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.997729385
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1219149027
Short name T690
Test name
Test status
Simulation time 3326421680 ps
CPU time 3.67 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:22 PM PDT 24
Peak memory 206932 kb
Host smart-af589dd7-3061-47cc-b8ec-445d1b4cc7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
49027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1219149027
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.3508643516
Short name T2171
Test name
Test status
Simulation time 13994303903 ps
CPU time 124.33 seconds
Started Jul 14 07:14:24 PM PDT 24
Finished Jul 14 07:18:41 PM PDT 24
Peak memory 207136 kb
Host smart-520dfc54-d21d-42d9-b71d-2402044bdf00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35086
43516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.3508643516
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2763009999
Short name T386
Test name
Test status
Simulation time 7817521093 ps
CPU time 52.15 seconds
Started Jul 14 07:14:21 PM PDT 24
Finished Jul 14 07:16:55 PM PDT 24
Peak memory 207092 kb
Host smart-738180a0-fa50-431d-9397-cea69149a799
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2763009999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2763009999
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.159571304
Short name T447
Test name
Test status
Simulation time 245749012 ps
CPU time 0.9 seconds
Started Jul 14 07:14:19 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206876 kb
Host smart-601adb8b-5628-4514-a617-b4b392658fef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=159571304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.159571304
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3781925765
Short name T2058
Test name
Test status
Simulation time 189998005 ps
CPU time 0.83 seconds
Started Jul 14 07:14:22 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206876 kb
Host smart-e65cfcca-8183-4d50-bcb1-0d1c4e05b72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37819
25765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3781925765
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1655931581
Short name T2161
Test name
Test status
Simulation time 4064316695 ps
CPU time 36.83 seconds
Started Jul 14 07:14:21 PM PDT 24
Finished Jul 14 07:16:40 PM PDT 24
Peak memory 207092 kb
Host smart-5b892c87-3874-4f8d-8fbd-88a3e88efeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
31581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1655931581
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1127772277
Short name T457
Test name
Test status
Simulation time 4779069197 ps
CPU time 45.34 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:17:46 PM PDT 24
Peak memory 207108 kb
Host smart-03c0a892-8274-4728-89fe-cbab198c8ce2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1127772277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1127772277
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.571322784
Short name T1464
Test name
Test status
Simulation time 147796034 ps
CPU time 0.79 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:09 PM PDT 24
Peak memory 206888 kb
Host smart-fa4105e1-b512-4696-a325-d9c70a0b1587
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=571322784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.571322784
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3905953560
Short name T2175
Test name
Test status
Simulation time 143040659 ps
CPU time 0.77 seconds
Started Jul 14 07:14:22 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206880 kb
Host smart-42390423-9f96-4678-ae3e-22ef708412be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39059
53560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3905953560
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3865074032
Short name T118
Test name
Test status
Simulation time 215597594 ps
CPU time 0.9 seconds
Started Jul 14 07:14:24 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 206840 kb
Host smart-5911d7b5-6d22-4aba-91ec-6b3231413213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650
74032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3865074032
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2976539545
Short name T750
Test name
Test status
Simulation time 146620860 ps
CPU time 0.8 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 206872 kb
Host smart-31486d31-2f63-4b4f-bfff-abfdbb4a2a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29765
39545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2976539545
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1863723426
Short name T551
Test name
Test status
Simulation time 185806542 ps
CPU time 0.78 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 206848 kb
Host smart-2e2c547d-7c72-4b58-b4bb-ffa25e1e66d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18637
23426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1863723426
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2079321639
Short name T1312
Test name
Test status
Simulation time 158232707 ps
CPU time 0.77 seconds
Started Jul 14 07:14:21 PM PDT 24
Finished Jul 14 07:16:09 PM PDT 24
Peak memory 206900 kb
Host smart-2f3f2893-5f72-4ec0-86e7-423d712a5852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20793
21639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2079321639
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1062064982
Short name T907
Test name
Test status
Simulation time 241126994 ps
CPU time 0.82 seconds
Started Jul 14 07:14:21 PM PDT 24
Finished Jul 14 07:16:09 PM PDT 24
Peak memory 206860 kb
Host smart-fe7e01d3-88ae-447d-a20d-e923791bbfce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10620
64982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1062064982
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3514147198
Short name T1147
Test name
Test status
Simulation time 245131525 ps
CPU time 0.95 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:09 PM PDT 24
Peak memory 206860 kb
Host smart-0edb5d89-6a87-4763-814f-16ab695f195d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3514147198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3514147198
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.512657475
Short name T2391
Test name
Test status
Simulation time 181741127 ps
CPU time 0.75 seconds
Started Jul 14 07:14:22 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206876 kb
Host smart-ef46205b-0cac-45f6-a7c3-b5a4bd0c33df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51265
7475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.512657475
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2288944924
Short name T2299
Test name
Test status
Simulation time 45628217 ps
CPU time 0.63 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:38 PM PDT 24
Peak memory 206876 kb
Host smart-027ed732-8d15-4d76-ba73-be593a5281fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22889
44924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2288944924
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1249067326
Short name T1445
Test name
Test status
Simulation time 8714233388 ps
CPU time 18.09 seconds
Started Jul 14 07:14:24 PM PDT 24
Finished Jul 14 07:16:55 PM PDT 24
Peak memory 207156 kb
Host smart-0735c4fb-4ed1-48d5-ab33-059e8b6b81f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12490
67326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1249067326
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3395651678
Short name T1071
Test name
Test status
Simulation time 153585862 ps
CPU time 0.78 seconds
Started Jul 14 07:14:20 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206876 kb
Host smart-159813c0-4aa3-4206-9c04-41e628115c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33956
51678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3395651678
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2872370697
Short name T1017
Test name
Test status
Simulation time 196510948 ps
CPU time 0.78 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 206868 kb
Host smart-84166a7e-ad81-478b-8f86-9c118f93af55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28723
70697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2872370697
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2123874973
Short name T1820
Test name
Test status
Simulation time 243837871 ps
CPU time 0.91 seconds
Started Jul 14 07:14:21 PM PDT 24
Finished Jul 14 07:16:09 PM PDT 24
Peak memory 206828 kb
Host smart-3db732f2-09f9-46d0-ad99-c78d659e0c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21238
74973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2123874973
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1952824229
Short name T2473
Test name
Test status
Simulation time 180703717 ps
CPU time 0.79 seconds
Started Jul 14 07:14:21 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206824 kb
Host smart-25974296-2085-44e0-8537-b1755fa324a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
24229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1952824229
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3817617484
Short name T2131
Test name
Test status
Simulation time 145125819 ps
CPU time 0.74 seconds
Started Jul 14 07:14:22 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206868 kb
Host smart-b89b20a7-e0ba-4601-a205-431c912247a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
17484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3817617484
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3961786441
Short name T1006
Test name
Test status
Simulation time 201413905 ps
CPU time 0.84 seconds
Started Jul 14 07:14:23 PM PDT 24
Finished Jul 14 07:17:01 PM PDT 24
Peak memory 206852 kb
Host smart-10b122a2-2cf1-4c63-9fac-17e65defe82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617
86441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3961786441
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.967041177
Short name T1192
Test name
Test status
Simulation time 194482312 ps
CPU time 0.8 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:10 PM PDT 24
Peak memory 206840 kb
Host smart-a8b6bace-31c4-4889-8c31-f49085fd4477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96704
1177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.967041177
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1445435235
Short name T787
Test name
Test status
Simulation time 206097547 ps
CPU time 0.92 seconds
Started Jul 14 07:14:31 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206880 kb
Host smart-8d5e4789-b697-44f3-9a3a-267486a57836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14454
35235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1445435235
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.802784354
Short name T2353
Test name
Test status
Simulation time 5589231508 ps
CPU time 147.74 seconds
Started Jul 14 07:14:24 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 207120 kb
Host smart-4a866d8c-b56c-4bfb-98d1-d1a75c0b3613
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=802784354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.802784354
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3387701788
Short name T1921
Test name
Test status
Simulation time 219421589 ps
CPU time 0.8 seconds
Started Jul 14 07:14:27 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206888 kb
Host smart-441671c0-fb0a-458f-8d99-47f27f80c94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33877
01788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3387701788
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1746886596
Short name T1283
Test name
Test status
Simulation time 190093942 ps
CPU time 0.81 seconds
Started Jul 14 07:14:27 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206844 kb
Host smart-f5f8f9dd-c10f-4d38-8739-579c83cee567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17468
86596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1746886596
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3837585568
Short name T1853
Test name
Test status
Simulation time 389291595 ps
CPU time 1.14 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:10 PM PDT 24
Peak memory 206880 kb
Host smart-c98a6c7f-e62f-4636-af33-8b11c40f7ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38375
85568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3837585568
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1226953117
Short name T2276
Test name
Test status
Simulation time 7847101470 ps
CPU time 222.61 seconds
Started Jul 14 07:14:25 PM PDT 24
Finished Jul 14 07:19:41 PM PDT 24
Peak memory 207100 kb
Host smart-0c006c2d-b19f-43c0-b1fd-9fdfece604b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12269
53117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1226953117
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.604315637
Short name T2731
Test name
Test status
Simulation time 42255658 ps
CPU time 0.67 seconds
Started Jul 14 07:14:38 PM PDT 24
Finished Jul 14 07:17:02 PM PDT 24
Peak memory 206940 kb
Host smart-6646fbbb-1c14-49ba-bc58-09895a417f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=604315637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.604315637
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.4242774454
Short name T1675
Test name
Test status
Simulation time 4141186355 ps
CPU time 4.59 seconds
Started Jul 14 07:14:33 PM PDT 24
Finished Jul 14 07:16:53 PM PDT 24
Peak memory 206912 kb
Host smart-f1122e6a-83f0-4045-af5d-ab36c7a729ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4242774454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.4242774454
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3904140639
Short name T2116
Test name
Test status
Simulation time 13359314900 ps
CPU time 14.08 seconds
Started Jul 14 07:14:25 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 207000 kb
Host smart-7626f833-719b-4bc4-879a-5366835ebe79
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3904140639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3904140639
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2699312321
Short name T700
Test name
Test status
Simulation time 23364320609 ps
CPU time 26.52 seconds
Started Jul 14 07:14:27 PM PDT 24
Finished Jul 14 07:16:30 PM PDT 24
Peak memory 207128 kb
Host smart-8140ed28-e29a-4b39-8e4d-82c227311e62
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2699312321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.2699312321
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.4019804700
Short name T2029
Test name
Test status
Simulation time 206037447 ps
CPU time 0.81 seconds
Started Jul 14 07:14:29 PM PDT 24
Finished Jul 14 07:16:37 PM PDT 24
Peak memory 206860 kb
Host smart-2d3878e1-085b-4695-a087-2e06c24cf6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198
04700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.4019804700
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2283069662
Short name T2128
Test name
Test status
Simulation time 158858634 ps
CPU time 0.77 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:10 PM PDT 24
Peak memory 206840 kb
Host smart-292a4a9f-1bbf-4813-96bf-a029909b9d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22830
69662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2283069662
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2767077732
Short name T2328
Test name
Test status
Simulation time 487390563 ps
CPU time 1.46 seconds
Started Jul 14 07:14:25 PM PDT 24
Finished Jul 14 07:16:37 PM PDT 24
Peak memory 207236 kb
Host smart-eababdae-f849-4a09-8d95-f93c257f14c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27670
77732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2767077732
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3868163218
Short name T1434
Test name
Test status
Simulation time 755843544 ps
CPU time 1.66 seconds
Started Jul 14 07:14:31 PM PDT 24
Finished Jul 14 07:16:39 PM PDT 24
Peak memory 207084 kb
Host smart-acdb7614-9976-47aa-b359-f651c3c56c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38681
63218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3868163218
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.4180861671
Short name T184
Test name
Test status
Simulation time 10968514493 ps
CPU time 19.91 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:29 PM PDT 24
Peak memory 207096 kb
Host smart-ac37aa9b-c9ea-4100-b081-154558f55c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41808
61671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.4180861671
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2109261059
Short name T392
Test name
Test status
Simulation time 337553032 ps
CPU time 1.03 seconds
Started Jul 14 07:14:26 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206892 kb
Host smart-abd93271-128a-4438-a85f-bdb31d18528e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21092
61059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2109261059
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1651235714
Short name T1776
Test name
Test status
Simulation time 152588599 ps
CPU time 0.77 seconds
Started Jul 14 07:14:30 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206856 kb
Host smart-675fbccd-8eca-4d62-a27d-4ecbc2ba3773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16512
35714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1651235714
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.3889014322
Short name T1425
Test name
Test status
Simulation time 43682439 ps
CPU time 0.65 seconds
Started Jul 14 07:14:26 PM PDT 24
Finished Jul 14 07:16:04 PM PDT 24
Peak memory 206836 kb
Host smart-b9120876-23bf-4e73-9ec0-07ef38f2584f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38890
14322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3889014322
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1957016511
Short name T2052
Test name
Test status
Simulation time 1012814494 ps
CPU time 2.19 seconds
Started Jul 14 07:14:26 PM PDT 24
Finished Jul 14 07:16:06 PM PDT 24
Peak memory 207092 kb
Host smart-92c38ea2-e22b-4eaf-94be-605016eb7489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19570
16511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1957016511
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.609921798
Short name T2530
Test name
Test status
Simulation time 190989534 ps
CPU time 1.85 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:11 PM PDT 24
Peak memory 207076 kb
Host smart-a50ae2a7-27a6-4e4d-8565-46786a82724f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60992
1798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.609921798
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4135262704
Short name T1428
Test name
Test status
Simulation time 192345084 ps
CPU time 0.83 seconds
Started Jul 14 07:14:31 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206884 kb
Host smart-a7c128ca-24bf-4546-baa4-a90e99bc707a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41352
62704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4135262704
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2074072098
Short name T1195
Test name
Test status
Simulation time 165352834 ps
CPU time 0.72 seconds
Started Jul 14 07:14:26 PM PDT 24
Finished Jul 14 07:17:01 PM PDT 24
Peak memory 206892 kb
Host smart-acbbba0c-1857-429d-81ce-065c88679085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20740
72098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2074072098
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2354514089
Short name T890
Test name
Test status
Simulation time 247079081 ps
CPU time 0.88 seconds
Started Jul 14 07:14:24 PM PDT 24
Finished Jul 14 07:15:59 PM PDT 24
Peak memory 206828 kb
Host smart-65f7f4e4-475d-408e-8ee0-ad0f7bc924c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23545
14089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2354514089
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.2681217342
Short name T1319
Test name
Test status
Simulation time 6235907766 ps
CPU time 53.91 seconds
Started Jul 14 07:14:31 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 207068 kb
Host smart-73b15d25-ee83-40f2-9f46-bfdc34c43f3d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2681217342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.2681217342
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.3699353991
Short name T2111
Test name
Test status
Simulation time 7700243988 ps
CPU time 28.23 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:32 PM PDT 24
Peak memory 207068 kb
Host smart-e8835970-80e2-4c32-bdeb-8cf63fbe3949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
53991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3699353991
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3231943913
Short name T1570
Test name
Test status
Simulation time 237816240 ps
CPU time 0.85 seconds
Started Jul 14 07:14:28 PM PDT 24
Finished Jul 14 07:16:10 PM PDT 24
Peak memory 206872 kb
Host smart-2c77edf4-7b2e-4ab8-bf10-f9bac40c8d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32319
43913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3231943913
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3908309182
Short name T41
Test name
Test status
Simulation time 23356174866 ps
CPU time 27.54 seconds
Started Jul 14 07:14:26 PM PDT 24
Finished Jul 14 07:16:31 PM PDT 24
Peak memory 206936 kb
Host smart-cd3dffff-2c41-49ff-b6b0-b463594ce449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39083
09182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3908309182
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.262281264
Short name T2047
Test name
Test status
Simulation time 3266284425 ps
CPU time 3.87 seconds
Started Jul 14 07:14:46 PM PDT 24
Finished Jul 14 07:17:15 PM PDT 24
Peak memory 206920 kb
Host smart-83d8584c-2368-476d-b0d0-515a9c658484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26228
1264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.262281264
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.782253739
Short name T585
Test name
Test status
Simulation time 11306889154 ps
CPU time 78.66 seconds
Started Jul 14 07:14:41 PM PDT 24
Finished Jul 14 07:18:21 PM PDT 24
Peak memory 207156 kb
Host smart-366d7341-f7a9-4b97-b48b-460905e47f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78225
3739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.782253739
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1610483776
Short name T1422
Test name
Test status
Simulation time 5135666214 ps
CPU time 138.34 seconds
Started Jul 14 07:14:33 PM PDT 24
Finished Jul 14 07:19:07 PM PDT 24
Peak memory 207092 kb
Host smart-b4d896c3-eae0-49ed-9cce-c600027cd9ce
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1610483776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1610483776
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1998897143
Short name T1984
Test name
Test status
Simulation time 253309249 ps
CPU time 0.89 seconds
Started Jul 14 07:14:31 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206872 kb
Host smart-ae547b71-ccfd-4223-9293-f4478015da7b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1998897143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1998897143
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2149963021
Short name T383
Test name
Test status
Simulation time 216128347 ps
CPU time 0.9 seconds
Started Jul 14 07:14:33 PM PDT 24
Finished Jul 14 07:17:02 PM PDT 24
Peak memory 206896 kb
Host smart-519462b7-b6e6-4d44-bf4a-ba5dadc3ebdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21499
63021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2149963021
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.4105446374
Short name T2037
Test name
Test status
Simulation time 3165431849 ps
CPU time 83.77 seconds
Started Jul 14 07:14:36 PM PDT 24
Finished Jul 14 07:18:13 PM PDT 24
Peak memory 207104 kb
Host smart-b8909c7e-30b1-4c11-91c1-84f5a94a3392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41054
46374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.4105446374
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.486837320
Short name T2311
Test name
Test status
Simulation time 2863444413 ps
CPU time 20.02 seconds
Started Jul 14 07:14:36 PM PDT 24
Finished Jul 14 07:17:08 PM PDT 24
Peak memory 207148 kb
Host smart-23f26e70-851e-4f4c-97ac-4ac280da5d69
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=486837320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.486837320
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2018476447
Short name T522
Test name
Test status
Simulation time 169993335 ps
CPU time 0.78 seconds
Started Jul 14 07:14:32 PM PDT 24
Finished Jul 14 07:16:38 PM PDT 24
Peak memory 206832 kb
Host smart-80212384-8ef9-42bf-a396-c53aa75b2202
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2018476447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2018476447
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2533722742
Short name T1031
Test name
Test status
Simulation time 152366300 ps
CPU time 0.78 seconds
Started Jul 14 07:14:32 PM PDT 24
Finished Jul 14 07:16:38 PM PDT 24
Peak memory 206864 kb
Host smart-e341b998-f952-4142-8b15-d376d0573f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25337
22742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2533722742
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.4260772673
Short name T2713
Test name
Test status
Simulation time 169750759 ps
CPU time 0.78 seconds
Started Jul 14 07:14:36 PM PDT 24
Finished Jul 14 07:16:49 PM PDT 24
Peak memory 206844 kb
Host smart-2a0d488d-3c7d-49e2-8f77-e46fa072efc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42607
72673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.4260772673
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1803290525
Short name T310
Test name
Test status
Simulation time 185925623 ps
CPU time 0.79 seconds
Started Jul 14 07:14:38 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206888 kb
Host smart-5a8a34d6-66da-48cf-819b-4752ed993bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18032
90525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1803290525
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3892268702
Short name T1152
Test name
Test status
Simulation time 146914774 ps
CPU time 0.84 seconds
Started Jul 14 07:14:30 PM PDT 24
Finished Jul 14 07:16:08 PM PDT 24
Peak memory 206852 kb
Host smart-69eaf975-86d8-4dad-86b6-392b6ba4c047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
68702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3892268702
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1543016574
Short name T2424
Test name
Test status
Simulation time 164656292 ps
CPU time 0.74 seconds
Started Jul 14 07:14:34 PM PDT 24
Finished Jul 14 07:16:39 PM PDT 24
Peak memory 206876 kb
Host smart-b3b78d9d-b1cd-48cd-8d68-6354debea641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15430
16574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1543016574
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.1013531965
Short name T2573
Test name
Test status
Simulation time 234485822 ps
CPU time 0.94 seconds
Started Jul 14 07:14:35 PM PDT 24
Finished Jul 14 07:16:49 PM PDT 24
Peak memory 206840 kb
Host smart-4292ccc2-aac1-4ae8-9755-cc3f044be213
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1013531965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.1013531965
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.892675961
Short name T1904
Test name
Test status
Simulation time 141486286 ps
CPU time 0.78 seconds
Started Jul 14 07:14:42 PM PDT 24
Finished Jul 14 07:17:15 PM PDT 24
Peak memory 206860 kb
Host smart-f90a75e9-83a4-499c-9b8c-730b73a63b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89267
5961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.892675961
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4188988555
Short name T2556
Test name
Test status
Simulation time 49008870 ps
CPU time 0.66 seconds
Started Jul 14 07:14:38 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 206868 kb
Host smart-f0a6b600-d274-4da0-be7e-473e86370c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41889
88555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4188988555
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2699315470
Short name T1971
Test name
Test status
Simulation time 6590141467 ps
CPU time 15.27 seconds
Started Jul 14 07:14:30 PM PDT 24
Finished Jul 14 07:16:34 PM PDT 24
Peak memory 207344 kb
Host smart-126ba1e3-93bb-4683-8781-df03ad8b85ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26993
15470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2699315470
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3231413862
Short name T2704
Test name
Test status
Simulation time 214354656 ps
CPU time 0.88 seconds
Started Jul 14 07:14:36 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 206888 kb
Host smart-d8d04291-7c56-4816-8073-69e2f5eec203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32314
13862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3231413862
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1483773002
Short name T1327
Test name
Test status
Simulation time 176900498 ps
CPU time 0.82 seconds
Started Jul 14 07:14:36 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 206888 kb
Host smart-896ad9b7-00eb-477d-8b4f-5fe1f229de63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14837
73002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1483773002
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.794055144
Short name T326
Test name
Test status
Simulation time 216204098 ps
CPU time 0.87 seconds
Started Jul 14 07:14:46 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206856 kb
Host smart-08f555e0-4c39-44a6-9d9c-cae444b570af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79405
5144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.794055144
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3944170067
Short name T1414
Test name
Test status
Simulation time 161810019 ps
CPU time 0.79 seconds
Started Jul 14 07:14:32 PM PDT 24
Finished Jul 14 07:16:38 PM PDT 24
Peak memory 206808 kb
Host smart-0b87ae61-95b5-4aac-8b57-f71b5d3e0ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39441
70067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3944170067
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.952895313
Short name T2542
Test name
Test status
Simulation time 167046937 ps
CPU time 0.8 seconds
Started Jul 14 07:14:32 PM PDT 24
Finished Jul 14 07:16:38 PM PDT 24
Peak memory 206896 kb
Host smart-19295463-95cf-4683-8db1-2ab5b6c23efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95289
5313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.952895313
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3195717136
Short name T299
Test name
Test status
Simulation time 158526446 ps
CPU time 0.8 seconds
Started Jul 14 07:14:33 PM PDT 24
Finished Jul 14 07:16:37 PM PDT 24
Peak memory 206856 kb
Host smart-3d7cf099-9926-41ba-9ca1-c829c84f5f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31957
17136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3195717136
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2804250981
Short name T1569
Test name
Test status
Simulation time 200434443 ps
CPU time 0.83 seconds
Started Jul 14 07:14:48 PM PDT 24
Finished Jul 14 07:16:51 PM PDT 24
Peak memory 206848 kb
Host smart-b8095e4e-e010-497a-8596-facb93062386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28042
50981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2804250981
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.4269371563
Short name T338
Test name
Test status
Simulation time 246000677 ps
CPU time 0.92 seconds
Started Jul 14 07:14:33 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 206876 kb
Host smart-16d65d18-fd11-4d2a-a157-2b6da21c899e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42693
71563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.4269371563
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2980479504
Short name T418
Test name
Test status
Simulation time 4783766672 ps
CPU time 125.47 seconds
Started Jul 14 07:14:32 PM PDT 24
Finished Jul 14 07:18:43 PM PDT 24
Peak memory 207124 kb
Host smart-a6b56cd4-a67f-4f90-b7c8-cda77514ed70
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2980479504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2980479504
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3706709970
Short name T1947
Test name
Test status
Simulation time 209315604 ps
CPU time 0.85 seconds
Started Jul 14 07:14:32 PM PDT 24
Finished Jul 14 07:16:38 PM PDT 24
Peak memory 206884 kb
Host smart-2e7f07ef-ced0-4570-bbf7-0a2b84879e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37067
09970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3706709970
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.762343502
Short name T1004
Test name
Test status
Simulation time 179305847 ps
CPU time 0.83 seconds
Started Jul 14 07:14:49 PM PDT 24
Finished Jul 14 07:17:13 PM PDT 24
Peak memory 206852 kb
Host smart-ba63dfe1-44eb-4302-8991-4d629282dd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76234
3502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.762343502
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3814387790
Short name T301
Test name
Test status
Simulation time 373906688 ps
CPU time 1.05 seconds
Started Jul 14 07:14:35 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 206872 kb
Host smart-d9c69615-3db9-445c-bd72-52a9af4d4574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38143
87790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3814387790
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3201500072
Short name T1664
Test name
Test status
Simulation time 6274653202 ps
CPU time 176.23 seconds
Started Jul 14 07:14:40 PM PDT 24
Finished Jul 14 07:19:45 PM PDT 24
Peak memory 207060 kb
Host smart-08b126ed-8511-4987-820d-aa89fb1dc95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32015
00072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3201500072
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.104727129
Short name T2298
Test name
Test status
Simulation time 42465692 ps
CPU time 0.68 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:04 PM PDT 24
Peak memory 206900 kb
Host smart-88b7d883-5351-4f72-a0e5-cc1411cb9807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=104727129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.104727129
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2814299188
Short name T733
Test name
Test status
Simulation time 3523837773 ps
CPU time 3.97 seconds
Started Jul 14 07:14:30 PM PDT 24
Finished Jul 14 07:16:40 PM PDT 24
Peak memory 206932 kb
Host smart-d9b0a2ad-d09b-444d-b0ba-021da9644237
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2814299188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.2814299188
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3826322116
Short name T2318
Test name
Test status
Simulation time 23310371702 ps
CPU time 25.04 seconds
Started Jul 14 07:14:43 PM PDT 24
Finished Jul 14 07:17:37 PM PDT 24
Peak memory 207132 kb
Host smart-03549168-7327-4468-b2e3-0bdb1395656a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3826322116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.3826322116
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2695392037
Short name T2380
Test name
Test status
Simulation time 178332803 ps
CPU time 0.79 seconds
Started Jul 14 07:14:39 PM PDT 24
Finished Jul 14 07:17:22 PM PDT 24
Peak memory 206888 kb
Host smart-a44b2274-20b1-4603-ad10-ed06f5604b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26953
92037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2695392037
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.4117988603
Short name T2243
Test name
Test status
Simulation time 157263965 ps
CPU time 0.79 seconds
Started Jul 14 07:14:40 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206888 kb
Host smart-86cc0128-cd7d-4212-af42-d0c6d931cfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41179
88603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.4117988603
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1917856748
Short name T1938
Test name
Test status
Simulation time 431281065 ps
CPU time 1.3 seconds
Started Jul 14 07:14:40 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206892 kb
Host smart-dda4c8da-7f3f-412d-95b1-8f3b6b404b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19178
56748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1917856748
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3262788832
Short name T714
Test name
Test status
Simulation time 615511927 ps
CPU time 1.48 seconds
Started Jul 14 07:14:42 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206976 kb
Host smart-be880081-5b15-4910-9ee3-70ae2047ff46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32627
88832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3262788832
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.401589052
Short name T2127
Test name
Test status
Simulation time 23131509215 ps
CPU time 42.3 seconds
Started Jul 14 07:14:37 PM PDT 24
Finished Jul 14 07:17:32 PM PDT 24
Peak memory 207108 kb
Host smart-f0b64bd4-8798-43bb-9209-87813cb262ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40158
9052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.401589052
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3408664580
Short name T809
Test name
Test status
Simulation time 357675861 ps
CPU time 1.19 seconds
Started Jul 14 07:14:45 PM PDT 24
Finished Jul 14 07:17:04 PM PDT 24
Peak memory 206884 kb
Host smart-3c366638-f841-4317-b73d-611c4bac391d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34086
64580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3408664580
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1934687471
Short name T674
Test name
Test status
Simulation time 166447557 ps
CPU time 0.79 seconds
Started Jul 14 07:14:42 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206872 kb
Host smart-56c9d9f0-ec81-4d72-bbb2-cb94956f1cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19346
87471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1934687471
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1995831587
Short name T2288
Test name
Test status
Simulation time 38137640 ps
CPU time 0.62 seconds
Started Jul 14 07:14:47 PM PDT 24
Finished Jul 14 07:17:11 PM PDT 24
Peak memory 206876 kb
Host smart-81340939-4dc7-4cb5-b46e-52d7f3495b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19958
31587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1995831587
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2013038636
Short name T649
Test name
Test status
Simulation time 1066517778 ps
CPU time 2.41 seconds
Started Jul 14 07:14:36 PM PDT 24
Finished Jul 14 07:16:52 PM PDT 24
Peak memory 207060 kb
Host smart-09933757-fd06-4f99-b8ba-c0381cffc00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20130
38636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2013038636
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2048931387
Short name T2290
Test name
Test status
Simulation time 346570213 ps
CPU time 2.16 seconds
Started Jul 14 07:14:43 PM PDT 24
Finished Jul 14 07:17:14 PM PDT 24
Peak memory 207008 kb
Host smart-49042e5b-e62d-467d-92a3-8ef8a906e4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20489
31387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2048931387
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2630166068
Short name T1214
Test name
Test status
Simulation time 216414845 ps
CPU time 0.84 seconds
Started Jul 14 07:14:41 PM PDT 24
Finished Jul 14 07:17:04 PM PDT 24
Peak memory 206868 kb
Host smart-48866f34-f735-4544-9cf8-f0e1425b9a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26301
66068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2630166068
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2256342714
Short name T424
Test name
Test status
Simulation time 159328495 ps
CPU time 0.74 seconds
Started Jul 14 07:14:40 PM PDT 24
Finished Jul 14 07:17:02 PM PDT 24
Peak memory 206884 kb
Host smart-fe41f0fb-c204-49ab-904c-423fec77becc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22563
42714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2256342714
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3807319824
Short name T2633
Test name
Test status
Simulation time 231589619 ps
CPU time 0.9 seconds
Started Jul 14 07:14:44 PM PDT 24
Finished Jul 14 07:16:40 PM PDT 24
Peak memory 206868 kb
Host smart-46439408-4a42-4262-9b4d-96aca075f3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38073
19824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3807319824
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.3384851494
Short name T2590
Test name
Test status
Simulation time 3550940327 ps
CPU time 12.43 seconds
Started Jul 14 07:14:48 PM PDT 24
Finished Jul 14 07:17:01 PM PDT 24
Peak memory 207148 kb
Host smart-d6f171e2-890e-4980-9745-eb9aff9fea33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33848
51494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3384851494
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.4139427064
Short name T1155
Test name
Test status
Simulation time 206970579 ps
CPU time 0.79 seconds
Started Jul 14 07:14:39 PM PDT 24
Finished Jul 14 07:16:48 PM PDT 24
Peak memory 206844 kb
Host smart-de58448d-62ba-4f94-8598-4a99ba1dbbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41394
27064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.4139427064
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.381898954
Short name T2551
Test name
Test status
Simulation time 23330553623 ps
CPU time 21.12 seconds
Started Jul 14 07:14:38 PM PDT 24
Finished Jul 14 07:17:23 PM PDT 24
Peak memory 206936 kb
Host smart-4a20e799-7fe6-40f6-9bda-486729b4c7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38189
8954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.381898954
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1950576844
Short name T20
Test name
Test status
Simulation time 3309186673 ps
CPU time 3.65 seconds
Started Jul 14 07:14:43 PM PDT 24
Finished Jul 14 07:17:15 PM PDT 24
Peak memory 206920 kb
Host smart-6e4e2b9e-ca2d-4feb-ad2b-d437fb66c856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19505
76844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1950576844
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3507767680
Short name T2271
Test name
Test status
Simulation time 7735590640 ps
CPU time 212.2 seconds
Started Jul 14 07:14:41 PM PDT 24
Finished Jul 14 07:20:35 PM PDT 24
Peak memory 207196 kb
Host smart-a0555620-7b1c-4400-a749-5be7331ec0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
67680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3507767680
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1761216645
Short name T578
Test name
Test status
Simulation time 4080359620 ps
CPU time 28.57 seconds
Started Jul 14 07:14:37 PM PDT 24
Finished Jul 14 07:17:17 PM PDT 24
Peak memory 207040 kb
Host smart-9596004b-ce8f-4710-a723-d64a2dab32ce
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1761216645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1761216645
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1936359785
Short name T1159
Test name
Test status
Simulation time 243717511 ps
CPU time 0.95 seconds
Started Jul 14 07:14:45 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206900 kb
Host smart-c48d892a-d88f-42fe-9adc-fc70d1dd52bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1936359785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1936359785
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2500687199
Short name T1042
Test name
Test status
Simulation time 199185723 ps
CPU time 0.84 seconds
Started Jul 14 07:14:43 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206856 kb
Host smart-1a53c81d-17b7-4439-a597-096d855eef7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25006
87199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2500687199
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.158900645
Short name T2113
Test name
Test status
Simulation time 3695996406 ps
CPU time 26.04 seconds
Started Jul 14 07:14:44 PM PDT 24
Finished Jul 14 07:17:28 PM PDT 24
Peak memory 207140 kb
Host smart-68fa8260-eec5-489d-943c-ed7ae3a04960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15890
0645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.158900645
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3190391645
Short name T1744
Test name
Test status
Simulation time 186418924 ps
CPU time 0.82 seconds
Started Jul 14 07:14:48 PM PDT 24
Finished Jul 14 07:17:22 PM PDT 24
Peak memory 206892 kb
Host smart-606fa040-fc6d-4d54-8eb7-0b23c32aa327
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3190391645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3190391645
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1122354520
Short name T1392
Test name
Test status
Simulation time 149757828 ps
CPU time 0.77 seconds
Started Jul 14 07:14:45 PM PDT 24
Finished Jul 14 07:17:33 PM PDT 24
Peak memory 206828 kb
Host smart-1b955454-ac33-4e67-918e-409bdeeb60a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11223
54520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1122354520
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1632359817
Short name T2149
Test name
Test status
Simulation time 173885016 ps
CPU time 0.79 seconds
Started Jul 14 07:14:49 PM PDT 24
Finished Jul 14 07:17:16 PM PDT 24
Peak memory 206868 kb
Host smart-bfd0f9af-bc98-426b-8488-6429d2f13953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16323
59817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1632359817
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3408153784
Short name T1720
Test name
Test status
Simulation time 152675731 ps
CPU time 0.82 seconds
Started Jul 14 07:14:44 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206880 kb
Host smart-1d868284-efa7-4a3a-a9a2-3dd36d739b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34081
53784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3408153784
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3044697693
Short name T1625
Test name
Test status
Simulation time 173382452 ps
CPU time 0.8 seconds
Started Jul 14 07:14:47 PM PDT 24
Finished Jul 14 07:16:59 PM PDT 24
Peak memory 206888 kb
Host smart-b5218dee-343a-48c8-9624-4a2df34c6a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30446
97693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3044697693
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3243098666
Short name T2181
Test name
Test status
Simulation time 173430806 ps
CPU time 0.75 seconds
Started Jul 14 07:14:53 PM PDT 24
Finished Jul 14 07:17:04 PM PDT 24
Peak memory 206808 kb
Host smart-5c2d96e6-9808-4e65-b983-c560e821a75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32430
98666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3243098666
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1049137382
Short name T1032
Test name
Test status
Simulation time 253678334 ps
CPU time 0.95 seconds
Started Jul 14 07:14:54 PM PDT 24
Finished Jul 14 07:17:13 PM PDT 24
Peak memory 206808 kb
Host smart-083a8004-bf85-409f-8f5b-6b839e82c2b4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1049137382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1049137382
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1782914229
Short name T1680
Test name
Test status
Simulation time 187213693 ps
CPU time 0.78 seconds
Started Jul 14 07:14:53 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206872 kb
Host smart-3285eec7-a7c0-4669-a9ae-e6204e35767e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17829
14229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1782914229
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2423335017
Short name T1092
Test name
Test status
Simulation time 44418131 ps
CPU time 0.66 seconds
Started Jul 14 07:14:48 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206820 kb
Host smart-51e08693-190c-4b03-829a-2fc9640bd7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24233
35017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2423335017
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2277433182
Short name T1138
Test name
Test status
Simulation time 22595958274 ps
CPU time 45.29 seconds
Started Jul 14 07:14:44 PM PDT 24
Finished Jul 14 07:17:57 PM PDT 24
Peak memory 207140 kb
Host smart-a8e65992-732c-40f7-ac87-e1dda2f2dcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22774
33182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2277433182
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1243354574
Short name T2025
Test name
Test status
Simulation time 181943028 ps
CPU time 0.88 seconds
Started Jul 14 07:14:59 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206852 kb
Host smart-1f973f8f-6337-47d9-b3cc-1e3d7cc5c5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12433
54574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1243354574
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.224616149
Short name T2313
Test name
Test status
Simulation time 238764580 ps
CPU time 0.88 seconds
Started Jul 14 07:14:50 PM PDT 24
Finished Jul 14 07:17:13 PM PDT 24
Peak memory 206860 kb
Host smart-899feb6a-2c13-4d56-aea7-6c8539cd64f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22461
6149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.224616149
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3010268628
Short name T2170
Test name
Test status
Simulation time 204642159 ps
CPU time 0.84 seconds
Started Jul 14 07:14:49 PM PDT 24
Finished Jul 14 07:17:15 PM PDT 24
Peak memory 206892 kb
Host smart-291a90b4-041b-4755-ac74-c77f493eefad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30102
68628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3010268628
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3980053373
Short name T763
Test name
Test status
Simulation time 138187142 ps
CPU time 0.71 seconds
Started Jul 14 07:14:47 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206884 kb
Host smart-ece8e396-6c78-4d11-be04-43ad749dca77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39800
53373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3980053373
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.181166304
Short name T1396
Test name
Test status
Simulation time 183348008 ps
CPU time 0.83 seconds
Started Jul 14 07:14:45 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206876 kb
Host smart-5c06c6cf-5086-4e24-86d3-583f3256c4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18116
6304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.181166304
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.850476296
Short name T1126
Test name
Test status
Simulation time 143125740 ps
CPU time 0.78 seconds
Started Jul 14 07:14:45 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 206888 kb
Host smart-f3435ab5-051b-4240-9587-bc9b872153a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85047
6296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.850476296
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.665996102
Short name T2578
Test name
Test status
Simulation time 3310964969 ps
CPU time 81.81 seconds
Started Jul 14 07:14:53 PM PDT 24
Finished Jul 14 07:18:01 PM PDT 24
Peak memory 207068 kb
Host smart-570448f9-5db3-4bcb-b68a-3adfd2f53fae
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=665996102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.665996102
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2256675585
Short name T2006
Test name
Test status
Simulation time 172178941 ps
CPU time 0.78 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:18:01 PM PDT 24
Peak memory 206860 kb
Host smart-e94b1b88-d851-488b-9ae2-336e64b9da40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22566
75585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2256675585
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3125607142
Short name T2163
Test name
Test status
Simulation time 185318407 ps
CPU time 0.82 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:13 PM PDT 24
Peak memory 206880 kb
Host smart-ad23760b-b9c3-4843-b0d2-c25efc5669bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31256
07142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3125607142
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2342868550
Short name T1815
Test name
Test status
Simulation time 249860436 ps
CPU time 0.94 seconds
Started Jul 14 07:14:52 PM PDT 24
Finished Jul 14 07:17:00 PM PDT 24
Peak memory 206848 kb
Host smart-c1a56ab5-e96d-4c33-aced-c565e96520fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23428
68550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2342868550
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2287517379
Short name T1692
Test name
Test status
Simulation time 7605711426 ps
CPU time 52.93 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:18:05 PM PDT 24
Peak memory 207040 kb
Host smart-1a76d97e-3331-4424-bd59-a2f1ab971920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22875
17379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2287517379
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3914476982
Short name T1297
Test name
Test status
Simulation time 43451303 ps
CPU time 0.72 seconds
Started Jul 14 07:15:16 PM PDT 24
Finished Jul 14 07:17:33 PM PDT 24
Peak memory 206940 kb
Host smart-7257383d-9517-4f9d-a47d-543316cf4f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3914476982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3914476982
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2454507625
Short name T1084
Test name
Test status
Simulation time 3975422196 ps
CPU time 5.37 seconds
Started Jul 14 07:14:53 PM PDT 24
Finished Jul 14 07:17:04 PM PDT 24
Peak memory 207128 kb
Host smart-716927ba-1061-4723-b4c7-db7ffcce3375
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2454507625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2454507625
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.4032409671
Short name T645
Test name
Test status
Simulation time 13450617675 ps
CPU time 16.43 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:17:49 PM PDT 24
Peak memory 206952 kb
Host smart-4840411f-36c3-4be5-b8ab-7da936744cb7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4032409671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.4032409671
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3569871516
Short name T1858
Test name
Test status
Simulation time 23336817191 ps
CPU time 21.9 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:21 PM PDT 24
Peak memory 207060 kb
Host smart-8af143b5-18de-4564-9391-5814583f5003
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3569871516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3569871516
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2579112203
Short name T2597
Test name
Test status
Simulation time 198550793 ps
CPU time 0.83 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:17:53 PM PDT 24
Peak memory 206880 kb
Host smart-4ac87721-0d7e-4959-918f-71c12e2310b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25791
12203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2579112203
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.4093771533
Short name T2049
Test name
Test status
Simulation time 167134072 ps
CPU time 0.86 seconds
Started Jul 14 07:16:27 PM PDT 24
Finished Jul 14 07:18:02 PM PDT 24
Peak memory 206892 kb
Host smart-75cf8736-8c16-4582-aff8-4f270d271982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
71533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.4093771533
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.331856159
Short name T2130
Test name
Test status
Simulation time 477328321 ps
CPU time 1.39 seconds
Started Jul 14 07:14:55 PM PDT 24
Finished Jul 14 07:16:50 PM PDT 24
Peak memory 207016 kb
Host smart-1e84d4cb-de8b-4eaa-8088-1fe33d4f9894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33185
6159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.331856159
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1371994563
Short name T98
Test name
Test status
Simulation time 1217448085 ps
CPU time 2.44 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:17 PM PDT 24
Peak memory 207040 kb
Host smart-4dec012a-5faa-42e6-8384-71c15ccb9639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13719
94563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1371994563
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.1187944932
Short name T2124
Test name
Test status
Simulation time 11322646065 ps
CPU time 21.27 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:35 PM PDT 24
Peak memory 207156 kb
Host smart-8952a33d-37eb-46c1-a8b5-eb21dc3e0547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11879
44932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1187944932
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3617899407
Short name T640
Test name
Test status
Simulation time 449654533 ps
CPU time 1.33 seconds
Started Jul 14 07:15:53 PM PDT 24
Finished Jul 14 07:17:43 PM PDT 24
Peak memory 206832 kb
Host smart-2a5ae7cd-8556-410c-8214-09116bd9fa64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
99407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3617899407
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.106148987
Short name T682
Test name
Test status
Simulation time 145376994 ps
CPU time 0.75 seconds
Started Jul 14 07:14:53 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206852 kb
Host smart-ce0f5665-8568-42bc-b168-2d4e7562254c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10614
8987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.106148987
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1876043390
Short name T352
Test name
Test status
Simulation time 43219578 ps
CPU time 0.63 seconds
Started Jul 14 07:16:05 PM PDT 24
Finished Jul 14 07:17:48 PM PDT 24
Peak memory 206868 kb
Host smart-6c7fc3df-fcba-4ae3-baf2-dc29f7d2f0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18760
43390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1876043390
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2738839647
Short name T580
Test name
Test status
Simulation time 1012622624 ps
CPU time 2.39 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:17:35 PM PDT 24
Peak memory 207024 kb
Host smart-9deef05c-efe7-4b18-975a-3df5f1a12741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27388
39647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2738839647
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1961174914
Short name T1027
Test name
Test status
Simulation time 167385980 ps
CPU time 1.49 seconds
Started Jul 14 07:14:51 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 207004 kb
Host smart-86f1eee6-e625-4b53-a035-a1592b940310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19611
74914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1961174914
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3644400254
Short name T2016
Test name
Test status
Simulation time 168507417 ps
CPU time 0.82 seconds
Started Jul 14 07:14:52 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206856 kb
Host smart-6ca2fecd-c77b-4438-9da6-7e15c29c7928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36444
00254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3644400254
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1889727738
Short name T613
Test name
Test status
Simulation time 138850883 ps
CPU time 0.73 seconds
Started Jul 14 07:14:59 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206884 kb
Host smart-38dc162c-1429-4c62-bea5-a70ba29c5b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18897
27738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1889727738
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3494757741
Short name T371
Test name
Test status
Simulation time 274410022 ps
CPU time 0.95 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206852 kb
Host smart-20c8bcea-01ce-46b7-83de-3e4883ad353f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
57741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3494757741
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.2950446345
Short name T1603
Test name
Test status
Simulation time 5161146644 ps
CPU time 139.79 seconds
Started Jul 14 07:16:35 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 207080 kb
Host smart-08d0fed8-1811-45a8-a44b-78831a2f87fa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2950446345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.2950446345
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.1552187933
Short name T742
Test name
Test status
Simulation time 7289065745 ps
CPU time 64.79 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 207120 kb
Host smart-0b3c0af8-c125-477b-85b0-79977d07e36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15521
87933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.1552187933
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.902813141
Short name T340
Test name
Test status
Simulation time 264081692 ps
CPU time 0.86 seconds
Started Jul 14 07:16:16 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206640 kb
Host smart-835b7a36-c8f9-4ab8-8b3d-f98f31c58c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90281
3141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.902813141
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.2110586997
Short name T470
Test name
Test status
Simulation time 23328058439 ps
CPU time 22.4 seconds
Started Jul 14 07:16:17 PM PDT 24
Finished Jul 14 07:18:19 PM PDT 24
Peak memory 206940 kb
Host smart-f8a6bd6e-cd55-4d2a-b989-b62c9ad3fbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105
86997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2110586997
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1661605536
Short name T896
Test name
Test status
Simulation time 3342648045 ps
CPU time 4.22 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:17:16 PM PDT 24
Peak memory 206892 kb
Host smart-02611ff7-0023-4c2d-8b38-311d950bb4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16616
05536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1661605536
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.3824751357
Short name T2132
Test name
Test status
Simulation time 9170882252 ps
CPU time 258.76 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:21:30 PM PDT 24
Peak memory 207152 kb
Host smart-aee75dd2-f62d-4b6f-818d-6f5ffb5740e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
51357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.3824751357
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3306655233
Short name T1979
Test name
Test status
Simulation time 3426579426 ps
CPU time 23.15 seconds
Started Jul 14 07:16:12 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 207048 kb
Host smart-2f10329c-60d9-41b0-b71d-72cabb8c4b10
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3306655233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3306655233
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2307645581
Short name T1831
Test name
Test status
Simulation time 245462313 ps
CPU time 0.87 seconds
Started Jul 14 07:16:04 PM PDT 24
Finished Jul 14 07:17:48 PM PDT 24
Peak memory 206872 kb
Host smart-51703543-8b1d-49d7-89f0-1966974a64e5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2307645581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2307645581
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3635738772
Short name T1969
Test name
Test status
Simulation time 253086924 ps
CPU time 0.87 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206872 kb
Host smart-8ca69721-688a-4dcb-a9cb-3fd498eb6524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36357
38772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3635738772
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.4169875878
Short name T2604
Test name
Test status
Simulation time 4267396005 ps
CPU time 28.42 seconds
Started Jul 14 07:16:19 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 207020 kb
Host smart-cb81ecfc-65b8-42b6-a574-c6fa48f70715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41698
75878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.4169875878
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2741512341
Short name T663
Test name
Test status
Simulation time 6525249748 ps
CPU time 168.21 seconds
Started Jul 14 07:16:06 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 207068 kb
Host smart-ed1262ef-da17-4523-a0ae-fc1dd3a56e85
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2741512341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2741512341
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2819120049
Short name T1162
Test name
Test status
Simulation time 161820458 ps
CPU time 0.84 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206892 kb
Host smart-fc367653-a60a-4ac3-92a7-becf978da181
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2819120049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2819120049
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.277623273
Short name T2533
Test name
Test status
Simulation time 154486933 ps
CPU time 0.73 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206852 kb
Host smart-3a8967f4-19c8-465b-99a3-381ab11070c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27762
3273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.277623273
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.534089134
Short name T113
Test name
Test status
Simulation time 170028793 ps
CPU time 0.81 seconds
Started Jul 14 07:14:59 PM PDT 24
Finished Jul 14 07:17:16 PM PDT 24
Peak memory 206892 kb
Host smart-97d69939-f890-4cde-8d93-4c4013c87b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53408
9134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.534089134
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2552477218
Short name T870
Test name
Test status
Simulation time 139703701 ps
CPU time 0.75 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206864 kb
Host smart-1646fbdd-d250-4798-bc90-a4711ee3375d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
77218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2552477218
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2607463820
Short name T738
Test name
Test status
Simulation time 159459492 ps
CPU time 0.79 seconds
Started Jul 14 07:16:13 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206828 kb
Host smart-01389ea9-c933-44f9-beef-a73131f4898e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26074
63820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2607463820
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3602520711
Short name T798
Test name
Test status
Simulation time 185220320 ps
CPU time 0.8 seconds
Started Jul 14 07:14:59 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 206824 kb
Host smart-382f1e64-73ed-416e-93b8-8c7a317be6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36025
20711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3602520711
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.4148815131
Short name T618
Test name
Test status
Simulation time 183763114 ps
CPU time 0.77 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206868 kb
Host smart-93fe0608-6299-45fe-8ff1-745be13b1857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41488
15131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.4148815131
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2684510736
Short name T391
Test name
Test status
Simulation time 242686454 ps
CPU time 0.93 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206844 kb
Host smart-76079aac-2210-4c97-bd69-940b09bee90b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2684510736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2684510736
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3175807454
Short name T1655
Test name
Test status
Simulation time 188766331 ps
CPU time 0.77 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206892 kb
Host smart-47bdcf2e-f65d-45be-8634-738dcfdefa27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31758
07454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3175807454
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3497614089
Short name T743
Test name
Test status
Simulation time 33840088 ps
CPU time 0.63 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206860 kb
Host smart-3ea6d6b5-29f1-4bcf-8a3d-896f87e90b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34976
14089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3497614089
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.934200015
Short name T1983
Test name
Test status
Simulation time 13226124638 ps
CPU time 28.5 seconds
Started Jul 14 07:15:04 PM PDT 24
Finished Jul 14 07:17:40 PM PDT 24
Peak memory 207124 kb
Host smart-fd83970a-732b-4d6c-bb7b-194d8d936124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93420
0015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.934200015
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2820352276
Short name T1524
Test name
Test status
Simulation time 216393197 ps
CPU time 0.86 seconds
Started Jul 14 07:16:05 PM PDT 24
Finished Jul 14 07:17:48 PM PDT 24
Peak memory 206860 kb
Host smart-46ddc988-7a9d-4cc9-b469-ae870d29d0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28203
52276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2820352276
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.522309477
Short name T1054
Test name
Test status
Simulation time 192730982 ps
CPU time 0.81 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206876 kb
Host smart-bbbebcb6-b9a0-4408-bba2-eaed9af65bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52230
9477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.522309477
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2226780077
Short name T389
Test name
Test status
Simulation time 163614774 ps
CPU time 0.8 seconds
Started Jul 14 07:15:01 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206872 kb
Host smart-d8e61313-ebf0-4ba7-9170-9c005f4d262f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22267
80077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2226780077
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2013851372
Short name T877
Test name
Test status
Simulation time 196677495 ps
CPU time 0.83 seconds
Started Jul 14 07:15:02 PM PDT 24
Finished Jul 14 07:17:04 PM PDT 24
Peak memory 206888 kb
Host smart-e161f7b0-fcb0-4872-90d8-dd1650dcd68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20138
51372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2013851372
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1472055703
Short name T2575
Test name
Test status
Simulation time 135779562 ps
CPU time 0.74 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:14 PM PDT 24
Peak memory 206892 kb
Host smart-2530569c-4029-4fd9-bab1-82ac64c27d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14720
55703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1472055703
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2691862067
Short name T1610
Test name
Test status
Simulation time 163625349 ps
CPU time 0.75 seconds
Started Jul 14 07:15:00 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206884 kb
Host smart-c5ecacb4-6dc9-4116-b751-7f00dbc0c920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26918
62067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2691862067
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1784301234
Short name T790
Test name
Test status
Simulation time 165900790 ps
CPU time 0.82 seconds
Started Jul 14 07:16:10 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206880 kb
Host smart-fb07cc65-c9bc-4681-85ac-df20bd1def6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17843
01234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1784301234
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1934117757
Short name T1074
Test name
Test status
Simulation time 247172537 ps
CPU time 0.95 seconds
Started Jul 14 07:16:10 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206852 kb
Host smart-f89dc801-ae20-4486-bd96-2ac57c8931d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19341
17757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1934117757
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3182227776
Short name T575
Test name
Test status
Simulation time 3905605497 ps
CPU time 26.22 seconds
Started Jul 14 07:16:17 PM PDT 24
Finished Jul 14 07:18:19 PM PDT 24
Peak memory 207108 kb
Host smart-170173f2-07bd-4d4d-9aae-efbbefed5df3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3182227776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3182227776
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2166755005
Short name T934
Test name
Test status
Simulation time 180374201 ps
CPU time 0.84 seconds
Started Jul 14 07:15:03 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206808 kb
Host smart-b040cf1a-d50e-4cd3-a93b-363b49e553a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21667
55005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2166755005
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3561551915
Short name T2555
Test name
Test status
Simulation time 198653121 ps
CPU time 0.8 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:00 PM PDT 24
Peak memory 206884 kb
Host smart-f911df29-2247-42ab-8f06-d4d143a1d096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35615
51915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3561551915
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2748925142
Short name T2083
Test name
Test status
Simulation time 618388200 ps
CPU time 1.45 seconds
Started Jul 14 07:16:10 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206872 kb
Host smart-3daab440-ae27-4962-818f-a960eaac6d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489
25142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2748925142
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3148584763
Short name T1120
Test name
Test status
Simulation time 5453114284 ps
CPU time 50.41 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:51 PM PDT 24
Peak memory 207092 kb
Host smart-22505f64-5a7e-45ac-a02f-9918219c765a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31485
84763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3148584763
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2639949493
Short name T2614
Test name
Test status
Simulation time 43334045 ps
CPU time 0.66 seconds
Started Jul 14 07:15:40 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206896 kb
Host smart-fd0430c1-bd42-4675-b792-04b5e4619394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2639949493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2639949493
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.339267295
Short name T1589
Test name
Test status
Simulation time 4079064042 ps
CPU time 5.03 seconds
Started Jul 14 07:15:11 PM PDT 24
Finished Jul 14 07:17:47 PM PDT 24
Peak memory 206968 kb
Host smart-94326b10-1d31-4bfa-9960-fe0663c9c89d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=339267295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.339267295
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2070894438
Short name T2071
Test name
Test status
Simulation time 13485349717 ps
CPU time 12.38 seconds
Started Jul 14 07:15:12 PM PDT 24
Finished Jul 14 07:17:23 PM PDT 24
Peak memory 207160 kb
Host smart-a72437ae-94eb-4d2e-abea-2d7ecc9aec84
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2070894438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2070894438
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3672812508
Short name T1328
Test name
Test status
Simulation time 23344314089 ps
CPU time 22.18 seconds
Started Jul 14 07:15:14 PM PDT 24
Finished Jul 14 07:17:55 PM PDT 24
Peak memory 206928 kb
Host smart-942646d5-ee60-4090-8f27-3c58900f877f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3672812508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3672812508
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.648416147
Short name T2009
Test name
Test status
Simulation time 151459084 ps
CPU time 0.75 seconds
Started Jul 14 07:15:14 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206876 kb
Host smart-972e4ade-f4cf-4f58-a481-575c7a5f6b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64841
6147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.648416147
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.4245457028
Short name T2660
Test name
Test status
Simulation time 170058297 ps
CPU time 0.74 seconds
Started Jul 14 07:15:11 PM PDT 24
Finished Jul 14 07:17:12 PM PDT 24
Peak memory 206864 kb
Host smart-85f0f556-b6ec-4567-b2ba-27417598a972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42454
57028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.4245457028
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.3455266436
Short name T2278
Test name
Test status
Simulation time 359471897 ps
CPU time 1.17 seconds
Started Jul 14 07:15:06 PM PDT 24
Finished Jul 14 07:17:04 PM PDT 24
Peak memory 206884 kb
Host smart-dae97f51-5271-4cd0-9cae-b093ac7a1c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34552
66436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3455266436
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1331477384
Short name T2054
Test name
Test status
Simulation time 982285857 ps
CPU time 2.21 seconds
Started Jul 14 07:15:11 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 207008 kb
Host smart-7fd9ab1b-8eae-49d1-b0db-9123d3f390ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13314
77384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1331477384
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3817976882
Short name T1738
Test name
Test status
Simulation time 18855462186 ps
CPU time 40.06 seconds
Started Jul 14 07:15:12 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 207092 kb
Host smart-f3026a36-164a-4fa3-a0f1-ae5f42d55303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38179
76882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3817976882
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3352221846
Short name T996
Test name
Test status
Simulation time 427620089 ps
CPU time 1.39 seconds
Started Jul 14 07:16:26 PM PDT 24
Finished Jul 14 07:18:02 PM PDT 24
Peak memory 206876 kb
Host smart-c40513a0-7200-49c3-9fc3-a63c9fa9b910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33522
21846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3352221846
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.4136372406
Short name T1485
Test name
Test status
Simulation time 171787506 ps
CPU time 0.75 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206888 kb
Host smart-736aa507-a1f1-426a-80cb-b11da3006b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41363
72406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.4136372406
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3285746273
Short name T1874
Test name
Test status
Simulation time 30908916 ps
CPU time 0.66 seconds
Started Jul 14 07:16:22 PM PDT 24
Finished Jul 14 07:18:01 PM PDT 24
Peak memory 206840 kb
Host smart-aaf3765e-14b0-4c58-886a-a3cb86611785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32857
46273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3285746273
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1599190986
Short name T1213
Test name
Test status
Simulation time 982760806 ps
CPU time 2.36 seconds
Started Jul 14 07:15:16 PM PDT 24
Finished Jul 14 07:17:14 PM PDT 24
Peak memory 206976 kb
Host smart-af38dd4d-5eac-4f2b-8179-34297a0d3754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15991
90986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1599190986
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1030400170
Short name T2168
Test name
Test status
Simulation time 179915738 ps
CPU time 1.89 seconds
Started Jul 14 07:15:15 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206968 kb
Host smart-b0f4a843-b88d-4496-a022-c6049054a099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10304
00170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1030400170
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1084396527
Short name T771
Test name
Test status
Simulation time 169244929 ps
CPU time 0.88 seconds
Started Jul 14 07:15:22 PM PDT 24
Finished Jul 14 07:17:53 PM PDT 24
Peak memory 206916 kb
Host smart-db27c229-6e25-40ec-b690-e085ce5b0557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
96527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1084396527
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1260924583
Short name T2062
Test name
Test status
Simulation time 140850420 ps
CPU time 0.77 seconds
Started Jul 14 07:16:15 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206856 kb
Host smart-d39c0361-c1be-444a-b46f-d28ba985fe52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12609
24583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1260924583
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1132763485
Short name T1012
Test name
Test status
Simulation time 177306817 ps
CPU time 0.79 seconds
Started Jul 14 07:15:16 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206860 kb
Host smart-f1fab748-169c-4b6c-b73f-1e9f8d1906db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11327
63485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1132763485
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2207707089
Short name T2738
Test name
Test status
Simulation time 9725077907 ps
CPU time 261.35 seconds
Started Jul 14 07:15:16 PM PDT 24
Finished Jul 14 07:21:54 PM PDT 24
Peak memory 207080 kb
Host smart-03df3ddb-8dfe-4022-a80c-b572d3a5c1b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2207707089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2207707089
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.519396724
Short name T1335
Test name
Test status
Simulation time 9477363010 ps
CPU time 28.12 seconds
Started Jul 14 07:16:23 PM PDT 24
Finished Jul 14 07:18:29 PM PDT 24
Peak memory 207124 kb
Host smart-2f648fe4-25c3-4d9c-93e8-1d0e6603e1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51939
6724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.519396724
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3608058904
Short name T2036
Test name
Test status
Simulation time 173647625 ps
CPU time 0.81 seconds
Started Jul 14 07:16:24 PM PDT 24
Finished Jul 14 07:18:02 PM PDT 24
Peak memory 206868 kb
Host smart-07a0e481-41f8-4b41-abfc-d00c70bf75ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36080
58904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3608058904
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3482318990
Short name T351
Test name
Test status
Simulation time 23426143484 ps
CPU time 27.46 seconds
Started Jul 14 07:15:20 PM PDT 24
Finished Jul 14 07:18:08 PM PDT 24
Peak memory 206896 kb
Host smart-013c34de-27f1-4fc6-9875-0d9386c3a5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34823
18990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3482318990
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.748269478
Short name T1286
Test name
Test status
Simulation time 3329573584 ps
CPU time 3.76 seconds
Started Jul 14 07:15:21 PM PDT 24
Finished Jul 14 07:17:43 PM PDT 24
Peak memory 206872 kb
Host smart-b639e443-fb5b-4b63-84a3-45a04fe1490a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74826
9478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.748269478
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.4231714792
Short name T1157
Test name
Test status
Simulation time 9433543275 ps
CPU time 245.33 seconds
Started Jul 14 07:15:25 PM PDT 24
Finished Jul 14 07:21:27 PM PDT 24
Peak memory 207144 kb
Host smart-97498d3a-c68e-496f-bb43-f2cbc3289e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
14792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.4231714792
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1219350819
Short name T1779
Test name
Test status
Simulation time 3364007405 ps
CPU time 29.57 seconds
Started Jul 14 07:15:24 PM PDT 24
Finished Jul 14 07:18:10 PM PDT 24
Peak memory 207108 kb
Host smart-4e682b7f-deb4-4953-ba19-0cd4055ade07
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1219350819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1219350819
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2995988683
Short name T2004
Test name
Test status
Simulation time 273048728 ps
CPU time 0.93 seconds
Started Jul 14 07:15:21 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206856 kb
Host smart-a3461b8e-ca98-47db-83d1-037f9269f92c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2995988683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2995988683
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3649838805
Short name T1294
Test name
Test status
Simulation time 215414137 ps
CPU time 0.88 seconds
Started Jul 14 07:15:25 PM PDT 24
Finished Jul 14 07:17:41 PM PDT 24
Peak memory 206860 kb
Host smart-927c6678-874c-4b7d-9bcd-cdd7ffed4824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36498
38805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3649838805
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.553551206
Short name T2657
Test name
Test status
Simulation time 5628254823 ps
CPU time 153.35 seconds
Started Jul 14 07:15:27 PM PDT 24
Finished Jul 14 07:20:25 PM PDT 24
Peak memory 207068 kb
Host smart-5c80d368-c301-481b-a5da-21c445b3682b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55355
1206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.553551206
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3148963802
Short name T2608
Test name
Test status
Simulation time 4193291958 ps
CPU time 37.64 seconds
Started Jul 14 07:16:24 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 207140 kb
Host smart-112df4e6-c427-4799-b52b-3ab157ed2bd5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3148963802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3148963802
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.617307295
Short name T1889
Test name
Test status
Simulation time 143079171 ps
CPU time 0.81 seconds
Started Jul 14 07:16:27 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206864 kb
Host smart-b2a4a8eb-20fe-43cf-8220-760354330839
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=617307295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.617307295
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2611205771
Short name T357
Test name
Test status
Simulation time 159586596 ps
CPU time 0.78 seconds
Started Jul 14 07:15:20 PM PDT 24
Finished Jul 14 07:17:41 PM PDT 24
Peak memory 206864 kb
Host smart-24d2c751-32eb-4fbe-8970-3d7649875055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112
05771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2611205771
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2343060471
Short name T931
Test name
Test status
Simulation time 162129496 ps
CPU time 0.79 seconds
Started Jul 14 07:16:22 PM PDT 24
Finished Jul 14 07:18:01 PM PDT 24
Peak memory 206880 kb
Host smart-c99afa70-b8e1-47b1-a488-cd18ccf95c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
60471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2343060471
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1202634263
Short name T1876
Test name
Test status
Simulation time 180037432 ps
CPU time 0.81 seconds
Started Jul 14 07:15:25 PM PDT 24
Finished Jul 14 07:17:41 PM PDT 24
Peak memory 206868 kb
Host smart-0d9804ee-be9c-4664-ba2e-b3135a2d9492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12026
34263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1202634263
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2754223160
Short name T704
Test name
Test status
Simulation time 169069296 ps
CPU time 0.77 seconds
Started Jul 14 07:15:25 PM PDT 24
Finished Jul 14 07:17:23 PM PDT 24
Peak memory 206852 kb
Host smart-dffbd452-8187-4217-aacb-2694b054eb1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27542
23160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2754223160
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.554642442
Short name T153
Test name
Test status
Simulation time 172213199 ps
CPU time 0.84 seconds
Started Jul 14 07:16:25 PM PDT 24
Finished Jul 14 07:18:02 PM PDT 24
Peak memory 206888 kb
Host smart-f2b8ce92-f62b-4a18-b27b-8cba41206834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55464
2442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.554642442
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2704308026
Short name T1990
Test name
Test status
Simulation time 245837295 ps
CPU time 1 seconds
Started Jul 14 07:15:26 PM PDT 24
Finished Jul 14 07:17:34 PM PDT 24
Peak memory 206844 kb
Host smart-cc98f68a-8329-49aa-9457-9a60c51ff0f1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2704308026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2704308026
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2990975116
Short name T1510
Test name
Test status
Simulation time 154543799 ps
CPU time 0.75 seconds
Started Jul 14 07:16:27 PM PDT 24
Finished Jul 14 07:18:02 PM PDT 24
Peak memory 206872 kb
Host smart-e68b5e19-493e-435f-9f4d-4ee7d60fe3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29909
75116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2990975116
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2000918
Short name T1394
Test name
Test status
Simulation time 37154209 ps
CPU time 0.64 seconds
Started Jul 14 07:16:27 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206912 kb
Host smart-f9b46e7d-111a-40fb-b27c-7c9f8ef64e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20009
18 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2000918
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.818788178
Short name T244
Test name
Test status
Simulation time 18826380759 ps
CPU time 38.86 seconds
Started Jul 14 07:16:33 PM PDT 24
Finished Jul 14 07:18:42 PM PDT 24
Peak memory 207188 kb
Host smart-ef98cfcc-7bf8-4f00-ab87-79089cf93305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81878
8178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.818788178
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2691653750
Short name T626
Test name
Test status
Simulation time 177331019 ps
CPU time 0.8 seconds
Started Jul 14 07:15:25 PM PDT 24
Finished Jul 14 07:17:23 PM PDT 24
Peak memory 206864 kb
Host smart-805429fc-955f-4964-b26c-b465577fe161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26916
53750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2691653750
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.421069829
Short name T2460
Test name
Test status
Simulation time 161188915 ps
CPU time 0.79 seconds
Started Jul 14 07:15:25 PM PDT 24
Finished Jul 14 07:17:23 PM PDT 24
Peak memory 206860 kb
Host smart-3df0f3b9-a0b4-4943-ad05-385d03e18e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42106
9829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.421069829
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.243459416
Short name T1590
Test name
Test status
Simulation time 180675187 ps
CPU time 0.76 seconds
Started Jul 14 07:15:24 PM PDT 24
Finished Jul 14 07:17:33 PM PDT 24
Peak memory 206884 kb
Host smart-a904a713-5d2a-46cb-952c-2288f1309e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24345
9416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.243459416
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.4169634239
Short name T335
Test name
Test status
Simulation time 164200498 ps
CPU time 0.76 seconds
Started Jul 14 07:15:29 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206804 kb
Host smart-ad05d08e-3088-4c05-bc27-afa89a91475f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41696
34239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.4169634239
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.368840425
Short name T1994
Test name
Test status
Simulation time 226635956 ps
CPU time 0.78 seconds
Started Jul 14 07:15:25 PM PDT 24
Finished Jul 14 07:17:40 PM PDT 24
Peak memory 206864 kb
Host smart-ea95ae0b-7141-4fc3-a97d-b09be25791d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36884
0425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.368840425
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3749272789
Short name T422
Test name
Test status
Simulation time 163577611 ps
CPU time 0.75 seconds
Started Jul 14 07:15:32 PM PDT 24
Finished Jul 14 07:17:41 PM PDT 24
Peak memory 206876 kb
Host smart-a1991683-5e02-4b96-b414-13d63eeb9427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37492
72789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3749272789
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3746091651
Short name T706
Test name
Test status
Simulation time 152763122 ps
CPU time 0.77 seconds
Started Jul 14 07:15:29 PM PDT 24
Finished Jul 14 07:17:33 PM PDT 24
Peak memory 206872 kb
Host smart-325a994c-438a-41a6-9d18-40ec4ac5d4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460
91651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3746091651
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2419509095
Short name T1576
Test name
Test status
Simulation time 233876942 ps
CPU time 0.89 seconds
Started Jul 14 07:15:30 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206828 kb
Host smart-e1ef6d3b-3a82-46e2-a9bb-3f3d4c842d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24195
09095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2419509095
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.64399784
Short name T2344
Test name
Test status
Simulation time 4888504463 ps
CPU time 44.68 seconds
Started Jul 14 07:15:28 PM PDT 24
Finished Jul 14 07:18:24 PM PDT 24
Peak memory 207088 kb
Host smart-95818133-3b28-4c7d-bbab-dbdfa4fa8130
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=64399784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.64399784
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.94806503
Short name T1472
Test name
Test status
Simulation time 173217820 ps
CPU time 0.79 seconds
Started Jul 14 07:15:29 PM PDT 24
Finished Jul 14 07:17:22 PM PDT 24
Peak memory 206888 kb
Host smart-21a50503-50b6-482e-b8cc-118a3d114bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94806
503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.94806503
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2372942544
Short name T926
Test name
Test status
Simulation time 173540623 ps
CPU time 0.76 seconds
Started Jul 14 07:15:41 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206884 kb
Host smart-0a2c5199-a05a-41d7-953c-45154e30cc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23729
42544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2372942544
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.103474466
Short name T1627
Test name
Test status
Simulation time 677148570 ps
CPU time 1.62 seconds
Started Jul 14 07:15:51 PM PDT 24
Finished Jul 14 07:17:47 PM PDT 24
Peak memory 207024 kb
Host smart-d7648b9f-8517-428b-b44d-22c23446acaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10347
4466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.103474466
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2949698975
Short name T2620
Test name
Test status
Simulation time 3856785149 ps
CPU time 34.24 seconds
Started Jul 14 07:15:50 PM PDT 24
Finished Jul 14 07:18:13 PM PDT 24
Peak memory 207308 kb
Host smart-c8a73a6d-a9c7-4e4c-a651-a9b853250b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496
98975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2949698975
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1682443103
Short name T1802
Test name
Test status
Simulation time 51114000 ps
CPU time 0.66 seconds
Started Jul 14 07:15:55 PM PDT 24
Finished Jul 14 07:17:40 PM PDT 24
Peak memory 206912 kb
Host smart-c14774ca-7daa-44e9-b6d1-cb18fc17c70c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1682443103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1682443103
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1882656821
Short name T13
Test name
Test status
Simulation time 4026535766 ps
CPU time 4.36 seconds
Started Jul 14 07:15:41 PM PDT 24
Finished Jul 14 07:17:46 PM PDT 24
Peak memory 206936 kb
Host smart-8aeab486-dd03-45d3-bf55-ad8eddf8d46c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1882656821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1882656821
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2586428742
Short name T781
Test name
Test status
Simulation time 13364107606 ps
CPU time 16.07 seconds
Started Jul 14 07:15:41 PM PDT 24
Finished Jul 14 07:18:02 PM PDT 24
Peak memory 206988 kb
Host smart-df50e1c6-1985-4b09-b54c-b37ff84d9c3e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2586428742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2586428742
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.1888547197
Short name T2524
Test name
Test status
Simulation time 23324139016 ps
CPU time 22.48 seconds
Started Jul 14 07:15:42 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 207140 kb
Host smart-7391792b-af94-45ea-9e6b-fe7ee1ff3e8a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1888547197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.1888547197
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.4060170830
Short name T1881
Test name
Test status
Simulation time 182720299 ps
CPU time 0.9 seconds
Started Jul 14 07:15:40 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206876 kb
Host smart-edcca68f-c690-43f1-8ce6-d038071f4eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40601
70830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.4060170830
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2699574047
Short name T969
Test name
Test status
Simulation time 163434489 ps
CPU time 0.79 seconds
Started Jul 14 07:15:41 PM PDT 24
Finished Jul 14 07:17:46 PM PDT 24
Peak memory 206840 kb
Host smart-4659019d-e302-4b49-bb03-81d433881133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26995
74047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2699574047
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.4283004169
Short name T537
Test name
Test status
Simulation time 449534481 ps
CPU time 1.26 seconds
Started Jul 14 07:15:41 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206916 kb
Host smart-5a1eff79-6722-44d6-80ee-d9d9e14952bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42830
04169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.4283004169
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2195359040
Short name T1267
Test name
Test status
Simulation time 1059378205 ps
CPU time 2.27 seconds
Started Jul 14 07:15:39 PM PDT 24
Finished Jul 14 07:17:43 PM PDT 24
Peak memory 207092 kb
Host smart-a24d89fa-8021-4973-a657-2b38e69378ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21953
59040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2195359040
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2839978391
Short name T181
Test name
Test status
Simulation time 8892844423 ps
CPU time 17.39 seconds
Started Jul 14 07:15:40 PM PDT 24
Finished Jul 14 07:17:59 PM PDT 24
Peak memory 207072 kb
Host smart-fad8e6bf-09be-424b-8e4d-74184dee870f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28399
78391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2839978391
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1483509879
Short name T1239
Test name
Test status
Simulation time 460033378 ps
CPU time 1.43 seconds
Started Jul 14 07:15:50 PM PDT 24
Finished Jul 14 07:17:43 PM PDT 24
Peak memory 206880 kb
Host smart-18ef44ac-7c4f-41e8-a3a3-2e77953dac2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14835
09879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1483509879
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1142853536
Short name T1222
Test name
Test status
Simulation time 142751274 ps
CPU time 0.74 seconds
Started Jul 14 07:15:45 PM PDT 24
Finished Jul 14 07:17:33 PM PDT 24
Peak memory 206880 kb
Host smart-c5eb8dbc-3064-443e-9236-dd8d904dac12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11428
53536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1142853536
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2204043302
Short name T223
Test name
Test status
Simulation time 35756121 ps
CPU time 0.63 seconds
Started Jul 14 07:15:49 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206880 kb
Host smart-2e459763-dc33-416f-a7f7-9e1e5e8921e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
43302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2204043302
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3509647467
Short name T379
Test name
Test status
Simulation time 893525228 ps
CPU time 2.11 seconds
Started Jul 14 07:15:48 PM PDT 24
Finished Jul 14 07:17:35 PM PDT 24
Peak memory 206988 kb
Host smart-24a2ba08-2ba6-4399-a057-312cd872ad1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35096
47467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3509647467
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.4236989789
Short name T930
Test name
Test status
Simulation time 252538512 ps
CPU time 1.4 seconds
Started Jul 14 07:15:49 PM PDT 24
Finished Jul 14 07:17:41 PM PDT 24
Peak memory 207000 kb
Host smart-c793dcb5-10ef-43d3-b0b5-c5bf42588d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42369
89789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4236989789
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2594495345
Short name T302
Test name
Test status
Simulation time 184711272 ps
CPU time 0.79 seconds
Started Jul 14 07:15:47 PM PDT 24
Finished Jul 14 07:17:41 PM PDT 24
Peak memory 206828 kb
Host smart-17fa06d9-9c2e-42ce-8626-71df8859f50f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25944
95345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2594495345
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3898366643
Short name T1702
Test name
Test status
Simulation time 143044008 ps
CPU time 0.77 seconds
Started Jul 14 07:15:47 PM PDT 24
Finished Jul 14 07:17:33 PM PDT 24
Peak memory 206860 kb
Host smart-a791a3c8-6396-4380-9555-b81aab8bad75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38983
66643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3898366643
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1984530927
Short name T439
Test name
Test status
Simulation time 212218286 ps
CPU time 0.86 seconds
Started Jul 14 07:15:47 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206844 kb
Host smart-268df6ad-4566-413b-ad9f-070509eb8793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
30927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1984530927
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.966619357
Short name T511
Test name
Test status
Simulation time 6353102462 ps
CPU time 55.89 seconds
Started Jul 14 07:15:49 PM PDT 24
Finished Jul 14 07:18:35 PM PDT 24
Peak memory 207060 kb
Host smart-21e8b6df-eb44-48b8-9e7f-e54bd4826623
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=966619357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.966619357
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.2447341301
Short name T2615
Test name
Test status
Simulation time 14009332225 ps
CPU time 42.09 seconds
Started Jul 14 07:15:44 PM PDT 24
Finished Jul 14 07:18:15 PM PDT 24
Peak memory 207148 kb
Host smart-36c505d9-69b8-4387-80bf-c0fde3437bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24473
41301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2447341301
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3948157069
Short name T660
Test name
Test status
Simulation time 217893382 ps
CPU time 0.87 seconds
Started Jul 14 07:15:49 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 207044 kb
Host smart-8618f8cc-09c5-4021-9c9d-6effa3cb6a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39481
57069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3948157069
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3404176404
Short name T1792
Test name
Test status
Simulation time 23373771687 ps
CPU time 24.77 seconds
Started Jul 14 07:15:48 PM PDT 24
Finished Jul 14 07:18:06 PM PDT 24
Peak memory 206868 kb
Host smart-7377cc05-b521-4766-a0c1-c0ef7e18e933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34041
76404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3404176404
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.942539333
Short name T1700
Test name
Test status
Simulation time 3314616810 ps
CPU time 3.68 seconds
Started Jul 14 07:15:48 PM PDT 24
Finished Jul 14 07:17:51 PM PDT 24
Peak memory 206892 kb
Host smart-b2f45e2e-ddee-42e6-87e6-abf5d6095253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94253
9333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.942539333
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.4235337337
Short name T2154
Test name
Test status
Simulation time 11884608160 ps
CPU time 318.53 seconds
Started Jul 14 07:15:47 PM PDT 24
Finished Jul 14 07:22:59 PM PDT 24
Peak memory 207128 kb
Host smart-6217210f-0434-449c-958d-cf3311461b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42353
37337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.4235337337
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.145979178
Short name T2465
Test name
Test status
Simulation time 6124990320 ps
CPU time 173.18 seconds
Started Jul 14 07:15:48 PM PDT 24
Finished Jul 14 07:20:26 PM PDT 24
Peak memory 207060 kb
Host smart-e367ec43-1d5a-4f82-a9a5-573c5dd78e43
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=145979178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.145979178
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3591745916
Short name T1124
Test name
Test status
Simulation time 253796536 ps
CPU time 0.91 seconds
Started Jul 14 07:15:52 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206912 kb
Host smart-c8af0b29-349f-4905-bdab-9a94089984c6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3591745916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3591745916
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3860375722
Short name T1197
Test name
Test status
Simulation time 220821591 ps
CPU time 0.86 seconds
Started Jul 14 07:15:51 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206808 kb
Host smart-36724e74-dfde-43b4-8ed3-269d7211ffb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603
75722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3860375722
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4222850895
Short name T1978
Test name
Test status
Simulation time 5576873693 ps
CPU time 54.26 seconds
Started Jul 14 07:15:52 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 207068 kb
Host smart-abe54ae8-1fd4-4368-a745-060189c864d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228
50895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4222850895
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3703088099
Short name T1965
Test name
Test status
Simulation time 3925291185 ps
CPU time 36.11 seconds
Started Jul 14 07:16:04 PM PDT 24
Finished Jul 14 07:18:23 PM PDT 24
Peak memory 207116 kb
Host smart-d3801430-b2b6-4b39-bc64-e3720102ff5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3703088099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3703088099
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3406450909
Short name T2045
Test name
Test status
Simulation time 176525853 ps
CPU time 0.8 seconds
Started Jul 14 07:15:49 PM PDT 24
Finished Jul 14 07:17:40 PM PDT 24
Peak memory 206888 kb
Host smart-0519ff82-a4bf-4fda-b2fd-4fd9fb9883c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3406450909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3406450909
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1205406033
Short name T1772
Test name
Test status
Simulation time 190995118 ps
CPU time 0.77 seconds
Started Jul 14 07:15:53 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206892 kb
Host smart-78eb668c-7c7c-468a-8bad-11650a64ba5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12054
06033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1205406033
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1869590494
Short name T1112
Test name
Test status
Simulation time 162245771 ps
CPU time 0.77 seconds
Started Jul 14 07:15:53 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206856 kb
Host smart-5f19f7fd-8304-4074-8edb-be34cff1f57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18695
90494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1869590494
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3576550970
Short name T1912
Test name
Test status
Simulation time 225161675 ps
CPU time 0.8 seconds
Started Jul 14 07:15:52 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206868 kb
Host smart-535d1497-7606-4ac2-8c39-4a611335dac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35765
50970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3576550970
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.567608239
Short name T2250
Test name
Test status
Simulation time 182684652 ps
CPU time 0.81 seconds
Started Jul 14 07:15:50 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206896 kb
Host smart-1d654ef4-7a04-42f1-99c0-be4ec2abb8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56760
8239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.567608239
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.814100255
Short name T2414
Test name
Test status
Simulation time 151082907 ps
CPU time 0.73 seconds
Started Jul 14 07:15:51 PM PDT 24
Finished Jul 14 07:17:46 PM PDT 24
Peak memory 206872 kb
Host smart-389e0231-f563-4e57-b7a2-2279f72a3f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81410
0255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.814100255
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.4202829315
Short name T1544
Test name
Test status
Simulation time 236407846 ps
CPU time 1.08 seconds
Started Jul 14 07:16:07 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206868 kb
Host smart-9f5fdf5e-9519-4425-86cc-64fae915ea4f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4202829315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.4202829315
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1600011874
Short name T1511
Test name
Test status
Simulation time 145227585 ps
CPU time 0.88 seconds
Started Jul 14 07:16:15 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206868 kb
Host smart-cea11cb2-056a-4020-af0e-61353a271506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16000
11874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1600011874
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1730968171
Short name T37
Test name
Test status
Simulation time 83104472 ps
CPU time 0.68 seconds
Started Jul 14 07:15:51 PM PDT 24
Finished Jul 14 07:17:45 PM PDT 24
Peak memory 206860 kb
Host smart-439aa0a6-5e4c-4b89-b0a8-78fc2aae01f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17309
68171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1730968171
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.421064195
Short name T1602
Test name
Test status
Simulation time 22929452597 ps
CPU time 49.29 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:49 PM PDT 24
Peak memory 207108 kb
Host smart-1a4e7304-27e8-4fd6-b074-98841cdaf305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42106
4195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.421064195
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.907935832
Short name T278
Test name
Test status
Simulation time 201414991 ps
CPU time 0.77 seconds
Started Jul 14 07:15:52 PM PDT 24
Finished Jul 14 07:17:40 PM PDT 24
Peak memory 206872 kb
Host smart-949c7c25-cc61-417a-b246-2e1220a0e45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90793
5832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.907935832
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2982860771
Short name T973
Test name
Test status
Simulation time 241321590 ps
CPU time 0.87 seconds
Started Jul 14 07:15:59 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206856 kb
Host smart-fefefc9f-5057-44e9-8f91-f0a4507ca9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29828
60771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2982860771
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1898142891
Short name T441
Test name
Test status
Simulation time 325145413 ps
CPU time 0.94 seconds
Started Jul 14 07:15:53 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206896 kb
Host smart-e88da6de-521a-46bc-825c-b8b3535f7fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18981
42891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1898142891
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2986947708
Short name T1285
Test name
Test status
Simulation time 168724901 ps
CPU time 0.75 seconds
Started Jul 14 07:15:54 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206840 kb
Host smart-6ada4b86-66bc-48fc-96c5-c8b76e8b6718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29869
47708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2986947708
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3776598136
Short name T1561
Test name
Test status
Simulation time 170219739 ps
CPU time 0.77 seconds
Started Jul 14 07:15:59 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206832 kb
Host smart-6f2149ed-434c-4744-a66f-58ca7a0ceaa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37765
98136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3776598136
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2309102204
Short name T791
Test name
Test status
Simulation time 157608722 ps
CPU time 0.73 seconds
Started Jul 14 07:15:54 PM PDT 24
Finished Jul 14 07:17:41 PM PDT 24
Peak memory 206836 kb
Host smart-8d4f1b54-8e41-4ebb-a577-cb815a0f2b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23091
02204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2309102204
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1049946250
Short name T2659
Test name
Test status
Simulation time 147267151 ps
CPU time 0.78 seconds
Started Jul 14 07:15:50 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206832 kb
Host smart-d8e8ec4a-3484-47c2-8235-2cb063cf58a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10499
46250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1049946250
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2243089586
Short name T498
Test name
Test status
Simulation time 222660590 ps
CPU time 0.85 seconds
Started Jul 14 07:15:52 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206868 kb
Host smart-cd4239b4-781c-4932-9ad4-f888eb6a6dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22430
89586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2243089586
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.734302761
Short name T1892
Test name
Test status
Simulation time 3905063694 ps
CPU time 106.43 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:19:45 PM PDT 24
Peak memory 207108 kb
Host smart-2488cdc0-7ce4-437a-9156-0024402d0235
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=734302761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.734302761
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1889795599
Short name T2681
Test name
Test status
Simulation time 199444483 ps
CPU time 0.8 seconds
Started Jul 14 07:15:52 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206876 kb
Host smart-512ea22e-0f8f-4d9a-bc3e-eea5e5ed1dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18897
95599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1889795599
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2224177496
Short name T2215
Test name
Test status
Simulation time 187675499 ps
CPU time 0.8 seconds
Started Jul 14 07:15:51 PM PDT 24
Finished Jul 14 07:17:42 PM PDT 24
Peak memory 206852 kb
Host smart-369f5c0f-5c27-4da0-a2a3-48e337fad67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22241
77496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2224177496
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3651586622
Short name T962
Test name
Test status
Simulation time 1357340919 ps
CPU time 2.79 seconds
Started Jul 14 07:15:58 PM PDT 24
Finished Jul 14 07:17:44 PM PDT 24
Peak memory 207064 kb
Host smart-a18332d0-4c16-4892-8352-3f2c598cad85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36515
86622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3651586622
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.156189478
Short name T769
Test name
Test status
Simulation time 4782696303 ps
CPU time 134.73 seconds
Started Jul 14 07:15:57 PM PDT 24
Finished Jul 14 07:19:56 PM PDT 24
Peak memory 207080 kb
Host smart-9e70a8c0-5255-42eb-be6a-ea6a7ae69920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618
9478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.156189478
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.985028669
Short name T2522
Test name
Test status
Simulation time 80627432 ps
CPU time 0.73 seconds
Started Jul 14 07:16:30 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206900 kb
Host smart-cd6ccfb7-38d0-44ce-8430-c6b13d0d79f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=985028669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.985028669
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3677284205
Short name T1034
Test name
Test status
Simulation time 3829849523 ps
CPU time 4.27 seconds
Started Jul 14 07:15:57 PM PDT 24
Finished Jul 14 07:17:45 PM PDT 24
Peak memory 207124 kb
Host smart-4466f77b-edd9-4fab-a13d-0b33fc263686
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3677284205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3677284205
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1920323172
Short name T1752
Test name
Test status
Simulation time 13380089596 ps
CPU time 13.84 seconds
Started Jul 14 07:15:57 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206940 kb
Host smart-e2bf4ae0-0233-4ec9-a0a9-3efca86da0b8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1920323172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1920323172
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3568483972
Short name T2222
Test name
Test status
Simulation time 164752832 ps
CPU time 0.78 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:00 PM PDT 24
Peak memory 206892 kb
Host smart-4e5fda1a-e7c7-428a-8895-7aa440701aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35684
83972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3568483972
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1110775019
Short name T2012
Test name
Test status
Simulation time 173582306 ps
CPU time 0.78 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:17:59 PM PDT 24
Peak memory 206872 kb
Host smart-f66c105d-e944-4f27-a72f-cb8e850728cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11107
75019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1110775019
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3626375931
Short name T1673
Test name
Test status
Simulation time 149598651 ps
CPU time 0.78 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:17:53 PM PDT 24
Peak memory 206880 kb
Host smart-49821b42-938d-4138-9381-486a5d12acd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36263
75931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3626375931
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2243748864
Short name T230
Test name
Test status
Simulation time 474145050 ps
CPU time 1.21 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:02 PM PDT 24
Peak memory 206828 kb
Host smart-d3de9f8b-c1e5-4286-b4b8-8f77d39fb25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
48864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2243748864
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.293183161
Short name T702
Test name
Test status
Simulation time 7983641722 ps
CPU time 15.48 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:18:08 PM PDT 24
Peak memory 207148 kb
Host smart-fe7c3430-2f33-48db-93da-83bfed7adca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
3161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.293183161
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1568244273
Short name T1713
Test name
Test status
Simulation time 343309027 ps
CPU time 1.05 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206888 kb
Host smart-9c3bd9cf-64ca-4dd2-81f4-495e03479a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15682
44273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1568244273
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3157931958
Short name T403
Test name
Test status
Simulation time 159203132 ps
CPU time 0.74 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:01 PM PDT 24
Peak memory 206892 kb
Host smart-2b9f34c6-1745-46f6-9216-33c267386c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31579
31958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3157931958
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3382843691
Short name T2690
Test name
Test status
Simulation time 43615733 ps
CPU time 0.67 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:01 PM PDT 24
Peak memory 206876 kb
Host smart-71de855d-2f30-4e9d-9c28-a38bc4f46e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33828
43691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3382843691
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.564609876
Short name T826
Test name
Test status
Simulation time 1095668463 ps
CPU time 2.23 seconds
Started Jul 14 07:16:10 PM PDT 24
Finished Jul 14 07:17:55 PM PDT 24
Peak memory 207012 kb
Host smart-1215a823-dc03-4ad2-a798-f51357774516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56460
9876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.564609876
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2417062204
Short name T721
Test name
Test status
Simulation time 341229611 ps
CPU time 2.11 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:17:55 PM PDT 24
Peak memory 206984 kb
Host smart-11be67eb-1e8a-49ff-9023-7b9058e520c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24170
62204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2417062204
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1075563080
Short name T1295
Test name
Test status
Simulation time 227759352 ps
CPU time 0.88 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:00 PM PDT 24
Peak memory 206860 kb
Host smart-60f18958-aaf4-44f5-9079-96b0eb9ac24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
63080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1075563080
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2324010492
Short name T1794
Test name
Test status
Simulation time 142941277 ps
CPU time 0.73 seconds
Started Jul 14 07:16:07 PM PDT 24
Finished Jul 14 07:17:57 PM PDT 24
Peak memory 206848 kb
Host smart-0ec25062-3dc8-40a9-8720-7e45cc99cb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23240
10492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2324010492
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.403028654
Short name T300
Test name
Test status
Simulation time 223323288 ps
CPU time 0.89 seconds
Started Jul 14 07:16:07 PM PDT 24
Finished Jul 14 07:17:48 PM PDT 24
Peak memory 206856 kb
Host smart-8ca03ee2-9eac-4df4-a072-953c574c0976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40302
8654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.403028654
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.1022753961
Short name T1504
Test name
Test status
Simulation time 7892030862 ps
CPU time 65.49 seconds
Started Jul 14 07:16:09 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 207120 kb
Host smart-1fa1f447-2e4a-4618-9027-91984a19cd28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10227
53961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.1022753961
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.824233067
Short name T2606
Test name
Test status
Simulation time 257351689 ps
CPU time 0.92 seconds
Started Jul 14 07:16:07 PM PDT 24
Finished Jul 14 07:17:49 PM PDT 24
Peak memory 206852 kb
Host smart-e6e99020-d3f0-4038-a5da-4c63063d9b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82423
3067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.824233067
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.3064420569
Short name T1315
Test name
Test status
Simulation time 23347829177 ps
CPU time 21.86 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:18:22 PM PDT 24
Peak memory 206940 kb
Host smart-4074bb6a-12a5-4124-a513-c0ee79f0e6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30644
20569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.3064420569
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.924365249
Short name T1370
Test name
Test status
Simulation time 3338755087 ps
CPU time 3.85 seconds
Started Jul 14 07:16:07 PM PDT 24
Finished Jul 14 07:17:51 PM PDT 24
Peak memory 206940 kb
Host smart-0f06e9b4-610e-48b4-827c-73751eb3c9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92436
5249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.924365249
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3980371060
Short name T1140
Test name
Test status
Simulation time 10435808395 ps
CPU time 301.41 seconds
Started Jul 14 07:16:08 PM PDT 24
Finished Jul 14 07:23:00 PM PDT 24
Peak memory 207164 kb
Host smart-2e332980-49d6-44e8-9513-87106f78d15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39803
71060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3980371060
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1617934697
Short name T1687
Test name
Test status
Simulation time 4938315943 ps
CPU time 136.22 seconds
Started Jul 14 07:16:15 PM PDT 24
Finished Jul 14 07:20:09 PM PDT 24
Peak memory 206932 kb
Host smart-6402b52b-6e98-413f-aabc-601dd7a63462
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1617934697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1617934697
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3479434512
Short name T1291
Test name
Test status
Simulation time 280833594 ps
CPU time 0.96 seconds
Started Jul 14 07:16:15 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206892 kb
Host smart-04c8bf47-ad0b-49f5-850c-946e592f2a51
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3479434512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3479434512
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.327289398
Short name T501
Test name
Test status
Simulation time 198930575 ps
CPU time 0.88 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206856 kb
Host smart-5fd3e17f-76f5-4272-8560-1ced0136b823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728
9398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.327289398
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.2347543125
Short name T2369
Test name
Test status
Simulation time 4340701751 ps
CPU time 39.27 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:18:32 PM PDT 24
Peak memory 207136 kb
Host smart-eca6bbc3-5ee9-4f15-b12a-82c22e7fe5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23475
43125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.2347543125
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.2619155342
Short name T994
Test name
Test status
Simulation time 5980995564 ps
CPU time 162.64 seconds
Started Jul 14 07:16:13 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 207236 kb
Host smart-43f4e42d-79e2-4002-9df5-a0c9eebf926a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2619155342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2619155342
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.4126007279
Short name T625
Test name
Test status
Simulation time 198515847 ps
CPU time 0.88 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206860 kb
Host smart-155f91be-2baa-4b70-88fd-63cdd2ef049c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4126007279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.4126007279
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3625504537
Short name T1349
Test name
Test status
Simulation time 166505519 ps
CPU time 0.75 seconds
Started Jul 14 07:16:11 PM PDT 24
Finished Jul 14 07:17:53 PM PDT 24
Peak memory 206884 kb
Host smart-4e5d61c2-08e3-4b59-9b24-4203e59d30cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36255
04537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3625504537
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1603992448
Short name T120
Test name
Test status
Simulation time 214670918 ps
CPU time 0.96 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206876 kb
Host smart-c7d0064b-c24d-478e-91e5-2e9f47bc1778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039
92448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1603992448
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3805858345
Short name T1326
Test name
Test status
Simulation time 169670030 ps
CPU time 0.86 seconds
Started Jul 14 07:16:16 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206872 kb
Host smart-1fcb69fa-4ea0-4f43-acdd-19519b322f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38058
58345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3805858345
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3595448475
Short name T1325
Test name
Test status
Simulation time 192815182 ps
CPU time 0.86 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206828 kb
Host smart-31ac89dc-dda2-478f-a69c-a21394f9a864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35954
48475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3595448475
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2152368900
Short name T2700
Test name
Test status
Simulation time 180520102 ps
CPU time 0.81 seconds
Started Jul 14 07:16:15 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206832 kb
Host smart-00666920-1f6d-41ac-ba63-aadfef2157b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21523
68900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2152368900
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3729652567
Short name T1609
Test name
Test status
Simulation time 176346682 ps
CPU time 0.82 seconds
Started Jul 14 07:16:13 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206860 kb
Host smart-e95dab61-d6ea-4787-904e-ec429369e3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37296
52567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3729652567
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2966110628
Short name T2492
Test name
Test status
Simulation time 268319685 ps
CPU time 0.94 seconds
Started Jul 14 07:16:16 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206864 kb
Host smart-7c0c7e84-ad1c-41d9-9d2a-0814944c6331
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2966110628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2966110628
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2799695360
Short name T2374
Test name
Test status
Simulation time 156551522 ps
CPU time 0.78 seconds
Started Jul 14 07:16:11 PM PDT 24
Finished Jul 14 07:17:53 PM PDT 24
Peak memory 206888 kb
Host smart-f5c8e358-a154-427c-9fc3-21456d98a70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27996
95360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2799695360
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2994597738
Short name T1866
Test name
Test status
Simulation time 41006252 ps
CPU time 0.66 seconds
Started Jul 14 07:16:14 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206848 kb
Host smart-074b8f74-32a9-4841-aef6-26e33291e10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
97738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2994597738
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2388053645
Short name T1216
Test name
Test status
Simulation time 15963869447 ps
CPU time 36.78 seconds
Started Jul 14 07:16:16 PM PDT 24
Finished Jul 14 07:18:30 PM PDT 24
Peak memory 207124 kb
Host smart-feead85e-ee80-4e8e-9cae-e9e11da8fcc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23880
53645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2388053645
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1732889743
Short name T2595
Test name
Test status
Simulation time 213371673 ps
CPU time 0.87 seconds
Started Jul 14 07:16:12 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206892 kb
Host smart-be703be3-30b3-4502-8925-e2e05fe7402b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17328
89743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1732889743
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2811751166
Short name T376
Test name
Test status
Simulation time 233045425 ps
CPU time 0.84 seconds
Started Jul 14 07:16:12 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206832 kb
Host smart-909438c3-b2f5-45a7-9720-0f81addaccc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28117
51166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2811751166
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3676475104
Short name T329
Test name
Test status
Simulation time 193524562 ps
CPU time 0.81 seconds
Started Jul 14 07:16:13 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206896 kb
Host smart-1786145b-6a73-4ddd-9f1f-e8b0f5283b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36764
75104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3676475104
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.4150615312
Short name T1812
Test name
Test status
Simulation time 186975082 ps
CPU time 0.81 seconds
Started Jul 14 07:16:12 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206820 kb
Host smart-0a9751b7-e514-4850-93e0-dd2b2b094044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
15312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.4150615312
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3895752095
Short name T2096
Test name
Test status
Simulation time 146847954 ps
CPU time 0.73 seconds
Started Jul 14 07:16:16 PM PDT 24
Finished Jul 14 07:17:54 PM PDT 24
Peak memory 206856 kb
Host smart-bc740a79-42c2-499a-aed3-22cea259bee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
52095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3895752095
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2545550017
Short name T2730
Test name
Test status
Simulation time 155953687 ps
CPU time 0.85 seconds
Started Jul 14 07:16:18 PM PDT 24
Finished Jul 14 07:18:00 PM PDT 24
Peak memory 206856 kb
Host smart-54932a43-c667-4c52-9c4b-ae506c6b8385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25455
50017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2545550017
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1731807002
Short name T2013
Test name
Test status
Simulation time 151591306 ps
CPU time 0.73 seconds
Started Jul 14 07:16:18 PM PDT 24
Finished Jul 14 07:18:00 PM PDT 24
Peak memory 206864 kb
Host smart-7baa30ce-71b3-413c-8a54-e8955195a0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17318
07002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1731807002
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.740613869
Short name T1790
Test name
Test status
Simulation time 259590986 ps
CPU time 0.96 seconds
Started Jul 14 07:16:19 PM PDT 24
Finished Jul 14 07:18:00 PM PDT 24
Peak memory 206804 kb
Host smart-1fb160c8-1d0c-47a0-bd0e-b3af5269e441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74061
3869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.740613869
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.4023845471
Short name T2210
Test name
Test status
Simulation time 6163035398 ps
CPU time 171.07 seconds
Started Jul 14 07:16:23 PM PDT 24
Finished Jul 14 07:20:52 PM PDT 24
Peak memory 207064 kb
Host smart-7ed30170-8537-471a-9838-8eaad39edc50
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4023845471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.4023845471
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3691892798
Short name T1743
Test name
Test status
Simulation time 209391787 ps
CPU time 0.88 seconds
Started Jul 14 07:16:23 PM PDT 24
Finished Jul 14 07:18:01 PM PDT 24
Peak memory 206884 kb
Host smart-43a5ae41-af23-4337-80be-bbb4f9e33bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36918
92798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3691892798
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.600749161
Short name T1878
Test name
Test status
Simulation time 181942346 ps
CPU time 0.8 seconds
Started Jul 14 07:16:24 PM PDT 24
Finished Jul 14 07:18:02 PM PDT 24
Peak memory 206844 kb
Host smart-0c37e5f3-a041-427b-b211-98609f444494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60074
9161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.600749161
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.4039661449
Short name T2662
Test name
Test status
Simulation time 959904405 ps
CPU time 2.24 seconds
Started Jul 14 07:16:22 PM PDT 24
Finished Jul 14 07:18:03 PM PDT 24
Peak memory 207032 kb
Host smart-2d56361e-10e5-4c51-a87e-82fff6c9d0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
61449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.4039661449
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1638759483
Short name T864
Test name
Test status
Simulation time 5167568246 ps
CPU time 37.32 seconds
Started Jul 14 07:16:21 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 207132 kb
Host smart-e64f6667-fb05-4760-bc48-cc8d8e8cae3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16387
59483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1638759483
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2544898181
Short name T492
Test name
Test status
Simulation time 42349065 ps
CPU time 0.66 seconds
Started Jul 14 07:16:47 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206912 kb
Host smart-0ed0fa25-824d-4056-81f4-d0679583403f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2544898181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2544898181
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.435768085
Short name T2469
Test name
Test status
Simulation time 3994540124 ps
CPU time 5.86 seconds
Started Jul 14 07:16:29 PM PDT 24
Finished Jul 14 07:18:09 PM PDT 24
Peak memory 206896 kb
Host smart-be664bac-69e3-4bba-8f95-672d2915d8d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=435768085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.435768085
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2408518718
Short name T570
Test name
Test status
Simulation time 13368326215 ps
CPU time 16.05 seconds
Started Jul 14 07:16:29 PM PDT 24
Finished Jul 14 07:18:19 PM PDT 24
Peak memory 206912 kb
Host smart-48dfeb70-493d-4f42-8c69-7663194ccf05
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2408518718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2408518718
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.420586525
Short name T804
Test name
Test status
Simulation time 23402525646 ps
CPU time 24.03 seconds
Started Jul 14 07:16:28 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206932 kb
Host smart-636c2cb8-a9ad-47c2-874b-7e2dfbe5b16d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=420586525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.420586525
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3685281710
Short name T1696
Test name
Test status
Simulation time 218902929 ps
CPU time 0.8 seconds
Started Jul 14 07:16:31 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206872 kb
Host smart-8c2d9f87-9fc4-4c26-8bf1-9399d7bff285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36852
81710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3685281710
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2555798283
Short name T427
Test name
Test status
Simulation time 251401000 ps
CPU time 1.02 seconds
Started Jul 14 07:16:29 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206840 kb
Host smart-b5eddafd-a4cd-474b-acda-3c72ed495dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25557
98283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2555798283
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1306463031
Short name T675
Test name
Test status
Simulation time 1315827220 ps
CPU time 2.86 seconds
Started Jul 14 07:16:29 PM PDT 24
Finished Jul 14 07:18:06 PM PDT 24
Peak memory 207052 kb
Host smart-3d5b9ef1-e5de-4579-9254-8361720c5ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13064
63031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1306463031
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.4219085482
Short name T542
Test name
Test status
Simulation time 21821171229 ps
CPU time 41.47 seconds
Started Jul 14 07:16:30 PM PDT 24
Finished Jul 14 07:18:45 PM PDT 24
Peak memory 207128 kb
Host smart-097ee483-fe22-4ccb-ae04-c23bc1b81b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42190
85482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.4219085482
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1641234950
Short name T692
Test name
Test status
Simulation time 449808750 ps
CPU time 1.22 seconds
Started Jul 14 07:16:29 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206876 kb
Host smart-d481546f-2782-4b01-bccf-a17039de186e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16412
34950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1641234950
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3571288454
Short name T803
Test name
Test status
Simulation time 137351552 ps
CPU time 0.79 seconds
Started Jul 14 07:16:29 PM PDT 24
Finished Jul 14 07:18:04 PM PDT 24
Peak memory 206860 kb
Host smart-c502a78e-7fdc-4039-b883-08979eeb353c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
88454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3571288454
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2045842258
Short name T868
Test name
Test status
Simulation time 63015791 ps
CPU time 0.69 seconds
Started Jul 14 07:16:36 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206764 kb
Host smart-9f00032b-e178-4f37-9079-9d5128d051ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20458
42258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2045842258
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3173347633
Short name T2504
Test name
Test status
Simulation time 801776579 ps
CPU time 1.85 seconds
Started Jul 14 07:16:33 PM PDT 24
Finished Jul 14 07:18:05 PM PDT 24
Peak memory 207084 kb
Host smart-65b0e293-c866-4c58-a72a-3092828436cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31733
47633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3173347633
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.74542498
Short name T2334
Test name
Test status
Simulation time 183139563 ps
CPU time 1.95 seconds
Started Jul 14 07:16:32 PM PDT 24
Finished Jul 14 07:18:05 PM PDT 24
Peak memory 207092 kb
Host smart-5ae366cd-7938-421c-969a-23eab2c92b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74542
498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.74542498
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1728622157
Short name T1580
Test name
Test status
Simulation time 158602553 ps
CPU time 0.81 seconds
Started Jul 14 07:16:36 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206772 kb
Host smart-384ca175-f72c-4e8a-90be-2f4630443782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17286
22157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1728622157
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.711923571
Short name T1934
Test name
Test status
Simulation time 162542735 ps
CPU time 0.79 seconds
Started Jul 14 07:16:36 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206840 kb
Host smart-9e92298b-7616-4257-b95f-315e8414d14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71192
3571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.711923571
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1953268960
Short name T1344
Test name
Test status
Simulation time 189859985 ps
CPU time 0.82 seconds
Started Jul 14 07:16:36 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206848 kb
Host smart-190bcc80-14e5-46bb-a3ce-8703e6dfaca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19532
68960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1953268960
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.1994813430
Short name T2308
Test name
Test status
Simulation time 7672605094 ps
CPU time 212.55 seconds
Started Jul 14 07:16:36 PM PDT 24
Finished Jul 14 07:21:43 PM PDT 24
Peak memory 207076 kb
Host smart-64950ac6-bc54-45b3-a55c-b438f3f92d57
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1994813430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1994813430
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.4278744619
Short name T2001
Test name
Test status
Simulation time 12294904074 ps
CPU time 102.53 seconds
Started Jul 14 07:16:35 PM PDT 24
Finished Jul 14 07:19:59 PM PDT 24
Peak memory 207132 kb
Host smart-d25a5f07-f0b6-480f-bc34-a28f2a43f2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42787
44619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.4278744619
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3901194481
Short name T1482
Test name
Test status
Simulation time 210876429 ps
CPU time 0.89 seconds
Started Jul 14 07:16:37 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206804 kb
Host smart-c76f87e6-6a75-4c74-a135-c85ab5850c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39011
94481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3901194481
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.276831151
Short name T1987
Test name
Test status
Simulation time 23348492539 ps
CPU time 27.31 seconds
Started Jul 14 07:16:36 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 206884 kb
Host smart-d2f37df5-29ec-456f-adef-e72e6804562b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27683
1151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.276831151
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.4040484387
Short name T1384
Test name
Test status
Simulation time 3274486031 ps
CPU time 3.84 seconds
Started Jul 14 07:16:35 PM PDT 24
Finished Jul 14 07:18:20 PM PDT 24
Peak memory 206908 kb
Host smart-72ed389b-30fb-438f-9d01-1238da6a5aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40404
84387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.4040484387
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1969576159
Short name T1843
Test name
Test status
Simulation time 9542188654 ps
CPU time 256.08 seconds
Started Jul 14 07:16:35 PM PDT 24
Finished Jul 14 07:22:26 PM PDT 24
Peak memory 207176 kb
Host smart-747a35c8-9e30-45d1-89a7-3072c9d00eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19695
76159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1969576159
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2176876507
Short name T561
Test name
Test status
Simulation time 5351768997 ps
CPU time 150.51 seconds
Started Jul 14 07:16:38 PM PDT 24
Finished Jul 14 07:20:42 PM PDT 24
Peak memory 207100 kb
Host smart-60c78288-35af-4eef-acb5-b192164be5b0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2176876507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2176876507
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.810826977
Short name T812
Test name
Test status
Simulation time 243023899 ps
CPU time 0.88 seconds
Started Jul 14 07:16:36 PM PDT 24
Finished Jul 14 07:18:11 PM PDT 24
Peak memory 206836 kb
Host smart-9ff60edd-a1ad-46b1-99fe-c4949072572d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=810826977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.810826977
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3853823774
Short name T75
Test name
Test status
Simulation time 239197801 ps
CPU time 0.91 seconds
Started Jul 14 07:16:34 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206892 kb
Host smart-385d87c2-7ba5-4c7c-9930-9ce0ee08037d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38538
23774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3853823774
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2346755751
Short name T1478
Test name
Test status
Simulation time 7405362503 ps
CPU time 206.15 seconds
Started Jul 14 07:16:31 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 207048 kb
Host smart-d3a5034f-93d0-44e3-a1ac-c1018c4fff1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23467
55751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2346755751
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.4104208332
Short name T1469
Test name
Test status
Simulation time 5473033906 ps
CPU time 48.03 seconds
Started Jul 14 07:16:40 PM PDT 24
Finished Jul 14 07:18:59 PM PDT 24
Peak memory 207124 kb
Host smart-caa44f5f-04d6-46e8-8070-a0255f445662
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4104208332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.4104208332
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1453296842
Short name T2589
Test name
Test status
Simulation time 155745643 ps
CPU time 0.76 seconds
Started Jul 14 07:16:44 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206884 kb
Host smart-f87eef86-14d8-44b3-a680-8b58294a82f2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1453296842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1453296842
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3659006377
Short name T2594
Test name
Test status
Simulation time 139388556 ps
CPU time 0.74 seconds
Started Jul 14 07:16:37 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206856 kb
Host smart-3af65206-0cad-4798-87cd-07ccd9c17d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36590
06377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3659006377
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.340411498
Short name T1477
Test name
Test status
Simulation time 170602205 ps
CPU time 0.82 seconds
Started Jul 14 07:16:38 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206844 kb
Host smart-01e64764-bc77-437a-934d-3c419e6b669f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34041
1498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.340411498
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2757523576
Short name T989
Test name
Test status
Simulation time 167764711 ps
CPU time 0.76 seconds
Started Jul 14 07:16:39 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206828 kb
Host smart-c8df1d60-a1f8-42de-a11e-a0d7b4494bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27575
23576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2757523576
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.4010434533
Short name T1270
Test name
Test status
Simulation time 148822442 ps
CPU time 0.75 seconds
Started Jul 14 07:16:39 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206840 kb
Host smart-36e41df3-b813-4ded-ae00-3d8130f1dc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40104
34533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.4010434533
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2985121884
Short name T167
Test name
Test status
Simulation time 212107836 ps
CPU time 0.87 seconds
Started Jul 14 07:16:37 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206888 kb
Host smart-f6223a25-198c-4b95-9841-993804a085c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29851
21884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2985121884
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.1061924239
Short name T1203
Test name
Test status
Simulation time 220416114 ps
CPU time 0.9 seconds
Started Jul 14 07:16:40 PM PDT 24
Finished Jul 14 07:18:06 PM PDT 24
Peak memory 206892 kb
Host smart-f9cd4251-7260-4ba1-a33e-6e6fd68fbf5e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1061924239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.1061924239
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.89176297
Short name T1553
Test name
Test status
Simulation time 153202127 ps
CPU time 0.76 seconds
Started Jul 14 07:16:40 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206860 kb
Host smart-97486aa2-17cb-48e9-9845-d445870f3146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89176
297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.89176297
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3176604775
Short name T1919
Test name
Test status
Simulation time 36319641 ps
CPU time 0.64 seconds
Started Jul 14 07:16:43 PM PDT 24
Finished Jul 14 07:18:10 PM PDT 24
Peak memory 206876 kb
Host smart-f37f479a-36f8-4e8e-a6b8-c85aa2467cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31766
04775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3176604775
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3201505044
Short name T1257
Test name
Test status
Simulation time 181763514 ps
CPU time 0.84 seconds
Started Jul 14 07:16:38 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206848 kb
Host smart-9bb6c783-98cb-4e86-991c-50f5782aac20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32015
05044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3201505044
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1938791606
Short name T749
Test name
Test status
Simulation time 246011397 ps
CPU time 0.87 seconds
Started Jul 14 07:16:40 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206872 kb
Host smart-0dbf986c-4b8f-4714-9575-3583eed826db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19387
91606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1938791606
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.1070564242
Short name T1927
Test name
Test status
Simulation time 224142580 ps
CPU time 0.84 seconds
Started Jul 14 07:16:37 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206876 kb
Host smart-1a1ea854-79b4-426e-b9d5-e172dc0edfe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
64242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.1070564242
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.578834822
Short name T2305
Test name
Test status
Simulation time 221833120 ps
CPU time 0.86 seconds
Started Jul 14 07:16:44 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 206844 kb
Host smart-c631c905-bc42-4fac-903d-8cb365f72f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57883
4822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.578834822
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2685314711
Short name T2325
Test name
Test status
Simulation time 135127645 ps
CPU time 0.76 seconds
Started Jul 14 07:16:46 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206844 kb
Host smart-b957acec-df7a-458d-b1c9-8a061d2e14f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26853
14711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2685314711
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.786262729
Short name T851
Test name
Test status
Simulation time 167185852 ps
CPU time 0.81 seconds
Started Jul 14 07:16:43 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206884 kb
Host smart-4af4b1bd-ee66-4da4-8597-93732499f4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78626
2729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.786262729
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3596617609
Short name T22
Test name
Test status
Simulation time 148296162 ps
CPU time 0.76 seconds
Started Jul 14 07:16:47 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206872 kb
Host smart-80465e1c-2f95-41c3-90ed-9b27176115d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35966
17609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3596617609
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1101184198
Short name T2372
Test name
Test status
Simulation time 210904617 ps
CPU time 0.91 seconds
Started Jul 14 07:16:46 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206868 kb
Host smart-6e9f8573-83f8-4f7f-94c8-a69e738aad7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11011
84198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1101184198
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2040329045
Short name T1697
Test name
Test status
Simulation time 4983737539 ps
CPU time 34.71 seconds
Started Jul 14 07:16:47 PM PDT 24
Finished Jul 14 07:18:46 PM PDT 24
Peak memory 207008 kb
Host smart-2ff4f66b-3e56-446f-a409-324cf38e4d69
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2040329045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2040329045
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2831253364
Short name T353
Test name
Test status
Simulation time 181852663 ps
CPU time 0.79 seconds
Started Jul 14 07:16:44 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206868 kb
Host smart-070e037f-61f7-4c60-9333-efe14fd5d361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28312
53364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2831253364
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2665861119
Short name T456
Test name
Test status
Simulation time 155448946 ps
CPU time 0.8 seconds
Started Jul 14 07:16:43 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206812 kb
Host smart-9161f610-9990-43d7-9b23-5275aea6dd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658
61119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2665861119
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.706989793
Short name T419
Test name
Test status
Simulation time 575780332 ps
CPU time 1.49 seconds
Started Jul 14 07:16:42 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206884 kb
Host smart-8fcfd8ed-5e54-4db1-bbd8-5cf526ff3644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70698
9793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.706989793
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2571083775
Short name T474
Test name
Test status
Simulation time 5974923706 ps
CPU time 171.46 seconds
Started Jul 14 07:16:47 PM PDT 24
Finished Jul 14 07:21:03 PM PDT 24
Peak memory 207044 kb
Host smart-98b8fe87-9c2b-4697-a4c9-bc2116421beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25710
83775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2571083775
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3400899496
Short name T536
Test name
Test status
Simulation time 53780690 ps
CPU time 0.69 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206928 kb
Host smart-ccf9b5f0-9e11-427b-966e-0e098c481db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3400899496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3400899496
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2726398019
Short name T1249
Test name
Test status
Simulation time 3979445687 ps
CPU time 4.47 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:08 PM PDT 24
Peak memory 206912 kb
Host smart-8e4e428e-d131-47b1-9974-39d6367deb8d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2726398019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.2726398019
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.4050549716
Short name T1046
Test name
Test status
Simulation time 13414576456 ps
CPU time 13.78 seconds
Started Jul 14 07:12:47 PM PDT 24
Finished Jul 14 07:13:19 PM PDT 24
Peak memory 207072 kb
Host smart-b8dbaf50-e70e-43e3-a3ed-96a45ee1a16c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4050549716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.4050549716
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2463310462
Short name T606
Test name
Test status
Simulation time 23511173100 ps
CPU time 23.82 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:28 PM PDT 24
Peak memory 207040 kb
Host smart-e6145819-b28b-403b-b9ac-006f80e90789
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2463310462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2463310462
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2679810227
Short name T2671
Test name
Test status
Simulation time 177321256 ps
CPU time 0.88 seconds
Started Jul 14 07:12:48 PM PDT 24
Finished Jul 14 07:13:06 PM PDT 24
Peak memory 206692 kb
Host smart-b33b6d5b-8778-4a17-93b6-fc7b54f2e35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26798
10227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2679810227
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1731141443
Short name T56
Test name
Test status
Simulation time 175773885 ps
CPU time 0.83 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206868 kb
Host smart-6a5fae54-95cb-4785-b682-aae8104486b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17311
41443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1731141443
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3595868328
Short name T2257
Test name
Test status
Simulation time 149421845 ps
CPU time 0.76 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:12:59 PM PDT 24
Peak memory 206888 kb
Host smart-2ca77f97-098f-404d-b062-6898f9cce48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35958
68328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3595868328
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3958487177
Short name T1905
Test name
Test status
Simulation time 441407887 ps
CPU time 1.37 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:14 PM PDT 24
Peak memory 206828 kb
Host smart-a12d9d4a-eabf-4772-982f-0bfb89f47aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39584
87177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3958487177
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.622528018
Short name T598
Test name
Test status
Simulation time 1207796987 ps
CPU time 2.66 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:07 PM PDT 24
Peak memory 207132 kb
Host smart-e04b84cb-4132-495b-8ad6-524ba225680f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62252
8018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.622528018
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.4188179938
Short name T2451
Test name
Test status
Simulation time 20052370581 ps
CPU time 36.96 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 207100 kb
Host smart-9d586acc-ee5b-46b3-821b-f3d44eb83ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41881
79938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.4188179938
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.4151655549
Short name T1451
Test name
Test status
Simulation time 386199970 ps
CPU time 1.16 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206876 kb
Host smart-6ffc4832-01be-4184-8fa9-95f61068f398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41516
55549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.4151655549
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.920234818
Short name T2156
Test name
Test status
Simulation time 140745631 ps
CPU time 0.78 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206928 kb
Host smart-1ff5db20-901d-40b3-9096-e1e8104921c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92023
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.920234818
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.4218057208
Short name T364
Test name
Test status
Simulation time 39031774 ps
CPU time 0.68 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206860 kb
Host smart-77b71ca6-5ce6-420b-853a-48351c452ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42180
57208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.4218057208
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.479387708
Short name T331
Test name
Test status
Simulation time 911530938 ps
CPU time 2.06 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:13:04 PM PDT 24
Peak memory 207116 kb
Host smart-d011ac30-f2b3-4847-84d5-f60ac7481785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47938
7708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.479387708
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1522837804
Short name T1508
Test name
Test status
Simulation time 174331367 ps
CPU time 1.77 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 207088 kb
Host smart-5ce30ce6-54ad-43a5-a1a4-f420f397507a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15228
37804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1522837804
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3328938248
Short name T2355
Test name
Test status
Simulation time 111185755586 ps
CPU time 137.83 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:15:18 PM PDT 24
Peak memory 207076 kb
Host smart-b1cd9e5e-4ac9-4d3b-bbad-2ae64239764f
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3328938248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3328938248
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.624051334
Short name T2668
Test name
Test status
Simulation time 85292256694 ps
CPU time 107.84 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:14:47 PM PDT 24
Peak memory 207128 kb
Host smart-2ba77ad5-da26-499b-8a19-8c2cb1d88768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624051334 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.624051334
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.2444026086
Short name T1855
Test name
Test status
Simulation time 116093716302 ps
CPU time 148.03 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:15:39 PM PDT 24
Peak memory 207132 kb
Host smart-c31607ea-141b-400d-a0a3-94feec2efd50
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2444026086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2444026086
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.3666285972
Short name T378
Test name
Test status
Simulation time 89188770358 ps
CPU time 117.15 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:14:58 PM PDT 24
Peak memory 207132 kb
Host smart-a8e925ae-f656-4e16-b691-3569f567ccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666285972 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.3666285972
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3295295693
Short name T2197
Test name
Test status
Simulation time 85119766045 ps
CPU time 118.73 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:15:03 PM PDT 24
Peak memory 207008 kb
Host smart-5711623f-994b-463a-9af7-e3f2a42c77a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32952
95693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3295295693
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3225035026
Short name T1223
Test name
Test status
Simulation time 205083111 ps
CPU time 0.88 seconds
Started Jul 14 07:12:47 PM PDT 24
Finished Jul 14 07:13:06 PM PDT 24
Peak memory 206860 kb
Host smart-c9826003-1c1a-493b-890d-be6d69f35d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32250
35026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3225035026
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.543117334
Short name T1465
Test name
Test status
Simulation time 143083392 ps
CPU time 0.73 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:11 PM PDT 24
Peak memory 206864 kb
Host smart-8007d1e9-de59-4b3f-9393-270f448c0645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54311
7334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.543117334
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2024344979
Short name T1726
Test name
Test status
Simulation time 267319017 ps
CPU time 1.02 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206856 kb
Host smart-d3bb5bfd-4ea0-49f0-8813-6bb1b379619c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20243
44979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2024344979
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1300481529
Short name T1796
Test name
Test status
Simulation time 172628223 ps
CPU time 0.83 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:13:03 PM PDT 24
Peak memory 206824 kb
Host smart-aa57d7b7-8995-4ca4-bc15-b71b26588b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13004
81529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1300481529
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1576561795
Short name T2166
Test name
Test status
Simulation time 23367703221 ps
CPU time 24.38 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:13:24 PM PDT 24
Peak memory 206896 kb
Host smart-ef69ec88-eb22-42ad-aa78-16442d4117c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15765
61795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1576561795
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.4222730148
Short name T345
Test name
Test status
Simulation time 3329034657 ps
CPU time 4.05 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:13:03 PM PDT 24
Peak memory 206948 kb
Host smart-bc51d79a-69c2-4b50-b035-e030be544b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42227
30148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.4222730148
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.999545704
Short name T1079
Test name
Test status
Simulation time 9178447216 ps
CPU time 255.43 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:17:13 PM PDT 24
Peak memory 207124 kb
Host smart-119fb3ef-3577-4792-8bb3-367a615d148f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99954
5704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.999545704
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1528926396
Short name T897
Test name
Test status
Simulation time 3389973122 ps
CPU time 23.52 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:27 PM PDT 24
Peak memory 207124 kb
Host smart-4641bdc5-2bc0-4d1f-9f5e-34fc4185b3be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1528926396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1528926396
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3663278287
Short name T894
Test name
Test status
Simulation time 246108827 ps
CPU time 0.86 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:12:58 PM PDT 24
Peak memory 206872 kb
Host smart-eb4d5bb8-e5f1-4fbc-943e-d0a44a72cb0d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3663278287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3663278287
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2931847034
Short name T321
Test name
Test status
Simulation time 183557331 ps
CPU time 0.89 seconds
Started Jul 14 07:12:47 PM PDT 24
Finished Jul 14 07:13:06 PM PDT 24
Peak memory 206892 kb
Host smart-10db7da6-2472-41a8-a446-b65aa8d6fa99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
47034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2931847034
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3295711862
Short name T972
Test name
Test status
Simulation time 6692986217 ps
CPU time 46.52 seconds
Started Jul 14 07:12:47 PM PDT 24
Finished Jul 14 07:13:51 PM PDT 24
Peak memory 207084 kb
Host smart-bb2f7d1d-d253-4886-b635-eb2a26c29e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32957
11862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3295711862
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1943522683
Short name T429
Test name
Test status
Simulation time 4270892907 ps
CPU time 29.7 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:34 PM PDT 24
Peak memory 207116 kb
Host smart-0d7e3d55-e66e-4cb5-9e1d-b453087c970f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1943522683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1943522683
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3834933740
Short name T1083
Test name
Test status
Simulation time 188398750 ps
CPU time 0.8 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206748 kb
Host smart-58b86812-149f-496a-96ba-184004d31de7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3834933740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3834933740
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1280927347
Short name T2042
Test name
Test status
Simulation time 152476054 ps
CPU time 0.81 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206896 kb
Host smart-8e26dc25-8052-493c-81cc-46c9712bbb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12809
27347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1280927347
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2960226123
Short name T104
Test name
Test status
Simulation time 229789232 ps
CPU time 0.87 seconds
Started Jul 14 07:12:43 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206888 kb
Host smart-b7fc20ed-e600-4686-a78f-8b2fc4262133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29602
26123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2960226123
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3024877819
Short name T516
Test name
Test status
Simulation time 208409567 ps
CPU time 0.88 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:06 PM PDT 24
Peak memory 206840 kb
Host smart-2ef14cb8-f4c3-4897-9014-9c52d6042af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30248
77819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3024877819
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2106110964
Short name T880
Test name
Test status
Simulation time 184903484 ps
CPU time 0.83 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206832 kb
Host smart-454b2963-8a30-4ff0-81b8-19d37e1e37e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21061
10964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2106110964
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1662269652
Short name T2415
Test name
Test status
Simulation time 198219136 ps
CPU time 0.8 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206856 kb
Host smart-e93ca631-5243-4ea6-8b82-639e74e34093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16622
69652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1662269652
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.295719544
Short name T1636
Test name
Test status
Simulation time 151789911 ps
CPU time 0.76 seconds
Started Jul 14 07:12:44 PM PDT 24
Finished Jul 14 07:13:00 PM PDT 24
Peak memory 206876 kb
Host smart-8c6a1021-85c1-415e-9110-5819ec75cda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29571
9544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.295719544
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2864503049
Short name T1
Test name
Test status
Simulation time 210344188 ps
CPU time 0.94 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206880 kb
Host smart-69ce3629-286f-49d4-bd66-16492c1613b4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2864503049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2864503049
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.4244782621
Short name T202
Test name
Test status
Simulation time 200341139 ps
CPU time 0.93 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:13:03 PM PDT 24
Peak memory 206860 kb
Host smart-76e7e6cb-885a-4aed-a38e-1de64fac8361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42447
82621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.4244782621
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2641576031
Short name T1725
Test name
Test status
Simulation time 145244571 ps
CPU time 0.78 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206880 kb
Host smart-e96a20ea-7a9f-4dda-887d-ed1aa1dc5c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26415
76031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2641576031
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3767770278
Short name T2629
Test name
Test status
Simulation time 74820196 ps
CPU time 0.67 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206884 kb
Host smart-91a88e43-c5e4-44d8-b46f-0eebf2edb1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37677
70278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3767770278
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2875569371
Short name T246
Test name
Test status
Simulation time 8975079873 ps
CPU time 21.28 seconds
Started Jul 14 07:12:45 PM PDT 24
Finished Jul 14 07:13:23 PM PDT 24
Peak memory 207080 kb
Host smart-20cf6fca-bfbe-4eb5-a22f-5c5baa013035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
69371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2875569371
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2184660050
Short name T604
Test name
Test status
Simulation time 155081525 ps
CPU time 0.79 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206896 kb
Host smart-6a40ea18-f10a-4369-8e3d-3d2d29de221c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
60050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2184660050
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1399370125
Short name T442
Test name
Test status
Simulation time 225747948 ps
CPU time 0.85 seconds
Started Jul 14 07:12:46 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 206888 kb
Host smart-3777c3eb-3730-462d-a781-54873bd01ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13993
70125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1399370125
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3544070600
Short name T1059
Test name
Test status
Simulation time 14067619464 ps
CPU time 115.99 seconds
Started Jul 14 07:12:49 PM PDT 24
Finished Jul 14 07:15:02 PM PDT 24
Peak memory 207176 kb
Host smart-07cc49f3-fd75-4e0a-bbfb-5dd18e6618cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3544070600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3544070600
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.538118434
Short name T2026
Test name
Test status
Simulation time 23879261521 ps
CPU time 142.25 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:15:42 PM PDT 24
Peak memory 207056 kb
Host smart-e1ce51b5-4a99-4a86-a267-9fe8da3c2a96
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=538118434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.538118434
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3329766337
Short name T954
Test name
Test status
Simulation time 236332183 ps
CPU time 0.88 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206896 kb
Host smart-281541ae-cad3-45ca-9426-cbeccec99cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33297
66337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3329766337
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.3623335575
Short name T19
Test name
Test status
Simulation time 185119927 ps
CPU time 0.84 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:10 PM PDT 24
Peak memory 206884 kb
Host smart-d7b1591e-8077-4786-b13f-19db835d807c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36233
35575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.3623335575
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1822549881
Short name T2718
Test name
Test status
Simulation time 156331040 ps
CPU time 0.76 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206868 kb
Host smart-c5a89ce5-1b4a-4b5f-a75d-419688be0741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18225
49881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1822549881
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.4155364075
Short name T2240
Test name
Test status
Simulation time 168123857 ps
CPU time 0.8 seconds
Started Jul 14 07:12:58 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206892 kb
Host smart-667a48f1-80dd-4689-857f-594f7ac95c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553
64075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.4155364075
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1143795181
Short name T195
Test name
Test status
Simulation time 461077376 ps
CPU time 1.31 seconds
Started Jul 14 07:12:59 PM PDT 24
Finished Jul 14 07:13:19 PM PDT 24
Peak memory 225564 kb
Host smart-391b88a6-0bd9-4aa9-8061-4c409f79e247
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1143795181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1143795181
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.4230851492
Short name T50
Test name
Test status
Simulation time 352651159 ps
CPU time 1.17 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:13:12 PM PDT 24
Peak memory 206884 kb
Host smart-3481152e-7621-4268-8dbe-b809a4430dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42308
51492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.4230851492
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.1090422863
Short name T2495
Test name
Test status
Simulation time 174140625 ps
CPU time 0.85 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206836 kb
Host smart-0d3faf67-6560-42db-96b8-8d5f39b2da5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904
22863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1090422863
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3335952788
Short name T1956
Test name
Test status
Simulation time 179414826 ps
CPU time 0.77 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206912 kb
Host smart-4cec09c0-384a-4525-a97e-8f5f5b1022eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33359
52788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3335952788
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2917007236
Short name T2626
Test name
Test status
Simulation time 151742659 ps
CPU time 0.77 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206828 kb
Host smart-f3c76527-7351-4aed-9685-6ad74380f149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29170
07236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2917007236
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.816062149
Short name T1883
Test name
Test status
Simulation time 216168870 ps
CPU time 0.87 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:13:11 PM PDT 24
Peak memory 206840 kb
Host smart-b7cfaf5e-9051-41db-8415-a570605ad6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81606
2149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.816062149
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.2828085060
Short name T1736
Test name
Test status
Simulation time 3694886211 ps
CPU time 25.35 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 207148 kb
Host smart-2f8c2c66-4448-4ebb-851d-fa15d18958a5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2828085060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.2828085060
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.4007784522
Short name T709
Test name
Test status
Simulation time 201742951 ps
CPU time 0.82 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206812 kb
Host smart-8be54a56-9bdf-4832-9e11-3abc3d67b1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
84522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.4007784522
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3915405921
Short name T2354
Test name
Test status
Simulation time 192718514 ps
CPU time 0.89 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206840 kb
Host smart-c106dcca-fc97-4dbb-8adf-bb02333725f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154
05921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3915405921
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1706875239
Short name T2081
Test name
Test status
Simulation time 555240604 ps
CPU time 1.53 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:11 PM PDT 24
Peak memory 206852 kb
Host smart-0b94d4f2-a038-440e-888a-20d9d545a0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068
75239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1706875239
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.18372504
Short name T161
Test name
Test status
Simulation time 5279774023 ps
CPU time 50.56 seconds
Started Jul 14 07:12:48 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 207120 kb
Host smart-e18ea83e-bea9-4355-905d-409e3f8bcb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18372
504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.18372504
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.718747997
Short name T1407
Test name
Test status
Simulation time 72037533 ps
CPU time 0.68 seconds
Started Jul 14 07:17:05 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206844 kb
Host smart-960c94a6-44e4-418f-bfce-9913177e8f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=718747997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.718747997
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1286426837
Short name T514
Test name
Test status
Simulation time 3823036018 ps
CPU time 4.53 seconds
Started Jul 14 07:16:49 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 206924 kb
Host smart-6b770fed-73c4-4056-97e4-8e0c6051ed30
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1286426837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1286426837
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3486609198
Short name T2672
Test name
Test status
Simulation time 13411146208 ps
CPU time 12.71 seconds
Started Jul 14 07:16:43 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206944 kb
Host smart-98bed3bf-e6a6-49e6-8bf8-70bb93eecd85
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3486609198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3486609198
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.4217424337
Short name T2481
Test name
Test status
Simulation time 23419254115 ps
CPU time 23.46 seconds
Started Jul 14 07:16:44 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 207036 kb
Host smart-fbe0cec4-f481-46a7-850e-a551351e8fb0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4217424337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.4217424337
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3705552895
Short name T2490
Test name
Test status
Simulation time 177269985 ps
CPU time 0.81 seconds
Started Jul 14 07:16:44 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206860 kb
Host smart-57708c7f-baeb-4dcd-b6e7-559852affce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37055
52895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3705552895
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2050178732
Short name T393
Test name
Test status
Simulation time 174401316 ps
CPU time 0.83 seconds
Started Jul 14 07:16:46 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206872 kb
Host smart-c7a8f7be-c958-409c-a78b-0b5c4530cfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20501
78732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2050178732
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3391072074
Short name T685
Test name
Test status
Simulation time 368291148 ps
CPU time 1.19 seconds
Started Jul 14 07:16:49 PM PDT 24
Finished Jul 14 07:18:13 PM PDT 24
Peak memory 206816 kb
Host smart-6a643f55-e72c-428c-842c-eac7bb6fdc67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33910
72074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3391072074
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.38661630
Short name T2078
Test name
Test status
Simulation time 1143524266 ps
CPU time 2.39 seconds
Started Jul 14 07:16:49 PM PDT 24
Finished Jul 14 07:18:14 PM PDT 24
Peak memory 207056 kb
Host smart-46c7e9d5-fb2f-4f39-a6ff-e9757c49bc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38661
630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.38661630
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.744266382
Short name T2484
Test name
Test status
Simulation time 18304590201 ps
CPU time 30.67 seconds
Started Jul 14 07:16:47 PM PDT 24
Finished Jul 14 07:18:42 PM PDT 24
Peak memory 206940 kb
Host smart-82da58a9-611b-4490-8a1b-1fb04bf88227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74426
6382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.744266382
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1305251247
Short name T2732
Test name
Test status
Simulation time 370583659 ps
CPU time 1.17 seconds
Started Jul 14 07:16:42 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206872 kb
Host smart-bd859156-a1e2-40e0-9d36-d4bcb3f4522f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13052
51247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1305251247
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1547483418
Short name T1292
Test name
Test status
Simulation time 140949304 ps
CPU time 0.77 seconds
Started Jul 14 07:16:49 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 206844 kb
Host smart-f8bbc278-534f-43a9-83c6-6ada173506cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15474
83418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1547483418
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.520705879
Short name T1167
Test name
Test status
Simulation time 102433558 ps
CPU time 0.69 seconds
Started Jul 14 07:16:53 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 206868 kb
Host smart-4ef57140-b972-4999-97be-be1aa21d0d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52070
5879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.520705879
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3432338356
Short name T328
Test name
Test status
Simulation time 1013026724 ps
CPU time 2.14 seconds
Started Jul 14 07:16:47 PM PDT 24
Finished Jul 14 07:18:14 PM PDT 24
Peak memory 207012 kb
Host smart-7230751f-a85c-4637-9563-64fd7267513d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34323
38356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3432338356
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3967353086
Short name T1998
Test name
Test status
Simulation time 240891410 ps
CPU time 2.2 seconds
Started Jul 14 07:16:48 PM PDT 24
Finished Jul 14 07:18:14 PM PDT 24
Peak memory 207012 kb
Host smart-15f999f3-b2b6-4c7b-843d-45fa31438703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39673
53086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3967353086
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.778573889
Short name T1748
Test name
Test status
Simulation time 213024955 ps
CPU time 0.85 seconds
Started Jul 14 07:16:55 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206872 kb
Host smart-cd19e970-dc85-4e20-bea2-6798bfdbf558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77857
3889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.778573889
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1047387808
Short name T103
Test name
Test status
Simulation time 220488588 ps
CPU time 0.78 seconds
Started Jul 14 07:16:55 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206868 kb
Host smart-9b33eb76-5247-44c2-a687-88da060417bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10473
87808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1047387808
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.631159421
Short name T1304
Test name
Test status
Simulation time 188392741 ps
CPU time 0.82 seconds
Started Jul 14 07:16:55 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206868 kb
Host smart-c3c8b3f5-02f7-4f28-ba5e-44b68935e473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63115
9421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.631159421
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.1730041105
Short name T2310
Test name
Test status
Simulation time 9278984085 ps
CPU time 261.44 seconds
Started Jul 14 07:16:53 PM PDT 24
Finished Jul 14 07:22:37 PM PDT 24
Peak memory 207112 kb
Host smart-ba5db7bc-ae25-4395-99be-82f170be6384
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1730041105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.1730041105
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.3423354000
Short name T2167
Test name
Test status
Simulation time 12972573131 ps
CPU time 40.36 seconds
Started Jul 14 07:16:52 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 207076 kb
Host smart-02f06cc6-aa48-45df-a0c0-46a97144ede7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34233
54000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.3423354000
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.4104874658
Short name T2059
Test name
Test status
Simulation time 202252172 ps
CPU time 0.85 seconds
Started Jul 14 07:16:53 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206852 kb
Host smart-ae5a2135-9ec6-4917-bfb9-145b636044cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41048
74658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.4104874658
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.609049712
Short name T581
Test name
Test status
Simulation time 23307241919 ps
CPU time 28.42 seconds
Started Jul 14 07:16:54 PM PDT 24
Finished Jul 14 07:18:43 PM PDT 24
Peak memory 206920 kb
Host smart-4f4ded59-db0e-43ce-b47a-5be975c9857c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60904
9712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.609049712
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2146280527
Short name T2043
Test name
Test status
Simulation time 3315799050 ps
CPU time 3.97 seconds
Started Jul 14 07:16:54 PM PDT 24
Finished Jul 14 07:18:21 PM PDT 24
Peak memory 206920 kb
Host smart-807a83d0-7ee4-4d7e-972d-81b945b43a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21462
80527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2146280527
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.721313071
Short name T848
Test name
Test status
Simulation time 8444871120 ps
CPU time 84.11 seconds
Started Jul 14 07:16:53 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 207156 kb
Host smart-d771aa1a-b2c2-4f94-b4d3-e5913e933c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72131
3071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.721313071
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2577323722
Short name T1954
Test name
Test status
Simulation time 4869887452 ps
CPU time 33.89 seconds
Started Jul 14 07:17:00 PM PDT 24
Finished Jul 14 07:18:50 PM PDT 24
Peak memory 207124 kb
Host smart-2d16dddd-727f-4cb3-adb1-ed81347f6012
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2577323722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2577323722
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1949886265
Short name T1699
Test name
Test status
Simulation time 246646325 ps
CPU time 0.9 seconds
Started Jul 14 07:16:55 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206828 kb
Host smart-a074fc2a-4518-46f2-b85c-b81708e7efbf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1949886265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1949886265
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2710447634
Short name T884
Test name
Test status
Simulation time 186146937 ps
CPU time 0.89 seconds
Started Jul 14 07:16:54 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 206824 kb
Host smart-8a8721cc-f1fc-45a1-8e5b-4e8705dc5626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104
47634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2710447634
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.918808082
Short name T1567
Test name
Test status
Simulation time 3993002432 ps
CPU time 27.53 seconds
Started Jul 14 07:16:53 PM PDT 24
Finished Jul 14 07:18:43 PM PDT 24
Peak memory 207136 kb
Host smart-844b9109-5480-41cd-918c-c1a63b503213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91880
8082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.918808082
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2809538262
Short name T1316
Test name
Test status
Simulation time 3347576831 ps
CPU time 23.3 seconds
Started Jul 14 07:16:55 PM PDT 24
Finished Jul 14 07:18:40 PM PDT 24
Peak memory 207128 kb
Host smart-3994264c-468b-421e-9554-2acc56282d56
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2809538262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2809538262
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1463809297
Short name T2068
Test name
Test status
Simulation time 225854213 ps
CPU time 0.81 seconds
Started Jul 14 07:16:56 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206852 kb
Host smart-9cadf041-386d-49a7-bf24-b98ca0232b1a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1463809297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1463809297
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.11954001
Short name T1330
Test name
Test status
Simulation time 146501207 ps
CPU time 0.77 seconds
Started Jul 14 07:17:00 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206868 kb
Host smart-a4538859-1e40-4a13-9e97-40fbe3e0ca94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11954
001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.11954001
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.70558800
Short name T2499
Test name
Test status
Simulation time 183119753 ps
CPU time 0.83 seconds
Started Jul 14 07:16:54 PM PDT 24
Finished Jul 14 07:18:18 PM PDT 24
Peak memory 206876 kb
Host smart-4dc52fbb-f017-45e6-9577-0283cbee48ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70558
800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.70558800
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2413240291
Short name T2072
Test name
Test status
Simulation time 146139307 ps
CPU time 0.8 seconds
Started Jul 14 07:16:54 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206900 kb
Host smart-83f41ad4-dbc3-4aba-9e5b-283c51471bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24132
40291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2413240291
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1448175601
Short name T1489
Test name
Test status
Simulation time 170757395 ps
CPU time 0.78 seconds
Started Jul 14 07:17:04 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206880 kb
Host smart-3a2b3d15-421c-4afc-8ea8-84a2e2b070b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14481
75601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1448175601
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3685828061
Short name T475
Test name
Test status
Simulation time 169224068 ps
CPU time 0.81 seconds
Started Jul 14 07:16:58 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 206916 kb
Host smart-06a9bee0-ba6b-4b9a-a773-0afa6e953ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36858
28061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3685828061
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.95905407
Short name T1417
Test name
Test status
Simulation time 152377400 ps
CPU time 0.75 seconds
Started Jul 14 07:17:04 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206888 kb
Host smart-1f131f7f-3a16-40fe-8d3f-47632d4c36b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95905
407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.95905407
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.7639994
Short name T1378
Test name
Test status
Simulation time 196040709 ps
CPU time 0.88 seconds
Started Jul 14 07:17:00 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206876 kb
Host smart-5a1cdb68-88ff-44d5-bcee-ab583ff3d7bb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=7639994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.7639994
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2760169457
Short name T1141
Test name
Test status
Simulation time 161139527 ps
CPU time 0.84 seconds
Started Jul 14 07:17:04 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 206872 kb
Host smart-946821c2-2652-4c83-97f0-21b15f46c6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27601
69457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2760169457
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2475649583
Short name T683
Test name
Test status
Simulation time 48221974 ps
CPU time 0.63 seconds
Started Jul 14 07:17:06 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206824 kb
Host smart-1f7dbc71-f868-4723-bd8f-49f49a00fc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24756
49583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2475649583
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2467013695
Short name T2512
Test name
Test status
Simulation time 21958476033 ps
CPU time 47.59 seconds
Started Jul 14 07:17:01 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 207124 kb
Host smart-605a6b4c-ebdb-479e-8775-c9bb3e805bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24670
13695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2467013695
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3553450824
Short name T416
Test name
Test status
Simulation time 197650811 ps
CPU time 0.84 seconds
Started Jul 14 07:17:04 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 206860 kb
Host smart-fab7e467-bf88-4123-96b5-048828ce2a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35534
50824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3553450824
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.45877151
Short name T1182
Test name
Test status
Simulation time 160593952 ps
CPU time 0.75 seconds
Started Jul 14 07:17:05 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206868 kb
Host smart-a68ab2d4-16c8-4ad1-ae04-4dbdee7bc089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45877
151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.45877151
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.2542277212
Short name T1486
Test name
Test status
Simulation time 184013130 ps
CPU time 0.83 seconds
Started Jul 14 07:17:07 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206856 kb
Host smart-c9c8738f-0b78-49e4-a09f-c0a5fc6fe3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25422
77212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2542277212
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.96444547
Short name T2653
Test name
Test status
Simulation time 170857494 ps
CPU time 0.83 seconds
Started Jul 14 07:17:04 PM PDT 24
Finished Jul 14 07:18:16 PM PDT 24
Peak memory 206860 kb
Host smart-8fc14f43-eabb-4d0e-a2f7-e7614dbb5187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96444
547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.96444547
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.4212460764
Short name T1021
Test name
Test status
Simulation time 173985389 ps
CPU time 0.74 seconds
Started Jul 14 07:17:06 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206824 kb
Host smart-3a16be38-4741-4dcc-b9d5-ddc7cd2a52e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124
60764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.4212460764
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.4083406310
Short name T1907
Test name
Test status
Simulation time 157670572 ps
CPU time 0.78 seconds
Started Jul 14 07:17:05 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206880 kb
Host smart-f420efcf-604c-4bd4-adbe-349c516655b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40834
06310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.4083406310
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1949219658
Short name T2286
Test name
Test status
Simulation time 182930964 ps
CPU time 0.79 seconds
Started Jul 14 07:17:04 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206872 kb
Host smart-d3aa7f77-1429-4aaa-a8f9-4b5dc06f1116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19492
19658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1949219658
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1082339294
Short name T2339
Test name
Test status
Simulation time 213279740 ps
CPU time 0.91 seconds
Started Jul 14 07:17:06 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206844 kb
Host smart-2001e32c-e742-4e2d-8dd6-bddc7ea3e76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10823
39294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1082339294
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1154449922
Short name T656
Test name
Test status
Simulation time 5964845323 ps
CPU time 157.19 seconds
Started Jul 14 07:17:02 PM PDT 24
Finished Jul 14 07:20:53 PM PDT 24
Peak memory 207044 kb
Host smart-032b194e-e1b6-4dd7-8983-6ac3da02c22a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1154449922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1154449922
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3903195337
Short name T1369
Test name
Test status
Simulation time 197955206 ps
CPU time 0.86 seconds
Started Jul 14 07:17:05 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206888 kb
Host smart-d9f566c2-2c38-4336-ab50-a4970b44d4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39031
95337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3903195337
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1122447810
Short name T605
Test name
Test status
Simulation time 166021407 ps
CPU time 0.81 seconds
Started Jul 14 07:17:03 PM PDT 24
Finished Jul 14 07:18:18 PM PDT 24
Peak memory 206868 kb
Host smart-0ce91365-a1d8-4a52-87ad-8e4fcd044598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11224
47810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1122447810
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.4249754388
Short name T823
Test name
Test status
Simulation time 677520555 ps
CPU time 1.76 seconds
Started Jul 14 07:17:05 PM PDT 24
Finished Jul 14 07:18:18 PM PDT 24
Peak memory 207068 kb
Host smart-c4ff5e50-405e-49c0-8e78-958ab67dc578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42497
54388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.4249754388
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.4281461542
Short name T990
Test name
Test status
Simulation time 7303918041 ps
CPU time 54.2 seconds
Started Jul 14 07:17:05 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 207148 kb
Host smart-fc0bbec1-1d82-4151-82b9-c76faade5624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42814
61542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.4281461542
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.4284875051
Short name T878
Test name
Test status
Simulation time 37302046 ps
CPU time 0.66 seconds
Started Jul 14 07:17:39 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206896 kb
Host smart-48263010-4bb5-4feb-be72-7b0e850d9882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4284875051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.4284875051
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.4160709456
Short name T694
Test name
Test status
Simulation time 3513554041 ps
CPU time 4.77 seconds
Started Jul 14 07:17:06 PM PDT 24
Finished Jul 14 07:18:21 PM PDT 24
Peak memory 207080 kb
Host smart-abb6e056-509e-46c8-9be4-554052de9148
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4160709456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.4160709456
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3535416975
Short name T1733
Test name
Test status
Simulation time 23377084183 ps
CPU time 20.75 seconds
Started Jul 14 07:17:06 PM PDT 24
Finished Jul 14 07:18:37 PM PDT 24
Peak memory 207052 kb
Host smart-60170c48-af3b-47e6-bd6e-d273073b2cca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3535416975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.3535416975
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2744505004
Short name T2445
Test name
Test status
Simulation time 157858521 ps
CPU time 0.82 seconds
Started Jul 14 07:17:12 PM PDT 24
Finished Jul 14 07:18:18 PM PDT 24
Peak memory 206876 kb
Host smart-fd675f6c-1f5d-46f7-85bf-723137193413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27445
05004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2744505004
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.917402608
Short name T2044
Test name
Test status
Simulation time 158603730 ps
CPU time 0.8 seconds
Started Jul 14 07:17:10 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 206872 kb
Host smart-493a8ab3-992b-4b54-a35a-b6087ce1d987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91740
2608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.917402608
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.3912777789
Short name T1535
Test name
Test status
Simulation time 260533225 ps
CPU time 1.02 seconds
Started Jul 14 07:17:10 PM PDT 24
Finished Jul 14 07:18:18 PM PDT 24
Peak memory 206848 kb
Host smart-f67ff1b5-6072-43f7-92ef-f9fb924ec665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39127
77789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.3912777789
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.366690313
Short name T1164
Test name
Test status
Simulation time 455570436 ps
CPU time 1.2 seconds
Started Jul 14 07:17:12 PM PDT 24
Finished Jul 14 07:18:18 PM PDT 24
Peak memory 206832 kb
Host smart-861220f2-018f-44ba-86d6-a0c41da54157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36669
0313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.366690313
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.1988394406
Short name T2144
Test name
Test status
Simulation time 8299689039 ps
CPU time 15.8 seconds
Started Jul 14 07:17:11 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 207096 kb
Host smart-5114ae3f-87dc-43ca-bfc5-6430a9bcdc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19883
94406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1988394406
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1956877931
Short name T632
Test name
Test status
Simulation time 453845554 ps
CPU time 1.31 seconds
Started Jul 14 07:17:14 PM PDT 24
Finished Jul 14 07:18:21 PM PDT 24
Peak memory 206860 kb
Host smart-40ba61b0-f34b-45d0-a745-240d3f030a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19568
77931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1956877931
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1906389139
Short name T2406
Test name
Test status
Simulation time 142604222 ps
CPU time 0.8 seconds
Started Jul 14 07:17:17 PM PDT 24
Finished Jul 14 07:18:22 PM PDT 24
Peak memory 206860 kb
Host smart-50bc1f77-0da9-4279-89d5-2fb75fb15e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19063
89139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1906389139
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.914335511
Short name T2060
Test name
Test status
Simulation time 76721924 ps
CPU time 0.66 seconds
Started Jul 14 07:17:15 PM PDT 24
Finished Jul 14 07:18:22 PM PDT 24
Peak memory 206832 kb
Host smart-475670d2-9f03-4c5e-bf9b-26a70530b87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91433
5511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.914335511
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2537601784
Short name T1255
Test name
Test status
Simulation time 923475354 ps
CPU time 2.15 seconds
Started Jul 14 07:17:19 PM PDT 24
Finished Jul 14 07:18:24 PM PDT 24
Peak memory 207016 kb
Host smart-26733b77-6755-456a-96e7-3467268169e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25376
01784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2537601784
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.515700887
Short name T2090
Test name
Test status
Simulation time 218670728 ps
CPU time 1.97 seconds
Started Jul 14 07:17:17 PM PDT 24
Finished Jul 14 07:18:24 PM PDT 24
Peak memory 207064 kb
Host smart-05f67663-1706-4645-b2d4-830e80e81ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51570
0887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.515700887
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3419064914
Short name T1885
Test name
Test status
Simulation time 190111175 ps
CPU time 0.85 seconds
Started Jul 14 07:17:21 PM PDT 24
Finished Jul 14 07:18:24 PM PDT 24
Peak memory 206880 kb
Host smart-b641d599-d826-4ce2-b7d2-28d7061ec48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190
64914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3419064914
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1116094099
Short name T2219
Test name
Test status
Simulation time 160356175 ps
CPU time 0.73 seconds
Started Jul 14 07:17:31 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 206844 kb
Host smart-b42fd1ab-bab1-4132-bedf-08c62b91045b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11160
94099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1116094099
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.648080365
Short name T2709
Test name
Test status
Simulation time 278506452 ps
CPU time 0.98 seconds
Started Jul 14 07:17:26 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206844 kb
Host smart-caccfc7b-c041-4507-a8f2-a4bfece6e42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64808
0365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.648080365
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.1100564232
Short name T2639
Test name
Test status
Simulation time 7074983238 ps
CPU time 47.81 seconds
Started Jul 14 07:17:20 PM PDT 24
Finished Jul 14 07:19:10 PM PDT 24
Peak memory 207116 kb
Host smart-c5d0c7e8-4c05-49dd-9578-df3e96d46a63
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1100564232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1100564232
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.2488015181
Short name T546
Test name
Test status
Simulation time 13075303613 ps
CPU time 42.6 seconds
Started Jul 14 07:17:25 PM PDT 24
Finished Jul 14 07:19:07 PM PDT 24
Peak memory 207068 kb
Host smart-19709dd6-2510-4414-8ef4-afd6535eccd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880
15181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.2488015181
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3001093417
Short name T363
Test name
Test status
Simulation time 171841786 ps
CPU time 0.83 seconds
Started Jul 14 07:17:23 PM PDT 24
Finished Jul 14 07:18:25 PM PDT 24
Peak memory 206880 kb
Host smart-e64661ed-e4c4-43f1-951b-42c054dcb056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30010
93417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3001093417
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2430214573
Short name T2513
Test name
Test status
Simulation time 23278881797 ps
CPU time 23.56 seconds
Started Jul 14 07:17:25 PM PDT 24
Finished Jul 14 07:18:48 PM PDT 24
Peak memory 206908 kb
Host smart-336738bf-318f-4976-9600-315955323567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24302
14573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2430214573
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1241305234
Short name T2092
Test name
Test status
Simulation time 3329820521 ps
CPU time 3.53 seconds
Started Jul 14 07:17:29 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206904 kb
Host smart-1d1c5bac-b50e-4abc-8010-b2199ee7af1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413
05234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1241305234
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1208571254
Short name T889
Test name
Test status
Simulation time 6868682217 ps
CPU time 183.81 seconds
Started Jul 14 07:17:20 PM PDT 24
Finished Jul 14 07:21:26 PM PDT 24
Peak memory 207100 kb
Host smart-6be979a0-dc37-4ebe-8e26-4307da63cde4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
71254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1208571254
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3219091758
Short name T2231
Test name
Test status
Simulation time 7540939941 ps
CPU time 197.66 seconds
Started Jul 14 07:17:22 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 207088 kb
Host smart-834d0adb-0066-4575-bb68-8e35aad1895d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3219091758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3219091758
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1023562557
Short name T1453
Test name
Test status
Simulation time 249822394 ps
CPU time 0.99 seconds
Started Jul 14 07:17:29 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 206844 kb
Host smart-498e02ec-bfb9-4911-9c84-545f80541416
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1023562557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1023562557
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.4164960255
Short name T1557
Test name
Test status
Simulation time 198197927 ps
CPU time 0.9 seconds
Started Jul 14 07:17:22 PM PDT 24
Finished Jul 14 07:18:25 PM PDT 24
Peak memory 206888 kb
Host smart-02c4f981-7d1a-4c00-ae58-2e19d404c45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41649
60255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.4164960255
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.4206487093
Short name T2593
Test name
Test status
Simulation time 4037821594 ps
CPU time 30.2 seconds
Started Jul 14 07:17:29 PM PDT 24
Finished Jul 14 07:18:55 PM PDT 24
Peak memory 207052 kb
Host smart-28a1d867-9cd2-4ba6-9d2e-19193df3c769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42064
87093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.4206487093
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1007407722
Short name T1228
Test name
Test status
Simulation time 5509426650 ps
CPU time 38.74 seconds
Started Jul 14 07:17:22 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 207128 kb
Host smart-056e15e4-031c-4162-983b-1ce78fbd748a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1007407722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1007407722
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1921168445
Short name T628
Test name
Test status
Simulation time 200334920 ps
CPU time 0.8 seconds
Started Jul 14 07:17:27 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 206848 kb
Host smart-0f55fff8-93ea-45fb-bddb-51465d2ef89a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1921168445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1921168445
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3492511770
Short name T1435
Test name
Test status
Simulation time 144366299 ps
CPU time 0.75 seconds
Started Jul 14 07:17:22 PM PDT 24
Finished Jul 14 07:18:24 PM PDT 24
Peak memory 206872 kb
Host smart-7e242f63-546c-449b-996a-0063ec17561a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34925
11770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3492511770
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2385428259
Short name T2569
Test name
Test status
Simulation time 184428942 ps
CPU time 0.81 seconds
Started Jul 14 07:17:25 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 206888 kb
Host smart-e8da86d7-7520-4e05-bc72-cb40a4b9ca3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23854
28259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2385428259
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3014235346
Short name T2488
Test name
Test status
Simulation time 163654216 ps
CPU time 0.76 seconds
Started Jul 14 07:17:29 PM PDT 24
Finished Jul 14 07:18:25 PM PDT 24
Peak memory 206864 kb
Host smart-f787d3a4-1d46-4bac-9255-20a186bb7679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30142
35346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3014235346
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.636137079
Short name T2038
Test name
Test status
Simulation time 188827681 ps
CPU time 0.84 seconds
Started Jul 14 07:17:26 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 206892 kb
Host smart-389e92ca-129e-4130-9e99-12a8b8c51f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63613
7079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.636137079
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.4067040041
Short name T1668
Test name
Test status
Simulation time 158313755 ps
CPU time 0.84 seconds
Started Jul 14 07:17:28 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 206844 kb
Host smart-2af4bc7f-5b07-4bc5-ae0b-edeee9a42e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40670
40041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.4067040041
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1047781789
Short name T2571
Test name
Test status
Simulation time 295542710 ps
CPU time 0.96 seconds
Started Jul 14 07:17:27 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 206880 kb
Host smart-ab8910da-4aa0-4669-8ac8-c72e67299138
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1047781789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1047781789
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1208050396
Short name T762
Test name
Test status
Simulation time 150955266 ps
CPU time 0.78 seconds
Started Jul 14 07:17:27 PM PDT 24
Finished Jul 14 07:18:26 PM PDT 24
Peak memory 206856 kb
Host smart-b3f341c5-2ac6-4486-bb40-49cfaab0249f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12080
50396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1208050396
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.4085677912
Short name T2226
Test name
Test status
Simulation time 32923326 ps
CPU time 0.65 seconds
Started Jul 14 07:17:31 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206804 kb
Host smart-e9724b54-289d-4071-98ed-0c2e926c7c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40856
77912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.4085677912
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.827883217
Short name T242
Test name
Test status
Simulation time 15946971411 ps
CPU time 34.26 seconds
Started Jul 14 07:17:34 PM PDT 24
Finished Jul 14 07:19:00 PM PDT 24
Peak memory 207100 kb
Host smart-daf2ecdd-7529-4a5b-a70c-332ae5d15237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82788
3217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.827883217
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1353579891
Short name T2661
Test name
Test status
Simulation time 166273113 ps
CPU time 0.79 seconds
Started Jul 14 07:17:33 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206860 kb
Host smart-8b351b1f-64a8-4756-8eba-e7a1ee517559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13535
79891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1353579891
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3407706710
Short name T320
Test name
Test status
Simulation time 266141961 ps
CPU time 0.99 seconds
Started Jul 14 07:17:31 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206848 kb
Host smart-5d9bf743-fe7d-4a1f-924b-544624e5397a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34077
06710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3407706710
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2054071755
Short name T1260
Test name
Test status
Simulation time 176288357 ps
CPU time 0.79 seconds
Started Jul 14 07:17:38 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206840 kb
Host smart-5aa08958-4e50-4de1-b914-12fca98d8313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20540
71755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2054071755
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2637426434
Short name T2346
Test name
Test status
Simulation time 182347382 ps
CPU time 0.84 seconds
Started Jul 14 07:17:39 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206868 kb
Host smart-9339fd75-b5d9-48b7-9de9-abe188304689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26374
26434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2637426434
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.119593633
Short name T993
Test name
Test status
Simulation time 207557845 ps
CPU time 0.91 seconds
Started Jul 14 07:17:36 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206864 kb
Host smart-1bd27aa0-e47a-445e-b4ff-33add4b73204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11959
3633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.119593633
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.157541613
Short name T1456
Test name
Test status
Simulation time 204899842 ps
CPU time 0.86 seconds
Started Jul 14 07:17:41 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206860 kb
Host smart-1f3eb659-5ada-4200-94af-dcc1b61283a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15754
1613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.157541613
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1525237832
Short name T2398
Test name
Test status
Simulation time 147671847 ps
CPU time 0.76 seconds
Started Jul 14 07:17:37 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206888 kb
Host smart-54cbf5cd-8288-4f5e-9e6b-6709fe69380d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15252
37832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1525237832
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2757587555
Short name T2061
Test name
Test status
Simulation time 245230814 ps
CPU time 0.95 seconds
Started Jul 14 07:17:36 PM PDT 24
Finished Jul 14 07:18:27 PM PDT 24
Peak memory 206856 kb
Host smart-07629dfc-7a35-447b-9e4e-b3dd7d3918da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27575
87555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2757587555
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2860452678
Short name T1351
Test name
Test status
Simulation time 4303590020 ps
CPU time 31.4 seconds
Started Jul 14 07:17:39 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 207092 kb
Host smart-2a7844ef-5458-48b9-99a2-bb7aa5af633e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2860452678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2860452678
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.461105860
Short name T2648
Test name
Test status
Simulation time 150983227 ps
CPU time 0.83 seconds
Started Jul 14 07:17:40 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206852 kb
Host smart-d192479a-7cbb-4288-a667-ef0f4361dde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46110
5860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.461105860
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3108913679
Short name T1784
Test name
Test status
Simulation time 184377008 ps
CPU time 0.84 seconds
Started Jul 14 07:17:39 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206868 kb
Host smart-15832990-2834-44e4-b2ee-e5faad3b256a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31089
13679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3108913679
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.1989509451
Short name T1019
Test name
Test status
Simulation time 292050055 ps
CPU time 1.03 seconds
Started Jul 14 07:17:41 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206868 kb
Host smart-5b30d018-e7de-49cd-8b22-fb1ccfdcbd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
09451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.1989509451
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1320913827
Short name T1037
Test name
Test status
Simulation time 6649295801 ps
CPU time 189.95 seconds
Started Jul 14 07:17:37 PM PDT 24
Finished Jul 14 07:21:36 PM PDT 24
Peak memory 207084 kb
Host smart-f84e0202-9dc9-47cf-900f-54cec20c0ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209
13827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1320913827
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2052380768
Short name T2335
Test name
Test status
Simulation time 46101228 ps
CPU time 0.74 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206960 kb
Host smart-e66558c1-8e05-4e27-af79-231d2ea68135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2052380768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2052380768
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.362045636
Short name T1932
Test name
Test status
Simulation time 4215156906 ps
CPU time 5.26 seconds
Started Jul 14 07:17:37 PM PDT 24
Finished Jul 14 07:18:31 PM PDT 24
Peak memory 207160 kb
Host smart-febcf220-4454-41b7-b00a-91e85c245204
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=362045636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.362045636
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.839533131
Short name T1739
Test name
Test status
Simulation time 13399443146 ps
CPU time 13.59 seconds
Started Jul 14 07:17:39 PM PDT 24
Finished Jul 14 07:18:41 PM PDT 24
Peak memory 207112 kb
Host smart-0940c60f-be3c-4734-9b0b-c79e4f2891a7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=839533131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.839533131
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1730916723
Short name T1142
Test name
Test status
Simulation time 23437271969 ps
CPU time 26.94 seconds
Started Jul 14 07:17:46 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 207292 kb
Host smart-ea51f654-81da-4dd1-b545-245d4f5b3310
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1730916723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1730916723
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4288355324
Short name T1847
Test name
Test status
Simulation time 177406391 ps
CPU time 0.79 seconds
Started Jul 14 07:17:42 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206856 kb
Host smart-99c53cc5-7b50-49e6-8b09-697c064aa13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42883
55324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4288355324
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3945270336
Short name T2688
Test name
Test status
Simulation time 252688679 ps
CPU time 0.9 seconds
Started Jul 14 07:17:42 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206868 kb
Host smart-fa115ae6-5a5f-4073-b0ff-36dace2e9755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
70336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3945270336
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.492790705
Short name T57
Test name
Test status
Simulation time 316363722 ps
CPU time 1.06 seconds
Started Jul 14 07:17:41 PM PDT 24
Finished Jul 14 07:18:28 PM PDT 24
Peak memory 206872 kb
Host smart-05cb605e-8f99-4de5-9d47-f9d399306efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49279
0705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.492790705
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.877431814
Short name T2289
Test name
Test status
Simulation time 787698341 ps
CPU time 1.83 seconds
Started Jul 14 07:17:44 PM PDT 24
Finished Jul 14 07:18:32 PM PDT 24
Peak memory 207012 kb
Host smart-13b4e9c6-37bd-4820-9db1-2364008776fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87743
1814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.877431814
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2905866170
Short name T179
Test name
Test status
Simulation time 13319957723 ps
CPU time 25.1 seconds
Started Jul 14 07:17:45 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 207092 kb
Host smart-03f4f1cf-ae2a-4ce4-a3c6-d5dd49f5a958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
66170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2905866170
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2956492767
Short name T2641
Test name
Test status
Simulation time 479574850 ps
CPU time 1.5 seconds
Started Jul 14 07:17:47 PM PDT 24
Finished Jul 14 07:18:32 PM PDT 24
Peak memory 206872 kb
Host smart-f4538a21-97f7-43e8-8933-621535175b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29564
92767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2956492767
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3348433867
Short name T650
Test name
Test status
Simulation time 137191901 ps
CPU time 0.74 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206884 kb
Host smart-e09cb2ed-6e4c-4717-87c7-c490055218da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33484
33867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3348433867
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1921072345
Short name T1076
Test name
Test status
Simulation time 129935311 ps
CPU time 0.72 seconds
Started Jul 14 07:17:46 PM PDT 24
Finished Jul 14 07:18:31 PM PDT 24
Peak memory 206836 kb
Host smart-ac7f0add-9b5c-460b-b6cb-c9436744b734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210
72345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1921072345
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.709269672
Short name T1039
Test name
Test status
Simulation time 877089013 ps
CPU time 1.97 seconds
Started Jul 14 07:17:47 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 207068 kb
Host smart-c7c5dfe0-3475-4c67-8a73-1a19aafc9dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70926
9672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.709269672
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2429954778
Short name T2711
Test name
Test status
Simulation time 277672450 ps
CPU time 1.95 seconds
Started Jul 14 07:17:46 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 207004 kb
Host smart-a969f904-06d1-467d-87d0-0658a330b9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24299
54778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2429954778
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1756077288
Short name T1466
Test name
Test status
Simulation time 199057361 ps
CPU time 0.86 seconds
Started Jul 14 07:17:48 PM PDT 24
Finished Jul 14 07:18:32 PM PDT 24
Peak memory 206884 kb
Host smart-5d69435e-32fe-43ee-93ec-05f6d22c0edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17560
77288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1756077288
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3933753596
Short name T454
Test name
Test status
Simulation time 153687135 ps
CPU time 0.78 seconds
Started Jul 14 07:17:46 PM PDT 24
Finished Jul 14 07:18:31 PM PDT 24
Peak memory 206892 kb
Host smart-f3097903-14de-4a77-9993-8d2c745e2a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39337
53596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3933753596
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3259402923
Short name T2193
Test name
Test status
Simulation time 202492414 ps
CPU time 0.86 seconds
Started Jul 14 07:17:51 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206844 kb
Host smart-4c970dc8-574f-4016-a59e-208917348459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32594
02923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3259402923
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.2103483168
Short name T634
Test name
Test status
Simulation time 5803273889 ps
CPU time 20.39 seconds
Started Jul 14 07:17:47 PM PDT 24
Finished Jul 14 07:18:51 PM PDT 24
Peak memory 207120 kb
Host smart-a0ea9b10-9ecd-4ffd-b063-cf4b7492e7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21034
83168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.2103483168
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2487893993
Short name T2326
Test name
Test status
Simulation time 241242856 ps
CPU time 0.86 seconds
Started Jul 14 07:17:57 PM PDT 24
Finished Jul 14 07:18:35 PM PDT 24
Peak memory 206872 kb
Host smart-62781e34-9311-4572-b340-57923f92ee2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24878
93993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2487893993
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.4125768696
Short name T2075
Test name
Test status
Simulation time 23350870193 ps
CPU time 21.66 seconds
Started Jul 14 07:17:49 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206944 kb
Host smart-ddc2a5f8-8bd6-44dd-ad3e-87041c1c6916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
68696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.4125768696
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3787355731
Short name T2253
Test name
Test status
Simulation time 3321707715 ps
CPU time 4.7 seconds
Started Jul 14 07:17:52 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 206908 kb
Host smart-83c21959-f8b4-419d-9961-dc0e5c7692e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37873
55731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3787355731
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2530244066
Short name T1982
Test name
Test status
Simulation time 9777033174 ps
CPU time 70.98 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:19:44 PM PDT 24
Peak memory 207144 kb
Host smart-3e2c5a16-8b7b-465c-9ac9-f48138b750b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25302
44066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2530244066
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.395154572
Short name T2077
Test name
Test status
Simulation time 6908403450 ps
CPU time 63.93 seconds
Started Jul 14 07:17:47 PM PDT 24
Finished Jul 14 07:19:35 PM PDT 24
Peak memory 207084 kb
Host smart-aac2f0be-908e-42c4-bb74-3d1a6e102e37
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=395154572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.395154572
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3193510457
Short name T394
Test name
Test status
Simulation time 238946960 ps
CPU time 0.88 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206876 kb
Host smart-2ca1f698-2636-4106-8999-3edd6b4bba67
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3193510457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3193510457
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1670930041
Short name T2509
Test name
Test status
Simulation time 189309618 ps
CPU time 0.85 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206876 kb
Host smart-0ca704a8-16ef-4810-8b56-4bb9bb79123e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16709
30041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1670930041
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3394081179
Short name T2498
Test name
Test status
Simulation time 6386723195 ps
CPU time 61.39 seconds
Started Jul 14 07:17:49 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 207068 kb
Host smart-c8a987fa-1bdb-4390-b416-5f24b440c7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33940
81179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3394081179
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2518953923
Short name T1413
Test name
Test status
Simulation time 4693824372 ps
CPU time 34.67 seconds
Started Jul 14 07:17:46 PM PDT 24
Finished Jul 14 07:19:05 PM PDT 24
Peak memory 207116 kb
Host smart-edd35e5a-06ea-44a7-9e1d-009876096ec1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2518953923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2518953923
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1046100765
Short name T1753
Test name
Test status
Simulation time 152233398 ps
CPU time 0.75 seconds
Started Jul 14 07:17:47 PM PDT 24
Finished Jul 14 07:18:31 PM PDT 24
Peak memory 206876 kb
Host smart-89394ac8-4711-4530-8543-134f5c9e83b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1046100765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1046100765
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.916774357
Short name T1149
Test name
Test status
Simulation time 157316387 ps
CPU time 0.76 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206888 kb
Host smart-2b29991c-b495-4da6-92d9-205617dbd066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91677
4357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.916774357
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.195680918
Short name T1438
Test name
Test status
Simulation time 237477985 ps
CPU time 0.92 seconds
Started Jul 14 07:17:52 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206844 kb
Host smart-ca9cee50-5526-4eab-a2f9-ed51ff8657cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19568
0918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.195680918
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2770014184
Short name T405
Test name
Test status
Simulation time 140479505 ps
CPU time 0.8 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206856 kb
Host smart-ad47560f-fd13-4a8f-95e0-5130a543bdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27700
14184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2770014184
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.4144065197
Short name T1732
Test name
Test status
Simulation time 173319232 ps
CPU time 0.79 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206848 kb
Host smart-8173dcc5-2e26-4fee-93ab-ad7db70c277b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41440
65197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.4144065197
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.4180668106
Short name T533
Test name
Test status
Simulation time 164059262 ps
CPU time 0.81 seconds
Started Jul 14 07:17:49 PM PDT 24
Finished Jul 14 07:18:32 PM PDT 24
Peak memory 206888 kb
Host smart-53861501-d01d-4183-a8ce-3ebff513ee10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
68106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.4180668106
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.837387715
Short name T2121
Test name
Test status
Simulation time 156572594 ps
CPU time 0.76 seconds
Started Jul 14 07:17:49 PM PDT 24
Finished Jul 14 07:18:31 PM PDT 24
Peak memory 206892 kb
Host smart-64802b1d-5580-4dae-91e9-0e5895568d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83738
7715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.837387715
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1409339055
Short name T748
Test name
Test status
Simulation time 210917381 ps
CPU time 0.9 seconds
Started Jul 14 07:17:51 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206972 kb
Host smart-720748c4-c998-4abd-8dfb-8735844cc40d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1409339055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1409339055
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.150463606
Short name T594
Test name
Test status
Simulation time 149173186 ps
CPU time 0.75 seconds
Started Jul 14 07:17:53 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206840 kb
Host smart-9127461d-3111-43d6-bc81-da743a308efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046
3606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.150463606
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.533276728
Short name T531
Test name
Test status
Simulation time 76904450 ps
CPU time 0.68 seconds
Started Jul 14 07:17:49 PM PDT 24
Finished Jul 14 07:18:31 PM PDT 24
Peak memory 206876 kb
Host smart-29331663-eff9-4faf-a581-3ae91110be56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53327
6728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.533276728
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3494266498
Short name T272
Test name
Test status
Simulation time 18725605333 ps
CPU time 42.58 seconds
Started Jul 14 07:17:48 PM PDT 24
Finished Jul 14 07:19:13 PM PDT 24
Peak memory 215292 kb
Host smart-d902ced4-59d2-4461-b331-8d57ce15080d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34942
66498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3494266498
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3973406730
Short name T452
Test name
Test status
Simulation time 194053027 ps
CPU time 0.9 seconds
Started Jul 14 07:17:49 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206900 kb
Host smart-22c6f967-6cd8-4b85-b010-631d7d7c45f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39734
06730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3973406730
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.4156897311
Short name T1816
Test name
Test status
Simulation time 238118252 ps
CPU time 0.9 seconds
Started Jul 14 07:17:51 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206980 kb
Host smart-58cb28ae-c996-436e-b53b-ecf811880e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41568
97311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.4156897311
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1063960353
Short name T1997
Test name
Test status
Simulation time 222707128 ps
CPU time 0.85 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206840 kb
Host smart-0a2df07b-c647-4009-960c-21bf40356b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
60353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1063960353
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.362858610
Short name T1755
Test name
Test status
Simulation time 207009405 ps
CPU time 0.86 seconds
Started Jul 14 07:17:48 PM PDT 24
Finished Jul 14 07:18:32 PM PDT 24
Peak memory 206808 kb
Host smart-9109a686-e1d6-43d6-b4b8-2fd595aded8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36285
8610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.362858610
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1113090411
Short name T1309
Test name
Test status
Simulation time 142811897 ps
CPU time 0.74 seconds
Started Jul 14 07:17:53 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206824 kb
Host smart-a764dd49-dad5-4496-bf77-2d624be05b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11130
90411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1113090411
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1873742472
Short name T659
Test name
Test status
Simulation time 176473670 ps
CPU time 0.79 seconds
Started Jul 14 07:17:47 PM PDT 24
Finished Jul 14 07:18:31 PM PDT 24
Peak memory 206888 kb
Host smart-ad65d25e-1608-4cc4-b1f8-37ee8317955c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18737
42472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1873742472
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2001062235
Short name T873
Test name
Test status
Simulation time 145247051 ps
CPU time 0.75 seconds
Started Jul 14 07:17:53 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206848 kb
Host smart-2dd9557e-aa34-4079-af42-77aec657cfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20010
62235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2001062235
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2250597976
Short name T627
Test name
Test status
Simulation time 250460352 ps
CPU time 0.96 seconds
Started Jul 14 07:17:57 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206872 kb
Host smart-912a1a01-7312-479e-a3ff-6033d93edfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22505
97976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2250597976
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.703326806
Short name T402
Test name
Test status
Simulation time 5602917899 ps
CPU time 37.18 seconds
Started Jul 14 07:17:46 PM PDT 24
Finished Jul 14 07:19:08 PM PDT 24
Peak memory 207156 kb
Host smart-12d958b5-88b8-4e9e-a115-0e7d0809664a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=703326806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.703326806
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1055701656
Short name T2304
Test name
Test status
Simulation time 166848099 ps
CPU time 0.81 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206860 kb
Host smart-79393df2-e218-4896-8d3e-ff01ba4e195f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10557
01656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1055701656
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1083978803
Short name T1514
Test name
Test status
Simulation time 189709287 ps
CPU time 0.85 seconds
Started Jul 14 07:17:51 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206896 kb
Host smart-705b4d33-8957-4ce4-99b8-da6a02f047fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10839
78803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1083978803
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3129934672
Short name T333
Test name
Test status
Simulation time 858380742 ps
CPU time 2.07 seconds
Started Jul 14 07:17:48 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 207060 kb
Host smart-3a93b047-349b-4d13-8a5b-431414efaea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31299
34672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3129934672
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.491888833
Short name T369
Test name
Test status
Simulation time 4758430262 ps
CPU time 43.79 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:19:19 PM PDT 24
Peak memory 207084 kb
Host smart-a2ff2d76-feeb-40d1-9855-279bcc507842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49188
8833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.491888833
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3676477578
Short name T841
Test name
Test status
Simulation time 50522383 ps
CPU time 0.74 seconds
Started Jul 14 07:18:15 PM PDT 24
Finished Jul 14 07:18:42 PM PDT 24
Peak memory 206912 kb
Host smart-9ded14e9-f962-4760-a6d5-cfbf63249343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3676477578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3676477578
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.564870785
Short name T16
Test name
Test status
Simulation time 3449745078 ps
CPU time 4.81 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 206924 kb
Host smart-d9eeb8cc-a680-4726-b9fc-163464d070d9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=564870785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.564870785
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.4120187458
Short name T15
Test name
Test status
Simulation time 13305042421 ps
CPU time 11.58 seconds
Started Jul 14 07:17:51 PM PDT 24
Finished Jul 14 07:18:44 PM PDT 24
Peak memory 207068 kb
Host smart-bdf17ea2-20db-48b5-89e2-aafaefa3c6e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4120187458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.4120187458
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.4036822406
Short name T2725
Test name
Test status
Simulation time 23413850936 ps
CPU time 23.43 seconds
Started Jul 14 07:17:51 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 207128 kb
Host smart-68d26b0f-688d-40ff-8f8c-1cd8487ec5ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4036822406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.4036822406
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.4278764803
Short name T1862
Test name
Test status
Simulation time 151738502 ps
CPU time 0.78 seconds
Started Jul 14 07:17:49 PM PDT 24
Finished Jul 14 07:18:32 PM PDT 24
Peak memory 206888 kb
Host smart-695fd475-c4fb-4375-a442-7081426cc686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42787
64803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.4278764803
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3334406448
Short name T461
Test name
Test status
Simulation time 176225297 ps
CPU time 0.78 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:33 PM PDT 24
Peak memory 206872 kb
Host smart-5b4a5a5f-d403-4771-8784-35e5ff951706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
06448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3334406448
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.860891706
Short name T756
Test name
Test status
Simulation time 481971085 ps
CPU time 1.55 seconds
Started Jul 14 07:17:48 PM PDT 24
Finished Jul 14 07:18:32 PM PDT 24
Peak memory 206860 kb
Host smart-350eb7bd-f337-481f-b89e-4d8cc4b690d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86089
1706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.860891706
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1610270822
Short name T1801
Test name
Test status
Simulation time 1159373017 ps
CPU time 2.54 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:35 PM PDT 24
Peak memory 207088 kb
Host smart-9921b812-7a60-48f7-b439-0ece9ac69213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16102
70822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1610270822
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1151425111
Short name T182
Test name
Test status
Simulation time 7815906176 ps
CPU time 14.17 seconds
Started Jul 14 07:17:50 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 207136 kb
Host smart-c593cade-f955-40f7-8f42-4597c8d59a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11514
25111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1151425111
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3129872824
Short name T2705
Test name
Test status
Simulation time 436853156 ps
CPU time 1.24 seconds
Started Jul 14 07:17:53 PM PDT 24
Finished Jul 14 07:18:35 PM PDT 24
Peak memory 206852 kb
Host smart-9e97d41e-4f90-4d37-af5f-c562314b0f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31298
72824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3129872824
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1960036404
Short name T540
Test name
Test status
Simulation time 156943461 ps
CPU time 0.75 seconds
Started Jul 14 07:17:55 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206872 kb
Host smart-461f6148-a556-406f-9ce6-944659431b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19600
36404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1960036404
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2383102406
Short name T1846
Test name
Test status
Simulation time 51518433 ps
CPU time 0.71 seconds
Started Jul 14 07:17:55 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206848 kb
Host smart-ab5236c5-a461-460b-a575-f87c8ba709a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23831
02406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2383102406
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1234301006
Short name T1232
Test name
Test status
Simulation time 774086844 ps
CPU time 1.92 seconds
Started Jul 14 07:17:54 PM PDT 24
Finished Jul 14 07:18:35 PM PDT 24
Peak memory 207012 kb
Host smart-9ad7bfe2-7cd3-4ef6-90c5-a190f6f8ac00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12343
01006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1234301006
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.532664028
Short name T1166
Test name
Test status
Simulation time 237255294 ps
CPU time 1.62 seconds
Started Jul 14 07:17:55 PM PDT 24
Finished Jul 14 07:18:37 PM PDT 24
Peak memory 206988 kb
Host smart-6e3985c3-23d0-4036-aea0-171eb122f0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53266
4028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.532664028
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.974233986
Short name T2040
Test name
Test status
Simulation time 312975277 ps
CPU time 0.92 seconds
Started Jul 14 07:17:53 PM PDT 24
Finished Jul 14 07:18:34 PM PDT 24
Peak memory 206852 kb
Host smart-89a685b5-05f9-4193-bb62-43014c54c90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97423
3986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.974233986
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3055603486
Short name T2292
Test name
Test status
Simulation time 151886136 ps
CPU time 0.77 seconds
Started Jul 14 07:17:56 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206860 kb
Host smart-294e9021-0bd4-49b7-a268-77ec1fb22674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30556
03486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3055603486
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.102353596
Short name T939
Test name
Test status
Simulation time 196624274 ps
CPU time 0.85 seconds
Started Jul 14 07:17:57 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206844 kb
Host smart-17c7d63e-3788-43ab-8757-e669a0697df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10235
3596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.102353596
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.3074977003
Short name T80
Test name
Test status
Simulation time 7408944328 ps
CPU time 27.08 seconds
Started Jul 14 07:18:00 PM PDT 24
Finished Jul 14 07:19:04 PM PDT 24
Peak memory 206960 kb
Host smart-cf1235be-5b9d-4f08-99ac-09c22671ebeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30749
77003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.3074977003
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1033580713
Short name T2403
Test name
Test status
Simulation time 290036982 ps
CPU time 0.9 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206884 kb
Host smart-478505b6-b3af-4445-9586-bd884acba9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10335
80713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1033580713
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.1706607178
Short name T815
Test name
Test status
Simulation time 23279720042 ps
CPU time 27.4 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 206952 kb
Host smart-e6805038-cc2f-40ed-b652-d8623b833c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
07178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.1706607178
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1944381327
Short name T18
Test name
Test status
Simulation time 3359268136 ps
CPU time 3.88 seconds
Started Jul 14 07:17:59 PM PDT 24
Finished Jul 14 07:18:40 PM PDT 24
Peak memory 206948 kb
Host smart-7f6d43d6-0eb4-48ad-8401-7e73334ee3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19443
81327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1944381327
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.845365171
Short name T1856
Test name
Test status
Simulation time 11693043459 ps
CPU time 78.15 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:19:55 PM PDT 24
Peak memory 207140 kb
Host smart-fcd70325-de75-4034-9dc7-263fe2b6f0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84536
5171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.845365171
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1374413926
Short name T1600
Test name
Test status
Simulation time 4176906005 ps
CPU time 39.66 seconds
Started Jul 14 07:17:59 PM PDT 24
Finished Jul 14 07:19:17 PM PDT 24
Peak memory 207000 kb
Host smart-8c35ac96-8d1e-4e83-b444-beaf742e4abc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1374413926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1374413926
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2740163057
Short name T1099
Test name
Test status
Simulation time 246153440 ps
CPU time 0.9 seconds
Started Jul 14 07:18:00 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 206644 kb
Host smart-f1bef81c-68c5-4447-aeb7-bc79a3e5b5c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2740163057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2740163057
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3126568450
Short name T1387
Test name
Test status
Simulation time 194128774 ps
CPU time 0.85 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 207048 kb
Host smart-816d1dc1-76b8-476f-a40f-496d3107e9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265
68450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3126568450
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3163830964
Short name T1896
Test name
Test status
Simulation time 6303065908 ps
CPU time 178.9 seconds
Started Jul 14 07:17:59 PM PDT 24
Finished Jul 14 07:21:36 PM PDT 24
Peak memory 207116 kb
Host smart-b80490b7-1bf4-434d-b2eb-0f80b71c1a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31638
30964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3163830964
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.4288756051
Short name T813
Test name
Test status
Simulation time 4674067507 ps
CPU time 45.17 seconds
Started Jul 14 07:18:00 PM PDT 24
Finished Jul 14 07:19:22 PM PDT 24
Peak memory 207132 kb
Host smart-87086646-7a3a-45ef-9057-121451aed9a3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4288756051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.4288756051
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.686807595
Short name T1199
Test name
Test status
Simulation time 157479355 ps
CPU time 0.84 seconds
Started Jul 14 07:18:00 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 206856 kb
Host smart-5d81a79c-faac-4bd0-a20c-282cf2c8ed9f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=686807595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.686807595
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3900830666
Short name T1360
Test name
Test status
Simulation time 178250572 ps
CPU time 0.79 seconds
Started Jul 14 07:18:00 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 206856 kb
Host smart-84c85ff7-a22e-42b3-9245-e59f638b61c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39008
30666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3900830666
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3811752610
Short name T1041
Test name
Test status
Simulation time 211780827 ps
CPU time 0.84 seconds
Started Jul 14 07:18:00 PM PDT 24
Finished Jul 14 07:18:37 PM PDT 24
Peak memory 206872 kb
Host smart-9a8577c3-e814-4e0d-85d5-5dea0bcfcb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38117
52610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3811752610
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2747059867
Short name T2101
Test name
Test status
Simulation time 191432500 ps
CPU time 0.83 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:18:36 PM PDT 24
Peak memory 206844 kb
Host smart-efdfdb64-04d2-4f05-b37b-fc68cf870593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27470
59867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2747059867
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3599890010
Short name T608
Test name
Test status
Simulation time 160421777 ps
CPU time 0.79 seconds
Started Jul 14 07:17:58 PM PDT 24
Finished Jul 14 07:18:37 PM PDT 24
Peak memory 206820 kb
Host smart-595ccce4-46ac-4c63-9369-6dff6a8fd0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35998
90010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3599890010
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.510321004
Short name T2200
Test name
Test status
Simulation time 145703019 ps
CPU time 0.77 seconds
Started Jul 14 07:18:07 PM PDT 24
Finished Jul 14 07:18:40 PM PDT 24
Peak memory 206840 kb
Host smart-e9e9ec2c-045c-4bd2-9053-bbc27dd377b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51032
1004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.510321004
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1325080383
Short name T1205
Test name
Test status
Simulation time 301665915 ps
CPU time 1.01 seconds
Started Jul 14 07:18:03 PM PDT 24
Finished Jul 14 07:18:40 PM PDT 24
Peak memory 206872 kb
Host smart-dda95921-7a4c-4a38-90c8-a63dd0a9cad0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1325080383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1325080383
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3945747297
Short name T1931
Test name
Test status
Simulation time 144544638 ps
CPU time 0.76 seconds
Started Jul 14 07:18:06 PM PDT 24
Finished Jul 14 07:18:40 PM PDT 24
Peak memory 206880 kb
Host smart-0030ddec-32df-4412-9af2-9f76e11c7727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39457
47297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3945747297
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.773780953
Short name T658
Test name
Test status
Simulation time 53732997 ps
CPU time 0.68 seconds
Started Jul 14 07:18:05 PM PDT 24
Finished Jul 14 07:18:39 PM PDT 24
Peak memory 206820 kb
Host smart-50525a2b-0501-4a85-8619-a3cd0899c7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77378
0953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.773780953
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.166738398
Short name T2663
Test name
Test status
Simulation time 13336255699 ps
CPU time 30.21 seconds
Started Jul 14 07:18:07 PM PDT 24
Finished Jul 14 07:19:09 PM PDT 24
Peak memory 207172 kb
Host smart-5fe742e4-d0ea-4f63-8ebb-9978882f90d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16673
8398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.166738398
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3663523295
Short name T1688
Test name
Test status
Simulation time 161417778 ps
CPU time 0.78 seconds
Started Jul 14 07:18:06 PM PDT 24
Finished Jul 14 07:18:40 PM PDT 24
Peak memory 206888 kb
Host smart-18910856-c402-49be-ad4a-dec9527f1032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36635
23295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3663523295
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.52691688
Short name T1314
Test name
Test status
Simulation time 271444774 ps
CPU time 0.92 seconds
Started Jul 14 07:18:11 PM PDT 24
Finished Jul 14 07:18:41 PM PDT 24
Peak memory 206888 kb
Host smart-444101e2-ef60-415d-add4-188d225dbc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52691
688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.52691688
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3102660699
Short name T268
Test name
Test status
Simulation time 172562637 ps
CPU time 0.8 seconds
Started Jul 14 07:18:08 PM PDT 24
Finished Jul 14 07:18:40 PM PDT 24
Peak memory 206888 kb
Host smart-a3d24c5b-87e0-45da-9258-92982b831f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31026
60699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3102660699
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.4151881065
Short name T1418
Test name
Test status
Simulation time 251284656 ps
CPU time 0.91 seconds
Started Jul 14 07:18:09 PM PDT 24
Finished Jul 14 07:18:41 PM PDT 24
Peak memory 206808 kb
Host smart-42766824-4589-4174-bcb9-078f75d00a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41518
81065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.4151881065
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1811004418
Short name T913
Test name
Test status
Simulation time 170014508 ps
CPU time 0.8 seconds
Started Jul 14 07:18:09 PM PDT 24
Finished Jul 14 07:18:41 PM PDT 24
Peak memory 206876 kb
Host smart-0b454fc7-7b71-4cec-951c-cf594d9c25d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18110
04418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1811004418
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3734715114
Short name T1507
Test name
Test status
Simulation time 163889821 ps
CPU time 0.8 seconds
Started Jul 14 07:18:08 PM PDT 24
Finished Jul 14 07:18:41 PM PDT 24
Peak memory 206864 kb
Host smart-0b0853e2-f49a-4311-9ab5-209272d94106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37347
15114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3734715114
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1662671957
Short name T1421
Test name
Test status
Simulation time 164787125 ps
CPU time 0.77 seconds
Started Jul 14 07:18:09 PM PDT 24
Finished Jul 14 07:18:41 PM PDT 24
Peak memory 206856 kb
Host smart-e9434a27-d3e5-4cac-82dd-5e586194dd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16626
71957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1662671957
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2222791313
Short name T2446
Test name
Test status
Simulation time 228836469 ps
CPU time 1 seconds
Started Jul 14 07:18:15 PM PDT 24
Finished Jul 14 07:18:42 PM PDT 24
Peak memory 206856 kb
Host smart-06cbd641-4125-4549-b191-9fc0d82f23b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22227
91313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2222791313
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.920238325
Short name T155
Test name
Test status
Simulation time 6651931409 ps
CPU time 177.48 seconds
Started Jul 14 07:18:24 PM PDT 24
Finished Jul 14 07:21:45 PM PDT 24
Peak memory 207080 kb
Host smart-62f58b66-068d-4b7d-afad-b315c61cf7d3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=920238325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.920238325
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2333293940
Short name T1628
Test name
Test status
Simulation time 248810893 ps
CPU time 0.87 seconds
Started Jul 14 07:18:16 PM PDT 24
Finished Jul 14 07:18:42 PM PDT 24
Peak memory 206864 kb
Host smart-762ae61d-c166-449b-8ee4-570b71ecf956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332
93940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2333293940
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.458472145
Short name T325
Test name
Test status
Simulation time 184874344 ps
CPU time 0.81 seconds
Started Jul 14 07:18:14 PM PDT 24
Finished Jul 14 07:18:42 PM PDT 24
Peak memory 206884 kb
Host smart-5edcc8aa-e92e-4d43-80cd-24f92853ea78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45847
2145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.458472145
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.3693485299
Short name T1490
Test name
Test status
Simulation time 1236648146 ps
CPU time 2.53 seconds
Started Jul 14 07:18:16 PM PDT 24
Finished Jul 14 07:18:44 PM PDT 24
Peak memory 207036 kb
Host smart-fa98d3d2-1154-4d95-a264-f00196793dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36934
85299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.3693485299
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2694189176
Short name T2698
Test name
Test status
Simulation time 4030508959 ps
CPU time 111.35 seconds
Started Jul 14 07:18:16 PM PDT 24
Finished Jul 14 07:20:32 PM PDT 24
Peak memory 207048 kb
Host smart-807f6c47-53f4-41e3-992a-48d3c83bd939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26941
89176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2694189176
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2095065073
Short name T189
Test name
Test status
Simulation time 74680923 ps
CPU time 0.71 seconds
Started Jul 14 07:18:28 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206936 kb
Host smart-a376fe87-8720-4c37-aa7d-b2341b1377c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2095065073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2095065073
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3975740863
Short name T1672
Test name
Test status
Simulation time 4082982148 ps
CPU time 5.41 seconds
Started Jul 14 07:18:15 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206912 kb
Host smart-e6e97ff9-c9af-4346-be20-e8b9ef93a7d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3975740863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3975740863
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1086591267
Short name T2260
Test name
Test status
Simulation time 13461261311 ps
CPU time 13.32 seconds
Started Jul 14 07:18:15 PM PDT 24
Finished Jul 14 07:18:55 PM PDT 24
Peak memory 207072 kb
Host smart-30471846-f87b-4aa1-87e5-592a0bf05df1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1086591267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1086591267
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3896026526
Short name T1411
Test name
Test status
Simulation time 23441827169 ps
CPU time 26.65 seconds
Started Jul 14 07:18:16 PM PDT 24
Finished Jul 14 07:19:08 PM PDT 24
Peak memory 207140 kb
Host smart-ad3f68e2-e5c6-48d4-99fc-5d3d61a28f3e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3896026526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.3896026526
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3326739693
Short name T555
Test name
Test status
Simulation time 162865900 ps
CPU time 0.81 seconds
Started Jul 14 07:18:18 PM PDT 24
Finished Jul 14 07:18:43 PM PDT 24
Peak memory 206752 kb
Host smart-31be04e6-dacf-47aa-bcdd-d7b9da1686da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33267
39693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3326739693
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3318914482
Short name T1010
Test name
Test status
Simulation time 187323677 ps
CPU time 0.78 seconds
Started Jul 14 07:18:16 PM PDT 24
Finished Jul 14 07:18:43 PM PDT 24
Peak memory 206892 kb
Host smart-c21c66d9-8af1-4241-8e16-3112fdaff879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33189
14482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3318914482
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2435978757
Short name T1834
Test name
Test status
Simulation time 330711752 ps
CPU time 1.09 seconds
Started Jul 14 07:18:18 PM PDT 24
Finished Jul 14 07:18:44 PM PDT 24
Peak memory 206868 kb
Host smart-774e56a5-c9e0-4d17-9b75-822fb3a70cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24359
78757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2435978757
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.245583341
Short name T1513
Test name
Test status
Simulation time 943018462 ps
CPU time 2.13 seconds
Started Jul 14 07:18:18 PM PDT 24
Finished Jul 14 07:18:45 PM PDT 24
Peak memory 206844 kb
Host smart-437e96bd-a2c6-499b-a887-e6884f1f9128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24558
3341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.245583341
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.4283594117
Short name T1190
Test name
Test status
Simulation time 11962351646 ps
CPU time 21.94 seconds
Started Jul 14 07:18:19 PM PDT 24
Finished Jul 14 07:19:06 PM PDT 24
Peak memory 207052 kb
Host smart-ae93afd1-f417-42ad-a8b1-231ed519b432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42835
94117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.4283594117
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.558777832
Short name T821
Test name
Test status
Simulation time 357973356 ps
CPU time 1.26 seconds
Started Jul 14 07:18:15 PM PDT 24
Finished Jul 14 07:18:43 PM PDT 24
Peak memory 206860 kb
Host smart-44892f03-e3b4-41a3-837c-d3932c24c6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55877
7832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.558777832
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.266602318
Short name T1622
Test name
Test status
Simulation time 147977094 ps
CPU time 0.76 seconds
Started Jul 14 07:18:19 PM PDT 24
Finished Jul 14 07:18:45 PM PDT 24
Peak memory 206868 kb
Host smart-ee2b1d50-44ea-4981-8b52-98419473df81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
2318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.266602318
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.3041190501
Short name T776
Test name
Test status
Simulation time 40238709 ps
CPU time 0.65 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:18:54 PM PDT 24
Peak memory 206884 kb
Host smart-579b953f-c96c-42b5-bbb4-68afd0d9fd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30411
90501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3041190501
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.890186229
Short name T2362
Test name
Test status
Simulation time 793029076 ps
CPU time 2.14 seconds
Started Jul 14 07:18:21 PM PDT 24
Finished Jul 14 07:18:48 PM PDT 24
Peak memory 207012 kb
Host smart-3176f694-9ebb-4125-b4fc-a845c5d9937d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89018
6229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.890186229
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.221682659
Short name T1542
Test name
Test status
Simulation time 255607889 ps
CPU time 1.54 seconds
Started Jul 14 07:18:21 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 207048 kb
Host smart-67694f8d-dad8-4cba-9d96-5eff24c6b362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22168
2659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.221682659
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3766041825
Short name T1224
Test name
Test status
Simulation time 169765102 ps
CPU time 0.83 seconds
Started Jul 14 07:18:22 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206884 kb
Host smart-39aada83-b267-4f1f-969e-8968bddf1ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37660
41825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3766041825
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3920783348
Short name T1371
Test name
Test status
Simulation time 196420673 ps
CPU time 0.78 seconds
Started Jul 14 07:18:21 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206860 kb
Host smart-e9e7c62f-3d78-431b-a824-ed5943150c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39207
83348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3920783348
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.40637959
Short name T528
Test name
Test status
Simulation time 254826295 ps
CPU time 0.99 seconds
Started Jul 14 07:18:20 PM PDT 24
Finished Jul 14 07:18:46 PM PDT 24
Peak memory 206896 kb
Host smart-cc8d0040-7fad-4c30-9065-e82bc561d0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40637
959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.40637959
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.2485955866
Short name T1959
Test name
Test status
Simulation time 6233434789 ps
CPU time 54.51 seconds
Started Jul 14 07:18:20 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 207112 kb
Host smart-0296fbf3-ac57-4e04-b0aa-84424499ed3b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2485955866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2485955866
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.1597542932
Short name T2520
Test name
Test status
Simulation time 11603529320 ps
CPU time 41.7 seconds
Started Jul 14 07:18:22 PM PDT 24
Finished Jul 14 07:19:28 PM PDT 24
Peak memory 207092 kb
Host smart-6c3d1493-c8ef-4061-af9b-70b9e5d83d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15975
42932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1597542932
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.416092530
Short name T2300
Test name
Test status
Simulation time 235077117 ps
CPU time 0.87 seconds
Started Jul 14 07:18:20 PM PDT 24
Finished Jul 14 07:18:45 PM PDT 24
Peak memory 206876 kb
Host smart-3723cf53-cd37-44ca-917b-a35429aee8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609
2530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.416092530
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3338984118
Short name T414
Test name
Test status
Simulation time 23297976521 ps
CPU time 23.1 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:19:16 PM PDT 24
Peak memory 206952 kb
Host smart-5c959501-63b0-4a24-9663-387beb4c7826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33389
84118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3338984118
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2773159013
Short name T438
Test name
Test status
Simulation time 3316202962 ps
CPU time 3.75 seconds
Started Jul 14 07:18:26 PM PDT 24
Finished Jul 14 07:18:54 PM PDT 24
Peak memory 206936 kb
Host smart-b9b6199e-c9ae-4ed0-8a46-5c548d850fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27731
59013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2773159013
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1762356117
Short name T676
Test name
Test status
Simulation time 9645914276 ps
CPU time 87.31 seconds
Started Jul 14 07:18:20 PM PDT 24
Finished Jul 14 07:20:11 PM PDT 24
Peak memory 207176 kb
Host smart-347a1066-73c8-4615-9794-b6f1796789e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17623
56117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1762356117
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1658436127
Short name T1596
Test name
Test status
Simulation time 7537355562 ps
CPU time 207.51 seconds
Started Jul 14 07:18:28 PM PDT 24
Finished Jul 14 07:22:19 PM PDT 24
Peak memory 207056 kb
Host smart-8c050a7e-f8f4-43c3-a3db-1ddb8c1d5219
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1658436127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1658436127
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1363843493
Short name T1254
Test name
Test status
Simulation time 241186705 ps
CPU time 0.91 seconds
Started Jul 14 07:18:19 PM PDT 24
Finished Jul 14 07:18:45 PM PDT 24
Peak memory 206856 kb
Host smart-87b1fc1e-fb00-4a49-9432-e2a42d5d27f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1363843493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1363843493
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1330849828
Short name T1637
Test name
Test status
Simulation time 204807998 ps
CPU time 0.82 seconds
Started Jul 14 07:18:18 PM PDT 24
Finished Jul 14 07:18:44 PM PDT 24
Peak memory 206888 kb
Host smart-4fd92f7e-4f30-4e84-a4bc-674dba10b470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13308
49828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1330849828
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3779222489
Short name T1747
Test name
Test status
Simulation time 6097474123 ps
CPU time 54.3 seconds
Started Jul 14 07:18:22 PM PDT 24
Finished Jul 14 07:19:41 PM PDT 24
Peak memory 207052 kb
Host smart-015055ca-519a-464d-9577-904f80a9055d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37792
22489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3779222489
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.260895588
Short name T1691
Test name
Test status
Simulation time 3394885451 ps
CPU time 25.48 seconds
Started Jul 14 07:18:22 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 207144 kb
Host smart-2152a3d2-29a7-4d2d-8bb8-ed8b6a18315c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=260895588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.260895588
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3751188583
Short name T2557
Test name
Test status
Simulation time 158492319 ps
CPU time 0.76 seconds
Started Jul 14 07:18:33 PM PDT 24
Finished Jul 14 07:18:54 PM PDT 24
Peak memory 206892 kb
Host smart-a75761b2-1e2d-4f47-b553-464e0822b269
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3751188583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3751188583
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2294082724
Short name T388
Test name
Test status
Simulation time 173651501 ps
CPU time 0.86 seconds
Started Jul 14 07:18:26 PM PDT 24
Finished Jul 14 07:18:51 PM PDT 24
Peak memory 206872 kb
Host smart-b1df2070-e9e7-49f2-b226-3e2bfdf83165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22940
82724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2294082724
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.580163115
Short name T128
Test name
Test status
Simulation time 249847680 ps
CPU time 0.95 seconds
Started Jul 14 07:18:25 PM PDT 24
Finished Jul 14 07:18:49 PM PDT 24
Peak memory 206912 kb
Host smart-b34375d7-c891-44b8-a1bf-5a9426ac080d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58016
3115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.580163115
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3437314805
Short name T1259
Test name
Test status
Simulation time 177309201 ps
CPU time 0.79 seconds
Started Jul 14 07:18:33 PM PDT 24
Finished Jul 14 07:18:54 PM PDT 24
Peak memory 206888 kb
Host smart-372fa9d8-ca51-4066-b502-897b875c7aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
14805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3437314805
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1179191088
Short name T1850
Test name
Test status
Simulation time 187653320 ps
CPU time 0.82 seconds
Started Jul 14 07:18:21 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206868 kb
Host smart-a88832b9-2d76-4e61-8ebe-a01b32200122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11791
91088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1179191088
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3587409301
Short name T1676
Test name
Test status
Simulation time 158505891 ps
CPU time 0.79 seconds
Started Jul 14 07:18:33 PM PDT 24
Finished Jul 14 07:18:54 PM PDT 24
Peak memory 206872 kb
Host smart-039235cd-4390-4461-8343-cfbe0cb1f668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35874
09301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3587409301
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.846899563
Short name T1109
Test name
Test status
Simulation time 164161552 ps
CPU time 0.82 seconds
Started Jul 14 07:18:21 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206860 kb
Host smart-76443732-e953-416d-b8cd-2e7df37fb9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84689
9563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.846899563
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.4026142124
Short name T988
Test name
Test status
Simulation time 200460335 ps
CPU time 0.9 seconds
Started Jul 14 07:18:24 PM PDT 24
Finished Jul 14 07:18:49 PM PDT 24
Peak memory 206856 kb
Host smart-1c89289f-3eb5-4d32-ab0c-d8b89ef39b00
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4026142124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.4026142124
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1760553485
Short name T898
Test name
Test status
Simulation time 177574745 ps
CPU time 0.79 seconds
Started Jul 14 07:18:18 PM PDT 24
Finished Jul 14 07:18:43 PM PDT 24
Peak memory 206736 kb
Host smart-9d412b4c-feb0-408d-b717-0d24b2b0c822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17605
53485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1760553485
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2684276504
Short name T2613
Test name
Test status
Simulation time 42478876 ps
CPU time 0.67 seconds
Started Jul 14 07:18:28 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206820 kb
Host smart-1d20399f-dd6d-44df-9569-d208253a8aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26842
76504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2684276504
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3292822829
Short name T796
Test name
Test status
Simulation time 21126719004 ps
CPU time 45.51 seconds
Started Jul 14 07:18:22 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 207068 kb
Host smart-f48e0c7e-c4b9-441b-8290-7649446b678c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32928
22829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3292822829
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3922093462
Short name T1452
Test name
Test status
Simulation time 164670443 ps
CPU time 0.85 seconds
Started Jul 14 07:18:26 PM PDT 24
Finished Jul 14 07:18:51 PM PDT 24
Peak memory 206872 kb
Host smart-22ab16e8-75e8-4f5d-aaf0-afd8be31cd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39220
93462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3922093462
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1502816486
Short name T1515
Test name
Test status
Simulation time 176087297 ps
CPU time 0.81 seconds
Started Jul 14 07:18:20 PM PDT 24
Finished Jul 14 07:18:45 PM PDT 24
Peak memory 206844 kb
Host smart-09583373-dbaf-4401-96c2-27114c24f0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
16486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1502816486
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3939639409
Short name T342
Test name
Test status
Simulation time 212764751 ps
CPU time 0.86 seconds
Started Jul 14 07:18:28 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206824 kb
Host smart-21a57343-317f-4625-884e-f56e049f69ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39396
39409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3939639409
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2649146944
Short name T473
Test name
Test status
Simulation time 144184838 ps
CPU time 0.75 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:18:54 PM PDT 24
Peak memory 206872 kb
Host smart-7d460696-611d-43c6-bdbe-e1432196be9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26491
46944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2649146944
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.912371617
Short name T1483
Test name
Test status
Simulation time 166535259 ps
CPU time 0.79 seconds
Started Jul 14 07:18:22 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206828 kb
Host smart-b5367d77-613a-4b33-874a-4ccd321efac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91237
1617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.912371617
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1881275585
Short name T1442
Test name
Test status
Simulation time 171763420 ps
CPU time 0.81 seconds
Started Jul 14 07:18:23 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206876 kb
Host smart-1e3b10ef-a3f3-4a3e-b184-c2fc3f0c9bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18812
75585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1881275585
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.767014772
Short name T1355
Test name
Test status
Simulation time 188876385 ps
CPU time 0.83 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:18:53 PM PDT 24
Peak memory 206664 kb
Host smart-7efcbd5d-da01-490b-a695-8d1fbd686b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76701
4772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.767014772
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1609113135
Short name T800
Test name
Test status
Simulation time 260939885 ps
CPU time 1 seconds
Started Jul 14 07:18:22 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206844 kb
Host smart-1dfcf14c-086c-41b2-a5d3-55c71c17ea30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16091
13135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1609113135
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.2891426562
Short name T2070
Test name
Test status
Simulation time 5954434139 ps
CPU time 156.22 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 207008 kb
Host smart-53d7197d-1bd3-4ef0-ae93-d1aaeb2080b8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2891426562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.2891426562
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1620576753
Short name T1163
Test name
Test status
Simulation time 161587935 ps
CPU time 0.89 seconds
Started Jul 14 07:18:21 PM PDT 24
Finished Jul 14 07:18:47 PM PDT 24
Peak memory 206860 kb
Host smart-2bcf1b02-2b66-4ec8-a062-77232bf56823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16205
76753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1620576753
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2160450357
Short name T1136
Test name
Test status
Simulation time 156042806 ps
CPU time 0.76 seconds
Started Jul 14 07:18:28 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206828 kb
Host smart-1b261029-fa72-4de4-9641-c88937f311d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21604
50357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2160450357
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.3189062408
Short name T2675
Test name
Test status
Simulation time 529396770 ps
CPU time 1.49 seconds
Started Jul 14 07:18:28 PM PDT 24
Finished Jul 14 07:18:53 PM PDT 24
Peak memory 206808 kb
Host smart-a1cbf327-b74d-4871-909b-0fce8be6cbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31890
62408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3189062408
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3773144608
Short name T2108
Test name
Test status
Simulation time 5267310419 ps
CPU time 47.91 seconds
Started Jul 14 07:18:21 PM PDT 24
Finished Jul 14 07:19:33 PM PDT 24
Peak memory 207116 kb
Host smart-b9c51059-7759-44f1-bc11-6fed11d2a040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37731
44608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3773144608
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1648105617
Short name T188
Test name
Test status
Simulation time 39874632 ps
CPU time 0.67 seconds
Started Jul 14 07:18:37 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 206924 kb
Host smart-40bfacf0-4c8d-49aa-8614-6ac3e772dd3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1648105617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1648105617
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3085900287
Short name T2624
Test name
Test status
Simulation time 4304323881 ps
CPU time 4.85 seconds
Started Jul 14 07:18:26 PM PDT 24
Finished Jul 14 07:18:55 PM PDT 24
Peak memory 207232 kb
Host smart-cf1b3dca-3712-4a8c-a637-bed688101a9c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3085900287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.3085900287
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.784618619
Short name T1122
Test name
Test status
Simulation time 13351308190 ps
CPU time 13.34 seconds
Started Jul 14 07:18:27 PM PDT 24
Finished Jul 14 07:19:05 PM PDT 24
Peak memory 206924 kb
Host smart-3ac65b00-6148-4d60-a2db-dccf8c0fef85
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=784618619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.784618619
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1225926083
Short name T1737
Test name
Test status
Simulation time 23309491909 ps
CPU time 22.95 seconds
Started Jul 14 07:18:26 PM PDT 24
Finished Jul 14 07:19:13 PM PDT 24
Peak memory 206924 kb
Host smart-cf6ebb67-55f7-4f14-8fa4-685e5d3d04cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1225926083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.1225926083
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.493014730
Short name T1730
Test name
Test status
Simulation time 167118242 ps
CPU time 0.8 seconds
Started Jul 14 07:18:28 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206888 kb
Host smart-35da41da-020b-42ef-95aa-b82ded1acb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49301
4730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.493014730
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1139146542
Short name T1519
Test name
Test status
Simulation time 202236583 ps
CPU time 0.8 seconds
Started Jul 14 07:18:27 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206808 kb
Host smart-6f2a9f89-b509-45c0-b5e5-1f18f675f0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11391
46542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1139146542
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.578347476
Short name T101
Test name
Test status
Simulation time 233383887 ps
CPU time 1.08 seconds
Started Jul 14 07:18:27 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206828 kb
Host smart-c1145947-b7a0-4fdf-959b-6f1a3c6a6286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57834
7476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.578347476
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.4079048906
Short name T980
Test name
Test status
Simulation time 813139951 ps
CPU time 1.98 seconds
Started Jul 14 07:18:28 PM PDT 24
Finished Jul 14 07:18:53 PM PDT 24
Peak memory 206952 kb
Host smart-3bc57af9-0a4b-4fbc-b61a-2a03740dac5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40790
48906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.4079048906
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3569370676
Short name T160
Test name
Test status
Simulation time 7255896809 ps
CPU time 15.45 seconds
Started Jul 14 07:18:24 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 207136 kb
Host smart-63049710-a6c7-41e0-9373-ec066bc4462a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35693
70676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3569370676
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.700706184
Short name T413
Test name
Test status
Simulation time 343967998 ps
CPU time 1.17 seconds
Started Jul 14 07:18:27 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206888 kb
Host smart-cf4394f0-9292-4595-ace0-b40fd21c28b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70070
6184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.700706184
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2766881011
Short name T485
Test name
Test status
Simulation time 144645924 ps
CPU time 0.8 seconds
Started Jul 14 07:18:27 PM PDT 24
Finished Jul 14 07:18:51 PM PDT 24
Peak memory 206888 kb
Host smart-2a0a4c85-cbed-49e2-89c5-0eace5f29571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27668
81011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2766881011
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3029288958
Short name T311
Test name
Test status
Simulation time 42613230 ps
CPU time 0.67 seconds
Started Jul 14 07:18:27 PM PDT 24
Finished Jul 14 07:18:52 PM PDT 24
Peak memory 206796 kb
Host smart-e24133e7-9dd8-444c-8fc4-8cbacc0695eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30292
88958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3029288958
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.3783162835
Short name T1757
Test name
Test status
Simulation time 822248084 ps
CPU time 2.07 seconds
Started Jul 14 07:18:24 PM PDT 24
Finished Jul 14 07:18:50 PM PDT 24
Peak memory 207104 kb
Host smart-9340d05a-3dc7-4cc2-ab4a-af46fdf93313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37831
62835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3783162835
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.534027081
Short name T2493
Test name
Test status
Simulation time 258916220 ps
CPU time 1.52 seconds
Started Jul 14 07:18:24 PM PDT 24
Finished Jul 14 07:18:49 PM PDT 24
Peak memory 207056 kb
Host smart-f964d7d6-e28b-42d9-94f6-d494c6194557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53402
7081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.534027081
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.132420158
Short name T1877
Test name
Test status
Simulation time 150693564 ps
CPU time 0.82 seconds
Started Jul 14 07:18:26 PM PDT 24
Finished Jul 14 07:18:51 PM PDT 24
Peak memory 206888 kb
Host smart-3a2ec639-6d41-4b60-a7fe-9e33dc056eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13242
0158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.132420158
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4111337963
Short name T398
Test name
Test status
Simulation time 165391558 ps
CPU time 0.76 seconds
Started Jul 14 07:18:27 PM PDT 24
Finished Jul 14 07:18:51 PM PDT 24
Peak memory 206872 kb
Host smart-09a96359-fec2-4d52-a62a-4c847567215b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
37963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4111337963
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1009231667
Short name T847
Test name
Test status
Simulation time 229229297 ps
CPU time 0.88 seconds
Started Jul 14 07:18:26 PM PDT 24
Finished Jul 14 07:18:51 PM PDT 24
Peak memory 206888 kb
Host smart-f8a070d4-d0aa-4af6-8e3c-53d0ae3e836c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10092
31667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1009231667
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.4095021748
Short name T2266
Test name
Test status
Simulation time 6564401283 ps
CPU time 20.94 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 207028 kb
Host smart-71b17ea3-77e8-453a-b714-7812bf35acce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40950
21748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.4095021748
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1945515559
Short name T2100
Test name
Test status
Simulation time 163821007 ps
CPU time 0.78 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:18:54 PM PDT 24
Peak memory 206844 kb
Host smart-b12b368f-b6ac-4314-8893-4c2269c9ac53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19455
15559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1945515559
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.962666567
Short name T822
Test name
Test status
Simulation time 23316744254 ps
CPU time 26.11 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:19:18 PM PDT 24
Peak memory 206932 kb
Host smart-6a2dacad-45bb-4126-a8d8-d7c4962e9bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96266
6567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.962666567
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1479049582
Short name T1305
Test name
Test status
Simulation time 3337020254 ps
CPU time 4.51 seconds
Started Jul 14 07:18:31 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206924 kb
Host smart-cad143d2-4aeb-4c25-b99e-867bd4cf2155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14790
49582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1479049582
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3660593959
Short name T2409
Test name
Test status
Simulation time 8934446555 ps
CPU time 235.03 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:22:48 PM PDT 24
Peak memory 207120 kb
Host smart-d61b2dc7-6570-4044-8c66-271aaaa9af3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36605
93959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3660593959
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.790149008
Short name T2204
Test name
Test status
Simulation time 4207337780 ps
CPU time 31.34 seconds
Started Jul 14 07:18:31 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 207044 kb
Host smart-a12ed78d-3656-46ff-b968-2c941499bf8b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=790149008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.790149008
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1246887702
Short name T2552
Test name
Test status
Simulation time 240354550 ps
CPU time 0.9 seconds
Started Jul 14 07:18:31 PM PDT 24
Finished Jul 14 07:18:53 PM PDT 24
Peak memory 206872 kb
Host smart-e0e1fa85-695a-4a44-b6c0-b89f7c97191e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1246887702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1246887702
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3091955962
Short name T484
Test name
Test status
Simulation time 184428405 ps
CPU time 0.83 seconds
Started Jul 14 07:18:31 PM PDT 24
Finished Jul 14 07:18:53 PM PDT 24
Peak memory 206848 kb
Host smart-9a6eef1c-89d1-4507-9059-37ba01ff6c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30919
55962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3091955962
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.54999329
Short name T1521
Test name
Test status
Simulation time 3733903700 ps
CPU time 105.76 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:20:39 PM PDT 24
Peak memory 207096 kb
Host smart-43670ead-42a2-4526-8ad8-56593a2d8966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54999
329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.54999329
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.4264574131
Short name T1278
Test name
Test status
Simulation time 6675789740 ps
CPU time 185.84 seconds
Started Jul 14 07:18:32 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 207080 kb
Host smart-6fd931ea-0844-4818-9422-d63759970f42
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4264574131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.4264574131
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3707363555
Short name T1583
Test name
Test status
Simulation time 153473821 ps
CPU time 0.79 seconds
Started Jul 14 07:18:38 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 207020 kb
Host smart-5d607d7e-ee68-4c79-943c-e6354b7a75d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3707363555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3707363555
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.73060836
Short name T2487
Test name
Test status
Simulation time 143756555 ps
CPU time 0.75 seconds
Started Jul 14 07:18:40 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206856 kb
Host smart-9c9f538b-9629-4b6b-a24d-efd1de9bb444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73060
836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.73060836
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2816984691
Short name T108
Test name
Test status
Simulation time 189881248 ps
CPU time 0.83 seconds
Started Jul 14 07:18:38 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 206832 kb
Host smart-c84cbb2a-ac6e-4ae1-bfb5-3a8884cfa9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28169
84691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2816984691
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.442183008
Short name T1242
Test name
Test status
Simulation time 191178339 ps
CPU time 0.83 seconds
Started Jul 14 07:18:41 PM PDT 24
Finished Jul 14 07:18:59 PM PDT 24
Peak memory 206888 kb
Host smart-f4f3005b-10f6-4268-bf0c-8556784f2d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44218
3008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.442183008
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2653670160
Short name T2140
Test name
Test status
Simulation time 160997344 ps
CPU time 0.8 seconds
Started Jul 14 07:18:40 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206844 kb
Host smart-208b6c97-c579-4835-8491-e6419c75d6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26536
70160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2653670160
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3976172855
Short name T2528
Test name
Test status
Simulation time 170661636 ps
CPU time 0.81 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206804 kb
Host smart-551e1a58-c545-414b-965b-55d5da7e953c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39761
72855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3976172855
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3572867780
Short name T29
Test name
Test status
Simulation time 151841833 ps
CPU time 0.77 seconds
Started Jul 14 07:18:42 PM PDT 24
Finished Jul 14 07:19:00 PM PDT 24
Peak memory 206872 kb
Host smart-7238e6ad-2b14-4c41-81bf-087399cfd42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35728
67780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3572867780
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2077011511
Short name T2728
Test name
Test status
Simulation time 223363676 ps
CPU time 0.93 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206884 kb
Host smart-8aba7a30-e7e6-468d-8e10-846e50259dbf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2077011511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2077011511
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3238922481
Short name T2295
Test name
Test status
Simulation time 143026520 ps
CPU time 0.73 seconds
Started Jul 14 07:18:38 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206856 kb
Host smart-402d24b5-5dbb-440a-bf4a-ed4a5df40396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32389
22481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3238922481
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.465102885
Short name T2332
Test name
Test status
Simulation time 80183946 ps
CPU time 0.73 seconds
Started Jul 14 07:18:41 PM PDT 24
Finished Jul 14 07:18:59 PM PDT 24
Peak memory 206840 kb
Host smart-bb037877-15e5-4c25-b257-a085cf7caa66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46510
2885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.465102885
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1434007345
Short name T963
Test name
Test status
Simulation time 18023024250 ps
CPU time 43.32 seconds
Started Jul 14 07:18:38 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 215316 kb
Host smart-5e9a62c9-be41-4c6b-947c-2af56eba76a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
07345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1434007345
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.940557546
Short name T1256
Test name
Test status
Simulation time 165011759 ps
CPU time 0.82 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206892 kb
Host smart-dc9a4b50-b0e6-4898-be03-d75208f15896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94055
7546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.940557546
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.4069170298
Short name T1014
Test name
Test status
Simulation time 273548690 ps
CPU time 0.89 seconds
Started Jul 14 07:18:37 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 206880 kb
Host smart-ee1145a0-d529-4539-9ae5-8938954f11c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40691
70298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.4069170298
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.1862252017
Short name T917
Test name
Test status
Simulation time 167391204 ps
CPU time 0.79 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206860 kb
Host smart-e7b12273-1e3d-4e14-be56-e91e71b954f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18622
52017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.1862252017
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2272227374
Short name T1253
Test name
Test status
Simulation time 189247122 ps
CPU time 0.87 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:01 PM PDT 24
Peak memory 206876 kb
Host smart-04b78485-9421-4770-a840-22b32334cb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22722
27374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2272227374
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.2209211514
Short name T1174
Test name
Test status
Simulation time 182282140 ps
CPU time 0.81 seconds
Started Jul 14 07:18:37 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 206872 kb
Host smart-37fb0e95-79de-4881-bf93-c4cf94d9361e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
11514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.2209211514
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1889878627
Short name T1705
Test name
Test status
Simulation time 156052844 ps
CPU time 0.79 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206852 kb
Host smart-f3dcf822-fb69-439d-bca8-0a05def81511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18898
78627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1889878627
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1772673060
Short name T666
Test name
Test status
Simulation time 156233999 ps
CPU time 0.77 seconds
Started Jul 14 07:18:42 PM PDT 24
Finished Jul 14 07:19:01 PM PDT 24
Peak memory 206868 kb
Host smart-7f30ad11-249c-47ec-ab43-9accb2d5c2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17726
73060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1772673060
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1578464226
Short name T32
Test name
Test status
Simulation time 213092055 ps
CPU time 0.91 seconds
Started Jul 14 07:18:40 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206860 kb
Host smart-fec68f50-e432-4319-ae3e-0acacd49ae7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15784
64226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1578464226
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.2804644885
Short name T1869
Test name
Test status
Simulation time 4294195481 ps
CPU time 40.05 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:40 PM PDT 24
Peak memory 206936 kb
Host smart-85b8ed9a-cd7f-4a66-b9f3-cccf508a2513
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2804644885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2804644885
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.104489707
Short name T409
Test name
Test status
Simulation time 166842030 ps
CPU time 0.78 seconds
Started Jul 14 07:18:38 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 206896 kb
Host smart-29490fb6-8c28-49cc-a080-a749d0c4f79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10448
9707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.104489707
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1110851100
Short name T365
Test name
Test status
Simulation time 192565267 ps
CPU time 0.78 seconds
Started Jul 14 07:18:40 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206868 kb
Host smart-608cef94-4b71-4624-abcb-870af292aceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11108
51100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1110851100
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.2375497336
Short name T82
Test name
Test status
Simulation time 1067224732 ps
CPU time 2.51 seconds
Started Jul 14 07:18:41 PM PDT 24
Finished Jul 14 07:19:01 PM PDT 24
Peak memory 207044 kb
Host smart-d906fe22-6000-4acc-96a0-9a6b48eafb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754
97336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2375497336
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.798868906
Short name T2329
Test name
Test status
Simulation time 3018517429 ps
CPU time 21.95 seconds
Started Jul 14 07:18:40 PM PDT 24
Finished Jul 14 07:19:19 PM PDT 24
Peak memory 207156 kb
Host smart-4d2ad896-a505-4e5c-98a8-2e1aaa0dde9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79886
8906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.798868906
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.771339979
Short name T1814
Test name
Test status
Simulation time 39079531 ps
CPU time 0.7 seconds
Started Jul 14 07:18:46 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 206896 kb
Host smart-19208476-eab7-454f-8c1a-7497ad65a1a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=771339979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.771339979
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2791961369
Short name T1823
Test name
Test status
Simulation time 3951631748 ps
CPU time 4.59 seconds
Started Jul 14 07:18:41 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 207080 kb
Host smart-a08d83ee-da2c-4172-9842-3925c1a4cc78
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2791961369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2791961369
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3082409207
Short name T1926
Test name
Test status
Simulation time 13413010072 ps
CPU time 12.33 seconds
Started Jul 14 07:18:36 PM PDT 24
Finished Jul 14 07:19:07 PM PDT 24
Peak memory 206948 kb
Host smart-218a536e-91d3-4227-bbab-0cc1436deccc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3082409207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3082409207
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2404693815
Short name T2420
Test name
Test status
Simulation time 23387762393 ps
CPU time 25.55 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:19:22 PM PDT 24
Peak memory 206960 kb
Host smart-65ce2227-1337-438d-a6ea-1f14dcd2c42d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2404693815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2404693815
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3803097258
Short name T1933
Test name
Test status
Simulation time 158480969 ps
CPU time 0.81 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:01 PM PDT 24
Peak memory 206868 kb
Host smart-cc4cde3c-5a79-4311-ba41-321ac291c2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38030
97258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3803097258
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2170684968
Short name T967
Test name
Test status
Simulation time 148506189 ps
CPU time 0.79 seconds
Started Jul 14 07:18:42 PM PDT 24
Finished Jul 14 07:19:00 PM PDT 24
Peak memory 206828 kb
Host smart-621702ce-4f5b-4c16-8c0e-2cafc9288944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21706
84968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2170684968
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.1198306906
Short name T829
Test name
Test status
Simulation time 427838592 ps
CPU time 1.41 seconds
Started Jul 14 07:18:38 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206872 kb
Host smart-1c7a4458-77c7-43dc-83d3-13bbe426c9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11983
06906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.1198306906
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2178693062
Short name T1562
Test name
Test status
Simulation time 259569647 ps
CPU time 0.91 seconds
Started Jul 14 07:18:41 PM PDT 24
Finished Jul 14 07:18:59 PM PDT 24
Peak memory 206864 kb
Host smart-ce64e71d-030e-468b-bbdb-f6e65e04595b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21786
93062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2178693062
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.4184612453
Short name T180
Test name
Test status
Simulation time 11338245700 ps
CPU time 21.15 seconds
Started Jul 14 07:18:42 PM PDT 24
Finished Jul 14 07:19:21 PM PDT 24
Peak memory 207080 kb
Host smart-71a1f5cb-85c2-46c9-bc94-e4f2221c873d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41846
12453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.4184612453
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.788846611
Short name T2453
Test name
Test status
Simulation time 518679196 ps
CPU time 1.46 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206840 kb
Host smart-efeb0403-2719-422d-a229-c28b845496cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78884
6611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.788846611
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1234262483
Short name T960
Test name
Test status
Simulation time 136367986 ps
CPU time 0.77 seconds
Started Jul 14 07:18:40 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206824 kb
Host smart-08990027-d02b-4111-8848-849ec05a9f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12342
62483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1234262483
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1306973388
Short name T327
Test name
Test status
Simulation time 39000778 ps
CPU time 0.69 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206840 kb
Host smart-1c99f519-bf0a-403b-ab11-8ba548b2fa7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13069
73388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1306973388
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.728854401
Short name T1168
Test name
Test status
Simulation time 849519060 ps
CPU time 1.99 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:59 PM PDT 24
Peak memory 207036 kb
Host smart-ac212613-35aa-4c15-b398-7cb43f9091db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72885
4401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.728854401
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1556014031
Short name T1930
Test name
Test status
Simulation time 252378577 ps
CPU time 1.59 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 206804 kb
Host smart-e1c52f0a-0b68-4336-a126-e5d5a3ab746c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15560
14031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1556014031
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1665715436
Short name T1208
Test name
Test status
Simulation time 196969057 ps
CPU time 0.81 seconds
Started Jul 14 07:18:38 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206868 kb
Host smart-e2965041-b557-4859-8965-5fa8ccb535e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16657
15436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1665715436
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.303109926
Short name T932
Test name
Test status
Simulation time 140156923 ps
CPU time 0.74 seconds
Started Jul 14 07:18:40 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206856 kb
Host smart-d7561eda-000a-466a-b038-9cbf633ab6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30310
9926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.303109926
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3448978815
Short name T2110
Test name
Test status
Simulation time 270088638 ps
CPU time 0.96 seconds
Started Jul 14 07:18:37 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 206876 kb
Host smart-511fdba9-3329-4e6f-ba75-5ec52c265e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34489
78815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3448978815
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1533611042
Short name T1555
Test name
Test status
Simulation time 212298095 ps
CPU time 0.85 seconds
Started Jul 14 07:18:37 PM PDT 24
Finished Jul 14 07:18:56 PM PDT 24
Peak memory 206876 kb
Host smart-87b8446c-b491-4287-b8ad-2517b62b3ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15336
11042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1533611042
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3919940183
Short name T1481
Test name
Test status
Simulation time 23354784469 ps
CPU time 23.04 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206892 kb
Host smart-762c65ae-014d-43a5-aa5d-4a305e755556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39199
40183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3919940183
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.972996359
Short name T622
Test name
Test status
Simulation time 3316687244 ps
CPU time 3.53 seconds
Started Jul 14 07:18:36 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206948 kb
Host smart-8ce6ad47-39c5-429d-9ccb-df86d14323ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97299
6359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.972996359
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.4045711991
Short name T1343
Test name
Test status
Simulation time 4903804871 ps
CPU time 34.56 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:35 PM PDT 24
Peak memory 207120 kb
Host smart-faa23646-ab7a-4e3a-a690-f4e5ed19388c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4045711991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.4045711991
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3270816929
Short name T1026
Test name
Test status
Simulation time 235027103 ps
CPU time 0.84 seconds
Started Jul 14 07:18:40 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 206856 kb
Host smart-78f11501-78e7-48fa-8a53-817126c56add
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3270816929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3270816929
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2263787397
Short name T717
Test name
Test status
Simulation time 206408129 ps
CPU time 0.9 seconds
Started Jul 14 07:18:39 PM PDT 24
Finished Jul 14 07:18:57 PM PDT 24
Peak memory 206888 kb
Host smart-174d5efc-84c0-469c-a027-c53408a4d54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22637
87397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2263787397
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.4229534704
Short name T2322
Test name
Test status
Simulation time 4761755809 ps
CPU time 132.67 seconds
Started Jul 14 07:18:44 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 207068 kb
Host smart-195c2374-ab90-4eda-a99a-635f6fbfcf29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42295
34704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.4229534704
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1106933348
Short name T1939
Test name
Test status
Simulation time 5687530025 ps
CPU time 41.82 seconds
Started Jul 14 07:18:44 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 207096 kb
Host smart-d2515edb-816e-4f60-9bbf-6a9a4f4d8cd4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1106933348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1106933348
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.4071504583
Short name T1911
Test name
Test status
Simulation time 170400504 ps
CPU time 0.83 seconds
Started Jul 14 07:18:45 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 206844 kb
Host smart-0cb2b460-d1af-45a5-b906-13c89d721884
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4071504583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.4071504583
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2679234236
Short name T832
Test name
Test status
Simulation time 149605164 ps
CPU time 0.74 seconds
Started Jul 14 07:18:44 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 206888 kb
Host smart-f60bacea-38cc-4483-a5db-488d9146a219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792
34236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2679234236
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3482532256
Short name T2475
Test name
Test status
Simulation time 182749287 ps
CPU time 0.89 seconds
Started Jul 14 07:18:48 PM PDT 24
Finished Jul 14 07:19:05 PM PDT 24
Peak memory 206792 kb
Host smart-7c2db4e6-ca67-4174-8cd8-e374a0711bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825
32256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3482532256
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2480297419
Short name T1809
Test name
Test status
Simulation time 151421876 ps
CPU time 0.77 seconds
Started Jul 14 07:18:45 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 206868 kb
Host smart-2434dcec-d7b5-470a-9524-2fd835ed59f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24802
97419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2480297419
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.389388976
Short name T1961
Test name
Test status
Simulation time 191599842 ps
CPU time 0.82 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 206880 kb
Host smart-cc3dfef6-194b-4942-8693-1a6c6fa4c72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38938
8976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.389388976
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3620159075
Short name T2669
Test name
Test status
Simulation time 218156902 ps
CPU time 0.86 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 206880 kb
Host smart-ec88c95c-dd37-4010-aaf5-1491b680ae70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36201
59075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3620159075
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.336780169
Short name T942
Test name
Test status
Simulation time 195057403 ps
CPU time 0.88 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 206888 kb
Host smart-f6841d34-017e-46c7-b2f1-841fda617d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33678
0169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.336780169
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.915389497
Short name T2602
Test name
Test status
Simulation time 204456649 ps
CPU time 0.9 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:01 PM PDT 24
Peak memory 206868 kb
Host smart-4d74132e-9440-4969-a567-4ef5ad1bdb53
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=915389497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.915389497
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2495402872
Short name T566
Test name
Test status
Simulation time 155256646 ps
CPU time 0.75 seconds
Started Jul 14 07:18:47 PM PDT 24
Finished Jul 14 07:19:05 PM PDT 24
Peak memory 206868 kb
Host smart-413580f0-da26-49cf-b947-3661e800b0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24954
02872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2495402872
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.873551758
Short name T247
Test name
Test status
Simulation time 11155792308 ps
CPU time 25.79 seconds
Started Jul 14 07:18:48 PM PDT 24
Finished Jul 14 07:19:30 PM PDT 24
Peak memory 206960 kb
Host smart-34a7c62f-c45f-45d7-8fe1-747419df9611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87355
1758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.873551758
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.993324688
Short name T1078
Test name
Test status
Simulation time 194375043 ps
CPU time 0.83 seconds
Started Jul 14 07:18:42 PM PDT 24
Finished Jul 14 07:19:01 PM PDT 24
Peak memory 206856 kb
Host smart-bc5224ca-ae0d-4e75-8885-4a3d2e4b0f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99332
4688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.993324688
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.309697179
Short name T1419
Test name
Test status
Simulation time 240547153 ps
CPU time 1 seconds
Started Jul 14 07:18:44 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 206856 kb
Host smart-ec2c83ee-4e50-4670-a6f3-70be70e839af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
7179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.309697179
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2315278119
Short name T2454
Test name
Test status
Simulation time 227501897 ps
CPU time 0.92 seconds
Started Jul 14 07:18:46 PM PDT 24
Finished Jul 14 07:19:04 PM PDT 24
Peak memory 206812 kb
Host smart-5a756e99-776f-4928-9b62-c9a983b23f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23152
78119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2315278119
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2510343559
Short name T900
Test name
Test status
Simulation time 192908362 ps
CPU time 0.87 seconds
Started Jul 14 07:18:48 PM PDT 24
Finished Jul 14 07:19:05 PM PDT 24
Peak memory 206860 kb
Host smart-a4112a72-0dbb-4999-83c5-5c8322931943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25103
43559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2510343559
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.557540402
Short name T2554
Test name
Test status
Simulation time 196819539 ps
CPU time 0.81 seconds
Started Jul 14 07:18:44 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 206868 kb
Host smart-768753fa-05ea-4ad2-a532-9c0af2261fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55754
0402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.557540402
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3956879097
Short name T1247
Test name
Test status
Simulation time 152899123 ps
CPU time 0.82 seconds
Started Jul 14 07:18:46 PM PDT 24
Finished Jul 14 07:19:04 PM PDT 24
Peak memory 206852 kb
Host smart-10c7dd4e-3365-4918-a9dc-3ef53e74c863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39568
79097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3956879097
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2650916960
Short name T2729
Test name
Test status
Simulation time 217340355 ps
CPU time 0.86 seconds
Started Jul 14 07:18:42 PM PDT 24
Finished Jul 14 07:19:01 PM PDT 24
Peak memory 206860 kb
Host smart-1a7c0540-b598-4995-ba4a-7c83abaecf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26509
16960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2650916960
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4074240977
Short name T2237
Test name
Test status
Simulation time 220906903 ps
CPU time 0.95 seconds
Started Jul 14 07:18:44 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 206888 kb
Host smart-8c4f234c-266e-4dc1-b986-63f4c2198511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40742
40977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4074240977
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.4285801294
Short name T2685
Test name
Test status
Simulation time 4900343055 ps
CPU time 137.51 seconds
Started Jul 14 07:18:45 PM PDT 24
Finished Jul 14 07:21:19 PM PDT 24
Peak memory 207052 kb
Host smart-7c57b43b-e9ba-4150-aec2-97f3abd066e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4285801294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.4285801294
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3021958953
Short name T2011
Test name
Test status
Simulation time 176272592 ps
CPU time 0.94 seconds
Started Jul 14 07:18:45 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 206860 kb
Host smart-7faf7777-cb55-4151-a783-1eb3be3f6ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30219
58953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3021958953
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2683844450
Short name T1130
Test name
Test status
Simulation time 169173974 ps
CPU time 0.84 seconds
Started Jul 14 07:18:45 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 206856 kb
Host smart-f9da0029-51e4-4777-a93b-b5778ef9cdc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26838
44450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2683844450
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3203951271
Short name T1390
Test name
Test status
Simulation time 1179455106 ps
CPU time 2.59 seconds
Started Jul 14 07:18:43 PM PDT 24
Finished Jul 14 07:19:04 PM PDT 24
Peak memory 206984 kb
Host smart-13df0027-79f7-4ec2-99c4-f6a8d84c2fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32039
51271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3203951271
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.752255764
Short name T6
Test name
Test status
Simulation time 4648355842 ps
CPU time 131.65 seconds
Started Jul 14 07:18:44 PM PDT 24
Finished Jul 14 07:21:13 PM PDT 24
Peak memory 207076 kb
Host smart-b08f294e-bee2-412d-b9b1-f3b89431c948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75225
5764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.752255764
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.403883219
Short name T1506
Test name
Test status
Simulation time 53858484 ps
CPU time 0.68 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:19:10 PM PDT 24
Peak memory 206904 kb
Host smart-afc1ac55-cdd5-467f-8a6e-784bd6de0ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=403883219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.403883219
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3646727778
Short name T602
Test name
Test status
Simulation time 3538498537 ps
CPU time 4.37 seconds
Started Jul 14 07:18:45 PM PDT 24
Finished Jul 14 07:19:06 PM PDT 24
Peak memory 206928 kb
Host smart-c323c783-c3ff-4846-9cbf-5b8a0a3655b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3646727778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3646727778
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2654586818
Short name T953
Test name
Test status
Simulation time 13297894510 ps
CPU time 13.09 seconds
Started Jul 14 07:18:51 PM PDT 24
Finished Jul 14 07:19:20 PM PDT 24
Peak memory 206924 kb
Host smart-a3dca62c-56ba-4f74-8fda-f0e3eb3246b1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2654586818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2654586818
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3394734828
Short name T2186
Test name
Test status
Simulation time 23433647909 ps
CPU time 21.25 seconds
Started Jul 14 07:18:49 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 207108 kb
Host smart-310ed0ab-2e5d-4d07-9cd7-a32848611f30
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3394734828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.3394734828
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1506226487
Short name T2405
Test name
Test status
Simulation time 153639360 ps
CPU time 0.82 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 206896 kb
Host smart-16309897-e9a0-4ae6-a7cb-f263a2c9bac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15062
26487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1506226487
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2274333495
Short name T695
Test name
Test status
Simulation time 154944844 ps
CPU time 0.81 seconds
Started Jul 14 07:18:48 PM PDT 24
Finished Jul 14 07:19:05 PM PDT 24
Peak memory 206880 kb
Host smart-1d8d8ba0-4330-4de7-a706-c977c220c61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22743
33495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2274333495
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.906678763
Short name T935
Test name
Test status
Simulation time 477681118 ps
CPU time 1.5 seconds
Started Jul 14 07:18:50 PM PDT 24
Finished Jul 14 07:19:07 PM PDT 24
Peak memory 207016 kb
Host smart-4534cb2d-6624-4c0d-a0bd-39241d5a03fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90667
8763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.906678763
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.7240518
Short name T1177
Test name
Test status
Simulation time 414082669 ps
CPU time 1.2 seconds
Started Jul 14 07:18:49 PM PDT 24
Finished Jul 14 07:19:07 PM PDT 24
Peak memory 206852 kb
Host smart-24cff431-3f47-4d10-adde-568519e155b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72405
18 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.7240518
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2506372734
Short name T2269
Test name
Test status
Simulation time 11882435133 ps
CPU time 22.28 seconds
Started Jul 14 07:18:52 PM PDT 24
Finished Jul 14 07:19:29 PM PDT 24
Peak memory 207012 kb
Host smart-a9dd2591-fed9-4c02-b44b-0841ca32632e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
72734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2506372734
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1917380451
Short name T592
Test name
Test status
Simulation time 394292087 ps
CPU time 1.18 seconds
Started Jul 14 07:18:50 PM PDT 24
Finished Jul 14 07:19:07 PM PDT 24
Peak memory 206876 kb
Host smart-9427e4e9-79f1-4f34-96e6-05b02373216f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19173
80451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1917380451
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1446928079
Short name T2649
Test name
Test status
Simulation time 157538415 ps
CPU time 0.8 seconds
Started Jul 14 07:18:51 PM PDT 24
Finished Jul 14 07:19:08 PM PDT 24
Peak memory 206848 kb
Host smart-6eae1b6a-2c3f-490c-9db0-d3d8dc369953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14469
28079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1446928079
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1827576399
Short name T2255
Test name
Test status
Simulation time 68622522 ps
CPU time 0.67 seconds
Started Jul 14 07:18:49 PM PDT 24
Finished Jul 14 07:19:06 PM PDT 24
Peak memory 206884 kb
Host smart-e58cfade-7a98-4741-88f4-d33143cb956b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18275
76399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1827576399
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.4016948986
Short name T1503
Test name
Test status
Simulation time 965572044 ps
CPU time 2.08 seconds
Started Jul 14 07:18:54 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 206988 kb
Host smart-a3100e08-7705-4999-a9e9-f23ecb6cda5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40169
48986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.4016948986
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1798079661
Short name T1321
Test name
Test status
Simulation time 366394486 ps
CPU time 2.19 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206988 kb
Host smart-1f488fcc-16f1-4f36-8b91-8e957d86d054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17980
79661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1798079661
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1783365326
Short name T2400
Test name
Test status
Simulation time 226818217 ps
CPU time 0.87 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206836 kb
Host smart-f3d1c235-7ff3-4ae5-b438-26e194af4dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17833
65326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1783365326
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.528154623
Short name T337
Test name
Test status
Simulation time 193899624 ps
CPU time 0.86 seconds
Started Jul 14 07:18:53 PM PDT 24
Finished Jul 14 07:19:09 PM PDT 24
Peak memory 206852 kb
Host smart-663c6579-4c30-44c2-9e53-2bc549c87cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52815
4623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.528154623
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.236928391
Short name T882
Test name
Test status
Simulation time 179509706 ps
CPU time 0.86 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206868 kb
Host smart-0477f708-752d-4f3e-a47d-0276bf446581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23692
8391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.236928391
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.2064755329
Short name T1236
Test name
Test status
Simulation time 13618936841 ps
CPU time 44.91 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:19:55 PM PDT 24
Peak memory 207120 kb
Host smart-24892861-74f1-461e-b28a-91654a3150b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20647
55329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.2064755329
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2256376787
Short name T2506
Test name
Test status
Simulation time 165812278 ps
CPU time 0.81 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206840 kb
Host smart-75020a14-0b69-465c-95bb-a710a157b18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22563
76787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2256376787
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3129695248
Short name T693
Test name
Test status
Simulation time 23341782366 ps
CPU time 22.19 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:36 PM PDT 24
Peak memory 206760 kb
Host smart-561fb94b-9d75-4b4e-b43f-172fa8d34c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31296
95248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3129695248
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.666755509
Short name T2531
Test name
Test status
Simulation time 3324024986 ps
CPU time 4.56 seconds
Started Jul 14 07:18:54 PM PDT 24
Finished Jul 14 07:19:13 PM PDT 24
Peak memory 206916 kb
Host smart-bfdc1086-1d16-4a7f-ac36-eb1fb9ae5b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66675
5509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.666755509
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2510154812
Short name T2316
Test name
Test status
Simulation time 6700665211 ps
CPU time 183.31 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:22:14 PM PDT 24
Peak memory 207088 kb
Host smart-684f666c-f0fb-4643-ab5a-cb3682bd5165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25101
54812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2510154812
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.333765737
Short name T903
Test name
Test status
Simulation time 4315883679 ps
CPU time 116.24 seconds
Started Jul 14 07:18:54 PM PDT 24
Finished Jul 14 07:21:06 PM PDT 24
Peak memory 207080 kb
Host smart-71df8116-d6e8-4786-a718-95c1622e641d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=333765737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.333765737
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1539464493
Short name T1760
Test name
Test status
Simulation time 232234084 ps
CPU time 0.87 seconds
Started Jul 14 07:18:55 PM PDT 24
Finished Jul 14 07:19:10 PM PDT 24
Peak memory 206856 kb
Host smart-ffe5fcfb-c996-4681-a789-d95dbbc277c3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1539464493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1539464493
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1317799120
Short name T240
Test name
Test status
Simulation time 194474688 ps
CPU time 0.83 seconds
Started Jul 14 07:18:53 PM PDT 24
Finished Jul 14 07:19:09 PM PDT 24
Peak memory 206888 kb
Host smart-761f397c-53bf-4d52-815c-102f72215bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13177
99120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1317799120
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.2394081570
Short name T2205
Test name
Test status
Simulation time 4517507111 ps
CPU time 44.01 seconds
Started Jul 14 07:18:54 PM PDT 24
Finished Jul 14 07:19:53 PM PDT 24
Peak memory 207316 kb
Host smart-0296e649-b24d-4636-bd13-0578fb29f27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23940
81570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.2394081570
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2418793102
Short name T2030
Test name
Test status
Simulation time 4287179561 ps
CPU time 29.69 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:41 PM PDT 24
Peak memory 207044 kb
Host smart-6811a793-085f-4ae7-9490-6b3ccbc185e1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2418793102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2418793102
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.1388147366
Short name T1651
Test name
Test status
Simulation time 160900843 ps
CPU time 0.78 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 206848 kb
Host smart-21f74ae8-0b84-4090-9263-a9443c8b6754
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1388147366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.1388147366
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2584792135
Short name T2242
Test name
Test status
Simulation time 159216814 ps
CPU time 0.77 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206876 kb
Host smart-d662aef3-d25f-4d17-b001-090791ba298f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25847
92135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2584792135
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2851058774
Short name T94
Test name
Test status
Simulation time 212726570 ps
CPU time 0.88 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206868 kb
Host smart-f91e63ef-09fe-479b-9371-ca0fc8c31c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510
58774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2851058774
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2992683235
Short name T1240
Test name
Test status
Simulation time 198298736 ps
CPU time 0.93 seconds
Started Jul 14 07:18:55 PM PDT 24
Finished Jul 14 07:19:10 PM PDT 24
Peak memory 206836 kb
Host smart-e51ab41f-e730-4b66-8885-e49e4c429a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29926
83235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2992683235
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.429509281
Short name T2041
Test name
Test status
Simulation time 181256013 ps
CPU time 0.82 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206744 kb
Host smart-7cc7be4e-c8e2-452d-9c60-edda51ef412e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42950
9281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.429509281
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1207397278
Short name T1545
Test name
Test status
Simulation time 203595116 ps
CPU time 0.79 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 206880 kb
Host smart-4da79066-7722-4da1-9952-68405c53fd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
97278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1207397278
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3026391123
Short name T1101
Test name
Test status
Simulation time 160550099 ps
CPU time 0.82 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206860 kb
Host smart-07fd902f-cc98-49c2-bce3-0596fd77fde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30263
91123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3026391123
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2886777713
Short name T2195
Test name
Test status
Simulation time 219411002 ps
CPU time 0.93 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 206840 kb
Host smart-19429a79-61cb-4ca5-b77e-ab90d0709b17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2886777713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2886777713
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.31005257
Short name T1187
Test name
Test status
Simulation time 149092517 ps
CPU time 0.78 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206840 kb
Host smart-fa0ec619-9fc1-440c-b180-d86e009fe2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31005
257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.31005257
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.80888565
Short name T2129
Test name
Test status
Simulation time 52540083 ps
CPU time 0.67 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:19:10 PM PDT 24
Peak memory 206868 kb
Host smart-91f48b98-3381-4057-92cb-27f4ae0fe911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80888
565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.80888565
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3785035593
Short name T2003
Test name
Test status
Simulation time 16718812633 ps
CPU time 38.89 seconds
Started Jul 14 07:18:54 PM PDT 24
Finished Jul 14 07:19:48 PM PDT 24
Peak memory 207152 kb
Host smart-71f27879-ffe5-4bfd-8c78-4a9ce9879a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37850
35593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3785035593
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.729027807
Short name T2027
Test name
Test status
Simulation time 200328011 ps
CPU time 0.86 seconds
Started Jul 14 07:19:01 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206856 kb
Host smart-69ff6229-80e2-454b-aa4e-04f2b9413d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72902
7807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.729027807
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2234763083
Short name T827
Test name
Test status
Simulation time 158507128 ps
CPU time 0.75 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206876 kb
Host smart-a0d2b6e3-f957-4f13-9a73-33994f085056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22347
63083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2234763083
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3019295340
Short name T713
Test name
Test status
Simulation time 311513045 ps
CPU time 1.03 seconds
Started Jul 14 07:18:53 PM PDT 24
Finished Jul 14 07:19:10 PM PDT 24
Peak memory 206840 kb
Host smart-da5bf3de-a30a-4e2e-aa43-01bca4c7c4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30192
95340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3019295340
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.4002884851
Short name T1612
Test name
Test status
Simulation time 180941018 ps
CPU time 0.9 seconds
Started Jul 14 07:18:59 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206868 kb
Host smart-8aa44921-fbeb-4155-90db-9b9d2d5de158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40028
84851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.4002884851
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.713111937
Short name T1117
Test name
Test status
Simulation time 161166366 ps
CPU time 0.83 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:13 PM PDT 24
Peak memory 206836 kb
Host smart-c7a948ac-f7de-4c42-9b9b-cb3d6dae482b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71311
1937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.713111937
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.4007739426
Short name T1029
Test name
Test status
Simulation time 178076518 ps
CPU time 0.81 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206840 kb
Host smart-c9941776-bf2a-4525-94fc-3e761f0faabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
39426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.4007739426
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.923619169
Short name T886
Test name
Test status
Simulation time 157261154 ps
CPU time 0.8 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206864 kb
Host smart-f6e1ae40-d25f-402f-b8d3-fafaf86b2c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92361
9169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.923619169
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2294717953
Short name T1399
Test name
Test status
Simulation time 275372056 ps
CPU time 0.99 seconds
Started Jul 14 07:18:55 PM PDT 24
Finished Jul 14 07:19:10 PM PDT 24
Peak memory 206868 kb
Host smart-5d1c7653-e36a-4098-a51d-d4c21792c1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22947
17953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2294717953
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.358251589
Short name T183
Test name
Test status
Simulation time 3398192765 ps
CPU time 24.85 seconds
Started Jul 14 07:19:01 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 207112 kb
Host smart-c9bfb987-ac9b-4612-b2b0-efee0bf181a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=358251589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.358251589
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.676395196
Short name T1458
Test name
Test status
Simulation time 186242003 ps
CPU time 0.83 seconds
Started Jul 14 07:18:55 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 206892 kb
Host smart-5ca22b81-adfd-4cff-824e-c6f64b139a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67639
5196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.676395196
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2361311507
Short name T2683
Test name
Test status
Simulation time 181748901 ps
CPU time 0.79 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206808 kb
Host smart-a9cea3c1-b050-4e8d-8680-3ce1872a213d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23613
11507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2361311507
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.1189071902
Short name T1066
Test name
Test status
Simulation time 762479160 ps
CPU time 1.72 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:19:18 PM PDT 24
Peak memory 206780 kb
Host smart-2f07eb89-af48-4e87-8b49-a9f6e069c7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
71902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.1189071902
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1182588692
Short name T168
Test name
Test status
Simulation time 7580998020 ps
CPU time 56.72 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 207048 kb
Host smart-1f211dfb-6066-4f34-b795-cb5659fe145a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11825
88692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1182588692
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.1653850802
Short name T396
Test name
Test status
Simulation time 43930353 ps
CPU time 0.68 seconds
Started Jul 14 07:19:01 PM PDT 24
Finished Jul 14 07:19:16 PM PDT 24
Peak memory 206908 kb
Host smart-77802a06-8716-4647-a33b-59d9a2c85b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1653850802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1653850802
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1702349196
Short name T2508
Test name
Test status
Simulation time 3592675190 ps
CPU time 4.41 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 207096 kb
Host smart-685a70ee-16c8-47dd-b63a-cf2a11378a27
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1702349196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1702349196
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.483149009
Short name T647
Test name
Test status
Simulation time 13506510950 ps
CPU time 13.16 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:26 PM PDT 24
Peak memory 207020 kb
Host smart-4e4170d3-feea-46bb-aad7-5f6f0a0ade76
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=483149009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.483149009
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2335976354
Short name T908
Test name
Test status
Simulation time 23346714628 ps
CPU time 29.11 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:42 PM PDT 24
Peak memory 206936 kb
Host smart-42ea95a0-f343-4000-9e2d-4189ab81959e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2335976354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.2335976354
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.443069658
Short name T1400
Test name
Test status
Simulation time 204901450 ps
CPU time 0.84 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:13 PM PDT 24
Peak memory 206896 kb
Host smart-cd1c5a83-2b1d-4acb-93d7-c11dc6bb1133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44306
9658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.443069658
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3175495045
Short name T902
Test name
Test status
Simulation time 152440688 ps
CPU time 0.78 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206848 kb
Host smart-4b2fea21-48f6-4b5d-9189-c99dec9a9f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31754
95045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3175495045
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3097974011
Short name T2617
Test name
Test status
Simulation time 296850542 ps
CPU time 1.15 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206844 kb
Host smart-9e693a06-7937-42cd-a35a-48fc71ccf013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30979
74011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3097974011
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1105313501
Short name T901
Test name
Test status
Simulation time 1114750223 ps
CPU time 2.22 seconds
Started Jul 14 07:18:53 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 207060 kb
Host smart-26739485-3465-43fa-a008-2a78a2398c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11053
13501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1105313501
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2068700323
Short name T2726
Test name
Test status
Simulation time 13450122460 ps
CPU time 24.78 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:36 PM PDT 24
Peak memory 207064 kb
Host smart-0f124c05-475f-4e99-95f9-6ecca1cabd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20687
00323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2068700323
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3719695834
Short name T983
Test name
Test status
Simulation time 305252057 ps
CPU time 1.09 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:19:18 PM PDT 24
Peak memory 206900 kb
Host smart-b7962257-fa95-4750-b8e2-c7520042ec91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37196
95834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3719695834
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1072618174
Short name T1337
Test name
Test status
Simulation time 141941486 ps
CPU time 0.78 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206864 kb
Host smart-e844d82a-a968-4242-9a90-f777cf7452e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10726
18174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1072618174
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1311665778
Short name T2187
Test name
Test status
Simulation time 60911576 ps
CPU time 0.69 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206860 kb
Host smart-9a72052a-c134-42ae-946b-ca8e22a982e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13116
65778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1311665778
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2649437366
Short name T2370
Test name
Test status
Simulation time 1090472400 ps
CPU time 2.47 seconds
Started Jul 14 07:19:04 PM PDT 24
Finished Jul 14 07:19:20 PM PDT 24
Peak memory 206956 kb
Host smart-d4314b1e-a2e8-4d62-b3c7-16ee3589d24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
37366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2649437366
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3617549923
Short name T1595
Test name
Test status
Simulation time 156495575 ps
CPU time 1.28 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:19:18 PM PDT 24
Peak memory 206856 kb
Host smart-e2295595-33e1-457f-a32d-e78742397e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36175
49923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3617549923
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2917834982
Short name T807
Test name
Test status
Simulation time 187213277 ps
CPU time 0.91 seconds
Started Jul 14 07:19:04 PM PDT 24
Finished Jul 14 07:19:18 PM PDT 24
Peak memory 206724 kb
Host smart-7ac6f880-267e-44d6-a692-f92f6f381d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29178
34982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2917834982
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3659472637
Short name T411
Test name
Test status
Simulation time 180542969 ps
CPU time 0.8 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:19:17 PM PDT 24
Peak memory 206908 kb
Host smart-38539104-9e19-4c98-a859-f4580cfb591f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36594
72637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3659472637
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3514535502
Short name T1087
Test name
Test status
Simulation time 262363698 ps
CPU time 1.03 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206872 kb
Host smart-8b7ba9f4-d65b-4e2c-b56c-0b60459310d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35145
35502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3514535502
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.894657328
Short name T1333
Test name
Test status
Simulation time 8884599754 ps
CPU time 75.76 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:20:32 PM PDT 24
Peak memory 206740 kb
Host smart-64c4b9d7-7e5c-482c-82b1-378a21c881bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89465
7328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.894657328
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3262652535
Short name T2153
Test name
Test status
Simulation time 263827812 ps
CPU time 0.93 seconds
Started Jul 14 07:18:59 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206852 kb
Host smart-ed3ac9c5-c1d8-4a14-970a-2753073a275f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32626
52535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3262652535
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1429224409
Short name T2534
Test name
Test status
Simulation time 23337157710 ps
CPU time 25.88 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:40 PM PDT 24
Peak memory 206916 kb
Host smart-167541bd-64f4-49f4-8ca8-6f3440e3624d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14292
24409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1429224409
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1970473651
Short name T651
Test name
Test status
Simulation time 3295245490 ps
CPU time 3.45 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206936 kb
Host smart-0f58a510-4551-417e-9ff6-5c35d2a29bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19704
73651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1970473651
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1096690309
Short name T148
Test name
Test status
Simulation time 9230374564 ps
CPU time 68.74 seconds
Started Jul 14 07:18:59 PM PDT 24
Finished Jul 14 07:20:23 PM PDT 24
Peak memory 207160 kb
Host smart-2782831a-61ae-42e0-9b4f-a46c60e98e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10966
90309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1096690309
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3277977463
Short name T708
Test name
Test status
Simulation time 7720705363 ps
CPU time 57.95 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 207100 kb
Host smart-8a22239c-7324-49ef-9b9a-d227d7c31fbd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3277977463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3277977463
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3004064330
Short name T1033
Test name
Test status
Simulation time 292733731 ps
CPU time 1.01 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206856 kb
Host smart-88ff2aa0-beab-45dd-b8ce-2a510f7b66ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3004064330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3004064330
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2882670410
Short name T637
Test name
Test status
Simulation time 199482713 ps
CPU time 0.9 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206892 kb
Host smart-11e6167b-ef07-473a-a60d-123d20ba0300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28826
70410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2882670410
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.344435947
Short name T630
Test name
Test status
Simulation time 3356403774 ps
CPU time 30.77 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:44 PM PDT 24
Peak memory 207096 kb
Host smart-5e78cb5a-e14c-442b-9029-8207a8ef5d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34443
5947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.344435947
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.239302963
Short name T2076
Test name
Test status
Simulation time 6224877402 ps
CPU time 42.45 seconds
Started Jul 14 07:19:05 PM PDT 24
Finished Jul 14 07:20:00 PM PDT 24
Peak memory 207084 kb
Host smart-5e435f84-7458-4b22-a9f3-46025dacdc88
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=239302963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.239302963
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1744837211
Short name T1235
Test name
Test status
Simulation time 157991292 ps
CPU time 0.79 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206736 kb
Host smart-11e8c3da-cd18-4e20-8c90-9c1be3db8ccc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1744837211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1744837211
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2272419232
Short name T2431
Test name
Test status
Simulation time 158211174 ps
CPU time 0.79 seconds
Started Jul 14 07:19:05 PM PDT 24
Finished Jul 14 07:19:18 PM PDT 24
Peak memory 206852 kb
Host smart-4babdc7b-1994-42d3-9cba-854cf48e567e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22724
19232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2272419232
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2915161058
Short name T1724
Test name
Test status
Simulation time 215926619 ps
CPU time 0.94 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206832 kb
Host smart-5f6be210-e959-4746-a9f9-3c5b9cccaabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29151
61058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2915161058
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.460953456
Short name T2537
Test name
Test status
Simulation time 158602280 ps
CPU time 0.8 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:13 PM PDT 24
Peak memory 206844 kb
Host smart-a6734e25-6db6-45ac-b2c0-e5790413206f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46095
3456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.460953456
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3783868554
Short name T1055
Test name
Test status
Simulation time 176608919 ps
CPU time 0.81 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206868 kb
Host smart-f0121db0-ab2f-4f4b-b887-a8fe7433b77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37838
68554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3783868554
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3980782638
Short name T2348
Test name
Test status
Simulation time 246328869 ps
CPU time 0.87 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206680 kb
Host smart-18b7dc89-6ec1-437f-9dd5-01e490fe3c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39807
82638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3980782638
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1008891179
Short name T2489
Test name
Test status
Simulation time 153432763 ps
CPU time 0.74 seconds
Started Jul 14 07:18:57 PM PDT 24
Finished Jul 14 07:19:12 PM PDT 24
Peak memory 206888 kb
Host smart-4cd78895-fbde-4a2e-a7da-c9e2114fb5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10088
91179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1008891179
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1091127559
Short name T2256
Test name
Test status
Simulation time 231714437 ps
CPU time 0.95 seconds
Started Jul 14 07:18:56 PM PDT 24
Finished Jul 14 07:19:11 PM PDT 24
Peak memory 206824 kb
Host smart-279a51d9-3d49-4397-9a2d-8851526410af
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1091127559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1091127559
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3831882830
Short name T1859
Test name
Test status
Simulation time 178044788 ps
CPU time 0.8 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:13 PM PDT 24
Peak memory 206864 kb
Host smart-b57517a0-707a-4340-a224-cb94444b11d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38318
82830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3831882830
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3940466218
Short name T2584
Test name
Test status
Simulation time 34388835 ps
CPU time 0.65 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206844 kb
Host smart-dfa8d0b8-73a2-4cf7-89f8-aee8b4160c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39404
66218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3940466218
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1736093642
Short name T1894
Test name
Test status
Simulation time 18315876228 ps
CPU time 39.19 seconds
Started Jul 14 07:18:59 PM PDT 24
Finished Jul 14 07:19:52 PM PDT 24
Peak memory 215348 kb
Host smart-3d834635-6ca0-4183-a008-7f2454f5389e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17360
93642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1736093642
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2635029449
Short name T2407
Test name
Test status
Simulation time 185784585 ps
CPU time 0.84 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206884 kb
Host smart-9a91cc21-c9a0-4b72-b50c-c9abbf5b3fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26350
29449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2635029449
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.820638855
Short name T2198
Test name
Test status
Simulation time 160094874 ps
CPU time 0.82 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206844 kb
Host smart-26b65a31-ee42-4f03-9532-00dade87bb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82063
8855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.820638855
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.481816549
Short name T2357
Test name
Test status
Simulation time 224591293 ps
CPU time 0.91 seconds
Started Jul 14 07:19:01 PM PDT 24
Finished Jul 14 07:19:17 PM PDT 24
Peak memory 206844 kb
Host smart-ef2b5008-7504-4813-97cf-cd72189dccc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48181
6549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.481816549
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1562705884
Short name T2645
Test name
Test status
Simulation time 162261106 ps
CPU time 0.78 seconds
Started Jul 14 07:19:01 PM PDT 24
Finished Jul 14 07:19:16 PM PDT 24
Peak memory 206872 kb
Host smart-afb7df3b-a46e-41f7-bc89-afb781507428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15627
05884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1562705884
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2647670315
Short name T1110
Test name
Test status
Simulation time 174652974 ps
CPU time 0.83 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:15 PM PDT 24
Peak memory 206872 kb
Host smart-94cc3d16-34b6-4885-9dff-d4577adbd649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26476
70315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2647670315
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2318986845
Short name T550
Test name
Test status
Simulation time 185984581 ps
CPU time 0.79 seconds
Started Jul 14 07:19:04 PM PDT 24
Finished Jul 14 07:19:18 PM PDT 24
Peak memory 206864 kb
Host smart-d6992f39-6c1c-4c78-b9e7-d8e8a8c46d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23189
86845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2318986845
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3763453935
Short name T1036
Test name
Test status
Simulation time 157456909 ps
CPU time 0.74 seconds
Started Jul 14 07:19:02 PM PDT 24
Finished Jul 14 07:19:17 PM PDT 24
Peak memory 206880 kb
Host smart-4b3b8302-c511-419f-87e1-5c6edfa2ea27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37634
53935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3763453935
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.235213483
Short name T2000
Test name
Test status
Simulation time 188038932 ps
CPU time 0.88 seconds
Started Jul 14 07:18:58 PM PDT 24
Finished Jul 14 07:19:14 PM PDT 24
Peak memory 206872 kb
Host smart-25892672-464e-45d1-91b9-c388060b51eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23521
3483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.235213483
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1708382904
Short name T2667
Test name
Test status
Simulation time 4410531013 ps
CPU time 42.54 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:57 PM PDT 24
Peak memory 207068 kb
Host smart-a5c33861-7bb0-4026-b1f5-7fd408bb46de
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1708382904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1708382904
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1921755271
Short name T1787
Test name
Test status
Simulation time 190539807 ps
CPU time 0.87 seconds
Started Jul 14 07:19:05 PM PDT 24
Finished Jul 14 07:19:18 PM PDT 24
Peak memory 206868 kb
Host smart-1987765a-84d0-466f-969d-dfb0aae31195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19217
55271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1921755271
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1025946277
Short name T2287
Test name
Test status
Simulation time 166872403 ps
CPU time 0.81 seconds
Started Jul 14 07:19:04 PM PDT 24
Finished Jul 14 07:19:17 PM PDT 24
Peak memory 206864 kb
Host smart-b4176fc1-060c-4afe-81bd-73bd7e864a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10259
46277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1025946277
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.2845451253
Short name T2588
Test name
Test status
Simulation time 1122125982 ps
CPU time 2.49 seconds
Started Jul 14 07:19:00 PM PDT 24
Finished Jul 14 07:19:17 PM PDT 24
Peak memory 207032 kb
Host smart-9bc65632-d06c-4e30-a8c2-53fcea870d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28454
51253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2845451253
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2434057839
Short name T696
Test name
Test status
Simulation time 7570066453 ps
CPU time 209.1 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:22:46 PM PDT 24
Peak memory 207080 kb
Host smart-fc60840f-9894-4e38-96fc-b960122f94d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24340
57839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2434057839
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.243523717
Short name T1089
Test name
Test status
Simulation time 48327536 ps
CPU time 0.71 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:29 PM PDT 24
Peak memory 206908 kb
Host smart-b84716a4-ad03-4ccd-92f8-16e2d4a6329e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=243523717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.243523717
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1490550331
Short name T2521
Test name
Test status
Simulation time 4201482665 ps
CPU time 4.7 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:19:21 PM PDT 24
Peak memory 207140 kb
Host smart-583e639c-a99e-46ff-a04a-7a02edf8e10e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1490550331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1490550331
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2711043119
Short name T654
Test name
Test status
Simulation time 13342097306 ps
CPU time 15.53 seconds
Started Jul 14 07:19:05 PM PDT 24
Finished Jul 14 07:19:33 PM PDT 24
Peak memory 206940 kb
Host smart-83a80be9-0740-47be-bfc4-a85c33c43a1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2711043119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2711043119
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2503633501
Short name T820
Test name
Test status
Simulation time 23356425543 ps
CPU time 22.39 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 206944 kb
Host smart-8ec4fefa-3bcc-4905-b076-e158a06c4c43
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2503633501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2503633501
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1912627297
Short name T543
Test name
Test status
Simulation time 152677428 ps
CPU time 0.84 seconds
Started Jul 14 07:19:03 PM PDT 24
Finished Jul 14 07:19:17 PM PDT 24
Peak memory 206864 kb
Host smart-66de9b5a-39ef-493d-9014-479a1c0e5b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126
27297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1912627297
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2578985994
Short name T992
Test name
Test status
Simulation time 160104074 ps
CPU time 0.76 seconds
Started Jul 14 07:19:09 PM PDT 24
Finished Jul 14 07:19:21 PM PDT 24
Peak memory 206860 kb
Host smart-354caff0-909b-4aa9-b813-312250f1778e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25789
85994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2578985994
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.2829649968
Short name T96
Test name
Test status
Simulation time 532768542 ps
CPU time 1.51 seconds
Started Jul 14 07:19:05 PM PDT 24
Finished Jul 14 07:19:19 PM PDT 24
Peak memory 206952 kb
Host smart-2175cf06-cd95-46ac-a5a5-7925fd3c5c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28296
49968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.2829649968
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.610660020
Short name T2518
Test name
Test status
Simulation time 662983898 ps
CPU time 1.6 seconds
Started Jul 14 07:18:59 PM PDT 24
Finished Jul 14 07:19:16 PM PDT 24
Peak memory 206992 kb
Host smart-b35da6c8-0c77-410d-9ab5-ac56bd130a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61066
0020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.610660020
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1067130008
Short name T2098
Test name
Test status
Simulation time 10544898103 ps
CPU time 19.03 seconds
Started Jul 14 07:19:09 PM PDT 24
Finished Jul 14 07:19:40 PM PDT 24
Peak memory 207064 kb
Host smart-30e30c92-c0cf-4a8c-9283-c74e3e7a5add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10671
30008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1067130008
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.3266088669
Short name T1838
Test name
Test status
Simulation time 425673174 ps
CPU time 1.25 seconds
Started Jul 14 07:19:08 PM PDT 24
Finished Jul 14 07:19:20 PM PDT 24
Peak memory 206888 kb
Host smart-7aacbf2d-9786-485e-a08a-9943fe236bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32660
88669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.3266088669
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1877648961
Short name T1373
Test name
Test status
Simulation time 146018981 ps
CPU time 0.77 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 206832 kb
Host smart-fd509a50-0dd8-4281-a9d8-f332a6e5af75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18776
48961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1877648961
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2577619096
Short name T1186
Test name
Test status
Simulation time 40701594 ps
CPU time 0.65 seconds
Started Jul 14 07:19:12 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 206836 kb
Host smart-50d02d70-0374-409b-ab4a-0a70ab25ee1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25776
19096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2577619096
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3281600226
Short name T1923
Test name
Test status
Simulation time 927088038 ps
CPU time 2.24 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:25 PM PDT 24
Peak memory 206988 kb
Host smart-a1f1b793-d43e-46e7-bb30-eca28a1fcc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32816
00226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3281600226
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1623585020
Short name T789
Test name
Test status
Simulation time 319406894 ps
CPU time 1.6 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 206992 kb
Host smart-4d4d28c1-7142-4ec0-bfd3-c0034a5c5723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16235
85020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1623585020
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2415283528
Short name T2185
Test name
Test status
Simulation time 157266071 ps
CPU time 0.82 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206852 kb
Host smart-500a15bb-d108-4484-9dc2-a21833e551cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24152
83528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2415283528
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1474987629
Short name T1049
Test name
Test status
Simulation time 138353958 ps
CPU time 0.77 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:19:22 PM PDT 24
Peak memory 206860 kb
Host smart-8ae23f50-9c02-4215-b235-6786fdcaacf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14749
87629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1474987629
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1659440086
Short name T76
Test name
Test status
Simulation time 252467643 ps
CPU time 0.92 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:19:22 PM PDT 24
Peak memory 206852 kb
Host smart-d0e7927c-857f-4745-b404-8f715fe7052f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16594
40086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1659440086
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1529170381
Short name T2182
Test name
Test status
Simulation time 192472638 ps
CPU time 0.89 seconds
Started Jul 14 07:19:15 PM PDT 24
Finished Jul 14 07:19:26 PM PDT 24
Peak memory 206840 kb
Host smart-4bf2cfa5-597b-4cd6-87cb-202df43014be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15291
70381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1529170381
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1339085764
Short name T462
Test name
Test status
Simulation time 23339979670 ps
CPU time 21.23 seconds
Started Jul 14 07:19:09 PM PDT 24
Finished Jul 14 07:19:42 PM PDT 24
Peak memory 206924 kb
Host smart-ffc68d27-2ac1-492c-862a-69935784413a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13390
85764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1339085764
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3809514812
Short name T2440
Test name
Test status
Simulation time 3274093034 ps
CPU time 3.47 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:19:25 PM PDT 24
Peak memory 206892 kb
Host smart-919e88a0-1d56-4d94-a591-0ff3a1e67639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38095
14812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3809514812
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3066198716
Short name T496
Test name
Test status
Simulation time 9431082653 ps
CPU time 260.81 seconds
Started Jul 14 07:19:13 PM PDT 24
Finished Jul 14 07:23:44 PM PDT 24
Peak memory 207100 kb
Host smart-b2f01d76-37b5-4e44-ae4a-13c677849ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30661
98716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3066198716
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.932347580
Short name T661
Test name
Test status
Simulation time 4696446053 ps
CPU time 43.58 seconds
Started Jul 14 07:19:09 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 207128 kb
Host smart-12d74216-695b-4191-8b3d-b4c8a234c7e8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=932347580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.932347580
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1308340194
Short name T981
Test name
Test status
Simulation time 253881738 ps
CPU time 0.9 seconds
Started Jul 14 07:19:09 PM PDT 24
Finished Jul 14 07:19:21 PM PDT 24
Peak memory 206856 kb
Host smart-f0ed9f4f-97c1-462d-b9e3-0369c4fb1931
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1308340194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1308340194
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3281805974
Short name T906
Test name
Test status
Simulation time 194947130 ps
CPU time 0.85 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206884 kb
Host smart-d16acd91-1117-460e-abba-86cd1ee728c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32818
05974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3281805974
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3573532065
Short name T1658
Test name
Test status
Simulation time 5110387876 ps
CPU time 142.2 seconds
Started Jul 14 07:19:08 PM PDT 24
Finished Jul 14 07:21:41 PM PDT 24
Peak memory 207076 kb
Host smart-c503678c-59b6-4348-9320-a0ad523917f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35735
32065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3573532065
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2334029793
Short name T2637
Test name
Test status
Simulation time 4927388807 ps
CPU time 131.48 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 207064 kb
Host smart-e02f68aa-ca8f-49bc-888a-5017370caa37
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2334029793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2334029793
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.453283573
Short name T746
Test name
Test status
Simulation time 158463485 ps
CPU time 0.82 seconds
Started Jul 14 07:19:15 PM PDT 24
Finished Jul 14 07:19:26 PM PDT 24
Peak memory 206840 kb
Host smart-28337205-f941-4d8e-963c-b9f7f201952b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=453283573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.453283573
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3051984806
Short name T2138
Test name
Test status
Simulation time 167560653 ps
CPU time 0.86 seconds
Started Jul 14 07:19:13 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 206820 kb
Host smart-64c69a89-4c6d-46a0-af51-dd0d68ddfe7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30519
84806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3051984806
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2793133271
Short name T2051
Test name
Test status
Simulation time 185749804 ps
CPU time 0.86 seconds
Started Jul 14 07:19:09 PM PDT 24
Finished Jul 14 07:19:21 PM PDT 24
Peak memory 206844 kb
Host smart-3930a936-3873-4274-bf83-31916f46db0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27931
33271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2793133271
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.223651834
Short name T1740
Test name
Test status
Simulation time 147352645 ps
CPU time 0.8 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206868 kb
Host smart-d1a3f546-16b7-4faf-8b10-eafef05a2f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
1834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.223651834
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2976820617
Short name T346
Test name
Test status
Simulation time 151573756 ps
CPU time 0.76 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206868 kb
Host smart-79ed5b43-43c5-43fa-b908-4625d0fa466f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29768
20617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2976820617
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2707495699
Short name T323
Test name
Test status
Simulation time 172889441 ps
CPU time 0.82 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206864 kb
Host smart-8c47076f-afca-4390-9ef4-bff2a79659d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27074
95699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2707495699
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.367234001
Short name T538
Test name
Test status
Simulation time 168678300 ps
CPU time 0.81 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206864 kb
Host smart-30e5a86b-cb1e-4d11-8b95-312598eaf4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36723
4001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.367234001
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3011483923
Short name T1550
Test name
Test status
Simulation time 190369250 ps
CPU time 0.88 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206884 kb
Host smart-ffb30525-18d8-4186-9ba5-f7e569d1636d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3011483923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3011483923
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.26345037
Short name T1009
Test name
Test status
Simulation time 148091220 ps
CPU time 0.74 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 206864 kb
Host smart-8dec4b48-18ba-403a-a0cc-b8cfe07c05c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26345
037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.26345037
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3875025927
Short name T1416
Test name
Test status
Simulation time 52496963 ps
CPU time 0.68 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:23 PM PDT 24
Peak memory 206868 kb
Host smart-c61a6a4f-49d7-49d6-a722-04431a1d87ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38750
25927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3875025927
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.584246414
Short name T1943
Test name
Test status
Simulation time 13139245041 ps
CPU time 31.95 seconds
Started Jul 14 07:19:10 PM PDT 24
Finished Jul 14 07:19:55 PM PDT 24
Peak memory 215344 kb
Host smart-88db308d-a82b-4647-956f-2464fb9af923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58424
6414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.584246414
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.4186046016
Short name T2676
Test name
Test status
Simulation time 193566867 ps
CPU time 0.89 seconds
Started Jul 14 07:19:14 PM PDT 24
Finished Jul 14 07:19:25 PM PDT 24
Peak memory 206848 kb
Host smart-dab0700e-54b6-477f-a2e6-5ce4da500fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41860
46016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.4186046016
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3936348578
Short name T2634
Test name
Test status
Simulation time 229875461 ps
CPU time 0.92 seconds
Started Jul 14 07:19:11 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 206880 kb
Host smart-f41ef1e2-d9ae-4005-b007-82abe3af3b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39363
48578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3936348578
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.451145446
Short name T426
Test name
Test status
Simulation time 164724693 ps
CPU time 0.84 seconds
Started Jul 14 07:19:09 PM PDT 24
Finished Jul 14 07:19:21 PM PDT 24
Peak memory 206848 kb
Host smart-5b7a455e-e44f-407c-9486-17e045cc55c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45114
5446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.451145446
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3514212495
Short name T1233
Test name
Test status
Simulation time 246882797 ps
CPU time 0.88 seconds
Started Jul 14 07:19:12 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 206840 kb
Host smart-d567c364-67c7-41c0-ae58-d192be9a6b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35142
12495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3514212495
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.680930193
Short name T449
Test name
Test status
Simulation time 182345438 ps
CPU time 0.82 seconds
Started Jul 14 07:19:16 PM PDT 24
Finished Jul 14 07:19:26 PM PDT 24
Peak memory 206888 kb
Host smart-33d74a4d-80d6-42c0-a9fc-7f9d678f593c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68093
0193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.680930193
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3675653431
Short name T425
Test name
Test status
Simulation time 173519922 ps
CPU time 0.8 seconds
Started Jul 14 07:19:16 PM PDT 24
Finished Jul 14 07:19:26 PM PDT 24
Peak memory 206916 kb
Host smart-92f7ddd0-bf54-421f-868b-063e40eefce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36756
53431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3675653431
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1866078971
Short name T603
Test name
Test status
Simulation time 149055155 ps
CPU time 0.8 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:19:38 PM PDT 24
Peak memory 206888 kb
Host smart-88e1daf0-58c7-4ab9-a553-01b0a856f1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18660
78971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1866078971
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3034335737
Short name T469
Test name
Test status
Simulation time 233545873 ps
CPU time 0.89 seconds
Started Jul 14 07:19:23 PM PDT 24
Finished Jul 14 07:19:34 PM PDT 24
Peak memory 206868 kb
Host smart-2425cfc6-77f5-4365-b6b8-40d3f054763a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30343
35737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3034335737
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3340276830
Short name T1731
Test name
Test status
Simulation time 4178091719 ps
CPU time 115.19 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:21:21 PM PDT 24
Peak memory 207068 kb
Host smart-8325236d-ba76-4012-8eb8-33b5b00d24d9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3340276830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3340276830
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3769170056
Short name T2707
Test name
Test status
Simulation time 187651490 ps
CPU time 0.9 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:19:28 PM PDT 24
Peak memory 206896 kb
Host smart-af5f107e-f147-42e2-b912-b688a7da5e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691
70056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3769170056
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.968171158
Short name T1077
Test name
Test status
Simulation time 181668809 ps
CPU time 0.85 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 206872 kb
Host smart-0d7f6f4d-edc3-4e53-a06e-d7d094cb4e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96817
1158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.968171158
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1517676396
Short name T1830
Test name
Test status
Simulation time 210598467 ps
CPU time 0.85 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:36 PM PDT 24
Peak memory 206864 kb
Host smart-bd9bbcb9-fa32-42f5-beae-fe96f635fa37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15176
76396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1517676396
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1956525997
Short name T2566
Test name
Test status
Simulation time 6777962024 ps
CPU time 182.44 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:22:29 PM PDT 24
Peak memory 207096 kb
Host smart-a05ef5be-c4c3-4cc7-8087-be7557b4f1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19565
25997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1956525997
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.297035501
Short name T2642
Test name
Test status
Simulation time 45202531 ps
CPU time 0.66 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:16 PM PDT 24
Peak memory 206948 kb
Host smart-6c60c093-101d-42d1-b12b-13beb97d529f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=297035501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.297035501
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1269670233
Short name T799
Test name
Test status
Simulation time 4223087483 ps
CPU time 4.75 seconds
Started Jul 14 07:12:49 PM PDT 24
Finished Jul 14 07:13:11 PM PDT 24
Peak memory 206932 kb
Host smart-301bd61b-53bc-4170-ba4f-a01661ddb912
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1269670233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.1269670233
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.825270773
Short name T14
Test name
Test status
Simulation time 13350123926 ps
CPU time 13.28 seconds
Started Jul 14 07:12:50 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 207104 kb
Host smart-409a7e69-5b8f-4d32-84e8-48bfe50b6096
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=825270773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.825270773
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2189054310
Short name T968
Test name
Test status
Simulation time 23495585984 ps
CPU time 23.66 seconds
Started Jul 14 07:12:50 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 207084 kb
Host smart-20b02cc0-cfaa-4c85-a4bc-c4661c18b191
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2189054310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.2189054310
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3879536625
Short name T1439
Test name
Test status
Simulation time 149254242 ps
CPU time 0.79 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206856 kb
Host smart-6a63b06d-cb30-42b0-b0ca-6630ecbac526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38795
36625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3879536625
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2222625738
Short name T55
Test name
Test status
Simulation time 179044726 ps
CPU time 0.79 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206860 kb
Host smart-f8269590-338c-4eaf-8009-a82b9057ada8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
25738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2222625738
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3428118229
Short name T62
Test name
Test status
Simulation time 156627393 ps
CPU time 0.79 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206800 kb
Host smart-cf29f62f-751e-4f6d-b52e-2010d1c5ce15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
18229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3428118229
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.468065821
Short name T2450
Test name
Test status
Simulation time 190559831 ps
CPU time 0.8 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:10 PM PDT 24
Peak memory 206876 kb
Host smart-f030156d-9293-4b09-9965-08cd0aec881e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46806
5821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.468065821
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.634248484
Short name T2570
Test name
Test status
Simulation time 357903595 ps
CPU time 1.14 seconds
Started Jul 14 07:12:49 PM PDT 24
Finished Jul 14 07:13:07 PM PDT 24
Peak memory 206860 kb
Host smart-c048073a-9a4b-4402-b70b-077a9bf34fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63424
8484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.634248484
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.792218721
Short name T1860
Test name
Test status
Simulation time 517471974 ps
CPU time 1.39 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:11 PM PDT 24
Peak memory 206864 kb
Host smart-065f615d-ca35-492f-b35b-046d68123bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79221
8721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.792218721
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1560968475
Short name T1546
Test name
Test status
Simulation time 12772548850 ps
CPU time 21.68 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 207132 kb
Host smart-de7b681e-856e-40f0-af66-b139b0bf19e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15609
68475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1560968475
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2364797790
Short name T307
Test name
Test status
Simulation time 371017020 ps
CPU time 1.19 seconds
Started Jul 14 07:12:50 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 206900 kb
Host smart-e8e86c62-2bf1-4c38-8479-1131fa2ae9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23647
97790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2364797790
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.654838928
Short name T517
Test name
Test status
Simulation time 200236541 ps
CPU time 0.8 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206884 kb
Host smart-56808dd9-2408-4350-b7c1-81d737e31efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65483
8928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.654838928
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2148849685
Short name T1703
Test name
Test status
Simulation time 35108406 ps
CPU time 0.64 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:10 PM PDT 24
Peak memory 206848 kb
Host smart-bd257a68-81c3-49e0-a569-e1247ac498bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488
49685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2148849685
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.853521853
Short name T1298
Test name
Test status
Simulation time 772842803 ps
CPU time 1.9 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:13:12 PM PDT 24
Peak memory 206968 kb
Host smart-394b1400-e135-4edc-8447-061b1b840665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85352
1853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.853521853
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.48194308
Short name T679
Test name
Test status
Simulation time 272112768 ps
CPU time 1.93 seconds
Started Jul 14 07:12:49 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 207068 kb
Host smart-8301eea2-145a-4047-8454-9c1e5ca66316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48194
308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.48194308
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.710131971
Short name T1537
Test name
Test status
Simulation time 92186958179 ps
CPU time 133.67 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:15:23 PM PDT 24
Peak memory 207140 kb
Host smart-e08c507b-2f39-4ef5-ad6c-ae64b2f8abe6
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=710131971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.710131971
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.2355229347
Short name T547
Test name
Test status
Simulation time 81303248537 ps
CPU time 106 seconds
Started Jul 14 07:12:49 PM PDT 24
Finished Jul 14 07:14:54 PM PDT 24
Peak memory 207084 kb
Host smart-b45f314a-4647-40e7-a34b-af871bee1c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355229347 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.2355229347
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.1148948620
Short name T669
Test name
Test status
Simulation time 104136703308 ps
CPU time 144.86 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:15:35 PM PDT 24
Peak memory 207084 kb
Host smart-aa454e47-64ea-4b34-81fe-8b16a47bd45e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1148948620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.1148948620
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.3638487972
Short name T30
Test name
Test status
Simulation time 112984513596 ps
CPU time 161.62 seconds
Started Jul 14 07:12:50 PM PDT 24
Finished Jul 14 07:15:51 PM PDT 24
Peak memory 207168 kb
Host smart-048f253c-a848-4a1f-a5ad-369a55759848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638487972 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.3638487972
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.904781666
Short name T1107
Test name
Test status
Simulation time 100122211917 ps
CPU time 151.47 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:15:44 PM PDT 24
Peak memory 207020 kb
Host smart-bbe051e8-3073-4702-b174-d5cb94a4f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90478
1666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.904781666
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1543389413
Short name T614
Test name
Test status
Simulation time 214602344 ps
CPU time 0.95 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206888 kb
Host smart-0b2d3200-26ba-4adc-ad5b-b77588a506fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15433
89413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1543389413
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3234639822
Short name T1915
Test name
Test status
Simulation time 160419332 ps
CPU time 0.77 seconds
Started Jul 14 07:12:50 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 206884 kb
Host smart-e0cb14c3-77cd-43bd-9da4-d90613dbb075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32346
39822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3234639822
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.499560635
Short name T298
Test name
Test status
Simulation time 232874010 ps
CPU time 0.92 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:10 PM PDT 24
Peak memory 206880 kb
Host smart-76eddddc-ff9b-4119-b607-7347500bec8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49956
0635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.499560635
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.4207076576
Short name T212
Test name
Test status
Simulation time 10727496976 ps
CPU time 73.94 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:14:23 PM PDT 24
Peak memory 207144 kb
Host smart-f6cdee98-b965-4a47-89c1-cbd7fc87103f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4207076576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.4207076576
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2448885448
Short name T1824
Test name
Test status
Simulation time 12824451464 ps
CPU time 106.13 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:14:57 PM PDT 24
Peak memory 207160 kb
Host smart-8ef35d8a-344e-4aa1-9579-a91cb0a3809b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
85448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2448885448
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1551835499
Short name T1684
Test name
Test status
Simulation time 170357259 ps
CPU time 0.8 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:10 PM PDT 24
Peak memory 206864 kb
Host smart-cda89482-48d5-4cdb-aee1-448999b79bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15518
35499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1551835499
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2715593425
Short name T2545
Test name
Test status
Simulation time 23292373828 ps
CPU time 20.33 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206892 kb
Host smart-6e91a7d4-e181-4dfb-b9de-cb5319974237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27155
93425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2715593425
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3375195725
Short name T745
Test name
Test status
Simulation time 3334401846 ps
CPU time 3.66 seconds
Started Jul 14 07:12:47 PM PDT 24
Finished Jul 14 07:13:08 PM PDT 24
Peak memory 206936 kb
Host smart-31975c30-c643-4eb8-b41e-eedaf9bdc32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33751
95725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3375195725
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1637976493
Short name T2125
Test name
Test status
Simulation time 5212404032 ps
CPU time 36 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:50 PM PDT 24
Peak memory 207128 kb
Host smart-61754aeb-7b0b-49f0-9e35-df86b68f6de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16379
76493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1637976493
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2976099767
Short name T1016
Test name
Test status
Simulation time 7852572675 ps
CPU time 209.98 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:16:47 PM PDT 24
Peak memory 207060 kb
Host smart-3e218d39-1fd0-4389-997d-ccf0da5c1fb8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2976099767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2976099767
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2368259238
Short name T1721
Test name
Test status
Simulation time 240197805 ps
CPU time 0.9 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:14 PM PDT 24
Peak memory 206884 kb
Host smart-c9ec1f89-ea65-40f9-b157-d0c3cd92f72f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2368259238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2368259238
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1998379947
Short name T2715
Test name
Test status
Simulation time 207445892 ps
CPU time 0.86 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206856 kb
Host smart-c8903f20-179d-4fba-98bd-eecbd13d58b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19983
79947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1998379947
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2205560829
Short name T1769
Test name
Test status
Simulation time 5234693921 ps
CPU time 37.59 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:47 PM PDT 24
Peak memory 207088 kb
Host smart-66d41708-d33d-4257-85eb-8d03bed4f5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22055
60829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2205560829
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.990883439
Short name T1479
Test name
Test status
Simulation time 4038902889 ps
CPU time 29 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:13:40 PM PDT 24
Peak memory 207144 kb
Host smart-143c111f-c65b-4f2b-affd-109158677c74
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=990883439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.990883439
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1201003051
Short name T2600
Test name
Test status
Simulation time 156545171 ps
CPU time 0.84 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206884 kb
Host smart-a1660404-490d-4eb8-a005-23b3b127c3dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1201003051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1201003051
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3140996348
Short name T1780
Test name
Test status
Simulation time 162397579 ps
CPU time 0.8 seconds
Started Jul 14 07:12:49 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 206828 kb
Host smart-bc3c573f-39b6-4e00-bd72-11af295292e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31409
96348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3140996348
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.433502518
Short name T370
Test name
Test status
Simulation time 215822739 ps
CPU time 0.9 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:10 PM PDT 24
Peak memory 206876 kb
Host smart-ee92465c-5d76-46e9-af69-8edc9d2e17a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43350
2518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.433502518
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1137779701
Short name T1554
Test name
Test status
Simulation time 155621357 ps
CPU time 0.78 seconds
Started Jul 14 07:12:50 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 206864 kb
Host smart-1550eb81-dc27-4908-9c50-b8a0d1d308c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11377
79701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1137779701
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2827087669
Short name T512
Test name
Test status
Simulation time 158130090 ps
CPU time 0.78 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 206868 kb
Host smart-7a520130-b316-445f-a43e-de5d22c1c4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28270
87669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2827087669
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2449571461
Short name T1976
Test name
Test status
Simulation time 218693702 ps
CPU time 0.84 seconds
Started Jul 14 07:12:51 PM PDT 24
Finished Jul 14 07:13:10 PM PDT 24
Peak memory 206888 kb
Host smart-f54bcf6c-beec-4654-a933-199bb4d20684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24495
71461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2449571461
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2486054929
Short name T910
Test name
Test status
Simulation time 309144536 ps
CPU time 1 seconds
Started Jul 14 07:12:50 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 206852 kb
Host smart-f2c12d10-e825-442f-917b-23c3e31dcd50
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2486054929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2486054929
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1077882360
Short name T2192
Test name
Test status
Simulation time 250299982 ps
CPU time 1.02 seconds
Started Jul 14 07:12:50 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 207048 kb
Host smart-bd55c7c5-1828-446d-9a7b-8e59db9ceb0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10778
82360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1077882360
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2176558237
Short name T691
Test name
Test status
Simulation time 140669339 ps
CPU time 0.73 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206908 kb
Host smart-cb2ac368-5a1e-4028-8ffa-ddefda40b659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21765
58237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2176558237
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.483179402
Short name T2658
Test name
Test status
Simulation time 80449290 ps
CPU time 0.75 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206836 kb
Host smart-7683cdc0-c358-44f1-9b6a-56f214662f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48317
9402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.483179402
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3117742582
Short name T1463
Test name
Test status
Simulation time 6109457222 ps
CPU time 12.18 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 207104 kb
Host smart-bdecb063-e6e6-4f31-ab86-67133ede77f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31177
42582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3117742582
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.710680651
Short name T560
Test name
Test status
Simulation time 175235170 ps
CPU time 0.82 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206912 kb
Host smart-afe17b2d-12a8-4356-9b14-c85eae97824b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71068
0651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.710680651
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3045842860
Short name T1410
Test name
Test status
Simulation time 222774927 ps
CPU time 0.88 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206876 kb
Host smart-4f4f7b67-46ac-41e0-a48d-3e843af5e78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30458
42860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3045842860
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.106825905
Short name T1284
Test name
Test status
Simulation time 8342140666 ps
CPU time 70.35 seconds
Started Jul 14 07:13:12 PM PDT 24
Finished Jul 14 07:14:37 PM PDT 24
Peak memory 207136 kb
Host smart-bb1fc7e6-72c6-40bc-98b9-7acb1990d6ab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=106825905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.106825905
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.1701381185
Short name T2296
Test name
Test status
Simulation time 14760331313 ps
CPU time 104.71 seconds
Started Jul 14 07:12:53 PM PDT 24
Finished Jul 14 07:14:57 PM PDT 24
Peak memory 207104 kb
Host smart-2ec6ad94-c268-4fac-afcd-4a153818af2d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1701381185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1701381185
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2600736397
Short name T455
Test name
Test status
Simulation time 11456227011 ps
CPU time 217.51 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:16:53 PM PDT 24
Peak memory 207108 kb
Host smart-c6d3624a-f2b2-46bf-a2a7-f05be5ccf167
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2600736397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2600736397
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3938239920
Short name T2647
Test name
Test status
Simulation time 207249778 ps
CPU time 0.82 seconds
Started Jul 14 07:12:55 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206884 kb
Host smart-009b4361-02a7-450c-ac3d-e7d7920a9b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
39920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3938239920
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.232087617
Short name T1723
Test name
Test status
Simulation time 173608916 ps
CPU time 0.83 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:16 PM PDT 24
Peak memory 206848 kb
Host smart-e432ab37-0d8b-4e64-a750-77f4058f5dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208
7617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.232087617
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1610158544
Short name T1973
Test name
Test status
Simulation time 156434810 ps
CPU time 0.76 seconds
Started Jul 14 07:12:58 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206844 kb
Host smart-b3783516-ac0a-402f-91b4-d4000f20174c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16101
58544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1610158544
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3797263016
Short name T1276
Test name
Test status
Simulation time 211350768 ps
CPU time 0.87 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:16 PM PDT 24
Peak memory 206868 kb
Host smart-57637a7d-3082-4022-bbb4-64d3c63fd534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37972
63016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3797263016
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.381748933
Short name T211
Test name
Test status
Simulation time 569311601 ps
CPU time 1.46 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:14 PM PDT 24
Peak memory 225572 kb
Host smart-89649c69-a41f-4e9e-b3a4-9cc49124cd1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=381748933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.381748933
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3303419019
Short name T2703
Test name
Test status
Simulation time 496264202 ps
CPU time 1.36 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206840 kb
Host smart-e43b60d4-aea0-4afb-a1e5-96986790696f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33034
19019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3303419019
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.676356303
Short name T836
Test name
Test status
Simulation time 195967066 ps
CPU time 0.83 seconds
Started Jul 14 07:13:12 PM PDT 24
Finished Jul 14 07:13:27 PM PDT 24
Peak memory 206864 kb
Host smart-0851bbed-0888-4ce2-bbfb-adfee482fd29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67635
6303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.676356303
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2161320804
Short name T2293
Test name
Test status
Simulation time 175464600 ps
CPU time 0.75 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:16 PM PDT 24
Peak memory 206864 kb
Host smart-d9467408-e53b-4c2a-9386-acb04bb62a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21613
20804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2161320804
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.24438710
Short name T1492
Test name
Test status
Simulation time 225370658 ps
CPU time 0.83 seconds
Started Jul 14 07:12:52 PM PDT 24
Finished Jul 14 07:13:11 PM PDT 24
Peak memory 206824 kb
Host smart-1358eac8-309c-4cd3-926a-da5439e20256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24438
710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.24438710
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1140064430
Short name T912
Test name
Test status
Simulation time 218523944 ps
CPU time 0.87 seconds
Started Jul 14 07:12:55 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206804 kb
Host smart-75aab50a-e501-426f-8da0-fb337134f2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11400
64430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1140064430
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3486084686
Short name T784
Test name
Test status
Simulation time 3924326995 ps
CPU time 107.06 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:15:04 PM PDT 24
Peak memory 207128 kb
Host smart-757b550b-b8f0-4827-8e93-e14a8bd8723b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3486084686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3486084686
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2911980716
Short name T2497
Test name
Test status
Simulation time 170488632 ps
CPU time 0.86 seconds
Started Jul 14 07:13:12 PM PDT 24
Finished Jul 14 07:13:28 PM PDT 24
Peak memory 206868 kb
Host smart-f0fa1252-dda4-46e8-b6b8-6a05198d629a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29119
80716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2911980716
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.688787987
Short name T565
Test name
Test status
Simulation time 155665089 ps
CPU time 0.77 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:16 PM PDT 24
Peak memory 206656 kb
Host smart-dbb55b55-888c-4266-b29a-946ddc32272d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68878
7987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.688787987
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2242563170
Short name T479
Test name
Test status
Simulation time 365598097 ps
CPU time 1.1 seconds
Started Jul 14 07:12:59 PM PDT 24
Finished Jul 14 07:13:18 PM PDT 24
Peak memory 206808 kb
Host smart-1e73266b-3de3-4c43-8b72-12794e24e518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22425
63170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2242563170
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2340746218
Short name T2281
Test name
Test status
Simulation time 3301159267 ps
CPU time 23.14 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 207052 kb
Host smart-dbfcb17d-4cb4-49f5-acda-fac1a87efe91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
46218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2340746218
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2971557557
Short name T158
Test name
Test status
Simulation time 18045818977 ps
CPU time 137.11 seconds
Started Jul 14 07:12:59 PM PDT 24
Finished Jul 14 07:15:35 PM PDT 24
Peak memory 207096 kb
Host smart-3480aff2-cd1d-4463-b457-008a91be6e7f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2971557557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2971557557
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3997996788
Short name T1991
Test name
Test status
Simulation time 34094683 ps
CPU time 0.69 seconds
Started Jul 14 07:19:21 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 206912 kb
Host smart-7cbd2359-d1af-4546-8e03-a8332836980d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3997996788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3997996788
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3395032091
Short name T590
Test name
Test status
Simulation time 3461666301 ps
CPU time 4.59 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206620 kb
Host smart-efa5af79-142d-48e5-9134-75eb0584c99a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3395032091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.3395032091
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.166017086
Short name T2423
Test name
Test status
Simulation time 13377644081 ps
CPU time 12.86 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:48 PM PDT 24
Peak memory 206932 kb
Host smart-54c91a74-f046-4ab4-9665-c7f5e106358f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=166017086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.166017086
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1781391856
Short name T2048
Test name
Test status
Simulation time 23357275240 ps
CPU time 25.01 seconds
Started Jul 14 07:19:23 PM PDT 24
Finished Jul 14 07:19:58 PM PDT 24
Peak memory 206924 kb
Host smart-f429a33a-f514-431a-8340-260a4eecba10
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1781391856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1781391856
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1443619686
Short name T1706
Test name
Test status
Simulation time 162556513 ps
CPU time 0.83 seconds
Started Jul 14 07:19:16 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 206860 kb
Host smart-2b460c5f-7b4f-49ce-a92d-59bb886228ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14436
19686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1443619686
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1449879648
Short name T1951
Test name
Test status
Simulation time 145514349 ps
CPU time 0.74 seconds
Started Jul 14 07:19:28 PM PDT 24
Finished Jul 14 07:19:41 PM PDT 24
Peak memory 206840 kb
Host smart-1f9eab09-8fb5-449c-9233-64ecd383043e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14498
79648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1449879648
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.4276364310
Short name T339
Test name
Test status
Simulation time 168929169 ps
CPU time 0.85 seconds
Started Jul 14 07:19:15 PM PDT 24
Finished Jul 14 07:19:26 PM PDT 24
Peak memory 206856 kb
Host smart-2a7cf7c9-23fd-42bb-9d7c-dd89aaf72fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42763
64310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.4276364310
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3273833521
Short name T905
Test name
Test status
Simulation time 321277531 ps
CPU time 1.02 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:28 PM PDT 24
Peak memory 206872 kb
Host smart-e4f3b031-9a9f-4866-95be-110d6f488ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32738
33521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3273833521
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3456607597
Short name T2229
Test name
Test status
Simulation time 390089984 ps
CPU time 1.33 seconds
Started Jul 14 07:19:16 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 206876 kb
Host smart-d0716298-626d-48a0-8cdf-9572e2ec0e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34566
07597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3456607597
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3889210553
Short name T1348
Test name
Test status
Simulation time 156150567 ps
CPU time 0.78 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:28 PM PDT 24
Peak memory 206872 kb
Host smart-7d2ba30f-378e-4980-9886-b5c07e211045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38892
10553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3889210553
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1091179684
Short name T837
Test name
Test status
Simulation time 56540843 ps
CPU time 0.65 seconds
Started Jul 14 07:19:23 PM PDT 24
Finished Jul 14 07:19:34 PM PDT 24
Peak memory 206884 kb
Host smart-7ffc8efa-34e8-4ef3-a0cc-5f9dd2fc67a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10911
79684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1091179684
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3100182332
Short name T2515
Test name
Test status
Simulation time 860945027 ps
CPU time 2.12 seconds
Started Jul 14 07:19:15 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 207088 kb
Host smart-f09c38a1-2920-45e4-b928-2fe820e856a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31001
82332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3100182332
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1017609031
Short name T1638
Test name
Test status
Simulation time 221721834 ps
CPU time 1.28 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 207048 kb
Host smart-9048fef2-c55c-4672-9287-86c6073118dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10176
09031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1017609031
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1104447810
Short name T1043
Test name
Test status
Simulation time 232497443 ps
CPU time 0.93 seconds
Started Jul 14 07:19:21 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 206808 kb
Host smart-1490557e-c5ae-469f-8cb2-db37bd1a32e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11044
47810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1104447810
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1447198029
Short name T1293
Test name
Test status
Simulation time 153131846 ps
CPU time 0.78 seconds
Started Jul 14 07:19:16 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 206872 kb
Host smart-0c86faf4-8c24-45ff-b82e-7dc2134c67ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14471
98029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1447198029
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1954668043
Short name T586
Test name
Test status
Simulation time 228210085 ps
CPU time 0.9 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 206832 kb
Host smart-94072b2d-c96e-4d71-9d77-e76c42c8e4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19546
68043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1954668043
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.493355453
Short name T2323
Test name
Test status
Simulation time 10937273974 ps
CPU time 34.1 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:20:01 PM PDT 24
Peak memory 207072 kb
Host smart-25b59c4a-e1b7-48f8-95f6-b8ab79e0015d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49335
5453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.493355453
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2906848822
Short name T636
Test name
Test status
Simulation time 314573995 ps
CPU time 0.99 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:19:38 PM PDT 24
Peak memory 206824 kb
Host smart-d6fe4b6e-a6ac-4661-a731-148ef771ff59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
48822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2906848822
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.147447071
Short name T1667
Test name
Test status
Simulation time 23275660980 ps
CPU time 23.92 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:59 PM PDT 24
Peak memory 206908 kb
Host smart-359aad19-ceee-4491-a90d-700b50498d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
7071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.147447071
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3952797623
Short name T2337
Test name
Test status
Simulation time 3305109923 ps
CPU time 4.01 seconds
Started Jul 14 07:19:19 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 206932 kb
Host smart-6c02e058-2d38-49bd-b6fd-2a166a65c47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
97623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3952797623
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.3642262639
Short name T2471
Test name
Test status
Simulation time 12086194113 ps
CPU time 87.66 seconds
Started Jul 14 07:19:16 PM PDT 24
Finished Jul 14 07:20:54 PM PDT 24
Peak memory 207128 kb
Host smart-d00e65eb-9e13-48e1-85fd-51fe698aba1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36422
62639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.3642262639
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1334724689
Short name T1227
Test name
Test status
Simulation time 5256130950 ps
CPU time 36.14 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:20:03 PM PDT 24
Peak memory 207052 kb
Host smart-6f7314d1-66b6-480f-8ec7-0ed84a36da4e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1334724689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1334724689
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2754649097
Short name T1626
Test name
Test status
Simulation time 243401839 ps
CPU time 0.92 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:36 PM PDT 24
Peak memory 206828 kb
Host smart-dd046a26-265f-49f1-a726-cb9cebf4bfa9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2754649097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2754649097
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2563711633
Short name T395
Test name
Test status
Simulation time 185541508 ps
CPU time 0.88 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:29 PM PDT 24
Peak memory 206868 kb
Host smart-1ca59c07-2639-4e7c-8069-4b5c98385e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25637
11633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2563711633
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1269451846
Short name T1306
Test name
Test status
Simulation time 4506686010 ps
CPU time 123.4 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 207116 kb
Host smart-8af99119-5525-4df4-99f3-f5f15428f6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12694
51846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1269451846
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3855113080
Short name T2421
Test name
Test status
Simulation time 4720842929 ps
CPU time 33.38 seconds
Started Jul 14 07:19:15 PM PDT 24
Finished Jul 14 07:19:59 PM PDT 24
Peak memory 207112 kb
Host smart-9eb65249-57b6-4c81-96a6-3335b0b8c5ce
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3855113080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3855113080
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.175817425
Short name T532
Test name
Test status
Simulation time 185561784 ps
CPU time 0.78 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 206868 kb
Host smart-9236ca18-e0a5-4221-ac09-f279c2d63a5e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=175817425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.175817425
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.153921290
Short name T552
Test name
Test status
Simulation time 158625438 ps
CPU time 0.78 seconds
Started Jul 14 07:19:16 PM PDT 24
Finished Jul 14 07:19:26 PM PDT 24
Peak memory 206848 kb
Host smart-9ffad654-c4be-48ae-8508-45df4746d726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15392
1290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.153921290
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1096170171
Short name T112
Test name
Test status
Simulation time 226470253 ps
CPU time 0.87 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 206852 kb
Host smart-b0c72d7d-ad08-4bca-b75a-7941161dd567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10961
70171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1096170171
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3489517487
Short name T1873
Test name
Test status
Simulation time 167969308 ps
CPU time 0.81 seconds
Started Jul 14 07:19:19 PM PDT 24
Finished Jul 14 07:19:29 PM PDT 24
Peak memory 206888 kb
Host smart-94bb0810-98de-4a26-ba5e-b9da6a1eb570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34895
17487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3489517487
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.962857872
Short name T854
Test name
Test status
Simulation time 164295115 ps
CPU time 0.8 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:29 PM PDT 24
Peak memory 206888 kb
Host smart-a54604f2-b279-477b-ab34-a64912de59c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96285
7872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.962857872
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1124194217
Short name T2063
Test name
Test status
Simulation time 234260088 ps
CPU time 0.91 seconds
Started Jul 14 07:19:19 PM PDT 24
Finished Jul 14 07:19:29 PM PDT 24
Peak memory 206872 kb
Host smart-ca9446ef-0316-4db0-99da-9b1607c0f563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11241
94217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1124194217
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2086175721
Short name T2079
Test name
Test status
Simulation time 149957452 ps
CPU time 0.79 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:19:38 PM PDT 24
Peak memory 206876 kb
Host smart-cad0f353-bd49-4b90-9fea-f5c6cc8e8d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
75721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2086175721
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.4124325464
Short name T1457
Test name
Test status
Simulation time 193873884 ps
CPU time 0.85 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:29 PM PDT 24
Peak memory 206868 kb
Host smart-9da24b67-f95a-4ce3-9ded-c3fa5dbe0fd5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4124325464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.4124325464
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2560838124
Short name T2476
Test name
Test status
Simulation time 188441761 ps
CPU time 0.81 seconds
Started Jul 14 07:19:19 PM PDT 24
Finished Jul 14 07:19:29 PM PDT 24
Peak memory 206868 kb
Host smart-66b9f0eb-c361-4f2a-9450-488ace41cc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25608
38124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2560838124
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2181233835
Short name T2349
Test name
Test status
Simulation time 54600598 ps
CPU time 0.69 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 206864 kb
Host smart-4014c74e-d10f-4717-8c31-36d9c7a31fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812
33835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2181233835
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2915302429
Short name T2160
Test name
Test status
Simulation time 16579472782 ps
CPU time 40.69 seconds
Started Jul 14 07:19:19 PM PDT 24
Finished Jul 14 07:20:09 PM PDT 24
Peak memory 207128 kb
Host smart-37dc0d12-bd63-4242-8f72-6c880b4c1ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
02429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2915302429
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.36942599
Short name T1212
Test name
Test status
Simulation time 191868278 ps
CPU time 0.79 seconds
Started Jul 14 07:19:21 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 206872 kb
Host smart-789b1aa3-4357-4ece-84f9-ca85d3932c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36942
599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.36942599
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1173156595
Short name T958
Test name
Test status
Simulation time 165580214 ps
CPU time 0.76 seconds
Started Jul 14 07:19:20 PM PDT 24
Finished Jul 14 07:19:31 PM PDT 24
Peak memory 206864 kb
Host smart-89c798c2-d206-40f2-b500-d1e157af8497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11731
56595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1173156595
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.713955592
Short name T947
Test name
Test status
Simulation time 186248655 ps
CPU time 0.85 seconds
Started Jul 14 07:19:21 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 206868 kb
Host smart-3f153661-3dc5-4f67-bbd6-72051649b595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71395
5592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.713955592
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.810084603
Short name T1183
Test name
Test status
Simulation time 183080804 ps
CPU time 0.89 seconds
Started Jul 14 07:19:21 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 206868 kb
Host smart-af4ccdb6-b9ec-4669-bebd-659b11dee147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81008
4603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.810084603
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1512535211
Short name T1271
Test name
Test status
Simulation time 163195476 ps
CPU time 0.79 seconds
Started Jul 14 07:19:20 PM PDT 24
Finished Jul 14 07:19:31 PM PDT 24
Peak memory 207040 kb
Host smart-9e8f3702-dc40-4945-8054-531d6312d36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125
35211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1512535211
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.158114732
Short name T2265
Test name
Test status
Simulation time 163147550 ps
CPU time 0.86 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206824 kb
Host smart-30d6ad9d-da91-4033-949f-1fb9b4de7eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15811
4732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.158114732
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3557127731
Short name T2282
Test name
Test status
Simulation time 153334601 ps
CPU time 0.82 seconds
Started Jul 14 07:19:18 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 207044 kb
Host smart-73aaf3d4-eda9-41b5-8e29-dcd9843e700c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35571
27731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3557127731
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3726946140
Short name T1899
Test name
Test status
Simulation time 235630901 ps
CPU time 0.91 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206848 kb
Host smart-4a95fe08-54d9-4df8-a413-b92332c35635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37269
46140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3726946140
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.345429061
Short name T2395
Test name
Test status
Simulation time 3729186077 ps
CPU time 27.26 seconds
Started Jul 14 07:19:20 PM PDT 24
Finished Jul 14 07:19:58 PM PDT 24
Peak memory 207288 kb
Host smart-1416776f-5eb6-41ac-a049-07c7f283715b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=345429061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.345429061
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1635422008
Short name T2383
Test name
Test status
Simulation time 180506091 ps
CPU time 0.85 seconds
Started Jul 14 07:19:21 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 206868 kb
Host smart-78f3c509-885d-41da-ae06-9163c6343aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16354
22008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1635422008
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2263308323
Short name T1677
Test name
Test status
Simulation time 172429206 ps
CPU time 0.78 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:19:27 PM PDT 24
Peak memory 206852 kb
Host smart-af35f6f3-62c3-477d-974c-8de95a8291bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22633
08323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2263308323
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3003998425
Short name T2174
Test name
Test status
Simulation time 829573912 ps
CPU time 1.87 seconds
Started Jul 14 07:19:30 PM PDT 24
Finished Jul 14 07:19:45 PM PDT 24
Peak memory 207072 kb
Host smart-a621bf1d-7780-493f-b08a-71c822b36fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30039
98425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3003998425
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.387802407
Short name T176
Test name
Test status
Simulation time 5727413669 ps
CPU time 162.95 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:22:25 PM PDT 24
Peak memory 207032 kb
Host smart-38d1b962-2e4b-49bd-941b-49f2ceea29c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38780
2407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.387802407
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1333084095
Short name T567
Test name
Test status
Simulation time 75189962 ps
CPU time 0.71 seconds
Started Jul 14 07:19:30 PM PDT 24
Finished Jul 14 07:19:45 PM PDT 24
Peak memory 206908 kb
Host smart-8f0c5047-5ebf-4cdf-8207-a2c1c9012656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1333084095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1333084095
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3129886839
Short name T940
Test name
Test status
Simulation time 3975900117 ps
CPU time 4.5 seconds
Started Jul 14 07:19:28 PM PDT 24
Finished Jul 14 07:19:45 PM PDT 24
Peak memory 207152 kb
Host smart-cd1c3098-5802-4973-b4fb-fafd376ef5f1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3129886839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3129886839
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3836080419
Short name T2532
Test name
Test status
Simulation time 13297448681 ps
CPU time 13.28 seconds
Started Jul 14 07:19:28 PM PDT 24
Finished Jul 14 07:19:54 PM PDT 24
Peak memory 207128 kb
Host smart-ab028988-1c80-4319-9bfd-4112d6ce422d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3836080419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3836080419
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1282850112
Short name T1549
Test name
Test status
Simulation time 23497759766 ps
CPU time 23.58 seconds
Started Jul 14 07:19:17 PM PDT 24
Finished Jul 14 07:19:50 PM PDT 24
Peak memory 207084 kb
Host smart-47f2fe80-4edc-490c-9a18-f9457537b101
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1282850112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.1282850112
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3944561103
Short name T1989
Test name
Test status
Simulation time 181166575 ps
CPU time 0.83 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206852 kb
Host smart-0813ea61-6656-4fd1-b631-a12ed0fabd58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39445
61103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3944561103
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1446074474
Short name T58
Test name
Test status
Simulation time 181975380 ps
CPU time 0.83 seconds
Started Jul 14 07:19:20 PM PDT 24
Finished Jul 14 07:19:31 PM PDT 24
Peak memory 206872 kb
Host smart-a3993e8a-c4a4-45b0-b4d4-763882b49a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14460
74474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1446074474
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.584663756
Short name T2436
Test name
Test status
Simulation time 371653924 ps
CPU time 1.29 seconds
Started Jul 14 07:19:19 PM PDT 24
Finished Jul 14 07:19:30 PM PDT 24
Peak memory 206872 kb
Host smart-61a2228e-8d34-4099-98a4-3987bf27b7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58466
3756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.584663756
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3069056973
Short name T2087
Test name
Test status
Simulation time 1168033333 ps
CPU time 2.73 seconds
Started Jul 14 07:19:21 PM PDT 24
Finished Jul 14 07:19:35 PM PDT 24
Peak memory 207072 kb
Host smart-1c95cef9-e24e-47be-9df8-cd465b704001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30690
56973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3069056973
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.87629548
Short name T86
Test name
Test status
Simulation time 8092275724 ps
CPU time 14.48 seconds
Started Jul 14 07:19:16 PM PDT 24
Finished Jul 14 07:19:40 PM PDT 24
Peak memory 207100 kb
Host smart-9714e430-18c0-4cf5-a98b-d64887e7e704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87629
548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.87629548
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.1025128188
Short name T2147
Test name
Test status
Simulation time 358151149 ps
CPU time 1.23 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:19:38 PM PDT 24
Peak memory 206868 kb
Host smart-971029df-5ca8-43c5-9ece-6a14dabd050c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10251
28188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.1025128188
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2316756479
Short name T2443
Test name
Test status
Simulation time 149096217 ps
CPU time 0.74 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:00 PM PDT 24
Peak memory 206884 kb
Host smart-7476d870-b5f1-4f2d-b75b-80af4566808b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
56479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2316756479
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1961787644
Short name T407
Test name
Test status
Simulation time 34728814 ps
CPU time 0.67 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:19:50 PM PDT 24
Peak memory 206836 kb
Host smart-a24554a8-f004-43df-ad3a-c5c7331fa19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19617
87644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1961787644
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3007618099
Short name T831
Test name
Test status
Simulation time 845795051 ps
CPU time 2.03 seconds
Started Jul 14 07:19:32 PM PDT 24
Finished Jul 14 07:19:50 PM PDT 24
Peak memory 207008 kb
Host smart-66ec24cd-908c-4334-82ba-011c91a0c697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30076
18099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3007618099
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2605166357
Short name T2694
Test name
Test status
Simulation time 273947230 ps
CPU time 1.73 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:44 PM PDT 24
Peak memory 207036 kb
Host smart-42ac84bb-b870-4a18-b01a-d0c806892bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26051
66357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2605166357
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1428155853
Short name T305
Test name
Test status
Simulation time 221213345 ps
CPU time 0.87 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:36 PM PDT 24
Peak memory 206864 kb
Host smart-1b2e6f77-9854-4a0a-8f97-43d7a25f6ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14281
55853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1428155853
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2310477375
Short name T2737
Test name
Test status
Simulation time 141705413 ps
CPU time 0.78 seconds
Started Jul 14 07:19:30 PM PDT 24
Finished Jul 14 07:19:44 PM PDT 24
Peak memory 206896 kb
Host smart-faa1b9e8-becc-45a5-84fa-62a366c18ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23104
77375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2310477375
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.120537142
Short name T2640
Test name
Test status
Simulation time 193811699 ps
CPU time 0.85 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 206860 kb
Host smart-69563c0c-9975-4cec-aa72-4d3647fe5722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12053
7142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.120537142
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.315759879
Short name T359
Test name
Test status
Simulation time 5175190492 ps
CPU time 17.34 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206980 kb
Host smart-6c5ccc23-58db-4d14-b139-47e7fcad0f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31575
9879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.315759879
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3620920548
Short name T577
Test name
Test status
Simulation time 206983189 ps
CPU time 0.91 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:37 PM PDT 24
Peak memory 206852 kb
Host smart-c6db904f-c577-4a7e-979c-39379c27f5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36209
20548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3620920548
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3566758982
Short name T1404
Test name
Test status
Simulation time 23370910657 ps
CPU time 22.63 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:20:00 PM PDT 24
Peak memory 206940 kb
Host smart-f47cc314-04ed-45aa-9313-d0952362b938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35667
58982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3566758982
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.227596707
Short name T1040
Test name
Test status
Simulation time 3369933826 ps
CPU time 4.08 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:19:42 PM PDT 24
Peak memory 206924 kb
Host smart-97409165-8ec5-4d32-9069-e73316cdb088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22759
6707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.227596707
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.4163601333
Short name T508
Test name
Test status
Simulation time 12687659339 ps
CPU time 121.73 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:21:38 PM PDT 24
Peak memory 207144 kb
Host smart-ecb87a86-4c9b-4edf-9a10-84a36cda2f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41636
01333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.4163601333
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.968495645
Short name T1289
Test name
Test status
Simulation time 6194345909 ps
CPU time 173.85 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:22:30 PM PDT 24
Peak memory 207080 kb
Host smart-cb5e8b6a-ed4f-4311-8dcb-04e599ce5eb2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=968495645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.968495645
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1564190037
Short name T2280
Test name
Test status
Simulation time 244925906 ps
CPU time 0.91 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206884 kb
Host smart-74363c07-da5e-4d17-8d6b-c8d3be4888d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1564190037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1564190037
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1344963134
Short name T1211
Test name
Test status
Simulation time 206585506 ps
CPU time 0.87 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:19:50 PM PDT 24
Peak memory 206844 kb
Host smart-445b541c-4d13-4c34-8cb9-34b4a0a86db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13449
63134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1344963134
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.3146683413
Short name T1454
Test name
Test status
Simulation time 6312858682 ps
CPU time 45.52 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:20:23 PM PDT 24
Peak memory 207060 kb
Host smart-dd873089-8ce7-4336-bfe9-27a6c05d7e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31466
83413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.3146683413
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.4034226073
Short name T2143
Test name
Test status
Simulation time 5369825576 ps
CPU time 38.24 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:38 PM PDT 24
Peak memory 207076 kb
Host smart-9d756d29-c51a-4ecb-9361-a7952ee581ca
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4034226073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.4034226073
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3314334485
Short name T2382
Test name
Test status
Simulation time 226968991 ps
CPU time 0.84 seconds
Started Jul 14 07:19:31 PM PDT 24
Finished Jul 14 07:19:47 PM PDT 24
Peak memory 206892 kb
Host smart-51c17b5f-7450-4986-beaf-8e0e81a8884a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3314334485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3314334485
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3424151030
Short name T2306
Test name
Test status
Simulation time 145243251 ps
CPU time 0.76 seconds
Started Jul 14 07:19:31 PM PDT 24
Finished Jul 14 07:19:47 PM PDT 24
Peak memory 206876 kb
Host smart-2ef957e8-0731-49d3-9b48-e3ddb3685c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34241
51030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3424151030
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2998941382
Short name T2393
Test name
Test status
Simulation time 245625791 ps
CPU time 0.89 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206848 kb
Host smart-9223fa22-5634-47de-ae8f-51e4a5a91f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29989
41382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2998941382
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4167056451
Short name T2272
Test name
Test status
Simulation time 235350811 ps
CPU time 0.85 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 206880 kb
Host smart-d53ada97-8a9a-47ab-8adc-344de19cf3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41670
56451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4167056451
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1124685692
Short name T2230
Test name
Test status
Simulation time 184375149 ps
CPU time 0.79 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:00 PM PDT 24
Peak memory 206884 kb
Host smart-02ffa751-bef9-4987-877d-fee7c862d5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11246
85692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1124685692
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2295991527
Short name T1339
Test name
Test status
Simulation time 150893166 ps
CPU time 0.78 seconds
Started Jul 14 07:19:32 PM PDT 24
Finished Jul 14 07:19:49 PM PDT 24
Peak memory 206768 kb
Host smart-bbbf0505-7b81-4ccb-a24f-660f30682953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22959
91527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2295991527
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1936655507
Short name T1376
Test name
Test status
Simulation time 262954539 ps
CPU time 0.94 seconds
Started Jul 14 07:19:23 PM PDT 24
Finished Jul 14 07:19:34 PM PDT 24
Peak memory 206864 kb
Host smart-3fdc2c5c-2b4f-474d-9802-0e0c3977f391
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1936655507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1936655507
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3037638992
Short name T2207
Test name
Test status
Simulation time 140811631 ps
CPU time 0.79 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:19:38 PM PDT 24
Peak memory 206868 kb
Host smart-5e586142-4bb5-409d-9ef4-6e68aa44c1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
38992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3037638992
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3091310759
Short name T646
Test name
Test status
Simulation time 34209531 ps
CPU time 0.66 seconds
Started Jul 14 07:19:28 PM PDT 24
Finished Jul 14 07:19:41 PM PDT 24
Peak memory 206864 kb
Host smart-526dab16-4345-458e-9c26-803b31dd5dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30913
10759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3091310759
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1900710678
Short name T2619
Test name
Test status
Simulation time 12329810402 ps
CPU time 30.34 seconds
Started Jul 14 07:19:24 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 207184 kb
Host smart-7925bac6-2bb4-437d-a7dc-5ed1d3835509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19007
10678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1900710678
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1337126644
Short name T1531
Test name
Test status
Simulation time 172308779 ps
CPU time 0.79 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:36 PM PDT 24
Peak memory 206868 kb
Host smart-a0c764a1-7a90-412f-b4ff-53a09be65a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13371
26644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1337126644
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1781642418
Short name T354
Test name
Test status
Simulation time 193932950 ps
CPU time 0.87 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206888 kb
Host smart-11e09276-6b8f-4757-8498-8186a123ab2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17816
42418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1781642418
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1424356048
Short name T1030
Test name
Test status
Simulation time 239742462 ps
CPU time 0.99 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206812 kb
Host smart-1b4a0b1d-cdfc-400c-b816-c06b7640025f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14243
56048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1424356048
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2617922226
Short name T1804
Test name
Test status
Simulation time 173415887 ps
CPU time 0.82 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:47 PM PDT 24
Peak memory 206896 kb
Host smart-a98e6071-aae8-42af-8241-e925626e2f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
22226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2617922226
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2505837306
Short name T33
Test name
Test status
Simulation time 159086177 ps
CPU time 0.8 seconds
Started Jul 14 07:19:31 PM PDT 24
Finished Jul 14 07:19:47 PM PDT 24
Peak memory 206860 kb
Host smart-292834ab-e1a5-45f6-b702-38a9dcb25c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058
37306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2505837306
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1095130206
Short name T2118
Test name
Test status
Simulation time 166414676 ps
CPU time 0.8 seconds
Started Jul 14 07:19:31 PM PDT 24
Finished Jul 14 07:19:47 PM PDT 24
Peak memory 206304 kb
Host smart-98923546-197c-40ea-aa1d-551226e07f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10951
30206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1095130206
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2220772216
Short name T1679
Test name
Test status
Simulation time 169520826 ps
CPU time 0.79 seconds
Started Jul 14 07:19:26 PM PDT 24
Finished Jul 14 07:19:38 PM PDT 24
Peak memory 206872 kb
Host smart-b04ada5a-beed-4d0f-99c2-043250b9c132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22207
72216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2220772216
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1819645367
Short name T2084
Test name
Test status
Simulation time 235230406 ps
CPU time 1.03 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 206888 kb
Host smart-9dc4f693-4785-4faf-81bf-b42f92d61a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18196
45367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1819645367
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3218302404
Short name T1786
Test name
Test status
Simulation time 4488266120 ps
CPU time 128.93 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 207076 kb
Host smart-3399887b-66de-4b11-abe1-e1955cf003c4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3218302404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3218302404
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1414150392
Short name T1196
Test name
Test status
Simulation time 151400308 ps
CPU time 0.82 seconds
Started Jul 14 07:19:28 PM PDT 24
Finished Jul 14 07:19:41 PM PDT 24
Peak memory 206860 kb
Host smart-43eb9417-c99f-49df-aebc-f13c4545946f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141
50392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1414150392
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2096942656
Short name T1473
Test name
Test status
Simulation time 196195850 ps
CPU time 0.79 seconds
Started Jul 14 07:19:23 PM PDT 24
Finished Jul 14 07:19:34 PM PDT 24
Peak memory 206880 kb
Host smart-b8f9e113-52c5-48cb-adcf-e1bf63504b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20969
42656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2096942656
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2059120773
Short name T1415
Test name
Test status
Simulation time 851699603 ps
CPU time 2.01 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:37 PM PDT 24
Peak memory 207056 kb
Host smart-883be570-0940-44d6-8330-bd7d2ef88c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
20773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2059120773
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1032265537
Short name T1065
Test name
Test status
Simulation time 5555433729 ps
CPU time 54.73 seconds
Started Jul 14 07:19:23 PM PDT 24
Finished Jul 14 07:20:27 PM PDT 24
Peak memory 207064 kb
Host smart-1beeb22d-7214-4642-b971-9305ddcd612a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10322
65537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1032265537
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.3828650414
Short name T1137
Test name
Test status
Simulation time 36752943 ps
CPU time 0.72 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:19:50 PM PDT 24
Peak memory 206932 kb
Host smart-0f768111-a1d9-4bca-906f-6a14a9346054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3828650414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3828650414
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3698557466
Short name T562
Test name
Test status
Simulation time 3817525639 ps
CPU time 4.87 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:40 PM PDT 24
Peak memory 206976 kb
Host smart-64e2f086-e3be-44f6-81b5-f28448cb4875
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3698557466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3698557466
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3143086575
Short name T217
Test name
Test status
Simulation time 13541311736 ps
CPU time 16.89 seconds
Started Jul 14 07:19:31 PM PDT 24
Finished Jul 14 07:20:03 PM PDT 24
Peak memory 206448 kb
Host smart-01df2b8a-a295-425f-ba0a-ec1d3bf9c26b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3143086575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3143086575
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3048700053
Short name T1494
Test name
Test status
Simulation time 23398767166 ps
CPU time 28.84 seconds
Started Jul 14 07:19:32 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 206796 kb
Host smart-aa4304eb-0656-433f-9983-37f578b900a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3048700053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3048700053
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3173525377
Short name T607
Test name
Test status
Simulation time 162555621 ps
CPU time 0.82 seconds
Started Jul 14 07:19:24 PM PDT 24
Finished Jul 14 07:19:36 PM PDT 24
Peak memory 206864 kb
Host smart-5c83f66d-4e16-4408-8795-4ec1ad88e1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31735
25377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3173525377
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3649543591
Short name T494
Test name
Test status
Simulation time 148884556 ps
CPU time 0.81 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:19:50 PM PDT 24
Peak memory 206804 kb
Host smart-2157e6cd-689e-4ae0-8d34-df11d0f9d8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
43591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3649543591
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.949982940
Short name T1000
Test name
Test status
Simulation time 417873471 ps
CPU time 1.39 seconds
Started Jul 14 07:19:25 PM PDT 24
Finished Jul 14 07:19:37 PM PDT 24
Peak memory 206884 kb
Host smart-9d9756b8-9a5d-4209-a7c2-589b7a2401e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94998
2940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.949982940
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1120390378
Short name T2539
Test name
Test status
Simulation time 1143817366 ps
CPU time 2.35 seconds
Started Jul 14 07:19:30 PM PDT 24
Finished Jul 14 07:19:47 PM PDT 24
Peak memory 207044 kb
Host smart-252ab118-8572-40e2-8695-bf9a83f521b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11203
90378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1120390378
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3825664339
Short name T999
Test name
Test status
Simulation time 21199130791 ps
CPU time 38.21 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:20:15 PM PDT 24
Peak memory 207120 kb
Host smart-4f4f915c-e7aa-444e-a375-316b9e325103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
64339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3825664339
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.26490417
Short name T1219
Test name
Test status
Simulation time 466303977 ps
CPU time 1.54 seconds
Started Jul 14 07:19:29 PM PDT 24
Finished Jul 14 07:19:44 PM PDT 24
Peak memory 206808 kb
Host smart-e51b2a5d-3e36-4df4-9c34-f87fabf0a6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.26490417
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.697123149
Short name T1250
Test name
Test status
Simulation time 135062328 ps
CPU time 0.74 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206884 kb
Host smart-359fb46b-a67f-496a-baee-0d8557a021d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69712
3149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.697123149
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3319669864
Short name T1095
Test name
Test status
Simulation time 37899847 ps
CPU time 0.66 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:19:57 PM PDT 24
Peak memory 206352 kb
Host smart-21fb3e57-0f6d-4554-8b91-67012afc687b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33196
69864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3319669864
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1087723068
Short name T2312
Test name
Test status
Simulation time 882013087 ps
CPU time 2.15 seconds
Started Jul 14 07:19:27 PM PDT 24
Finished Jul 14 07:19:40 PM PDT 24
Peak memory 207076 kb
Host smart-79e9bb77-e655-4e0e-99d6-27be2f50994b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10877
23068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1087723068
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1309587684
Short name T185
Test name
Test status
Simulation time 338078389 ps
CPU time 2.11 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:19:59 PM PDT 24
Peak memory 207072 kb
Host smart-5a1b190a-bf60-4888-90e1-de57a00652d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
87684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1309587684
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.730573477
Short name T1821
Test name
Test status
Simulation time 220036125 ps
CPU time 0.87 seconds
Started Jul 14 07:19:28 PM PDT 24
Finished Jul 14 07:19:40 PM PDT 24
Peak memory 206876 kb
Host smart-6e172b4c-d1b2-46b1-9e45-4cad954319e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73057
3477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.730573477
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3711801686
Short name T601
Test name
Test status
Simulation time 192870940 ps
CPU time 0.78 seconds
Started Jul 14 07:19:30 PM PDT 24
Finished Jul 14 07:19:45 PM PDT 24
Peak memory 206824 kb
Host smart-0dc1088b-7e5e-49e9-bdb1-6837a7e4d114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37118
01686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3711801686
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2800352850
Short name T2740
Test name
Test status
Simulation time 185096602 ps
CPU time 0.86 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:19:55 PM PDT 24
Peak memory 206848 kb
Host smart-c7facc53-eb42-4a5d-93fb-d2ec77b0a076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28003
52850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2800352850
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.905605519
Short name T368
Test name
Test status
Simulation time 234723240 ps
CPU time 0.88 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:20:03 PM PDT 24
Peak memory 206288 kb
Host smart-441963c5-06a1-4d23-a824-2511cbf9b5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90560
5519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.905605519
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1838304726
Short name T697
Test name
Test status
Simulation time 23387815232 ps
CPU time 26.17 seconds
Started Jul 14 07:19:39 PM PDT 24
Finished Jul 14 07:20:27 PM PDT 24
Peak memory 206772 kb
Host smart-45cc88ec-b599-4bdd-90bc-4cd99a825dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18383
04726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1838304726
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2324145251
Short name T1950
Test name
Test status
Simulation time 3331624745 ps
CPU time 4.09 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:20:06 PM PDT 24
Peak memory 206360 kb
Host smart-147b647c-ec13-4587-a164-7fb0a114084d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23241
45251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2324145251
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1496634366
Short name T1613
Test name
Test status
Simulation time 9140956113 ps
CPU time 239.94 seconds
Started Jul 14 07:19:39 PM PDT 24
Finished Jul 14 07:24:01 PM PDT 24
Peak memory 207028 kb
Host smart-eac90378-273b-4523-b508-43e4277e1461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966
34366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1496634366
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3018062599
Short name T2673
Test name
Test status
Simulation time 3492625054 ps
CPU time 92.05 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:21:26 PM PDT 24
Peak memory 207076 kb
Host smart-e3662ecb-657a-479a-82e0-cc47bddbf4db
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3018062599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3018062599
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3715291106
Short name T588
Test name
Test status
Simulation time 274703924 ps
CPU time 0.99 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206868 kb
Host smart-f74c0446-f2c7-4a57-ab9d-24b1623c4bdc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3715291106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3715291106
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1677460066
Short name T1070
Test name
Test status
Simulation time 184946119 ps
CPU time 0.86 seconds
Started Jul 14 07:19:37 PM PDT 24
Finished Jul 14 07:19:58 PM PDT 24
Peak memory 206872 kb
Host smart-29dfbe32-df27-4d01-9050-946ec815f362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16774
60066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1677460066
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2457361723
Short name T2427
Test name
Test status
Simulation time 5027571352 ps
CPU time 139.59 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:22:22 PM PDT 24
Peak memory 207096 kb
Host smart-6344bcae-f935-4f36-9a5c-6cc102edb836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24573
61723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2457361723
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1695413322
Short name T2248
Test name
Test status
Simulation time 5072704965 ps
CPU time 136.72 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:22:14 PM PDT 24
Peak memory 207072 kb
Host smart-b8d7c391-e93a-46a7-a358-8beba56c0472
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1695413322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1695413322
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.34230931
Short name T701
Test name
Test status
Simulation time 160246421 ps
CPU time 0.83 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206860 kb
Host smart-ff74ef75-2c50-4601-b7ad-02609f0299b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=34230931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.34230931
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3628638097
Short name T925
Test name
Test status
Simulation time 145648957 ps
CPU time 0.76 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:19:57 PM PDT 24
Peak memory 206844 kb
Host smart-2a12b327-7b60-4d43-ad17-d592caaed3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36286
38097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3628638097
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1730257895
Short name T116
Test name
Test status
Simulation time 212604889 ps
CPU time 0.83 seconds
Started Jul 14 07:19:37 PM PDT 24
Finished Jul 14 07:19:58 PM PDT 24
Peak memory 206872 kb
Host smart-84f59d59-82fc-46e1-992d-3e26fa40ddc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17302
57895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1730257895
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3477687458
Short name T689
Test name
Test status
Simulation time 185700692 ps
CPU time 0.85 seconds
Started Jul 14 07:19:32 PM PDT 24
Finished Jul 14 07:19:49 PM PDT 24
Peak memory 206888 kb
Host smart-807d83a2-91cf-4d33-aef2-2ee03964af36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34776
87458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3477687458
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2356267623
Short name T31
Test name
Test status
Simulation time 173239978 ps
CPU time 0.81 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:19:54 PM PDT 24
Peak memory 206864 kb
Host smart-5c504023-4e91-4191-90d3-a444fff45950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23562
67623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2356267623
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.13746266
Short name T557
Test name
Test status
Simulation time 199902619 ps
CPU time 0.82 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:19:54 PM PDT 24
Peak memory 206868 kb
Host smart-d0d794ec-d0fb-47ee-96f2-997fb1aa1500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13746
266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.13746266
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3311971393
Short name T2088
Test name
Test status
Simulation time 156580137 ps
CPU time 0.79 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:05 PM PDT 24
Peak memory 206888 kb
Host smart-f9ee7534-0d08-49f1-b744-651c3b5e0e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33119
71393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3311971393
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2029365038
Short name T1936
Test name
Test status
Simulation time 225044694 ps
CPU time 0.9 seconds
Started Jul 14 07:19:39 PM PDT 24
Finished Jul 14 07:20:02 PM PDT 24
Peak memory 206888 kb
Host smart-a977d37a-08ec-412e-b56f-670bca4dd305
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2029365038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2029365038
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.15981836
Short name T2283
Test name
Test status
Simulation time 150722120 ps
CPU time 0.78 seconds
Started Jul 14 07:19:37 PM PDT 24
Finished Jul 14 07:19:58 PM PDT 24
Peak memory 206852 kb
Host smart-da019d2f-fa18-46fb-a08d-ab643dca1f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15981
836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.15981836
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1004626948
Short name T722
Test name
Test status
Simulation time 37620157 ps
CPU time 0.64 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:19:57 PM PDT 24
Peak memory 206696 kb
Host smart-fa6548a0-add5-4a92-9fc3-9d3b5dbfb6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10046
26948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1004626948
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3615455840
Short name T270
Test name
Test status
Simulation time 7081409942 ps
CPU time 16.02 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206824 kb
Host smart-3b1160f6-add7-4615-b3df-d05eaacb4a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36154
55840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3615455840
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3591771880
Short name T611
Test name
Test status
Simulation time 159164847 ps
CPU time 0.84 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:19:57 PM PDT 24
Peak memory 206804 kb
Host smart-5955979e-7e70-427e-80c6-732c8e29c1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35917
71880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3591771880
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3824700272
Short name T1832
Test name
Test status
Simulation time 256664636 ps
CPU time 0.92 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206780 kb
Host smart-90427089-8534-4776-a858-2dfe5e9d83cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
00272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3824700272
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2661473579
Short name T1829
Test name
Test status
Simulation time 177410083 ps
CPU time 0.82 seconds
Started Jul 14 07:19:28 PM PDT 24
Finished Jul 14 07:19:43 PM PDT 24
Peak memory 206896 kb
Host smart-5630b9ae-41c8-4230-a182-6d8f35ac6005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26614
73579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2661473579
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.3061480605
Short name T1362
Test name
Test status
Simulation time 194318829 ps
CPU time 0.81 seconds
Started Jul 14 07:19:43 PM PDT 24
Finished Jul 14 07:20:05 PM PDT 24
Peak memory 206848 kb
Host smart-15da0518-bf1d-4a9e-993e-9f60457d7580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30614
80605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.3061480605
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.420392545
Short name T1153
Test name
Test status
Simulation time 194890796 ps
CPU time 0.81 seconds
Started Jul 14 07:19:30 PM PDT 24
Finished Jul 14 07:19:47 PM PDT 24
Peak memory 206832 kb
Host smart-6417d294-0fd8-4bdc-8a7d-8d001716ad0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42039
2545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.420392545
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1960421961
Short name T360
Test name
Test status
Simulation time 149599128 ps
CPU time 0.74 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:20:03 PM PDT 24
Peak memory 206864 kb
Host smart-5977bfae-9fc1-437c-af66-d4c1b6d62eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19604
21961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1960421961
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1093957290
Short name T1639
Test name
Test status
Simulation time 151302984 ps
CPU time 0.76 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:19:57 PM PDT 24
Peak memory 206844 kb
Host smart-374dbdec-f9a4-4cd5-8ae5-a2e9cf5dc57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10939
57290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1093957290
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.472125543
Short name T147
Test name
Test status
Simulation time 232319664 ps
CPU time 0.88 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:19:57 PM PDT 24
Peak memory 206840 kb
Host smart-859e45f3-f205-4a07-8d04-dc8e60da8efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47212
5543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.472125543
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2327081754
Short name T2486
Test name
Test status
Simulation time 5691470610 ps
CPU time 52.83 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:56 PM PDT 24
Peak memory 207064 kb
Host smart-7e9a19b3-3ed4-4f46-b0d7-2d8076001a5c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2327081754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2327081754
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.848940919
Short name T1977
Test name
Test status
Simulation time 154650542 ps
CPU time 0.78 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206796 kb
Host smart-76ef8c2d-cd1c-4371-84e0-433e25cd092a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84894
0919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.848940919
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.4147344652
Short name T1644
Test name
Test status
Simulation time 160240549 ps
CPU time 0.77 seconds
Started Jul 14 07:19:43 PM PDT 24
Finished Jul 14 07:20:05 PM PDT 24
Peak memory 206844 kb
Host smart-dd7b8eda-9f3f-427d-8aed-0ee2774b7a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41473
44652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.4147344652
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.400007700
Short name T341
Test name
Test status
Simulation time 1052405064 ps
CPU time 2.11 seconds
Started Jul 14 07:19:32 PM PDT 24
Finished Jul 14 07:19:51 PM PDT 24
Peak memory 207040 kb
Host smart-7e60ec7f-8b04-4d75-a814-0651884f3618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40000
7700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.400007700
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3143655574
Short name T2408
Test name
Test status
Simulation time 4626218354 ps
CPU time 124.93 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:22:08 PM PDT 24
Peak memory 207088 kb
Host smart-4af923c1-6635-4577-b8ba-513b9523fbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31436
55574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3143655574
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.539973121
Short name T489
Test name
Test status
Simulation time 36788983 ps
CPU time 0.69 seconds
Started Jul 14 07:19:46 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206928 kb
Host smart-e953c032-ab8a-4115-97f6-75cff78b6e7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=539973121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.539973121
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2420462228
Short name T1505
Test name
Test status
Simulation time 3936611794 ps
CPU time 4.5 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:19:54 PM PDT 24
Peak memory 206924 kb
Host smart-02eb7305-6421-4049-b112-8fc01fa89913
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2420462228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2420462228
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3734347507
Short name T2270
Test name
Test status
Simulation time 13520853462 ps
CPU time 12.63 seconds
Started Jul 14 07:19:43 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 207136 kb
Host smart-c4ec08ee-4fcf-4fba-b18b-ea5bf75ecb05
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3734347507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3734347507
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2341128481
Short name T12
Test name
Test status
Simulation time 23435685168 ps
CPU time 26.08 seconds
Started Jul 14 07:19:43 PM PDT 24
Finished Jul 14 07:20:31 PM PDT 24
Peak memory 206936 kb
Host smart-a748d69d-0b51-442f-99b2-5b153527d9aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2341128481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2341128481
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2742561918
Short name T1841
Test name
Test status
Simulation time 156540622 ps
CPU time 0.78 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:00 PM PDT 24
Peak memory 206888 kb
Host smart-af36a5f5-6948-47ad-b229-586729d1a32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27425
61918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2742561918
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2967230759
Short name T772
Test name
Test status
Simulation time 166509486 ps
CPU time 0.76 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:19:53 PM PDT 24
Peak memory 206884 kb
Host smart-a5ef215a-fd84-44c1-83eb-366261420996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29672
30759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2967230759
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1984377176
Short name T1430
Test name
Test status
Simulation time 475948005 ps
CPU time 1.42 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:01 PM PDT 24
Peak memory 206860 kb
Host smart-d6578ed2-a180-41e7-8079-1171aa5c68cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19843
77176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1984377176
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3496722165
Short name T2394
Test name
Test status
Simulation time 1336943335 ps
CPU time 2.81 seconds
Started Jul 14 07:19:31 PM PDT 24
Finished Jul 14 07:19:49 PM PDT 24
Peak memory 207084 kb
Host smart-562e3570-5f61-4c03-82f9-634b1b4298b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34967
22165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3496722165
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2208334603
Short name T1375
Test name
Test status
Simulation time 7919907637 ps
CPU time 14.58 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 207104 kb
Host smart-3f5e4db5-a85e-4e67-9a23-7178d69aef39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22083
34603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2208334603
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3625930742
Short name T1875
Test name
Test status
Simulation time 493909061 ps
CPU time 1.34 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:19:54 PM PDT 24
Peak memory 206860 kb
Host smart-3dcf0467-60f7-476c-918a-3e2dc3398f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36259
30742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3625930742
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.1368497695
Short name T1632
Test name
Test status
Simulation time 186881478 ps
CPU time 0.78 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206880 kb
Host smart-7fcfe766-73dd-495a-abdc-966604093401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13684
97695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1368497695
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.980314296
Short name T1993
Test name
Test status
Simulation time 50358563 ps
CPU time 0.65 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:19:52 PM PDT 24
Peak memory 206840 kb
Host smart-f4ae7bc0-8032-4307-912a-2043aeaf53c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98031
4296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.980314296
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.3337513816
Short name T2169
Test name
Test status
Simulation time 893594982 ps
CPU time 2.04 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:19:55 PM PDT 24
Peak memory 206932 kb
Host smart-547075f3-1aab-4b71-80f3-a7e5b943c894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33375
13816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3337513816
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3623077842
Short name T2247
Test name
Test status
Simulation time 302636628 ps
CPU time 1.68 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 207028 kb
Host smart-533de2af-1784-4344-8229-2945aae5581e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36230
77842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3623077842
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.44524796
Short name T1560
Test name
Test status
Simulation time 223454935 ps
CPU time 0.88 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:19:55 PM PDT 24
Peak memory 206848 kb
Host smart-47ecc44d-f269-4231-9fdb-8fd42db75f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44524
796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.44524796
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3501070457
Short name T576
Test name
Test status
Simulation time 155607612 ps
CPU time 0.76 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:19:54 PM PDT 24
Peak memory 206788 kb
Host smart-e72001a8-77f3-4051-994d-4883802e3460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35010
70457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3501070457
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2902747373
Short name T2665
Test name
Test status
Simulation time 211329111 ps
CPU time 0.94 seconds
Started Jul 14 07:19:37 PM PDT 24
Finished Jul 14 07:19:58 PM PDT 24
Peak memory 206868 kb
Host smart-0cea875c-b577-4904-8cd4-feaa6370bbac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29027
47373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2902747373
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2224586342
Short name T380
Test name
Test status
Simulation time 6883407148 ps
CPU time 21.86 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:25 PM PDT 24
Peak memory 207124 kb
Host smart-6bc9da55-b433-4e88-be5b-36e03e1a213a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22245
86342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2224586342
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.1432103434
Short name T843
Test name
Test status
Simulation time 220324079 ps
CPU time 0.83 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206888 kb
Host smart-6a00ca4e-bfd8-4a03-af3e-021c9ab224fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14321
03434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.1432103434
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2688863034
Short name T1361
Test name
Test status
Simulation time 23297026734 ps
CPU time 24.5 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:20:18 PM PDT 24
Peak memory 206932 kb
Host smart-3ed9a99c-7d21-4f4e-b163-8bee8af7ae2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26888
63034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2688863034
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1402202901
Short name T1045
Test name
Test status
Simulation time 3286057443 ps
CPU time 3.59 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:06 PM PDT 24
Peak memory 206944 kb
Host smart-a9147d76-603c-4743-8ae3-58914bf82e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
02901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1402202901
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3131400682
Short name T476
Test name
Test status
Simulation time 11706043033 ps
CPU time 329.4 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:25:25 PM PDT 24
Peak memory 207348 kb
Host smart-c74613ed-e819-48b7-8a9a-75515f585100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31314
00682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3131400682
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1088531506
Short name T1825
Test name
Test status
Simulation time 5570359144 ps
CPU time 52.74 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:52 PM PDT 24
Peak memory 207124 kb
Host smart-016aeb26-a0d4-40ec-9c44-370580d1215c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1088531506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1088531506
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2828381829
Short name T343
Test name
Test status
Simulation time 238567681 ps
CPU time 0.91 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:00 PM PDT 24
Peak memory 206868 kb
Host smart-b98cdd89-e596-4d7c-8152-16a60c2344c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2828381829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2828381829
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1106864030
Short name T1665
Test name
Test status
Simulation time 186178557 ps
CPU time 0.88 seconds
Started Jul 14 07:19:32 PM PDT 24
Finished Jul 14 07:19:49 PM PDT 24
Peak memory 206840 kb
Host smart-93fe8b83-6776-4e74-8b15-1568a0d4b06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068
64030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1106864030
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.3346950662
Short name T1461
Test name
Test status
Simulation time 5227576176 ps
CPU time 133.2 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:22:11 PM PDT 24
Peak memory 207068 kb
Host smart-f7cc4318-e4aa-4d9e-8736-7bcfd7ba152a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33469
50662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.3346950662
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.991281900
Short name T1115
Test name
Test status
Simulation time 7189691323 ps
CPU time 49.91 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:20:43 PM PDT 24
Peak memory 207108 kb
Host smart-eda89f88-789a-4542-94de-28b5dd72bdcd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=991281900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.991281900
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3574962891
Short name T2366
Test name
Test status
Simulation time 153094691 ps
CPU time 0.77 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206888 kb
Host smart-119335ba-32c2-4205-a794-7ad934008a4d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3574962891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3574962891
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3556044815
Short name T852
Test name
Test status
Simulation time 144772606 ps
CPU time 0.76 seconds
Started Jul 14 07:19:39 PM PDT 24
Finished Jul 14 07:20:02 PM PDT 24
Peak memory 206884 kb
Host smart-8c4d1c6e-7d23-41b4-a549-bb04629fe14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35560
44815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3556044815
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1528332026
Short name T129
Test name
Test status
Simulation time 184392708 ps
CPU time 0.93 seconds
Started Jul 14 07:19:33 PM PDT 24
Finished Jul 14 07:19:53 PM PDT 24
Peak memory 206848 kb
Host smart-447b69b2-8ee8-4dbf-a89e-2037933fddaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15283
32026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1528332026
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.453077700
Short name T2464
Test name
Test status
Simulation time 194115503 ps
CPU time 0.83 seconds
Started Jul 14 07:19:35 PM PDT 24
Finished Jul 14 07:19:55 PM PDT 24
Peak memory 206804 kb
Host smart-221819b4-4f3a-48b1-ba7e-91697202020d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45307
7700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.453077700
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.454999504
Short name T1839
Test name
Test status
Simulation time 195037825 ps
CPU time 0.8 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206892 kb
Host smart-643f0fd8-eb57-471e-8e69-fb2fba8624da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45499
9504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.454999504
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.180321772
Short name T2448
Test name
Test status
Simulation time 158525082 ps
CPU time 0.79 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206872 kb
Host smart-affb503f-da2c-41fa-b77e-2d0d4ed68eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18032
1772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.180321772
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3257975565
Short name T170
Test name
Test status
Simulation time 166513958 ps
CPU time 0.8 seconds
Started Jul 14 07:19:37 PM PDT 24
Finished Jul 14 07:20:00 PM PDT 24
Peak memory 206876 kb
Host smart-a4d113ce-25da-4c00-9f46-3d7507504317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32579
75565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3257975565
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3493855679
Short name T2677
Test name
Test status
Simulation time 212180546 ps
CPU time 0.86 seconds
Started Jul 14 07:19:39 PM PDT 24
Finished Jul 14 07:20:02 PM PDT 24
Peak memory 206884 kb
Host smart-2fa507c3-fea0-4610-9c82-7be5cf22ac8b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3493855679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3493855679
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2479867389
Short name T2297
Test name
Test status
Simulation time 146497186 ps
CPU time 0.78 seconds
Started Jul 14 07:19:38 PM PDT 24
Finished Jul 14 07:20:00 PM PDT 24
Peak memory 206872 kb
Host smart-dfb8b4ec-8b1c-4770-8dda-78295c5c71b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
67389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2479867389
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3788019628
Short name T1368
Test name
Test status
Simulation time 55817906 ps
CPU time 0.66 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:03 PM PDT 24
Peak memory 206848 kb
Host smart-33ca010f-05e5-4b4a-a141-32750900e516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37880
19628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3788019628
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.225156383
Short name T1391
Test name
Test status
Simulation time 11687199226 ps
CPU time 27.29 seconds
Started Jul 14 07:19:34 PM PDT 24
Finished Jul 14 07:20:23 PM PDT 24
Peak memory 215392 kb
Host smart-d65388c7-f5b4-4b58-bb9b-2ad3e5086b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22515
6383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.225156383
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2913318534
Short name T481
Test name
Test status
Simulation time 182403976 ps
CPU time 0.89 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206820 kb
Host smart-5c65f14b-5bca-41ba-8796-9abb82594db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29133
18534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2913318534
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1577854785
Short name T2261
Test name
Test status
Simulation time 229676993 ps
CPU time 0.88 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:19:57 PM PDT 24
Peak memory 206848 kb
Host smart-da4a1d6c-6c86-4943-855f-225da1be0c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15778
54785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1577854785
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3170837020
Short name T1710
Test name
Test status
Simulation time 164611556 ps
CPU time 0.78 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206820 kb
Host smart-9558bc60-698e-4117-b813-433eee64358a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31708
37020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3170837020
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3388667248
Short name T888
Test name
Test status
Simulation time 193655015 ps
CPU time 0.81 seconds
Started Jul 14 07:19:36 PM PDT 24
Finished Jul 14 07:19:58 PM PDT 24
Peak memory 207048 kb
Host smart-9e09533d-607b-4b4d-a98a-a91556938f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
67248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3388667248
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2774889034
Short name T2162
Test name
Test status
Simulation time 184303027 ps
CPU time 0.77 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:05 PM PDT 24
Peak memory 206868 kb
Host smart-907772fe-e41b-4e39-acf0-0038d5872fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27748
89034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2774889034
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.590311766
Short name T2165
Test name
Test status
Simulation time 157877119 ps
CPU time 0.82 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206860 kb
Host smart-256f8477-f7bc-4a17-85b1-b1b8ecb11f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59031
1766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.590311766
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3846983488
Short name T2444
Test name
Test status
Simulation time 155079875 ps
CPU time 0.84 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:09 PM PDT 24
Peak memory 206880 kb
Host smart-ea21ddf8-3719-4d16-b9f6-e04648699959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38469
83488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3846983488
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2545394669
Short name T2244
Test name
Test status
Simulation time 234529627 ps
CPU time 1.03 seconds
Started Jul 14 07:19:43 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206840 kb
Host smart-42884912-ed7d-4cf6-8d5f-4624bb305f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25453
94669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2545394669
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3787656849
Short name T1427
Test name
Test status
Simulation time 4608483889 ps
CPU time 44.25 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 207060 kb
Host smart-22d61795-159c-494e-91f7-c7d54bb6bdcd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3787656849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3787656849
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.502277007
Short name T2467
Test name
Test status
Simulation time 205300961 ps
CPU time 0.85 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206856 kb
Host smart-97da7674-5460-4807-aa04-44ef30d30774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50227
7007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.502277007
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1454304329
Short name T959
Test name
Test status
Simulation time 250350493 ps
CPU time 0.88 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206848 kb
Host smart-f40130a6-f838-4b07-b09b-6c239dd5f140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14543
04329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1454304329
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.2969275038
Short name T459
Test name
Test status
Simulation time 381142395 ps
CPU time 1.21 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 207040 kb
Host smart-69bcabfa-6b22-44b8-82d7-82220997e110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29692
75038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.2969275038
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.2740399732
Short name T1143
Test name
Test status
Simulation time 4791341471 ps
CPU time 32.25 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:39 PM PDT 24
Peak memory 207096 kb
Host smart-dd406682-01d3-48af-b56d-d14aa028e5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27403
99732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2740399732
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2634893083
Short name T629
Test name
Test status
Simulation time 32667675 ps
CPU time 0.65 seconds
Started Jul 14 07:19:49 PM PDT 24
Finished Jul 14 07:20:11 PM PDT 24
Peak memory 206932 kb
Host smart-bc353255-000c-4b59-b2b5-ee1643077973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2634893083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2634893083
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1271493350
Short name T2418
Test name
Test status
Simulation time 4254345093 ps
CPU time 4.8 seconds
Started Jul 14 07:19:49 PM PDT 24
Finished Jul 14 07:20:15 PM PDT 24
Peak memory 206904 kb
Host smart-4323e63a-0b34-44c8-a8a7-768beea39f4e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1271493350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1271493350
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1026832731
Short name T671
Test name
Test status
Simulation time 13332678419 ps
CPU time 12.59 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:20:14 PM PDT 24
Peak memory 206956 kb
Host smart-53b56b96-2e42-47db-bca9-9cb6e0359214
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1026832731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1026832731
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3663204006
Short name T2548
Test name
Test status
Simulation time 23493136050 ps
CPU time 22.95 seconds
Started Jul 14 07:19:40 PM PDT 24
Finished Jul 14 07:20:24 PM PDT 24
Peak memory 207044 kb
Host smart-8e8c5823-04cf-404c-bd0a-f058cd3edc3a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3663204006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3663204006
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.988015833
Short name T1827
Test name
Test status
Simulation time 182560107 ps
CPU time 1 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:20:03 PM PDT 24
Peak memory 206876 kb
Host smart-34e7c81b-a3a4-4541-b664-6b90c4ec02e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98801
5833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.988015833
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.327801318
Short name T1764
Test name
Test status
Simulation time 149973821 ps
CPU time 0.79 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206876 kb
Host smart-5982db5b-61a4-48bf-a168-c50112aff3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32780
1318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.327801318
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1738116470
Short name T2239
Test name
Test status
Simulation time 484645472 ps
CPU time 1.45 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206824 kb
Host smart-fca5f1a3-6322-4e6b-a694-d87a0ef1dc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17381
16470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1738116470
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2336653835
Short name T1845
Test name
Test status
Simulation time 988199766 ps
CPU time 2.12 seconds
Started Jul 14 07:19:43 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 207016 kb
Host smart-1bae8593-9ced-4391-876d-f88baf25aab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23366
53835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2336653835
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.706654288
Short name T2137
Test name
Test status
Simulation time 5667966364 ps
CPU time 11.13 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:18 PM PDT 24
Peak memory 207048 kb
Host smart-9f6df336-f084-4da2-bb99-d4afa7c25ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70665
4288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.706654288
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.426397106
Short name T1165
Test name
Test status
Simulation time 409767775 ps
CPU time 1.42 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206828 kb
Host smart-d391c31a-5a84-4d40-9c2e-46520923e35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
7106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.426397106
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.571042777
Short name T2208
Test name
Test status
Simulation time 137187799 ps
CPU time 0.74 seconds
Started Jul 14 07:19:46 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206880 kb
Host smart-51815d1d-7d3b-4b92-a63e-afcdbdee3e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57104
2777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.571042777
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1005978793
Short name T916
Test name
Test status
Simulation time 67780122 ps
CPU time 0.75 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206852 kb
Host smart-a98fde00-1fc8-46d8-b2fc-986e18c228b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10059
78793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1005978793
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1359251554
Short name T2392
Test name
Test status
Simulation time 847094367 ps
CPU time 2.12 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 207044 kb
Host smart-2dca6a3a-8b38-4d40-a2b7-2f9f02e3b0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13592
51554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1359251554
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2725443587
Short name T2099
Test name
Test status
Simulation time 273143650 ps
CPU time 1.64 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 207004 kb
Host smart-9ecd3354-82db-4f95-a2f2-ea540b4a3da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27254
43587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2725443587
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3224781436
Short name T1173
Test name
Test status
Simulation time 185270445 ps
CPU time 0.89 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 206856 kb
Host smart-822ae2ab-3625-453e-b5fd-5fb8ac18298e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32247
81436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3224781436
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.643436166
Short name T497
Test name
Test status
Simulation time 153453601 ps
CPU time 0.77 seconds
Started Jul 14 07:19:46 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206852 kb
Host smart-7ed4c267-e7bc-43b1-b668-553ef3b6474b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64343
6166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.643436166
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2336847787
Short name T1751
Test name
Test status
Simulation time 220438387 ps
CPU time 0.94 seconds
Started Jul 14 07:19:40 PM PDT 24
Finished Jul 14 07:20:02 PM PDT 24
Peak memory 206892 kb
Host smart-ff4cdec2-36dd-4272-aa3c-02934b0eec97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23368
47787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2336847787
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3646553967
Short name T673
Test name
Test status
Simulation time 5004703620 ps
CPU time 140.27 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:22:25 PM PDT 24
Peak memory 207064 kb
Host smart-d993d463-7968-4a13-a887-c1811b0476b6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3646553967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3646553967
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.437667220
Short name T1683
Test name
Test status
Simulation time 8156701235 ps
CPU time 66.82 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 207136 kb
Host smart-266e6476-2e47-4f9e-a506-afefaddde57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43766
7220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.437667220
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2094904964
Short name T2581
Test name
Test status
Simulation time 192675429 ps
CPU time 0.89 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:20:03 PM PDT 24
Peak memory 206868 kb
Host smart-a83b3c40-4679-4e52-a6cd-41579d3e5ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20949
04964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2094904964
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1427313527
Short name T885
Test name
Test status
Simulation time 23308562038 ps
CPU time 21.08 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:28 PM PDT 24
Peak memory 206932 kb
Host smart-10daa01d-1e28-4e18-8df7-d6c2035c56ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14273
13527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1427313527
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.740272614
Short name T468
Test name
Test status
Simulation time 3310626912 ps
CPU time 4.33 seconds
Started Jul 14 07:19:44 PM PDT 24
Finished Jul 14 07:20:11 PM PDT 24
Peak memory 206956 kb
Host smart-d6cc1662-d627-4287-91b1-bacf63df43a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74027
2614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.740272614
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.4270993416
Short name T808
Test name
Test status
Simulation time 10355681326 ps
CPU time 270.98 seconds
Started Jul 14 07:19:41 PM PDT 24
Finished Jul 14 07:24:33 PM PDT 24
Peak memory 207128 kb
Host smart-69b52dbd-9516-4b1b-aff9-3e19fd90c593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42709
93416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.4270993416
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2253782544
Short name T2343
Test name
Test status
Simulation time 5123175345 ps
CPU time 134.67 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:22:22 PM PDT 24
Peak memory 207056 kb
Host smart-3b1739ff-12e7-4583-922c-5ba31e4a9171
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2253782544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2253782544
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.978203123
Short name T1585
Test name
Test status
Simulation time 289825313 ps
CPU time 0.95 seconds
Started Jul 14 07:19:48 PM PDT 24
Finished Jul 14 07:20:09 PM PDT 24
Peak memory 206856 kb
Host smart-42d6784f-9500-4506-9208-3ce7730018bc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=978203123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.978203123
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2520076783
Short name T1601
Test name
Test status
Simulation time 201920946 ps
CPU time 0.88 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206844 kb
Host smart-0b3154c9-501e-4f87-9600-436fe42fce68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200
76783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2520076783
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.2293600051
Short name T986
Test name
Test status
Simulation time 7491534601 ps
CPU time 211.45 seconds
Started Jul 14 07:19:40 PM PDT 24
Finished Jul 14 07:23:32 PM PDT 24
Peak memory 207088 kb
Host smart-e2a91ae1-cad4-4af9-918c-0f7b75d65ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
00051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.2293600051
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3847237021
Short name T1336
Test name
Test status
Simulation time 2727036468 ps
CPU time 73.61 seconds
Started Jul 14 07:19:40 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 207044 kb
Host smart-2e8f7c4b-a2ff-4dda-9dbc-02a36e3fe788
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3847237021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3847237021
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3340906345
Short name T1172
Test name
Test status
Simulation time 178337699 ps
CPU time 0.79 seconds
Started Jul 14 07:19:42 PM PDT 24
Finished Jul 14 07:20:04 PM PDT 24
Peak memory 206856 kb
Host smart-1cb8a631-c3c3-4f43-a2f7-749b8b2581ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3340906345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3340906345
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.780258829
Short name T2249
Test name
Test status
Simulation time 171429777 ps
CPU time 0.81 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206844 kb
Host smart-6958ad75-c788-4b15-8f29-7809dc592d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78025
8829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.780258829
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1166518342
Short name T124
Test name
Test status
Simulation time 197600067 ps
CPU time 0.88 seconds
Started Jul 14 07:19:51 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206868 kb
Host smart-fd4f3748-f884-4fc1-a82b-4235f1e57349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11665
18342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1166518342
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1473638427
Short name T471
Test name
Test status
Simulation time 253810426 ps
CPU time 0.88 seconds
Started Jul 14 07:19:51 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206856 kb
Host smart-335464f6-83bc-41f2-bd4a-83276c76503a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
38427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1473638427
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.476407787
Short name T420
Test name
Test status
Simulation time 183247341 ps
CPU time 0.78 seconds
Started Jul 14 07:19:47 PM PDT 24
Finished Jul 14 07:20:09 PM PDT 24
Peak memory 206892 kb
Host smart-0e75a518-43bf-47bd-9abc-91efe144368f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47640
7787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.476407787
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.811363103
Short name T1512
Test name
Test status
Simulation time 217925899 ps
CPU time 0.89 seconds
Started Jul 14 07:19:54 PM PDT 24
Finished Jul 14 07:20:15 PM PDT 24
Peak memory 206892 kb
Host smart-010cab28-c2b7-4e38-904e-66faaae7c3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81136
3103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.811363103
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.226878046
Short name T1536
Test name
Test status
Simulation time 162682943 ps
CPU time 0.8 seconds
Started Jul 14 07:19:52 PM PDT 24
Finished Jul 14 07:20:14 PM PDT 24
Peak memory 206812 kb
Host smart-38cac2f2-29bb-45c2-a87f-d4288e1ab2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22687
8046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.226878046
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3126941967
Short name T1758
Test name
Test status
Simulation time 224529141 ps
CPU time 0.93 seconds
Started Jul 14 07:19:49 PM PDT 24
Finished Jul 14 07:20:11 PM PDT 24
Peak memory 206848 kb
Host smart-83b36a6f-4b69-41fa-bded-340cc799a551
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3126941967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3126941967
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.780450115
Short name T985
Test name
Test status
Simulation time 228122879 ps
CPU time 0.81 seconds
Started Jul 14 07:19:49 PM PDT 24
Finished Jul 14 07:20:11 PM PDT 24
Peak memory 206872 kb
Host smart-23de09cc-9287-4eed-8200-e83e21e6ce49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78045
0115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.780450115
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.4103217858
Short name T2442
Test name
Test status
Simulation time 43376143 ps
CPU time 0.68 seconds
Started Jul 14 07:19:51 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206820 kb
Host smart-f0b1e0a6-5f5c-468a-bb82-e03f79b9edf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41032
17858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.4103217858
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3120499625
Short name T136
Test name
Test status
Simulation time 9426876656 ps
CPU time 21.83 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:53 PM PDT 24
Peak memory 207152 kb
Host smart-bfc02484-3279-4ca7-8d4c-47038968172e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31204
99625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3120499625
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2628410564
Short name T1617
Test name
Test status
Simulation time 213509231 ps
CPU time 0.93 seconds
Started Jul 14 07:19:50 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206812 kb
Host smart-ac143b6d-bce5-4f97-a8a6-f6a65fff3120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26284
10564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2628410564
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1432559821
Short name T855
Test name
Test status
Simulation time 235360651 ps
CPU time 0.86 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206888 kb
Host smart-d49e9132-e1bb-45eb-aebb-40ea5bfe70da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14325
59821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1432559821
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3527448292
Short name T759
Test name
Test status
Simulation time 227510539 ps
CPU time 0.87 seconds
Started Jul 14 07:19:46 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206856 kb
Host smart-b5450879-8e78-4c89-a23e-0c9d36a827eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35274
48292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3527448292
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.781638514
Short name T2540
Test name
Test status
Simulation time 159893037 ps
CPU time 0.82 seconds
Started Jul 14 07:19:56 PM PDT 24
Finished Jul 14 07:20:18 PM PDT 24
Peak memory 206836 kb
Host smart-82f68115-66c8-494e-95cb-4962420ec1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78163
8514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.781638514
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1848036308
Short name T2183
Test name
Test status
Simulation time 190886201 ps
CPU time 0.86 seconds
Started Jul 14 07:19:51 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206840 kb
Host smart-fe3a2c76-b5f1-41fa-a6b2-d4dc5f24c0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18480
36308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1848036308
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.178680410
Short name T584
Test name
Test status
Simulation time 153960212 ps
CPU time 0.76 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:15 PM PDT 24
Peak memory 206856 kb
Host smart-dd26acd8-fbe3-4f9a-a3cc-b0219dac446f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17868
0410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.178680410
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1428120588
Short name T883
Test name
Test status
Simulation time 152706120 ps
CPU time 0.78 seconds
Started Jul 14 07:19:46 PM PDT 24
Finished Jul 14 07:20:08 PM PDT 24
Peak memory 206856 kb
Host smart-c1a3f158-4198-4760-ad3a-05cb43897d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14281
20588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1428120588
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1614129258
Short name T1279
Test name
Test status
Simulation time 231154167 ps
CPU time 0.95 seconds
Started Jul 14 07:19:50 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206868 kb
Host smart-3f20df5c-84f3-4b9c-860d-130476a0cebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141
29258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1614129258
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3449936552
Short name T766
Test name
Test status
Simulation time 4373514776 ps
CPU time 122.4 seconds
Started Jul 14 07:19:50 PM PDT 24
Finished Jul 14 07:22:14 PM PDT 24
Peak memory 207052 kb
Host smart-cd833ddb-54f0-4dc2-a5d4-f772440edfc0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3449936552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3449936552
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3275953643
Short name T918
Test name
Test status
Simulation time 189558222 ps
CPU time 0.79 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:15 PM PDT 24
Peak memory 206860 kb
Host smart-b69f01b8-25c5-4ae7-bbfb-db32ed04182a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32759
53643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3275953643
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.4077847233
Short name T2246
Test name
Test status
Simulation time 158703576 ps
CPU time 0.81 seconds
Started Jul 14 07:19:50 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206804 kb
Host smart-681b0370-468c-4385-b37c-82386d8a3318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40778
47233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.4077847233
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2062709757
Short name T2179
Test name
Test status
Simulation time 1205407041 ps
CPU time 2.4 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 207060 kb
Host smart-b1c4a5e2-c810-4d42-b6e4-a76d060cae46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20627
09757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2062709757
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1336729595
Short name T1015
Test name
Test status
Simulation time 4208130081 ps
CPU time 28.68 seconds
Started Jul 14 07:19:48 PM PDT 24
Finished Jul 14 07:20:38 PM PDT 24
Peak memory 207080 kb
Host smart-e93d34d3-b115-4c79-a097-deef0c4c2af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13367
29595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1336729595
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1241680639
Short name T1646
Test name
Test status
Simulation time 34217061 ps
CPU time 0.73 seconds
Started Jul 14 07:19:59 PM PDT 24
Finished Jul 14 07:20:20 PM PDT 24
Peak memory 206892 kb
Host smart-c2954a2d-b5ec-466a-a147-6d710f937f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1241680639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1241680639
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1983092608
Short name T1914
Test name
Test status
Simulation time 3358345006 ps
CPU time 3.77 seconds
Started Jul 14 07:19:45 PM PDT 24
Finished Jul 14 07:20:10 PM PDT 24
Peak memory 206972 kb
Host smart-ed45ec4e-5ee9-4a0f-a564-f10d3b4d9073
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1983092608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1983092608
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1425779447
Short name T2180
Test name
Test status
Simulation time 13311301503 ps
CPU time 12.63 seconds
Started Jul 14 07:19:47 PM PDT 24
Finished Jul 14 07:20:21 PM PDT 24
Peak memory 207060 kb
Host smart-58ce70e2-f9c0-4bfc-9583-90aedf9ba5f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1425779447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1425779447
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2607532164
Short name T563
Test name
Test status
Simulation time 23329443907 ps
CPU time 24.17 seconds
Started Jul 14 07:20:02 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206916 kb
Host smart-d8cb2c99-ed55-441e-8f4b-977279c00d9d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2607532164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.2607532164
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.870303026
Short name T571
Test name
Test status
Simulation time 154132937 ps
CPU time 0.8 seconds
Started Jul 14 07:19:55 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 206864 kb
Host smart-831e23bb-5835-4406-a838-c77ca929247e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87030
3026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.870303026
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1503227755
Short name T1397
Test name
Test status
Simulation time 148910593 ps
CPU time 0.79 seconds
Started Jul 14 07:19:56 PM PDT 24
Finished Jul 14 07:20:18 PM PDT 24
Peak memory 206868 kb
Host smart-57488660-e6dd-43f8-8244-94becd35b09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15032
27755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1503227755
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2895201472
Short name T2535
Test name
Test status
Simulation time 326233862 ps
CPU time 1.34 seconds
Started Jul 14 07:19:52 PM PDT 24
Finished Jul 14 07:20:14 PM PDT 24
Peak memory 206864 kb
Host smart-b20b793e-9d36-4f92-a786-3ab4389204a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28952
01472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2895201472
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.494271522
Short name T2102
Test name
Test status
Simulation time 1203323389 ps
CPU time 2.52 seconds
Started Jul 14 07:20:00 PM PDT 24
Finished Jul 14 07:20:27 PM PDT 24
Peak memory 207016 kb
Host smart-2d31ba41-6c94-4e78-b53d-e287767ed317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49427
1522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.494271522
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.2073292271
Short name T2254
Test name
Test status
Simulation time 6850432840 ps
CPU time 12.43 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:41 PM PDT 24
Peak memory 207152 kb
Host smart-7b74c5c7-e662-472c-b9f3-1da493454b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20732
92271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.2073292271
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.184253459
Short name T1382
Test name
Test status
Simulation time 314118628 ps
CPU time 1.11 seconds
Started Jul 14 07:19:50 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206888 kb
Host smart-c376b2cf-8cb6-4c4f-a1a4-eef8c15a51a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18425
3459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.184253459
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1940901571
Short name T1150
Test name
Test status
Simulation time 133353145 ps
CPU time 0.74 seconds
Started Jul 14 07:19:51 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206880 kb
Host smart-1b20afdd-c833-42ed-afa9-87fb0f04a22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409
01571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1940901571
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.4234690927
Short name T2155
Test name
Test status
Simulation time 41929857 ps
CPU time 0.64 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:32 PM PDT 24
Peak memory 206852 kb
Host smart-4d163777-de91-42b7-9679-870f76c719ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42346
90927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.4234690927
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.999486717
Short name T1616
Test name
Test status
Simulation time 932519348 ps
CPU time 2.4 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 207004 kb
Host smart-9e35a1a1-ab30-4661-a512-d62dbe558afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99948
6717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.999486717
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.570487954
Short name T1864
Test name
Test status
Simulation time 167843218 ps
CPU time 1.72 seconds
Started Jul 14 07:19:50 PM PDT 24
Finished Jul 14 07:20:13 PM PDT 24
Peak memory 207040 kb
Host smart-b1d33131-b3cc-444c-a1a8-98995e51a0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57048
7954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.570487954
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2232860731
Short name T2341
Test name
Test status
Simulation time 160430348 ps
CPU time 0.78 seconds
Started Jul 14 07:20:00 PM PDT 24
Finished Jul 14 07:20:21 PM PDT 24
Peak memory 206808 kb
Host smart-787b6f03-7b4f-4365-a07d-54a9d996f327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22328
60731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2232860731
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.432821415
Short name T2360
Test name
Test status
Simulation time 156665887 ps
CPU time 0.76 seconds
Started Jul 14 07:20:05 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206876 kb
Host smart-adb33ee4-7c6d-479b-9d11-b28c2a870569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43282
1415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.432821415
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1348658832
Short name T1047
Test name
Test status
Simulation time 163696756 ps
CPU time 0.76 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206868 kb
Host smart-0e6493c8-5a86-45d3-b244-15df643d2932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13486
58832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1348658832
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3404866683
Short name T534
Test name
Test status
Simulation time 255815060 ps
CPU time 0.94 seconds
Started Jul 14 07:20:02 PM PDT 24
Finished Jul 14 07:20:28 PM PDT 24
Peak memory 206852 kb
Host smart-db620a3d-c34f-43f6-abce-ceb19d0940f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34048
66683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3404866683
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.3043992363
Short name T2228
Test name
Test status
Simulation time 23322512410 ps
CPU time 26.72 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:21:02 PM PDT 24
Peak memory 206932 kb
Host smart-4e71e770-0f43-4869-936c-2376265c0163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30439
92363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.3043992363
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.4681078
Short name T2307
Test name
Test status
Simulation time 3303266459 ps
CPU time 4.81 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:19 PM PDT 24
Peak memory 206932 kb
Host smart-89289e24-6862-4300-ad4b-631bdc04b8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46810
78 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.4681078
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2696340344
Short name T1171
Test name
Test status
Simulation time 9815269447 ps
CPU time 89.77 seconds
Started Jul 14 07:19:54 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 207100 kb
Host smart-22aba87f-7c6f-4d43-8d60-59587664e2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26963
40344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2696340344
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.4239812865
Short name T1940
Test name
Test status
Simulation time 5766933806 ps
CPU time 53.2 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:21:26 PM PDT 24
Peak memory 207068 kb
Host smart-5063c793-ede5-4494-ad20-f2fe9f4d7c81
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4239812865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.4239812865
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2450911114
Short name T845
Test name
Test status
Simulation time 263571842 ps
CPU time 0.94 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206860 kb
Host smart-0f3a3d67-a031-482c-87dd-0096dff9bb37
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2450911114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2450911114
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1164839163
Short name T2317
Test name
Test status
Simulation time 258330233 ps
CPU time 0.94 seconds
Started Jul 14 07:20:11 PM PDT 24
Finished Jul 14 07:20:38 PM PDT 24
Peak memory 206868 kb
Host smart-a81ff859-7c42-442f-aa0a-d09c1eb4e65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11648
39163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1164839163
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.1945684174
Short name T1265
Test name
Test status
Simulation time 4012761200 ps
CPU time 37.83 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:21:06 PM PDT 24
Peak memory 207084 kb
Host smart-3166feae-f809-41b6-af7e-cb9a83e3dd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19456
84174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.1945684174
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.297729941
Short name T2377
Test name
Test status
Simulation time 5220600425 ps
CPU time 47 seconds
Started Jul 14 07:19:57 PM PDT 24
Finished Jul 14 07:21:06 PM PDT 24
Peak memory 207136 kb
Host smart-831a60a0-dce7-4856-88e0-6b8b25a3e692
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=297729941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.297729941
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3930116870
Short name T2164
Test name
Test status
Simulation time 150634228 ps
CPU time 0.77 seconds
Started Jul 14 07:20:08 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 206888 kb
Host smart-6d84d632-ca1e-49d0-a04b-c1641ecc6de9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3930116870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3930116870
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2742512574
Short name T1663
Test name
Test status
Simulation time 158966663 ps
CPU time 0.77 seconds
Started Jul 14 07:19:51 PM PDT 24
Finished Jul 14 07:20:12 PM PDT 24
Peak memory 206828 kb
Host smart-a289e003-bd4e-4616-8a20-2f318c7ef1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27425
12574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2742512574
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2192946572
Short name T117
Test name
Test status
Simulation time 207820882 ps
CPU time 0.86 seconds
Started Jul 14 07:20:00 PM PDT 24
Finished Jul 14 07:20:21 PM PDT 24
Peak memory 206884 kb
Host smart-3d515333-9d69-4927-a72f-31f6f4846b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21929
46572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2192946572
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.607364150
Short name T1749
Test name
Test status
Simulation time 169735157 ps
CPU time 0.79 seconds
Started Jul 14 07:19:55 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 206876 kb
Host smart-cd773819-46eb-4bad-9e76-a7faa0ed015a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60736
4150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.607364150
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2716182714
Short name T2463
Test name
Test status
Simulation time 153914936 ps
CPU time 0.77 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206880 kb
Host smart-6d854698-4766-4bf2-95f8-390c0bb74b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27161
82714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2716182714
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2583857485
Short name T2691
Test name
Test status
Simulation time 152804606 ps
CPU time 0.82 seconds
Started Jul 14 07:19:52 PM PDT 24
Finished Jul 14 07:20:13 PM PDT 24
Peak memory 206824 kb
Host smart-f01fe7f1-5095-417c-8996-a0c0d9c16cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25838
57485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2583857485
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3208255286
Short name T178
Test name
Test status
Simulation time 171358934 ps
CPU time 0.76 seconds
Started Jul 14 07:19:56 PM PDT 24
Finished Jul 14 07:20:18 PM PDT 24
Peak memory 206864 kb
Host smart-2ab3bdb9-d2eb-484a-b38e-482ad35afddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32082
55286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3208255286
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2913000017
Short name T362
Test name
Test status
Simulation time 225530792 ps
CPU time 0.99 seconds
Started Jul 14 07:20:11 PM PDT 24
Finished Jul 14 07:20:38 PM PDT 24
Peak memory 206880 kb
Host smart-84b04896-1020-4e57-98fa-283f09cf2185
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2913000017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2913000017
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1183247954
Short name T1105
Test name
Test status
Simulation time 150441876 ps
CPU time 0.75 seconds
Started Jul 14 07:19:52 PM PDT 24
Finished Jul 14 07:20:13 PM PDT 24
Peak memory 206864 kb
Host smart-bd031869-1024-4e1a-bf21-21dbecd3d700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11832
47954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1183247954
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3962950984
Short name T2422
Test name
Test status
Simulation time 57576682 ps
CPU time 0.68 seconds
Started Jul 14 07:20:05 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206864 kb
Host smart-8dd54090-6378-4f12-af65-941a78ace08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39629
50984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3962950984
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1300298233
Short name T269
Test name
Test status
Simulation time 6018193277 ps
CPU time 12.26 seconds
Started Jul 14 07:19:55 PM PDT 24
Finished Jul 14 07:20:29 PM PDT 24
Peak memory 207100 kb
Host smart-e34d4bef-2861-40f4-9b08-15fa38cbb62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13002
98233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1300298233
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1875254143
Short name T2375
Test name
Test status
Simulation time 266202809 ps
CPU time 0.92 seconds
Started Jul 14 07:19:52 PM PDT 24
Finished Jul 14 07:20:13 PM PDT 24
Peak memory 206872 kb
Host smart-4abcc611-53e0-4ad4-b756-7353c4825258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18752
54143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1875254143
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2250417187
Short name T1530
Test name
Test status
Simulation time 190191547 ps
CPU time 0.92 seconds
Started Jul 14 07:19:54 PM PDT 24
Finished Jul 14 07:20:15 PM PDT 24
Peak memory 206888 kb
Host smart-7d9e7ef5-70a6-4112-8b8f-555e6ef76763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504
17187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2250417187
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1955055886
Short name T858
Test name
Test status
Simulation time 182275288 ps
CPU time 0.87 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 206876 kb
Host smart-1f839ad3-89ea-495c-a252-98647bf10d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19550
55886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1955055886
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3451730657
Short name T1386
Test name
Test status
Simulation time 163345814 ps
CPU time 0.77 seconds
Started Jul 14 07:19:57 PM PDT 24
Finished Jul 14 07:20:20 PM PDT 24
Peak memory 206884 kb
Host smart-e536ce3c-80e5-4180-b387-f49883bfc8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34517
30657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3451730657
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.1678316430
Short name T615
Test name
Test status
Simulation time 195883007 ps
CPU time 0.84 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206844 kb
Host smart-efa371f0-72e3-4359-ac69-9d7240dbf997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16783
16430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1678316430
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.99292325
Short name T2017
Test name
Test status
Simulation time 152993063 ps
CPU time 0.82 seconds
Started Jul 14 07:20:00 PM PDT 24
Finished Jul 14 07:20:26 PM PDT 24
Peak memory 206860 kb
Host smart-012c697f-1836-485c-812a-4c9a61c4a984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99292
325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.99292325
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2259257922
Short name T1558
Test name
Test status
Simulation time 152802174 ps
CPU time 0.77 seconds
Started Jul 14 07:20:02 PM PDT 24
Finished Jul 14 07:20:28 PM PDT 24
Peak memory 206856 kb
Host smart-c9301b99-f0c6-454b-9070-568ebbfb5e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22592
57922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2259257922
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3725551189
Short name T445
Test name
Test status
Simulation time 241603454 ps
CPU time 0.95 seconds
Started Jul 14 07:19:55 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 206860 kb
Host smart-915bef5b-e42b-4206-b92c-4cf7d58a5676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37255
51189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3725551189
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3531044507
Short name T760
Test name
Test status
Simulation time 3642592828 ps
CPU time 26.45 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:41 PM PDT 24
Peak memory 207028 kb
Host smart-04098da2-c2fe-4945-bcbd-934ef5392297
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3531044507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3531044507
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3985776492
Short name T744
Test name
Test status
Simulation time 178424945 ps
CPU time 0.78 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 206876 kb
Host smart-c1ba301a-2af0-433d-8c93-817482e005c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39857
76492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3985776492
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.757102803
Short name T95
Test name
Test status
Simulation time 151105418 ps
CPU time 0.74 seconds
Started Jul 14 07:20:08 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 206848 kb
Host smart-fd3eef0e-8dc6-4209-acb8-2593b46d9bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75710
2803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.757102803
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.4007673699
Short name T1381
Test name
Test status
Simulation time 263705436 ps
CPU time 0.96 seconds
Started Jul 14 07:20:00 PM PDT 24
Finished Jul 14 07:20:26 PM PDT 24
Peak memory 206872 kb
Host smart-0c39cf81-8a2d-4792-b5f0-c8581a40e9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40076
73699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.4007673699
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3290732193
Short name T2502
Test name
Test status
Simulation time 2917406570 ps
CPU time 25.83 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 207152 kb
Host smart-a6c40bf5-1924-497e-b4ac-93b863aee39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32907
32193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3290732193
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.423247109
Short name T933
Test name
Test status
Simulation time 64832709 ps
CPU time 0.7 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:20:29 PM PDT 24
Peak memory 206908 kb
Host smart-c56800d1-e445-4f85-a107-e6faf026c090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=423247109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.423247109
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3295869497
Short name T8
Test name
Test status
Simulation time 3762785586 ps
CPU time 4.48 seconds
Started Jul 14 07:19:54 PM PDT 24
Finished Jul 14 07:20:19 PM PDT 24
Peak memory 206940 kb
Host smart-5334dbf0-e48a-4801-9f90-b600474cef6f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3295869497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3295869497
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.4247575093
Short name T833
Test name
Test status
Simulation time 13343058634 ps
CPU time 13.73 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:20:52 PM PDT 24
Peak memory 207076 kb
Host smart-c253436b-b2d4-4cb0-b990-23a3258f7fc2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4247575093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.4247575093
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.143814607
Short name T1970
Test name
Test status
Simulation time 23461091967 ps
CPU time 22.35 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:54 PM PDT 24
Peak memory 207144 kb
Host smart-b602e9c5-d4d5-4928-96de-3d67f36bbe3a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=143814607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.143814607
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1084635187
Short name T652
Test name
Test status
Simulation time 194146583 ps
CPU time 0.83 seconds
Started Jul 14 07:19:55 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 206840 kb
Host smart-677ea5fc-be2e-48de-bdaa-902a57e5b80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10846
35187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1084635187
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.735392960
Short name T59
Test name
Test status
Simulation time 185572393 ps
CPU time 0.82 seconds
Started Jul 14 07:20:11 PM PDT 24
Finished Jul 14 07:20:37 PM PDT 24
Peak memory 206888 kb
Host smart-a3049e79-3b4e-4806-8808-51e0d4ab4c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73539
2960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.735392960
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.393385465
Short name T1992
Test name
Test status
Simulation time 533767660 ps
CPU time 1.56 seconds
Started Jul 14 07:19:55 PM PDT 24
Finished Jul 14 07:20:18 PM PDT 24
Peak memory 206812 kb
Host smart-8dc3f8d4-1567-4974-887c-2dfa59e5dd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39338
5465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.393385465
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1842849146
Short name T2209
Test name
Test status
Simulation time 385169535 ps
CPU time 1.14 seconds
Started Jul 14 07:19:57 PM PDT 24
Finished Jul 14 07:20:19 PM PDT 24
Peak memory 206872 kb
Host smart-f2ea3eec-7751-4695-b06c-677b3df8b394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18428
49146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1842849146
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1270065222
Short name T171
Test name
Test status
Simulation time 12237232184 ps
CPU time 21.95 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:20:57 PM PDT 24
Peak memory 207136 kb
Host smart-5d895820-8be4-495a-a462-044502bcda5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12700
65222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1270065222
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3070988004
Short name T624
Test name
Test status
Simulation time 476940498 ps
CPU time 1.3 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:15 PM PDT 24
Peak memory 206828 kb
Host smart-1bbcf114-bde5-4c6f-908e-3c8ce74d72e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30709
88004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3070988004
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1203466556
Short name T412
Test name
Test status
Simulation time 182886563 ps
CPU time 0.84 seconds
Started Jul 14 07:19:52 PM PDT 24
Finished Jul 14 07:20:13 PM PDT 24
Peak memory 206892 kb
Host smart-584c3cbc-81d5-43d6-b130-809b1c158588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12034
66556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1203466556
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.889972438
Short name T1338
Test name
Test status
Simulation time 108558545 ps
CPU time 0.75 seconds
Started Jul 14 07:20:00 PM PDT 24
Finished Jul 14 07:20:26 PM PDT 24
Peak memory 206860 kb
Host smart-de61ed72-d257-4936-a392-ae363b60dc77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88997
2438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.889972438
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.4279712855
Short name T2390
Test name
Test status
Simulation time 842521576 ps
CPU time 2.25 seconds
Started Jul 14 07:19:54 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 207072 kb
Host smart-cc5b1a5f-bfb0-4f95-8d25-dd02788a7337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42797
12855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.4279712855
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2480688946
Short name T2741
Test name
Test status
Simulation time 192626944 ps
CPU time 1.75 seconds
Started Jul 14 07:19:55 PM PDT 24
Finished Jul 14 07:20:18 PM PDT 24
Peak memory 207080 kb
Host smart-59252089-7c2e-41f5-9873-632f54ecd093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24806
88946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2480688946
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.4066822044
Short name T1308
Test name
Test status
Simulation time 217365295 ps
CPU time 0.91 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:33 PM PDT 24
Peak memory 206888 kb
Host smart-53cd507e-43ad-42d2-9a34-0b48e06b72a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40668
22044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.4066822044
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1305233243
Short name T1480
Test name
Test status
Simulation time 138455754 ps
CPU time 0.77 seconds
Started Jul 14 07:19:57 PM PDT 24
Finished Jul 14 07:20:20 PM PDT 24
Peak memory 206868 kb
Host smart-707a4d6a-c1e1-462b-ad41-790cd3d65f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13052
33243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1305233243
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.536766725
Short name T1022
Test name
Test status
Simulation time 208247323 ps
CPU time 0.88 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:15 PM PDT 24
Peak memory 206844 kb
Host smart-5d905a09-35bd-4104-8849-535bb14c66f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53676
6725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.536766725
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.1716154016
Short name T1571
Test name
Test status
Simulation time 9596964350 ps
CPU time 89.15 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:22:11 PM PDT 24
Peak memory 207108 kb
Host smart-89736b22-e445-43e9-8076-2fec6d0de1e3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1716154016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1716154016
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2774356029
Short name T1771
Test name
Test status
Simulation time 7665354706 ps
CPU time 28.89 seconds
Started Jul 14 07:19:56 PM PDT 24
Finished Jul 14 07:20:46 PM PDT 24
Peak memory 207112 kb
Host smart-f7ac56bd-d648-4f2e-9fe7-fb74378400ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27743
56029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2774356029
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2823609502
Short name T1106
Test name
Test status
Simulation time 212956068 ps
CPU time 0.82 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 206864 kb
Host smart-f0070ad1-ab8d-4889-82cd-dc280c51a993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28236
09502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2823609502
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3155730364
Short name T2010
Test name
Test status
Simulation time 23324685324 ps
CPU time 22.73 seconds
Started Jul 14 07:19:54 PM PDT 24
Finished Jul 14 07:20:37 PM PDT 24
Peak memory 206900 kb
Host smart-82ae78fb-04bd-4d81-bcae-99a6bb9d5c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31557
30364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3155730364
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.942871278
Short name T319
Test name
Test status
Simulation time 3301264532 ps
CPU time 3.91 seconds
Started Jul 14 07:19:53 PM PDT 24
Finished Jul 14 07:20:18 PM PDT 24
Peak memory 206904 kb
Host smart-e50c4f85-f5f4-4074-88c6-67c8829b013b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94287
1278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.942871278
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.920193763
Short name T801
Test name
Test status
Simulation time 5804395782 ps
CPU time 161.32 seconds
Started Jul 14 07:20:14 PM PDT 24
Finished Jul 14 07:23:22 PM PDT 24
Peak memory 207172 kb
Host smart-20a28b33-e848-44bd-bc6e-931417ac8a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92019
3763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.920193763
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3396429969
Short name T2385
Test name
Test status
Simulation time 4562221388 ps
CPU time 30.75 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:59 PM PDT 24
Peak memory 207060 kb
Host smart-1683ddde-7e7f-436a-8c09-b7d30ccba8c7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3396429969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3396429969
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1342153075
Short name T1962
Test name
Test status
Simulation time 280654580 ps
CPU time 0.91 seconds
Started Jul 14 07:19:55 PM PDT 24
Finished Jul 14 07:20:17 PM PDT 24
Peak memory 206860 kb
Host smart-1fe81bd2-e5cf-4ee7-a83f-c0db94caf01a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1342153075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1342153075
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3198066304
Short name T780
Test name
Test status
Simulation time 265133908 ps
CPU time 0.96 seconds
Started Jul 14 07:20:14 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206848 kb
Host smart-7e009987-53b8-46c1-8591-f981a633afad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31980
66304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3198066304
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1327685541
Short name T2319
Test name
Test status
Simulation time 5508914318 ps
CPU time 40.99 seconds
Started Jul 14 07:19:59 PM PDT 24
Finished Jul 14 07:21:00 PM PDT 24
Peak memory 207020 kb
Host smart-20cd7bfe-2f47-4ea9-88aa-720275a14333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13276
85541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1327685541
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3565308194
Short name T2491
Test name
Test status
Simulation time 4735995000 ps
CPU time 127.58 seconds
Started Jul 14 07:20:09 PM PDT 24
Finished Jul 14 07:22:43 PM PDT 24
Peak memory 207116 kb
Host smart-2311f84a-550a-4d2b-a2fd-2e68a539f990
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3565308194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3565308194
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3647643301
Short name T366
Test name
Test status
Simulation time 155220071 ps
CPU time 0.8 seconds
Started Jul 14 07:20:01 PM PDT 24
Finished Jul 14 07:20:26 PM PDT 24
Peak memory 206872 kb
Host smart-85905eee-12da-40c3-91a9-ddd99959a07b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3647643301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3647643301
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1477849600
Short name T1611
Test name
Test status
Simulation time 168848547 ps
CPU time 0.78 seconds
Started Jul 14 07:20:23 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206808 kb
Host smart-77a3edee-90bd-4290-9da8-9140704802a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778
49600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1477849600
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1573119430
Short name T2478
Test name
Test status
Simulation time 234658747 ps
CPU time 0.9 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206868 kb
Host smart-15902a7c-8cc7-40fb-840a-614ad9593182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15731
19430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1573119430
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.2712352239
Short name T505
Test name
Test status
Simulation time 156923947 ps
CPU time 0.83 seconds
Started Jul 14 07:19:59 PM PDT 24
Finished Jul 14 07:20:21 PM PDT 24
Peak memory 206868 kb
Host smart-382f3283-a952-4148-b0f1-d896d0cca2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27123
52239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.2712352239
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2168197607
Short name T1647
Test name
Test status
Simulation time 170730144 ps
CPU time 0.79 seconds
Started Jul 14 07:19:59 PM PDT 24
Finished Jul 14 07:20:20 PM PDT 24
Peak memory 206880 kb
Host smart-73574165-7a8d-434f-8cf8-1dacd0e9111e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21681
97607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2168197607
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.104465698
Short name T349
Test name
Test status
Simulation time 157171498 ps
CPU time 0.77 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:20:37 PM PDT 24
Peak memory 206804 kb
Host smart-1a88d348-e7d4-4e4e-9c33-245719a19e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10446
5698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.104465698
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.437781429
Short name T1775
Test name
Test status
Simulation time 158887298 ps
CPU time 0.75 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 206856 kb
Host smart-f7d8fc97-cfa0-42f2-ae16-bbd16eb2371c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43778
1429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.437781429
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3118964329
Short name T1980
Test name
Test status
Simulation time 243684256 ps
CPU time 0.93 seconds
Started Jul 14 07:20:15 PM PDT 24
Finished Jul 14 07:20:42 PM PDT 24
Peak memory 206812 kb
Host smart-b07e1c9c-444d-4cde-b84f-8dad965c927b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3118964329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3118964329
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.130717799
Short name T1729
Test name
Test status
Simulation time 158321517 ps
CPU time 0.76 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206872 kb
Host smart-5f681114-1b41-4938-b339-9b07f0ca8eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13071
7799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.130717799
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2723689863
Short name T2373
Test name
Test status
Simulation time 40380290 ps
CPU time 0.66 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:20:39 PM PDT 24
Peak memory 206880 kb
Host smart-60edf435-c70c-4489-8d7e-8b0c224843cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27236
89863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2723689863
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.530828524
Short name T273
Test name
Test status
Simulation time 20689081057 ps
CPU time 45.36 seconds
Started Jul 14 07:20:01 PM PDT 24
Finished Jul 14 07:21:10 PM PDT 24
Peak memory 207092 kb
Host smart-48416cb5-b09d-4b54-837e-8f8ea74a7f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53082
8524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.530828524
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3458572480
Short name T2461
Test name
Test status
Simulation time 204289200 ps
CPU time 0.84 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:32 PM PDT 24
Peak memory 206864 kb
Host smart-459624b1-d862-4608-a6ee-6f9ef180d7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585
72480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3458572480
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1760814341
Short name T1148
Test name
Test status
Simulation time 217898330 ps
CPU time 0.85 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:29 PM PDT 24
Peak memory 206860 kb
Host smart-6f940a63-8d70-47fc-aa90-1653934abab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17608
14341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1760814341
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3523334402
Short name T387
Test name
Test status
Simulation time 153437407 ps
CPU time 0.82 seconds
Started Jul 14 07:20:08 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 206860 kb
Host smart-d549c5a5-9834-4662-ab54-02f489a3411a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35233
34402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3523334402
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.4101506633
Short name T1091
Test name
Test status
Simulation time 194078310 ps
CPU time 0.85 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:28 PM PDT 24
Peak memory 206856 kb
Host smart-a766db35-7333-4c5b-8157-bc607dc99a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41015
06633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.4101506633
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2269794249
Short name T1273
Test name
Test status
Simulation time 196700856 ps
CPU time 0.78 seconds
Started Jul 14 07:19:58 PM PDT 24
Finished Jul 14 07:20:20 PM PDT 24
Peak memory 206844 kb
Host smart-8473ec32-defc-42a9-bda8-eddfed24deb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22697
94249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2269794249
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.353018366
Short name T2544
Test name
Test status
Simulation time 142336514 ps
CPU time 0.76 seconds
Started Jul 14 07:20:02 PM PDT 24
Finished Jul 14 07:20:28 PM PDT 24
Peak memory 206836 kb
Host smart-ee3c9a06-0906-429e-83f1-1e325411baf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35301
8366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.353018366
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2088214413
Short name T1656
Test name
Test status
Simulation time 235623331 ps
CPU time 0.81 seconds
Started Jul 14 07:20:00 PM PDT 24
Finished Jul 14 07:20:26 PM PDT 24
Peak memory 206892 kb
Host smart-12ed3a69-c821-4330-a751-20399a2cfb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20882
14413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2088214413
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3566434933
Short name T1964
Test name
Test status
Simulation time 256569888 ps
CPU time 0.97 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206880 kb
Host smart-6a8eda74-dbb3-443a-b3b1-1b88ffcc49c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35664
34933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3566434933
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.904749260
Short name T1887
Test name
Test status
Simulation time 6022251697 ps
CPU time 54.08 seconds
Started Jul 14 07:20:09 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 207072 kb
Host smart-4b7dd4b1-2190-4640-9c19-5da9293be614
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=904749260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.904749260
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1703306534
Short name T919
Test name
Test status
Simulation time 166806726 ps
CPU time 0.75 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 206844 kb
Host smart-9074cd88-d092-49c2-8e60-314fd53694b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
06534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1703306534
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.808844160
Short name T1207
Test name
Test status
Simulation time 181917225 ps
CPU time 0.79 seconds
Started Jul 14 07:19:58 PM PDT 24
Finished Jul 14 07:20:20 PM PDT 24
Peak memory 206860 kb
Host smart-b7b0a542-aa1b-4c25-b277-4d61757c2039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80884
4160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.808844160
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.198902344
Short name T1038
Test name
Test status
Simulation time 253638835 ps
CPU time 0.96 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:33 PM PDT 24
Peak memory 206872 kb
Host smart-9682792b-7cb4-42d4-ad54-7266ce28c829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19890
2344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.198902344
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.734566023
Short name T2529
Test name
Test status
Simulation time 5268972484 ps
CPU time 35.21 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:21:04 PM PDT 24
Peak memory 207108 kb
Host smart-16aaf375-1fd1-48fc-8ca2-44778ea2ed85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73456
6023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.734566023
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2482668472
Short name T1003
Test name
Test status
Simulation time 33117503 ps
CPU time 0.66 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:20:43 PM PDT 24
Peak memory 207088 kb
Host smart-d689a4fb-8435-48a6-ba99-d1ca01024767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2482668472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2482668472
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3860466597
Short name T1662
Test name
Test status
Simulation time 3730964642 ps
CPU time 4.47 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:33 PM PDT 24
Peak memory 206932 kb
Host smart-1d09847b-808c-4a4a-ba15-214a35591f0e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3860466597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.3860466597
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2775274856
Short name T589
Test name
Test status
Simulation time 13366518689 ps
CPU time 12.63 seconds
Started Jul 14 07:20:06 PM PDT 24
Finished Jul 14 07:20:44 PM PDT 24
Peak memory 207144 kb
Host smart-39da15dd-ab16-466d-8eca-4ae6d7d1b0e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2775274856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2775274856
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2871173463
Short name T1682
Test name
Test status
Simulation time 23328903905 ps
CPU time 24.22 seconds
Started Jul 14 07:19:59 PM PDT 24
Finished Jul 14 07:20:44 PM PDT 24
Peak memory 206956 kb
Host smart-87339058-2312-4427-85e6-036f6b59a00f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2871173463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.2871173463
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.733246786
Short name T785
Test name
Test status
Simulation time 186869787 ps
CPU time 0.8 seconds
Started Jul 14 07:19:59 PM PDT 24
Finished Jul 14 07:20:20 PM PDT 24
Peak memory 206840 kb
Host smart-4db4d772-6ec7-439d-9719-68ee8ca4727b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73324
6786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.733246786
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1180298416
Short name T355
Test name
Test status
Simulation time 180748575 ps
CPU time 0.77 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:29 PM PDT 24
Peak memory 206860 kb
Host smart-19ddd31f-1077-43c0-af73-b2c5b0f0b09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11802
98416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1180298416
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1048440078
Short name T521
Test name
Test status
Simulation time 220833978 ps
CPU time 1 seconds
Started Jul 14 07:20:14 PM PDT 24
Finished Jul 14 07:20:41 PM PDT 24
Peak memory 206864 kb
Host smart-0491de4d-ca9c-4ee3-aaa1-2e66e1edffa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484
40078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1048440078
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.209415640
Short name T1379
Test name
Test status
Simulation time 828491149 ps
CPU time 1.91 seconds
Started Jul 14 07:19:58 PM PDT 24
Finished Jul 14 07:20:21 PM PDT 24
Peak memory 207088 kb
Host smart-59c909bd-f660-4e12-b229-d13befcf1c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20941
5640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.209415640
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.634087831
Short name T166
Test name
Test status
Simulation time 6429993126 ps
CPU time 11.57 seconds
Started Jul 14 07:19:56 PM PDT 24
Finished Jul 14 07:20:29 PM PDT 24
Peak memory 207076 kb
Host smart-dda2976a-9b42-49a2-af39-673730f9946c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63408
7831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.634087831
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.286302053
Short name T1817
Test name
Test status
Simulation time 396898376 ps
CPU time 1.27 seconds
Started Jul 14 07:20:15 PM PDT 24
Finished Jul 14 07:20:42 PM PDT 24
Peak memory 206876 kb
Host smart-b1561496-f983-4ace-9fc2-ee9e5dd765b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28630
2053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.286302053
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1903751910
Short name T1870
Test name
Test status
Simulation time 152304009 ps
CPU time 0.76 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206864 kb
Host smart-bee9d794-1db7-4e35-8481-7d18bc4d699c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19037
51910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1903751910
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3075236787
Short name T2666
Test name
Test status
Simulation time 99049592 ps
CPU time 0.68 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206868 kb
Host smart-28633da4-3106-49a3-b000-5f5fa298436a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30752
36787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3075236787
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2269758487
Short name T1194
Test name
Test status
Simulation time 894931976 ps
CPU time 2.27 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 207060 kb
Host smart-555b4f6f-3c0d-4141-9d1b-b45d780c0c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22697
58487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2269758487
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.511053412
Short name T186
Test name
Test status
Simulation time 325613862 ps
CPU time 2.24 seconds
Started Jul 14 07:20:05 PM PDT 24
Finished Jul 14 07:20:31 PM PDT 24
Peak memory 206996 kb
Host smart-9134d433-0c15-4622-aa64-1807d1d1175e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51105
3412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.511053412
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.4250352130
Short name T2189
Test name
Test status
Simulation time 232173011 ps
CPU time 0.91 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:20:42 PM PDT 24
Peak memory 206876 kb
Host smart-5751e03e-6e5a-4d0b-82bb-12f9bb8f6e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42503
52130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.4250352130
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3235650407
Short name T2462
Test name
Test status
Simulation time 144459591 ps
CPU time 0.76 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206884 kb
Host smart-f0464b7d-baf2-4480-ac09-18bdb0581b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
50407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3235650407
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1408367605
Short name T2651
Test name
Test status
Simulation time 230832295 ps
CPU time 0.94 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:20:43 PM PDT 24
Peak memory 206888 kb
Host smart-d4529cdc-9f88-48d1-83cc-39c868c8fc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14083
67605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1408367605
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1951661600
Short name T764
Test name
Test status
Simulation time 5173614666 ps
CPU time 48.9 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 207108 kb
Host smart-95b5f4cb-9feb-478e-9bd4-e42280dfabff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1951661600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1951661600
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.1876056324
Short name T2397
Test name
Test status
Simulation time 5458567192 ps
CPU time 18.1 seconds
Started Jul 14 07:20:05 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 207016 kb
Host smart-7fa384af-e605-4301-b578-a14d3fd0ffa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18760
56324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.1876056324
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.2245642162
Short name T2008
Test name
Test status
Simulation time 202164809 ps
CPU time 0.84 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:20:44 PM PDT 24
Peak memory 206852 kb
Host smart-76a6e973-bb23-419e-b0fd-9ea07d19b119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22456
42162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2245642162
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.4220893838
Short name T1243
Test name
Test status
Simulation time 23275268062 ps
CPU time 23.38 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:21:02 PM PDT 24
Peak memory 206916 kb
Host smart-41dce9e3-7da9-4892-86aa-ca48c1e09135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42208
93838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.4220893838
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3987542684
Short name T1341
Test name
Test status
Simulation time 3315200308 ps
CPU time 3.54 seconds
Started Jul 14 07:20:09 PM PDT 24
Finished Jul 14 07:20:38 PM PDT 24
Peak memory 206928 kb
Host smart-caf121f2-6156-49ae-a33b-4818e6c6a48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39875
42684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3987542684
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.2256182147
Short name T2114
Test name
Test status
Simulation time 8694052247 ps
CPU time 227.73 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:24:35 PM PDT 24
Peak memory 207160 kb
Host smart-40f3089f-ea8a-4dfb-b930-0683fd8f789e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22561
82147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.2256182147
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.458303649
Short name T2736
Test name
Test status
Simulation time 4244921983 ps
CPU time 29.94 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:20:59 PM PDT 24
Peak memory 207032 kb
Host smart-64c2f7be-3a18-418c-b5cc-32e68453961b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=458303649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.458303649
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.608806850
Short name T1073
Test name
Test status
Simulation time 249159748 ps
CPU time 1.03 seconds
Started Jul 14 07:20:09 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 206860 kb
Host smart-04dfc54a-24a5-4d0a-b8e0-1759f4ae4504
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=608806850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.608806850
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3429841654
Short name T846
Test name
Test status
Simulation time 228557876 ps
CPU time 0.95 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 206884 kb
Host smart-37088b38-7951-4872-9ae3-0848d94c18a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34298
41654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3429841654
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.455406960
Short name T687
Test name
Test status
Simulation time 3079596695 ps
CPU time 80.56 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:22:10 PM PDT 24
Peak memory 207108 kb
Host smart-a20c4d05-69ad-4426-8858-64169c39bbf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45540
6960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.455406960
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.4191177623
Short name T2585
Test name
Test status
Simulation time 5216984160 ps
CPU time 139.67 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:23:04 PM PDT 24
Peak memory 207060 kb
Host smart-8abce607-f4c0-487e-8085-5d3e6cd10921
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4191177623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.4191177623
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3402334194
Short name T950
Test name
Test status
Simulation time 194773243 ps
CPU time 0.82 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206892 kb
Host smart-63c3d6e0-5a94-4789-b252-1e81aa544b4a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3402334194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3402334194
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.573517647
Short name T1405
Test name
Test status
Simulation time 159986432 ps
CPU time 0.75 seconds
Started Jul 14 07:20:14 PM PDT 24
Finished Jul 14 07:20:41 PM PDT 24
Peak memory 206892 kb
Host smart-b01aec61-c61c-46d6-a7ad-15baab345cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57351
7647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.573517647
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3590506827
Short name T2553
Test name
Test status
Simulation time 184807598 ps
CPU time 0.81 seconds
Started Jul 14 07:20:19 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206888 kb
Host smart-b98641b5-b689-4d59-8b43-70868f7e75b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
06827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3590506827
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3228717259
Short name T2216
Test name
Test status
Simulation time 166120466 ps
CPU time 0.81 seconds
Started Jul 14 07:20:19 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 206856 kb
Host smart-d386fcc0-c2e8-4391-98da-8970d2bb3dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32287
17259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3228717259
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3094415646
Short name T593
Test name
Test status
Simulation time 176663379 ps
CPU time 0.91 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 206888 kb
Host smart-c9d18cfd-9c64-4cd4-8f06-169ed372a503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944
15646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3094415646
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.417488186
Short name T1431
Test name
Test status
Simulation time 171922690 ps
CPU time 0.78 seconds
Started Jul 14 07:20:15 PM PDT 24
Finished Jul 14 07:20:42 PM PDT 24
Peak memory 206836 kb
Host smart-99c9bd96-1637-4577-8c94-ae7d71af87ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
8186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.417488186
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.882067423
Short name T1189
Test name
Test status
Simulation time 148841087 ps
CPU time 0.83 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 206860 kb
Host smart-ac9e66f3-a0e9-443f-b820-243c705f9ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88206
7423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.882067423
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.249656135
Short name T77
Test name
Test status
Simulation time 217541477 ps
CPU time 0.88 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206876 kb
Host smart-a27b40a8-e413-4fe6-87a7-4ba20d5813ed
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=249656135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.249656135
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2341691941
Short name T2351
Test name
Test status
Simulation time 137849330 ps
CPU time 0.79 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:20:38 PM PDT 24
Peak memory 206828 kb
Host smart-4069f640-eeb5-431c-b249-d079417e459e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23416
91941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2341691941
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.501322180
Short name T2719
Test name
Test status
Simulation time 28838371 ps
CPU time 0.64 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:20:43 PM PDT 24
Peak memory 206888 kb
Host smart-267140fd-0986-499d-bc33-4a51b34441d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50132
2180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.501322180
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1743294195
Short name T243
Test name
Test status
Simulation time 6923020360 ps
CPU time 15.38 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 207136 kb
Host smart-821fcbfb-b36d-4a6c-9cb8-ff807be02a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17432
94195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1743294195
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3746054070
Short name T1288
Test name
Test status
Simulation time 165252790 ps
CPU time 0.82 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206876 kb
Host smart-480adf4b-39ca-4f92-aba4-ef7608f4a63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460
54070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3746054070
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.4221007002
Short name T464
Test name
Test status
Simulation time 167867559 ps
CPU time 0.79 seconds
Started Jul 14 07:20:14 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206844 kb
Host smart-a07440d7-ad81-48f8-bff3-5e2c5ab9d020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42210
07002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.4221007002
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1790201021
Short name T1127
Test name
Test status
Simulation time 237818813 ps
CPU time 0.95 seconds
Started Jul 14 07:20:14 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206880 kb
Host smart-ba316122-1901-4c02-b897-dddf074a0a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17902
01021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1790201021
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1496957209
Short name T1035
Test name
Test status
Simulation time 165971978 ps
CPU time 0.79 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206888 kb
Host smart-d5c33446-c096-46d9-8aa6-d8a0e9387255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
57209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1496957209
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.403731750
Short name T684
Test name
Test status
Simulation time 214368575 ps
CPU time 0.86 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:20:42 PM PDT 24
Peak memory 206856 kb
Host smart-3b83fdb5-a5e0-402c-b878-5c8ae5259e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
1750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.403731750
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.718480963
Short name T465
Test name
Test status
Simulation time 176166536 ps
CPU time 0.8 seconds
Started Jul 14 07:20:04 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206860 kb
Host smart-ffcc782e-1a3b-41ed-819c-274d47cf2876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71848
0963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.718480963
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3789309660
Short name T1574
Test name
Test status
Simulation time 239273322 ps
CPU time 0.87 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:20:44 PM PDT 24
Peak memory 206856 kb
Host smart-675e1d99-a710-4d11-ae8e-782be34206b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37893
09660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3789309660
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2557132256
Short name T377
Test name
Test status
Simulation time 254632727 ps
CPU time 0.96 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:20:38 PM PDT 24
Peak memory 206832 kb
Host smart-d81f3654-aeb1-4a55-8269-e401911587fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25571
32256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2557132256
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1656536439
Short name T2656
Test name
Test status
Simulation time 3256601346 ps
CPU time 29.32 seconds
Started Jul 14 07:20:14 PM PDT 24
Finished Jul 14 07:21:09 PM PDT 24
Peak memory 207012 kb
Host smart-0067f840-2599-44cc-93f1-68ed1d59df75
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1656536439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1656536439
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1594846102
Short name T1096
Test name
Test status
Simulation time 210024124 ps
CPU time 0.85 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206872 kb
Host smart-168b59c9-2dda-42ee-9064-c4de704713c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15948
46102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1594846102
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2497547491
Short name T1135
Test name
Test status
Simulation time 169049306 ps
CPU time 0.82 seconds
Started Jul 14 07:20:03 PM PDT 24
Finished Jul 14 07:20:30 PM PDT 24
Peak memory 206848 kb
Host smart-f5c830f8-3502-4410-a1ea-2b58bcacc62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24975
47491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2497547491
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.3191146957
Short name T1607
Test name
Test status
Simulation time 642247991 ps
CPU time 1.58 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:20:49 PM PDT 24
Peak memory 207040 kb
Host smart-b02128b7-a74e-4b79-88f0-17e8e25900a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31911
46957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.3191146957
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.903771178
Short name T1653
Test name
Test status
Simulation time 4999101146 ps
CPU time 35.49 seconds
Started Jul 14 07:20:05 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 207076 kb
Host smart-801291a3-2745-46c8-aee6-346a08e39a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90377
1178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.903771178
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.735308428
Short name T1929
Test name
Test status
Simulation time 61599584 ps
CPU time 0.67 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206968 kb
Host smart-9cdc4b3c-19ef-422a-b0cc-ba765d024f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=735308428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.735308428
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1341916431
Short name T1346
Test name
Test status
Simulation time 3431553496 ps
CPU time 4.88 seconds
Started Jul 14 07:20:24 PM PDT 24
Finished Jul 14 07:20:54 PM PDT 24
Peak memory 207076 kb
Host smart-dc29af6d-fc4a-427d-9706-176697c6ea21
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1341916431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1341916431
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.539274654
Short name T2173
Test name
Test status
Simulation time 13330021212 ps
CPU time 13.93 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:21:01 PM PDT 24
Peak memory 207068 kb
Host smart-5e96e155-be80-454a-8577-22b174b1d539
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=539274654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.539274654
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.241894773
Short name T1403
Test name
Test status
Simulation time 23370537532 ps
CPU time 23.51 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:21:08 PM PDT 24
Peak memory 207056 kb
Host smart-c451b0ee-3a0d-4fe4-8aef-7c60240fa95a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=241894773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.241894773
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.320797105
Short name T436
Test name
Test status
Simulation time 211263252 ps
CPU time 0.84 seconds
Started Jul 14 07:20:20 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 206868 kb
Host smart-b3ae4181-2494-4954-ac48-ad7676faa055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32079
7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.320797105
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2940786256
Short name T2479
Test name
Test status
Simulation time 171024206 ps
CPU time 0.77 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206868 kb
Host smart-b99d0fb1-067d-43b1-baf2-545be4f77798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29407
86256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2940786256
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.128923295
Short name T2211
Test name
Test status
Simulation time 302558579 ps
CPU time 1.08 seconds
Started Jul 14 07:20:15 PM PDT 24
Finished Jul 14 07:20:42 PM PDT 24
Peak memory 206860 kb
Host smart-898540be-b7f8-46b4-a079-5e303e02f050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12892
3295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.128923295
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1543700975
Short name T1520
Test name
Test status
Simulation time 352582903 ps
CPU time 1.1 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:20:43 PM PDT 24
Peak memory 206892 kb
Host smart-7a74cd95-7ad7-46be-908e-1a9dbeffc9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15437
00975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1543700975
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1976112527
Short name T159
Test name
Test status
Simulation time 21846950633 ps
CPU time 42.8 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:21:27 PM PDT 24
Peak memory 207080 kb
Host smart-f8de76c2-b44b-4977-8b57-c5d722b708a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19761
12527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1976112527
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1359323942
Short name T1020
Test name
Test status
Simulation time 396851685 ps
CPU time 1.27 seconds
Started Jul 14 07:20:20 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 206876 kb
Host smart-ea2cbc59-0b9f-453b-be13-cfd3ee1f183e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13593
23942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1359323942
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2045092646
Short name T478
Test name
Test status
Simulation time 169005901 ps
CPU time 0.75 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206884 kb
Host smart-96ce05c9-07b6-4231-94ff-576b0e0203df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20450
92646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2045092646
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2232268334
Short name T707
Test name
Test status
Simulation time 35403471 ps
CPU time 0.65 seconds
Started Jul 14 07:20:20 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 206876 kb
Host smart-e9bb3d52-e10d-4923-9908-12b2a6cc04f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322
68334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2232268334
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1732204871
Short name T952
Test name
Test status
Simulation time 851816341 ps
CPU time 2.33 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:20:39 PM PDT 24
Peak memory 207060 kb
Host smart-28237e53-93a3-46b9-b2d9-68053eddb3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17322
04871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1732204871
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1826497940
Short name T2437
Test name
Test status
Simulation time 151352641 ps
CPU time 1.4 seconds
Started Jul 14 07:20:20 PM PDT 24
Finished Jul 14 07:20:48 PM PDT 24
Peak memory 207008 kb
Host smart-09875c5c-7334-4674-97e0-f6faa79155dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18264
97940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1826497940
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.863322486
Short name T1714
Test name
Test status
Simulation time 192043032 ps
CPU time 0.83 seconds
Started Jul 14 07:20:09 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 206840 kb
Host smart-74645b53-16a9-42f4-a23c-61100d7694b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86332
2486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.863322486
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3779143384
Short name T1448
Test name
Test status
Simulation time 142736642 ps
CPU time 0.74 seconds
Started Jul 14 07:20:07 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 206844 kb
Host smart-9f3df3bb-ae64-44ef-8811-7aa5adf03daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37791
43384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3779143384
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.812307063
Short name T367
Test name
Test status
Simulation time 227244640 ps
CPU time 0.91 seconds
Started Jul 14 07:20:15 PM PDT 24
Finished Jul 14 07:20:42 PM PDT 24
Peak memory 206764 kb
Host smart-48a803b7-3f11-44da-9127-be732d77b414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81230
7063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.812307063
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1789511077
Short name T1318
Test name
Test status
Simulation time 6969789349 ps
CPU time 196.81 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:23:55 PM PDT 24
Peak memory 207096 kb
Host smart-90b643bd-86d3-44f3-a9b0-affbff2815cc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1789511077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1789511077
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.3289357905
Short name T1252
Test name
Test status
Simulation time 13407496204 ps
CPU time 45.9 seconds
Started Jul 14 07:20:15 PM PDT 24
Finished Jul 14 07:21:27 PM PDT 24
Peak memory 207044 kb
Host smart-d969f4c4-07ce-4036-907d-6dfac4d21428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32893
57905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.3289357905
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1556376546
Short name T1803
Test name
Test status
Simulation time 232676101 ps
CPU time 0.88 seconds
Started Jul 14 07:20:09 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 206856 kb
Host smart-9b3a3c50-02cb-4f6a-880e-bfc3f1a07c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15563
76546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1556376546
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.3968377110
Short name T568
Test name
Test status
Simulation time 23291655473 ps
CPU time 23.74 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:21:03 PM PDT 24
Peak memory 206904 kb
Host smart-2c22f31d-daed-4342-9c94-f89a6bdba260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39683
77110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3968377110
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1832854035
Short name T2190
Test name
Test status
Simulation time 3347101530 ps
CPU time 4.11 seconds
Started Jul 14 07:20:15 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206936 kb
Host smart-c5aaae97-6d64-46b2-8f54-33b8b1ac1357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18328
54035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1832854035
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.715907820
Short name T487
Test name
Test status
Simulation time 12737667671 ps
CPU time 341.02 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:26:20 PM PDT 24
Peak memory 207100 kb
Host smart-b7c37053-75fc-43bc-a2ad-2b7c9636b809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71590
7820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.715907820
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3025901129
Short name T609
Test name
Test status
Simulation time 3952925569 ps
CPU time 27.02 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:21:10 PM PDT 24
Peak memory 207136 kb
Host smart-f75404b8-f90c-4792-bb5c-73fd649dd528
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3025901129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3025901129
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.787326999
Short name T723
Test name
Test status
Simulation time 266900349 ps
CPU time 0.94 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206872 kb
Host smart-f0ab6672-a4ef-4443-96c0-fd91152bd40a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=787326999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.787326999
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.549734066
Short name T887
Test name
Test status
Simulation time 212620260 ps
CPU time 0.86 seconds
Started Jul 14 07:20:12 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206872 kb
Host smart-1c0377fd-58ee-46d3-b4b8-aa956f83600b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54973
4066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.549734066
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1443528174
Short name T1329
Test name
Test status
Simulation time 5708192316 ps
CPU time 54.55 seconds
Started Jul 14 07:20:10 PM PDT 24
Finished Jul 14 07:21:30 PM PDT 24
Peak memory 207052 kb
Host smart-a08a40e6-5208-4e49-9a89-f2e670918cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14435
28174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1443528174
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1482220559
Short name T2151
Test name
Test status
Simulation time 4176552911 ps
CPU time 39.32 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:21:22 PM PDT 24
Peak memory 207048 kb
Host smart-ed3244d6-9d1c-4b06-993d-6161c0c7ed0d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1482220559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1482220559
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.597275510
Short name T135
Test name
Test status
Simulation time 154601641 ps
CPU time 0.79 seconds
Started Jul 14 07:20:20 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 206872 kb
Host smart-8bd3bf1c-8d33-4922-bc76-84e8b61761c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=597275510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.597275510
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.4201999788
Short name T2635
Test name
Test status
Simulation time 146950033 ps
CPU time 0.74 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:20:43 PM PDT 24
Peak memory 206868 kb
Host smart-70da668f-b368-45ad-804f-0f5bd1bfc795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42019
99788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.4201999788
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.624337088
Short name T716
Test name
Test status
Simulation time 225924558 ps
CPU time 0.86 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206852 kb
Host smart-e979bdca-5982-42bb-944b-11741c73b4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62433
7088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.624337088
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3282806540
Short name T1023
Test name
Test status
Simulation time 203541923 ps
CPU time 0.8 seconds
Started Jul 14 07:20:24 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206860 kb
Host smart-217625b3-a84f-4827-b188-7d609d3276e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32828
06540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3282806540
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2579524709
Short name T1082
Test name
Test status
Simulation time 155917480 ps
CPU time 0.81 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206880 kb
Host smart-7582aca7-2df4-4363-80f0-443f427eb634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25795
24709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2579524709
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1873326528
Short name T518
Test name
Test status
Simulation time 167602952 ps
CPU time 0.79 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206864 kb
Host smart-313a05aa-3d79-4c52-984f-460f8795768a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18733
26528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1873326528
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3413001451
Short name T1246
Test name
Test status
Simulation time 155198120 ps
CPU time 0.76 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206816 kb
Host smart-5647e333-c815-4aae-99a3-cda94b32c8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34130
01451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3413001451
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3692872881
Short name T1952
Test name
Test status
Simulation time 221071298 ps
CPU time 0.89 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206872 kb
Host smart-3a09b041-f92b-4734-b732-fc1abfc5456a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3692872881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3692872881
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.809755285
Short name T1175
Test name
Test status
Simulation time 150206489 ps
CPU time 0.77 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:20:43 PM PDT 24
Peak memory 206844 kb
Host smart-e930ac9d-b0f0-4c20-bb87-5c27552fdec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80975
5285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.809755285
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.31151260
Short name T1898
Test name
Test status
Simulation time 54991569 ps
CPU time 0.67 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206784 kb
Host smart-4d8de72a-0825-42b3-8898-7cf4dc92757a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31151
260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.31151260
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.4289764471
Short name T2417
Test name
Test status
Simulation time 12406381370 ps
CPU time 25.76 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 215356 kb
Host smart-e1312e5a-4f42-40da-901d-e93d4584aacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42897
64471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.4289764471
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3248904514
Short name T2457
Test name
Test status
Simulation time 151847398 ps
CPU time 0.78 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206864 kb
Host smart-1bde852f-7b16-4177-89e1-cc5a9a3977d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32489
04514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3248904514
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3799152915
Short name T2706
Test name
Test status
Simulation time 188421651 ps
CPU time 0.8 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206860 kb
Host smart-54ea3fb4-21c7-44f0-bf1a-0a1976923b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37991
52915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3799152915
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.466852538
Short name T2721
Test name
Test status
Simulation time 179207134 ps
CPU time 0.83 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:20:48 PM PDT 24
Peak memory 206856 kb
Host smart-2acdb604-e0ed-4a89-be2a-343b861a3b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46685
2538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.466852538
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.2194921491
Short name T2609
Test name
Test status
Simulation time 198274816 ps
CPU time 0.87 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206820 kb
Host smart-a63cad26-9d3f-45bc-afa4-7c3a8a48519b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21949
21491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.2194921491
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.570812505
Short name T1946
Test name
Test status
Simulation time 168477616 ps
CPU time 0.81 seconds
Started Jul 14 07:20:19 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 206872 kb
Host smart-04843ee3-608d-4451-8fd0-5f58e874abc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57081
2505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.570812505
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2118277487
Short name T17
Test name
Test status
Simulation time 165129729 ps
CPU time 0.8 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206860 kb
Host smart-7a402f21-c2dc-4f41-96a7-3c924f5b4b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21182
77487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2118277487
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.334499380
Short name T2007
Test name
Test status
Simulation time 168411736 ps
CPU time 0.79 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:20:40 PM PDT 24
Peak memory 206852 kb
Host smart-78688f48-0167-4490-a26e-b1a569b18c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33449
9380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.334499380
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2935403169
Short name T1230
Test name
Test status
Simulation time 202271194 ps
CPU time 0.84 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:20:43 PM PDT 24
Peak memory 206872 kb
Host smart-d7faa931-9f16-451d-a9dc-1536227b47dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29354
03169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2935403169
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2576809020
Short name T1455
Test name
Test status
Simulation time 5904454201 ps
CPU time 162.31 seconds
Started Jul 14 07:20:13 PM PDT 24
Finished Jul 14 07:23:21 PM PDT 24
Peak memory 207036 kb
Host smart-66fbafe0-c740-4e9f-9880-3ac293422c14
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2576809020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2576809020
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2801102215
Short name T951
Test name
Test status
Simulation time 182004600 ps
CPU time 0.84 seconds
Started Jul 14 07:20:25 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206872 kb
Host smart-9e5190ea-6bd0-4ab2-ab68-4b7b97ecc36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28011
02215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2801102215
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.591175835
Short name T373
Test name
Test status
Simulation time 175701366 ps
CPU time 0.77 seconds
Started Jul 14 07:20:17 PM PDT 24
Finished Jul 14 07:20:44 PM PDT 24
Peak memory 206888 kb
Host smart-6d60662a-e57b-4f0a-9169-f693ec312293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59117
5835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.591175835
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3143385950
Short name T2507
Test name
Test status
Simulation time 1325834362 ps
CPU time 2.74 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:57 PM PDT 24
Peak memory 207064 kb
Host smart-bfde579e-049e-47aa-a3c2-d676f2b6faf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
85950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3143385950
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1473344082
Short name T1340
Test name
Test status
Simulation time 6205892993 ps
CPU time 59.94 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 206996 kb
Host smart-1601e0cc-be13-4a18-a29a-dd8074ef9009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14733
44082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1473344082
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.3318162772
Short name T500
Test name
Test status
Simulation time 116929396 ps
CPU time 0.73 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206936 kb
Host smart-6cd0501d-80ec-46d2-b565-0142dcf105ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3318162772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3318162772
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3676233131
Short name T860
Test name
Test status
Simulation time 3462160640 ps
CPU time 4.05 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:20:59 PM PDT 24
Peak memory 206928 kb
Host smart-88fbe4a5-84b9-47e9-8dcb-216df087761c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3676233131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.3676233131
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.507783241
Short name T2359
Test name
Test status
Simulation time 13361597853 ps
CPU time 12.02 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:21:06 PM PDT 24
Peak memory 206900 kb
Host smart-59490de1-fabb-4794-93df-a5eb0eaa502e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=507783241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.507783241
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3232947838
Short name T1060
Test name
Test status
Simulation time 23324940314 ps
CPU time 23.83 seconds
Started Jul 14 07:20:16 PM PDT 24
Finished Jul 14 07:21:06 PM PDT 24
Peak memory 206936 kb
Host smart-3d7b0246-c6b9-49ad-870d-84e823b3f2c8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3232947838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.3232947838
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3468668338
Short name T2680
Test name
Test status
Simulation time 171112194 ps
CPU time 0.79 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206848 kb
Host smart-31acccac-995b-4655-a9af-8014802c0aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34686
68338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3468668338
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.972827461
Short name T2139
Test name
Test status
Simulation time 179316352 ps
CPU time 0.75 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206864 kb
Host smart-c7799811-9411-429a-ba79-77611cc9829b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97282
7461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.972827461
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3055596349
Short name T2582
Test name
Test status
Simulation time 392923073 ps
CPU time 1.23 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206568 kb
Host smart-14d231de-24fb-46df-a212-6ff98166971b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30555
96349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3055596349
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2449040166
Short name T1575
Test name
Test status
Simulation time 935813087 ps
CPU time 2.22 seconds
Started Jul 14 07:20:26 PM PDT 24
Finished Jul 14 07:20:53 PM PDT 24
Peak memory 207012 kb
Host smart-6135a75d-c004-4b9a-87b1-51a685038332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24490
40166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2449040166
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2009557185
Short name T844
Test name
Test status
Simulation time 16694406953 ps
CPU time 31.26 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:21:21 PM PDT 24
Peak memory 207084 kb
Host smart-54ea2437-c829-4ea7-be14-ac5fc9aecf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20095
57185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2009557185
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1387095852
Short name T2031
Test name
Test status
Simulation time 424785647 ps
CPU time 1.15 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206876 kb
Host smart-e9244dc6-6c58-49ba-901c-db2fbb9cc2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13870
95852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1387095852
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3063907648
Short name T1281
Test name
Test status
Simulation time 149694303 ps
CPU time 0.77 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:20:56 PM PDT 24
Peak memory 206872 kb
Host smart-a8485617-1016-4810-acc9-7eb6640603ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30639
07648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3063907648
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1573519542
Short name T2650
Test name
Test status
Simulation time 30600749 ps
CPU time 0.67 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206804 kb
Host smart-9a628eb6-b59c-496a-b1ef-d419a33dc173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15735
19542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1573519542
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3041234730
Short name T2251
Test name
Test status
Simulation time 844961972 ps
CPU time 2.1 seconds
Started Jul 14 07:20:23 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 207092 kb
Host smart-1a7fbe23-bf25-43d4-9b00-1ab98553d790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30412
34730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3041234730
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3545330816
Short name T643
Test name
Test status
Simulation time 168018763 ps
CPU time 1.61 seconds
Started Jul 14 07:20:24 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 207048 kb
Host smart-fd47b95d-32fa-41d2-b3ce-1810e679bb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35453
30816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3545330816
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2739384084
Short name T1158
Test name
Test status
Simulation time 290279234 ps
CPU time 0.92 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206876 kb
Host smart-6190d527-57cb-4954-aa63-bb3c22998583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27393
84084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2739384084
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3078217557
Short name T2413
Test name
Test status
Simulation time 145228794 ps
CPU time 0.75 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206892 kb
Host smart-b9d2364c-4a9b-4737-93e3-f00198c93f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30782
17557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3078217557
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3065210878
Short name T239
Test name
Test status
Simulation time 158096966 ps
CPU time 0.77 seconds
Started Jul 14 07:20:23 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206888 kb
Host smart-4cdb26ec-6978-40d1-a0a5-8c6836512363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30652
10878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3065210878
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.3310263346
Short name T91
Test name
Test status
Simulation time 6892077715 ps
CPU time 183.13 seconds
Started Jul 14 07:20:20 PM PDT 24
Finished Jul 14 07:23:50 PM PDT 24
Peak memory 207076 kb
Host smart-1f0ddc2a-23e9-4b66-b7c7-e00fad24fa50
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3310263346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.3310263346
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.547068719
Short name T2714
Test name
Test status
Simulation time 6232435344 ps
CPU time 23.92 seconds
Started Jul 14 07:20:23 PM PDT 24
Finished Jul 14 07:21:13 PM PDT 24
Peak memory 207108 kb
Host smart-d541e432-4bf7-43ee-8c91-969723d267c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54706
8719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.547068719
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3258115667
Short name T1848
Test name
Test status
Simulation time 235259052 ps
CPU time 0.88 seconds
Started Jul 14 07:20:18 PM PDT 24
Finished Jul 14 07:20:45 PM PDT 24
Peak memory 206868 kb
Host smart-0ac33199-b7aa-4241-911b-d9e0dc36e716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32581
15667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3258115667
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2218510313
Short name T1474
Test name
Test status
Simulation time 23317343725 ps
CPU time 26.69 seconds
Started Jul 14 07:20:23 PM PDT 24
Finished Jul 14 07:21:16 PM PDT 24
Peak memory 206908 kb
Host smart-24bdf23e-1979-406d-9508-6307e0f495bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22185
10313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2218510313
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.174790547
Short name T2523
Test name
Test status
Simulation time 3317387590 ps
CPU time 3.53 seconds
Started Jul 14 07:20:23 PM PDT 24
Finished Jul 14 07:20:53 PM PDT 24
Peak memory 206912 kb
Host smart-0b51d1a8-8005-4d4f-b287-7d719a53016b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17479
0547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.174790547
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1383109119
Short name T2632
Test name
Test status
Simulation time 9456462595 ps
CPU time 254.35 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:25:02 PM PDT 24
Peak memory 207100 kb
Host smart-b3c260f5-578c-4c30-be4e-46188ba74571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13831
09119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1383109119
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1725248198
Short name T2733
Test name
Test status
Simulation time 6184015036 ps
CPU time 44.3 seconds
Started Jul 14 07:20:22 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 207000 kb
Host smart-4373f835-3b7b-46b8-a3c4-1cc0b790a25d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1725248198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1725248198
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2622903503
Short name T2103
Test name
Test status
Simulation time 243114292 ps
CPU time 0.92 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:20:48 PM PDT 24
Peak memory 206852 kb
Host smart-aa37aca3-2578-43a9-b5d7-a267e380bc63
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2622903503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2622903503
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3841759721
Short name T2028
Test name
Test status
Simulation time 194324659 ps
CPU time 0.88 seconds
Started Jul 14 07:20:20 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 206872 kb
Host smart-2c37f0b2-acd9-4177-b6f8-90a40a1fd5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38417
59721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3841759721
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.3013353011
Short name T2664
Test name
Test status
Simulation time 5615713115 ps
CPU time 51.37 seconds
Started Jul 14 07:20:19 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 207104 kb
Host smart-e47330a8-8386-43ed-b485-e7ccab454c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30133
53011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.3013353011
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.32394011
Short name T1529
Test name
Test status
Simulation time 5491691861 ps
CPU time 52.68 seconds
Started Jul 14 07:20:33 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 207108 kb
Host smart-fee630ca-01e9-42b5-9e21-2cfcefd2778b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=32394011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.32394011
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3719796525
Short name T1960
Test name
Test status
Simulation time 162797448 ps
CPU time 0.83 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206876 kb
Host smart-94c8e896-bc34-4f7e-8d49-68f96a0279bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3719796525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3719796525
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1601861104
Short name T597
Test name
Test status
Simulation time 149919012 ps
CPU time 0.77 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206824 kb
Host smart-0c96439b-9fe8-4dd1-9678-37cd2d656e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16018
61104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1601861104
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3391031435
Short name T122
Test name
Test status
Simulation time 255215205 ps
CPU time 0.9 seconds
Started Jul 14 07:20:20 PM PDT 24
Finished Jul 14 07:20:47 PM PDT 24
Peak memory 206880 kb
Host smart-224609a9-c326-468d-a5ee-3252e3c0f94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33910
31435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3391031435
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2765013196
Short name T2623
Test name
Test status
Simulation time 160456959 ps
CPU time 0.83 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:20:48 PM PDT 24
Peak memory 206888 kb
Host smart-61eff9fd-6cf6-4736-8af7-83bd1373778f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650
13196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2765013196
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1452312862
Short name T1593
Test name
Test status
Simulation time 146515072 ps
CPU time 0.75 seconds
Started Jul 14 07:20:27 PM PDT 24
Finished Jul 14 07:20:53 PM PDT 24
Peak memory 206864 kb
Host smart-bdcdb975-1a03-4bfa-9561-f2eafba65391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14523
12862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1452312862
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2730871077
Short name T1587
Test name
Test status
Simulation time 193453197 ps
CPU time 0.79 seconds
Started Jul 14 07:20:23 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206868 kb
Host smart-beed8f2b-4913-4948-a1ba-e61a5d224c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27308
71077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2730871077
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1026396259
Short name T678
Test name
Test status
Simulation time 196726206 ps
CPU time 0.93 seconds
Started Jul 14 07:20:24 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206872 kb
Host smart-746059d6-a34b-46f8-9c46-1ab243131cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10263
96259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1026396259
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.2937152996
Short name T1372
Test name
Test status
Simulation time 249062829 ps
CPU time 0.99 seconds
Started Jul 14 07:20:26 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206856 kb
Host smart-2d466dd3-b678-4d98-b1f0-f9274f339ba2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2937152996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.2937152996
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2341387754
Short name T1025
Test name
Test status
Simulation time 156641531 ps
CPU time 0.79 seconds
Started Jul 14 07:20:24 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206868 kb
Host smart-bb9576be-c14d-4d85-a53b-7b87d8b7ec89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
87754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2341387754
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3497732950
Short name T2674
Test name
Test status
Simulation time 33572107 ps
CPU time 0.67 seconds
Started Jul 14 07:20:21 PM PDT 24
Finished Jul 14 07:20:48 PM PDT 24
Peak memory 206816 kb
Host smart-7f594519-aceb-4bb7-8490-c32998b10924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34977
32950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3497732950
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3366892733
Short name T2438
Test name
Test status
Simulation time 21982035731 ps
CPU time 47.92 seconds
Started Jul 14 07:20:28 PM PDT 24
Finished Jul 14 07:21:41 PM PDT 24
Peak memory 207120 kb
Host smart-1e999212-b513-4299-8464-3cb12265a48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33668
92733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3366892733
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.4170185464
Short name T279
Test name
Test status
Simulation time 202525502 ps
CPU time 0.9 seconds
Started Jul 14 07:20:26 PM PDT 24
Finished Jul 14 07:20:52 PM PDT 24
Peak memory 206860 kb
Host smart-ed8e0ff6-3601-44b9-abff-74788e1f4287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701
85464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.4170185464
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1305588051
Short name T2022
Test name
Test status
Simulation time 196117348 ps
CPU time 0.8 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206888 kb
Host smart-49b3fba3-9e6a-42bd-bbe9-eb7566300a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13055
88051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1305588051
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1136643290
Short name T2238
Test name
Test status
Simulation time 183057806 ps
CPU time 0.83 seconds
Started Jul 14 07:20:26 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206844 kb
Host smart-cb7e77c4-15a3-4d47-bc5e-d51644a09b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11366
43290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1136643290
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1366840239
Short name T811
Test name
Test status
Simulation time 232728240 ps
CPU time 0.88 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206884 kb
Host smart-d7453514-c426-49a8-a75d-199d1e508930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13668
40239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1366840239
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.277435175
Short name T2196
Test name
Test status
Simulation time 195431094 ps
CPU time 0.79 seconds
Started Jul 14 07:20:25 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206876 kb
Host smart-8a4819a6-a3f5-4def-8f53-abdf38200974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27743
5175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.277435175
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3206750359
Short name T1928
Test name
Test status
Simulation time 175657455 ps
CPU time 0.75 seconds
Started Jul 14 07:20:25 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206856 kb
Host smart-da66ec33-2432-4ce0-8dde-cdee3f6238a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32067
50359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3206750359
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3674126112
Short name T2039
Test name
Test status
Simulation time 171263378 ps
CPU time 0.8 seconds
Started Jul 14 07:20:25 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206828 kb
Host smart-19eec02e-7379-4007-9c28-b3c4bb04d063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36741
26112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3674126112
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1393873716
Short name T2002
Test name
Test status
Simulation time 225916133 ps
CPU time 0.9 seconds
Started Jul 14 07:20:33 PM PDT 24
Finished Jul 14 07:20:58 PM PDT 24
Peak memory 206840 kb
Host smart-7213891c-c017-4488-802f-f073396a5187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13938
73716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1393873716
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3333375148
Short name T2064
Test name
Test status
Simulation time 5224314802 ps
CPU time 35.07 seconds
Started Jul 14 07:20:28 PM PDT 24
Finished Jul 14 07:21:28 PM PDT 24
Peak memory 207164 kb
Host smart-48583972-c65c-4257-9a2d-cf03a81ef0e5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3333375148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3333375148
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.695341072
Short name T1716
Test name
Test status
Simulation time 167120535 ps
CPU time 0.79 seconds
Started Jul 14 07:20:28 PM PDT 24
Finished Jul 14 07:20:54 PM PDT 24
Peak memory 206892 kb
Host smart-da699767-6241-4f14-8f4e-43600ddede55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69534
1072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.695341072
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3856712254
Short name T574
Test name
Test status
Simulation time 174953305 ps
CPU time 0.82 seconds
Started Jul 14 07:20:24 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206856 kb
Host smart-0e4c3ca9-650c-4b4c-95b4-6f7fb7fa5bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
12254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3856712254
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.2561113135
Short name T2432
Test name
Test status
Simulation time 223483839 ps
CPU time 0.88 seconds
Started Jul 14 07:20:33 PM PDT 24
Finished Jul 14 07:20:58 PM PDT 24
Peak memory 206752 kb
Host smart-97a2b6df-5ee1-489b-aabd-e5fb75250ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25611
13135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.2561113135
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.354792906
Short name T2291
Test name
Test status
Simulation time 4834613445 ps
CPU time 37.16 seconds
Started Jul 14 07:20:25 PM PDT 24
Finished Jul 14 07:21:27 PM PDT 24
Peak memory 207120 kb
Host smart-210e3f36-93f0-4a63-ab7d-dea7cd1834c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35479
2906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.354792906
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1536064509
Short name T1128
Test name
Test status
Simulation time 62639897 ps
CPU time 0.72 seconds
Started Jul 14 07:13:09 PM PDT 24
Finished Jul 14 07:13:26 PM PDT 24
Peak memory 206920 kb
Host smart-72b6e0b6-72f8-450c-b818-83bb2a1b7c32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1536064509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1536064509
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3213696480
Short name T1493
Test name
Test status
Simulation time 3980893003 ps
CPU time 5.42 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:13:22 PM PDT 24
Peak memory 206912 kb
Host smart-62d26d01-1702-4231-954d-d013bf6573b7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3213696480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.3213696480
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1409908396
Short name T1380
Test name
Test status
Simulation time 13408268343 ps
CPU time 11.98 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:13:28 PM PDT 24
Peak memory 207084 kb
Host smart-c9f67075-1bb6-4066-83a7-f10b2b6d530a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1409908396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1409908396
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2997497223
Short name T1061
Test name
Test status
Simulation time 23356449335 ps
CPU time 24.18 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:40 PM PDT 24
Peak memory 206724 kb
Host smart-075090d8-d9f4-44a3-991e-3d45e6ec80d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2997497223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.2997497223
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.48388489
Short name T1350
Test name
Test status
Simulation time 187955519 ps
CPU time 0.9 seconds
Started Jul 14 07:13:01 PM PDT 24
Finished Jul 14 07:13:20 PM PDT 24
Peak memory 206928 kb
Host smart-71d3f01f-e38e-45fb-84fd-5365668b7aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48388
489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.48388489
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.369652644
Short name T48
Test name
Test status
Simulation time 154661444 ps
CPU time 0.74 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:16 PM PDT 24
Peak memory 206864 kb
Host smart-ca314cd6-e6b1-4319-92e5-2e36dfb3e75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36965
2644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.369652644
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.696164966
Short name T78
Test name
Test status
Simulation time 141705068 ps
CPU time 0.75 seconds
Started Jul 14 07:13:07 PM PDT 24
Finished Jul 14 07:13:24 PM PDT 24
Peak memory 206860 kb
Host smart-48ba0a0d-cb82-4627-b9e7-446d77ee19ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69616
4966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.696164966
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3427825830
Short name T648
Test name
Test status
Simulation time 185731290 ps
CPU time 0.81 seconds
Started Jul 14 07:12:58 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206856 kb
Host smart-1fee5613-4e75-4ce1-aedd-01dd9c4f85c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34278
25830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3427825830
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2763644835
Short name T1218
Test name
Test status
Simulation time 371530549 ps
CPU time 1.17 seconds
Started Jul 14 07:13:00 PM PDT 24
Finished Jul 14 07:13:20 PM PDT 24
Peak memory 206856 kb
Host smart-30cf240c-4a7c-403c-a229-ab5675883d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
44835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2763644835
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1552440221
Short name T2273
Test name
Test status
Simulation time 277023520 ps
CPU time 0.91 seconds
Started Jul 14 07:12:58 PM PDT 24
Finished Jul 14 07:13:18 PM PDT 24
Peak memory 206916 kb
Host smart-92a37650-38ab-4e18-917c-bcfbf0ab500b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
40221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1552440221
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3441869591
Short name T1086
Test name
Test status
Simulation time 20101055619 ps
CPU time 33.75 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:49 PM PDT 24
Peak memory 207120 kb
Host smart-aa9e9d88-84a4-4715-8821-69ddb35d7b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34418
69591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3441869591
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3540291559
Short name T915
Test name
Test status
Simulation time 355680158 ps
CPU time 1.23 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:13:18 PM PDT 24
Peak memory 206876 kb
Host smart-cef37862-7f99-4c1e-9ba5-0524394158e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35402
91559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3540291559
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1699821842
Short name T45
Test name
Test status
Simulation time 174871510 ps
CPU time 0.8 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206860 kb
Host smart-4d896b13-2784-4fad-9582-698250c4ffc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998
21842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1699821842
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.844423517
Short name T1974
Test name
Test status
Simulation time 81261297 ps
CPU time 0.72 seconds
Started Jul 14 07:12:58 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206864 kb
Host smart-1bc41ccb-50d6-4c27-b011-c571eafb5a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84442
3517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.844423517
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2620562178
Short name T1642
Test name
Test status
Simulation time 886270435 ps
CPU time 2.12 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:13:18 PM PDT 24
Peak memory 207056 kb
Host smart-40007b36-a867-4169-9d1d-789b511ea79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26205
62178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2620562178
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.810827657
Short name T1156
Test name
Test status
Simulation time 204296077 ps
CPU time 1.29 seconds
Started Jul 14 07:12:58 PM PDT 24
Finished Jul 14 07:13:18 PM PDT 24
Peak memory 206964 kb
Host smart-8eee1e2d-7de4-477c-8ddf-8b212c040a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81082
7657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.810827657
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2147420995
Short name T1717
Test name
Test status
Simulation time 100177255204 ps
CPU time 131.47 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:15:27 PM PDT 24
Peak memory 207108 kb
Host smart-b289f78e-a200-4326-b2ef-dca7dcdd75cf
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2147420995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2147420995
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2548512019
Short name T1594
Test name
Test status
Simulation time 119227422625 ps
CPU time 151.55 seconds
Started Jul 14 07:12:57 PM PDT 24
Finished Jul 14 07:15:48 PM PDT 24
Peak memory 207152 kb
Host smart-2dcd5dc2-17b8-4b5b-aafa-57ac7ed5e383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548512019 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2548512019
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.3966951970
Short name T39
Test name
Test status
Simulation time 115155275746 ps
CPU time 153.47 seconds
Started Jul 14 07:13:00 PM PDT 24
Finished Jul 14 07:15:51 PM PDT 24
Peak memory 207072 kb
Host smart-8b0de5fe-9e1f-4c36-92bb-a55aa7e9c696
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3966951970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3966951970
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.2665409669
Short name T1132
Test name
Test status
Simulation time 83043666371 ps
CPU time 120.69 seconds
Started Jul 14 07:13:13 PM PDT 24
Finished Jul 14 07:15:27 PM PDT 24
Peak memory 207068 kb
Host smart-f4097e17-2786-4652-8c5b-2efca8ea014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665409669 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.2665409669
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3312177610
Short name T361
Test name
Test status
Simulation time 91125527374 ps
CPU time 114.42 seconds
Started Jul 14 07:12:56 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 207124 kb
Host smart-99a3e8da-ef2b-4355-94bc-2a91b5296d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33121
77610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3312177610
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1330812731
Short name T765
Test name
Test status
Simulation time 216048139 ps
CPU time 0.84 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206860 kb
Host smart-63c98350-12d2-4bc4-85cb-1fa2a184a49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13308
12731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1330812731
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3499837134
Short name T309
Test name
Test status
Simulation time 142095980 ps
CPU time 0.76 seconds
Started Jul 14 07:12:54 PM PDT 24
Finished Jul 14 07:13:15 PM PDT 24
Peak memory 206848 kb
Host smart-9c55d4e9-aa0a-425e-bc11-694547a44efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34998
37134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3499837134
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2204736594
Short name T1191
Test name
Test status
Simulation time 254347337 ps
CPU time 0.89 seconds
Started Jul 14 07:12:58 PM PDT 24
Finished Jul 14 07:13:17 PM PDT 24
Peak memory 206912 kb
Host smart-922b237c-e655-4cbf-843d-c8d6f8d899f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22047
36594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2204736594
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3642473147
Short name T463
Test name
Test status
Simulation time 5601371607 ps
CPU time 18.68 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:42 PM PDT 24
Peak memory 207060 kb
Host smart-ea84e6fe-ff8f-42be-869b-0d9314abf80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36424
73147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3642473147
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.918044777
Short name T2720
Test name
Test status
Simulation time 262395195 ps
CPU time 0.93 seconds
Started Jul 14 07:13:07 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206872 kb
Host smart-3aa316ce-bad1-4139-ac95-940d835e6e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91804
4777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.918044777
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1408864798
Short name T775
Test name
Test status
Simulation time 23393695566 ps
CPU time 24.07 seconds
Started Jul 14 07:13:07 PM PDT 24
Finished Jul 14 07:13:48 PM PDT 24
Peak memory 206888 kb
Host smart-e6e1abe6-44ca-4a41-88b2-78f943869b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14088
64798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1408864798
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3561727478
Short name T1599
Test name
Test status
Simulation time 3277700206 ps
CPU time 3.82 seconds
Started Jul 14 07:13:09 PM PDT 24
Finished Jul 14 07:13:28 PM PDT 24
Peak memory 206932 kb
Host smart-16281326-3c26-4739-95a0-b2b63a3f8c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35617
27478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3561727478
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.4241589439
Short name T2536
Test name
Test status
Simulation time 11895375273 ps
CPU time 114.15 seconds
Started Jul 14 07:13:04 PM PDT 24
Finished Jul 14 07:15:15 PM PDT 24
Peak memory 207184 kb
Host smart-421064ed-d68f-4aa8-a853-08b4b8fbe199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42415
89439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.4241589439
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3939589521
Short name T1470
Test name
Test status
Simulation time 6591093891 ps
CPU time 45.44 seconds
Started Jul 14 07:13:04 PM PDT 24
Finished Jul 14 07:14:07 PM PDT 24
Peak memory 207036 kb
Host smart-c09f9900-ae72-4423-ba35-90150ba544fd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3939589521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3939589521
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3363843190
Short name T330
Test name
Test status
Simulation time 328892442 ps
CPU time 0.94 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206884 kb
Host smart-e4494783-cf73-47ec-9f10-510749e329f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3363843190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3363843190
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2034532955
Short name T2176
Test name
Test status
Simulation time 213905582 ps
CPU time 0.9 seconds
Started Jul 14 07:13:07 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206872 kb
Host smart-d7f18895-2b2a-435c-a382-c0dcb0373387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20345
32955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2034532955
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3034241718
Short name T1615
Test name
Test status
Simulation time 4675631048 ps
CPU time 127.95 seconds
Started Jul 14 07:13:03 PM PDT 24
Finished Jul 14 07:15:28 PM PDT 24
Peak memory 207048 kb
Host smart-04250490-57bf-4413-97cf-9db95aa6be37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30342
41718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3034241718
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1956242840
Short name T653
Test name
Test status
Simulation time 3045906600 ps
CPU time 77.23 seconds
Started Jul 14 07:13:04 PM PDT 24
Finished Jul 14 07:14:38 PM PDT 24
Peak memory 207068 kb
Host smart-3c44c8ce-6621-4de7-8209-84ccc97a7427
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1956242840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1956242840
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.4184693369
Short name T267
Test name
Test status
Simulation time 155624215 ps
CPU time 0.82 seconds
Started Jul 14 07:13:00 PM PDT 24
Finished Jul 14 07:13:19 PM PDT 24
Peak memory 207020 kb
Host smart-f8c232c4-0a7e-4fb9-bf9e-a85b738146cb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4184693369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.4184693369
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.81980455
Short name T1527
Test name
Test status
Simulation time 159689194 ps
CPU time 0.77 seconds
Started Jul 14 07:13:03 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206876 kb
Host smart-08882493-d85f-4403-bbc0-c0a03f165aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81980
455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.81980455
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.992097060
Short name T922
Test name
Test status
Simulation time 233990546 ps
CPU time 0.85 seconds
Started Jul 14 07:13:01 PM PDT 24
Finished Jul 14 07:13:20 PM PDT 24
Peak memory 206832 kb
Host smart-1a4c5ea0-80cf-488c-bc78-56f74c9cb078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99209
7060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.992097060
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.238612576
Short name T1805
Test name
Test status
Simulation time 223754254 ps
CPU time 0.92 seconds
Started Jul 14 07:13:06 PM PDT 24
Finished Jul 14 07:13:24 PM PDT 24
Peak memory 206888 kb
Host smart-db48a674-54ff-401b-950a-a8c884ab19cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861
2576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.238612576
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.483565
Short name T544
Test name
Test status
Simulation time 161370976 ps
CPU time 0.78 seconds
Started Jul 14 07:13:06 PM PDT 24
Finished Jul 14 07:13:23 PM PDT 24
Peak memory 206888 kb
Host smart-78964ea0-d248-43cb-8c8b-e5a2634e26b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48356
5 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.483565
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2102569050
Short name T2468
Test name
Test status
Simulation time 186119587 ps
CPU time 0.83 seconds
Started Jul 14 07:13:07 PM PDT 24
Finished Jul 14 07:13:24 PM PDT 24
Peak memory 206820 kb
Host smart-97c044e5-2231-4d3d-a6aa-a92dfb4d833d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
69050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2102569050
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1693537733
Short name T2263
Test name
Test status
Simulation time 167721607 ps
CPU time 0.84 seconds
Started Jul 14 07:13:05 PM PDT 24
Finished Jul 14 07:13:23 PM PDT 24
Peak memory 206840 kb
Host smart-fb9fc955-e129-4f0c-b05d-70aa327dfe05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16935
37733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1693537733
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2086936249
Short name T1903
Test name
Test status
Simulation time 244865446 ps
CPU time 0.93 seconds
Started Jul 14 07:13:00 PM PDT 24
Finished Jul 14 07:13:19 PM PDT 24
Peak memory 206896 kb
Host smart-06d8ed7c-0f2e-4c15-b1d7-91a6b233fad2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2086936249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2086936249
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.1358373855
Short name T1909
Test name
Test status
Simulation time 220045986 ps
CPU time 0.9 seconds
Started Jul 14 07:13:04 PM PDT 24
Finished Jul 14 07:13:22 PM PDT 24
Peak memory 206852 kb
Host smart-b92fd0cc-b145-4204-99db-8399f3abe252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13583
73855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.1358373855
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3330602902
Short name T1426
Test name
Test status
Simulation time 144319195 ps
CPU time 0.75 seconds
Started Jul 14 07:13:04 PM PDT 24
Finished Jul 14 07:13:22 PM PDT 24
Peak memory 206884 kb
Host smart-5acbde7f-3c4d-49df-bcc6-66f84569b736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33306
02902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3330602902
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3853007318
Short name T23
Test name
Test status
Simulation time 49531707 ps
CPU time 0.67 seconds
Started Jul 14 07:13:04 PM PDT 24
Finished Jul 14 07:13:22 PM PDT 24
Peak memory 206860 kb
Host smart-b28cee5d-40f9-4951-af02-177077866fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
07318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3853007318
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.638933629
Short name T1635
Test name
Test status
Simulation time 7341396787 ps
CPU time 15.51 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:39 PM PDT 24
Peak memory 207144 kb
Host smart-59757705-987b-4f9e-a34b-b8ee7aba1d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63893
3629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.638933629
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.4128520330
Short name T1746
Test name
Test status
Simulation time 152383635 ps
CPU time 0.82 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206840 kb
Host smart-3073cdb1-82f9-40be-8a5a-7efe0875a006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
20330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.4128520330
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1767346678
Short name T734
Test name
Test status
Simulation time 238877112 ps
CPU time 0.87 seconds
Started Jul 14 07:13:04 PM PDT 24
Finished Jul 14 07:13:22 PM PDT 24
Peak memory 206856 kb
Host smart-4d2a6a98-834e-4b37-befc-3330a8790f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17673
46678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1767346678
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3218191617
Short name T2526
Test name
Test status
Simulation time 13591308103 ps
CPU time 342.96 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:19:03 PM PDT 24
Peak memory 207180 kb
Host smart-5e93e153-1189-486b-a15f-51796842a54d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3218191617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3218191617
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.104514533
Short name T2333
Test name
Test status
Simulation time 11880584799 ps
CPU time 328.73 seconds
Started Jul 14 07:13:03 PM PDT 24
Finished Jul 14 07:18:49 PM PDT 24
Peak memory 207104 kb
Host smart-f4c79269-9006-496c-b511-b1558fa0a9cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=104514533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.104514533
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2866684422
Short name T976
Test name
Test status
Simulation time 12690279198 ps
CPU time 244.13 seconds
Started Jul 14 07:13:03 PM PDT 24
Finished Jul 14 07:17:25 PM PDT 24
Peak memory 207136 kb
Host smart-c094ae0e-3e21-40d7-b7fd-77a1aa315684
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2866684422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2866684422
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2556814060
Short name T1605
Test name
Test status
Simulation time 217629669 ps
CPU time 0.87 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206872 kb
Host smart-012bd360-7531-4398-ad49-92b7fceb8e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25568
14060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2556814060
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.358729443
Short name T778
Test name
Test status
Simulation time 192751032 ps
CPU time 0.96 seconds
Started Jul 14 07:13:01 PM PDT 24
Finished Jul 14 07:13:20 PM PDT 24
Peak memory 206872 kb
Host smart-5b6b722f-5bd4-4248-9c63-cfce0be21fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35872
9443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.358729443
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3707161205
Short name T1475
Test name
Test status
Simulation time 154214998 ps
CPU time 0.77 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206860 kb
Host smart-09c26360-eaf8-4975-9a90-c807413b13cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37071
61205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3707161205
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2875204814
Short name T72
Test name
Test status
Simulation time 213211984 ps
CPU time 0.82 seconds
Started Jul 14 07:13:03 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206828 kb
Host smart-7eafdf4e-1dbf-45bd-a14f-56b3cd86a52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28752
04814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2875204814
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.4185504208
Short name T35
Test name
Test status
Simulation time 638104176 ps
CPU time 1.39 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 224576 kb
Host smart-7e95cf21-b594-440b-9218-0165b5d5a20f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4185504208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.4185504208
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.1950051270
Short name T2021
Test name
Test status
Simulation time 421403215 ps
CPU time 1.23 seconds
Started Jul 14 07:13:07 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206824 kb
Host smart-51753c98-e6a9-4b25-bdb0-550caf1b2e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19500
51270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1950051270
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3853847161
Short name T1798
Test name
Test status
Simulation time 212162675 ps
CPU time 0.92 seconds
Started Jul 14 07:13:03 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206872 kb
Host smart-a49e0df3-c0d9-4f72-8149-20ac4cbf1953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38538
47161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3853847161
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1040904541
Short name T1274
Test name
Test status
Simulation time 161460712 ps
CPU time 0.79 seconds
Started Jul 14 07:13:02 PM PDT 24
Finished Jul 14 07:13:21 PM PDT 24
Peak memory 206836 kb
Host smart-4ab2dada-5821-4c67-82f9-b74605456381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10409
04541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1040904541
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1869726311
Short name T1516
Test name
Test status
Simulation time 148270356 ps
CPU time 0.75 seconds
Started Jul 14 07:13:06 PM PDT 24
Finished Jul 14 07:13:23 PM PDT 24
Peak memory 206892 kb
Host smart-f19cd802-b6f1-4d94-b6a3-73a9d4d48cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18697
26311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1869726311
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3488326539
Short name T2315
Test name
Test status
Simulation time 228088584 ps
CPU time 0.92 seconds
Started Jul 14 07:13:01 PM PDT 24
Finished Jul 14 07:13:20 PM PDT 24
Peak memory 206860 kb
Host smart-ff2b7dc8-7bba-4c9f-a6c7-79c0d0f2f285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34883
26539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3488326539
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.992173611
Short name T408
Test name
Test status
Simulation time 5839818166 ps
CPU time 165.41 seconds
Started Jul 14 07:13:04 PM PDT 24
Finished Jul 14 07:16:07 PM PDT 24
Peak memory 207088 kb
Host smart-2165f793-c0d3-4f14-81ce-910366ea7132
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=992173611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.992173611
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1150388911
Short name T2416
Test name
Test status
Simulation time 169234403 ps
CPU time 0.78 seconds
Started Jul 14 07:13:10 PM PDT 24
Finished Jul 14 07:13:26 PM PDT 24
Peak memory 206860 kb
Host smart-244ca84e-bbb8-49df-b669-6d6cf835b939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
88911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1150388911
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2918895955
Short name T2411
Test name
Test status
Simulation time 154659912 ps
CPU time 0.81 seconds
Started Jul 14 07:13:07 PM PDT 24
Finished Jul 14 07:13:24 PM PDT 24
Peak memory 206844 kb
Host smart-94045e5d-4288-44e0-a754-80f3a0fe8e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29188
95955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2918895955
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2807269521
Short name T2356
Test name
Test status
Simulation time 1325460917 ps
CPU time 2.59 seconds
Started Jul 14 07:13:09 PM PDT 24
Finished Jul 14 07:13:27 PM PDT 24
Peak memory 207048 kb
Host smart-5e5382a9-65ee-4b43-9375-9ac84c4f95ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072
69521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2807269521
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2912539103
Short name T825
Test name
Test status
Simulation time 5090800118 ps
CPU time 131.69 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:15:35 PM PDT 24
Peak memory 207040 kb
Host smart-163bb311-4bc2-4727-b536-22b33b3da534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29125
39103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2912539103
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.681634155
Short name T657
Test name
Test status
Simulation time 34117788 ps
CPU time 0.72 seconds
Started Jul 14 07:20:36 PM PDT 24
Finished Jul 14 07:21:00 PM PDT 24
Peak memory 206904 kb
Host smart-6bedb154-532a-4b85-9a7c-d7eb735cc812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=681634155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.681634155
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3732113910
Short name T1160
Test name
Test status
Simulation time 4343020541 ps
CPU time 4.88 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:21:00 PM PDT 24
Peak memory 206920 kb
Host smart-212d945f-0262-40b5-9532-8bddf3d99b7d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3732113910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3732113910
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2047714650
Short name T1116
Test name
Test status
Simulation time 13290103777 ps
CPU time 11.93 seconds
Started Jul 14 07:20:28 PM PDT 24
Finished Jul 14 07:21:05 PM PDT 24
Peak memory 207100 kb
Host smart-5e334068-8350-4102-8e62-1dc15fbe4446
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2047714650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2047714650
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2145093017
Short name T1389
Test name
Test status
Simulation time 23392513591 ps
CPU time 24.08 seconds
Started Jul 14 07:20:26 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 207084 kb
Host smart-bc5ee0f6-b3d2-4804-abf2-ad7b52ea0460
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2145093017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.2145093017
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1443778763
Short name T313
Test name
Test status
Simulation time 188558532 ps
CPU time 0.85 seconds
Started Jul 14 07:20:25 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206840 kb
Host smart-ed24d422-1098-4350-b86c-093cd8a6f70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14437
78763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1443778763
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.842689215
Short name T1051
Test name
Test status
Simulation time 213966997 ps
CPU time 0.87 seconds
Started Jul 14 07:20:26 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 206864 kb
Host smart-7f86354f-6439-4f04-a18a-c9393cd05e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84268
9215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.842689215
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2502347541
Short name T1005
Test name
Test status
Simulation time 569422522 ps
CPU time 1.57 seconds
Started Jul 14 07:20:24 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 207024 kb
Host smart-f91121b4-b023-4a6f-a9a3-e6c154c4d233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25023
47541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2502347541
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3477256186
Short name T2275
Test name
Test status
Simulation time 765326045 ps
CPU time 1.91 seconds
Started Jul 14 07:20:25 PM PDT 24
Finished Jul 14 07:20:52 PM PDT 24
Peak memory 207060 kb
Host smart-af8dca49-c9ef-41e7-ad72-1c99bc5f5e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34772
56186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3477256186
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3714047668
Short name T1559
Test name
Test status
Simulation time 15474956098 ps
CPU time 31.3 seconds
Started Jul 14 07:20:28 PM PDT 24
Finished Jul 14 07:21:24 PM PDT 24
Peak memory 207160 kb
Host smart-0111bbbe-f4df-4ae3-901c-ae5a1e58794a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37140
47668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3714047668
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2411846160
Short name T1241
Test name
Test status
Simulation time 347203316 ps
CPU time 1.17 seconds
Started Jul 14 07:20:26 PM PDT 24
Finished Jul 14 07:20:52 PM PDT 24
Peak memory 206860 kb
Host smart-7a54f4f4-b952-4da7-9810-75de91a47eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24118
46160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2411846160
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1307534911
Short name T1799
Test name
Test status
Simulation time 159465730 ps
CPU time 0.75 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206872 kb
Host smart-95be999d-39c3-4ffb-915b-8f677b28577c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13075
34911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1307534911
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.530360450
Short name T681
Test name
Test status
Simulation time 38608029 ps
CPU time 0.67 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:54 PM PDT 24
Peak memory 206892 kb
Host smart-c7da222b-6c03-496f-991e-5fcd213fd01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53036
0450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.530360450
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2772781039
Short name T134
Test name
Test status
Simulation time 945594568 ps
CPU time 2.04 seconds
Started Jul 14 07:20:24 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 207040 kb
Host smart-a6f4081e-cbdb-4e7d-9c60-fbb7433841a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27727
81039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2772781039
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.353103672
Short name T1942
Test name
Test status
Simulation time 431352792 ps
CPU time 2.34 seconds
Started Jul 14 07:20:28 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 207084 kb
Host smart-ebbbcf30-3ce2-46dd-b54e-9d761bc42713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35310
3672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.353103672
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.4092276518
Short name T782
Test name
Test status
Simulation time 204074383 ps
CPU time 0.92 seconds
Started Jul 14 07:20:23 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206860 kb
Host smart-ac05c8e8-029f-4656-b023-866c8c5c3c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
76518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.4092276518
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.4139355619
Short name T1761
Test name
Test status
Simulation time 137899462 ps
CPU time 0.77 seconds
Started Jul 14 07:20:33 PM PDT 24
Finished Jul 14 07:20:58 PM PDT 24
Peak memory 206788 kb
Host smart-cc5bc40d-d934-49fb-8be4-c6904bbefd1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41393
55619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.4139355619
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3764202958
Short name T2091
Test name
Test status
Simulation time 246826202 ps
CPU time 0.94 seconds
Started Jul 14 07:20:35 PM PDT 24
Finished Jul 14 07:21:00 PM PDT 24
Peak memory 206840 kb
Host smart-3fc926b8-80df-42b3-8cb0-c40f25db56c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37642
02958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3764202958
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.4134032334
Short name T1649
Test name
Test status
Simulation time 6660651064 ps
CPU time 22.33 seconds
Started Jul 14 07:20:38 PM PDT 24
Finished Jul 14 07:21:24 PM PDT 24
Peak memory 207092 kb
Host smart-bff4c542-5700-4178-b2ea-e55ecd08daf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41340
32334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.4134032334
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.4123651157
Short name T1484
Test name
Test status
Simulation time 223785727 ps
CPU time 0.92 seconds
Started Jul 14 07:20:29 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206856 kb
Host smart-af3c1630-0ed0-41ec-927b-d9c732a61963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41236
51157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.4123651157
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3495289896
Short name T554
Test name
Test status
Simulation time 23278989024 ps
CPU time 23.54 seconds
Started Jul 14 07:20:32 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206876 kb
Host smart-e6207774-0ea9-43d5-b99e-e0d3fed003b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34952
89896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3495289896
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3950653132
Short name T1226
Test name
Test status
Simulation time 3262285315 ps
CPU time 4.39 seconds
Started Jul 14 07:20:38 PM PDT 24
Finished Jul 14 07:21:06 PM PDT 24
Peak memory 206908 kb
Host smart-757e8e74-2129-42df-8b40-19274989dac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39506
53132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3950653132
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.3086549118
Short name T1879
Test name
Test status
Simulation time 10273380781 ps
CPU time 283.47 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:25:38 PM PDT 24
Peak memory 207128 kb
Host smart-ac3da5c1-8b49-43a4-9ffd-eee83d2d33b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865
49118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.3086549118
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2998262565
Short name T1170
Test name
Test status
Simulation time 3954672418 ps
CPU time 38.39 seconds
Started Jul 14 07:20:35 PM PDT 24
Finished Jul 14 07:21:38 PM PDT 24
Peak memory 207136 kb
Host smart-bcb957ed-548e-43be-b4b2-eb4c8e7c4f62
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2998262565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2998262565
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2761110649
Short name T1704
Test name
Test status
Simulation time 247391972 ps
CPU time 0.87 seconds
Started Jul 14 07:20:33 PM PDT 24
Finished Jul 14 07:20:59 PM PDT 24
Peak memory 206892 kb
Host smart-5bbc9ec4-1e78-4a54-828e-2c46735a92e5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2761110649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2761110649
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3301850996
Short name T1300
Test name
Test status
Simulation time 191755646 ps
CPU time 0.89 seconds
Started Jul 14 07:20:31 PM PDT 24
Finished Jul 14 07:20:57 PM PDT 24
Peak memory 206892 kb
Host smart-916e05f0-4a61-4fb0-9f93-61330b48dca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33018
50996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3301850996
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1940521277
Short name T869
Test name
Test status
Simulation time 6145602046 ps
CPU time 43.57 seconds
Started Jul 14 07:20:31 PM PDT 24
Finished Jul 14 07:21:38 PM PDT 24
Peak memory 207136 kb
Host smart-ad1f08b7-d5fe-485f-adec-af35cf1202b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19405
21277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1940521277
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.402391677
Short name T410
Test name
Test status
Simulation time 7340829196 ps
CPU time 51.26 seconds
Started Jul 14 07:20:31 PM PDT 24
Finished Jul 14 07:21:48 PM PDT 24
Peak memory 207132 kb
Host smart-a50b3fca-9083-4a38-98a7-a8ad83098795
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=402391677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.402391677
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.801939551
Short name T755
Test name
Test status
Simulation time 166953738 ps
CPU time 0.82 seconds
Started Jul 14 07:20:35 PM PDT 24
Finished Jul 14 07:20:59 PM PDT 24
Peak memory 206864 kb
Host smart-b69c3a5f-eb45-4471-bad2-1d2138386751
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=801939551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.801939551
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1149418218
Short name T737
Test name
Test status
Simulation time 153632627 ps
CPU time 0.76 seconds
Started Jul 14 07:20:28 PM PDT 24
Finished Jul 14 07:20:54 PM PDT 24
Peak memory 206856 kb
Host smart-5579543f-e22e-4c1c-b7bd-6b3d8296bd49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11494
18218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1149418218
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.982053111
Short name T1498
Test name
Test status
Simulation time 221901934 ps
CPU time 0.95 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:20:56 PM PDT 24
Peak memory 206832 kb
Host smart-570546f2-4822-48f5-9a90-5153ea540754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98205
3111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.982053111
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.131852742
Short name T1491
Test name
Test status
Simulation time 186286324 ps
CPU time 0.79 seconds
Started Jul 14 07:20:31 PM PDT 24
Finished Jul 14 07:20:57 PM PDT 24
Peak memory 206868 kb
Host smart-a575b91b-51a3-4991-b565-bf5674d5552e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185
2742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.131852742
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2564907741
Short name T336
Test name
Test status
Simulation time 181145167 ps
CPU time 0.79 seconds
Started Jul 14 07:20:33 PM PDT 24
Finished Jul 14 07:20:58 PM PDT 24
Peak memory 206852 kb
Host smart-50735e21-9cb8-48ed-9511-c6d667e60c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
07741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2564907741
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.31093987
Short name T569
Test name
Test status
Simulation time 165509425 ps
CPU time 0.79 seconds
Started Jul 14 07:20:37 PM PDT 24
Finished Jul 14 07:21:02 PM PDT 24
Peak memory 206848 kb
Host smart-bd94de73-e0f5-4ea6-be27-7c9ff6cd7467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31093
987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.31093987
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3017883061
Short name T2434
Test name
Test status
Simulation time 156340271 ps
CPU time 0.8 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:20:56 PM PDT 24
Peak memory 206884 kb
Host smart-86a049dc-c9a9-45b0-a3f8-a2c079a96e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30178
83061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3017883061
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2585533725
Short name T1958
Test name
Test status
Simulation time 199501779 ps
CPU time 0.92 seconds
Started Jul 14 07:20:33 PM PDT 24
Finished Jul 14 07:20:59 PM PDT 24
Peak memory 207024 kb
Host smart-cdd20995-3fde-4530-be3d-3ae3b01e95c3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2585533725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2585533725
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2485218541
Short name T1462
Test name
Test status
Simulation time 177863307 ps
CPU time 0.87 seconds
Started Jul 14 07:20:35 PM PDT 24
Finished Jul 14 07:21:00 PM PDT 24
Peak memory 206872 kb
Host smart-358f4146-d5e6-4619-9cc2-421051567f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24852
18541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2485218541
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2463991835
Short name T853
Test name
Test status
Simulation time 62875394 ps
CPU time 0.7 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206848 kb
Host smart-41d96f4b-ac6d-4a0d-a284-9e601b6edb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24639
91835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2463991835
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1169340045
Short name T1606
Test name
Test status
Simulation time 8042769423 ps
CPU time 17.8 seconds
Started Jul 14 07:20:32 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 207100 kb
Host smart-f74a4ef1-746c-478b-87c8-138adf12adad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693
40045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1169340045
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1244677455
Short name T644
Test name
Test status
Simulation time 198689060 ps
CPU time 0.84 seconds
Started Jul 14 07:20:35 PM PDT 24
Finished Jul 14 07:21:00 PM PDT 24
Peak memory 206864 kb
Host smart-2c09ee60-4ebd-4e9e-9f95-d5a2c4f61eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12446
77455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1244677455
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.521014587
Short name T2386
Test name
Test status
Simulation time 159713978 ps
CPU time 0.82 seconds
Started Jul 14 07:20:37 PM PDT 24
Finished Jul 14 07:21:02 PM PDT 24
Peak memory 206840 kb
Host smart-68ded793-2605-41e6-aa5d-9d6be73133f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52101
4587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.521014587
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.3495764784
Short name T432
Test name
Test status
Simulation time 183985095 ps
CPU time 0.83 seconds
Started Jul 14 07:20:30 PM PDT 24
Finished Jul 14 07:20:55 PM PDT 24
Peak memory 206868 kb
Host smart-c1a78a4d-c922-4e63-b9ce-48d19bad611d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34957
64784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.3495764784
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2200205875
Short name T665
Test name
Test status
Simulation time 204430059 ps
CPU time 0.88 seconds
Started Jul 14 07:20:35 PM PDT 24
Finished Jul 14 07:21:00 PM PDT 24
Peak memory 206840 kb
Host smart-3ef62449-f966-4e57-95eb-d7c398710778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22002
05875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2200205875
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3074883035
Short name T2379
Test name
Test status
Simulation time 140340299 ps
CPU time 0.75 seconds
Started Jul 14 07:20:53 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 207040 kb
Host smart-217e97c3-872a-429e-903d-defccbe16d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30748
83035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3074883035
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2451696866
Short name T2643
Test name
Test status
Simulation time 166746439 ps
CPU time 0.79 seconds
Started Jul 14 07:20:42 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 206888 kb
Host smart-56a693c7-1fa4-4f70-93b2-57bbe45fe25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24516
96866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2451696866
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2183031021
Short name T1072
Test name
Test status
Simulation time 147438074 ps
CPU time 0.76 seconds
Started Jul 14 07:20:44 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 206868 kb
Host smart-2cb543c3-895f-430f-9f80-7ac86a2e8652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21830
31021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2183031021
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1265131190
Short name T2549
Test name
Test status
Simulation time 185357267 ps
CPU time 0.9 seconds
Started Jul 14 07:20:46 PM PDT 24
Finished Jul 14 07:21:09 PM PDT 24
Peak memory 206804 kb
Host smart-b31ff2e7-d3c6-44bc-bb55-7bd04969478c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12651
31190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1265131190
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2249562567
Short name T1715
Test name
Test status
Simulation time 5607421722 ps
CPU time 40.75 seconds
Started Jul 14 07:20:42 PM PDT 24
Finished Jul 14 07:21:46 PM PDT 24
Peak memory 207108 kb
Host smart-e4e18fa0-4fda-4ccd-824a-22639eb43289
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2249562567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2249562567
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.731626310
Short name T1849
Test name
Test status
Simulation time 204043831 ps
CPU time 0.79 seconds
Started Jul 14 07:20:38 PM PDT 24
Finished Jul 14 07:21:02 PM PDT 24
Peak memory 206828 kb
Host smart-f7632b08-a2e9-4c20-9a95-7dd25c6f5e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73162
6310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.731626310
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2190868859
Short name T688
Test name
Test status
Simulation time 189088827 ps
CPU time 0.8 seconds
Started Jul 14 07:20:38 PM PDT 24
Finished Jul 14 07:21:02 PM PDT 24
Peak memory 206880 kb
Host smart-d2c5007d-e636-46fd-82da-aa0f0c00fdc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21908
68859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2190868859
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.471236911
Short name T936
Test name
Test status
Simulation time 704569057 ps
CPU time 1.61 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 207068 kb
Host smart-9aa52fe2-6201-42f4-bb6e-4c687d079928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47123
6911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.471236911
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3971041544
Short name T2455
Test name
Test status
Simulation time 4334327074 ps
CPU time 120.42 seconds
Started Jul 14 07:20:36 PM PDT 24
Finished Jul 14 07:23:00 PM PDT 24
Peak memory 207036 kb
Host smart-e2089abb-2af2-42b6-ac41-30e93c29a061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39710
41544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3971041544
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.3610922540
Short name T1528
Test name
Test status
Simulation time 195340354 ps
CPU time 0.8 seconds
Started Jul 14 07:20:25 PM PDT 24
Finished Jul 14 07:20:50 PM PDT 24
Peak memory 206840 kb
Host smart-b20f5147-e41c-4974-bdd7-a92086b053de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
22540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_host_handshake.3610922540
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1034362226
Short name T1922
Test name
Test status
Simulation time 47284102 ps
CPU time 0.67 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206936 kb
Host smart-7d2e1a58-1689-4151-875b-e1650091c31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1034362226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1034362226
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3104013835
Short name T1837
Test name
Test status
Simulation time 4370887581 ps
CPU time 4.79 seconds
Started Jul 14 07:20:39 PM PDT 24
Finished Jul 14 07:21:08 PM PDT 24
Peak memory 206888 kb
Host smart-bdfd6d90-5d38-4376-b4a6-b6bb08dd592b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3104013835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3104013835
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2778007364
Short name T2213
Test name
Test status
Simulation time 13365535280 ps
CPU time 11.89 seconds
Started Jul 14 07:20:40 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206912 kb
Host smart-134bb73f-aacd-400f-a4a8-29732a5babea
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2778007364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2778007364
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.734447978
Short name T1893
Test name
Test status
Simulation time 23335164112 ps
CPU time 23.76 seconds
Started Jul 14 07:20:41 PM PDT 24
Finished Jul 14 07:21:28 PM PDT 24
Peak memory 206908 kb
Host smart-927a80ca-8b00-4060-8918-a4a3bfb18fff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=734447978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.734447978
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3936662596
Short name T2654
Test name
Test status
Simulation time 165619758 ps
CPU time 0.79 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 206880 kb
Host smart-747a3b21-d2a4-4a43-899b-cf78dc5beaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39366
62596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3936662596
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.541637666
Short name T830
Test name
Test status
Simulation time 175744496 ps
CPU time 0.8 seconds
Started Jul 14 07:20:39 PM PDT 24
Finished Jul 14 07:21:03 PM PDT 24
Peak memory 206848 kb
Host smart-28f425d0-324d-46ce-8d72-51bce903e1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54163
7666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.541637666
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2933089772
Short name T1541
Test name
Test status
Simulation time 278273225 ps
CPU time 1.03 seconds
Started Jul 14 07:20:35 PM PDT 24
Finished Jul 14 07:20:59 PM PDT 24
Peak memory 206880 kb
Host smart-1359a715-286f-424c-af02-9af826628500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29330
89772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2933089772
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.687870315
Short name T1598
Test name
Test status
Simulation time 418897387 ps
CPU time 1.24 seconds
Started Jul 14 07:20:40 PM PDT 24
Finished Jul 14 07:21:04 PM PDT 24
Peak memory 206864 kb
Host smart-78ad3c3d-378a-468f-bb7a-0df76b93a1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68787
0315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.687870315
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2140374971
Short name T1359
Test name
Test status
Simulation time 21484413009 ps
CPU time 38.7 seconds
Started Jul 14 07:20:35 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 207108 kb
Host smart-9b754c82-d4fa-4158-b1a4-437d78c82553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21403
74971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2140374971
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3118368140
Short name T334
Test name
Test status
Simulation time 429175801 ps
CPU time 1.29 seconds
Started Jul 14 07:20:38 PM PDT 24
Finished Jul 14 07:21:03 PM PDT 24
Peak memory 206852 kb
Host smart-851d3c76-83fa-4952-956e-43bd39b2f1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
68140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3118368140
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.4055666600
Short name T46
Test name
Test status
Simulation time 139229231 ps
CPU time 0.73 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206828 kb
Host smart-61d7b9c5-37c5-4ae3-8c84-4c713cf563a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40556
66600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.4055666600
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3441156986
Short name T2055
Test name
Test status
Simulation time 61835282 ps
CPU time 0.74 seconds
Started Jul 14 07:20:48 PM PDT 24
Finished Jul 14 07:21:10 PM PDT 24
Peak memory 206868 kb
Host smart-f1ea6ba3-7f3f-4c6a-8e89-0cec5308e74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34411
56986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3441156986
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3408197366
Short name T1718
Test name
Test status
Simulation time 839073966 ps
CPU time 1.98 seconds
Started Jul 14 07:20:39 PM PDT 24
Finished Jul 14 07:21:04 PM PDT 24
Peak memory 207032 kb
Host smart-2e0530c3-7d58-4761-a191-ff383f404431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34081
97366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3408197366
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1365324532
Short name T1621
Test name
Test status
Simulation time 388351539 ps
CPU time 2.29 seconds
Started Jul 14 07:20:44 PM PDT 24
Finished Jul 14 07:21:09 PM PDT 24
Peak memory 207000 kb
Host smart-8aef02d8-44e4-4d34-8f72-05d1641c8589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653
24532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1365324532
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2836345412
Short name T1200
Test name
Test status
Simulation time 173738990 ps
CPU time 0.87 seconds
Started Jul 14 07:20:39 PM PDT 24
Finished Jul 14 07:21:03 PM PDT 24
Peak memory 206884 kb
Host smart-162067c3-2fdb-432b-8687-8cb11847e44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28363
45412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2836345412
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.671408908
Short name T655
Test name
Test status
Simulation time 174134955 ps
CPU time 0.78 seconds
Started Jul 14 07:20:36 PM PDT 24
Finished Jul 14 07:21:00 PM PDT 24
Peak memory 206876 kb
Host smart-88c61099-a4ff-42c7-99cb-7dc9479f9419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67140
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.671408908
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3118275366
Short name T1842
Test name
Test status
Simulation time 275255736 ps
CPU time 0.93 seconds
Started Jul 14 07:20:39 PM PDT 24
Finished Jul 14 07:21:04 PM PDT 24
Peak memory 206812 kb
Host smart-f0cc257e-2d00-4c01-baa3-f7f1f2eebb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31182
75366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3118275366
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2081611180
Short name T2267
Test name
Test status
Simulation time 8315128611 ps
CPU time 240.34 seconds
Started Jul 14 07:20:48 PM PDT 24
Finished Jul 14 07:25:09 PM PDT 24
Peak memory 207236 kb
Host smart-fbaae2c6-f332-48c0-8d9c-e29cc2d351a5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2081611180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2081611180
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2564377881
Short name T2268
Test name
Test status
Simulation time 9546756189 ps
CPU time 80.57 seconds
Started Jul 14 07:20:47 PM PDT 24
Finished Jul 14 07:22:29 PM PDT 24
Peak memory 207128 kb
Host smart-029a01fe-fda5-4589-9148-dc1d6aa7f5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25643
77881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2564377881
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2623050892
Short name T975
Test name
Test status
Simulation time 201473738 ps
CPU time 0.88 seconds
Started Jul 14 07:20:38 PM PDT 24
Finished Jul 14 07:21:03 PM PDT 24
Peak memory 206860 kb
Host smart-a6f007e7-cd08-48c7-9499-f459e358f950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26230
50892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2623050892
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3131044724
Short name T390
Test name
Test status
Simulation time 23325292364 ps
CPU time 26.82 seconds
Started Jul 14 07:20:38 PM PDT 24
Finished Jul 14 07:21:28 PM PDT 24
Peak memory 206912 kb
Host smart-3d939fd7-9ead-4538-a331-f7c7db88006b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
44724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3131044724
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2284526080
Short name T2157
Test name
Test status
Simulation time 3293842253 ps
CPU time 3.45 seconds
Started Jul 14 07:20:40 PM PDT 24
Finished Jul 14 07:21:06 PM PDT 24
Peak memory 206908 kb
Host smart-6c298428-3aee-47a8-b3d0-6644fb381cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22845
26080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2284526080
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3288612417
Short name T2428
Test name
Test status
Simulation time 11943725822 ps
CPU time 89.16 seconds
Started Jul 14 07:20:40 PM PDT 24
Finished Jul 14 07:22:34 PM PDT 24
Peak memory 207096 kb
Host smart-9cecdff3-d12b-451c-a796-6fb9379e45dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32886
12417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3288612417
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1932590423
Short name T458
Test name
Test status
Simulation time 6118683145 ps
CPU time 55.1 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:22:06 PM PDT 24
Peak memory 206944 kb
Host smart-42c0bb91-8167-4c98-a55d-85d3c57344d5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1932590423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1932590423
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1430261869
Short name T1975
Test name
Test status
Simulation time 252581839 ps
CPU time 0.93 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206896 kb
Host smart-42a18bf8-f861-425d-aded-75fb694b092c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1430261869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1430261869
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.816593174
Short name T727
Test name
Test status
Simulation time 194230015 ps
CPU time 0.89 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206856 kb
Host smart-42bcaf3f-34ca-493e-9646-4660b8c9d6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81659
3174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.816593174
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.4112775665
Short name T1741
Test name
Test status
Simulation time 4666626329 ps
CPU time 32.28 seconds
Started Jul 14 07:20:42 PM PDT 24
Finished Jul 14 07:21:38 PM PDT 24
Peak memory 207076 kb
Host smart-bdee139e-e87c-4243-887f-e4a758375aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41127
75665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.4112775665
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.899665497
Short name T2516
Test name
Test status
Simulation time 5807931873 ps
CPU time 55.91 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:22:06 PM PDT 24
Peak memory 207076 kb
Host smart-82fca868-1d09-41b7-8f16-a548b0bb24d5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=899665497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.899665497
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.93872793
Short name T797
Test name
Test status
Simulation time 172052152 ps
CPU time 0.81 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206872 kb
Host smart-aa451fc5-afd6-4e16-89c2-a2c46b005927
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=93872793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.93872793
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3838937237
Short name T2034
Test name
Test status
Simulation time 220340366 ps
CPU time 0.88 seconds
Started Jul 14 07:20:47 PM PDT 24
Finished Jul 14 07:21:09 PM PDT 24
Peak memory 206880 kb
Host smart-7a07a649-5cc2-428d-8b23-c398c060b815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38389
37237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3838937237
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3133919271
Short name T1119
Test name
Test status
Simulation time 203435218 ps
CPU time 0.85 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206888 kb
Host smart-11c97f96-501f-404d-bd70-d2ed57e57ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31339
19271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3133919271
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1029732885
Short name T2401
Test name
Test status
Simulation time 178613137 ps
CPU time 0.87 seconds
Started Jul 14 07:21:15 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 206876 kb
Host smart-a98b74f5-aa1d-44e7-8360-5623729b88fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10297
32885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1029732885
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2029775760
Short name T724
Test name
Test status
Simulation time 197655280 ps
CPU time 0.87 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 206868 kb
Host smart-64cc0a39-c7da-4400-b1c5-1762a4d13339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20297
75760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2029775760
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3737693242
Short name T2572
Test name
Test status
Simulation time 172009974 ps
CPU time 0.84 seconds
Started Jul 14 07:20:56 PM PDT 24
Finished Jul 14 07:21:17 PM PDT 24
Peak memory 206872 kb
Host smart-2e7daab2-05d2-4835-960f-75c55ac621f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37376
93242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3737693242
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3592782896
Short name T2109
Test name
Test status
Simulation time 155794199 ps
CPU time 0.82 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206860 kb
Host smart-be1e2113-d333-40a6-9e82-1cc0e58ba114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35927
82896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3592782896
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3342825688
Short name T1693
Test name
Test status
Simulation time 260245528 ps
CPU time 0.94 seconds
Started Jul 14 07:20:53 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206884 kb
Host smart-0b33a691-ac21-4519-9754-1a84882f2ba9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3342825688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3342825688
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.996113439
Short name T191
Test name
Test status
Simulation time 140717109 ps
CPU time 0.78 seconds
Started Jul 14 07:20:47 PM PDT 24
Finished Jul 14 07:21:09 PM PDT 24
Peak memory 206828 kb
Host smart-f3791b73-9e36-4481-b666-a1715b97a486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99611
3439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.996113439
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3893806312
Short name T559
Test name
Test status
Simulation time 115303716 ps
CPU time 0.7 seconds
Started Jul 14 07:20:44 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 206864 kb
Host smart-f6c6a4b4-2668-4cfa-8a27-4f681adf41b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38938
06312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3893806312
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3507633282
Short name T1299
Test name
Test status
Simulation time 15787080823 ps
CPU time 39.51 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:51 PM PDT 24
Peak memory 207104 kb
Host smart-ce0c7f8b-df7d-42ef-9b68-068a5365bf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35076
33282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3507633282
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1251851504
Short name T2262
Test name
Test status
Simulation time 182608926 ps
CPU time 0.83 seconds
Started Jul 14 07:21:09 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206856 kb
Host smart-1a31118b-2006-44ee-af11-800639bb108b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12518
51504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1251851504
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.195086620
Short name T1068
Test name
Test status
Simulation time 189397685 ps
CPU time 0.8 seconds
Started Jul 14 07:20:57 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 206880 kb
Host smart-994d0a68-f35f-4380-8677-1532aaeea7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19508
6620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.195086620
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1687065111
Short name T754
Test name
Test status
Simulation time 200530316 ps
CPU time 0.88 seconds
Started Jul 14 07:20:48 PM PDT 24
Finished Jul 14 07:21:10 PM PDT 24
Peak memory 206872 kb
Host smart-8d019011-c41a-486d-94db-92c86948f25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16870
65111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1687065111
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3018384054
Short name T1861
Test name
Test status
Simulation time 161169358 ps
CPU time 0.79 seconds
Started Jul 14 07:20:51 PM PDT 24
Finished Jul 14 07:21:13 PM PDT 24
Peak memory 206860 kb
Host smart-7497b468-a227-458e-a156-a3c284e03445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30183
84054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3018384054
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2844748162
Short name T1179
Test name
Test status
Simulation time 173003833 ps
CPU time 0.79 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206880 kb
Host smart-1e87dc22-6e10-4fc7-baa6-929e20f09f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28447
48162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2844748162
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1019619880
Short name T324
Test name
Test status
Simulation time 149690697 ps
CPU time 0.79 seconds
Started Jul 14 07:20:43 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 206864 kb
Host smart-352488e8-e902-4fc5-a077-361b864f25c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10196
19880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1019619880
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2752524078
Short name T982
Test name
Test status
Simulation time 149501807 ps
CPU time 0.76 seconds
Started Jul 14 07:20:48 PM PDT 24
Finished Jul 14 07:21:10 PM PDT 24
Peak memory 206828 kb
Host smart-e26b8944-dc2f-4eaa-b162-e6c422c23d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
24078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2752524078
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.66153392
Short name T2739
Test name
Test status
Simulation time 231495962 ps
CPU time 0.95 seconds
Started Jul 14 07:20:52 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 206876 kb
Host smart-c943640b-33a5-454c-bb75-9daf8bc232df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66153
392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.66153392
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2051395868
Short name T2112
Test name
Test status
Simulation time 6644272124 ps
CPU time 49.22 seconds
Started Jul 14 07:20:51 PM PDT 24
Finished Jul 14 07:22:01 PM PDT 24
Peak memory 207208 kb
Host smart-343d8726-fb23-47bf-a2ad-80ddbc1b8528
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2051395868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2051395868
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2163174351
Short name T2695
Test name
Test status
Simulation time 182725874 ps
CPU time 0.87 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206884 kb
Host smart-cf9238a3-818d-487b-b704-df70a15987c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
74351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2163174351
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3958599746
Short name T444
Test name
Test status
Simulation time 165339641 ps
CPU time 0.82 seconds
Started Jul 14 07:20:43 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 206888 kb
Host smart-d37442af-62cc-4000-8b81-43a0ad467e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
99746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3958599746
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.1945851618
Short name T1807
Test name
Test status
Simulation time 709005008 ps
CPU time 1.65 seconds
Started Jul 14 07:20:43 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 207052 kb
Host smart-230a0f07-99af-4eaa-a307-36346c4359cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19458
51618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.1945851618
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.703599275
Short name T2148
Test name
Test status
Simulation time 7147808254 ps
CPU time 63.84 seconds
Started Jul 14 07:20:53 PM PDT 24
Finished Jul 14 07:22:17 PM PDT 24
Peak memory 207120 kb
Host smart-75166169-45be-4c00-ac16-9a0a90fcceed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70359
9275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.703599275
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1287110802
Short name T698
Test name
Test status
Simulation time 62895768 ps
CPU time 0.72 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206928 kb
Host smart-68d6430d-c0f6-48bf-a2e0-5ca0bf900cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1287110802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1287110802
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.47376476
Short name T502
Test name
Test status
Simulation time 4138122232 ps
CPU time 5.64 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:16 PM PDT 24
Peak memory 207116 kb
Host smart-f81ac506-e05b-4a93-99fe-963db6f23e48
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=47376476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.47376476
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1697095524
Short name T1539
Test name
Test status
Simulation time 13401758951 ps
CPU time 13.45 seconds
Started Jul 14 07:20:55 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 206952 kb
Host smart-cba23a55-61ec-472b-bf28-20b7f7061cef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1697095524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1697095524
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.860731908
Short name T2452
Test name
Test status
Simulation time 23414061022 ps
CPU time 23.91 seconds
Started Jul 14 07:20:53 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 206952 kb
Host smart-07541155-ed68-462b-b1a7-81b3f4687d9b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=860731908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.860731908
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.634905915
Short name T322
Test name
Test status
Simulation time 152991362 ps
CPU time 0.82 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 206844 kb
Host smart-5afadade-3961-44f7-824d-1adb24b5db88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63490
5915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.634905915
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2819954784
Short name T1499
Test name
Test status
Simulation time 143945693 ps
CPU time 0.75 seconds
Started Jul 14 07:20:52 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 206856 kb
Host smart-37ce706d-9f69-4e49-85f2-810d32909668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28199
54784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2819954784
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2556413912
Short name T2682
Test name
Test status
Simulation time 198195573 ps
CPU time 0.84 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 206880 kb
Host smart-2d906b6b-669e-441b-9b56-8d3e9ed8ebd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25564
13912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2556413912
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1929594081
Short name T2133
Test name
Test status
Simulation time 294502093 ps
CPU time 0.93 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206772 kb
Host smart-893a63e7-0d62-4275-9693-e8342e517e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19295
94081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1929594081
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.2152554463
Short name T174
Test name
Test status
Simulation time 12871372920 ps
CPU time 22.76 seconds
Started Jul 14 07:20:47 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 207068 kb
Host smart-6414e9be-4a1c-4b07-bfe2-4c7fe0610f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21525
54463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2152554463
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3583837965
Short name T400
Test name
Test status
Simulation time 463433973 ps
CPU time 1.33 seconds
Started Jul 14 07:20:43 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 206860 kb
Host smart-ec31544c-a280-4795-8f76-bf4b0c891dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35838
37965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3583837965
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3371056805
Short name T1722
Test name
Test status
Simulation time 140935945 ps
CPU time 0.77 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206884 kb
Host smart-0126cfcb-a322-4b1e-b13f-3c771a992590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33710
56805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3371056805
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2152938010
Short name T711
Test name
Test status
Simulation time 78669762 ps
CPU time 0.7 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206852 kb
Host smart-eba6a867-01ac-4d98-8d75-f3c6f2ffa541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21529
38010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2152938010
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3116400365
Short name T1282
Test name
Test status
Simulation time 959776617 ps
CPU time 2.28 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:13 PM PDT 24
Peak memory 207024 kb
Host smart-f16e3de3-08f0-489b-9724-9b47e8ae54a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31164
00365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3116400365
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3889609663
Short name T1406
Test name
Test status
Simulation time 305523976 ps
CPU time 2.13 seconds
Started Jul 14 07:20:40 PM PDT 24
Finished Jul 14 07:21:07 PM PDT 24
Peak memory 207108 kb
Host smart-817b5985-4e06-4b0b-a4f3-cf67845085aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38896
09663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3889609663
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2738118452
Short name T1789
Test name
Test status
Simulation time 211437046 ps
CPU time 0.87 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206872 kb
Host smart-b211c191-0057-44cd-b4f9-7d91d4a59a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27381
18452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2738118452
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.4203635022
Short name T385
Test name
Test status
Simulation time 143130467 ps
CPU time 0.79 seconds
Started Jul 14 07:20:52 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 206872 kb
Host smart-d28f1966-f361-4573-83a3-9a104e9be938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42036
35022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.4203635022
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.686737368
Short name T1501
Test name
Test status
Simulation time 188273332 ps
CPU time 0.92 seconds
Started Jul 14 07:20:42 PM PDT 24
Finished Jul 14 07:21:06 PM PDT 24
Peak memory 206868 kb
Host smart-e5ff71e5-c273-49ee-9c25-d730a4a7f661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68673
7368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.686737368
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.982372894
Short name T1872
Test name
Test status
Simulation time 10266086303 ps
CPU time 31.58 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 207140 kb
Host smart-49c8636b-1052-4584-910a-709009f6354e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98237
2894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.982372894
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.597404374
Short name T26
Test name
Test status
Simulation time 182623296 ps
CPU time 0.81 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206888 kb
Host smart-f76ea6f1-e225-433e-86d5-908ebf389c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59740
4374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.597404374
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.175586971
Short name T995
Test name
Test status
Simulation time 23356399284 ps
CPU time 22.51 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:40 PM PDT 24
Peak memory 206944 kb
Host smart-a749d524-d1dc-498d-af51-bdc659f8cfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17558
6971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.175586971
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.4051913835
Short name T937
Test name
Test status
Simulation time 3320975189 ps
CPU time 3.98 seconds
Started Jul 14 07:20:59 PM PDT 24
Finished Jul 14 07:21:23 PM PDT 24
Peak memory 206944 kb
Host smart-5f49178f-f88c-4678-919a-e54a45733e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40519
13835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.4051913835
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3031050153
Short name T2245
Test name
Test status
Simulation time 10440752010 ps
CPU time 71.01 seconds
Started Jul 14 07:21:08 PM PDT 24
Finished Jul 14 07:22:40 PM PDT 24
Peak memory 207132 kb
Host smart-76f6cc56-46c1-43b0-8c08-51c727321c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30310
50153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3031050153
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2533698856
Short name T1822
Test name
Test status
Simulation time 6081962129 ps
CPU time 161.34 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:23:52 PM PDT 24
Peak memory 207108 kb
Host smart-a92963ac-8b15-43ff-8893-468d5b7a6293
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2533698856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2533698856
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2707344851
Short name T304
Test name
Test status
Simulation time 247480404 ps
CPU time 0.95 seconds
Started Jul 14 07:21:01 PM PDT 24
Finished Jul 14 07:21:23 PM PDT 24
Peak memory 206868 kb
Host smart-ff26f83c-89db-4b96-8961-d07e4aa7ea6f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2707344851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2707344851
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3048092494
Short name T2184
Test name
Test status
Simulation time 182351791 ps
CPU time 0.88 seconds
Started Jul 14 07:21:02 PM PDT 24
Finished Jul 14 07:21:23 PM PDT 24
Peak memory 206872 kb
Host smart-e6971489-be98-484f-9849-064399ec4a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30480
92494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3048092494
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1423071029
Short name T623
Test name
Test status
Simulation time 6550466559 ps
CPU time 45.58 seconds
Started Jul 14 07:20:51 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 207096 kb
Host smart-de391f4a-f988-484c-a03b-2e9d3631fee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14230
71029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1423071029
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.4224901910
Short name T446
Test name
Test status
Simulation time 7039601418 ps
CPU time 192.67 seconds
Started Jul 14 07:21:00 PM PDT 24
Finished Jul 14 07:24:33 PM PDT 24
Peak memory 207144 kb
Host smart-c875e7be-6963-4a4c-b747-8b831cdb6e58
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4224901910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.4224901910
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3657964721
Short name T2724
Test name
Test status
Simulation time 193626409 ps
CPU time 0.82 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 206868 kb
Host smart-3ee6b820-3617-47e3-bc78-07ccaf964cb8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3657964721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3657964721
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.144367614
Short name T2105
Test name
Test status
Simulation time 173566022 ps
CPU time 0.82 seconds
Started Jul 14 07:21:01 PM PDT 24
Finished Jul 14 07:21:22 PM PDT 24
Peak memory 206896 kb
Host smart-a7fb910c-afec-42e4-9cff-b957c6a0b649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14436
7614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.144367614
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2155465064
Short name T110
Test name
Test status
Simulation time 178635224 ps
CPU time 0.9 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 206880 kb
Host smart-1109b728-c933-4a1c-9b4f-cc40d3b7e72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554
65064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2155465064
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.976971454
Short name T1215
Test name
Test status
Simulation time 193965560 ps
CPU time 0.88 seconds
Started Jul 14 07:20:56 PM PDT 24
Finished Jul 14 07:21:17 PM PDT 24
Peak memory 206876 kb
Host smart-99f5027e-715d-4811-be4d-fd8614c0bb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97697
1454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.976971454
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.588114549
Short name T535
Test name
Test status
Simulation time 197411240 ps
CPU time 0.82 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 206848 kb
Host smart-f5717a70-8cc6-4828-b7b6-de331444d701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58811
4549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.588114549
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4179421076
Short name T725
Test name
Test status
Simulation time 191349309 ps
CPU time 0.8 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206824 kb
Host smart-839b74a7-e4ba-46c5-9f0f-d52e0774e997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41794
21076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4179421076
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2728294710
Short name T1088
Test name
Test status
Simulation time 198969620 ps
CPU time 0.84 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206888 kb
Host smart-8cd7dc53-eb66-419b-ade0-8d8dfe4e8079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27282
94710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2728294710
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2416403542
Short name T486
Test name
Test status
Simulation time 206889922 ps
CPU time 0.91 seconds
Started Jul 14 07:21:07 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 206848 kb
Host smart-c749f46a-e81c-4730-9729-5cf440e5aa2a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2416403542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2416403542
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.4125759196
Short name T1081
Test name
Test status
Simulation time 153720859 ps
CPU time 0.78 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206832 kb
Host smart-52b144e1-21bd-430b-b116-05012fc550e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
59196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.4125759196
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1048947733
Short name T1629
Test name
Test status
Simulation time 113750429 ps
CPU time 0.73 seconds
Started Jul 14 07:20:55 PM PDT 24
Finished Jul 14 07:21:16 PM PDT 24
Peak memory 206856 kb
Host smart-98e64117-20ba-497a-9914-689c97c14678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10489
47733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1048947733
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3245781222
Short name T1840
Test name
Test status
Simulation time 11101592853 ps
CPU time 24.66 seconds
Started Jul 14 07:20:52 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 207084 kb
Host smart-49789271-8b83-44f4-a9e8-a97b286a1f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32457
81222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3245781222
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.268837508
Short name T280
Test name
Test status
Simulation time 156211944 ps
CPU time 0.78 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206860 kb
Host smart-d0bec2c6-3489-458f-8c06-3118f6e31691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26883
7508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.268837508
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2561994892
Short name T1301
Test name
Test status
Simulation time 235511075 ps
CPU time 0.9 seconds
Started Jul 14 07:20:51 PM PDT 24
Finished Jul 14 07:21:13 PM PDT 24
Peak memory 206892 kb
Host smart-4b9aaf38-fd46-4f00-bd6a-a962e4e65b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25619
94892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2561994892
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2855689177
Short name T1097
Test name
Test status
Simulation time 244147621 ps
CPU time 0.95 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:11 PM PDT 24
Peak memory 206828 kb
Host smart-e599b0d0-0fcb-4c2b-8cad-73363edc0778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28556
89177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2855689177
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2946868136
Short name T358
Test name
Test status
Simulation time 175183581 ps
CPU time 0.82 seconds
Started Jul 14 07:20:56 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 206884 kb
Host smart-7218eb11-888f-484c-816a-45346fa7946d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29468
68136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2946868136
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.172366855
Short name T1125
Test name
Test status
Simulation time 169610976 ps
CPU time 0.87 seconds
Started Jul 14 07:20:50 PM PDT 24
Finished Jul 14 07:21:12 PM PDT 24
Peak memory 206840 kb
Host smart-36768428-0710-45c8-b368-0c4045eafedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17236
6855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.172366855
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2652588365
Short name T2123
Test name
Test status
Simulation time 173816402 ps
CPU time 0.79 seconds
Started Jul 14 07:21:02 PM PDT 24
Finished Jul 14 07:21:23 PM PDT 24
Peak memory 206848 kb
Host smart-62d1f209-7a29-4a9b-9b82-8b3c5def9d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26525
88365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2652588365
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1373267245
Short name T545
Test name
Test status
Simulation time 191414072 ps
CPU time 0.84 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206868 kb
Host smart-5331f691-3207-4b76-9e90-a7889f08f64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13732
67245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1373267245
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.3368667343
Short name T810
Test name
Test status
Simulation time 5420992198 ps
CPU time 48 seconds
Started Jul 14 07:20:52 PM PDT 24
Finished Jul 14 07:22:01 PM PDT 24
Peak memory 207092 kb
Host smart-2fa24e58-5567-4a9c-b000-395f009ff8bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3368667343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.3368667343
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1127477187
Short name T312
Test name
Test status
Simulation time 219826743 ps
CPU time 0.84 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206896 kb
Host smart-f8d52905-e6ff-48d7-b2d1-d570a3c1c4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11274
77187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1127477187
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1017882032
Short name T1018
Test name
Test status
Simulation time 193688927 ps
CPU time 0.81 seconds
Started Jul 14 07:20:51 PM PDT 24
Finished Jul 14 07:21:13 PM PDT 24
Peak memory 206844 kb
Host smart-9f7522b4-a2f9-404f-b56c-8968539172dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10178
82032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1017882032
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.4212630576
Short name T2218
Test name
Test status
Simulation time 1300799587 ps
CPU time 3 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 206992 kb
Host smart-ecc49e4f-2d68-436f-954d-f382a359660c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42126
30576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.4212630576
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1950275010
Short name T946
Test name
Test status
Simulation time 6694870036 ps
CPU time 194.17 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:24:25 PM PDT 24
Peak memory 207084 kb
Host smart-9307acae-1ba5-4f9a-804f-36f395ff594f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19502
75010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1950275010
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.3614498170
Short name T1342
Test name
Test status
Simulation time 68216910 ps
CPU time 0.72 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206928 kb
Host smart-221124e7-86e2-4cb2-9147-4790d3fecd76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3614498170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.3614498170
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2938767610
Short name T2225
Test name
Test status
Simulation time 3860517435 ps
CPU time 4.65 seconds
Started Jul 14 07:20:49 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206940 kb
Host smart-a07b361c-2956-4035-aef0-cd4fac355709
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2938767610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.2938767610
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1737879391
Short name T753
Test name
Test status
Simulation time 13345827247 ps
CPU time 13.3 seconds
Started Jul 14 07:20:55 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 206924 kb
Host smart-bbfedc8d-749f-4063-ba31-256faf0388a1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1737879391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1737879391
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1186829768
Short name T1357
Test name
Test status
Simulation time 23341750629 ps
CPU time 25.48 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 206928 kb
Host smart-1fcdf55c-b476-45d2-87b1-1ccd48afa5aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1186829768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1186829768
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1921666449
Short name T739
Test name
Test status
Simulation time 207462090 ps
CPU time 0.82 seconds
Started Jul 14 07:20:56 PM PDT 24
Finished Jul 14 07:21:17 PM PDT 24
Peak memory 206868 kb
Host smart-8ca67939-0832-4c30-8401-a60b4823a4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19216
66449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1921666449
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3965610301
Short name T1871
Test name
Test status
Simulation time 155812975 ps
CPU time 0.78 seconds
Started Jul 14 07:21:13 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 206872 kb
Host smart-4dde404d-e2c4-418a-82cf-7d86d1e38fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39656
10301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3965610301
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3838289237
Short name T751
Test name
Test status
Simulation time 282010452 ps
CPU time 1.07 seconds
Started Jul 14 07:20:57 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 206820 kb
Host smart-8dfc2520-0ae6-4648-b011-2efebb7965e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38382
89237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3838289237
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1052857131
Short name T1266
Test name
Test status
Simulation time 534655056 ps
CPU time 1.38 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:16 PM PDT 24
Peak memory 206832 kb
Host smart-003c6382-4ad9-4775-9055-410b445b28cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10528
57131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1052857131
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3154519485
Short name T173
Test name
Test status
Simulation time 22094261218 ps
CPU time 40.44 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:55 PM PDT 24
Peak memory 207096 kb
Host smart-b60b2047-7000-4c31-86c1-1614080440fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31545
19485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3154519485
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3140275522
Short name T1882
Test name
Test status
Simulation time 401789442 ps
CPU time 1.19 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206880 kb
Host smart-7f69721c-ab23-4e78-8212-add3eafbd0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31402
75522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3140275522
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1102672545
Short name T1146
Test name
Test status
Simulation time 182410137 ps
CPU time 0.76 seconds
Started Jul 14 07:20:55 PM PDT 24
Finished Jul 14 07:21:16 PM PDT 24
Peak memory 206840 kb
Host smart-c629fcf0-946a-42e9-905e-fe4ef4533f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11026
72545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1102672545
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2235189868
Short name T2560
Test name
Test status
Simulation time 100511476 ps
CPU time 0.66 seconds
Started Jul 14 07:20:53 PM PDT 24
Finished Jul 14 07:21:14 PM PDT 24
Peak memory 206840 kb
Host smart-e721475d-11aa-4a3b-b998-d71496d085c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22351
89868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2235189868
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1604147130
Short name T399
Test name
Test status
Simulation time 868807655 ps
CPU time 2.12 seconds
Started Jul 14 07:20:57 PM PDT 24
Finished Jul 14 07:21:19 PM PDT 24
Peak memory 207064 kb
Host smart-9bb202d0-01d4-4d97-bd4f-abcfbdef89b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16041
47130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1604147130
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2424762559
Short name T814
Test name
Test status
Simulation time 309568483 ps
CPU time 2.21 seconds
Started Jul 14 07:21:01 PM PDT 24
Finished Jul 14 07:21:24 PM PDT 24
Peak memory 207016 kb
Host smart-64e792f5-d887-4309-aadc-d83e68e99972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24247
62559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2424762559
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.4137194902
Short name T1538
Test name
Test status
Simulation time 242188576 ps
CPU time 0.92 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 206884 kb
Host smart-33198be0-9e41-4093-abed-7135e025c439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41371
94902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.4137194902
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1088576593
Short name T350
Test name
Test status
Simulation time 147400837 ps
CPU time 0.75 seconds
Started Jul 14 07:21:07 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 206848 kb
Host smart-f5a5fb56-bb93-456e-9b0a-164e548a691a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10885
76593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1088576593
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1188843324
Short name T904
Test name
Test status
Simulation time 229713504 ps
CPU time 0.87 seconds
Started Jul 14 07:21:05 PM PDT 24
Finished Jul 14 07:21:26 PM PDT 24
Peak memory 206880 kb
Host smart-5ddc7c60-2908-4b09-8258-d5d0a1f178a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
43324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1188843324
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.3799840320
Short name T81
Test name
Test status
Simulation time 5618606772 ps
CPU time 42.63 seconds
Started Jul 14 07:20:53 PM PDT 24
Finished Jul 14 07:21:56 PM PDT 24
Peak memory 207136 kb
Host smart-a4bbcaa5-ab30-4d23-b6ce-10da134e2680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37998
40320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.3799840320
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2708916408
Short name T1745
Test name
Test status
Simulation time 197013340 ps
CPU time 0.84 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206824 kb
Host smart-253bdb2d-bd69-4b74-ac17-9e09c9ee0e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27089
16408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2708916408
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1468783504
Short name T450
Test name
Test status
Simulation time 23325459556 ps
CPU time 26.58 seconds
Started Jul 14 07:21:06 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206892 kb
Host smart-e768bcd7-400f-4f4c-9d2a-ec9f36acc767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14687
83504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1468783504
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3607465676
Short name T964
Test name
Test status
Simulation time 3318081044 ps
CPU time 3.76 seconds
Started Jul 14 07:21:05 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 206872 kb
Host smart-8712da6f-38b9-4355-b7f0-82720d9c67fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
65676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3607465676
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3797712791
Short name T621
Test name
Test status
Simulation time 7309148935 ps
CPU time 50.81 seconds
Started Jul 14 07:21:02 PM PDT 24
Finished Jul 14 07:22:13 PM PDT 24
Peak memory 207136 kb
Host smart-7a5ba01c-0b18-4c7c-bfc4-610f44e7abaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37977
12791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3797712791
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1917919650
Short name T1280
Test name
Test status
Simulation time 4331334680 ps
CPU time 29.88 seconds
Started Jul 14 07:21:01 PM PDT 24
Finished Jul 14 07:21:51 PM PDT 24
Peak memory 207112 kb
Host smart-39c98cb6-5da0-4b5d-9c7e-2b55e58f3935
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1917919650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1917919650
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.29124828
Short name T2483
Test name
Test status
Simulation time 251347085 ps
CPU time 0.91 seconds
Started Jul 14 07:20:57 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 206876 kb
Host smart-a4a9001c-0995-469b-ba6b-bca0bd4a56e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=29124828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.29124828
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2912201049
Short name T2309
Test name
Test status
Simulation time 197331729 ps
CPU time 0.88 seconds
Started Jul 14 07:20:56 PM PDT 24
Finished Jul 14 07:21:17 PM PDT 24
Peak memory 206856 kb
Host smart-614ab66a-71ea-4177-be0c-bb36e841b90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29122
01049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2912201049
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.1246615580
Short name T633
Test name
Test status
Simulation time 6342559758 ps
CPU time 175.88 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:24:15 PM PDT 24
Peak memory 207076 kb
Host smart-97573be2-38d5-4198-a5d9-326af7777ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12466
15580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.1246615580
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3732053202
Short name T2050
Test name
Test status
Simulation time 6611228069 ps
CPU time 175.94 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:24:11 PM PDT 24
Peak memory 207036 kb
Host smart-5d32c5c7-0d95-46f6-a610-86ecc91daf37
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3732053202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3732053202
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1203319618
Short name T1835
Test name
Test status
Simulation time 164794937 ps
CPU time 0.79 seconds
Started Jul 14 07:21:00 PM PDT 24
Finished Jul 14 07:21:22 PM PDT 24
Peak memory 206836 kb
Host smart-b3e0b48f-4c2e-4da4-bddb-0cbd762e41b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1203319618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1203319618
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.310952455
Short name T1178
Test name
Test status
Simulation time 144462740 ps
CPU time 0.77 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:19 PM PDT 24
Peak memory 206872 kb
Host smart-2bace4b9-8701-42b5-84e6-f27e4b77c6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31095
2455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.310952455
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2227774607
Short name T1584
Test name
Test status
Simulation time 165135394 ps
CPU time 0.8 seconds
Started Jul 14 07:20:57 PM PDT 24
Finished Jul 14 07:21:18 PM PDT 24
Peak memory 206832 kb
Host smart-e22eb543-753f-4956-8e9c-03978173ad65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22277
74607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2227774607
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.922680812
Short name T2441
Test name
Test status
Simulation time 181981857 ps
CPU time 0.79 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:32 PM PDT 24
Peak memory 206880 kb
Host smart-2bc7a134-e97e-4c0d-9750-72fe1409898f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92268
0812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.922680812
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1729571106
Short name T1592
Test name
Test status
Simulation time 191695865 ps
CPU time 0.81 seconds
Started Jul 14 07:21:01 PM PDT 24
Finished Jul 14 07:21:22 PM PDT 24
Peak memory 206860 kb
Host smart-47a5211e-728c-4cc4-8775-1ee2fb9a9916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17295
71106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1729571106
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1628458342
Short name T1262
Test name
Test status
Simulation time 193432758 ps
CPU time 0.81 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206876 kb
Host smart-59d7c6d0-f471-411b-a9b5-832ee4fa469d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16284
58342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1628458342
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.291040951
Short name T719
Test name
Test status
Simulation time 259019219 ps
CPU time 0.95 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206868 kb
Host smart-c8e51b32-dc8d-41ae-8c45-a0959a69465e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=291040951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.291040951
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3122221855
Short name T2716
Test name
Test status
Simulation time 149988367 ps
CPU time 0.76 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206876 kb
Host smart-2b2e5e89-7609-4860-9cfd-3bdf841d0eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31222
21855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3122221855
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2678450972
Short name T1500
Test name
Test status
Simulation time 52673170 ps
CPU time 0.68 seconds
Started Jul 14 07:21:02 PM PDT 24
Finished Jul 14 07:21:23 PM PDT 24
Peak memory 206856 kb
Host smart-d9253c6c-affa-458e-8334-7fa1505c7c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26784
50972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2678450972
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.797773342
Short name T2565
Test name
Test status
Simulation time 9585852844 ps
CPU time 21.94 seconds
Started Jul 14 07:20:55 PM PDT 24
Finished Jul 14 07:21:38 PM PDT 24
Peak memory 207192 kb
Host smart-4ba96d68-64da-4634-bb0a-ee49759c1809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79777
3342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.797773342
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1114469977
Short name T1356
Test name
Test status
Simulation time 183986575 ps
CPU time 0.83 seconds
Started Jul 14 07:21:04 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206884 kb
Host smart-07cdca45-9406-4bfa-baf9-60204b90dd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11144
69977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1114469977
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3437275768
Short name T2519
Test name
Test status
Simulation time 229901477 ps
CPU time 0.92 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206864 kb
Host smart-c83586d7-8029-4c85-b743-c27282511dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34372
75768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3437275768
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.813930991
Short name T1363
Test name
Test status
Simulation time 204171978 ps
CPU time 0.86 seconds
Started Jul 14 07:20:54 PM PDT 24
Finished Jul 14 07:21:15 PM PDT 24
Peak memory 206832 kb
Host smart-41292290-ca99-41cf-a92d-60f484c7ea0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81393
0991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.813930991
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3373772929
Short name T2485
Test name
Test status
Simulation time 176308374 ps
CPU time 0.94 seconds
Started Jul 14 07:20:55 PM PDT 24
Finished Jul 14 07:21:17 PM PDT 24
Peak memory 206840 kb
Host smart-f0dd6a49-8f1d-4e5b-8fe4-30cd836be63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33737
72929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3373772929
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3284096369
Short name T761
Test name
Test status
Simulation time 212792414 ps
CPU time 0.81 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206844 kb
Host smart-8e844dca-2fe6-4821-a757-94ece34d2194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
96369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3284096369
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2743190717
Short name T2053
Test name
Test status
Simulation time 156839665 ps
CPU time 0.82 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206856 kb
Host smart-7ec59cee-0ba8-492b-b420-3d36c8bbeb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27431
90717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2743190717
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.778006965
Short name T1852
Test name
Test status
Simulation time 213251715 ps
CPU time 0.89 seconds
Started Jul 14 07:21:00 PM PDT 24
Finished Jul 14 07:21:22 PM PDT 24
Peak memory 206876 kb
Host smart-d3a89f3c-be73-4146-8677-6899919ea0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77800
6965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.778006965
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1511189231
Short name T1901
Test name
Test status
Simulation time 237273333 ps
CPU time 0.93 seconds
Started Jul 14 07:20:58 PM PDT 24
Finished Jul 14 07:21:20 PM PDT 24
Peak memory 206880 kb
Host smart-61b56e73-b3a0-4894-963d-2ef8997d3cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15111
89231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1511189231
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1384527871
Short name T1320
Test name
Test status
Simulation time 3845417961 ps
CPU time 38.17 seconds
Started Jul 14 07:21:08 PM PDT 24
Finished Jul 14 07:22:07 PM PDT 24
Peak memory 207128 kb
Host smart-0387e60e-d99b-42ac-b4e5-5f2f093a9824
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1384527871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1384527871
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2623973094
Short name T306
Test name
Test status
Simulation time 184498496 ps
CPU time 0.81 seconds
Started Jul 14 07:20:59 PM PDT 24
Finished Jul 14 07:21:21 PM PDT 24
Peak memory 206840 kb
Host smart-02328b4f-7665-4a96-b4ad-b72e2fe4cc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26239
73094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2623973094
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3124599131
Short name T1161
Test name
Test status
Simulation time 176328023 ps
CPU time 0.84 seconds
Started Jul 14 07:21:01 PM PDT 24
Finished Jul 14 07:21:23 PM PDT 24
Peak memory 206900 kb
Host smart-62c50609-91b5-4aa2-bd45-02eac1afbee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31245
99131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3124599131
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.4120746589
Short name T779
Test name
Test status
Simulation time 1030140749 ps
CPU time 2.08 seconds
Started Jul 14 07:21:02 PM PDT 24
Finished Jul 14 07:21:26 PM PDT 24
Peak memory 207040 kb
Host smart-4f66ff80-ae47-4fc9-a1a6-bbbc5ac5baa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41207
46589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.4120746589
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.4287813412
Short name T667
Test name
Test status
Simulation time 4802992074 ps
CPU time 33.67 seconds
Started Jul 14 07:21:04 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 207160 kb
Host smart-3363db73-0ea5-4532-a436-1cee41187be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42878
13412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.4287813412
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3547473958
Short name T1131
Test name
Test status
Simulation time 37510597 ps
CPU time 0.66 seconds
Started Jul 14 07:21:19 PM PDT 24
Finished Jul 14 07:21:40 PM PDT 24
Peak memory 206912 kb
Host smart-05efc93f-f133-493b-bd42-5d6d4454b8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3547473958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3547473958
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2419322863
Short name T1868
Test name
Test status
Simulation time 3810575653 ps
CPU time 4.9 seconds
Started Jul 14 07:21:01 PM PDT 24
Finished Jul 14 07:21:27 PM PDT 24
Peak memory 206956 kb
Host smart-eb14d4f7-c8e6-4b4f-9fda-fefa3afe2ea0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2419322863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2419322863
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.220960948
Short name T1865
Test name
Test status
Simulation time 13432010375 ps
CPU time 12.92 seconds
Started Jul 14 07:21:05 PM PDT 24
Finished Jul 14 07:21:38 PM PDT 24
Peak memory 207084 kb
Host smart-9868572d-ef51-4fbf-834e-9ec13fc64133
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=220960948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.220960948
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.1944159172
Short name T875
Test name
Test status
Simulation time 23348734738 ps
CPU time 26.94 seconds
Started Jul 14 07:21:02 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 206936 kb
Host smart-79d23ab6-5a4e-4c30-8fbd-2af8de8e8b44
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1944159172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.1944159172
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.227549924
Short name T2611
Test name
Test status
Simulation time 176337460 ps
CPU time 0.82 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206860 kb
Host smart-a3167f14-8d89-44d6-8103-6fddb137564c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22754
9924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.227549924
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3371822494
Short name T1808
Test name
Test status
Simulation time 207746110 ps
CPU time 0.79 seconds
Started Jul 14 07:21:05 PM PDT 24
Finished Jul 14 07:21:26 PM PDT 24
Peak memory 206868 kb
Host smart-ba3adc91-ff45-479c-be2e-5ed5c4b70bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33718
22494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3371822494
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1105186384
Short name T1258
Test name
Test status
Simulation time 368136605 ps
CPU time 1.14 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206872 kb
Host smart-1772fd7b-e8d0-4bf1-8a66-0086bcba4efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11051
86384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1105186384
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.998911637
Short name T2232
Test name
Test status
Simulation time 867722436 ps
CPU time 2 seconds
Started Jul 14 07:21:00 PM PDT 24
Finished Jul 14 07:21:23 PM PDT 24
Peak memory 207032 kb
Host smart-6abb442c-8930-46e2-ae57-6cd160a86b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99891
1637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.998911637
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2429522339
Short name T154
Test name
Test status
Simulation time 21582108458 ps
CPU time 41.35 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 207068 kb
Host smart-82f92825-a12e-47ec-bf98-fe486b32efad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24295
22339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2429522339
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2858249360
Short name T824
Test name
Test status
Simulation time 301120314 ps
CPU time 1.1 seconds
Started Jul 14 07:21:04 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206872 kb
Host smart-ea954760-b30b-44b6-91c7-f47947170eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28582
49360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2858249360
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.356438284
Short name T1217
Test name
Test status
Simulation time 174465331 ps
CPU time 0.75 seconds
Started Jul 14 07:21:12 PM PDT 24
Finished Jul 14 07:21:33 PM PDT 24
Peak memory 206884 kb
Host smart-558d756b-71bc-43f2-a366-d5538eff541b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35643
8284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.356438284
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1995880510
Short name T2371
Test name
Test status
Simulation time 36401101 ps
CPU time 0.61 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206732 kb
Host smart-803f7431-d382-44c2-ac8c-28890ede9438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19958
80510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1995880510
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1996744550
Short name T1324
Test name
Test status
Simulation time 668719557 ps
CPU time 1.87 seconds
Started Jul 14 07:21:02 PM PDT 24
Finished Jul 14 07:21:24 PM PDT 24
Peak memory 207040 kb
Host smart-da25b2cf-8fb3-4e89-a063-215d2472e2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19967
44550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1996744550
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.188358889
Short name T872
Test name
Test status
Simulation time 216992190 ps
CPU time 2.12 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:26 PM PDT 24
Peak memory 207080 kb
Host smart-5144fe21-9361-4dba-b898-036d1b074566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18835
8889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.188358889
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.275248115
Short name T2104
Test name
Test status
Simulation time 210807431 ps
CPU time 0.89 seconds
Started Jul 14 07:21:15 PM PDT 24
Finished Jul 14 07:21:36 PM PDT 24
Peak memory 206868 kb
Host smart-eaed59b2-2156-425b-9f85-eaca712ede56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27524
8115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.275248115
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2520000256
Short name T642
Test name
Test status
Simulation time 148089799 ps
CPU time 0.72 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206756 kb
Host smart-37cc96b7-0f92-4005-b0a0-b80934226f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200
00256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2520000256
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1924528156
Short name T2447
Test name
Test status
Simulation time 237394877 ps
CPU time 0.87 seconds
Started Jul 14 07:21:13 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 206868 kb
Host smart-a5930ab2-d411-4827-a34f-e18a12ac6c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19245
28156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1924528156
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.2787874736
Short name T1941
Test name
Test status
Simulation time 4971070394 ps
CPU time 33.64 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:22:04 PM PDT 24
Peak memory 207032 kb
Host smart-4e5ee744-a531-405a-b763-19b0df67086e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2787874736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.2787874736
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3501351819
Short name T529
Test name
Test status
Simulation time 11576852048 ps
CPU time 40.97 seconds
Started Jul 14 07:21:04 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 207128 kb
Host smart-5fb20f06-7bce-460c-9981-fb6b9fb31adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
51819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3501351819
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2195522376
Short name T1972
Test name
Test status
Simulation time 263204873 ps
CPU time 0.99 seconds
Started Jul 14 07:21:03 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206828 kb
Host smart-28a42755-d1e5-4e47-9dc7-c9beb2907d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21955
22376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2195522376
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1089808743
Short name T2035
Test name
Test status
Simulation time 23380586928 ps
CPU time 23.04 seconds
Started Jul 14 07:21:15 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 206916 kb
Host smart-1360f818-6c75-400a-a43c-180421c54d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10898
08743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1089808743
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.4029130214
Short name T736
Test name
Test status
Simulation time 3381945180 ps
CPU time 3.93 seconds
Started Jul 14 07:21:07 PM PDT 24
Finished Jul 14 07:21:32 PM PDT 24
Peak memory 206944 kb
Host smart-57edc154-7ab8-4922-8251-6f6e4075095c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40291
30214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.4029130214
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1693277322
Short name T1685
Test name
Test status
Simulation time 10648324272 ps
CPU time 103.85 seconds
Started Jul 14 07:21:14 PM PDT 24
Finished Jul 14 07:23:19 PM PDT 24
Peak memory 207128 kb
Host smart-d0a66ece-adaf-41c9-82e1-6d368786e44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16932
77322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1693277322
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.624717811
Short name T144
Test name
Test status
Simulation time 4166521887 ps
CPU time 27.55 seconds
Started Jul 14 07:21:04 PM PDT 24
Finished Jul 14 07:21:52 PM PDT 24
Peak memory 207108 kb
Host smart-7db1efa6-dffd-4d0a-a684-a4a6312a6d00
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=624717811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.624717811
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.97080924
Short name T2188
Test name
Test status
Simulation time 239969377 ps
CPU time 0.9 seconds
Started Jul 14 07:21:13 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 206872 kb
Host smart-9c08449e-5721-4a3e-871f-378567e6714e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=97080924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.97080924
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2681147692
Short name T1354
Test name
Test status
Simulation time 185208258 ps
CPU time 0.82 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206880 kb
Host smart-d9d0a9ef-b143-4c6a-b167-4b4199cca071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26811
47692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2681147692
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3014020970
Short name T948
Test name
Test status
Simulation time 3603618508 ps
CPU time 31.51 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:22:02 PM PDT 24
Peak memory 207156 kb
Host smart-e432b771-941e-4f07-a193-0a85531448b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30140
20970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3014020970
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.1576791107
Short name T1311
Test name
Test status
Simulation time 5040801828 ps
CPU time 36.22 seconds
Started Jul 14 07:21:11 PM PDT 24
Finished Jul 14 07:22:07 PM PDT 24
Peak memory 207108 kb
Host smart-6ff3d095-1fdb-4cf5-bedb-047fe35b8b76
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1576791107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.1576791107
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3112774449
Short name T2095
Test name
Test status
Simulation time 155409778 ps
CPU time 0.76 seconds
Started Jul 14 07:21:05 PM PDT 24
Finished Jul 14 07:21:26 PM PDT 24
Peak memory 206880 kb
Host smart-9955cb2a-7780-40c0-9ac6-e21ad3b77e26
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3112774449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3112774449
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3628214950
Short name T2449
Test name
Test status
Simulation time 159408511 ps
CPU time 0.76 seconds
Started Jul 14 07:21:07 PM PDT 24
Finished Jul 14 07:21:29 PM PDT 24
Peak memory 206884 kb
Host smart-2b08784f-af75-4394-b280-6e28d500501f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36282
14950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3628214950
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2155237600
Short name T866
Test name
Test status
Simulation time 192570009 ps
CPU time 0.8 seconds
Started Jul 14 07:21:13 PM PDT 24
Finished Jul 14 07:21:35 PM PDT 24
Peak memory 206868 kb
Host smart-5a39c67f-0c7e-4740-8297-3bfdd475e1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21552
37600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2155237600
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.671547126
Short name T914
Test name
Test status
Simulation time 173900846 ps
CPU time 0.89 seconds
Started Jul 14 07:21:04 PM PDT 24
Finished Jul 14 07:21:25 PM PDT 24
Peak memory 206840 kb
Host smart-7485c05a-c4ae-4adb-8534-aa0365455ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67154
7126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.671547126
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4154671784
Short name T2692
Test name
Test status
Simulation time 184669557 ps
CPU time 0.85 seconds
Started Jul 14 07:21:12 PM PDT 24
Finished Jul 14 07:21:33 PM PDT 24
Peak memory 206872 kb
Host smart-ceeba2ca-3979-4afe-9db0-43751029f39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41546
71784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4154671784
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.521168509
Short name T2410
Test name
Test status
Simulation time 174644885 ps
CPU time 0.82 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206856 kb
Host smart-5b7da405-95cd-402f-be31-a7dc33d04858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52116
8509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.521168509
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2569212448
Short name T165
Test name
Test status
Simulation time 160105778 ps
CPU time 0.81 seconds
Started Jul 14 07:21:14 PM PDT 24
Finished Jul 14 07:21:35 PM PDT 24
Peak memory 206876 kb
Host smart-80347283-ad8b-438c-b738-8ff36bc12429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25692
12448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2569212448
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.2194759266
Short name T317
Test name
Test status
Simulation time 236499763 ps
CPU time 0.91 seconds
Started Jul 14 07:21:12 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 206856 kb
Host smart-01d4d931-1f93-4847-b22b-b83aa106afba
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2194759266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.2194759266
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1339435573
Short name T527
Test name
Test status
Simulation time 140450484 ps
CPU time 0.73 seconds
Started Jul 14 07:21:17 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 206856 kb
Host smart-c45f56ce-3f2a-415a-b9db-10fc9a1742d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
35573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1339435573
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3152016527
Short name T1449
Test name
Test status
Simulation time 31901731 ps
CPU time 0.63 seconds
Started Jul 14 07:21:14 PM PDT 24
Finished Jul 14 07:21:35 PM PDT 24
Peak memory 206800 kb
Host smart-8ad49271-e0ae-4b95-b6c4-7a836ae43d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31520
16527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3152016527
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3371057509
Short name T1317
Test name
Test status
Simulation time 8675399166 ps
CPU time 21.33 seconds
Started Jul 14 07:21:17 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 207072 kb
Host smart-fe4493a7-c51c-4c6e-9913-378811a5a128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33710
57509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3371057509
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.889565820
Short name T1013
Test name
Test status
Simulation time 253106092 ps
CPU time 0.89 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206848 kb
Host smart-c03aeaf8-b77c-443f-a473-f15ab83fcf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88956
5820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.889565820
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1019108372
Short name T2686
Test name
Test status
Simulation time 225290047 ps
CPU time 0.88 seconds
Started Jul 14 07:21:11 PM PDT 24
Finished Jul 14 07:21:32 PM PDT 24
Peak memory 206880 kb
Host smart-bd628b6e-7d21-46ac-acf7-480d71a3b9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10191
08372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1019108372
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2900533839
Short name T2612
Test name
Test status
Simulation time 233995845 ps
CPU time 1.02 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:32 PM PDT 24
Peak memory 206852 kb
Host smart-410b1cea-5f98-4a89-a02a-e62c2b2d677a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29005
33839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2900533839
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.601590607
Short name T1591
Test name
Test status
Simulation time 194032695 ps
CPU time 0.83 seconds
Started Jul 14 07:21:09 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206900 kb
Host smart-2a9a0238-888c-4759-976e-0c9ad5f70a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60159
0607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.601590607
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.596580410
Short name T84
Test name
Test status
Simulation time 132578684 ps
CPU time 0.79 seconds
Started Jul 14 07:21:16 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 206856 kb
Host smart-f0332ca6-4156-4223-9e9b-a2d0694731eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59658
0410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.596580410
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.747361805
Short name T1366
Test name
Test status
Simulation time 144343275 ps
CPU time 0.75 seconds
Started Jul 14 07:21:09 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206864 kb
Host smart-32265933-ce4b-4569-8d73-4c6e8857aa05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74736
1805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.747361805
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3417959003
Short name T635
Test name
Test status
Simulation time 199376178 ps
CPU time 0.83 seconds
Started Jul 14 07:21:09 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206864 kb
Host smart-03825504-878c-44cb-affe-5691c330d59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34179
59003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3417959003
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1894431335
Short name T483
Test name
Test status
Simulation time 221961718 ps
CPU time 0.9 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:32 PM PDT 24
Peak memory 206888 kb
Host smart-aab287c7-0dd1-4578-afcb-8541efd4c077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18944
31335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1894431335
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.178770228
Short name T564
Test name
Test status
Simulation time 3782623299 ps
CPU time 103.84 seconds
Started Jul 14 07:21:15 PM PDT 24
Finished Jul 14 07:23:18 PM PDT 24
Peak memory 207116 kb
Host smart-63f3fd93-a09c-4eb4-a3dc-e9287c1ce75b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=178770228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.178770228
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1605818568
Short name T1657
Test name
Test status
Simulation time 171007737 ps
CPU time 0.83 seconds
Started Jul 14 07:21:12 PM PDT 24
Finished Jul 14 07:21:33 PM PDT 24
Peak memory 206848 kb
Host smart-1c37c2eb-ce61-4d4f-af78-799bb7385e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16058
18568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1605818568
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.399778739
Short name T2601
Test name
Test status
Simulation time 166361811 ps
CPU time 0.78 seconds
Started Jul 14 07:21:09 PM PDT 24
Finished Jul 14 07:21:31 PM PDT 24
Peak memory 206884 kb
Host smart-8e3bb5cc-af53-4303-a338-803325144893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39977
8739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.399778739
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.3042020278
Short name T938
Test name
Test status
Simulation time 844472155 ps
CPU time 1.96 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:32 PM PDT 24
Peak memory 207028 kb
Host smart-89ac9658-4148-4faf-a0e4-c4bd8805eaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30420
20278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.3042020278
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.660518374
Short name T2429
Test name
Test status
Simulation time 5314653859 ps
CPU time 48.89 seconds
Started Jul 14 07:21:17 PM PDT 24
Finished Jul 14 07:22:27 PM PDT 24
Peak memory 207048 kb
Host smart-b39049be-45cb-4163-bd5e-090015f71f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66051
8374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.660518374
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.5020106
Short name T741
Test name
Test status
Simulation time 41674371 ps
CPU time 0.66 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:21:38 PM PDT 24
Peak memory 206924 kb
Host smart-32a54a04-5727-4fc7-8e92-025fb657a973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=5020106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.5020106
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.130900295
Short name T10
Test name
Test status
Simulation time 4222663393 ps
CPU time 4.72 seconds
Started Jul 14 07:21:17 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206928 kb
Host smart-a752e88c-87bb-45ca-bed2-93ec87436d53
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=130900295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.130900295
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.4114788224
Short name T2320
Test name
Test status
Simulation time 13396593023 ps
CPU time 12.63 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:43 PM PDT 24
Peak memory 207156 kb
Host smart-2adefe4c-e6e1-445d-b413-1ff64a601d3a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4114788224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.4114788224
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.4062190990
Short name T1057
Test name
Test status
Simulation time 23401374664 ps
CPU time 28.36 seconds
Started Jul 14 07:21:14 PM PDT 24
Finished Jul 14 07:22:03 PM PDT 24
Peak memory 206940 kb
Host smart-5d64048e-015a-44b1-86c1-61abb4665bb6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4062190990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.4062190990
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3732370378
Short name T591
Test name
Test status
Simulation time 158140819 ps
CPU time 0.79 seconds
Started Jul 14 07:21:10 PM PDT 24
Finished Jul 14 07:21:32 PM PDT 24
Peak memory 206844 kb
Host smart-84ab8b89-06f7-4f2f-af65-8297653d3b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
70378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3732370378
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2656202610
Short name T60
Test name
Test status
Simulation time 167733420 ps
CPU time 0.76 seconds
Started Jul 14 07:21:15 PM PDT 24
Finished Jul 14 07:21:35 PM PDT 24
Peak memory 206896 kb
Host smart-c7b938aa-fe32-4cb2-8ab3-2a9e3fb757b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26562
02610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2656202610
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2515705532
Short name T757
Test name
Test status
Simulation time 301719625 ps
CPU time 1.07 seconds
Started Jul 14 07:21:13 PM PDT 24
Finished Jul 14 07:21:35 PM PDT 24
Peak memory 206880 kb
Host smart-5ebdc4c1-45ac-4084-b805-493f256b39d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25157
05532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2515705532
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3638303903
Short name T997
Test name
Test status
Simulation time 1388212485 ps
CPU time 2.92 seconds
Started Jul 14 07:21:12 PM PDT 24
Finished Jul 14 07:21:36 PM PDT 24
Peak memory 207060 kb
Host smart-2e5c14cb-79b8-4d7a-bf23-a14b15ed5b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36383
03903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3638303903
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.911767255
Short name T1123
Test name
Test status
Simulation time 19408140749 ps
CPU time 35.22 seconds
Started Jul 14 07:21:12 PM PDT 24
Finished Jul 14 07:22:08 PM PDT 24
Peak memory 207140 kb
Host smart-ad5b6bfd-6bd4-4071-a5f2-358b3dfbabe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91176
7255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.911767255
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.131486632
Short name T838
Test name
Test status
Simulation time 425884255 ps
CPU time 1.23 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:21:39 PM PDT 24
Peak memory 206860 kb
Host smart-344e2972-e9c7-47a7-abe1-35f771a4e696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13148
6632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.131486632
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1551804530
Short name T1689
Test name
Test status
Simulation time 147186394 ps
CPU time 0.77 seconds
Started Jul 14 07:21:12 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 206872 kb
Host smart-9048db0b-f8de-4276-9094-6e7ced4473e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15518
04530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1551804530
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3761127337
Short name T2697
Test name
Test status
Simulation time 65568108 ps
CPU time 0.66 seconds
Started Jul 14 07:21:13 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 206880 kb
Host smart-2fee7e07-6461-4d8e-a51e-30140c0d31b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37611
27337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3761127337
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2558096866
Short name T2419
Test name
Test status
Simulation time 842869444 ps
CPU time 1.89 seconds
Started Jul 14 07:21:12 PM PDT 24
Finished Jul 14 07:21:34 PM PDT 24
Peak memory 207064 kb
Host smart-5e1b81ab-770e-4b1b-af42-98cd6ead2fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25580
96866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2558096866
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2287035261
Short name T1518
Test name
Test status
Simulation time 442434032 ps
CPU time 2.22 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:21:40 PM PDT 24
Peak memory 207052 kb
Host smart-f328845e-5c65-4d1e-a2dc-693c57592c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22870
35261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2287035261
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.96746113
Short name T735
Test name
Test status
Simulation time 216995680 ps
CPU time 0.87 seconds
Started Jul 14 07:21:19 PM PDT 24
Finished Jul 14 07:21:40 PM PDT 24
Peak memory 206860 kb
Host smart-39202baf-62fa-4994-8cb1-cf0f5c32c4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96746
113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.96746113
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.4195488959
Short name T921
Test name
Test status
Simulation time 169642893 ps
CPU time 0.82 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:21:39 PM PDT 24
Peak memory 206888 kb
Host smart-5af74c48-05a5-4026-9ce4-0716881010eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41954
88959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.4195488959
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.833319176
Short name T2543
Test name
Test status
Simulation time 272886331 ps
CPU time 0.93 seconds
Started Jul 14 07:21:26 PM PDT 24
Finished Jul 14 07:21:47 PM PDT 24
Peak memory 206868 kb
Host smart-825125b9-751a-4e1b-87fa-84490933be0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83331
9176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.833319176
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.524258869
Short name T1547
Test name
Test status
Simulation time 8749641084 ps
CPU time 62.94 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:22:44 PM PDT 24
Peak memory 207056 kb
Host smart-65a7ad6a-fbc0-4742-ac85-42b1be09eca3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=524258869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.524258869
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.2023876546
Short name T374
Test name
Test status
Simulation time 10175548399 ps
CPU time 37.6 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:22:15 PM PDT 24
Peak memory 207048 kb
Host smart-2feda5f4-1b01-4001-9979-b238dcdb7554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
76546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.2023876546
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.727068180
Short name T1052
Test name
Test status
Simulation time 167952798 ps
CPU time 0.78 seconds
Started Jul 14 07:21:16 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 206828 kb
Host smart-8a5112d3-61a4-430c-967d-e368a5f3852a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72706
8180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.727068180
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.4104904736
Short name T2152
Test name
Test status
Simulation time 23343866795 ps
CPU time 26.9 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:22:15 PM PDT 24
Peak memory 206868 kb
Host smart-e1353256-6b72-4251-96bf-5c512e704366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41049
04736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.4104904736
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2976463692
Short name T672
Test name
Test status
Simulation time 3339633593 ps
CPU time 4.29 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:47 PM PDT 24
Peak memory 206912 kb
Host smart-b87f5a4d-35e6-4b11-8b01-bdb8c657ff5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29764
63692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2976463692
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.3145667270
Short name T1234
Test name
Test status
Simulation time 7779149085 ps
CPU time 221.78 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:25:20 PM PDT 24
Peak memory 207128 kb
Host smart-9ce2838e-d9e6-41b3-894a-4d6ca9e9d58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31456
67270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.3145667270
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3863223700
Short name T2107
Test name
Test status
Simulation time 4870405662 ps
CPU time 32.57 seconds
Started Jul 14 07:21:24 PM PDT 24
Finished Jul 14 07:22:17 PM PDT 24
Peak memory 207120 kb
Host smart-b7f9c932-4449-4772-8e31-5cdb5c8f5a8a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3863223700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3863223700
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.1921695204
Short name T1813
Test name
Test status
Simulation time 236649678 ps
CPU time 0.89 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 206880 kb
Host smart-bececd9b-aa42-4a9f-9f83-5a145ada5b0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1921695204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.1921695204
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.592989728
Short name T1619
Test name
Test status
Simulation time 196567727 ps
CPU time 0.83 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206880 kb
Host smart-420c61ff-78f8-48cc-8a14-1d9482ad17cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59298
9728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.592989728
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2585453823
Short name T381
Test name
Test status
Simulation time 3784361763 ps
CPU time 35.38 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:22:16 PM PDT 24
Peak memory 207084 kb
Host smart-204cd18f-e93a-4c66-898f-1bf3ea2dee23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25854
53823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2585453823
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2574328396
Short name T572
Test name
Test status
Simulation time 5354549083 ps
CPU time 49.12 seconds
Started Jul 14 07:21:19 PM PDT 24
Finished Jul 14 07:22:29 PM PDT 24
Peak memory 207056 kb
Host smart-408a538b-e7d6-414e-a4b6-648bef7507da
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2574328396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2574328396
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.433099825
Short name T404
Test name
Test status
Simulation time 213391915 ps
CPU time 0.82 seconds
Started Jul 14 07:21:21 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206848 kb
Host smart-7ce346f0-d9d7-4c9f-9b93-04e2a327c6a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=433099825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.433099825
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.4117172724
Short name T318
Test name
Test status
Simulation time 159455274 ps
CPU time 0.81 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:21:41 PM PDT 24
Peak memory 206868 kb
Host smart-787add3f-2803-4bd9-b953-3261005938b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41171
72724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.4117172724
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.358097633
Short name T125
Test name
Test status
Simulation time 223407249 ps
CPU time 0.91 seconds
Started Jul 14 07:21:24 PM PDT 24
Finished Jul 14 07:21:45 PM PDT 24
Peak memory 206868 kb
Host smart-8e3051eb-64a1-4912-b8fe-c20b858792e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
7633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.358097633
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2440526464
Short name T1433
Test name
Test status
Simulation time 203611322 ps
CPU time 0.87 seconds
Started Jul 14 07:21:16 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 206840 kb
Host smart-18f71657-b4b6-4af9-9f62-dfe712cf3c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24405
26464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2440526464
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.85548597
Short name T1447
Test name
Test status
Simulation time 173684158 ps
CPU time 0.77 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:21:40 PM PDT 24
Peak memory 206872 kb
Host smart-f73de01d-5d39-40cf-a3fa-d5706f51b13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85548
597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.85548597
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3092419750
Short name T1044
Test name
Test status
Simulation time 190811602 ps
CPU time 0.81 seconds
Started Jul 14 07:21:17 PM PDT 24
Finished Jul 14 07:21:39 PM PDT 24
Peak memory 206856 kb
Host smart-3d14800e-f7e8-4a35-9098-552c7f40be97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30924
19750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3092419750
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1127444133
Short name T2426
Test name
Test status
Simulation time 232288693 ps
CPU time 0.81 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:21:39 PM PDT 24
Peak memory 206864 kb
Host smart-876a2540-69d7-4364-8d26-bacb30968ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11274
44133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1127444133
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2098607190
Short name T1008
Test name
Test status
Simulation time 240900772 ps
CPU time 0.94 seconds
Started Jul 14 07:21:16 PM PDT 24
Finished Jul 14 07:21:37 PM PDT 24
Peak memory 206848 kb
Host smart-cbfa7aa3-e1ba-4e0b-9072-84d98f4f7db8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2098607190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2098607190
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1954572473
Short name T956
Test name
Test status
Simulation time 157588694 ps
CPU time 0.79 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206864 kb
Host smart-cdb116a4-3f4a-434e-adf1-4b2eef31789e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19545
72473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1954572473
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1536093340
Short name T1385
Test name
Test status
Simulation time 84064165 ps
CPU time 0.76 seconds
Started Jul 14 07:21:23 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206880 kb
Host smart-0a9b6777-1a16-4ef8-ab30-34bf355a766e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15360
93340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1536093340
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2761090688
Short name T1918
Test name
Test status
Simulation time 22252627148 ps
CPU time 55.76 seconds
Started Jul 14 07:21:19 PM PDT 24
Finished Jul 14 07:22:35 PM PDT 24
Peak memory 215320 kb
Host smart-3c06d333-dcee-49ac-b695-f7176f429b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27610
90688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2761090688
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1371148619
Short name T433
Test name
Test status
Simulation time 186166120 ps
CPU time 0.88 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:21:39 PM PDT 24
Peak memory 206828 kb
Host smart-182d4c93-7c87-455c-abec-934a79749f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13711
48619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1371148619
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2373789231
Short name T2303
Test name
Test status
Simulation time 289128633 ps
CPU time 0.96 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:21:39 PM PDT 24
Peak memory 206844 kb
Host smart-e3c74bf4-1531-4cab-ab59-5423682e1e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23737
89231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2373789231
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1033627537
Short name T2710
Test name
Test status
Simulation time 189519083 ps
CPU time 0.83 seconds
Started Jul 14 07:21:43 PM PDT 24
Finished Jul 14 07:22:03 PM PDT 24
Peak memory 206856 kb
Host smart-5897999d-8ee1-4539-9c7c-94b3fe90d9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10336
27537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1033627537
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3875034420
Short name T1540
Test name
Test status
Simulation time 190367639 ps
CPU time 0.84 seconds
Started Jul 14 07:21:19 PM PDT 24
Finished Jul 14 07:21:40 PM PDT 24
Peak memory 206840 kb
Host smart-69d3aff6-3807-4002-a746-5d6bffbd7ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38750
34420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3875034420
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1837611042
Short name T69
Test name
Test status
Simulation time 142149298 ps
CPU time 0.73 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:21:41 PM PDT 24
Peak memory 206848 kb
Host smart-f072bcd8-205b-4184-9b06-5ef08a2bbc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18376
11042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1837611042
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3592988554
Short name T861
Test name
Test status
Simulation time 151402687 ps
CPU time 0.78 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206884 kb
Host smart-5a5959ac-f397-440d-9f0a-6bb5df3c6f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35929
88554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3592988554
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.567450905
Short name T1488
Test name
Test status
Simulation time 151983881 ps
CPU time 0.77 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206876 kb
Host smart-3b7285be-b4cd-44fb-92f1-3e4e9148e136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56745
0905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.567450905
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2098808541
Short name T895
Test name
Test status
Simulation time 208858209 ps
CPU time 0.88 seconds
Started Jul 14 07:21:23 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206868 kb
Host smart-f69f2624-d8b0-42e1-bdf3-58f577b03194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20988
08541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2098808541
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1566443707
Short name T1113
Test name
Test status
Simulation time 6525038428 ps
CPU time 170.96 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:24:29 PM PDT 24
Peak memory 207080 kb
Host smart-45255187-02ac-44db-959d-b3233c142f46
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1566443707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1566443707
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.416968025
Short name T2562
Test name
Test status
Simulation time 165294230 ps
CPU time 0.85 seconds
Started Jul 14 07:21:19 PM PDT 24
Finished Jul 14 07:21:40 PM PDT 24
Peak memory 206880 kb
Host smart-3da0fad5-3a94-4e28-bf57-431557836df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41696
8025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.416968025
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1103244405
Short name T1102
Test name
Test status
Simulation time 213641649 ps
CPU time 0.83 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206888 kb
Host smart-ea1148fd-fb91-4671-ae94-3478a22524da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11032
44405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1103244405
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.3673892591
Short name T1069
Test name
Test status
Simulation time 616235284 ps
CPU time 1.67 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:45 PM PDT 24
Peak memory 206860 kb
Host smart-3345d5bb-b15e-498a-a939-78c19f47e5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36738
92591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.3673892591
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.40800485
Short name T977
Test name
Test status
Simulation time 4497965498 ps
CPU time 32.61 seconds
Started Jul 14 07:21:19 PM PDT 24
Finished Jul 14 07:22:12 PM PDT 24
Peak memory 207088 kb
Host smart-1a5298b9-b1fb-4abf-8d08-707275c6b401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40800
485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.40800485
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2612426966
Short name T372
Test name
Test status
Simulation time 62434634 ps
CPU time 0.68 seconds
Started Jul 14 07:21:29 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 206920 kb
Host smart-b20b9f79-e26f-4182-b02d-60dbb70e32a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2612426966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2612426966
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3551852539
Short name T2734
Test name
Test status
Simulation time 4215992414 ps
CPU time 5.26 seconds
Started Jul 14 07:21:19 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 207144 kb
Host smart-8ccd1db2-a8cc-48da-acda-0c7155fb21ae
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3551852539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3551852539
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.635630884
Short name T1374
Test name
Test status
Simulation time 13308494645 ps
CPU time 11.6 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 207128 kb
Host smart-81140af1-5eb1-4385-bb23-1bbd5facf69a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=635630884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.635630884
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.275476274
Short name T1496
Test name
Test status
Simulation time 23335649801 ps
CPU time 27.26 seconds
Started Jul 14 07:21:18 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 206948 kb
Host smart-b8cf0c62-e81f-45af-956b-7cf7010a519d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=275476274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.275476274
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2109536797
Short name T712
Test name
Test status
Simulation time 176316122 ps
CPU time 0.83 seconds
Started Jul 14 07:21:23 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206880 kb
Host smart-eea11087-aa7b-41f1-808f-83e06f39d7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21095
36797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2109536797
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1620118177
Short name T460
Test name
Test status
Simulation time 160157484 ps
CPU time 0.75 seconds
Started Jul 14 07:21:24 PM PDT 24
Finished Jul 14 07:21:45 PM PDT 24
Peak memory 206872 kb
Host smart-4efdc243-542b-45ed-b9df-26abca7aa6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16201
18177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1620118177
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1672842295
Short name T467
Test name
Test status
Simulation time 365050000 ps
CPU time 1.21 seconds
Started Jul 14 07:21:23 PM PDT 24
Finished Jul 14 07:21:45 PM PDT 24
Peak memory 206900 kb
Host smart-fe1f3d3c-fc1c-441e-a863-d76b6993ee76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16728
42295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1672842295
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.97557233
Short name T1237
Test name
Test status
Simulation time 715512240 ps
CPU time 1.73 seconds
Started Jul 14 07:21:24 PM PDT 24
Finished Jul 14 07:21:45 PM PDT 24
Peak memory 207024 kb
Host smart-d904d153-9517-46d5-974f-d699e2dee524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97557
233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.97557233
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2037662562
Short name T43
Test name
Test status
Simulation time 10259800447 ps
CPU time 18.96 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:22:02 PM PDT 24
Peak memory 207096 kb
Host smart-84da01e7-119d-4f97-92b7-3b430d5f2f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20376
62562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2037662562
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1511931778
Short name T1671
Test name
Test status
Simulation time 349761989 ps
CPU time 1.1 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206896 kb
Host smart-c6bc9b0e-30ef-47ba-9964-8afc7d198038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15119
31778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1511931778
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.593438876
Short name T2106
Test name
Test status
Simulation time 187139392 ps
CPU time 0.86 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206848 kb
Host smart-c74cd6b9-5578-493c-8ac4-cb72c863b82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59343
8876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.593438876
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1979452461
Short name T2472
Test name
Test status
Simulation time 57341798 ps
CPU time 0.74 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:52 PM PDT 24
Peak memory 206860 kb
Host smart-92b868d1-56f3-40a3-bdf1-9753dc1fab3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
52461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1979452461
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.610003880
Short name T1728
Test name
Test status
Simulation time 1130493657 ps
CPU time 2.32 seconds
Started Jul 14 07:21:24 PM PDT 24
Finished Jul 14 07:21:46 PM PDT 24
Peak memory 207192 kb
Host smart-30057a1c-2316-40e9-82e0-eafb1d4ed27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61000
3880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.610003880
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.255353122
Short name T1436
Test name
Test status
Simulation time 189826128 ps
CPU time 2.04 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 207032 kb
Host smart-64ee002c-94f5-4f7b-a405-9042df7b2262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25535
3122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.255353122
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1890089112
Short name T1277
Test name
Test status
Simulation time 174508533 ps
CPU time 0.85 seconds
Started Jul 14 07:21:26 PM PDT 24
Finished Jul 14 07:21:47 PM PDT 24
Peak memory 206868 kb
Host smart-96c5b360-05a5-478f-9ef7-3965c53da353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18900
89112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1890089112
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3800968493
Short name T850
Test name
Test status
Simulation time 150259549 ps
CPU time 0.76 seconds
Started Jul 14 07:21:26 PM PDT 24
Finished Jul 14 07:21:47 PM PDT 24
Peak memory 206868 kb
Host smart-1319779d-dd3a-496a-80c2-d07fb87790aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
68493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3800968493
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3190133319
Short name T1906
Test name
Test status
Simulation time 251585963 ps
CPU time 0.94 seconds
Started Jul 14 07:21:20 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206860 kb
Host smart-cce60a5b-8975-4cba-8ddf-3232a759f448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31901
33319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3190133319
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.1214172420
Short name T1358
Test name
Test status
Simulation time 9572546294 ps
CPU time 80.36 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:23:04 PM PDT 24
Peak memory 207144 kb
Host smart-68685ebb-db22-4f4c-acbb-189ff38f896a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12141
72420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1214172420
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1491066115
Short name T1581
Test name
Test status
Simulation time 197567607 ps
CPU time 0.88 seconds
Started Jul 14 07:21:23 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206880 kb
Host smart-e02bcdb3-a7dc-4e19-9590-45e8c51eb019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14910
66115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1491066115
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2303183307
Short name T2264
Test name
Test status
Simulation time 23302009268 ps
CPU time 22.77 seconds
Started Jul 14 07:21:30 PM PDT 24
Finished Jul 14 07:22:13 PM PDT 24
Peak memory 206932 kb
Host smart-8631f587-39da-4661-9a11-e78c1ec16b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23031
83307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2303183307
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2719460856
Short name T1630
Test name
Test status
Simulation time 3326083995 ps
CPU time 4 seconds
Started Jul 14 07:22:08 PM PDT 24
Finished Jul 14 07:22:37 PM PDT 24
Peak memory 206964 kb
Host smart-f0c4ec64-9f81-4d81-8673-10b58f3c30c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27194
60856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2719460856
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.958188147
Short name T715
Test name
Test status
Simulation time 12440719144 ps
CPU time 97.32 seconds
Started Jul 14 07:21:26 PM PDT 24
Finished Jul 14 07:23:24 PM PDT 24
Peak memory 207148 kb
Host smart-6690f980-e62a-45a4-9aab-66da0c78c795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95818
8147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.958188147
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3417859149
Short name T2019
Test name
Test status
Simulation time 5123973025 ps
CPU time 135.8 seconds
Started Jul 14 07:21:24 PM PDT 24
Finished Jul 14 07:24:00 PM PDT 24
Peak memory 207048 kb
Host smart-9cba97b0-71c6-44d1-9d6c-7c4a2160b7bc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3417859149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3417859149
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3605778400
Short name T941
Test name
Test status
Simulation time 244828675 ps
CPU time 0.93 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206808 kb
Host smart-ebaff456-2cb1-45ca-ba80-d994d497dd60
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3605778400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3605778400
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.485462463
Short name T2631
Test name
Test status
Simulation time 189623829 ps
CPU time 0.81 seconds
Started Jul 14 07:21:25 PM PDT 24
Finished Jul 14 07:21:46 PM PDT 24
Peak memory 206876 kb
Host smart-6b9a7831-ea79-4b59-9a2e-fe87a5c01701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48546
2463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.485462463
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1812418780
Short name T2199
Test name
Test status
Simulation time 4681827959 ps
CPU time 44.82 seconds
Started Jul 14 07:21:26 PM PDT 24
Finished Jul 14 07:22:31 PM PDT 24
Peak memory 207116 kb
Host smart-618792cb-efce-476e-953c-ee6dffe4bca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18124
18780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1812418780
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.29069128
Short name T2065
Test name
Test status
Simulation time 5042147734 ps
CPU time 37.09 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:22:27 PM PDT 24
Peak memory 207128 kb
Host smart-836c9751-2adc-497d-8beb-f26442270a0e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=29069128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.29069128
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.748336040
Short name T793
Test name
Test status
Simulation time 161417534 ps
CPU time 0.84 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:51 PM PDT 24
Peak memory 206868 kb
Host smart-55238931-efe4-4232-839d-bbd18afb2915
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=748336040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.748336040
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1845559194
Short name T2259
Test name
Test status
Simulation time 154504326 ps
CPU time 0.76 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206868 kb
Host smart-3b9b81c6-6eb7-4f66-9e89-759085bb1308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18455
59194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1845559194
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2881606727
Short name T119
Test name
Test status
Simulation time 246772984 ps
CPU time 0.97 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206872 kb
Host smart-3772ba01-880f-49e0-ad45-71ff0912a9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28816
06727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2881606727
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2866660693
Short name T1409
Test name
Test status
Simulation time 177635868 ps
CPU time 0.79 seconds
Started Jul 14 07:21:30 PM PDT 24
Finished Jul 14 07:21:51 PM PDT 24
Peak memory 206868 kb
Host smart-f30f6608-d354-44cf-ae45-e8910e0ef582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28666
60693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2866660693
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2615159669
Short name T619
Test name
Test status
Simulation time 187574934 ps
CPU time 0.79 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:21:57 PM PDT 24
Peak memory 206892 kb
Host smart-4b592d01-d0cc-4626-8992-33701e99cca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26151
59669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2615159669
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3644820475
Short name T1666
Test name
Test status
Simulation time 167188457 ps
CPU time 0.77 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 206868 kb
Host smart-5461e53a-6fb7-4843-883e-4ba0867c0257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36448
20475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3644820475
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3585894174
Short name T1836
Test name
Test status
Simulation time 221209107 ps
CPU time 0.82 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:21:57 PM PDT 24
Peak memory 206892 kb
Host smart-2df05fd9-5f7f-4bdd-995f-6058e1fe299c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35858
94174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3585894174
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3789671366
Short name T401
Test name
Test status
Simulation time 220232697 ps
CPU time 0.88 seconds
Started Jul 14 07:21:34 PM PDT 24
Finished Jul 14 07:21:55 PM PDT 24
Peak memory 206912 kb
Host smart-af3134ce-d421-49d8-bfb9-1fff69a5a5c4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3789671366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3789671366
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3729583051
Short name T2396
Test name
Test status
Simulation time 139934710 ps
CPU time 0.73 seconds
Started Jul 14 07:21:34 PM PDT 24
Finished Jul 14 07:21:55 PM PDT 24
Peak memory 206908 kb
Host smart-f6e1f30e-ae0c-48e6-bbaf-34601abab80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37295
83051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3729583051
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2048261281
Short name T1024
Test name
Test status
Simulation time 29224519 ps
CPU time 0.62 seconds
Started Jul 14 07:21:34 PM PDT 24
Finished Jul 14 07:21:55 PM PDT 24
Peak memory 206908 kb
Host smart-8ad2470c-75db-4a14-9aa7-939d6996506a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482
61281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2048261281
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.871196923
Short name T245
Test name
Test status
Simulation time 11153720410 ps
CPU time 26.34 seconds
Started Jul 14 07:21:25 PM PDT 24
Finished Jul 14 07:22:11 PM PDT 24
Peak memory 215324 kb
Host smart-2945c9d0-119f-43a7-87e6-68d6c7e0576f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87119
6923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.871196923
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1426259708
Short name T991
Test name
Test status
Simulation time 157695322 ps
CPU time 0.77 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206864 kb
Host smart-a1d57abf-f206-45f7-b11d-f926bec4d83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
59708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1426259708
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1173154558
Short name T1432
Test name
Test status
Simulation time 185633291 ps
CPU time 0.82 seconds
Started Jul 14 07:21:21 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206852 kb
Host smart-bd0da065-1154-49c8-b373-cc0d17a8db92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11731
54558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1173154558
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.184371620
Short name T1144
Test name
Test status
Simulation time 201128354 ps
CPU time 0.83 seconds
Started Jul 14 07:21:24 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206856 kb
Host smart-3f8ffdc2-27dc-4efa-9a9d-e21439132e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18437
1620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.184371620
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.4189117639
Short name T2628
Test name
Test status
Simulation time 188373158 ps
CPU time 0.93 seconds
Started Jul 14 07:21:21 PM PDT 24
Finished Jul 14 07:21:42 PM PDT 24
Peak memory 206836 kb
Host smart-7a4400f8-3e84-4792-94ea-5348f5bb40f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41891
17639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.4189117639
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2300075229
Short name T2477
Test name
Test status
Simulation time 174001114 ps
CPU time 0.8 seconds
Started Jul 14 07:21:22 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206892 kb
Host smart-0de4637e-fa53-4816-a1bd-b5e99ed69e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23000
75229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2300075229
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1990490651
Short name T2563
Test name
Test status
Simulation time 167222650 ps
CPU time 0.8 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 206888 kb
Host smart-cfc69b45-e40c-416a-b799-9375186d0881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19904
90651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1990490651
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1313417641
Short name T1509
Test name
Test status
Simulation time 157568927 ps
CPU time 0.77 seconds
Started Jul 14 07:21:23 PM PDT 24
Finished Jul 14 07:21:44 PM PDT 24
Peak memory 206868 kb
Host smart-9ecea1ea-ebc7-44fa-9c28-76abaa5e6bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
17641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1313417641
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2736449337
Short name T140
Test name
Test status
Simulation time 200423290 ps
CPU time 0.89 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 206888 kb
Host smart-78ae2161-3cfb-4564-bc65-b5c9cd9592ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27364
49337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2736449337
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.616444417
Short name T2220
Test name
Test status
Simulation time 5691017736 ps
CPU time 41.46 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:22:38 PM PDT 24
Peak memory 207152 kb
Host smart-549231df-77d1-4bf0-9167-84a0ebcdc392
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=616444417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.616444417
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.4054716661
Short name T2217
Test name
Test status
Simulation time 223739762 ps
CPU time 0.86 seconds
Started Jul 14 07:21:25 PM PDT 24
Finished Jul 14 07:21:47 PM PDT 24
Peak memory 206888 kb
Host smart-b4748a65-4b25-479b-b9af-574772da220a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40547
16661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.4054716661
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.4208901497
Short name T1652
Test name
Test status
Simulation time 178770161 ps
CPU time 0.81 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206836 kb
Host smart-50877ea8-854d-41e6-a7a6-936fe15791a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42089
01497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.4208901497
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.193030136
Short name T1788
Test name
Test status
Simulation time 200843924 ps
CPU time 0.86 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 206868 kb
Host smart-80c05c7d-42b4-4d29-9250-451f7b39b63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19303
0136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.193030136
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1941308458
Short name T2459
Test name
Test status
Simulation time 5027770785 ps
CPU time 47.29 seconds
Started Jul 14 07:21:29 PM PDT 24
Finished Jul 14 07:22:37 PM PDT 24
Peak memory 207136 kb
Host smart-1f487db7-28eb-40a8-87ec-33f9e4df116d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19413
08458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1941308458
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.1713278898
Short name T788
Test name
Test status
Simulation time 36138006 ps
CPU time 0.68 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206900 kb
Host smart-24e741b3-3ce8-432c-b979-a30b348eeb6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1713278898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1713278898
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2235269354
Short name T1347
Test name
Test status
Simulation time 3796268655 ps
CPU time 4.88 seconds
Started Jul 14 07:21:30 PM PDT 24
Finished Jul 14 07:21:54 PM PDT 24
Peak memory 206912 kb
Host smart-9c87be22-82fb-4a3a-912e-82065b8b9741
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2235269354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2235269354
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3676600642
Short name T2082
Test name
Test status
Simulation time 13409762885 ps
CPU time 12.11 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:22:00 PM PDT 24
Peak memory 207128 kb
Host smart-2cf39d67-ca53-4a1d-a5d8-fcedc6842cba
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3676600642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3676600642
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2791700557
Short name T1502
Test name
Test status
Simulation time 23415877745 ps
CPU time 27.72 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:22:16 PM PDT 24
Peak memory 206940 kb
Host smart-36162574-328c-43fe-bdd4-385e0b488470
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2791700557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.2791700557
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.4135777962
Short name T867
Test name
Test status
Simulation time 190540646 ps
CPU time 0.89 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206964 kb
Host smart-e4853c35-7915-433d-9a16-f3fcaff018cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
77962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.4135777962
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2290356653
Short name T2439
Test name
Test status
Simulation time 154680310 ps
CPU time 0.82 seconds
Started Jul 14 07:21:37 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 206916 kb
Host smart-313bd028-e371-4d83-9eef-8eea42510f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22903
56653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2290356653
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2127247789
Short name T2500
Test name
Test status
Simulation time 252577264 ps
CPU time 1 seconds
Started Jul 14 07:21:32 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206960 kb
Host smart-d36d2b09-a523-4508-a421-0579651d57fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21272
47789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2127247789
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3268726166
Short name T1634
Test name
Test status
Simulation time 1289300399 ps
CPU time 2.85 seconds
Started Jul 14 07:21:39 PM PDT 24
Finished Jul 14 07:22:02 PM PDT 24
Peak memory 207036 kb
Host smart-de9d7023-0d2e-4386-b112-0471bfe95e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32687
26166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3268726166
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.1715930551
Short name T152
Test name
Test status
Simulation time 19377031441 ps
CPU time 40 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:22:28 PM PDT 24
Peak memory 207304 kb
Host smart-bab4b7cf-9020-4189-b80f-963d81b2af33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17159
30551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1715930551
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2467717928
Short name T2236
Test name
Test status
Simulation time 336227171 ps
CPU time 1.11 seconds
Started Jul 14 07:21:32 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206964 kb
Host smart-9a508d90-e290-4866-bba1-39629bfcb16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
17928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2467717928
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2566136874
Short name T1811
Test name
Test status
Simulation time 139936177 ps
CPU time 0.78 seconds
Started Jul 14 07:21:26 PM PDT 24
Finished Jul 14 07:21:47 PM PDT 24
Peak memory 206856 kb
Host smart-c11a36f7-b85f-42f2-8ca2-702b8e900e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25661
36874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2566136874
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.855520198
Short name T805
Test name
Test status
Simulation time 88026148 ps
CPU time 0.73 seconds
Started Jul 14 07:21:29 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 206876 kb
Host smart-6282fc71-751c-4f7b-9664-28f5f1b9945c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85552
0198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.855520198
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.721263765
Short name T2412
Test name
Test status
Simulation time 736402344 ps
CPU time 1.85 seconds
Started Jul 14 07:21:27 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 207032 kb
Host smart-fd445141-1c0f-4f0f-9794-8b39f813d492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72126
3765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.721263765
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1536390662
Short name T1773
Test name
Test status
Simulation time 252756792 ps
CPU time 1.82 seconds
Started Jul 14 07:21:39 PM PDT 24
Finished Jul 14 07:22:00 PM PDT 24
Peak memory 207032 kb
Host smart-85ac0bd1-644a-4cf9-b7d3-06cbc00b35b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15363
90662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1536390662
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.320840357
Short name T2670
Test name
Test status
Simulation time 252057549 ps
CPU time 0.91 seconds
Started Jul 14 07:21:39 PM PDT 24
Finished Jul 14 07:22:00 PM PDT 24
Peak memory 206852 kb
Host smart-c3775628-fcc8-41d4-b814-48e7971e0bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32084
0357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.320840357
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1921949726
Short name T303
Test name
Test status
Simulation time 149170219 ps
CPU time 0.73 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 206888 kb
Host smart-a913c1ec-e816-45cf-a460-96e0da84bede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19219
49726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1921949726
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2710200382
Short name T1104
Test name
Test status
Simulation time 224358135 ps
CPU time 0.89 seconds
Started Jul 14 07:21:39 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 206788 kb
Host smart-95bea395-f227-4783-bf3b-70f90b4692dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27102
00382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2710200382
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.3273783128
Short name T1719
Test name
Test status
Simulation time 9000384782 ps
CPU time 33.39 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:22:25 PM PDT 24
Peak memory 207108 kb
Host smart-67e4e220-c016-422e-a9ee-71e61aa61648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32737
83128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.3273783128
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.4171257501
Short name T752
Test name
Test status
Simulation time 189440062 ps
CPU time 0.9 seconds
Started Jul 14 07:21:29 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 207044 kb
Host smart-4f89a728-c71c-46c5-8317-13e77789cddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41712
57501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.4171257501
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.3895786481
Short name T1701
Test name
Test status
Simulation time 23335975581 ps
CPU time 25.09 seconds
Started Jul 14 07:21:27 PM PDT 24
Finished Jul 14 07:22:13 PM PDT 24
Peak memory 206936 kb
Host smart-0e2793a2-e00b-4cd7-9f7d-3f63f63746a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
86481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3895786481
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3686185719
Short name T375
Test name
Test status
Simulation time 3319431110 ps
CPU time 3.51 seconds
Started Jul 14 07:21:29 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206944 kb
Host smart-a60d87cd-1a6b-467f-adad-63fb3aa532c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36861
85719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3686185719
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1758660327
Short name T1957
Test name
Test status
Simulation time 11798187445 ps
CPU time 80.09 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:23:18 PM PDT 24
Peak memory 207148 kb
Host smart-c3d17660-8ec4-42f6-93d7-22644c77bc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17586
60327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1758660327
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.859052445
Short name T849
Test name
Test status
Simulation time 3128918846 ps
CPU time 85.96 seconds
Started Jul 14 07:21:27 PM PDT 24
Finished Jul 14 07:23:14 PM PDT 24
Peak memory 207064 kb
Host smart-f2d9ad51-50a7-4c27-9654-947f5b68ef3c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=859052445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.859052445
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1091799707
Short name T1643
Test name
Test status
Simulation time 252860532 ps
CPU time 0.92 seconds
Started Jul 14 07:21:37 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 206912 kb
Host smart-5189ed43-c6ea-4eff-8098-853e0bcb75f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1091799707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1091799707
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1222274674
Short name T2679
Test name
Test status
Simulation time 219538222 ps
CPU time 0.93 seconds
Started Jul 14 07:21:34 PM PDT 24
Finished Jul 14 07:21:54 PM PDT 24
Peak memory 206868 kb
Host smart-02af80a8-2a82-48aa-9130-a8cfe316e49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12222
74674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1222274674
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.3269691132
Short name T817
Test name
Test status
Simulation time 4639260511 ps
CPU time 129.25 seconds
Started Jul 14 07:21:42 PM PDT 24
Finished Jul 14 07:24:11 PM PDT 24
Peak memory 207068 kb
Host smart-90e444c8-1925-4db3-b380-1441daf8117c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32696
91132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.3269691132
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2037022885
Short name T1275
Test name
Test status
Simulation time 4877576202 ps
CPU time 132.47 seconds
Started Jul 14 07:21:32 PM PDT 24
Finished Jul 14 07:24:05 PM PDT 24
Peak memory 207092 kb
Host smart-f35af3cf-9736-40d2-bf4e-bc6bc598584b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2037022885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2037022885
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.1114548788
Short name T504
Test name
Test status
Simulation time 164130614 ps
CPU time 0.84 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 206864 kb
Host smart-fd91c669-cc5e-4eae-a8ea-6c86ba980396
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1114548788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.1114548788
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.143490619
Short name T1698
Test name
Test status
Simulation time 184291163 ps
CPU time 0.81 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206944 kb
Host smart-88999c30-0a33-48f3-a9af-3d9be7b32403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14349
0619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.143490619
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1680282433
Short name T2605
Test name
Test status
Simulation time 167995528 ps
CPU time 0.83 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 206808 kb
Host smart-d78ecfdf-9768-4dfc-9788-9575a81314e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16802
82433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1680282433
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3586714133
Short name T1981
Test name
Test status
Simulation time 227336291 ps
CPU time 0.91 seconds
Started Jul 14 07:21:29 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 206872 kb
Host smart-c6363827-b924-44dc-9dd2-4832492d26aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35867
14133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3586714133
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.223928852
Short name T1364
Test name
Test status
Simulation time 168810208 ps
CPU time 0.81 seconds
Started Jul 14 07:21:37 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 206912 kb
Host smart-cda5d9b0-3824-411d-b737-19df9156806f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22392
8852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.223928852
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3638070146
Short name T435
Test name
Test status
Simulation time 179857664 ps
CPU time 0.85 seconds
Started Jul 14 07:21:39 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 206768 kb
Host smart-4c9482e1-0ca0-4cdd-b723-5e8cb9cf59b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36380
70146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3638070146
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2051990244
Short name T835
Test name
Test status
Simulation time 152024906 ps
CPU time 0.78 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 206868 kb
Host smart-39a6a930-65b0-491c-8eb2-2325d7c721b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20519
90244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2051990244
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3851583144
Short name T1198
Test name
Test status
Simulation time 211017910 ps
CPU time 0.9 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 206840 kb
Host smart-e6f89618-4400-462f-8989-cc0d50784132
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3851583144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3851583144
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3179270338
Short name T192
Test name
Test status
Simulation time 168680519 ps
CPU time 0.76 seconds
Started Jul 14 07:21:30 PM PDT 24
Finished Jul 14 07:21:51 PM PDT 24
Peak memory 206868 kb
Host smart-a39bf469-0a71-4c87-b09c-485bdeb472c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31792
70338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3179270338
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3375033241
Short name T2324
Test name
Test status
Simulation time 37387330 ps
CPU time 0.66 seconds
Started Jul 14 07:21:32 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206952 kb
Host smart-b7135258-fe94-41a7-ae1c-c376e79b513f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33750
33241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3375033241
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2797521451
Short name T1352
Test name
Test status
Simulation time 12062813114 ps
CPU time 27.7 seconds
Started Jul 14 07:21:37 PM PDT 24
Finished Jul 14 07:22:25 PM PDT 24
Peak memory 207156 kb
Host smart-c8936604-0592-48fd-8e1c-1aa83ea6bab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27975
21451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2797521451
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2830047169
Short name T2191
Test name
Test status
Simulation time 212395229 ps
CPU time 0.87 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 206876 kb
Host smart-f43a934c-a4a5-4549-abf4-45a81b886c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28300
47169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2830047169
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1313717270
Short name T1398
Test name
Test status
Simulation time 272465683 ps
CPU time 0.91 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 206824 kb
Host smart-b183f210-87f4-47f2-b594-76c26e6d5e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137
17270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1313717270
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3017095038
Short name T2723
Test name
Test status
Simulation time 204119225 ps
CPU time 0.86 seconds
Started Jul 14 07:21:27 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 206884 kb
Host smart-bf677215-45bc-4406-bf8a-d704bc80c166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30170
95038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3017095038
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.475774146
Short name T1917
Test name
Test status
Simulation time 151401003 ps
CPU time 0.82 seconds
Started Jul 14 07:21:29 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 206872 kb
Host smart-8e2b5158-7a57-4c1c-a7dc-b6104c9c83d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47577
4146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.475774146
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.944542283
Short name T3
Test name
Test status
Simulation time 157182860 ps
CPU time 0.76 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:21:55 PM PDT 24
Peak memory 206872 kb
Host smart-4d232676-aecc-4091-9d57-19c17e6665c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94454
2283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.944542283
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1560377457
Short name T978
Test name
Test status
Simulation time 215528405 ps
CPU time 0.82 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206800 kb
Host smart-c4f152bb-b619-4943-bc4c-43302e8390bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
77457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1560377457
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2091123314
Short name T1819
Test name
Test status
Simulation time 153749578 ps
CPU time 0.77 seconds
Started Jul 14 07:21:29 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 206880 kb
Host smart-21c9f6f7-d5bd-492e-b90e-a6bd24c318cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20911
23314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2091123314
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1485893010
Short name T686
Test name
Test status
Simulation time 233145599 ps
CPU time 0.94 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 206864 kb
Host smart-59a60c5d-0980-4657-87a8-a2665c8ca871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14858
93010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1485893010
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.852769520
Short name T795
Test name
Test status
Simulation time 5899428446 ps
CPU time 40.81 seconds
Started Jul 14 07:21:33 PM PDT 24
Finished Jul 14 07:22:34 PM PDT 24
Peak memory 207136 kb
Host smart-8a38b356-6d36-498f-af28-01a86f318fc4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=852769520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.852769520
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.482740436
Short name T2687
Test name
Test status
Simulation time 185741089 ps
CPU time 0.84 seconds
Started Jul 14 07:21:28 PM PDT 24
Finished Jul 14 07:21:50 PM PDT 24
Peak memory 206828 kb
Host smart-f24d94b0-9401-43d4-9bdf-8e3c1868c478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48274
0436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.482740436
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.94754626
Short name T1154
Test name
Test status
Simulation time 191512714 ps
CPU time 0.82 seconds
Started Jul 14 07:21:34 PM PDT 24
Finished Jul 14 07:21:55 PM PDT 24
Peak memory 206872 kb
Host smart-4a0d16b9-55ec-4242-8b9e-49800f213183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94754
626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.94754626
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.3386523300
Short name T1586
Test name
Test status
Simulation time 1035614414 ps
CPU time 2.19 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:21:56 PM PDT 24
Peak memory 207068 kb
Host smart-76d6bd27-26b1-485a-a4f7-c6c50b52adfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33865
23300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.3386523300
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1781830810
Short name T2592
Test name
Test status
Simulation time 5405836596 ps
CPU time 147.6 seconds
Started Jul 14 07:21:32 PM PDT 24
Finished Jul 14 07:24:25 PM PDT 24
Peak memory 207088 kb
Host smart-9e9e6f52-8c5f-49cc-8f22-2ec6d95c40ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
30810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1781830810
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.4010436542
Short name T1844
Test name
Test status
Simulation time 100565957 ps
CPU time 0.69 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 206924 kb
Host smart-fcfd2c05-13d6-4883-a095-76779c1eadc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4010436542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.4010436542
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.4010020268
Short name T943
Test name
Test status
Simulation time 3437726486 ps
CPU time 3.81 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 207064 kb
Host smart-2d2ce49e-1a28-49c9-866d-d0615d749905
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4010020268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.4010020268
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2421284284
Short name T729
Test name
Test status
Simulation time 13392692887 ps
CPU time 15.82 seconds
Started Jul 14 07:21:34 PM PDT 24
Finished Jul 14 07:22:09 PM PDT 24
Peak memory 206956 kb
Host smart-69439692-2fa7-40ff-ab04-e5c8bc061e59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2421284284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2421284284
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3291387200
Short name T1302
Test name
Test status
Simulation time 23387406243 ps
CPU time 23.93 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:22:18 PM PDT 24
Peak memory 206912 kb
Host smart-7463557c-9a58-4eef-8c41-f23936cc6978
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3291387200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3291387200
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1106650556
Short name T2314
Test name
Test status
Simulation time 193890290 ps
CPU time 0.8 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:21:57 PM PDT 24
Peak memory 206840 kb
Host smart-282b256f-f186-4c10-b511-ba0dc271ebf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11066
50556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1106650556
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.221698384
Short name T1967
Test name
Test status
Simulation time 159081678 ps
CPU time 0.77 seconds
Started Jul 14 07:21:49 PM PDT 24
Finished Jul 14 07:22:08 PM PDT 24
Peak memory 206856 kb
Host smart-3cb68865-95cc-41f4-9c6e-9465d5e30b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22169
8384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.221698384
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2617470800
Short name T2433
Test name
Test status
Simulation time 250463443 ps
CPU time 0.92 seconds
Started Jul 14 07:21:49 PM PDT 24
Finished Jul 14 07:22:09 PM PDT 24
Peak memory 206808 kb
Host smart-a2267abc-f2d2-4874-bb2d-b12855df94ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26174
70800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2617470800
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.513191389
Short name T1331
Test name
Test status
Simulation time 702045057 ps
CPU time 1.95 seconds
Started Jul 14 07:21:47 PM PDT 24
Finished Jul 14 07:22:08 PM PDT 24
Peak memory 207036 kb
Host smart-3e4aaad7-8744-41ab-a278-aeb21d40bda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51319
1389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.513191389
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1565537227
Short name T1108
Test name
Test status
Simulation time 18883759712 ps
CPU time 35.34 seconds
Started Jul 14 07:21:32 PM PDT 24
Finished Jul 14 07:22:27 PM PDT 24
Peak memory 207108 kb
Host smart-83f806e3-2798-4c98-81da-d62998f1c5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15655
37227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1565537227
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3991877093
Short name T876
Test name
Test status
Simulation time 433726985 ps
CPU time 1.5 seconds
Started Jul 14 07:21:41 PM PDT 24
Finished Jul 14 07:22:02 PM PDT 24
Peak memory 206860 kb
Host smart-eb62bbda-b224-4b42-b3dc-178240fd19e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
77093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3991877093
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.2148420803
Short name T2621
Test name
Test status
Simulation time 136546458 ps
CPU time 0.73 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:56 PM PDT 24
Peak memory 206872 kb
Host smart-ffb759e2-7aa5-4534-af7c-efff3ecf6fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21484
20803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2148420803
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1908619006
Short name T923
Test name
Test status
Simulation time 43016464 ps
CPU time 0.67 seconds
Started Jul 14 07:21:32 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206868 kb
Host smart-fef5b603-452c-4e9d-a8e4-2f4f111967b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19086
19006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1908619006
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2525415606
Short name T2258
Test name
Test status
Simulation time 983646409 ps
CPU time 2 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:21:57 PM PDT 24
Peak memory 206960 kb
Host smart-10b01f5b-509d-435f-841f-e0036c5f28b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25254
15606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2525415606
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.910523630
Short name T1133
Test name
Test status
Simulation time 228345297 ps
CPU time 1.51 seconds
Started Jul 14 07:21:47 PM PDT 24
Finished Jul 14 07:22:08 PM PDT 24
Peak memory 206984 kb
Host smart-c532526e-4c36-4eb0-a09e-254dff750796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91052
3630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.910523630
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2133966120
Short name T2587
Test name
Test status
Simulation time 188554766 ps
CPU time 0.8 seconds
Started Jul 14 07:21:42 PM PDT 24
Finished Jul 14 07:22:02 PM PDT 24
Peak memory 206868 kb
Host smart-5ca6002f-42a3-4861-b9f6-c6c256003eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21339
66120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2133966120
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2409164185
Short name T1770
Test name
Test status
Simulation time 169503272 ps
CPU time 0.77 seconds
Started Jul 14 07:21:45 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 206864 kb
Host smart-c48e08d3-7e2e-42b3-b111-9bc269877222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24091
64185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2409164185
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1262339840
Short name T1290
Test name
Test status
Simulation time 216812764 ps
CPU time 0.93 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:51 PM PDT 24
Peak memory 206860 kb
Host smart-6bdc40ec-eee8-4868-b159-a5013d7ef017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
39840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1262339840
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1344885415
Short name T214
Test name
Test status
Simulation time 5787564602 ps
CPU time 54.49 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:22:49 PM PDT 24
Peak memory 207116 kb
Host smart-72d003c3-e0e2-4260-b596-dccd7e11481f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1344885415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1344885415
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3671391992
Short name T1999
Test name
Test status
Simulation time 251273056 ps
CPU time 0.92 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:21:58 PM PDT 24
Peak memory 206820 kb
Host smart-26270f00-ab49-4c15-a2b7-8b5d55ed8635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713
91992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3671391992
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2842261917
Short name T1968
Test name
Test status
Simulation time 23358415852 ps
CPU time 23.12 seconds
Started Jul 14 07:21:53 PM PDT 24
Finished Jul 14 07:22:36 PM PDT 24
Peak memory 206932 kb
Host smart-71c41cb5-6940-4e28-9e13-745a5db80ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28422
61917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2842261917
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2111271831
Short name T1209
Test name
Test status
Simulation time 3381239592 ps
CPU time 3.93 seconds
Started Jul 14 07:21:47 PM PDT 24
Finished Jul 14 07:22:10 PM PDT 24
Peak memory 206932 kb
Host smart-6390fdc5-875c-4ace-893a-73b697f6dff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21112
71831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2111271831
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2388124324
Short name T583
Test name
Test status
Simulation time 7848695031 ps
CPU time 71.76 seconds
Started Jul 14 07:21:36 PM PDT 24
Finished Jul 14 07:23:08 PM PDT 24
Peak memory 207128 kb
Host smart-36d2abd3-4af9-4838-892b-288eeff1575d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23881
24324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2388124324
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2701743137
Short name T2622
Test name
Test status
Simulation time 4961771693 ps
CPU time 136.26 seconds
Started Jul 14 07:21:33 PM PDT 24
Finished Jul 14 07:24:09 PM PDT 24
Peak memory 207044 kb
Host smart-1471a3b4-c62d-412b-aa5b-63f24cc5e9b5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2701743137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2701743137
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3512993434
Short name T1296
Test name
Test status
Simulation time 242110476 ps
CPU time 0.92 seconds
Started Jul 14 07:21:52 PM PDT 24
Finished Jul 14 07:22:13 PM PDT 24
Peak memory 206864 kb
Host smart-48602c36-6744-4e4a-9b7a-2ea6b1f6407c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3512993434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3512993434
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1214671174
Short name T1202
Test name
Test status
Simulation time 211580152 ps
CPU time 0.95 seconds
Started Jul 14 07:21:45 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 206872 kb
Host smart-5abe421f-cbac-4251-85ff-507cef4c6e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12146
71174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1214671174
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3282158710
Short name T987
Test name
Test status
Simulation time 4835973515 ps
CPU time 135.4 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:24:10 PM PDT 24
Peak memory 207048 kb
Host smart-ac35c0e6-3fdc-4a6f-b60e-4cf14d9d9fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32821
58710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3282158710
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.1233844059
Short name T1577
Test name
Test status
Simulation time 5860931475 ps
CPU time 166.11 seconds
Started Jul 14 07:21:52 PM PDT 24
Finished Jul 14 07:24:58 PM PDT 24
Peak memory 207088 kb
Host smart-bba0fe46-cef9-417e-8974-9de9222449b3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1233844059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.1233844059
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.3130679072
Short name T1471
Test name
Test status
Simulation time 164056735 ps
CPU time 0.84 seconds
Started Jul 14 07:21:51 PM PDT 24
Finished Jul 14 07:22:12 PM PDT 24
Peak memory 206860 kb
Host smart-ceb9cff7-54f5-462a-97ee-a98ba5ab20ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3130679072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.3130679072
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1848031207
Short name T472
Test name
Test status
Simulation time 164805589 ps
CPU time 0.83 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:21:56 PM PDT 24
Peak memory 206856 kb
Host smart-67081e82-35b1-4339-a750-8debf2a23399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18480
31207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1848031207
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.45964642
Short name T115
Test name
Test status
Simulation time 222525244 ps
CPU time 0.87 seconds
Started Jul 14 07:21:35 PM PDT 24
Finished Jul 14 07:21:55 PM PDT 24
Peak memory 206848 kb
Host smart-adf02b61-7a85-41b1-ac43-1265ede7513c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45964
642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.45964642
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1364445326
Short name T1063
Test name
Test status
Simulation time 209482348 ps
CPU time 0.9 seconds
Started Jul 14 07:21:46 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 206808 kb
Host smart-48b301d2-5157-4f87-b92e-a5e2e7ee6722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
45326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1364445326
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1548730066
Short name T924
Test name
Test status
Simulation time 174437137 ps
CPU time 0.81 seconds
Started Jul 14 07:21:31 PM PDT 24
Finished Jul 14 07:21:53 PM PDT 24
Peak memory 206852 kb
Host smart-9cb8aaec-35d7-4cbd-889e-d0b5897611dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15487
30066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1548730066
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3215400325
Short name T2142
Test name
Test status
Simulation time 216130760 ps
CPU time 0.83 seconds
Started Jul 14 07:21:51 PM PDT 24
Finished Jul 14 07:22:12 PM PDT 24
Peak memory 206892 kb
Host smart-a7369b17-ccd9-4b71-96a3-88ebf1b0dea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
00325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3215400325
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3229628753
Short name T1690
Test name
Test status
Simulation time 160326387 ps
CPU time 0.76 seconds
Started Jul 14 07:21:46 PM PDT 24
Finished Jul 14 07:22:07 PM PDT 24
Peak memory 206896 kb
Host smart-28beb48b-12cc-42f8-9374-2d64bac9f2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32296
28753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3229628753
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1935893967
Short name T2583
Test name
Test status
Simulation time 201607286 ps
CPU time 0.95 seconds
Started Jul 14 07:21:40 PM PDT 24
Finished Jul 14 07:22:00 PM PDT 24
Peak memory 206864 kb
Host smart-79d5de32-3d2a-451a-934e-15c75f9a096d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1935893967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1935893967
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3585479026
Short name T1268
Test name
Test status
Simulation time 148821254 ps
CPU time 0.78 seconds
Started Jul 14 07:21:53 PM PDT 24
Finished Jul 14 07:22:14 PM PDT 24
Peak memory 206880 kb
Host smart-9c577245-bbfe-41af-949d-1c2f6c644eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35854
79026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3585479026
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1838920140
Short name T491
Test name
Test status
Simulation time 47924338 ps
CPU time 0.7 seconds
Started Jul 14 07:21:41 PM PDT 24
Finished Jul 14 07:22:02 PM PDT 24
Peak memory 206888 kb
Host smart-0edd5091-233d-46de-94e7-8509464afea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18389
20140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1838920140
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2537402035
Short name T1851
Test name
Test status
Simulation time 17059340586 ps
CPU time 37.23 seconds
Started Jul 14 07:22:07 PM PDT 24
Finished Jul 14 07:23:09 PM PDT 24
Peak memory 207176 kb
Host smart-9a40c882-d59a-484a-8dec-451711b4b4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25374
02035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2537402035
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1122372640
Short name T1184
Test name
Test status
Simulation time 175338927 ps
CPU time 0.79 seconds
Started Jul 14 07:22:00 PM PDT 24
Finished Jul 14 07:22:23 PM PDT 24
Peak memory 206872 kb
Host smart-6234efe6-e8ff-4b71-8d75-28f44be4ad10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11223
72640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1122372640
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1401223249
Short name T1708
Test name
Test status
Simulation time 221514717 ps
CPU time 0.84 seconds
Started Jul 14 07:21:40 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 206888 kb
Host smart-437cee9b-b67a-4bb1-94f7-ef43f788b2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14012
23249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1401223249
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.754875346
Short name T1857
Test name
Test status
Simulation time 233926105 ps
CPU time 0.87 seconds
Started Jul 14 07:21:58 PM PDT 24
Finished Jul 14 07:22:18 PM PDT 24
Peak memory 206836 kb
Host smart-2ae43ee5-3c45-4bf2-a28f-67f6f0cc8bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75487
5346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.754875346
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1163104054
Short name T1902
Test name
Test status
Simulation time 157763708 ps
CPU time 0.78 seconds
Started Jul 14 07:21:56 PM PDT 24
Finished Jul 14 07:22:18 PM PDT 24
Peak memory 206860 kb
Host smart-47ea9901-b1e8-4613-a8c9-d307516949f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11631
04054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1163104054
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1292947730
Short name T839
Test name
Test status
Simulation time 152837138 ps
CPU time 0.77 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:21:59 PM PDT 24
Peak memory 206848 kb
Host smart-ffbc7a91-e75e-42c8-b944-798ff15803f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12929
47730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1292947730
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1335484245
Short name T794
Test name
Test status
Simulation time 151183709 ps
CPU time 0.81 seconds
Started Jul 14 07:21:50 PM PDT 24
Finished Jul 14 07:22:10 PM PDT 24
Peak memory 206872 kb
Host smart-5ee66241-ab5a-457b-80a6-a240128b6409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13354
84245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1335484245
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2351211355
Short name T443
Test name
Test status
Simulation time 159630976 ps
CPU time 0.81 seconds
Started Jul 14 07:21:50 PM PDT 24
Finished Jul 14 07:22:11 PM PDT 24
Peak memory 207044 kb
Host smart-bb0d0a1f-bb30-44db-816f-3a0fcc76cd3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23512
11355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2351211355
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2656549035
Short name T143
Test name
Test status
Simulation time 244510837 ps
CPU time 0.91 seconds
Started Jul 14 07:21:41 PM PDT 24
Finished Jul 14 07:22:02 PM PDT 24
Peak memory 206840 kb
Host smart-05ac410c-9d2d-4e2f-8b2e-c3a04fc32028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26565
49035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2656549035
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2253129585
Short name T519
Test name
Test status
Simulation time 6593685297 ps
CPU time 187.05 seconds
Started Jul 14 07:21:50 PM PDT 24
Finished Jul 14 07:25:18 PM PDT 24
Peak memory 207044 kb
Host smart-7211784f-28d2-4f5e-b534-d24a9e5aee16
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2253129585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2253129585
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.467030678
Short name T1565
Test name
Test status
Simulation time 172394917 ps
CPU time 0.78 seconds
Started Jul 14 07:21:41 PM PDT 24
Finished Jul 14 07:22:02 PM PDT 24
Peak memory 206832 kb
Host smart-8ff80eeb-a4dc-4eb8-b6cd-c91721af3be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46703
0678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.467030678
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1099525230
Short name T1711
Test name
Test status
Simulation time 167752380 ps
CPU time 0.78 seconds
Started Jul 14 07:21:55 PM PDT 24
Finished Jul 14 07:22:17 PM PDT 24
Peak memory 206864 kb
Host smart-4d9251a5-cb55-4b93-a69d-985772a5000b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10995
25230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1099525230
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.1942930283
Short name T1793
Test name
Test status
Simulation time 1312779548 ps
CPU time 3.12 seconds
Started Jul 14 07:21:41 PM PDT 24
Finished Jul 14 07:22:04 PM PDT 24
Peak memory 207068 kb
Host smart-c80297f2-a50f-4b0a-9c0d-b32b0f51231c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19429
30283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1942930283
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3913866732
Short name T1908
Test name
Test status
Simulation time 6282954816 ps
CPU time 174.75 seconds
Started Jul 14 07:21:37 PM PDT 24
Finished Jul 14 07:24:52 PM PDT 24
Peak memory 207056 kb
Host smart-046c46d5-2c63-4d8b-a9df-ac115dc84946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39138
66732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3913866732
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.2925724192
Short name T2378
Test name
Test status
Simulation time 43025181 ps
CPU time 0.66 seconds
Started Jul 14 07:22:05 PM PDT 24
Finished Jul 14 07:22:29 PM PDT 24
Peak memory 206924 kb
Host smart-f4eacc83-b2f4-49b9-87ea-86ea89e51ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2925724192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2925724192
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2036991337
Short name T1090
Test name
Test status
Simulation time 3592574861 ps
CPU time 3.96 seconds
Started Jul 14 07:21:40 PM PDT 24
Finished Jul 14 07:22:03 PM PDT 24
Peak memory 206896 kb
Host smart-75b6868f-5939-4881-83a9-aa4f1f42c52c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2036991337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.2036991337
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.761615065
Short name T2577
Test name
Test status
Simulation time 13336991656 ps
CPU time 12.38 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:22:09 PM PDT 24
Peak memory 206940 kb
Host smart-8c5916fb-92fb-48eb-bc91-ec1e0bcb9849
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=761615065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.761615065
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.204608446
Short name T865
Test name
Test status
Simulation time 23405041142 ps
CPU time 29.45 seconds
Started Jul 14 07:21:38 PM PDT 24
Finished Jul 14 07:22:27 PM PDT 24
Peak memory 206892 kb
Host smart-5276316e-b947-438d-bf21-33b14923e202
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=204608446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.204608446
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1524109328
Short name T1139
Test name
Test status
Simulation time 147674261 ps
CPU time 0.78 seconds
Started Jul 14 07:22:22 PM PDT 24
Finished Jul 14 07:22:49 PM PDT 24
Peak memory 206900 kb
Host smart-0f24a54d-8322-4f93-932f-4df7dde64945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15241
09328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1524109328
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.486403956
Short name T1332
Test name
Test status
Simulation time 197398476 ps
CPU time 0.82 seconds
Started Jul 14 07:21:52 PM PDT 24
Finished Jul 14 07:22:13 PM PDT 24
Peak memory 206856 kb
Host smart-015ded8f-cc93-4ea1-8333-8c78c9fda313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48640
3956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.486403956
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2027048999
Short name T1423
Test name
Test status
Simulation time 380818464 ps
CPU time 1.28 seconds
Started Jul 14 07:21:58 PM PDT 24
Finished Jul 14 07:22:21 PM PDT 24
Peak memory 206872 kb
Host smart-03b9565b-56c9-4f18-b195-dcc0e0958ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20270
48999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2027048999
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.4166655039
Short name T944
Test name
Test status
Simulation time 921626129 ps
CPU time 2.01 seconds
Started Jul 14 07:21:41 PM PDT 24
Finished Jul 14 07:22:03 PM PDT 24
Peak memory 206988 kb
Host smart-e8bd514c-3717-4103-a1fd-733dada99466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41666
55039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.4166655039
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3472550480
Short name T87
Test name
Test status
Simulation time 6161697115 ps
CPU time 12.85 seconds
Started Jul 14 07:21:40 PM PDT 24
Finished Jul 14 07:22:12 PM PDT 24
Peak memory 207088 kb
Host smart-9cbad3a1-e835-4350-bc8a-dcb8af6ea29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725
50480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3472550480
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.2663744024
Short name T1774
Test name
Test status
Simulation time 320705315 ps
CPU time 1.14 seconds
Started Jul 14 07:21:56 PM PDT 24
Finished Jul 14 07:22:17 PM PDT 24
Peak memory 206868 kb
Host smart-aa7b857b-59f2-4607-b008-24e56ef98c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26637
44024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.2663744024
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.177069008
Short name T2701
Test name
Test status
Simulation time 164711532 ps
CPU time 0.76 seconds
Started Jul 14 07:21:58 PM PDT 24
Finished Jul 14 07:22:20 PM PDT 24
Peak memory 206864 kb
Host smart-2a32d721-ff9b-445f-a41b-b02b3c0a1b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17706
9008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.177069008
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3451160797
Short name T1944
Test name
Test status
Simulation time 51995362 ps
CPU time 0.69 seconds
Started Jul 14 07:21:59 PM PDT 24
Finished Jul 14 07:22:20 PM PDT 24
Peak memory 206888 kb
Host smart-8c0b44e9-3f7b-4b17-b0f9-8eb16b11c8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34511
60797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3451160797
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2014423217
Short name T2056
Test name
Test status
Simulation time 721003866 ps
CPU time 1.76 seconds
Started Jul 14 07:21:51 PM PDT 24
Finished Jul 14 07:22:13 PM PDT 24
Peak memory 207248 kb
Host smart-4cc683b4-ee3c-4aac-9047-2f081351c01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20144
23217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2014423217
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1335621723
Short name T1263
Test name
Test status
Simulation time 335779471 ps
CPU time 1.93 seconds
Started Jul 14 07:21:59 PM PDT 24
Finished Jul 14 07:22:22 PM PDT 24
Peak memory 207028 kb
Host smart-bcddc8dd-bbcb-4969-90fc-a462756053f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13356
21723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1335621723
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.203731614
Short name T558
Test name
Test status
Simulation time 267707299 ps
CPU time 0.96 seconds
Started Jul 14 07:21:53 PM PDT 24
Finished Jul 14 07:22:14 PM PDT 24
Peak memory 206864 kb
Host smart-b811c45a-c15c-411f-a302-7820927c3bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373
1614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.203731614
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2664334422
Short name T2033
Test name
Test status
Simulation time 147816125 ps
CPU time 0.75 seconds
Started Jul 14 07:21:58 PM PDT 24
Finished Jul 14 07:22:20 PM PDT 24
Peak memory 206864 kb
Host smart-3dd3077a-119c-478f-8fc5-8d328da3f15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26643
34422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2664334422
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3559631671
Short name T482
Test name
Test status
Simulation time 262509583 ps
CPU time 1.01 seconds
Started Jul 14 07:21:44 PM PDT 24
Finished Jul 14 07:22:04 PM PDT 24
Peak memory 206860 kb
Host smart-9afd0a9a-cdd4-4ccb-b50f-94b3b1407fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35596
31671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3559631671
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3152902357
Short name T1231
Test name
Test status
Simulation time 9711041926 ps
CPU time 260.17 seconds
Started Jul 14 07:21:56 PM PDT 24
Finished Jul 14 07:26:36 PM PDT 24
Peak memory 207080 kb
Host smart-cf6e8f90-2061-4ba4-83dc-5f470763e6d1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3152902357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3152902357
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.1714361131
Short name T1526
Test name
Test status
Simulation time 11079796662 ps
CPU time 93.64 seconds
Started Jul 14 07:21:56 PM PDT 24
Finished Jul 14 07:23:50 PM PDT 24
Peak memory 207156 kb
Host smart-e7ef0286-6f56-44a9-975a-41ba8867d67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17143
61131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.1714361131
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1300203897
Short name T97
Test name
Test status
Simulation time 252530034 ps
CPU time 0.89 seconds
Started Jul 14 07:21:56 PM PDT 24
Finished Jul 14 07:22:18 PM PDT 24
Peak memory 206860 kb
Host smart-073503ad-2b8d-49a3-b8a0-866a29acebe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13002
03897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1300203897
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3312181773
Short name T1532
Test name
Test status
Simulation time 23365995264 ps
CPU time 26.93 seconds
Started Jul 14 07:21:44 PM PDT 24
Finished Jul 14 07:22:29 PM PDT 24
Peak memory 206932 kb
Host smart-f6962714-1255-4d6c-a3e3-d466e3e78711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33121
81773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3312181773
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3460105535
Short name T1695
Test name
Test status
Simulation time 3395022385 ps
CPU time 4.32 seconds
Started Jul 14 07:21:54 PM PDT 24
Finished Jul 14 07:22:18 PM PDT 24
Peak memory 206948 kb
Host smart-04e43da7-ab18-4e33-8240-afa1506ae027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34601
05535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3460105535
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.4044509787
Short name T595
Test name
Test status
Simulation time 8051544286 ps
CPU time 224.43 seconds
Started Jul 14 07:22:02 PM PDT 24
Finished Jul 14 07:26:10 PM PDT 24
Peak memory 207152 kb
Host smart-97483d21-f1d5-4aa8-9b2a-b03d42249f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40445
09787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.4044509787
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.425275382
Short name T477
Test name
Test status
Simulation time 4658452237 ps
CPU time 131.68 seconds
Started Jul 14 07:22:02 PM PDT 24
Finished Jul 14 07:24:37 PM PDT 24
Peak memory 207048 kb
Host smart-ed500d5e-1075-4370-9395-62d46213611f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=425275382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.425275382
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3382053225
Short name T1310
Test name
Test status
Simulation time 244762999 ps
CPU time 0.94 seconds
Started Jul 14 07:21:44 PM PDT 24
Finished Jul 14 07:22:04 PM PDT 24
Peak memory 206888 kb
Host smart-6a49b0ab-ce6c-43b7-90ce-023c4a6943ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3382053225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3382053225
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3536455514
Short name T448
Test name
Test status
Simulation time 196262696 ps
CPU time 0.87 seconds
Started Jul 14 07:21:50 PM PDT 24
Finished Jul 14 07:22:10 PM PDT 24
Peak memory 206872 kb
Host smart-34b276a7-52c1-483b-9e87-fe7cf0e51767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35364
55514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3536455514
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2056017347
Short name T524
Test name
Test status
Simulation time 4525162634 ps
CPU time 30.93 seconds
Started Jul 14 07:21:52 PM PDT 24
Finished Jul 14 07:22:43 PM PDT 24
Peak memory 207136 kb
Host smart-f324c9bd-16ac-4101-9bcc-6e91ed4d7f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20560
17347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2056017347
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.4014550207
Short name T2546
Test name
Test status
Simulation time 7702859309 ps
CPU time 51.81 seconds
Started Jul 14 07:21:42 PM PDT 24
Finished Jul 14 07:22:53 PM PDT 24
Peak memory 207060 kb
Host smart-8b829e8c-3175-4d8c-ac03-3eef2944c3d7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4014550207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.4014550207
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2598115648
Short name T2430
Test name
Test status
Simulation time 257749059 ps
CPU time 0.95 seconds
Started Jul 14 07:21:44 PM PDT 24
Finished Jul 14 07:22:04 PM PDT 24
Peak memory 206832 kb
Host smart-70d778e6-6e0a-4674-be2a-73c915191299
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2598115648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2598115648
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1596974935
Short name T430
Test name
Test status
Simulation time 139498616 ps
CPU time 0.75 seconds
Started Jul 14 07:21:59 PM PDT 24
Finished Jul 14 07:22:20 PM PDT 24
Peak memory 206868 kb
Host smart-7177f071-dda6-4bf1-950f-0a452615cf1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15969
74935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1596974935
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.448410864
Short name T131
Test name
Test status
Simulation time 198786007 ps
CPU time 0.84 seconds
Started Jul 14 07:21:54 PM PDT 24
Finished Jul 14 07:22:14 PM PDT 24
Peak memory 206880 kb
Host smart-f31c3465-38c0-4d71-af6a-45439b2f7547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44841
0864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.448410864
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1120147501
Short name T88
Test name
Test status
Simulation time 176232171 ps
CPU time 0.78 seconds
Started Jul 14 07:21:55 PM PDT 24
Finished Jul 14 07:22:16 PM PDT 24
Peak memory 206888 kb
Host smart-367d4ef5-cf6b-4b63-9af1-b41f05538cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11201
47501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1120147501
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2822207937
Short name T549
Test name
Test status
Simulation time 191164599 ps
CPU time 0.79 seconds
Started Jul 14 07:21:58 PM PDT 24
Finished Jul 14 07:22:20 PM PDT 24
Peak memory 206856 kb
Host smart-40dfb2a2-86bc-46e2-bbdf-82c63d0b7482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28222
07937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2822207937
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1610615308
Short name T1204
Test name
Test status
Simulation time 157655452 ps
CPU time 0.74 seconds
Started Jul 14 07:21:45 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 206856 kb
Host smart-2f6e89f4-e24a-470e-a4a5-6e784cb70d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16106
15308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1610615308
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1378950984
Short name T1797
Test name
Test status
Simulation time 147818451 ps
CPU time 0.8 seconds
Started Jul 14 07:21:45 PM PDT 24
Finished Jul 14 07:22:05 PM PDT 24
Peak memory 206840 kb
Host smart-69108dfa-16a9-4f0b-a10c-1acef7c29e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13789
50984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1378950984
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.4192804456
Short name T2
Test name
Test status
Simulation time 316026832 ps
CPU time 1.12 seconds
Started Jul 14 07:21:43 PM PDT 24
Finished Jul 14 07:22:04 PM PDT 24
Peak memory 206840 kb
Host smart-c173542a-1a50-4cec-a14b-8bca11769daf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4192804456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.4192804456
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3074756754
Short name T2458
Test name
Test status
Simulation time 143960503 ps
CPU time 0.78 seconds
Started Jul 14 07:22:02 PM PDT 24
Finished Jul 14 07:22:27 PM PDT 24
Peak memory 206876 kb
Host smart-3aa1526e-50b4-49bf-829b-41f66b8cce2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30747
56754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3074756754
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2197130850
Short name T36
Test name
Test status
Simulation time 94440858 ps
CPU time 0.69 seconds
Started Jul 14 07:21:58 PM PDT 24
Finished Jul 14 07:22:20 PM PDT 24
Peak memory 206876 kb
Host smart-7a06f339-20fe-4a71-9c32-72edcc79ab65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21971
30850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2197130850
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3252836502
Short name T241
Test name
Test status
Simulation time 10295299093 ps
CPU time 23.94 seconds
Started Jul 14 07:21:57 PM PDT 24
Finished Jul 14 07:22:41 PM PDT 24
Peak memory 207104 kb
Host smart-e9ce3bef-b792-488e-8901-38806f113235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32528
36502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3252836502
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1550394683
Short name T740
Test name
Test status
Simulation time 153930862 ps
CPU time 0.81 seconds
Started Jul 14 07:21:49 PM PDT 24
Finished Jul 14 07:22:08 PM PDT 24
Peak memory 206848 kb
Host smart-36673f7e-d84b-4b09-96d0-00db8cc5de59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15503
94683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1550394683
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1410147495
Short name T2015
Test name
Test status
Simulation time 203751315 ps
CPU time 0.89 seconds
Started Jul 14 07:22:00 PM PDT 24
Finished Jul 14 07:22:24 PM PDT 24
Peak memory 206868 kb
Host smart-bc3b03f4-e2f8-4496-830d-02143a4b2e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14101
47495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1410147495
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.4220741320
Short name T2684
Test name
Test status
Simulation time 246444681 ps
CPU time 0.89 seconds
Started Jul 14 07:21:59 PM PDT 24
Finished Jul 14 07:22:23 PM PDT 24
Peak memory 206872 kb
Host smart-ea1bff57-b5ca-4990-a8f5-7b9a609f8662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42207
41320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.4220741320
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2531400320
Short name T2517
Test name
Test status
Simulation time 228552111 ps
CPU time 0.86 seconds
Started Jul 14 07:21:59 PM PDT 24
Finished Jul 14 07:22:23 PM PDT 24
Peak memory 206852 kb
Host smart-fde604e5-c0f3-464a-80e7-7a988c31fb55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25314
00320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2531400320
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3093778069
Short name T2404
Test name
Test status
Simulation time 175389021 ps
CPU time 0.85 seconds
Started Jul 14 07:21:49 PM PDT 24
Finished Jul 14 07:22:09 PM PDT 24
Peak memory 206856 kb
Host smart-49149bcb-4083-41a7-99f1-b48e759d6357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30937
78069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3093778069
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.4060147340
Short name T503
Test name
Test status
Simulation time 178730109 ps
CPU time 0.85 seconds
Started Jul 14 07:21:54 PM PDT 24
Finished Jul 14 07:22:14 PM PDT 24
Peak memory 206864 kb
Host smart-111dcdd7-a4bc-494c-a26c-4b34ae2f6340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40601
47340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.4060147340
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2750632171
Short name T2342
Test name
Test status
Simulation time 182409300 ps
CPU time 0.84 seconds
Started Jul 14 07:22:04 PM PDT 24
Finished Jul 14 07:22:28 PM PDT 24
Peak memory 206868 kb
Host smart-4a34f820-fdde-48cd-b9cd-e8e0123ab45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27506
32171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2750632171
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1119814378
Short name T1353
Test name
Test status
Simulation time 197723593 ps
CPU time 0.86 seconds
Started Jul 14 07:22:07 PM PDT 24
Finished Jul 14 07:22:32 PM PDT 24
Peak memory 206860 kb
Host smart-56d17cdd-7527-4684-81d4-dd6c015dc3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11198
14378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1119814378
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.185858414
Short name T699
Test name
Test status
Simulation time 5915583386 ps
CPU time 53.61 seconds
Started Jul 14 07:22:00 PM PDT 24
Finished Jul 14 07:23:16 PM PDT 24
Peak memory 207112 kb
Host smart-97de31ee-d84e-4d7a-a8e0-527f6620a32d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=185858414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.185858414
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3699542390
Short name T520
Test name
Test status
Simulation time 185067600 ps
CPU time 0.83 seconds
Started Jul 14 07:21:57 PM PDT 24
Finished Jul 14 07:22:18 PM PDT 24
Peak memory 206876 kb
Host smart-946c505a-cfdc-4189-95cb-07b87d676de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36995
42390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3699542390
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3622067684
Short name T2367
Test name
Test status
Simulation time 156592606 ps
CPU time 0.83 seconds
Started Jul 14 07:21:56 PM PDT 24
Finished Jul 14 07:22:17 PM PDT 24
Peak memory 206824 kb
Host smart-ef9e157a-1d1d-479f-9235-3edfedbc28f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36220
67684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3622067684
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1248120890
Short name T1221
Test name
Test status
Simulation time 796107216 ps
CPU time 1.79 seconds
Started Jul 14 07:22:02 PM PDT 24
Finished Jul 14 07:22:27 PM PDT 24
Peak memory 207024 kb
Host smart-8ef140c4-305e-46bf-9ec1-be2d329d8ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12481
20890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1248120890
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2512109036
Short name T2603
Test name
Test status
Simulation time 3112250234 ps
CPU time 22.07 seconds
Started Jul 14 07:21:52 PM PDT 24
Finished Jul 14 07:22:34 PM PDT 24
Peak memory 207148 kb
Host smart-b448b11e-2bc7-400a-b247-90c512fdca5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25121
09036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2512109036
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3701240165
Short name T2352
Test name
Test status
Simulation time 40355937 ps
CPU time 0.68 seconds
Started Jul 14 07:13:19 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206916 kb
Host smart-bf96d5bc-fba7-4f12-9438-8cc1577480da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3701240165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3701240165
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2445240351
Short name T1782
Test name
Test status
Simulation time 3943521207 ps
CPU time 4.64 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:29 PM PDT 24
Peak memory 206924 kb
Host smart-6448e893-59d8-46aa-8830-05e70e0dfa7c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2445240351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2445240351
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3128420276
Short name T2599
Test name
Test status
Simulation time 13425588502 ps
CPU time 12.46 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 206924 kb
Host smart-505f2fe8-d1af-4374-9369-ea31bdb8ea87
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3128420276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3128420276
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.771551037
Short name T806
Test name
Test status
Simulation time 23445449491 ps
CPU time 30.02 seconds
Started Jul 14 07:13:10 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 207100 kb
Host smart-f9b49133-f6d8-4010-95a6-80de7e1818bf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=771551037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.771551037
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.857274894
Short name T1322
Test name
Test status
Simulation time 163275786 ps
CPU time 0.78 seconds
Started Jul 14 07:13:09 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206888 kb
Host smart-549eae87-4f60-40e1-aff4-43b19e8565ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85727
4894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.857274894
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2268126615
Short name T2574
Test name
Test status
Simulation time 183244091 ps
CPU time 0.88 seconds
Started Jul 14 07:13:09 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206880 kb
Host smart-90a3ae86-d4d8-4904-b9f4-51f120c8579b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22681
26615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2268126615
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3072683468
Short name T616
Test name
Test status
Simulation time 395029893 ps
CPU time 1.3 seconds
Started Jul 14 07:13:09 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206856 kb
Host smart-65a1576c-09be-4231-8fd6-abe842493d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30726
83468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3072683468
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3759602855
Short name T929
Test name
Test status
Simulation time 518533060 ps
CPU time 1.42 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:25 PM PDT 24
Peak memory 206804 kb
Host smart-ee0e36fe-d257-4c9a-9e08-750259cf3816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37596
02855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3759602855
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.2814608925
Short name T2136
Test name
Test status
Simulation time 6597599155 ps
CPU time 12.04 seconds
Started Jul 14 07:13:08 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 207112 kb
Host smart-5eff5e3b-42d4-4a56-b3a4-fde82d6855f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28146
08925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.2814608925
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3585990244
Short name T541
Test name
Test status
Simulation time 435625526 ps
CPU time 1.33 seconds
Started Jul 14 07:13:18 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206876 kb
Host smart-08714fdb-81b8-4c3e-8a67-f6d864fa5883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35859
90244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3585990244
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2825920882
Short name T507
Test name
Test status
Simulation time 169494507 ps
CPU time 0.82 seconds
Started Jul 14 07:13:16 PM PDT 24
Finished Jul 14 07:13:29 PM PDT 24
Peak memory 206888 kb
Host smart-0075a6c9-2fd5-40b1-839e-0a6edb8a3e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259
20882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2825920882
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2597618071
Short name T2233
Test name
Test status
Simulation time 34979153 ps
CPU time 0.67 seconds
Started Jul 14 07:13:15 PM PDT 24
Finished Jul 14 07:13:28 PM PDT 24
Peak memory 206844 kb
Host smart-2140fcf2-ce57-4f18-adb0-428e41b60b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25976
18071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2597618071
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.33462148
Short name T668
Test name
Test status
Simulation time 947209506 ps
CPU time 2.37 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 207032 kb
Host smart-c4a8675b-19d1-4f2e-8eda-dd792e1286dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33462
148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.33462148
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4063633563
Short name T1383
Test name
Test status
Simulation time 238690905 ps
CPU time 1.54 seconds
Started Jul 14 07:13:18 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 207068 kb
Host smart-752893d9-b5fb-4b4c-b224-b9a9e4ee3083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40636
33563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4063633563
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.532320799
Short name T1566
Test name
Test status
Simulation time 191179750 ps
CPU time 0.91 seconds
Started Jul 14 07:13:15 PM PDT 24
Finished Jul 14 07:13:29 PM PDT 24
Peak memory 206868 kb
Host smart-f7fef192-257c-42ef-98c5-5c6d79268ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53232
0799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.532320799
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3268264423
Short name T1441
Test name
Test status
Simulation time 142013155 ps
CPU time 0.75 seconds
Started Jul 14 07:13:18 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206872 kb
Host smart-656a45fe-705b-4412-b345-e3e85e63b62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32682
64423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3268264423
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.976697252
Short name T2330
Test name
Test status
Simulation time 162106680 ps
CPU time 0.79 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:30 PM PDT 24
Peak memory 206880 kb
Host smart-1f9114d1-3a81-4e47-a817-178c43e6a050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97669
7252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.976697252
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3550246540
Short name T2086
Test name
Test status
Simulation time 182451911 ps
CPU time 0.86 seconds
Started Jul 14 07:13:14 PM PDT 24
Finished Jul 14 07:13:28 PM PDT 24
Peak memory 206900 kb
Host smart-58011c55-5432-4b45-ae50-dfd5acbcd5fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35502
46540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3550246540
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.850227672
Short name T1618
Test name
Test status
Simulation time 23322463724 ps
CPU time 23.74 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:53 PM PDT 24
Peak memory 206944 kb
Host smart-961d1190-5251-4de6-bfa3-b750daeabf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85022
7672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.850227672
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3644572901
Short name T1450
Test name
Test status
Simulation time 3352268126 ps
CPU time 3.63 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:33 PM PDT 24
Peak memory 206916 kb
Host smart-3f3ccaf2-80ab-4a65-bedd-06a5641a0183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
72901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3644572901
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.279698354
Short name T423
Test name
Test status
Simulation time 6978963765 ps
CPU time 49.87 seconds
Started Jul 14 07:13:15 PM PDT 24
Finished Jul 14 07:14:18 PM PDT 24
Peak memory 207152 kb
Host smart-6deb34c1-b489-45f2-b9f8-45b485e1183f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969
8354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.279698354
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2882168086
Short name T705
Test name
Test status
Simulation time 5555110504 ps
CPU time 39.79 seconds
Started Jul 14 07:13:16 PM PDT 24
Finished Jul 14 07:14:09 PM PDT 24
Peak memory 207132 kb
Host smart-913bc1ec-1b5d-4a0f-b273-d96238e3932a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2882168086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2882168086
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3674847358
Short name T2708
Test name
Test status
Simulation time 257709436 ps
CPU time 0.96 seconds
Started Jul 14 07:13:13 PM PDT 24
Finished Jul 14 07:13:28 PM PDT 24
Peak memory 206876 kb
Host smart-b69d24e9-b33c-4423-b26b-89f5c93ce999
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3674847358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3674847358
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3529305436
Short name T928
Test name
Test status
Simulation time 190159223 ps
CPU time 0.92 seconds
Started Jul 14 07:13:15 PM PDT 24
Finished Jul 14 07:13:29 PM PDT 24
Peak memory 206860 kb
Host smart-680bc4e5-682f-4c98-9c97-71ad213f1310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35293
05436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3529305436
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1713132385
Short name T2511
Test name
Test status
Simulation time 6556348531 ps
CPU time 62.72 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:14:32 PM PDT 24
Peak memory 207080 kb
Host smart-10919eaa-5246-49f0-9dd7-e9f58ae49edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
32385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1713132385
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2817193188
Short name T1888
Test name
Test status
Simulation time 5126675805 ps
CPU time 142.01 seconds
Started Jul 14 07:13:22 PM PDT 24
Finished Jul 14 07:15:55 PM PDT 24
Peak memory 207068 kb
Host smart-6493a165-2083-4001-9126-8dac3133956f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2817193188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2817193188
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1358821145
Short name T1002
Test name
Test status
Simulation time 181618115 ps
CPU time 0.85 seconds
Started Jul 14 07:13:16 PM PDT 24
Finished Jul 14 07:13:30 PM PDT 24
Peak memory 206872 kb
Host smart-a7d469b4-d206-4640-8a15-54a31880811c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1358821145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1358821145
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3324187583
Short name T1935
Test name
Test status
Simulation time 157974936 ps
CPU time 0.78 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:30 PM PDT 24
Peak memory 206836 kb
Host smart-69c3c661-6a5d-4224-9b4b-68c7b6953a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
87583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3324187583
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3863329811
Short name T130
Test name
Test status
Simulation time 208873785 ps
CPU time 0.91 seconds
Started Jul 14 07:13:15 PM PDT 24
Finished Jul 14 07:13:29 PM PDT 24
Peak memory 206860 kb
Host smart-3f3a182e-a45d-4ad0-bbaa-7fb1569c4d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633
29811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3863329811
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3386206830
Short name T2172
Test name
Test status
Simulation time 194773903 ps
CPU time 0.92 seconds
Started Jul 14 07:13:15 PM PDT 24
Finished Jul 14 07:13:29 PM PDT 24
Peak memory 206844 kb
Host smart-1e712d7b-bd73-455f-bb8a-2d8160c7111f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33862
06830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3386206830
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2076892957
Short name T2203
Test name
Test status
Simulation time 194931182 ps
CPU time 0.87 seconds
Started Jul 14 07:13:14 PM PDT 24
Finished Jul 14 07:13:28 PM PDT 24
Peak memory 206840 kb
Host smart-ac55bd27-792f-4d5e-b9e4-39d9a31898af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20768
92957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2076892957
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2335838647
Short name T961
Test name
Test status
Simulation time 224707378 ps
CPU time 0.84 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206848 kb
Host smart-be50e651-3826-4913-9430-1d0260b5bf21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
38647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2335838647
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1090859292
Short name T731
Test name
Test status
Simulation time 173191683 ps
CPU time 0.83 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:30 PM PDT 24
Peak memory 206868 kb
Host smart-5d1fae2d-cc43-4b4b-83fd-73f6a5d0c117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10908
59292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1090859292
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2848134333
Short name T1763
Test name
Test status
Simulation time 173806746 ps
CPU time 0.85 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:30 PM PDT 24
Peak memory 206884 kb
Host smart-aa3bc907-ae10-4e6c-92f1-772c50fbef7a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2848134333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2848134333
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.122354313
Short name T710
Test name
Test status
Simulation time 167972637 ps
CPU time 0.77 seconds
Started Jul 14 07:13:16 PM PDT 24
Finished Jul 14 07:13:30 PM PDT 24
Peak memory 206864 kb
Host smart-b5663ae3-ffaf-4ce6-93ac-a3587484da45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12235
4313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.122354313
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1808282230
Short name T1272
Test name
Test status
Simulation time 94064696 ps
CPU time 0.68 seconds
Started Jul 14 07:13:19 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206868 kb
Host smart-d7634084-48f5-42be-8797-0650f7e0d18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18082
82230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1808282230
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4062495283
Short name T1614
Test name
Test status
Simulation time 10681540484 ps
CPU time 24.95 seconds
Started Jul 14 07:13:17 PM PDT 24
Finished Jul 14 07:13:54 PM PDT 24
Peak memory 207148 kb
Host smart-3ed27917-3772-4275-bf9a-2d96575e232b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40624
95283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4062495283
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3419948370
Short name T2591
Test name
Test status
Simulation time 247975505 ps
CPU time 0.87 seconds
Started Jul 14 07:13:18 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206848 kb
Host smart-74525458-3281-4d85-9591-609f0ee49bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34199
48370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3419948370
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2259504283
Short name T662
Test name
Test status
Simulation time 185817155 ps
CPU time 0.9 seconds
Started Jul 14 07:13:14 PM PDT 24
Finished Jul 14 07:13:29 PM PDT 24
Peak memory 207044 kb
Host smart-9e3787ce-bcb8-4826-87bd-f83de96a5e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22595
04283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2259504283
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3987581856
Short name T169
Test name
Test status
Simulation time 9785300558 ps
CPU time 178.83 seconds
Started Jul 14 07:13:16 PM PDT 24
Finished Jul 14 07:16:27 PM PDT 24
Peak memory 207096 kb
Host smart-b84de8a9-be74-4a69-bb9c-ca8b7d4e293a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3987581856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3987581856
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.4229333279
Short name T2285
Test name
Test status
Simulation time 11152666550 ps
CPU time 203.03 seconds
Started Jul 14 07:13:26 PM PDT 24
Finished Jul 14 07:16:58 PM PDT 24
Peak memory 207136 kb
Host smart-60976c7c-b6cc-4ea9-82b3-7928a4a5409c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4229333279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.4229333279
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2615819975
Short name T891
Test name
Test status
Simulation time 10695694283 ps
CPU time 73.14 seconds
Started Jul 14 07:13:21 PM PDT 24
Finished Jul 14 07:14:45 PM PDT 24
Peak memory 207168 kb
Host smart-a5647107-c208-4269-ba62-f3bda512661e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2615819975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2615819975
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2667883244
Short name T1670
Test name
Test status
Simulation time 223210535 ps
CPU time 0.87 seconds
Started Jul 14 07:13:18 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206848 kb
Host smart-a768a7bb-fbb8-4459-891d-973041436b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26678
83244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2667883244
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3829002565
Short name T2652
Test name
Test status
Simulation time 234821267 ps
CPU time 0.88 seconds
Started Jul 14 07:13:16 PM PDT 24
Finished Jul 14 07:13:29 PM PDT 24
Peak memory 206812 kb
Host smart-05b8a873-2f3a-499c-9dc3-852967d12e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38290
02565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3829002565
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1863927644
Short name T582
Test name
Test status
Simulation time 224836784 ps
CPU time 0.82 seconds
Started Jul 14 07:13:20 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 206820 kb
Host smart-a3ace91a-f9ee-4775-83bd-737514f111a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18639
27644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1863927644
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.875083397
Short name T1707
Test name
Test status
Simulation time 146748121 ps
CPU time 0.75 seconds
Started Jul 14 07:13:28 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 206872 kb
Host smart-5e596a99-081c-4111-80c6-c62dc44b383f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87508
3397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.875083397
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.8050643
Short name T1111
Test name
Test status
Simulation time 152746268 ps
CPU time 0.75 seconds
Started Jul 14 07:13:19 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206812 kb
Host smart-22620b4e-b942-4f1e-95cb-5c88e48f9111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80506
43 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.8050643
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1460666697
Short name T1476
Test name
Test status
Simulation time 234459281 ps
CPU time 0.93 seconds
Started Jul 14 07:13:19 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 206856 kb
Host smart-b1079b49-d924-42c9-a5a8-c23f6495cb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14606
66697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1460666697
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3660818016
Short name T2384
Test name
Test status
Simulation time 4514892777 ps
CPU time 124.31 seconds
Started Jul 14 07:13:20 PM PDT 24
Finished Jul 14 07:15:35 PM PDT 24
Peak memory 207064 kb
Host smart-e4240330-4843-489e-b11c-62becf26d721
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3660818016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3660818016
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.721459489
Short name T899
Test name
Test status
Simulation time 223530717 ps
CPU time 0.85 seconds
Started Jul 14 07:13:21 PM PDT 24
Finished Jul 14 07:13:33 PM PDT 24
Peak memory 206872 kb
Host smart-e893db08-65b5-430a-8bff-4ae3cf437246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72145
9489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.721459489
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2628001257
Short name T641
Test name
Test status
Simulation time 177846613 ps
CPU time 0.85 seconds
Started Jul 14 07:13:26 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 206852 kb
Host smart-082d29ac-2165-40aa-9644-c788227e9979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26280
01257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2628001257
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.522612114
Short name T2089
Test name
Test status
Simulation time 664963289 ps
CPU time 1.7 seconds
Started Jul 14 07:13:28 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 207072 kb
Host smart-7bcff010-26cf-4ac3-97bf-5b6b0ef43e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52261
2114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.522612114
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2647731575
Short name T892
Test name
Test status
Simulation time 3443289136 ps
CPU time 24.82 seconds
Started Jul 14 07:13:21 PM PDT 24
Finished Jul 14 07:13:57 PM PDT 24
Peak memory 207068 kb
Host smart-2b7e1ac0-68ba-480a-ac93-72db6881bfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26477
31575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2647731575
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.4269932131
Short name T1220
Test name
Test status
Simulation time 35383670 ps
CPU time 0.69 seconds
Started Jul 14 07:13:36 PM PDT 24
Finished Jul 14 07:13:40 PM PDT 24
Peak memory 206940 kb
Host smart-434fe730-9073-4cce-8a45-aa2251e06e7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4269932131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.4269932131
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3009222742
Short name T1727
Test name
Test status
Simulation time 4354283742 ps
CPU time 5.98 seconds
Started Jul 14 07:13:22 PM PDT 24
Finished Jul 14 07:13:39 PM PDT 24
Peak memory 207168 kb
Host smart-4138adc3-93d8-4499-a3b7-282b2a29f650
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3009222742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3009222742
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.955682478
Short name T1080
Test name
Test status
Simulation time 13406756526 ps
CPU time 15.79 seconds
Started Jul 14 07:13:20 PM PDT 24
Finished Jul 14 07:13:48 PM PDT 24
Peak memory 206904 kb
Host smart-4d309208-e070-44e1-bc54-46562ad6dd14
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=955682478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.955682478
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1925332027
Short name T539
Test name
Test status
Simulation time 23346817256 ps
CPU time 21.97 seconds
Started Jul 14 07:13:22 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 207148 kb
Host smart-b1b726ad-124b-4602-a56d-83dedefed792
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1925332027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.1925332027
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2974900479
Short name T2480
Test name
Test status
Simulation time 163338373 ps
CPU time 0.77 seconds
Started Jul 14 07:13:27 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 206880 kb
Host smart-027243b0-b5f0-48cc-b953-e423c9ae492f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
00479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2974900479
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1233295235
Short name T2399
Test name
Test status
Simulation time 204458149 ps
CPU time 0.83 seconds
Started Jul 14 07:13:21 PM PDT 24
Finished Jul 14 07:13:33 PM PDT 24
Peak memory 206852 kb
Host smart-0638d8d8-791d-4faf-b08a-7a0aba9cf022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12332
95235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1233295235
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3929784330
Short name T431
Test name
Test status
Simulation time 158667317 ps
CPU time 0.8 seconds
Started Jul 14 07:13:23 PM PDT 24
Finished Jul 14 07:13:35 PM PDT 24
Peak memory 206864 kb
Host smart-d6f76f6d-084c-44a1-b640-a1ae3f70c588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39297
84330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3929784330
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3020393224
Short name T1129
Test name
Test status
Simulation time 486558088 ps
CPU time 1.33 seconds
Started Jul 14 07:13:28 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 206892 kb
Host smart-f34224a2-e521-4e38-abb1-ae673ef1f0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30203
93224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3020393224
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.1679140580
Short name T2115
Test name
Test status
Simulation time 8142283151 ps
CPU time 15.22 seconds
Started Jul 14 07:13:20 PM PDT 24
Finished Jul 14 07:13:46 PM PDT 24
Peak memory 207136 kb
Host smart-f2c3c770-c87b-4246-b923-723e0fad6b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16791
40580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.1679140580
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.2749871002
Short name T2388
Test name
Test status
Simulation time 365136271 ps
CPU time 1.31 seconds
Started Jul 14 07:13:19 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 206888 kb
Host smart-8507d2be-6f9b-4d17-9292-499efee02842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27498
71002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2749871002
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2975910365
Short name T515
Test name
Test status
Simulation time 173759048 ps
CPU time 0.85 seconds
Started Jul 14 07:13:24 PM PDT 24
Finished Jul 14 07:13:35 PM PDT 24
Peak memory 206872 kb
Host smart-a6ea74b4-ef38-457c-858d-625b40b55457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29759
10365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2975910365
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2327107865
Short name T1551
Test name
Test status
Simulation time 40065742 ps
CPU time 0.67 seconds
Started Jul 14 07:13:23 PM PDT 24
Finished Jul 14 07:13:34 PM PDT 24
Peak memory 206868 kb
Host smart-f93b9ab2-21e1-44c5-baf7-e199f8c2c448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23271
07865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2327107865
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3784619344
Short name T137
Test name
Test status
Simulation time 782746127 ps
CPU time 2.02 seconds
Started Jul 14 07:13:24 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 206836 kb
Host smart-9c77dcd6-8a95-4790-822b-20b73d52aafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37846
19344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3784619344
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2795215867
Short name T1533
Test name
Test status
Simulation time 311406490 ps
CPU time 2.46 seconds
Started Jul 14 07:13:27 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 206984 kb
Host smart-3611acdf-9d1a-44fb-b973-e7f145ffce52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27952
15867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2795215867
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2508689172
Short name T1145
Test name
Test status
Simulation time 288581395 ps
CPU time 0.87 seconds
Started Jul 14 07:13:21 PM PDT 24
Finished Jul 14 07:13:33 PM PDT 24
Peak memory 206960 kb
Host smart-faac5ff4-9809-4ff3-91b1-cdb099eb7499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25086
89172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2508689172
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1351923666
Short name T1895
Test name
Test status
Simulation time 151399356 ps
CPU time 0.8 seconds
Started Jul 14 07:13:19 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 206824 kb
Host smart-e1709270-8ba4-4beb-8597-55968251e55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
23666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1351923666
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.155149730
Short name T2085
Test name
Test status
Simulation time 238134971 ps
CPU time 0.95 seconds
Started Jul 14 07:13:31 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 206840 kb
Host smart-afcccf73-3bce-4556-b6cf-91dc5d72e89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15514
9730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.155149730
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.216526207
Short name T213
Test name
Test status
Simulation time 7208433635 ps
CPU time 66.14 seconds
Started Jul 14 07:13:24 PM PDT 24
Finished Jul 14 07:14:40 PM PDT 24
Peak memory 206848 kb
Host smart-2e0ddfe5-9b64-49b3-954e-142429f333c8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=216526207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.216526207
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.733257854
Short name T596
Test name
Test status
Simulation time 9459031165 ps
CPU time 28.09 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:14:04 PM PDT 24
Peak memory 207084 kb
Host smart-75fd6428-5255-42f8-8f5e-a3e870f62b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73325
7854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.733257854
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3802560794
Short name T1556
Test name
Test status
Simulation time 240919902 ps
CPU time 0.95 seconds
Started Jul 14 07:13:27 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 206860 kb
Host smart-2303b341-f227-46c4-b2ed-05c4d548d736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38025
60794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3802560794
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1574232604
Short name T2717
Test name
Test status
Simulation time 23337372237 ps
CPU time 21.92 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:13:58 PM PDT 24
Peak memory 206932 kb
Host smart-c929ef3d-0e5d-4d19-9937-35176e6efbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15742
32604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1574232604
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3850829395
Short name T2252
Test name
Test status
Simulation time 3294870459 ps
CPU time 3.85 seconds
Started Jul 14 07:13:31 PM PDT 24
Finished Jul 14 07:13:41 PM PDT 24
Peak memory 206900 kb
Host smart-c78c548d-764a-4a6b-8232-2649f8809b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38508
29395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3850829395
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.180138889
Short name T1597
Test name
Test status
Simulation time 11153165518 ps
CPU time 301.67 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:18:38 PM PDT 24
Peak memory 207144 kb
Host smart-0c77efcf-01df-42bf-b8bf-03a18ecd6ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18013
8889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.180138889
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2096416293
Short name T1028
Test name
Test status
Simulation time 5089431077 ps
CPU time 34.74 seconds
Started Jul 14 07:13:28 PM PDT 24
Finished Jul 14 07:14:10 PM PDT 24
Peak memory 207136 kb
Host smart-d0156ac4-a417-49fd-a581-ef56a0a23a97
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2096416293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2096416293
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.3334656511
Short name T1085
Test name
Test status
Simulation time 237086520 ps
CPU time 0.91 seconds
Started Jul 14 07:13:28 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 206808 kb
Host smart-c0238079-9574-4569-9b89-47809d4d57d9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3334656511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.3334656511
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.475839166
Short name T1206
Test name
Test status
Simulation time 203850524 ps
CPU time 0.88 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 206840 kb
Host smart-0bac1a3a-96b1-44d2-9eb1-84799537cb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47583
9166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.475839166
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2582465343
Short name T1523
Test name
Test status
Simulation time 3621344221 ps
CPU time 99.87 seconds
Started Jul 14 07:13:30 PM PDT 24
Finished Jul 14 07:15:17 PM PDT 24
Peak memory 207068 kb
Host smart-7dd73014-96ee-431b-b6ee-dc7801708e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25824
65343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2582465343
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3991406717
Short name T1654
Test name
Test status
Simulation time 5977182288 ps
CPU time 42.16 seconds
Started Jul 14 07:13:27 PM PDT 24
Finished Jul 14 07:14:17 PM PDT 24
Peak memory 207108 kb
Host smart-077f837f-33bd-485b-a9f4-3a64d071fe8a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3991406717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3991406717
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2061079618
Short name T1244
Test name
Test status
Simulation time 158673024 ps
CPU time 0.84 seconds
Started Jul 14 07:13:33 PM PDT 24
Finished Jul 14 07:13:39 PM PDT 24
Peak memory 206888 kb
Host smart-4a12de13-6b3d-4d69-b08c-a75afb8fb63c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2061079618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2061079618
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.59740736
Short name T998
Test name
Test status
Simulation time 159809750 ps
CPU time 0.8 seconds
Started Jul 14 07:13:32 PM PDT 24
Finished Jul 14 07:13:39 PM PDT 24
Peak memory 206876 kb
Host smart-dda12d52-08c4-487c-92a5-25fbd0690771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59740
736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.59740736
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.117917032
Short name T133
Test name
Test status
Simulation time 191136482 ps
CPU time 0.81 seconds
Started Jul 14 07:13:33 PM PDT 24
Finished Jul 14 07:13:39 PM PDT 24
Peak memory 206892 kb
Host smart-97e9974f-5fe5-459d-b4fe-dca35fb48f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11791
7032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.117917032
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1380656721
Short name T1429
Test name
Test status
Simulation time 176961709 ps
CPU time 0.87 seconds
Started Jul 14 07:13:31 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 206856 kb
Host smart-3f8b0e83-6918-45e1-aa2e-d8e03aa7dd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13806
56721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1380656721
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1132931573
Short name T2466
Test name
Test status
Simulation time 185735119 ps
CPU time 0.82 seconds
Started Jul 14 07:13:31 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 206860 kb
Host smart-4b604ee2-5d3e-4ff3-a8ad-2fa6ec16eb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11329
31573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1132931573
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2691933102
Short name T1568
Test name
Test status
Simulation time 150551860 ps
CPU time 0.78 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 206876 kb
Host smart-4018be3b-e744-4095-910d-5a8432678b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26919
33102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2691933102
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.246187978
Short name T1778
Test name
Test status
Simulation time 162589465 ps
CPU time 0.8 seconds
Started Jul 14 07:13:30 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 206876 kb
Host smart-8e0e5b94-b1c1-43e7-8ee5-48df4dbb8170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24618
7978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.246187978
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.4086307607
Short name T421
Test name
Test status
Simulation time 205980843 ps
CPU time 0.83 seconds
Started Jul 14 07:13:31 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 206856 kb
Host smart-25a0b969-1aa7-4386-b0f2-c654fdd2c2f9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4086307607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.4086307607
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2836056473
Short name T1185
Test name
Test status
Simulation time 164162448 ps
CPU time 0.76 seconds
Started Jul 14 07:13:31 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 206892 kb
Host smart-3dbbd5c1-e1a8-4db6-bb3c-7e0119ab7ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28360
56473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2836056473
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.478877475
Short name T1669
Test name
Test status
Simulation time 66517808 ps
CPU time 0.68 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:13:36 PM PDT 24
Peak memory 206836 kb
Host smart-98f62c7a-9cea-4b36-b55d-7ebad4305a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47887
7475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.478877475
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3482750092
Short name T1495
Test name
Test status
Simulation time 17542402137 ps
CPU time 43.61 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:14:19 PM PDT 24
Peak memory 207112 kb
Host smart-5788246a-1e76-47ef-847f-818605e431eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34827
50092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3482750092
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.4148707282
Short name T2093
Test name
Test status
Simulation time 188143706 ps
CPU time 0.88 seconds
Started Jul 14 07:13:31 PM PDT 24
Finished Jul 14 07:13:38 PM PDT 24
Peak memory 206828 kb
Host smart-2970ac8f-3255-4f5a-9a32-7b06ed6c1550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
07282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4148707282
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3682986183
Short name T525
Test name
Test status
Simulation time 221427830 ps
CPU time 0.94 seconds
Started Jul 14 07:13:30 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 206872 kb
Host smart-e2bd6999-2416-4010-8c02-01d8681ac862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36829
86183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3682986183
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2739647737
Short name T1988
Test name
Test status
Simulation time 8953371149 ps
CPU time 55.42 seconds
Started Jul 14 07:13:30 PM PDT 24
Finished Jul 14 07:14:32 PM PDT 24
Peak memory 207180 kb
Host smart-ac1a0943-246f-4274-a78d-7429d7929cdd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2739647737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2739647737
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2721916667
Short name T2693
Test name
Test status
Simulation time 8919976831 ps
CPU time 214.38 seconds
Started Jul 14 07:13:39 PM PDT 24
Finished Jul 14 07:17:15 PM PDT 24
Peak memory 207164 kb
Host smart-e712dc83-09d9-4832-b6ce-2caa9548427e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2721916667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2721916667
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2187947981
Short name T949
Test name
Test status
Simulation time 8170201496 ps
CPU time 34.18 seconds
Started Jul 14 07:13:36 PM PDT 24
Finished Jul 14 07:14:14 PM PDT 24
Peak memory 207120 kb
Host smart-c6558453-08e8-4cd0-bc00-a9193f1b3c35
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2187947981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2187947981
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.710455180
Short name T1631
Test name
Test status
Simulation time 178718466 ps
CPU time 0.89 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 206892 kb
Host smart-5ac79be3-d58a-4410-a498-395c50088477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71045
5180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.710455180
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2925173877
Short name T2689
Test name
Test status
Simulation time 209837294 ps
CPU time 0.88 seconds
Started Jul 14 07:13:29 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 206900 kb
Host smart-d6160edd-7ce8-4a44-b382-970171eabf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
73877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2925173877
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.86353016
Short name T2074
Test name
Test status
Simulation time 181538584 ps
CPU time 0.86 seconds
Started Jul 14 07:13:36 PM PDT 24
Finished Jul 14 07:13:40 PM PDT 24
Peak memory 206832 kb
Host smart-cdea58c9-540f-4375-947c-5c7b78dd8b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86353
016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.86353016
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.673667864
Short name T142
Test name
Test status
Simulation time 167922738 ps
CPU time 0.79 seconds
Started Jul 14 07:13:36 PM PDT 24
Finished Jul 14 07:13:41 PM PDT 24
Peak memory 206852 kb
Host smart-3dd166ab-a8c2-4ea3-ab61-ad285e424a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67366
7864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.673667864
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2597480764
Short name T2474
Test name
Test status
Simulation time 204865788 ps
CPU time 0.85 seconds
Started Jul 14 07:13:37 PM PDT 24
Finished Jul 14 07:13:41 PM PDT 24
Peak memory 206860 kb
Host smart-28a60aa3-28bd-4150-b348-81514b136b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25974
80764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2597480764
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3351741077
Short name T1712
Test name
Test status
Simulation time 194187114 ps
CPU time 0.86 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:13:46 PM PDT 24
Peak memory 206884 kb
Host smart-6959c7c7-0959-4894-8447-f98c863e0a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33517
41077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3351741077
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2547486794
Short name T141
Test name
Test status
Simulation time 3516103207 ps
CPU time 31.07 seconds
Started Jul 14 07:13:35 PM PDT 24
Finished Jul 14 07:14:10 PM PDT 24
Peak memory 207100 kb
Host smart-02b0a253-762c-484a-bc89-0870a1c83248
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2547486794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2547486794
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2597077573
Short name T1118
Test name
Test status
Simulation time 191842645 ps
CPU time 0.84 seconds
Started Jul 14 07:13:35 PM PDT 24
Finished Jul 14 07:13:40 PM PDT 24
Peak memory 206860 kb
Host smart-4d1bd790-c8cf-4861-801f-fd164b9f5ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25970
77573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2597077573
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.188397358
Short name T2135
Test name
Test status
Simulation time 190834926 ps
CPU time 0.85 seconds
Started Jul 14 07:13:37 PM PDT 24
Finished Jul 14 07:13:41 PM PDT 24
Peak memory 206864 kb
Host smart-684b34fc-715b-4819-8f25-a11ce1f9a41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
7358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.188397358
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1227908856
Short name T1067
Test name
Test status
Simulation time 1025926814 ps
CPU time 2.22 seconds
Started Jul 14 07:13:37 PM PDT 24
Finished Jul 14 07:13:42 PM PDT 24
Peak memory 207072 kb
Host smart-14ef4314-c432-4e51-a097-95038d2896e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12279
08856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1227908856
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3064992679
Short name T2194
Test name
Test status
Simulation time 3330037838 ps
CPU time 32.05 seconds
Started Jul 14 07:13:35 PM PDT 24
Finished Jul 14 07:14:11 PM PDT 24
Peak memory 207096 kb
Host smart-02ef17ba-b524-4f45-856f-b353a9a14a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30649
92679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3064992679
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2330169957
Short name T2541
Test name
Test status
Simulation time 113661427 ps
CPU time 0.77 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 206892 kb
Host smart-d704de3b-6fad-41bc-ba15-d9be8245a220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2330169957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2330169957
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.813511903
Short name T2559
Test name
Test status
Simulation time 3396189465 ps
CPU time 4.63 seconds
Started Jul 14 07:13:36 PM PDT 24
Finished Jul 14 07:13:44 PM PDT 24
Peak memory 206924 kb
Host smart-ecc6734e-44cc-4e3e-83c4-62db6bedbe6e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=813511903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.813511903
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3301012168
Short name T1225
Test name
Test status
Simulation time 13442604769 ps
CPU time 13.14 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:13:59 PM PDT 24
Peak memory 206968 kb
Host smart-cd765449-0765-45b3-b363-b5e39e83e91b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3301012168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3301012168
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.753224748
Short name T1880
Test name
Test status
Simulation time 23415646305 ps
CPU time 23.34 seconds
Started Jul 14 07:13:34 PM PDT 24
Finished Jul 14 07:14:02 PM PDT 24
Peak memory 207044 kb
Host smart-409cae56-7128-4b3a-aa59-d4366846cde1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=753224748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.753224748
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.892191663
Short name T2020
Test name
Test status
Simulation time 151967523 ps
CPU time 0.76 seconds
Started Jul 14 07:13:41 PM PDT 24
Finished Jul 14 07:13:42 PM PDT 24
Peak memory 206880 kb
Host smart-89149eed-c100-4d84-8cef-321d7c90ea6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89219
1663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.892191663
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2775409604
Short name T2327
Test name
Test status
Simulation time 147458821 ps
CPU time 0.77 seconds
Started Jul 14 07:13:41 PM PDT 24
Finished Jul 14 07:13:43 PM PDT 24
Peak memory 206876 kb
Host smart-9e7575f1-f57a-4235-9258-b24e55cd0e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27754
09604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2775409604
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3750612789
Short name T100
Test name
Test status
Simulation time 945092088 ps
CPU time 2.13 seconds
Started Jul 14 07:13:42 PM PDT 24
Finished Jul 14 07:13:46 PM PDT 24
Peak memory 207044 kb
Host smart-c4b28b0f-166b-4754-9f1c-50f7aaf52270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37506
12789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3750612789
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2690895988
Short name T1659
Test name
Test status
Simulation time 13355723142 ps
CPU time 24.4 seconds
Started Jul 14 07:13:41 PM PDT 24
Finished Jul 14 07:14:07 PM PDT 24
Peak memory 207132 kb
Host smart-6d874134-acdd-478e-bb3c-b1757c45dd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26908
95988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2690895988
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2596225885
Short name T1334
Test name
Test status
Simulation time 488140673 ps
CPU time 1.42 seconds
Started Jul 14 07:13:42 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 206876 kb
Host smart-e36ffb14-933d-4865-9064-cb6dd9128487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25962
25885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2596225885
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2074795376
Short name T1674
Test name
Test status
Simulation time 174407247 ps
CPU time 0.78 seconds
Started Jul 14 07:13:42 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 206840 kb
Host smart-b28b2d62-e816-408b-aedc-7b0e15cf8788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20747
95376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2074795376
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3030705418
Short name T2586
Test name
Test status
Simulation time 33841723 ps
CPU time 0.63 seconds
Started Jul 14 07:13:42 PM PDT 24
Finished Jul 14 07:13:44 PM PDT 24
Peak memory 206844 kb
Host smart-55964d10-9aa8-439d-914c-5d7a3209c013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30307
05418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3030705418
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.735971865
Short name T1709
Test name
Test status
Simulation time 889441738 ps
CPU time 2.11 seconds
Started Jul 14 07:13:42 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 207072 kb
Host smart-a92ee4bf-1537-4f49-ae0b-71784bd17812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73597
1865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.735971865
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3818590529
Short name T1564
Test name
Test status
Simulation time 172172957 ps
CPU time 1.69 seconds
Started Jul 14 07:13:49 PM PDT 24
Finished Jul 14 07:13:52 PM PDT 24
Peak memory 207128 kb
Host smart-32956af2-6929-4772-b2c7-24253467a22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38185
90529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3818590529
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1756233250
Short name T1114
Test name
Test status
Simulation time 197250673 ps
CPU time 0.88 seconds
Started Jul 14 07:13:40 PM PDT 24
Finished Jul 14 07:13:42 PM PDT 24
Peak memory 206844 kb
Host smart-27dcfb44-ea63-4cfc-85c1-bcfb4ae5fba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17562
33250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1756233250
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2752411481
Short name T2402
Test name
Test status
Simulation time 141897872 ps
CPU time 0.77 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 206868 kb
Host smart-880a7acd-668f-4df2-93ab-dc1b93116075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27524
11481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2752411481
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2545161438
Short name T670
Test name
Test status
Simulation time 233331776 ps
CPU time 0.97 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:13:46 PM PDT 24
Peak memory 207044 kb
Host smart-814f069a-5831-47d6-bb83-1933aff026e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25451
61438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2545161438
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.893501288
Short name T2655
Test name
Test status
Simulation time 8046369254 ps
CPU time 70.58 seconds
Started Jul 14 07:13:45 PM PDT 24
Finished Jul 14 07:14:58 PM PDT 24
Peak memory 207128 kb
Host smart-7c71c6de-72f0-4bd4-87e4-b0d3b94bf881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89350
1288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.893501288
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2737146347
Short name T1867
Test name
Test status
Simulation time 176588002 ps
CPU time 0.84 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 206840 kb
Host smart-33f0cff4-42ad-47df-a32b-b1a301f198f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27371
46347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2737146347
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2855495019
Short name T2365
Test name
Test status
Simulation time 23266065996 ps
CPU time 22.13 seconds
Started Jul 14 07:13:45 PM PDT 24
Finished Jul 14 07:14:08 PM PDT 24
Peak memory 206948 kb
Host smart-00d4e1a9-3a4b-49aa-8ef0-864f17056c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28554
95019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2855495019
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.4162763602
Short name T2223
Test name
Test status
Simulation time 3323058795 ps
CPU time 3.6 seconds
Started Jul 14 07:13:45 PM PDT 24
Finished Jul 14 07:13:51 PM PDT 24
Peak memory 206976 kb
Host smart-0ff50330-90c8-4da0-85db-ec4b3d597e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41627
63602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.4162763602
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.560131170
Short name T1193
Test name
Test status
Simulation time 9372884565 ps
CPU time 244.34 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:18:00 PM PDT 24
Peak memory 207104 kb
Host smart-e2400085-9a8f-4205-9291-9d8f9e7edaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56013
1170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.560131170
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2626223372
Short name T2579
Test name
Test status
Simulation time 3153262220 ps
CPU time 30.95 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:14:16 PM PDT 24
Peak memory 207292 kb
Host smart-0bfea53b-ee28-4897-a692-55bd3c757b27
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2626223372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2626223372
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.755985608
Short name T530
Test name
Test status
Simulation time 252040475 ps
CPU time 0.95 seconds
Started Jul 14 07:13:41 PM PDT 24
Finished Jul 14 07:13:44 PM PDT 24
Peak memory 206880 kb
Host smart-e1e365f4-4884-40bb-ad9a-7742f5518772
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=755985608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.755985608
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2585858919
Short name T802
Test name
Test status
Simulation time 188446364 ps
CPU time 0.92 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:13:57 PM PDT 24
Peak memory 206876 kb
Host smart-c289ec61-18de-48f4-ac3c-ad0ceccfab67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25858
58919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2585858919
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2243006895
Short name T1766
Test name
Test status
Simulation time 6507223431 ps
CPU time 183.37 seconds
Started Jul 14 07:13:45 PM PDT 24
Finished Jul 14 07:16:51 PM PDT 24
Peak memory 207068 kb
Host smart-576b3be3-37d3-4188-b7c6-dfa162f2af40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22430
06895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2243006895
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.568008132
Short name T1048
Test name
Test status
Simulation time 4759348792 ps
CPU time 132.34 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:15:57 PM PDT 24
Peak memory 207076 kb
Host smart-bc560030-e10a-462b-8f92-ec1f64562e0c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=568008132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.568008132
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3351642841
Short name T2301
Test name
Test status
Simulation time 156047658 ps
CPU time 0.83 seconds
Started Jul 14 07:13:41 PM PDT 24
Finished Jul 14 07:13:43 PM PDT 24
Peak memory 206880 kb
Host smart-95bbf47e-1b9a-4d1f-b5b1-f4ca9b3efc16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3351642841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3351642841
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2011294328
Short name T2503
Test name
Test status
Simulation time 173695136 ps
CPU time 0.79 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:13:46 PM PDT 24
Peak memory 206868 kb
Host smart-a158158a-0a50-4c9f-9fe9-a4fb03d50d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20112
94328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2011294328
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1198653300
Short name T105
Test name
Test status
Simulation time 210678546 ps
CPU time 0.84 seconds
Started Jul 14 07:13:40 PM PDT 24
Finished Jul 14 07:13:42 PM PDT 24
Peak memory 206844 kb
Host smart-dc069165-8de7-4acb-ab45-ae7c425bccee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
53300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1198653300
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3082139690
Short name T2073
Test name
Test status
Simulation time 175187699 ps
CPU time 0.89 seconds
Started Jul 14 07:13:49 PM PDT 24
Finished Jul 14 07:13:51 PM PDT 24
Peak memory 206928 kb
Host smart-bf3bb371-3ceb-49bc-91f8-401c7c31b0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30821
39690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3082139690
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4052329406
Short name T509
Test name
Test status
Simulation time 199732328 ps
CPU time 0.83 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:13:57 PM PDT 24
Peak memory 206880 kb
Host smart-b386f4a6-b7ea-432e-8bbc-619d3fa76ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40523
29406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4052329406
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.641833990
Short name T840
Test name
Test status
Simulation time 179608216 ps
CPU time 0.79 seconds
Started Jul 14 07:13:41 PM PDT 24
Finished Jul 14 07:13:43 PM PDT 24
Peak memory 206884 kb
Host smart-52a24e86-2872-4dbe-99b5-84f157e21e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64183
3990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.641833990
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.947299290
Short name T451
Test name
Test status
Simulation time 163958030 ps
CPU time 0.79 seconds
Started Jul 14 07:13:42 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 206868 kb
Host smart-c4d1cda9-7658-4f2f-8904-89585bc0c6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94729
9290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.947299290
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2202209695
Short name T1229
Test name
Test status
Simulation time 268511666 ps
CPU time 0.94 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:13:57 PM PDT 24
Peak memory 206852 kb
Host smart-8a8f91b7-15f2-4f61-b0f1-0cfd94d33fb2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2202209695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2202209695
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3388517354
Short name T573
Test name
Test status
Simulation time 211132641 ps
CPU time 0.86 seconds
Started Jul 14 07:13:42 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 206892 kb
Host smart-d6e88835-7901-41c9-bbcb-95e6e26305d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33885
17354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3388517354
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3870953318
Short name T2212
Test name
Test status
Simulation time 80902488 ps
CPU time 0.7 seconds
Started Jul 14 07:13:43 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 206868 kb
Host smart-bc8c320f-2df8-4758-922e-b3af2eded916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
53318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3870953318
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1487045439
Short name T2625
Test name
Test status
Simulation time 16912880085 ps
CPU time 34.33 seconds
Started Jul 14 07:13:49 PM PDT 24
Finished Jul 14 07:14:25 PM PDT 24
Peak memory 207168 kb
Host smart-b118fb36-4ef4-4515-897b-ecaf48f96c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14870
45439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1487045439
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.4278001725
Short name T1180
Test name
Test status
Simulation time 200876109 ps
CPU time 0.96 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 206884 kb
Host smart-f3fd2d55-6066-46e9-8598-57c41bde3139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42780
01725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.4278001725
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3397126780
Short name T238
Test name
Test status
Simulation time 237396735 ps
CPU time 0.89 seconds
Started Jul 14 07:13:50 PM PDT 24
Finished Jul 14 07:13:54 PM PDT 24
Peak memory 206844 kb
Host smart-9e897c29-56ca-4fa8-ac62-2151bc68075d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33971
26780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3397126780
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3270800311
Short name T1937
Test name
Test status
Simulation time 7555581374 ps
CPU time 118.82 seconds
Started Jul 14 07:13:49 PM PDT 24
Finished Jul 14 07:15:49 PM PDT 24
Peak memory 207184 kb
Host smart-8fd1dfb3-e0b5-4a15-89f4-b51d06181d62
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3270800311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3270800311
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1036504014
Short name T1767
Test name
Test status
Simulation time 13936185482 ps
CPU time 75.65 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:15:12 PM PDT 24
Peak memory 207128 kb
Host smart-1521e8bd-74e9-44f9-babd-19673cd190f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1036504014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1036504014
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1711834428
Short name T677
Test name
Test status
Simulation time 190213375 ps
CPU time 0.89 seconds
Started Jul 14 07:13:47 PM PDT 24
Finished Jul 14 07:13:49 PM PDT 24
Peak memory 206864 kb
Host smart-fc717a94-8b0d-4c4d-9cde-63a63d58e425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17118
34428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1711834428
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3100756437
Short name T770
Test name
Test status
Simulation time 180922086 ps
CPU time 0.85 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:13:58 PM PDT 24
Peak memory 206856 kb
Host smart-fdc42cc7-0cf4-4764-b893-3f80ae7333ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31007
56437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3100756437
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2962841186
Short name T2596
Test name
Test status
Simulation time 143539441 ps
CPU time 0.75 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:13:58 PM PDT 24
Peak memory 206856 kb
Host smart-f3a7f491-8898-4ddf-9062-0c52a01181d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29628
41186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2962841186
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1685356917
Short name T2363
Test name
Test status
Simulation time 167526682 ps
CPU time 0.77 seconds
Started Jul 14 07:13:46 PM PDT 24
Finished Jul 14 07:13:48 PM PDT 24
Peak memory 206884 kb
Host smart-8b6371fd-b3f9-4eac-bd21-64b06a2bf02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16853
56917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1685356917
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2460028018
Short name T1759
Test name
Test status
Simulation time 178066849 ps
CPU time 0.79 seconds
Started Jul 14 07:13:48 PM PDT 24
Finished Jul 14 07:13:50 PM PDT 24
Peak memory 206860 kb
Host smart-1bced384-aafa-497d-b5f3-8500a79766a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24600
28018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2460028018
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3612850252
Short name T1075
Test name
Test status
Simulation time 228132017 ps
CPU time 0.98 seconds
Started Jul 14 07:13:48 PM PDT 24
Finished Jul 14 07:13:49 PM PDT 24
Peak memory 206836 kb
Host smart-10249d65-0f7d-48ea-9459-132d12dc0502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36128
50252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3612850252
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.4114756027
Short name T638
Test name
Test status
Simulation time 5466784049 ps
CPU time 47.79 seconds
Started Jul 14 07:13:50 PM PDT 24
Finished Jul 14 07:14:40 PM PDT 24
Peak memory 207136 kb
Host smart-7956b8b8-9f84-4e46-a53a-e0990a6172fc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4114756027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.4114756027
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.4173469004
Short name T1058
Test name
Test status
Simulation time 175188159 ps
CPU time 0.81 seconds
Started Jul 14 07:13:49 PM PDT 24
Finished Jul 14 07:13:52 PM PDT 24
Peak memory 206876 kb
Host smart-9b256e3f-ca09-423e-a328-f53ef26c0250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
69004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.4173469004
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1245265486
Short name T2618
Test name
Test status
Simulation time 148197684 ps
CPU time 0.82 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:13:56 PM PDT 24
Peak memory 206876 kb
Host smart-1c529c6e-15a0-4364-95d2-3a20da67c41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12452
65486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1245265486
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.4199606675
Short name T344
Test name
Test status
Simulation time 448822698 ps
CPU time 1.33 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:13:58 PM PDT 24
Peak memory 206856 kb
Host smart-d6cf5516-cd2c-435a-9dc4-2f093a220923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41996
06675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.4199606675
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.376770585
Short name T2678
Test name
Test status
Simulation time 7277165698 ps
CPU time 51.95 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:14:46 PM PDT 24
Peak memory 207128 kb
Host smart-2e10d1df-cebd-4e2a-8e0f-7a08d4e8f5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37677
0585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.376770585
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1436868173
Short name T2032
Test name
Test status
Simulation time 39497525 ps
CPU time 0.65 seconds
Started Jul 14 07:14:04 PM PDT 24
Finished Jul 14 07:14:19 PM PDT 24
Peak memory 206916 kb
Host smart-0fb09879-959d-49b0-975d-43802207fb34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1436868173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1436868173
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3570992699
Short name T218
Test name
Test status
Simulation time 4080750374 ps
CPU time 5.4 seconds
Started Jul 14 07:13:50 PM PDT 24
Finished Jul 14 07:13:59 PM PDT 24
Peak memory 207112 kb
Host smart-ac59eb1b-4ebb-4516-88ac-067aae753a02
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3570992699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3570992699
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3800925872
Short name T2094
Test name
Test status
Simulation time 13305056711 ps
CPU time 12.76 seconds
Started Jul 14 07:13:46 PM PDT 24
Finished Jul 14 07:14:00 PM PDT 24
Peak memory 206876 kb
Host smart-738bddd7-e26d-45c1-b876-04005ba9b924
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3800925872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3800925872
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1554970254
Short name T9
Test name
Test status
Simulation time 23359315094 ps
CPU time 26.71 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:14:21 PM PDT 24
Peak memory 206952 kb
Host smart-c0416d4e-7f23-4b35-9ea4-daab30845282
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1554970254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.1554970254
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3188747571
Short name T1176
Test name
Test status
Simulation time 153512067 ps
CPU time 0.78 seconds
Started Jul 14 07:13:49 PM PDT 24
Finished Jul 14 07:13:51 PM PDT 24
Peak memory 206876 kb
Host smart-9f8d8b5b-ab43-469e-80fd-97af55529d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887
47571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3188747571
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1553576623
Short name T1955
Test name
Test status
Simulation time 152660786 ps
CPU time 0.81 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 206896 kb
Host smart-8faf98b3-a6fe-4280-a3f4-f71bff93cd02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15535
76623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1553576623
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3725834745
Short name T2696
Test name
Test status
Simulation time 259113067 ps
CPU time 1.02 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 207044 kb
Host smart-abb683fc-ddb0-4b8a-b9f6-2ab81ee1e77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
34745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3725834745
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2074787885
Short name T2145
Test name
Test status
Simulation time 19450364747 ps
CPU time 36.67 seconds
Started Jul 14 07:13:49 PM PDT 24
Finished Jul 14 07:14:28 PM PDT 24
Peak memory 207120 kb
Host smart-052ba0e6-a743-4731-a6b8-a3b0edbe66f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20747
87885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2074787885
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1478717808
Short name T2126
Test name
Test status
Simulation time 486011783 ps
CPU time 1.44 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 206888 kb
Host smart-6f6c2b6d-e944-47c5-8f2f-d8e72c9ebdb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14787
17808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1478717808
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.4021857173
Short name T1884
Test name
Test status
Simulation time 149112980 ps
CPU time 0.77 seconds
Started Jul 14 07:13:50 PM PDT 24
Finished Jul 14 07:13:53 PM PDT 24
Peak memory 206852 kb
Host smart-017faea8-0bf3-4ed4-bfc7-f1bc82bfc231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40218
57173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.4021857173
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.64281404
Short name T1645
Test name
Test status
Simulation time 64621341 ps
CPU time 0.68 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:13:59 PM PDT 24
Peak memory 206864 kb
Host smart-d06c2a34-9cc6-4276-a4b0-cfaf966a9c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64281
404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.64281404
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.108067494
Short name T1910
Test name
Test status
Simulation time 944231072 ps
CPU time 2.29 seconds
Started Jul 14 07:13:48 PM PDT 24
Finished Jul 14 07:13:52 PM PDT 24
Peak memory 207064 kb
Host smart-a78bb27f-ebed-446a-87fc-ab9442960daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10806
7494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.108067494
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1947344636
Short name T1238
Test name
Test status
Simulation time 308786312 ps
CPU time 2.4 seconds
Started Jul 14 07:13:52 PM PDT 24
Finished Jul 14 07:13:57 PM PDT 24
Peak memory 207052 kb
Host smart-5f2022bf-e361-42c7-9008-15742193c87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19473
44636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1947344636
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.4227384362
Short name T747
Test name
Test status
Simulation time 251242284 ps
CPU time 0.9 seconds
Started Jul 14 07:13:50 PM PDT 24
Finished Jul 14 07:13:54 PM PDT 24
Peak memory 206868 kb
Host smart-84d02601-fbb5-418d-9d6c-32b2b9992ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42273
84362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.4227384362
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2032617336
Short name T1948
Test name
Test status
Simulation time 156899463 ps
CPU time 0.78 seconds
Started Jul 14 07:13:50 PM PDT 24
Finished Jul 14 07:13:54 PM PDT 24
Peak memory 206924 kb
Host smart-9ba83c52-216d-4ad1-9da4-63a4c894a7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20326
17336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2032617336
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.567334566
Short name T758
Test name
Test status
Simulation time 234862528 ps
CPU time 0.87 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:13:55 PM PDT 24
Peak memory 206840 kb
Host smart-e0f926f0-f610-4e64-ae04-dc7a1d97bc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56733
4566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.567334566
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.1263439493
Short name T1460
Test name
Test status
Simulation time 6090971165 ps
CPU time 23.88 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:14:18 PM PDT 24
Peak memory 207124 kb
Host smart-9b6fe107-ca11-409c-8843-d3d4745dc893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12634
39493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.1263439493
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1026174760
Short name T2227
Test name
Test status
Simulation time 192598460 ps
CPU time 0.84 seconds
Started Jul 14 07:13:48 PM PDT 24
Finished Jul 14 07:13:50 PM PDT 24
Peak memory 206892 kb
Host smart-2d142fab-c241-428c-956d-4f40ac2d4f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10261
74760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1026174760
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3817199
Short name T1181
Test name
Test status
Simulation time 23400406641 ps
CPU time 22.03 seconds
Started Jul 14 07:13:50 PM PDT 24
Finished Jul 14 07:14:15 PM PDT 24
Peak memory 206956 kb
Host smart-72e4e7b7-958f-4ffa-a651-cf9278d7362e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38171
99 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3817199
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3301960223
Short name T783
Test name
Test status
Simulation time 3310046540 ps
CPU time 3.73 seconds
Started Jul 14 07:13:51 PM PDT 24
Finished Jul 14 07:13:58 PM PDT 24
Peak memory 206944 kb
Host smart-5ecc507e-9855-4bb0-8509-26999e20e094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33019
60223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3301960223
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.877054303
Short name T1062
Test name
Test status
Simulation time 11201015248 ps
CPU time 312.67 seconds
Started Jul 14 07:13:48 PM PDT 24
Finished Jul 14 07:19:02 PM PDT 24
Peak memory 207164 kb
Host smart-1cb94025-4baf-49a8-9261-4b2c098829ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87705
4303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.877054303
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.173247086
Short name T984
Test name
Test status
Simulation time 4994822835 ps
CPU time 136.23 seconds
Started Jul 14 07:13:59 PM PDT 24
Finished Jul 14 07:16:24 PM PDT 24
Peak memory 207024 kb
Host smart-42f214bb-f595-4ace-98ab-f99c926d587b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=173247086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.173247086
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.219145087
Short name T1497
Test name
Test status
Simulation time 246219478 ps
CPU time 0.88 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:13:58 PM PDT 24
Peak memory 206964 kb
Host smart-30f1e8e3-6353-4188-8119-a97bc87508ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=219145087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.219145087
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1705826127
Short name T1424
Test name
Test status
Simulation time 202656565 ps
CPU time 0.85 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:11 PM PDT 24
Peak memory 206824 kb
Host smart-39816308-b777-4e2c-bfc4-565d16348731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17058
26127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1705826127
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2508549243
Short name T600
Test name
Test status
Simulation time 5398681357 ps
CPU time 142.32 seconds
Started Jul 14 07:13:54 PM PDT 24
Finished Jul 14 07:16:22 PM PDT 24
Peak memory 207256 kb
Host smart-b673327d-e352-4317-986d-6c9505a50390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25085
49243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2508549243
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1056233554
Short name T2558
Test name
Test status
Simulation time 6448916023 ps
CPU time 176.84 seconds
Started Jul 14 07:13:57 PM PDT 24
Finished Jul 14 07:17:01 PM PDT 24
Peak memory 207072 kb
Host smart-364a162a-d736-461e-b371-a32228d37423
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1056233554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1056233554
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3908167162
Short name T2241
Test name
Test status
Simulation time 222699891 ps
CPU time 0.85 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:19 PM PDT 24
Peak memory 206892 kb
Host smart-16fc03d0-589d-4744-a908-94bd347d3ec2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3908167162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3908167162
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.988652539
Short name T499
Test name
Test status
Simulation time 144198681 ps
CPU time 0.74 seconds
Started Jul 14 07:13:55 PM PDT 24
Finished Jul 14 07:14:01 PM PDT 24
Peak memory 206860 kb
Host smart-f5913334-6e90-4cc2-8971-50f3fb125a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98865
2539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.988652539
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3986887890
Short name T2122
Test name
Test status
Simulation time 246295173 ps
CPU time 0.9 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:11 PM PDT 24
Peak memory 206912 kb
Host smart-9c79e36f-deae-4088-95ff-da20f2bb89c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39868
87890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3986887890
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1923336648
Short name T90
Test name
Test status
Simulation time 190903925 ps
CPU time 0.91 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:13:59 PM PDT 24
Peak memory 206856 kb
Host smart-edf51a76-ad96-4f42-a4c6-fb672875606c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19233
36648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1923336648
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2567946
Short name T440
Test name
Test status
Simulation time 192347782 ps
CPU time 0.83 seconds
Started Jul 14 07:13:55 PM PDT 24
Finished Jul 14 07:14:01 PM PDT 24
Peak memory 206872 kb
Host smart-0741e6ad-795b-4bf9-89a8-a4d503a0f5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25679
46 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2567946
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1761801454
Short name T1572
Test name
Test status
Simulation time 174362380 ps
CPU time 0.8 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:13:58 PM PDT 24
Peak memory 206888 kb
Host smart-52e8348b-88d9-4042-9f8e-e73060b01a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17618
01454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1761801454
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.630464897
Short name T1686
Test name
Test status
Simulation time 204528995 ps
CPU time 0.8 seconds
Started Jul 14 07:13:54 PM PDT 24
Finished Jul 14 07:14:00 PM PDT 24
Peak memory 206884 kb
Host smart-a7cfb9f9-77f1-44d7-b077-8926ca0feeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63046
4897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.630464897
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2902047763
Short name T979
Test name
Test status
Simulation time 183687327 ps
CPU time 0.81 seconds
Started Jul 14 07:13:55 PM PDT 24
Finished Jul 14 07:14:02 PM PDT 24
Peak memory 206896 kb
Host smart-a029cc33-ac0a-4c12-8ccf-0cfec9be6d5e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2902047763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2902047763
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.485581023
Short name T1573
Test name
Test status
Simulation time 176221121 ps
CPU time 0.82 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:10 PM PDT 24
Peak memory 206868 kb
Host smart-22fabaa5-4b21-4aaf-8b73-f897988f49cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48558
1023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.485581023
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2192114560
Short name T25
Test name
Test status
Simulation time 94792215 ps
CPU time 0.68 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:14 PM PDT 24
Peak memory 206820 kb
Host smart-9eaa7756-7db5-48ef-8339-22b47d382ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21921
14560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2192114560
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.4031770384
Short name T726
Test name
Test status
Simulation time 11193727695 ps
CPU time 24.38 seconds
Started Jul 14 07:13:57 PM PDT 24
Finished Jul 14 07:14:27 PM PDT 24
Peak memory 207152 kb
Host smart-fb155eac-1fd0-4616-ba72-5b36b3c916e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40317
70384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.4031770384
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2350276652
Short name T1897
Test name
Test status
Simulation time 192036754 ps
CPU time 0.89 seconds
Started Jul 14 07:13:57 PM PDT 24
Finished Jul 14 07:14:05 PM PDT 24
Peak memory 206844 kb
Host smart-3922cd70-3578-4598-ac72-10a66703b280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23502
76652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2350276652
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.32472245
Short name T2425
Test name
Test status
Simulation time 254432630 ps
CPU time 0.9 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:00 PM PDT 24
Peak memory 206856 kb
Host smart-45b9c36c-50b5-482e-9e88-b97e6420de60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472
245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.32472245
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3374170204
Short name T1734
Test name
Test status
Simulation time 12866653356 ps
CPU time 272.09 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:19:41 PM PDT 24
Peak memory 207160 kb
Host smart-5750e43e-51c3-4872-9f30-4dba5031584b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3374170204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3374170204
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3938428899
Short name T2527
Test name
Test status
Simulation time 12061345385 ps
CPU time 58.1 seconds
Started Jul 14 07:13:57 PM PDT 24
Finished Jul 14 07:15:03 PM PDT 24
Peak memory 207068 kb
Host smart-5ada8f59-9934-4326-865d-8adbbe35cd00
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3938428899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3938428899
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3864052971
Short name T909
Test name
Test status
Simulation time 17175316871 ps
CPU time 121.54 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:16:00 PM PDT 24
Peak memory 207156 kb
Host smart-b82c0470-1f6a-4185-96c0-65973ac71255
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3864052971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3864052971
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.3930394152
Short name T237
Test name
Test status
Simulation time 158059998 ps
CPU time 0.81 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206860 kb
Host smart-d219e0ab-e803-4aa3-80e3-b46861e28507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39303
94152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.3930394152
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1580100703
Short name T316
Test name
Test status
Simulation time 152015931 ps
CPU time 0.8 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206840 kb
Host smart-937f5656-b6f3-41eb-bd01-4aa76cdc0ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15801
00703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1580100703
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3983407322
Short name T1828
Test name
Test status
Simulation time 161758579 ps
CPU time 0.8 seconds
Started Jul 14 07:13:54 PM PDT 24
Finished Jul 14 07:14:00 PM PDT 24
Peak memory 206840 kb
Host smart-520401c3-57bf-48dc-91b0-1b4c2c9881ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39834
07322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3983407322
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1683906847
Short name T1307
Test name
Test status
Simulation time 158359412 ps
CPU time 0.79 seconds
Started Jul 14 07:13:56 PM PDT 24
Finished Jul 14 07:14:02 PM PDT 24
Peak memory 206800 kb
Host smart-122440f4-5837-4d76-9b81-455842a2fdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16839
06847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1683906847
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2706210801
Short name T1408
Test name
Test status
Simulation time 154642883 ps
CPU time 0.79 seconds
Started Jul 14 07:13:56 PM PDT 24
Finished Jul 14 07:14:03 PM PDT 24
Peak memory 206840 kb
Host smart-0427893a-dcc6-4f1b-b033-066808395fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27062
10801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2706210801
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2837461815
Short name T1924
Test name
Test status
Simulation time 252104251 ps
CPU time 1.03 seconds
Started Jul 14 07:13:54 PM PDT 24
Finished Jul 14 07:14:01 PM PDT 24
Peak memory 206868 kb
Host smart-03da2b37-f6b1-4f36-97dc-fdcadeddee7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
61815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2837461815
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.4266984486
Short name T2202
Test name
Test status
Simulation time 5973858727 ps
CPU time 154.97 seconds
Started Jul 14 07:13:56 PM PDT 24
Finished Jul 14 07:16:37 PM PDT 24
Peak memory 207048 kb
Host smart-136381c8-df53-4087-b2f0-5a66e37e958d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4266984486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.4266984486
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3907248089
Short name T842
Test name
Test status
Simulation time 225912554 ps
CPU time 0.84 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206860 kb
Host smart-4b56dbdf-2c53-432e-a18b-e8d8e7f7b0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
48089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3907248089
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3177055074
Short name T523
Test name
Test status
Simulation time 204836966 ps
CPU time 0.79 seconds
Started Jul 14 07:13:53 PM PDT 24
Finished Jul 14 07:13:59 PM PDT 24
Peak memory 206872 kb
Host smart-2e063b35-dd2d-482e-9c41-daafc8fd36c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31770
55074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3177055074
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2455910292
Short name T2274
Test name
Test status
Simulation time 547434534 ps
CPU time 1.41 seconds
Started Jul 14 07:13:57 PM PDT 24
Finished Jul 14 07:14:05 PM PDT 24
Peak memory 206840 kb
Host smart-9ab22c3e-3676-4b5f-b5a0-de7c24f753e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24559
10292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2455910292
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2596169851
Short name T2482
Test name
Test status
Simulation time 4440057503 ps
CPU time 41.27 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:14:57 PM PDT 24
Peak memory 207096 kb
Host smart-688f7614-957a-4d4c-9d8e-4d004138d672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25961
69851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2596169851
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.3583270750
Short name T2610
Test name
Test status
Simulation time 47806982 ps
CPU time 0.66 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:12 PM PDT 24
Peak memory 206888 kb
Host smart-f1f9e788-a09b-49bd-a357-5f700ced48a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3583270750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.3583270750
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.772401313
Short name T2340
Test name
Test status
Simulation time 3681534458 ps
CPU time 5.44 seconds
Started Jul 14 07:13:57 PM PDT 24
Finished Jul 14 07:14:08 PM PDT 24
Peak memory 207084 kb
Host smart-9597a6ea-ced3-49b6-9331-41780523f314
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=772401313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.772401313
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3157816241
Short name T2496
Test name
Test status
Simulation time 13312315966 ps
CPU time 12.8 seconds
Started Jul 14 07:13:55 PM PDT 24
Finished Jul 14 07:14:14 PM PDT 24
Peak memory 206908 kb
Host smart-2200b6d2-6c4e-4043-8f42-ccf221c8c408
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3157816241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3157816241
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1108921907
Short name T2120
Test name
Test status
Simulation time 23287764527 ps
CPU time 20.7 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:31 PM PDT 24
Peak memory 207092 kb
Host smart-615fcc4a-ec5a-49f7-adce-85847e64d9c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1108921907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.1108921907
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.444303604
Short name T2550
Test name
Test status
Simulation time 172589651 ps
CPU time 0.79 seconds
Started Jul 14 07:14:04 PM PDT 24
Finished Jul 14 07:14:19 PM PDT 24
Peak memory 206880 kb
Host smart-39af103d-c938-4fd2-bf2e-b65918a106ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44430
3604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.444303604
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1974322669
Short name T1402
Test name
Test status
Simulation time 149731886 ps
CPU time 0.76 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:14:17 PM PDT 24
Peak memory 206832 kb
Host smart-c571bd38-b739-4710-a4b0-d8de18f19463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19743
22669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1974322669
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.4052032450
Short name T2159
Test name
Test status
Simulation time 268610871 ps
CPU time 1.05 seconds
Started Jul 14 07:13:59 PM PDT 24
Finished Jul 14 07:14:09 PM PDT 24
Peak memory 206884 kb
Host smart-7d0f68c7-d0e4-48cd-b12e-7e69f1b1e516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
32450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.4052032450
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.974478859
Short name T2321
Test name
Test status
Simulation time 431000446 ps
CPU time 1.35 seconds
Started Jul 14 07:13:56 PM PDT 24
Finished Jul 14 07:14:03 PM PDT 24
Peak memory 206852 kb
Host smart-00cd7afb-e6e0-44a5-8e48-646293aebd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97447
8859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.974478859
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2912897841
Short name T2568
Test name
Test status
Simulation time 16628103386 ps
CPU time 30.75 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:40 PM PDT 24
Peak memory 207076 kb
Host smart-d8cd8cfa-4eeb-4d8b-9fa7-fcce5a23b0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29128
97841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2912897841
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1415371354
Short name T2294
Test name
Test status
Simulation time 371752067 ps
CPU time 1.23 seconds
Started Jul 14 07:13:55 PM PDT 24
Finished Jul 14 07:14:02 PM PDT 24
Peak memory 206808 kb
Host smart-eda7147a-30e2-4458-a850-36fbdf41526b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
71354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1415371354
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2893302933
Short name T1367
Test name
Test status
Simulation time 155848281 ps
CPU time 0.76 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:10 PM PDT 24
Peak memory 206868 kb
Host smart-fe995f6a-4b98-4da5-9de1-254cb8d3e720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28933
02933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2893302933
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2415551355
Short name T1121
Test name
Test status
Simulation time 43308708 ps
CPU time 0.64 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:19 PM PDT 24
Peak memory 206880 kb
Host smart-6ad5a3df-a807-4a77-a9a9-6f047c91a3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24155
51355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2415551355
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2878388507
Short name T526
Test name
Test status
Simulation time 1063846463 ps
CPU time 2.54 seconds
Started Jul 14 07:13:57 PM PDT 24
Finished Jul 14 07:14:06 PM PDT 24
Peak memory 206972 kb
Host smart-cce34365-7ede-4dfb-9f94-17a68d59fe95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28783
88507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2878388507
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1291744659
Short name T187
Test name
Test status
Simulation time 176593175 ps
CPU time 1.57 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:12 PM PDT 24
Peak memory 207020 kb
Host smart-9665c302-b610-4f6d-91ff-11118d4918bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12917
44659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1291744659
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1340724493
Short name T2046
Test name
Test status
Simulation time 179562553 ps
CPU time 0.84 seconds
Started Jul 14 07:13:57 PM PDT 24
Finished Jul 14 07:14:05 PM PDT 24
Peak memory 206880 kb
Host smart-9427f965-c891-4a9d-8b3f-f5cae6bd50c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13407
24493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1340724493
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2790701489
Short name T955
Test name
Test status
Simulation time 171603303 ps
CPU time 0.8 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:12 PM PDT 24
Peak memory 206912 kb
Host smart-8fe5456e-c379-4109-aa9d-7079bc8b45d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27907
01489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2790701489
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3066447162
Short name T1251
Test name
Test status
Simulation time 213512506 ps
CPU time 0.91 seconds
Started Jul 14 07:14:09 PM PDT 24
Finished Jul 14 07:15:10 PM PDT 24
Peak memory 206856 kb
Host smart-89cb070d-f8be-4e9f-a6aa-e44d80215621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30664
47162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3066447162
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.61227422
Short name T974
Test name
Test status
Simulation time 6329296047 ps
CPU time 44.39 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:56 PM PDT 24
Peak memory 207120 kb
Host smart-3f469d79-f95d-4937-b650-6ed08badae57
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=61227422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.61227422
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.3616062246
Short name T2221
Test name
Test status
Simulation time 10126794185 ps
CPU time 31.2 seconds
Started Jul 14 07:13:59 PM PDT 24
Finished Jul 14 07:14:39 PM PDT 24
Peak memory 207016 kb
Host smart-9fb626a4-ca14-4408-ac8f-529afff5b7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36160
62246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3616062246
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2790335567
Short name T1388
Test name
Test status
Simulation time 198132058 ps
CPU time 0.89 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:11 PM PDT 24
Peak memory 206916 kb
Host smart-5a227167-88b5-4230-acc5-7bd813f940dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27903
35567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2790335567
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1614039073
Short name T42
Test name
Test status
Simulation time 23333215412 ps
CPU time 21.05 seconds
Started Jul 14 07:13:59 PM PDT 24
Finished Jul 14 07:14:28 PM PDT 24
Peak memory 206924 kb
Host smart-3b95867a-6914-4607-b3af-c9707a1086f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16140
39073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1614039073
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3737258460
Short name T1245
Test name
Test status
Simulation time 3279349506 ps
CPU time 4.23 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:13 PM PDT 24
Peak memory 206920 kb
Host smart-b312cb4b-2850-4eb0-a5f8-f8cbd69ebacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37372
58460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3737258460
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1564482587
Short name T146
Test name
Test status
Simulation time 11737728623 ps
CPU time 80.16 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:15:31 PM PDT 24
Peak memory 207160 kb
Host smart-55bc7640-c442-4d9c-83df-e1f2a111e892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15644
82587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1564482587
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.1393275237
Short name T2699
Test name
Test status
Simulation time 5990374082 ps
CPU time 163.65 seconds
Started Jul 14 07:14:06 PM PDT 24
Finished Jul 14 07:17:14 PM PDT 24
Peak memory 206988 kb
Host smart-152a7e09-6c57-4170-a7bd-b0cd624f75b0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1393275237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.1393275237
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2743427197
Short name T610
Test name
Test status
Simulation time 291443306 ps
CPU time 0.96 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:14 PM PDT 24
Peak memory 206884 kb
Host smart-a05e7901-778a-4253-94b9-43ac50d16f31
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2743427197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2743427197
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2919660517
Short name T871
Test name
Test status
Simulation time 188956459 ps
CPU time 0.86 seconds
Started Jul 14 07:14:16 PM PDT 24
Finished Jul 14 07:15:55 PM PDT 24
Peak memory 206840 kb
Host smart-09b34ec3-a5d6-420d-adc0-e4e142ace69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29196
60517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2919660517
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.260999324
Short name T720
Test name
Test status
Simulation time 4822256742 ps
CPU time 128.92 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:16:27 PM PDT 24
Peak memory 207056 kb
Host smart-ef2dd63d-84a4-4949-a4a6-6892c15c3849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26099
9324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.260999324
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3562397783
Short name T1007
Test name
Test status
Simulation time 3371023538 ps
CPU time 91.11 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:15:47 PM PDT 24
Peak memory 207056 kb
Host smart-aef9fa4f-cc33-4794-88ff-a59619f45472
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3562397783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3562397783
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3747035923
Short name T1694
Test name
Test status
Simulation time 158604085 ps
CPU time 0.78 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:10 PM PDT 24
Peak memory 206828 kb
Host smart-bdb138f4-62a3-4b81-af7f-fecbfab7ca36
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3747035923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3747035923
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3559713895
Short name T2141
Test name
Test status
Simulation time 209760561 ps
CPU time 0.88 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:17 PM PDT 24
Peak memory 206860 kb
Host smart-c4087265-0a67-4a11-9665-3912709f0283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35597
13895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3559713895
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1605741288
Short name T107
Test name
Test status
Simulation time 260734611 ps
CPU time 0.9 seconds
Started Jul 14 07:14:04 PM PDT 24
Finished Jul 14 07:14:19 PM PDT 24
Peak memory 206852 kb
Host smart-696e5af3-d1b4-4470-ad9e-6a0a95615fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16057
41288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1605741288
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2167911767
Short name T612
Test name
Test status
Simulation time 161730988 ps
CPU time 0.85 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:19 PM PDT 24
Peak memory 206848 kb
Host smart-ad161d23-1b90-436e-9f68-85482b5c49d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21679
11767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2167911767
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.973112095
Short name T2514
Test name
Test status
Simulation time 165969555 ps
CPU time 0.77 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:12 PM PDT 24
Peak memory 206892 kb
Host smart-b1499268-d465-4f19-839e-66bf050c28fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97311
2095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.973112095
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4120695686
Short name T1777
Test name
Test status
Simulation time 166768319 ps
CPU time 0.77 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:14:16 PM PDT 24
Peak memory 206872 kb
Host smart-bef11974-d6c9-41cb-a523-bd03eb5992d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41206
95686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4120695686
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1848918013
Short name T1468
Test name
Test status
Simulation time 156774635 ps
CPU time 0.76 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:17 PM PDT 24
Peak memory 206872 kb
Host smart-068969e4-b6f0-4d4b-900b-c7a002ee6a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18489
18013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1848918013
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.787227586
Short name T1248
Test name
Test status
Simulation time 247528043 ps
CPU time 0.86 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:17 PM PDT 24
Peak memory 206920 kb
Host smart-d48f0e6f-f55f-4f1c-a3ef-f5b022047b36
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=787227586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.787227586
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2204365300
Short name T2066
Test name
Test status
Simulation time 149253960 ps
CPU time 0.79 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:11 PM PDT 24
Peak memory 206872 kb
Host smart-4ccce53f-f1d8-4d7e-832e-9f6531a5cce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22043
65300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2204365300
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2788617230
Short name T1762
Test name
Test status
Simulation time 41837204 ps
CPU time 0.67 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:14:14 PM PDT 24
Peak memory 206860 kb
Host smart-9e6c9465-bbdd-4f74-859b-55dd7ce22cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27886
17230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2788617230
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1493343015
Short name T859
Test name
Test status
Simulation time 21102098439 ps
CPU time 52.25 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:15:11 PM PDT 24
Peak memory 215352 kb
Host smart-18231d1d-0f0c-4ce8-a45c-361c94c11e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14933
43015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1493343015
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2795577054
Short name T2358
Test name
Test status
Simulation time 181779333 ps
CPU time 0.81 seconds
Started Jul 14 07:14:06 PM PDT 24
Finished Jul 14 07:14:31 PM PDT 24
Peak memory 206820 kb
Host smart-9bd152ed-ba99-4226-8419-d42068fe0c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
77054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2795577054
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3637577590
Short name T1925
Test name
Test status
Simulation time 296858038 ps
CPU time 0.94 seconds
Started Jul 14 07:14:16 PM PDT 24
Finished Jul 14 07:16:19 PM PDT 24
Peak memory 206848 kb
Host smart-b4b607e4-e95d-4293-b3ab-179c95b963f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36375
77590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3637577590
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1011035821
Short name T172
Test name
Test status
Simulation time 10727131687 ps
CPU time 53.13 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:15:02 PM PDT 24
Peak memory 207064 kb
Host smart-f08058a2-e1e0-4d3f-8955-b9bb9770284f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1011035821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1011035821
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1038446059
Short name T164
Test name
Test status
Simulation time 9099105507 ps
CPU time 57.03 seconds
Started Jul 14 07:14:05 PM PDT 24
Finished Jul 14 07:15:22 PM PDT 24
Peak memory 207152 kb
Host smart-ccdbd688-8d3b-4e5c-a85e-72d0cf7e53df
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1038446059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1038446059
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1426981632
Short name T1443
Test name
Test status
Simulation time 13472195643 ps
CPU time 95.8 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:15:46 PM PDT 24
Peak memory 207116 kb
Host smart-586a2d57-467d-4f9d-b7b1-ee98675de585
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1426981632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1426981632
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2391439516
Short name T2561
Test name
Test status
Simulation time 212132229 ps
CPU time 0.91 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:14:17 PM PDT 24
Peak memory 206824 kb
Host smart-2cbbaee9-1988-48ba-b18d-e3113ee29232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23914
39516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2391439516
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2874807521
Short name T2435
Test name
Test status
Simulation time 157870636 ps
CPU time 0.84 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:14:17 PM PDT 24
Peak memory 206884 kb
Host smart-fdad1916-005b-4d65-8e9e-d9445ca32f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28748
07521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2874807521
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.76050982
Short name T1996
Test name
Test status
Simulation time 181107690 ps
CPU time 0.83 seconds
Started Jul 14 07:14:01 PM PDT 24
Finished Jul 14 07:14:12 PM PDT 24
Peak memory 206912 kb
Host smart-1d115db5-e58e-4449-bee5-5a2a30e939b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76050
982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.76050982
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.431399106
Short name T1098
Test name
Test status
Simulation time 156648897 ps
CPU time 0.81 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:17 PM PDT 24
Peak memory 206836 kb
Host smart-48101e49-0d5a-4d53-88e5-d1256e826583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43139
9106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.431399106
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.265503412
Short name T1854
Test name
Test status
Simulation time 160044790 ps
CPU time 0.76 seconds
Started Jul 14 07:14:04 PM PDT 24
Finished Jul 14 07:14:23 PM PDT 24
Peak memory 206872 kb
Host smart-485762f2-8511-49f5-b4c5-7d215d1ba3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26550
3412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.265503412
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2831006012
Short name T828
Test name
Test status
Simulation time 194048512 ps
CPU time 0.91 seconds
Started Jul 14 07:14:05 PM PDT 24
Finished Jul 14 07:14:26 PM PDT 24
Peak memory 206832 kb
Host smart-fba0e43e-9f1d-48a8-b3e0-9773a10d33ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28310
06012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2831006012
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.722876165
Short name T1750
Test name
Test status
Simulation time 3324055160 ps
CPU time 91.2 seconds
Started Jul 14 07:14:02 PM PDT 24
Finished Jul 14 07:15:44 PM PDT 24
Peak memory 207088 kb
Host smart-b1b59f99-5ae5-4108-82eb-1b29683f44b6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=722876165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.722876165
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2644585265
Short name T1345
Test name
Test status
Simulation time 226756009 ps
CPU time 0.84 seconds
Started Jul 14 07:14:00 PM PDT 24
Finished Jul 14 07:14:10 PM PDT 24
Peak memory 206876 kb
Host smart-59f63e0c-3de2-4252-8cbd-09fb983d67cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26445
85265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2644585265
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1079556122
Short name T2501
Test name
Test status
Simulation time 187102083 ps
CPU time 0.81 seconds
Started Jul 14 07:14:05 PM PDT 24
Finished Jul 14 07:14:26 PM PDT 24
Peak memory 206888 kb
Host smart-7e19afae-80c6-4fe6-9c93-54ebcb73d221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10795
56122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1079556122
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.2234892124
Short name T620
Test name
Test status
Simulation time 1126566891 ps
CPU time 2.24 seconds
Started Jul 14 07:14:03 PM PDT 24
Finished Jul 14 07:14:21 PM PDT 24
Peak memory 207056 kb
Host smart-8dee64b2-b894-4d8f-a712-9c0d6a5b305d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22348
92124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.2234892124
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.836517294
Short name T1795
Test name
Test status
Simulation time 7801806601 ps
CPU time 75.87 seconds
Started Jul 14 07:14:16 PM PDT 24
Finished Jul 14 07:17:34 PM PDT 24
Peak memory 207096 kb
Host smart-ac2db6b3-f7c6-4023-98c9-5791381ec446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83651
7294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.836517294
Directory /workspace/9.usbdev_streaming_out/latest
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