Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	166972	1		T1	2		T2	2		T3	4
all_values[1]	166972	1		T1	2		T2	2		T3	4
all_values[2]	166972	1		T1	2		T2	2		T3	4
all_values[3]	166972	1		T1	2		T2	2		T3	4
all_values[4]	166972	1		T1	2		T2	2		T3	4
all_values[5]	166972	1		T1	2		T2	2		T3	4
all_values[6]	166972	1		T1	2		T2	2		T3	4
all_values[7]	166972	1		T1	2		T2	2		T3	4
all_values[8]	166972	1		T1	2		T2	2		T3	4
all_values[9]	166972	1		T1	2		T2	2		T3	4
all_values[10]	166972	1		T1	2		T2	2		T3	4
all_values[11]	166972	1		T1	2		T2	2		T3	4
all_values[12]	166972	1		T1	2		T2	2		T3	4
all_values[13]	166972	1		T1	2		T2	2		T3	4
all_values[14]	166972	1		T1	2		T2	2		T3	4
all_values[15]	166972	1		T1	2		T2	2		T3	4
all_values[16]	166972	1		T1	2		T2	2		T3	4
all_values[17]	166972	1		T1	2		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2998606	1		T1	36		T2	36		T3	72
auto[1]	6890	1		T35	2		T27	4		T28	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3000568	1		T1	36		T2	36		T3	72
auto[1]	4928	1		T189	64		T190	119		T191	123

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	165997	1		T1	2		T2	2		T3	4
all_values[0]	auto[0]	auto[1]	148	1		T189	3		T190	3		T191	2
all_values[0]	auto[1]	auto[0]	687	1		T27	4		T28	3		T22	3
all_values[0]	auto[1]	auto[1]	140	1		T190	5		T191	5		T194	4
all_values[1]	auto[0]	auto[0]	165166	1		T1	2		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	164	1		T189	3		T190	4		T191	5
all_values[1]	auto[1]	auto[0]	1526	1		T34	3		T6	2		T7	2
all_values[1]	auto[1]	auto[1]	116	1		T189	1		T190	3		T191	2
all_values[2]	auto[0]	auto[0]	166577	1		T1	2		T2	2		T3	4
all_values[2]	auto[0]	auto[1]	130	1		T189	3		T190	6		T191	2
all_values[2]	auto[1]	auto[0]	134	1		T35	2		T18	2		T41	2
all_values[2]	auto[1]	auto[1]	131	1		T189	2		T190	1		T191	4
all_values[3]	auto[0]	auto[0]	165188	1		T1	2		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	136	1		T189	3		T190	8		T191	3
all_values[3]	auto[1]	auto[0]	1517	1		T60	1485		T189	1		T191	3
all_values[3]	auto[1]	auto[1]	131	1		T194	3		T192	3		T193	3
all_values[4]	auto[0]	auto[0]	166671	1		T1	2		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	135	1		T190	1		T191	5		T194	2
all_values[4]	auto[1]	auto[0]	29	1		T61	2		T191	1		T194	1
all_values[4]	auto[1]	auto[1]	137	1		T189	5		T190	7		T191	2
all_values[5]	auto[0]	auto[0]	166669	1		T1	2		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	144	1		T190	1		T191	2		T194	5
all_values[5]	auto[1]	auto[0]	26	1		T189	4		T192	1		T264	1
all_values[5]	auto[1]	auto[1]	133	1		T190	7		T191	6		T194	2
all_values[6]	auto[0]	auto[0]	166661	1		T1	2		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	116	1		T194	5		T265	3		T193	4
all_values[6]	auto[1]	auto[0]	34	1		T189	2		T190	3		T194	1
all_values[6]	auto[1]	auto[1]	161	1		T189	3		T190	5		T191	8
all_values[7]	auto[0]	auto[0]	166673	1		T1	2		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	137	1		T190	2		T191	3		T194	6
all_values[7]	auto[1]	auto[0]	39	1		T43	2		T44	2		T45	2
all_values[7]	auto[1]	auto[1]	123	1		T190	6		T191	2		T194	2
all_values[8]	auto[0]	auto[0]	166651	1		T1	2		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	140	1		T189	1		T190	2		T191	3
all_values[8]	auto[1]	auto[0]	38	1		T49	11		T190	1		T194	2
all_values[8]	auto[1]	auto[1]	143	1		T189	4		T190	4		T191	5
all_values[9]	auto[0]	auto[0]	166651	1		T1	2		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	129	1		T189	4		T190	1		T191	5
all_values[9]	auto[1]	auto[0]	58	1		T57	5		T58	5		T59	5
all_values[9]	auto[1]	auto[1]	134	1		T190	5		T191	2		T194	6
all_values[10]	auto[0]	auto[0]	166669	1		T1	2		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	125	1		T190	6		T191	5		T265	1
all_values[10]	auto[1]	auto[0]	34	1		T189	1		T190	1		T194	1
all_values[10]	auto[1]	auto[1]	144	1		T189	4		T190	1		T191	3
all_values[11]	auto[0]	auto[0]	166566	1		T1	2		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	120	1		T190	3		T191	4		T265	4
all_values[11]	auto[1]	auto[0]	131	1		T23	2		T65	2		T66	2
all_values[11]	auto[1]	auto[1]	155	1		T190	3		T191	4		T265	1
all_values[12]	auto[0]	auto[0]	166646	1		T1	2		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	115	1		T189	1		T190	5		T191	6
all_values[12]	auto[1]	auto[0]	46	1		T68	3		T69	3		T70	3
all_values[12]	auto[1]	auto[1]	165	1		T189	4		T190	2		T191	2
all_values[13]	auto[0]	auto[0]	166676	1		T1	2		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	148	1		T190	3		T191	6		T194	2
all_values[13]	auto[1]	auto[0]	34	1		T189	1		T190	1		T191	1
all_values[13]	auto[1]	auto[1]	114	1		T189	4		T194	5		T265	1
all_values[14]	auto[0]	auto[0]	166672	1		T1	2		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	149	1		T189	3		T190	3		T191	2
all_values[14]	auto[1]	auto[0]	24	1		T189	1		T190	3		T194	1
all_values[14]	auto[1]	auto[1]	127	1		T189	1		T190	1		T191	6
all_values[15]	auto[0]	auto[0]	166679	1		T1	2		T2	2		T3	4
all_values[15]	auto[0]	auto[1]	149	1		T189	2		T190	5		T191	4
all_values[15]	auto[1]	auto[0]	23	1		T266	1		T263	1		T267	1
all_values[15]	auto[1]	auto[1]	121	1		T189	3		T190	3		T191	2
all_values[16]	auto[0]	auto[0]	166636	1		T1	2		T2	2		T3	4
all_values[16]	auto[0]	auto[1]	165	1		T189	2		T190	2		T191	5
all_values[16]	auto[1]	auto[0]	36	1		T62	8		T63	8		T64	8
all_values[16]	auto[1]	auto[1]	135	1		T189	3		T190	6		T191	2
all_values[17]	auto[0]	auto[0]	166667	1		T1	2		T2	2		T3	4
all_values[17]	auto[0]	auto[1]	141	1		T189	1		T190	4		T191	1
all_values[17]	auto[1]	auto[0]	37	1		T50	2		T51	2		T190	2
all_values[17]	auto[1]	auto[1]	127	1		T189	4		T190	1		T191	5