Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	166972	1		T1	2		T2	2		T3	4
all_pins[1]	166972	1		T1	2		T2	2		T3	4
all_pins[2]	166972	1		T1	2		T2	2		T3	4
all_pins[3]	166972	1		T1	2		T2	2		T3	4
all_pins[4]	166972	1		T1	2		T2	2		T3	4
all_pins[5]	166972	1		T1	2		T2	2		T3	4
all_pins[6]	166972	1		T1	2		T2	2		T3	4
all_pins[7]	166972	1		T1	2		T2	2		T3	4
all_pins[8]	166972	1		T1	2		T2	2		T3	4
all_pins[9]	166972	1		T1	2		T2	2		T3	4
all_pins[10]	166972	1		T1	2		T2	2		T3	4
all_pins[11]	166972	1		T1	2		T2	2		T3	4
all_pins[12]	166972	1		T1	2		T2	2		T3	4
all_pins[13]	166972	1		T1	2		T2	2		T3	4
all_pins[14]	166972	1		T1	2		T2	2		T3	4
all_pins[15]	166972	1		T1	2		T2	2		T3	4
all_pins[16]	166972	1		T1	2		T2	2		T3	4
all_pins[17]	166972	1		T1	2		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3003167	1		T1	36		T2	36		T3	72
values[0x1]	2329	1		T35	1		T27	1		T34	1
transitions[0x0=>0x1]	1989	1		T35	1		T27	1		T34	1
transitions[0x1=>0x0]	2006	1		T35	1		T27	1		T34	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	166855	1		T1	2		T2	2		T3	4
all_pins[0]	values[0x1]	117	1		T27	1		T268	1		T269	1
all_pins[0]	transitions[0x0=>0x1]	100	1		T27	1		T268	1		T269	1
all_pins[0]	transitions[0x1=>0x0]	994	1		T34	1		T6	1		T7	1
all_pins[1]	values[0x0]	165961	1		T1	2		T2	2		T3	4
all_pins[1]	values[0x1]	1011	1		T34	1		T6	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	995	1		T34	1		T6	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	106	1		T35	1		T18	1		T41	1
all_pins[2]	values[0x0]	166850	1		T1	2		T2	2		T3	4
all_pins[2]	values[0x1]	122	1		T35	1		T18	1		T41	1
all_pins[2]	transitions[0x0=>0x1]	98	1		T35	1		T18	1		T41	1
all_pins[2]	transitions[0x1=>0x0]	50	1		T60	1		T266	3		T264	3
all_pins[3]	values[0x0]	166898	1		T1	2		T2	2		T3	4
all_pins[3]	values[0x1]	74	1		T60	1		T192	2		T266	3
all_pins[3]	transitions[0x0=>0x1]	61	1		T60	1		T266	3		T264	3
all_pins[3]	transitions[0x1=>0x0]	42	1		T61	1		T190	4		T191	2
all_pins[4]	values[0x0]	166917	1		T1	2		T2	2		T3	4
all_pins[4]	values[0x1]	55	1		T61	1		T190	4		T191	2
all_pins[4]	transitions[0x0=>0x1]	38	1		T61	1		T190	1		T191	2
all_pins[4]	transitions[0x1=>0x0]	50	1		T190	2		T191	2		T194	2
all_pins[5]	values[0x0]	166905	1		T1	2		T2	2		T3	4
all_pins[5]	values[0x1]	67	1		T190	5		T191	2		T194	2
all_pins[5]	transitions[0x0=>0x1]	44	1		T190	2		T191	1		T194	2
all_pins[5]	transitions[0x1=>0x0]	57	1		T189	2		T190	1		T191	2
all_pins[6]	values[0x0]	166892	1		T1	2		T2	2		T3	4
all_pins[6]	values[0x1]	80	1		T189	2		T190	4		T191	3
all_pins[6]	transitions[0x0=>0x1]	63	1		T189	2		T190	2		T191	1
all_pins[6]	transitions[0x1=>0x0]	46	1		T43	1		T44	1		T45	1
all_pins[7]	values[0x0]	166909	1		T1	2		T2	2		T3	4
all_pins[7]	values[0x1]	63	1		T43	1		T44	1		T45	1
all_pins[7]	transitions[0x0=>0x1]	50	1		T43	1		T44	1		T45	1
all_pins[7]	transitions[0x1=>0x0]	35	1		T49	1		T189	1		T191	3
all_pins[8]	values[0x0]	166924	1		T1	2		T2	2		T3	4
all_pins[8]	values[0x1]	48	1		T49	1		T189	1		T190	1
all_pins[8]	transitions[0x0=>0x1]	37	1		T49	1		T189	1		T190	1
all_pins[8]	transitions[0x1=>0x0]	67	1		T57	2		T58	2		T59	2
all_pins[9]	values[0x0]	166894	1		T1	2		T2	2		T3	4
all_pins[9]	values[0x1]	78	1		T57	2		T58	2		T59	2
all_pins[9]	transitions[0x0=>0x1]	55	1		T57	2		T58	2		T59	2
all_pins[9]	transitions[0x1=>0x0]	58	1		T190	1		T194	3		T265	2
all_pins[10]	values[0x0]	166891	1		T1	2		T2	2		T3	4
all_pins[10]	values[0x1]	81	1		T190	1		T194	3		T265	2
all_pins[10]	transitions[0x0=>0x1]	57	1		T190	1		T194	3		T265	2
all_pins[10]	transitions[0x1=>0x0]	104	1		T23	1		T65	1		T66	1
all_pins[11]	values[0x0]	166844	1		T1	2		T2	2		T3	4
all_pins[11]	values[0x1]	128	1		T23	1		T65	1		T66	1
all_pins[11]	transitions[0x0=>0x1]	94	1		T23	1		T65	1		T66	1
all_pins[11]	transitions[0x1=>0x0]	46	1		T68	1		T69	1		T70	1
all_pins[12]	values[0x0]	166892	1		T1	2		T2	2		T3	4
all_pins[12]	values[0x1]	80	1		T68	1		T69	1		T70	1
all_pins[12]	transitions[0x0=>0x1]	70	1		T68	1		T69	1		T70	1
all_pins[12]	transitions[0x1=>0x0]	31	1		T189	1		T194	1		T193	4
all_pins[13]	values[0x0]	166931	1		T1	2		T2	2		T3	4
all_pins[13]	values[0x1]	41	1		T189	1		T194	1		T192	2
all_pins[13]	transitions[0x0=>0x1]	27	1		T189	1		T192	2		T193	3
all_pins[13]	transitions[0x1=>0x0]	52	1		T190	1		T191	4		T265	2
all_pins[14]	values[0x0]	166906	1		T1	2		T2	2		T3	4
all_pins[14]	values[0x1]	66	1		T190	1		T191	4		T194	1
all_pins[14]	transitions[0x0=>0x1]	46	1		T190	1		T191	3		T193	4
all_pins[14]	transitions[0x1=>0x0]	51	1		T189	2		T191	1		T194	3
all_pins[15]	values[0x0]	166901	1		T1	2		T2	2		T3	4
all_pins[15]	values[0x1]	71	1		T189	2		T191	2		T194	4
all_pins[15]	transitions[0x0=>0x1]	54	1		T191	2		T194	4		T265	2
all_pins[15]	transitions[0x1=>0x0]	66	1		T62	4		T63	4		T64	4
all_pins[16]	values[0x0]	166889	1		T1	2		T2	2		T3	4
all_pins[16]	values[0x1]	83	1		T62	4		T63	4		T64	4
all_pins[16]	transitions[0x0=>0x1]	65	1		T62	4		T63	4		T64	4
all_pins[16]	transitions[0x1=>0x0]	46	1		T50	1		T51	1		T189	1
all_pins[17]	values[0x0]	166908	1		T1	2		T2	2		T3	4
all_pins[17]	values[0x1]	64	1		T50	1		T51	1		T189	2
all_pins[17]	transitions[0x0=>0x1]	35	1		T50	1		T51	1		T189	2
all_pins[17]	transitions[0x1=>0x0]	105	1		T27	1		T268	1		T269	1