Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T189	4		T190	7		T191	7
all_values[1]	275	1		T189	4		T190	7		T191	7
all_values[2]	275	1		T189	4		T190	7		T191	7
all_values[3]	275	1		T189	4		T190	7		T191	7
all_values[4]	275	1		T189	4		T190	7		T191	7
all_values[5]	275	1		T189	4		T190	7		T191	7
all_values[6]	275	1		T189	4		T190	7		T191	7
all_values[7]	275	1		T189	4		T190	7		T191	7
all_values[8]	275	1		T189	4		T190	7		T191	7
all_values[9]	275	1		T189	4		T190	7		T191	7
all_values[10]	275	1		T189	4		T190	7		T191	7
all_values[11]	275	1		T189	4		T190	7		T191	7
all_values[12]	275	1		T189	4		T190	7		T191	7
all_values[13]	275	1		T189	4		T190	7		T191	7
all_values[14]	275	1		T189	4		T190	7		T191	7
all_values[15]	275	1		T189	4		T190	7		T191	7
all_values[16]	275	1		T189	4		T190	7		T191	7
all_values[17]	275	1		T189	4		T190	7		T191	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2623	1		T189	38		T190	65		T191	60
auto[1]	2327	1		T189	34		T190	61		T191	66

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	869	1		T189	23		T190	25		T191	21
auto[1]	4081	1		T189	49		T190	101		T191	105

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2885	1		T189	49		T190	80		T191	69
auto[1]	2065	1		T189	23		T190	46		T191	57

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	20	1		T189	1		T194	2		T265	1
all_values[0]	auto[0]	auto[0]	auto[1]	59	1		T189	1		T190	3		T194	2
all_values[0]	auto[0]	auto[1]	auto[0]	16	1		T189	1		T191	1		T192	2
all_values[0]	auto[0]	auto[1]	auto[1]	57	1		T190	3		T191	1		T194	1
all_values[0]	auto[1]	auto[0]	auto[1]	67	1		T189	1		T190	1		T191	1
all_values[0]	auto[1]	auto[1]	auto[1]	56	1		T191	4		T266	2		T264	2
all_values[1]	auto[0]	auto[0]	auto[0]	22	1		T189	1		T190	1		T264	1
all_values[1]	auto[0]	auto[0]	auto[1]	67	1		T189	2		T190	1		T191	1
all_values[1]	auto[0]	auto[1]	auto[0]	19	1		T191	1		T194	1		T267	1
all_values[1]	auto[0]	auto[1]	auto[1]	45	1		T190	1		T194	1		T193	1
all_values[1]	auto[1]	auto[0]	auto[1]	69	1		T190	1		T191	2		T265	1
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T189	1		T190	3		T191	3
all_values[2]	auto[0]	auto[0]	auto[0]	35	1		T190	1		T191	2		T194	4
all_values[2]	auto[0]	auto[0]	auto[1]	54	1		T189	1		T190	4		T194	2
all_values[2]	auto[0]	auto[1]	auto[0]	28	1		T266	3		T264	2		T270	2
all_values[2]	auto[0]	auto[1]	auto[1]	48	1		T189	1		T190	1		T191	1
all_values[2]	auto[1]	auto[0]	auto[1]	62	1		T189	2		T190	1		T191	2
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T191	2		T265	2		T192	1
all_values[3]	auto[0]	auto[0]	auto[0]	33	1		T189	2		T191	1		T265	1
all_values[3]	auto[0]	auto[0]	auto[1]	60	1		T189	1		T190	4		T191	1
all_values[3]	auto[0]	auto[1]	auto[0]	23	1		T191	4		T194	2		T265	3
all_values[3]	auto[0]	auto[1]	auto[1]	49	1		T194	1		T192	1		T193	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T189	1		T190	3		T191	1
all_values[3]	auto[1]	auto[1]	auto[1]	50	1		T192	1		T193	1		T266	3
all_values[4]	auto[0]	auto[0]	auto[0]	29	1		T265	1		T192	1		T193	2
all_values[4]	auto[0]	auto[0]	auto[1]	49	1		T191	2		T193	2		T264	2
all_values[4]	auto[0]	auto[1]	auto[0]	19	1		T191	1		T194	1		T265	3
all_values[4]	auto[0]	auto[1]	auto[1]	64	1		T189	3		T190	2		T191	1
all_values[4]	auto[1]	auto[0]	auto[1]	73	1		T189	1		T190	1		T191	2
all_values[4]	auto[1]	auto[1]	auto[1]	41	1		T190	4		T191	1		T194	2
all_values[5]	auto[0]	auto[0]	auto[0]	29	1		T189	1		T194	1		T192	1
all_values[5]	auto[0]	auto[0]	auto[1]	58	1		T190	1		T194	4		T265	3
all_values[5]	auto[0]	auto[1]	auto[0]	16	1		T189	3		T263	1		T267	1
all_values[5]	auto[0]	auto[1]	auto[1]	55	1		T190	2		T191	3		T192	1
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T191	2		T194	2		T265	1
all_values[5]	auto[1]	auto[1]	auto[1]	56	1		T190	4		T191	2		T192	1
all_values[6]	auto[0]	auto[0]	auto[0]	19	1		T189	1		T194	2		T265	1
all_values[6]	auto[0]	auto[0]	auto[1]	47	1		T194	1		T265	1		T193	3
all_values[6]	auto[0]	auto[1]	auto[0]	26	1		T189	1		T190	3		T192	2
all_values[6]	auto[0]	auto[1]	auto[1]	58	1		T189	1		T190	2		T191	3
all_values[6]	auto[1]	auto[0]	auto[1]	63	1		T194	2		T193	2		T266	2
all_values[6]	auto[1]	auto[1]	auto[1]	62	1		T189	1		T190	2		T191	4
all_values[7]	auto[0]	auto[0]	auto[0]	41	1		T189	4		T191	3		T265	3
all_values[7]	auto[0]	auto[0]	auto[1]	54	1		T191	2		T194	2		T192	1
all_values[7]	auto[0]	auto[1]	auto[0]	20	1		T265	1		T264	1		T267	1
all_values[7]	auto[0]	auto[1]	auto[1]	47	1		T190	3		T194	1		T193	1
all_values[7]	auto[1]	auto[0]	auto[1]	53	1		T190	2		T194	1		T192	1
all_values[7]	auto[1]	auto[1]	auto[1]	60	1		T190	2		T191	2		T194	3
all_values[8]	auto[0]	auto[0]	auto[0]	22	1		T190	1		T194	1		T266	2
all_values[8]	auto[0]	auto[0]	auto[1]	62	1		T190	2		T191	1		T194	3
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T190	1		T194	2		T265	2
all_values[8]	auto[0]	auto[1]	auto[1]	57	1		T189	2		T190	1		T191	1
all_values[8]	auto[1]	auto[0]	auto[1]	59	1		T189	1		T190	1		T191	1
all_values[8]	auto[1]	auto[1]	auto[1]	56	1		T189	1		T190	1		T191	4
all_values[9]	auto[0]	auto[0]	auto[0]	32	1		T189	1		T265	1		T264	1
all_values[9]	auto[0]	auto[0]	auto[1]	52	1		T189	2		T190	1		T191	2
all_values[9]	auto[0]	auto[1]	auto[0]	25	1		T190	2		T191	1		T267	4
all_values[9]	auto[0]	auto[1]	auto[1]	57	1		T190	2		T191	1		T194	3
all_values[9]	auto[1]	auto[0]	auto[1]	61	1		T190	1		T191	1		T194	3
all_values[9]	auto[1]	auto[1]	auto[1]	48	1		T189	1		T190	1		T191	2
all_values[10]	auto[0]	auto[0]	auto[0]	24	1		T189	1		T194	2		T266	1
all_values[10]	auto[0]	auto[0]	auto[1]	50	1		T190	2		T191	2		T265	1
all_values[10]	auto[0]	auto[1]	auto[0]	28	1		T190	1		T265	1		T264	2
all_values[10]	auto[0]	auto[1]	auto[1]	65	1		T189	2		T190	1		T191	2
all_values[10]	auto[1]	auto[0]	auto[1]	58	1		T190	3		T191	3		T265	1
all_values[10]	auto[1]	auto[1]	auto[1]	50	1		T189	1		T194	3		T264	3
all_values[11]	auto[0]	auto[0]	auto[0]	27	1		T189	1		T190	1		T194	5
all_values[11]	auto[0]	auto[0]	auto[1]	48	1		T190	2		T191	2		T265	1
all_values[11]	auto[0]	auto[1]	auto[0]	21	1		T189	3		T190	1		T194	2
all_values[11]	auto[0]	auto[1]	auto[1]	66	1		T190	1		T191	3		T193	3
all_values[11]	auto[1]	auto[0]	auto[1]	48	1		T190	2		T191	2		T265	1
all_values[11]	auto[1]	auto[1]	auto[1]	65	1		T265	2		T192	1		T266	2
all_values[12]	auto[0]	auto[0]	auto[0]	18	1		T190	1		T192	1		T266	1
all_values[12]	auto[0]	auto[0]	auto[1]	52	1		T189	1		T190	2		T191	2
all_values[12]	auto[0]	auto[1]	auto[0]	23	1		T265	1		T192	1		T267	1
all_values[12]	auto[0]	auto[1]	auto[1]	68	1		T189	2		T190	1		T191	2
all_values[12]	auto[1]	auto[0]	auto[1]	56	1		T189	1		T190	2		T191	3
all_values[12]	auto[1]	auto[1]	auto[1]	58	1		T190	1		T194	1		T265	1
all_values[13]	auto[0]	auto[0]	auto[0]	37	1		T189	1		T190	4		T191	2
all_values[13]	auto[0]	auto[0]	auto[1]	57	1		T190	1		T191	1		T265	1
all_values[13]	auto[0]	auto[1]	auto[0]	22	1		T190	1		T194	1		T264	4
all_values[13]	auto[0]	auto[1]	auto[1]	56	1		T189	2		T194	4		T265	1
all_values[13]	auto[1]	auto[0]	auto[1]	67	1		T190	1		T191	3		T265	1
all_values[13]	auto[1]	auto[1]	auto[1]	36	1		T189	1		T191	1		T194	2
all_values[14]	auto[0]	auto[0]	auto[0]	27	1		T189	1		T190	1		T270	1
all_values[14]	auto[0]	auto[0]	auto[1]	54	1		T189	1		T190	1		T191	1
all_values[14]	auto[0]	auto[1]	auto[0]	20	1		T190	3		T194	1		T265	1
all_values[14]	auto[0]	auto[1]	auto[1]	51	1		T191	3		T265	1		T193	3
all_values[14]	auto[1]	auto[0]	auto[1]	64	1		T189	1		T190	1		T191	1
all_values[14]	auto[1]	auto[1]	auto[1]	59	1		T189	1		T190	1		T191	2
all_values[15]	auto[0]	auto[0]	auto[0]	37	1		T191	2		T266	3		T264	1
all_values[15]	auto[0]	auto[0]	auto[1]	66	1		T190	4		T191	2		T265	1
all_values[15]	auto[0]	auto[1]	auto[0]	17	1		T266	1		T263	1		T267	1
all_values[15]	auto[0]	auto[1]	auto[1]	49	1		T189	1		T190	1		T191	1
all_values[15]	auto[1]	auto[0]	auto[1]	56	1		T189	2		T190	2		T191	2
all_values[15]	auto[1]	auto[1]	auto[1]	50	1		T189	1		T194	4		T193	1
all_values[16]	auto[0]	auto[0]	auto[0]	15	1		T193	1		T270	1		T271	1
all_values[16]	auto[0]	auto[0]	auto[1]	71	1		T189	1		T190	1		T191	2
all_values[16]	auto[0]	auto[1]	auto[0]	9	1		T191	1		T266	1		T272	1
all_values[16]	auto[0]	auto[1]	auto[1]	60	1		T189	1		T190	3		T191	2
all_values[16]	auto[1]	auto[0]	auto[1]	72	1		T189	1		T190	1		T191	1
all_values[16]	auto[1]	auto[1]	auto[1]	48	1		T189	1		T190	2		T191	1
all_values[17]	auto[0]	auto[0]	auto[0]	28	1		T190	1		T265	4		T193	2
all_values[17]	auto[0]	auto[0]	auto[1]	56	1		T190	2		T191	1		T194	2
all_values[17]	auto[0]	auto[1]	auto[0]	23	1		T190	2		T191	2		T194	1
all_values[17]	auto[0]	auto[1]	auto[1]	48	1		T189	1		T191	2		T194	1
all_values[17]	auto[1]	auto[0]	auto[1]	63	1		T189	2		T191	1		T194	2
all_values[17]	auto[1]	auto[1]	auto[1]	57	1		T189	1		T190	2		T191	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal