Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.36 97.82 93.83 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2856
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T245 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1764373941 Jul 15 06:12:07 PM PDT 24 Jul 15 06:12:08 PM PDT 24 76803861 ps
T2767 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1069607781 Jul 15 06:13:01 PM PDT 24 Jul 15 06:13:02 PM PDT 24 61490826 ps
T2768 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3282112728 Jul 15 06:12:44 PM PDT 24 Jul 15 06:12:45 PM PDT 24 107255422 ps
T2769 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2168963354 Jul 15 06:13:02 PM PDT 24 Jul 15 06:13:03 PM PDT 24 54791525 ps
T2770 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1786369738 Jul 15 06:12:34 PM PDT 24 Jul 15 06:12:36 PM PDT 24 93429613 ps
T275 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1178643171 Jul 15 06:12:41 PM PDT 24 Jul 15 06:12:45 PM PDT 24 584928095 ps
T2771 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.226320451 Jul 15 06:12:41 PM PDT 24 Jul 15 06:12:42 PM PDT 24 46550675 ps
T262 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3289495484 Jul 15 06:12:50 PM PDT 24 Jul 15 06:12:52 PM PDT 24 201601490 ps
T250 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1874344135 Jul 15 06:12:45 PM PDT 24 Jul 15 06:12:47 PM PDT 24 172203947 ps
T246 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3386727695 Jul 15 06:11:49 PM PDT 24 Jul 15 06:11:50 PM PDT 24 109311339 ps
T2772 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2587336102 Jul 15 06:12:34 PM PDT 24 Jul 15 06:12:35 PM PDT 24 211033552 ps
T2773 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3099221412 Jul 15 06:12:52 PM PDT 24 Jul 15 06:12:55 PM PDT 24 112883844 ps
T2774 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4134038608 Jul 15 06:13:03 PM PDT 24 Jul 15 06:13:06 PM PDT 24 308903045 ps
T273 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1474824689 Jul 15 06:12:22 PM PDT 24 Jul 15 06:12:25 PM PDT 24 414893599 ps
T2775 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1341995067 Jul 15 06:12:28 PM PDT 24 Jul 15 06:12:29 PM PDT 24 159489963 ps
T2776 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1980462280 Jul 15 06:12:25 PM PDT 24 Jul 15 06:12:29 PM PDT 24 120476898 ps
T2777 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1277638120 Jul 15 06:13:13 PM PDT 24 Jul 15 06:13:14 PM PDT 24 43840975 ps
T2778 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2528853380 Jul 15 06:13:03 PM PDT 24 Jul 15 06:13:04 PM PDT 24 194872218 ps
T2779 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1844110070 Jul 15 06:12:42 PM PDT 24 Jul 15 06:12:43 PM PDT 24 35103555 ps
T2780 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2883153435 Jul 15 06:12:34 PM PDT 24 Jul 15 06:12:38 PM PDT 24 498006229 ps
T2781 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2794988543 Jul 15 06:11:57 PM PDT 24 Jul 15 06:11:58 PM PDT 24 49850873 ps
T274 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1292783831 Jul 15 06:12:05 PM PDT 24 Jul 15 06:12:08 PM PDT 24 490621779 ps
T2782 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.627936644 Jul 15 06:12:58 PM PDT 24 Jul 15 06:12:59 PM PDT 24 29745812 ps
T2783 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2456555056 Jul 15 06:12:27 PM PDT 24 Jul 15 06:12:28 PM PDT 24 56424055 ps
T2784 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1100693184 Jul 15 06:12:05 PM PDT 24 Jul 15 06:12:07 PM PDT 24 98777008 ps
T2785 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2544714169 Jul 15 06:11:49 PM PDT 24 Jul 15 06:11:51 PM PDT 24 168760834 ps
T2786 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3790494700 Jul 15 06:12:43 PM PDT 24 Jul 15 06:12:46 PM PDT 24 150215287 ps
T2787 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3688964833 Jul 15 06:12:14 PM PDT 24 Jul 15 06:12:16 PM PDT 24 128296060 ps
T2788 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.413517432 Jul 15 06:12:20 PM PDT 24 Jul 15 06:12:21 PM PDT 24 46326594 ps
T2789 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3160562481 Jul 15 06:13:17 PM PDT 24 Jul 15 06:13:18 PM PDT 24 88218879 ps
T247 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3555460463 Jul 15 06:11:51 PM PDT 24 Jul 15 06:11:53 PM PDT 24 216426245 ps
T2790 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3076041092 Jul 15 06:12:51 PM PDT 24 Jul 15 06:12:53 PM PDT 24 181963344 ps
T2791 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1997493647 Jul 15 06:13:00 PM PDT 24 Jul 15 06:13:01 PM PDT 24 40464076 ps
T2792 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1597329354 Jul 15 06:12:18 PM PDT 24 Jul 15 06:12:19 PM PDT 24 69650201 ps
T2793 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2622480165 Jul 15 06:12:27 PM PDT 24 Jul 15 06:12:28 PM PDT 24 37184317 ps
T2794 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1458452979 Jul 15 06:12:22 PM PDT 24 Jul 15 06:12:23 PM PDT 24 70692915 ps
T2795 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2807193773 Jul 15 06:12:33 PM PDT 24 Jul 15 06:12:34 PM PDT 24 34756241 ps
T2796 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.36655841 Jul 15 06:12:23 PM PDT 24 Jul 15 06:12:25 PM PDT 24 75108297 ps
T248 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4186663590 Jul 15 06:12:14 PM PDT 24 Jul 15 06:12:18 PM PDT 24 370959423 ps
T2797 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1847931140 Jul 15 06:13:00 PM PDT 24 Jul 15 06:13:03 PM PDT 24 179969955 ps
T2798 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3000677900 Jul 15 06:12:51 PM PDT 24 Jul 15 06:12:54 PM PDT 24 281120332 ps
T2799 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3685783744 Jul 15 06:11:51 PM PDT 24 Jul 15 06:11:52 PM PDT 24 104263273 ps
T249 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3643909656 Jul 15 06:12:07 PM PDT 24 Jul 15 06:12:11 PM PDT 24 169651698 ps
T2800 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1689512322 Jul 15 06:12:15 PM PDT 24 Jul 15 06:12:18 PM PDT 24 270207005 ps
T279 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3638351259 Jul 15 06:12:34 PM PDT 24 Jul 15 06:12:39 PM PDT 24 711741646 ps
T2801 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1386709595 Jul 15 06:12:50 PM PDT 24 Jul 15 06:12:51 PM PDT 24 43038116 ps
T2802 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3031225849 Jul 15 06:12:31 PM PDT 24 Jul 15 06:12:33 PM PDT 24 77633706 ps
T2803 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2455688928 Jul 15 06:13:14 PM PDT 24 Jul 15 06:13:15 PM PDT 24 41478581 ps
T2804 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2018617631 Jul 15 06:12:23 PM PDT 24 Jul 15 06:12:28 PM PDT 24 485412373 ps
T2805 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3868988256 Jul 15 06:12:26 PM PDT 24 Jul 15 06:12:28 PM PDT 24 65565714 ps
T280 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1188470719 Jul 15 06:12:28 PM PDT 24 Jul 15 06:12:32 PM PDT 24 691311427 ps
T2806 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3279942597 Jul 15 06:12:05 PM PDT 24 Jul 15 06:12:09 PM PDT 24 295610083 ps
T2807 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1836937073 Jul 15 06:12:44 PM PDT 24 Jul 15 06:12:46 PM PDT 24 141741955 ps
T2808 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3670687831 Jul 15 06:12:26 PM PDT 24 Jul 15 06:12:27 PM PDT 24 45160642 ps
T2809 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1473012088 Jul 15 06:12:35 PM PDT 24 Jul 15 06:12:38 PM PDT 24 148779806 ps
T2810 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2303809426 Jul 15 06:12:34 PM PDT 24 Jul 15 06:12:36 PM PDT 24 87274390 ps
T2811 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1623219359 Jul 15 06:12:52 PM PDT 24 Jul 15 06:12:54 PM PDT 24 131827052 ps
T2812 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1672162967 Jul 15 06:12:20 PM PDT 24 Jul 15 06:12:23 PM PDT 24 150083736 ps
T2813 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2530804878 Jul 15 06:12:21 PM PDT 24 Jul 15 06:12:23 PM PDT 24 101686499 ps
T2814 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3019971248 Jul 15 06:13:14 PM PDT 24 Jul 15 06:13:16 PM PDT 24 52752322 ps
T281 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3248839258 Jul 15 06:12:42 PM PDT 24 Jul 15 06:12:47 PM PDT 24 719450896 ps
T2815 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1184439218 Jul 15 06:11:50 PM PDT 24 Jul 15 06:11:51 PM PDT 24 67520934 ps
T2816 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2993014516 Jul 15 06:13:14 PM PDT 24 Jul 15 06:13:15 PM PDT 24 85732402 ps
T2817 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3024471983 Jul 15 06:13:05 PM PDT 24 Jul 15 06:13:06 PM PDT 24 44184010 ps
T2818 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1573146525 Jul 15 06:12:59 PM PDT 24 Jul 15 06:13:02 PM PDT 24 176552470 ps
T2819 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.362301600 Jul 15 06:12:33 PM PDT 24 Jul 15 06:12:35 PM PDT 24 58181060 ps
T2820 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1690349232 Jul 15 06:13:14 PM PDT 24 Jul 15 06:13:15 PM PDT 24 85006478 ps
T2821 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2995900342 Jul 15 06:13:13 PM PDT 24 Jul 15 06:13:14 PM PDT 24 49862556 ps
T2822 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4019177714 Jul 15 06:12:12 PM PDT 24 Jul 15 06:12:13 PM PDT 24 56238703 ps
T2823 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2329387588 Jul 15 06:12:43 PM PDT 24 Jul 15 06:12:45 PM PDT 24 367942770 ps
T2824 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1804311420 Jul 15 06:12:04 PM PDT 24 Jul 15 06:12:09 PM PDT 24 307287829 ps
T277 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2203922589 Jul 15 06:12:21 PM PDT 24 Jul 15 06:12:27 PM PDT 24 833804315 ps
T2825 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3433339127 Jul 15 06:12:56 PM PDT 24 Jul 15 06:12:57 PM PDT 24 79893781 ps
T278 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.379042369 Jul 15 06:12:52 PM PDT 24 Jul 15 06:12:57 PM PDT 24 891261315 ps
T2826 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2625019266 Jul 15 06:12:50 PM PDT 24 Jul 15 06:12:51 PM PDT 24 40798832 ps
T2827 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3860161807 Jul 15 06:12:35 PM PDT 24 Jul 15 06:12:36 PM PDT 24 51529081 ps
T2828 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1633095143 Jul 15 06:12:27 PM PDT 24 Jul 15 06:12:30 PM PDT 24 97554140 ps
T2829 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3301473206 Jul 15 06:12:12 PM PDT 24 Jul 15 06:12:20 PM PDT 24 661985140 ps
T2830 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3231319614 Jul 15 06:12:43 PM PDT 24 Jul 15 06:12:45 PM PDT 24 129810320 ps
T2831 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.51004695 Jul 15 06:12:48 PM PDT 24 Jul 15 06:12:52 PM PDT 24 281847074 ps
T2832 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2495945085 Jul 15 06:12:28 PM PDT 24 Jul 15 06:12:29 PM PDT 24 76640501 ps
T2833 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.913648082 Jul 15 06:12:52 PM PDT 24 Jul 15 06:12:53 PM PDT 24 47570741 ps
T2834 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.217230681 Jul 15 06:12:13 PM PDT 24 Jul 15 06:12:15 PM PDT 24 195189957 ps
T2835 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.416814517 Jul 15 06:13:14 PM PDT 24 Jul 15 06:13:15 PM PDT 24 57469540 ps
T2836 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.126076410 Jul 15 06:13:00 PM PDT 24 Jul 15 06:13:01 PM PDT 24 77857127 ps
T2837 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2239717078 Jul 15 06:12:12 PM PDT 24 Jul 15 06:12:14 PM PDT 24 91549385 ps
T2838 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2223518604 Jul 15 06:12:34 PM PDT 24 Jul 15 06:12:37 PM PDT 24 169405292 ps
T2839 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1104670078 Jul 15 06:12:43 PM PDT 24 Jul 15 06:12:46 PM PDT 24 162018697 ps
T2840 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3474680252 Jul 15 06:13:15 PM PDT 24 Jul 15 06:13:16 PM PDT 24 47613747 ps
T2841 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.728827725 Jul 15 06:12:01 PM PDT 24 Jul 15 06:12:02 PM PDT 24 96587044 ps
T2842 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2980874392 Jul 15 06:12:07 PM PDT 24 Jul 15 06:12:08 PM PDT 24 41318587 ps
T2843 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.270558596 Jul 15 06:12:12 PM PDT 24 Jul 15 06:12:16 PM PDT 24 158950235 ps
T229 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3090424123 Jul 15 06:12:52 PM PDT 24 Jul 15 06:12:55 PM PDT 24 685063755 ps
T2844 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2698677473 Jul 15 06:12:43 PM PDT 24 Jul 15 06:12:47 PM PDT 24 177471781 ps
T2845 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1619267696 Jul 15 06:11:58 PM PDT 24 Jul 15 06:12:01 PM PDT 24 98309760 ps
T2846 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3111872495 Jul 15 06:12:26 PM PDT 24 Jul 15 06:12:29 PM PDT 24 524387666 ps
T2847 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3132113895 Jul 15 06:12:29 PM PDT 24 Jul 15 06:12:31 PM PDT 24 254153501 ps
T2848 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4190066416 Jul 15 06:13:13 PM PDT 24 Jul 15 06:13:14 PM PDT 24 46399888 ps
T2849 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1170408479 Jul 15 06:12:59 PM PDT 24 Jul 15 06:13:00 PM PDT 24 40037336 ps
T2850 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2582070200 Jul 15 06:12:13 PM PDT 24 Jul 15 06:12:17 PM PDT 24 157190845 ps
T2851 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4011074782 Jul 15 06:13:01 PM PDT 24 Jul 15 06:13:02 PM PDT 24 70762211 ps
T2852 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2638097285 Jul 15 06:11:57 PM PDT 24 Jul 15 06:11:59 PM PDT 24 95917181 ps
T2853 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2969844074 Jul 15 06:13:17 PM PDT 24 Jul 15 06:13:18 PM PDT 24 49130866 ps
T2854 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3196932978 Jul 15 06:12:43 PM PDT 24 Jul 15 06:12:45 PM PDT 24 181105126 ps
T2855 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2015797534 Jul 15 06:12:51 PM PDT 24 Jul 15 06:12:52 PM PDT 24 40091232 ps
T2856 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2604598818 Jul 15 06:12:41 PM PDT 24 Jul 15 06:12:47 PM PDT 24 1714180170 ps

Test location /workspace/coverage/default/26.usbdev_invalid_sync.980673007
Short name T30
Test name
Test status
Simulation time 6099779077 ps
CPU time 53.94 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:08:26 PM PDT 24
Peak memory 206400 kb
Host smart-02d70d78-712c-45dd-ab16-e5d19cf89577
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=980673007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.980673007
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3379142895
Short name T191
Test name
Test status
Simulation time 65079669 ps
CPU time 0.68 seconds
Started Jul 15 06:12:50 PM PDT 24
Finished Jul 15 06:12:52 PM PDT 24
Peak memory 206304 kb
Host smart-2cde946f-a8a3-4853-8d6b-ee2a16cb3b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3379142895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3379142895
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.4106910621
Short name T6
Test name
Test status
Simulation time 13303984252 ps
CPU time 13.82 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 207080 kb
Host smart-7b3522db-a679-4a42-80a7-38ead454441a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4106910621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.4106910621
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3697741389
Short name T74
Test name
Test status
Simulation time 171906851 ps
CPU time 0.81 seconds
Started Jul 15 07:04:11 PM PDT 24
Finished Jul 15 07:04:12 PM PDT 24
Peak memory 206824 kb
Host smart-3ea1a57f-9adc-4850-b857-fcb22de13e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36977
41389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3697741389
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.430438521
Short name T180
Test name
Test status
Simulation time 579712561 ps
CPU time 4.36 seconds
Started Jul 15 06:11:58 PM PDT 24
Finished Jul 15 06:12:03 PM PDT 24
Peak memory 206572 kb
Host smart-2bab0f0f-108b-47fd-970d-afa70f598c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=430438521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.430438521
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.337067724
Short name T5
Test name
Test status
Simulation time 7008978725 ps
CPU time 23.07 seconds
Started Jul 15 07:03:01 PM PDT 24
Finished Jul 15 07:03:25 PM PDT 24
Peak memory 207000 kb
Host smart-6b375b2b-83b3-43ee-848d-b63cc0a7b8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33706
7724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.337067724
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.112659493
Short name T267
Test name
Test status
Simulation time 64565264 ps
CPU time 0.71 seconds
Started Jul 15 06:13:03 PM PDT 24
Finished Jul 15 06:13:04 PM PDT 24
Peak memory 206248 kb
Host smart-6e91b49f-86fd-4420-8588-8b11e06b2618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=112659493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.112659493
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3311561505
Short name T53
Test name
Test status
Simulation time 344606685 ps
CPU time 1.18 seconds
Started Jul 15 07:07:56 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206768 kb
Host smart-fa309fc1-8d43-43d2-8f51-52e9fdbb84a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33115
61505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3311561505
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3119516904
Short name T41
Test name
Test status
Simulation time 145996679 ps
CPU time 0.77 seconds
Started Jul 15 07:04:55 PM PDT 24
Finished Jul 15 07:04:56 PM PDT 24
Peak memory 205896 kb
Host smart-ebb51e44-b980-4bc2-894c-c7fd4ac1bdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31195
16904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3119516904
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.2967125629
Short name T19
Test name
Test status
Simulation time 403400962 ps
CPU time 1.32 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:21 PM PDT 24
Peak memory 206792 kb
Host smart-0c4213eb-f716-4abd-b420-2174eb367511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29671
25629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2967125629
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1414834090
Short name T211
Test name
Test status
Simulation time 324567154 ps
CPU time 2.9 seconds
Started Jul 15 06:12:08 PM PDT 24
Finished Jul 15 06:12:11 PM PDT 24
Peak memory 206528 kb
Host smart-c4b491fb-271d-4e52-8f82-f6bb028675e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1414834090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1414834090
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1211904353
Short name T81
Test name
Test status
Simulation time 7633964159 ps
CPU time 18.26 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 207096 kb
Host smart-bf0782a2-6049-4cda-864e-ec129abcb205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12119
04353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1211904353
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3846063905
Short name T177
Test name
Test status
Simulation time 282379748 ps
CPU time 1.11 seconds
Started Jul 15 07:03:00 PM PDT 24
Finished Jul 15 07:03:02 PM PDT 24
Peak memory 224528 kb
Host smart-7d747913-d459-4e9b-9d3e-a96be3a6bdc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3846063905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3846063905
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3981300948
Short name T107
Test name
Test status
Simulation time 200655503 ps
CPU time 0.85 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:15 PM PDT 24
Peak memory 206756 kb
Host smart-c1d1ca9c-bd63-489d-b947-eac97b155f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39813
00948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3981300948
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1062027694
Short name T14
Test name
Test status
Simulation time 23458426793 ps
CPU time 26.83 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:05:20 PM PDT 24
Peak memory 207052 kb
Host smart-36af39f5-4400-43f0-b5fd-7e97ec1256bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1062027694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1062027694
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3420026443
Short name T194
Test name
Test status
Simulation time 71278279 ps
CPU time 0.77 seconds
Started Jul 15 06:13:03 PM PDT 24
Finished Jul 15 06:13:04 PM PDT 24
Peak memory 206316 kb
Host smart-cae89086-254b-44a1-b7b8-df51384d5bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3420026443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3420026443
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2177346556
Short name T39
Test name
Test status
Simulation time 39542589 ps
CPU time 0.71 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:20 PM PDT 24
Peak memory 206804 kb
Host smart-5f1e76a8-b461-42c7-b49c-794c61516a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21773
46556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2177346556
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1764373941
Short name T245
Test name
Test status
Simulation time 76803861 ps
CPU time 0.8 seconds
Started Jul 15 06:12:07 PM PDT 24
Finished Jul 15 06:12:08 PM PDT 24
Peak memory 206328 kb
Host smart-0de40d29-6ae2-4991-a9e7-291c8cdd53cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1764373941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1764373941
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1079062892
Short name T71
Test name
Test status
Simulation time 323938357 ps
CPU time 1.04 seconds
Started Jul 15 07:02:35 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 206780 kb
Host smart-11e5dff0-bf60-4935-9435-6bcded662e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10790
62892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1079062892
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.989559792
Short name T42
Test name
Test status
Simulation time 20166579114 ps
CPU time 20.1 seconds
Started Jul 15 07:02:41 PM PDT 24
Finished Jul 15 07:03:01 PM PDT 24
Peak memory 206876 kb
Host smart-bbb093f8-e015-402c-9a3b-ce9e0fe181bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98955
9792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.989559792
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3558414772
Short name T55
Test name
Test status
Simulation time 7341273326 ps
CPU time 71.27 seconds
Started Jul 15 07:03:24 PM PDT 24
Finished Jul 15 07:04:36 PM PDT 24
Peak memory 207064 kb
Host smart-8037e26e-4cf2-41d8-b641-9753f24110c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3558414772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3558414772
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.3207851973
Short name T515
Test name
Test status
Simulation time 172307476 ps
CPU time 0.82 seconds
Started Jul 15 07:02:43 PM PDT 24
Finished Jul 15 07:02:44 PM PDT 24
Peak memory 206824 kb
Host smart-ba244665-3234-437b-b183-6bc5b6c594e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32078
51973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.3207851973
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1837310106
Short name T268
Test name
Test status
Simulation time 161883123 ps
CPU time 0.78 seconds
Started Jul 15 07:06:53 PM PDT 24
Finished Jul 15 07:06:56 PM PDT 24
Peak memory 206812 kb
Host smart-c30b8068-d120-403a-b578-c48cddcafdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18373
10106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1837310106
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2805093199
Short name T230
Test name
Test status
Simulation time 1157184457 ps
CPU time 5.62 seconds
Started Jul 15 06:13:00 PM PDT 24
Finished Jul 15 06:13:06 PM PDT 24
Peak memory 206524 kb
Host smart-f306e4bd-54f1-4014-9a79-597694e48154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2805093199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2805093199
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4145811244
Short name T193
Test name
Test status
Simulation time 47610656 ps
CPU time 0.72 seconds
Started Jul 15 06:12:59 PM PDT 24
Finished Jul 15 06:13:01 PM PDT 24
Peak memory 206220 kb
Host smart-eda4601c-7466-4e97-95b8-8d168518c3f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145811244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.4145811244
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1849731858
Short name T236
Test name
Test status
Simulation time 60880649 ps
CPU time 0.78 seconds
Started Jul 15 06:12:24 PM PDT 24
Finished Jul 15 06:12:25 PM PDT 24
Peak memory 206320 kb
Host smart-473d193a-f55b-427e-b300-35271c6d11d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1849731858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1849731858
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2659988685
Short name T63
Test name
Test status
Simulation time 535515327 ps
CPU time 1.49 seconds
Started Jul 15 07:02:31 PM PDT 24
Finished Jul 15 07:02:33 PM PDT 24
Peak memory 206792 kb
Host smart-6e54d5ee-9929-4cf8-b1f0-5823f8e2bf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26599
88685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2659988685
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1178643171
Short name T275
Test name
Test status
Simulation time 584928095 ps
CPU time 4.36 seconds
Started Jul 15 06:12:41 PM PDT 24
Finished Jul 15 06:12:45 PM PDT 24
Peak memory 206444 kb
Host smart-c514fe9d-2bac-4fef-8a60-ed6530c9f297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1178643171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1178643171
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1466488168
Short name T735
Test name
Test status
Simulation time 42831925 ps
CPU time 0.68 seconds
Started Jul 15 07:02:48 PM PDT 24
Finished Jul 15 07:02:50 PM PDT 24
Peak memory 206840 kb
Host smart-f670735d-f34a-40a4-b3fc-388286115b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1466488168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1466488168
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1644826635
Short name T15
Test name
Test status
Simulation time 3760360621 ps
CPU time 4.21 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:09 PM PDT 24
Peak memory 206836 kb
Host smart-e7340e38-27ad-4f1f-94d1-dfb4a335cb8c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1644826635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1644826635
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.4135777213
Short name T16
Test name
Test status
Simulation time 1402828667 ps
CPU time 2.84 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:35 PM PDT 24
Peak memory 207016 kb
Host smart-6d6b07f8-df52-4754-94f6-168f355c1065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
77213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.4135777213
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.4242100255
Short name T49
Test name
Test status
Simulation time 261299881 ps
CPU time 1.01 seconds
Started Jul 15 07:02:41 PM PDT 24
Finished Jul 15 07:02:42 PM PDT 24
Peak memory 206816 kb
Host smart-a63b3ae4-daaa-4656-ba8b-9804a96123c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42421
00255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.4242100255
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1783784607
Short name T87
Test name
Test status
Simulation time 13090385103 ps
CPU time 25.09 seconds
Started Jul 15 07:04:53 PM PDT 24
Finished Jul 15 07:05:19 PM PDT 24
Peak memory 207088 kb
Host smart-be5277ee-6331-4383-8f9d-13f73159f731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17837
84607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1783784607
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3234331251
Short name T58
Test name
Test status
Simulation time 217051434 ps
CPU time 0.78 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:27 PM PDT 24
Peak memory 206820 kb
Host smart-91c1d70b-847f-4192-ad55-5408d13ba263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32343
31251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3234331251
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2794988543
Short name T2781
Test name
Test status
Simulation time 49850873 ps
CPU time 0.68 seconds
Started Jul 15 06:11:57 PM PDT 24
Finished Jul 15 06:11:58 PM PDT 24
Peak memory 206324 kb
Host smart-c58354bf-9013-4aef-9ccf-ef8d42752846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2794988543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2794988543
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3248839258
Short name T281
Test name
Test status
Simulation time 719450896 ps
CPU time 4.54 seconds
Started Jul 15 06:12:42 PM PDT 24
Finished Jul 15 06:12:47 PM PDT 24
Peak memory 206500 kb
Host smart-d8e01d02-4650-4329-8842-4b4631b585c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3248839258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3248839258
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.108086363
Short name T208
Test name
Test status
Simulation time 416460237 ps
CPU time 2.71 seconds
Started Jul 15 06:12:12 PM PDT 24
Finished Jul 15 06:12:15 PM PDT 24
Peak memory 206524 kb
Host smart-4bb3befb-ccec-48f4-8a8d-e753980c2149
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=108086363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.108086363
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2169629601
Short name T17
Test name
Test status
Simulation time 9225042242 ps
CPU time 43.07 seconds
Started Jul 15 07:03:44 PM PDT 24
Finished Jul 15 07:04:28 PM PDT 24
Peak memory 207064 kb
Host smart-8a21c36e-4719-42d8-8020-df84a2d69a32
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2169629601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2169629601
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3099221412
Short name T2773
Test name
Test status
Simulation time 112883844 ps
CPU time 2.42 seconds
Started Jul 15 06:12:52 PM PDT 24
Finished Jul 15 06:12:55 PM PDT 24
Peak memory 222268 kb
Host smart-dc91d80e-4758-4d84-a228-c68da261347e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3099221412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3099221412
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3765901732
Short name T642
Test name
Test status
Simulation time 139990238 ps
CPU time 0.76 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:10 PM PDT 24
Peak memory 206780 kb
Host smart-c7a25574-db3a-4010-ad95-e54869b4df53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37659
01732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3765901732
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3448137550
Short name T174
Test name
Test status
Simulation time 23263971892 ps
CPU time 20.95 seconds
Started Jul 15 07:05:34 PM PDT 24
Finished Jul 15 07:05:56 PM PDT 24
Peak memory 206852 kb
Host smart-e7bed555-e732-4ca7-b14e-42c6019977e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34481
37550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3448137550
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3172317170
Short name T106
Test name
Test status
Simulation time 225349851 ps
CPU time 0.9 seconds
Started Jul 15 07:02:40 PM PDT 24
Finished Jul 15 07:02:42 PM PDT 24
Peak memory 206824 kb
Host smart-020ff38d-4654-4dbf-a94a-2862e80f42b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723
17170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3172317170
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.4119390907
Short name T59
Test name
Test status
Simulation time 204729447 ps
CPU time 0.79 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:02:51 PM PDT 24
Peak memory 206800 kb
Host smart-eee45c87-1a77-4b8b-82ff-a4b6f9faa2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41193
90907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.4119390907
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.38116594
Short name T412
Test name
Test status
Simulation time 245106680 ps
CPU time 1.45 seconds
Started Jul 15 07:02:47 PM PDT 24
Finished Jul 15 07:02:49 PM PDT 24
Peak memory 206988 kb
Host smart-fe814f4e-8826-4ab1-8c4f-7a749ace0f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38116
594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.38116594
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1596879242
Short name T67
Test name
Test status
Simulation time 6821565621 ps
CPU time 48.93 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:09:44 PM PDT 24
Peak memory 207016 kb
Host smart-d57306c0-5e0e-4691-a78f-77655dec2446
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1596879242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1596879242
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.2502955957
Short name T50
Test name
Test status
Simulation time 191513429 ps
CPU time 0.8 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:02:32 PM PDT 24
Peak memory 206808 kb
Host smart-b559b31f-7656-4b8d-9e41-efb776e273c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25029
55957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.2502955957
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3442844403
Short name T60
Test name
Test status
Simulation time 4163409417 ps
CPU time 8.74 seconds
Started Jul 15 07:02:38 PM PDT 24
Finished Jul 15 07:02:48 PM PDT 24
Peak memory 207028 kb
Host smart-4128d1c6-3894-4fa8-becb-8dda618262df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34428
44403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3442844403
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3656489571
Short name T61
Test name
Test status
Simulation time 190473630 ps
CPU time 0.83 seconds
Started Jul 15 07:02:29 PM PDT 24
Finished Jul 15 07:02:31 PM PDT 24
Peak memory 206820 kb
Host smart-c2f41c29-0d1b-4d86-9364-2935b7814c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36564
89571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3656489571
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1628623012
Short name T75
Test name
Test status
Simulation time 219058057 ps
CPU time 0.87 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:02:38 PM PDT 24
Peak memory 206804 kb
Host smart-5d4e3fa9-31f2-44ab-ae63-6234a556681b
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1628623012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1628623012
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2232198782
Short name T848
Test name
Test status
Simulation time 71414710 ps
CPU time 0.69 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 206776 kb
Host smart-59c731bd-7b85-41c7-8e64-dc01aff9d0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22321
98782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2232198782
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1622533922
Short name T69
Test name
Test status
Simulation time 199902616 ps
CPU time 0.84 seconds
Started Jul 15 07:02:41 PM PDT 24
Finished Jul 15 07:02:42 PM PDT 24
Peak memory 206760 kb
Host smart-c2b983b3-73e5-4a5e-83e6-f84317b8fce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16225
33922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1622533922
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1381429716
Short name T43
Test name
Test status
Simulation time 179522080 ps
CPU time 0.8 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 206796 kb
Host smart-d2ec95fc-4b38-475b-8f1a-44376b12776f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13814
29716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1381429716
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3324343290
Short name T182
Test name
Test status
Simulation time 376407848 ps
CPU time 2.48 seconds
Started Jul 15 06:11:50 PM PDT 24
Finished Jul 15 06:11:53 PM PDT 24
Peak memory 206444 kb
Host smart-6002b521-c2d8-4dd8-9bb9-d0cc1cd2d9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3324343290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3324343290
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3090424123
Short name T229
Test name
Test status
Simulation time 685063755 ps
CPU time 2.98 seconds
Started Jul 15 06:12:52 PM PDT 24
Finished Jul 15 06:12:55 PM PDT 24
Peak memory 206444 kb
Host smart-0193d961-3916-4b94-9437-d5c9abaac699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3090424123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3090424123
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.689558231
Short name T115
Test name
Test status
Simulation time 180937771 ps
CPU time 0.85 seconds
Started Jul 15 07:02:41 PM PDT 24
Finished Jul 15 07:02:43 PM PDT 24
Peak memory 206808 kb
Host smart-cfe3d9c7-9edc-4d76-953a-be860dc5e5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68955
8231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.689558231
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.663269080
Short name T156
Test name
Test status
Simulation time 7346326066 ps
CPU time 62.29 seconds
Started Jul 15 07:02:34 PM PDT 24
Finished Jul 15 07:03:37 PM PDT 24
Peak memory 207024 kb
Host smart-3cbcb242-190f-4bec-ae61-220cb9893e62
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=663269080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.663269080
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.905656140
Short name T48
Test name
Test status
Simulation time 396634433 ps
CPU time 1.3 seconds
Started Jul 15 07:02:42 PM PDT 24
Finished Jul 15 07:02:44 PM PDT 24
Peak memory 206796 kb
Host smart-f4731343-38c5-4013-a008-7da2fe1226d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90565
6140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.905656140
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3930732679
Short name T113
Test name
Test status
Simulation time 164184746 ps
CPU time 0.83 seconds
Started Jul 15 07:02:52 PM PDT 24
Finished Jul 15 07:02:54 PM PDT 24
Peak memory 206840 kb
Host smart-c0358df5-cd02-418b-a811-b47ce471fdb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39307
32679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3930732679
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.577245589
Short name T135
Test name
Test status
Simulation time 168746331 ps
CPU time 0.85 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:04:46 PM PDT 24
Peak memory 206700 kb
Host smart-669aa8d7-40c7-4344-98b2-0d7721d832da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57724
5589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.577245589
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.43219263
Short name T2734
Test name
Test status
Simulation time 215549686 ps
CPU time 0.91 seconds
Started Jul 15 07:05:06 PM PDT 24
Finished Jul 15 07:05:08 PM PDT 24
Peak memory 206836 kb
Host smart-a35700b3-3a1f-4e49-9130-4a0083a5a7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43219
263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.43219263
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3016912873
Short name T2128
Test name
Test status
Simulation time 183085988 ps
CPU time 0.8 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:25 PM PDT 24
Peak memory 206816 kb
Host smart-649eaec9-f353-499e-96c3-17bf6b3ae7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30169
12873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3016912873
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.151127482
Short name T2325
Test name
Test status
Simulation time 6744263043 ps
CPU time 62.26 seconds
Started Jul 15 07:05:32 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 207112 kb
Host smart-58651bbe-4ad6-48fd-94af-55659d6f7ff3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=151127482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.151127482
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.4091288277
Short name T2163
Test name
Test status
Simulation time 171679650 ps
CPU time 0.81 seconds
Started Jul 15 07:05:41 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 206828 kb
Host smart-a35563e9-1b5a-4e56-aad8-76bea0e3f062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912
88277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.4091288277
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1617361799
Short name T121
Test name
Test status
Simulation time 188842436 ps
CPU time 0.83 seconds
Started Jul 15 07:05:44 PM PDT 24
Finished Jul 15 07:05:47 PM PDT 24
Peak memory 206144 kb
Host smart-9d39a7fa-7977-4cf4-9850-bcaef8d1d5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16173
61799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1617361799
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3191959526
Short name T126
Test name
Test status
Simulation time 188466216 ps
CPU time 0.92 seconds
Started Jul 15 07:06:04 PM PDT 24
Finished Jul 15 07:06:05 PM PDT 24
Peak memory 206792 kb
Host smart-f1ecc573-dc84-487d-a082-06d4021b1678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31919
59526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3191959526
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1709880204
Short name T129
Test name
Test status
Simulation time 200930769 ps
CPU time 0.9 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206812 kb
Host smart-fa32212f-795b-428f-81b7-8704937fc8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17098
80204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1709880204
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2438606785
Short name T131
Test name
Test status
Simulation time 192648036 ps
CPU time 0.88 seconds
Started Jul 15 07:07:05 PM PDT 24
Finished Jul 15 07:07:06 PM PDT 24
Peak memory 206800 kb
Host smart-a818e545-d0b6-4f79-b518-fba2d56d21e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24386
06785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2438606785
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3420446143
Short name T136
Test name
Test status
Simulation time 269791863 ps
CPU time 0.95 seconds
Started Jul 15 07:09:40 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206840 kb
Host smart-05ce47fa-ba85-4bbb-b021-adbbb6c9e4ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34204
46143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3420446143
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3555460463
Short name T247
Test name
Test status
Simulation time 216426245 ps
CPU time 2.2 seconds
Started Jul 15 06:11:51 PM PDT 24
Finished Jul 15 06:11:53 PM PDT 24
Peak memory 206468 kb
Host smart-3407e315-fe8e-4b15-bead-bdbed3b53947
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3555460463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3555460463
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4110279057
Short name T239
Test name
Test status
Simulation time 605925617 ps
CPU time 7.34 seconds
Started Jul 15 06:11:50 PM PDT 24
Finished Jul 15 06:11:58 PM PDT 24
Peak memory 206332 kb
Host smart-21770830-feb4-45ca-b767-a91a47d546c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4110279057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.4110279057
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2447065513
Short name T2754
Test name
Test status
Simulation time 83236061 ps
CPU time 0.8 seconds
Started Jul 15 06:11:50 PM PDT 24
Finished Jul 15 06:11:52 PM PDT 24
Peak memory 206320 kb
Host smart-07549fec-865c-4538-9bc1-7761b3e4d159
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2447065513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2447065513
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1619267696
Short name T2845
Test name
Test status
Simulation time 98309760 ps
CPU time 2.46 seconds
Started Jul 15 06:11:58 PM PDT 24
Finished Jul 15 06:12:01 PM PDT 24
Peak memory 214772 kb
Host smart-f69261f6-6ee1-4a58-81c0-c07fb3e21dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619267696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1619267696
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1184439218
Short name T2815
Test name
Test status
Simulation time 67520934 ps
CPU time 0.97 seconds
Started Jul 15 06:11:50 PM PDT 24
Finished Jul 15 06:11:51 PM PDT 24
Peak memory 206388 kb
Host smart-480bc3c5-a8e1-4656-9501-c2960b65642c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1184439218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1184439218
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3685783744
Short name T2799
Test name
Test status
Simulation time 104263273 ps
CPU time 0.71 seconds
Started Jul 15 06:11:51 PM PDT 24
Finished Jul 15 06:11:52 PM PDT 24
Peak memory 206312 kb
Host smart-472f1707-a309-401c-879c-9296b5a8e1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3685783744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3685783744
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3386727695
Short name T246
Test name
Test status
Simulation time 109311339 ps
CPU time 1.4 seconds
Started Jul 15 06:11:49 PM PDT 24
Finished Jul 15 06:11:50 PM PDT 24
Peak memory 214676 kb
Host smart-a518f40b-abcc-4fd7-8077-3a3902adfad1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3386727695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3386727695
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.401383997
Short name T2749
Test name
Test status
Simulation time 99399670 ps
CPU time 2.22 seconds
Started Jul 15 06:11:50 PM PDT 24
Finished Jul 15 06:11:53 PM PDT 24
Peak memory 206456 kb
Host smart-1c41fe2d-11dc-4add-a532-968881fbdaee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=401383997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.401383997
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2544714169
Short name T2785
Test name
Test status
Simulation time 168760834 ps
CPU time 1.2 seconds
Started Jul 15 06:11:49 PM PDT 24
Finished Jul 15 06:11:51 PM PDT 24
Peak memory 206448 kb
Host smart-7e48738e-fcc8-444e-bcec-0a53a8c12e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2544714169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2544714169
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1713770296
Short name T210
Test name
Test status
Simulation time 67663606 ps
CPU time 1.57 seconds
Started Jul 15 06:11:49 PM PDT 24
Finished Jul 15 06:11:51 PM PDT 24
Peak memory 206656 kb
Host smart-83675df3-9dc7-49fe-877c-ac2556ba3d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1713770296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1713770296
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3279942597
Short name T2806
Test name
Test status
Simulation time 295610083 ps
CPU time 3.73 seconds
Started Jul 15 06:12:05 PM PDT 24
Finished Jul 15 06:12:09 PM PDT 24
Peak memory 206408 kb
Host smart-bedb1d6d-8dfd-441b-ad9b-d4fd53bca7e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3279942597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3279942597
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3643909656
Short name T249
Test name
Test status
Simulation time 169651698 ps
CPU time 3.76 seconds
Started Jul 15 06:12:07 PM PDT 24
Finished Jul 15 06:12:11 PM PDT 24
Peak memory 206396 kb
Host smart-00d6681b-d8d3-4408-ae6b-12dc26d889bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3643909656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3643909656
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.728827725
Short name T2841
Test name
Test status
Simulation time 96587044 ps
CPU time 0.93 seconds
Started Jul 15 06:12:01 PM PDT 24
Finished Jul 15 06:12:02 PM PDT 24
Peak memory 206244 kb
Host smart-d4ea864f-adbe-4bc3-97f4-3ce233808564
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=728827725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.728827725
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1100693184
Short name T2784
Test name
Test status
Simulation time 98777008 ps
CPU time 1.18 seconds
Started Jul 15 06:12:05 PM PDT 24
Finished Jul 15 06:12:07 PM PDT 24
Peak memory 214736 kb
Host smart-fb8d95de-5772-498e-8f9d-d01a187ada14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100693184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1100693184
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2699815000
Short name T255
Test name
Test status
Simulation time 67751088 ps
CPU time 0.87 seconds
Started Jul 15 06:11:58 PM PDT 24
Finished Jul 15 06:11:59 PM PDT 24
Peak memory 206312 kb
Host smart-af23a3b2-af63-4acf-896d-77287d218224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2699815000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2699815000
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1592449421
Short name T243
Test name
Test status
Simulation time 161494385 ps
CPU time 1.53 seconds
Started Jul 15 06:12:01 PM PDT 24
Finished Jul 15 06:12:03 PM PDT 24
Peak memory 215920 kb
Host smart-f7386ee9-71ae-4182-844c-033d4d0c5387
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1592449421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1592449421
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2638097285
Short name T2852
Test name
Test status
Simulation time 95917181 ps
CPU time 2.31 seconds
Started Jul 15 06:11:57 PM PDT 24
Finished Jul 15 06:11:59 PM PDT 24
Peak memory 206424 kb
Host smart-749bdf96-0139-488c-b849-eeb6736cc9db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2638097285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2638097285
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.388984074
Short name T253
Test name
Test status
Simulation time 164706512 ps
CPU time 1.07 seconds
Started Jul 15 06:12:05 PM PDT 24
Finished Jul 15 06:12:07 PM PDT 24
Peak memory 206460 kb
Host smart-c143eca2-cb54-4694-a57c-a1617bf6a789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=388984074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.388984074
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2857444354
Short name T209
Test name
Test status
Simulation time 114093366 ps
CPU time 1.41 seconds
Started Jul 15 06:11:58 PM PDT 24
Finished Jul 15 06:12:00 PM PDT 24
Peak memory 206560 kb
Host smart-db2273e9-dd71-4ebc-966e-be8da394a6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2857444354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2857444354
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2223518604
Short name T2838
Test name
Test status
Simulation time 169405292 ps
CPU time 1.64 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:37 PM PDT 24
Peak memory 214816 kb
Host smart-ad869c50-23e2-4037-a845-9c6c70a9d6dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223518604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2223518604
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.365264414
Short name T2760
Test name
Test status
Simulation time 70356558 ps
CPU time 0.83 seconds
Started Jul 15 06:12:33 PM PDT 24
Finished Jul 15 06:12:35 PM PDT 24
Peak memory 206356 kb
Host smart-8cf38c48-feaa-46dc-affa-87a151c0479e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=365264414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.365264414
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3860161807
Short name T2827
Test name
Test status
Simulation time 51529081 ps
CPU time 0.69 seconds
Started Jul 15 06:12:35 PM PDT 24
Finished Jul 15 06:12:36 PM PDT 24
Peak memory 206292 kb
Host smart-e8e91a3c-5891-43bc-b61a-526dde48d556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3860161807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3860161807
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.695596296
Short name T183
Test name
Test status
Simulation time 103642376 ps
CPU time 1.36 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:35 PM PDT 24
Peak memory 206544 kb
Host smart-fb73661d-3b75-445f-a81c-b8976d52031d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=695596296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.695596296
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3242917393
Short name T221
Test name
Test status
Simulation time 92369842 ps
CPU time 2.18 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:37 PM PDT 24
Peak memory 206632 kb
Host smart-318b45d6-c60a-4c78-9211-4d77a77a9dad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3242917393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3242917393
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2191211951
Short name T231
Test name
Test status
Simulation time 473381459 ps
CPU time 2.5 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:37 PM PDT 24
Peak memory 206476 kb
Host smart-b30db823-62cc-4a11-95ad-afd378d7acc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2191211951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2191211951
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1836937073
Short name T2807
Test name
Test status
Simulation time 141741955 ps
CPU time 1.21 seconds
Started Jul 15 06:12:44 PM PDT 24
Finished Jul 15 06:12:46 PM PDT 24
Peak memory 214800 kb
Host smart-0706feb2-364c-4907-8647-2bdf6b56090a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836937073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1836937073
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1874344135
Short name T250
Test name
Test status
Simulation time 172203947 ps
CPU time 1.16 seconds
Started Jul 15 06:12:45 PM PDT 24
Finished Jul 15 06:12:47 PM PDT 24
Peak memory 206508 kb
Host smart-c3efe764-5b3e-4aba-8ca2-52ba2eab6508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1874344135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1874344135
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2807193773
Short name T2795
Test name
Test status
Simulation time 34756241 ps
CPU time 0.67 seconds
Started Jul 15 06:12:33 PM PDT 24
Finished Jul 15 06:12:34 PM PDT 24
Peak memory 206296 kb
Host smart-24794b0a-67fe-4c98-80c7-4da75af7b1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2807193773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2807193773
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3196932978
Short name T2854
Test name
Test status
Simulation time 181105126 ps
CPU time 1.51 seconds
Started Jul 15 06:12:43 PM PDT 24
Finished Jul 15 06:12:45 PM PDT 24
Peak memory 206472 kb
Host smart-f5d11e4e-50e8-47e2-a20c-da4511b94728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3196932978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3196932978
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1473012088
Short name T2809
Test name
Test status
Simulation time 148779806 ps
CPU time 2.91 seconds
Started Jul 15 06:12:35 PM PDT 24
Finished Jul 15 06:12:38 PM PDT 24
Peak memory 206588 kb
Host smart-9c2c7340-9669-45a9-a4a4-810c8b0a5d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1473012088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1473012088
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2883153435
Short name T2780
Test name
Test status
Simulation time 498006229 ps
CPU time 2.92 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:38 PM PDT 24
Peak memory 206524 kb
Host smart-9aaec594-a258-4c31-87d8-e54d3e3195e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2883153435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2883153435
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3282112728
Short name T2768
Test name
Test status
Simulation time 107255422 ps
CPU time 1.18 seconds
Started Jul 15 06:12:44 PM PDT 24
Finished Jul 15 06:12:45 PM PDT 24
Peak memory 214824 kb
Host smart-cdd4ab65-89e2-413a-b885-dae9cc592013
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282112728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3282112728
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1844110070
Short name T2779
Test name
Test status
Simulation time 35103555 ps
CPU time 0.75 seconds
Started Jul 15 06:12:42 PM PDT 24
Finished Jul 15 06:12:43 PM PDT 24
Peak memory 206340 kb
Host smart-e765b864-1ff1-4289-a4f6-37ce9855d8f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1844110070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1844110070
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.226320451
Short name T2771
Test name
Test status
Simulation time 46550675 ps
CPU time 0.71 seconds
Started Jul 15 06:12:41 PM PDT 24
Finished Jul 15 06:12:42 PM PDT 24
Peak memory 206312 kb
Host smart-e855ca16-7a73-434f-a40b-e16e31fe9869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=226320451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.226320451
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3231319614
Short name T2830
Test name
Test status
Simulation time 129810320 ps
CPU time 1.2 seconds
Started Jul 15 06:12:43 PM PDT 24
Finished Jul 15 06:12:45 PM PDT 24
Peak memory 206592 kb
Host smart-63d4e585-b3d3-4296-aecf-0bc4d2a31bf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3231319614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3231319614
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1939629349
Short name T223
Test name
Test status
Simulation time 125906801 ps
CPU time 1.49 seconds
Started Jul 15 06:12:45 PM PDT 24
Finished Jul 15 06:12:46 PM PDT 24
Peak memory 214708 kb
Host smart-61addc18-a713-4861-ab35-87a3177940e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1939629349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1939629349
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1104670078
Short name T2839
Test name
Test status
Simulation time 162018697 ps
CPU time 1.99 seconds
Started Jul 15 06:12:43 PM PDT 24
Finished Jul 15 06:12:46 PM PDT 24
Peak memory 214632 kb
Host smart-4079f0fd-154e-4a37-b5f2-af6863fd07b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104670078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1104670078
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.557412608
Short name T241
Test name
Test status
Simulation time 109524517 ps
CPU time 0.91 seconds
Started Jul 15 06:12:44 PM PDT 24
Finished Jul 15 06:12:46 PM PDT 24
Peak memory 206292 kb
Host smart-e0340094-64f6-4464-ad53-eb375692b3c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=557412608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.557412608
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1710660579
Short name T190
Test name
Test status
Simulation time 43737099 ps
CPU time 0.68 seconds
Started Jul 15 06:12:42 PM PDT 24
Finished Jul 15 06:12:43 PM PDT 24
Peak memory 206272 kb
Host smart-924b3eef-e190-48ab-ab38-20baab87696a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1710660579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1710660579
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2329387588
Short name T2823
Test name
Test status
Simulation time 367942770 ps
CPU time 1.64 seconds
Started Jul 15 06:12:43 PM PDT 24
Finished Jul 15 06:12:45 PM PDT 24
Peak memory 206444 kb
Host smart-00067a26-bae1-47f1-87e4-67ee190e9f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2329387588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2329387588
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3790494700
Short name T2786
Test name
Test status
Simulation time 150215287 ps
CPU time 1.71 seconds
Started Jul 15 06:12:43 PM PDT 24
Finished Jul 15 06:12:46 PM PDT 24
Peak memory 215796 kb
Host smart-ad35f6b6-63b3-4185-9407-38fb06d4c671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3790494700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3790494700
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3076041092
Short name T2790
Test name
Test status
Simulation time 181963344 ps
CPU time 2.06 seconds
Started Jul 15 06:12:51 PM PDT 24
Finished Jul 15 06:12:53 PM PDT 24
Peak memory 214772 kb
Host smart-1d621933-b3e4-45de-96e9-8026fed2dc0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076041092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3076041092
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1386709595
Short name T2801
Test name
Test status
Simulation time 43038116 ps
CPU time 0.8 seconds
Started Jul 15 06:12:50 PM PDT 24
Finished Jul 15 06:12:51 PM PDT 24
Peak memory 206344 kb
Host smart-1ee298b8-3585-4968-8ba0-ad608f59cac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1386709595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1386709595
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3557847342
Short name T189
Test name
Test status
Simulation time 42537335 ps
CPU time 0.65 seconds
Started Jul 15 06:12:51 PM PDT 24
Finished Jul 15 06:12:53 PM PDT 24
Peak memory 206300 kb
Host smart-e2eaa30e-a881-443d-8172-110d0dd0517c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3557847342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3557847342
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4032061277
Short name T2751
Test name
Test status
Simulation time 60398066 ps
CPU time 1.08 seconds
Started Jul 15 06:12:49 PM PDT 24
Finished Jul 15 06:12:51 PM PDT 24
Peak memory 206444 kb
Host smart-e0025bc0-68cb-439d-b5fe-e4edf8660323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4032061277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.4032061277
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2698677473
Short name T2844
Test name
Test status
Simulation time 177471781 ps
CPU time 3.06 seconds
Started Jul 15 06:12:43 PM PDT 24
Finished Jul 15 06:12:47 PM PDT 24
Peak memory 222180 kb
Host smart-4add2b1b-9367-4b5d-9fea-891097a1d663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2698677473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2698677473
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2604598818
Short name T2856
Test name
Test status
Simulation time 1714180170 ps
CPU time 5.46 seconds
Started Jul 15 06:12:41 PM PDT 24
Finished Jul 15 06:12:47 PM PDT 24
Peak memory 206488 kb
Host smart-9f03affb-6631-467d-986b-318486c5fd2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2604598818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2604598818
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3289495484
Short name T262
Test name
Test status
Simulation time 201601490 ps
CPU time 1.25 seconds
Started Jul 15 06:12:50 PM PDT 24
Finished Jul 15 06:12:52 PM PDT 24
Peak memory 214832 kb
Host smart-38d10aa7-b638-48d9-b7e1-0c7904efa711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289495484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3289495484
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.913648082
Short name T2833
Test name
Test status
Simulation time 47570741 ps
CPU time 0.8 seconds
Started Jul 15 06:12:52 PM PDT 24
Finished Jul 15 06:12:53 PM PDT 24
Peak memory 206292 kb
Host smart-a3cfedf1-2c15-432e-ae08-cbdc2da7eeb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=913648082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.913648082
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2625019266
Short name T2826
Test name
Test status
Simulation time 40798832 ps
CPU time 0.64 seconds
Started Jul 15 06:12:50 PM PDT 24
Finished Jul 15 06:12:51 PM PDT 24
Peak memory 206300 kb
Host smart-ff2bf381-fb9f-485f-98e1-833c12168ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2625019266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2625019266
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1423055016
Short name T214
Test name
Test status
Simulation time 419897970 ps
CPU time 2.01 seconds
Started Jul 15 06:12:51 PM PDT 24
Finished Jul 15 06:12:54 PM PDT 24
Peak memory 206568 kb
Host smart-681a92fe-5ef3-4102-af6d-1f50a3554b77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1423055016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1423055016
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.51004695
Short name T2831
Test name
Test status
Simulation time 281847074 ps
CPU time 3.22 seconds
Started Jul 15 06:12:48 PM PDT 24
Finished Jul 15 06:12:52 PM PDT 24
Peak memory 222580 kb
Host smart-f6688b46-7af7-44d3-9713-f7c798c27a67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=51004695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.51004695
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3000677900
Short name T2798
Test name
Test status
Simulation time 281120332 ps
CPU time 2.59 seconds
Started Jul 15 06:12:51 PM PDT 24
Finished Jul 15 06:12:54 PM PDT 24
Peak memory 206496 kb
Host smart-a426f484-4da1-4e23-81b8-f3c4b0ca896b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3000677900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3000677900
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1623219359
Short name T2811
Test name
Test status
Simulation time 131827052 ps
CPU time 1.67 seconds
Started Jul 15 06:12:52 PM PDT 24
Finished Jul 15 06:12:54 PM PDT 24
Peak memory 222940 kb
Host smart-e82a3b48-cc2c-43a6-a927-28bc55444925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623219359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1623219359
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2243417372
Short name T261
Test name
Test status
Simulation time 111353558 ps
CPU time 1.06 seconds
Started Jul 15 06:12:52 PM PDT 24
Finished Jul 15 06:12:53 PM PDT 24
Peak memory 206328 kb
Host smart-2fe03ed7-cecf-4fff-9295-7ac0037c8d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2243417372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2243417372
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1164184144
Short name T251
Test name
Test status
Simulation time 227464938 ps
CPU time 1.28 seconds
Started Jul 15 06:12:50 PM PDT 24
Finished Jul 15 06:12:51 PM PDT 24
Peak memory 206496 kb
Host smart-36e9d7b2-3f24-48a9-9c40-248ba56e5b2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1164184144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1164184144
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3753137984
Short name T2761
Test name
Test status
Simulation time 61917440 ps
CPU time 1.37 seconds
Started Jul 15 06:12:59 PM PDT 24
Finished Jul 15 06:13:01 PM PDT 24
Peak memory 214736 kb
Host smart-124bfac6-7e67-447c-aa4f-4d80a58e0680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753137984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3753137984
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3433339127
Short name T2825
Test name
Test status
Simulation time 79893781 ps
CPU time 0.97 seconds
Started Jul 15 06:12:56 PM PDT 24
Finished Jul 15 06:12:57 PM PDT 24
Peak memory 206488 kb
Host smart-7331b9ed-17a3-4074-abc3-1e5435d4148d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3433339127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3433339127
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2015797534
Short name T2855
Test name
Test status
Simulation time 40091232 ps
CPU time 0.63 seconds
Started Jul 15 06:12:51 PM PDT 24
Finished Jul 15 06:12:52 PM PDT 24
Peak memory 206296 kb
Host smart-c9c1cc8a-a934-4ef0-ad5d-d30b0a41851d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2015797534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2015797534
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4134038608
Short name T2774
Test name
Test status
Simulation time 308903045 ps
CPU time 2.06 seconds
Started Jul 15 06:13:03 PM PDT 24
Finished Jul 15 06:13:06 PM PDT 24
Peak memory 206540 kb
Host smart-18cc3e31-a378-4450-9fa9-45d44df3b9f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4134038608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.4134038608
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1167906760
Short name T227
Test name
Test status
Simulation time 92742803 ps
CPU time 2.37 seconds
Started Jul 15 06:12:51 PM PDT 24
Finished Jul 15 06:12:54 PM PDT 24
Peak memory 214776 kb
Host smart-676f6011-1f24-4895-957e-b8f7cbfd20f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1167906760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1167906760
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.379042369
Short name T278
Test name
Test status
Simulation time 891261315 ps
CPU time 4.85 seconds
Started Jul 15 06:12:52 PM PDT 24
Finished Jul 15 06:12:57 PM PDT 24
Peak memory 206728 kb
Host smart-33e34092-a712-4686-ae0d-200013752f78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=379042369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.379042369
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4011074782
Short name T2851
Test name
Test status
Simulation time 70762211 ps
CPU time 1.41 seconds
Started Jul 15 06:13:01 PM PDT 24
Finished Jul 15 06:13:02 PM PDT 24
Peak memory 214768 kb
Host smart-cb0d3134-ffcc-4300-aadc-2ba3946f59ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011074782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.4011074782
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1997493647
Short name T2791
Test name
Test status
Simulation time 40464076 ps
CPU time 0.73 seconds
Started Jul 15 06:13:00 PM PDT 24
Finished Jul 15 06:13:01 PM PDT 24
Peak memory 206332 kb
Host smart-9ca53047-c4d5-46e0-907b-c87184f200ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1997493647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1997493647
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2594716055
Short name T2763
Test name
Test status
Simulation time 35311716 ps
CPU time 0.64 seconds
Started Jul 15 06:12:57 PM PDT 24
Finished Jul 15 06:12:58 PM PDT 24
Peak memory 206316 kb
Host smart-7f0ab4ad-bad0-4d38-9e2a-d81496605ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2594716055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2594716055
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1497181035
Short name T2753
Test name
Test status
Simulation time 274684784 ps
CPU time 2.19 seconds
Started Jul 15 06:13:00 PM PDT 24
Finished Jul 15 06:13:03 PM PDT 24
Peak memory 206512 kb
Host smart-ad9b7403-9705-4bdb-8ea3-c0864d838f79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1497181035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1497181035
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1573146525
Short name T2818
Test name
Test status
Simulation time 176552470 ps
CPU time 1.94 seconds
Started Jul 15 06:12:59 PM PDT 24
Finished Jul 15 06:13:02 PM PDT 24
Peak memory 206620 kb
Host smart-966c5e69-aec4-4dc1-a494-7e58f46f1e07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1573146525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1573146525
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1847931140
Short name T2797
Test name
Test status
Simulation time 179969955 ps
CPU time 1.98 seconds
Started Jul 15 06:13:00 PM PDT 24
Finished Jul 15 06:13:03 PM PDT 24
Peak memory 214772 kb
Host smart-b9d664ab-cafa-4766-833c-a4547208c81f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847931140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1847931140
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3197373391
Short name T244
Test name
Test status
Simulation time 102456516 ps
CPU time 1.03 seconds
Started Jul 15 06:12:58 PM PDT 24
Finished Jul 15 06:13:00 PM PDT 24
Peak memory 206436 kb
Host smart-5b2d0775-47d1-444e-a954-372482cbc5ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3197373391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3197373391
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.980359329
Short name T265
Test name
Test status
Simulation time 122653948 ps
CPU time 0.7 seconds
Started Jul 15 06:12:58 PM PDT 24
Finished Jul 15 06:12:59 PM PDT 24
Peak memory 206320 kb
Host smart-56ea9080-7514-4c8f-a2fc-6d3b7f59fbc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=980359329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.980359329
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2528853380
Short name T2778
Test name
Test status
Simulation time 194872218 ps
CPU time 1.29 seconds
Started Jul 15 06:13:03 PM PDT 24
Finished Jul 15 06:13:04 PM PDT 24
Peak memory 206504 kb
Host smart-8d1bd6c9-d021-414f-a74b-b2276f05b62b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2528853380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2528853380
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2002342206
Short name T225
Test name
Test status
Simulation time 113099594 ps
CPU time 1.93 seconds
Started Jul 15 06:13:03 PM PDT 24
Finished Jul 15 06:13:06 PM PDT 24
Peak memory 214668 kb
Host smart-accf1b36-0207-461a-a6d8-b31677715b02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2002342206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2002342206
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1513612088
Short name T181
Test name
Test status
Simulation time 802152734 ps
CPU time 3.09 seconds
Started Jul 15 06:13:01 PM PDT 24
Finished Jul 15 06:13:05 PM PDT 24
Peak memory 206528 kb
Host smart-3e97a64d-7577-4ab8-8da9-6b4cbb564629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1513612088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1513612088
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2582070200
Short name T2850
Test name
Test status
Simulation time 157190845 ps
CPU time 3.16 seconds
Started Jul 15 06:12:13 PM PDT 24
Finished Jul 15 06:12:17 PM PDT 24
Peak memory 206484 kb
Host smart-cb8c7a15-e353-4135-a976-698927b1ff39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2582070200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2582070200
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1804311420
Short name T2824
Test name
Test status
Simulation time 307287829 ps
CPU time 4.18 seconds
Started Jul 15 06:12:04 PM PDT 24
Finished Jul 15 06:12:09 PM PDT 24
Peak memory 206412 kb
Host smart-b73de9ec-fe7e-40f2-aed3-32bdee7f7723
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1804311420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1804311420
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1560178913
Short name T238
Test name
Test status
Simulation time 189948591 ps
CPU time 0.92 seconds
Started Jul 15 06:12:04 PM PDT 24
Finished Jul 15 06:12:05 PM PDT 24
Peak memory 206284 kb
Host smart-74ca9736-5405-47f6-88e0-fbfa1e5daaf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1560178913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1560178913
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2239717078
Short name T2837
Test name
Test status
Simulation time 91549385 ps
CPU time 1.19 seconds
Started Jul 15 06:12:12 PM PDT 24
Finished Jul 15 06:12:14 PM PDT 24
Peak memory 214760 kb
Host smart-b7b5002a-72d4-4d6e-aa6d-b2f4d726f732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239717078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2239717078
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2980874392
Short name T2842
Test name
Test status
Simulation time 41318587 ps
CPU time 0.64 seconds
Started Jul 15 06:12:07 PM PDT 24
Finished Jul 15 06:12:08 PM PDT 24
Peak memory 206320 kb
Host smart-901cb846-737f-467f-bb20-c4aca53360aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2980874392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2980874392
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.167708634
Short name T237
Test name
Test status
Simulation time 127411197 ps
CPU time 1.48 seconds
Started Jul 15 06:12:03 PM PDT 24
Finished Jul 15 06:12:05 PM PDT 24
Peak memory 222804 kb
Host smart-44aee7ea-2f2a-449a-b33d-e73fc69b2c6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=167708634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.167708634
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3440984430
Short name T2750
Test name
Test status
Simulation time 370144505 ps
CPU time 2.65 seconds
Started Jul 15 06:12:04 PM PDT 24
Finished Jul 15 06:12:07 PM PDT 24
Peak memory 206396 kb
Host smart-66a94b5f-4b47-4313-b85f-ee10909eb9c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3440984430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3440984430
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.217230681
Short name T2834
Test name
Test status
Simulation time 195189957 ps
CPU time 1.74 seconds
Started Jul 15 06:12:13 PM PDT 24
Finished Jul 15 06:12:15 PM PDT 24
Peak memory 206552 kb
Host smart-6a5c4f2b-3be2-4983-9e17-93b80e7cccfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=217230681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.217230681
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1292783831
Short name T274
Test name
Test status
Simulation time 490621779 ps
CPU time 2.68 seconds
Started Jul 15 06:12:05 PM PDT 24
Finished Jul 15 06:12:08 PM PDT 24
Peak memory 206560 kb
Host smart-1cd8f405-8955-4696-922c-601c38de48fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1292783831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1292783831
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.627936644
Short name T2782
Test name
Test status
Simulation time 29745812 ps
CPU time 0.65 seconds
Started Jul 15 06:12:58 PM PDT 24
Finished Jul 15 06:12:59 PM PDT 24
Peak memory 206284 kb
Host smart-d89832ca-ac58-49d8-8d15-2ec44d5062c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=627936644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.627936644
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1190575551
Short name T270
Test name
Test status
Simulation time 31859345 ps
CPU time 0.66 seconds
Started Jul 15 06:13:02 PM PDT 24
Finished Jul 15 06:13:03 PM PDT 24
Peak memory 206268 kb
Host smart-5289f7ec-c106-4b82-800e-961f11f6f3c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1190575551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1190575551
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1170408479
Short name T2849
Test name
Test status
Simulation time 40037336 ps
CPU time 0.7 seconds
Started Jul 15 06:12:59 PM PDT 24
Finished Jul 15 06:13:00 PM PDT 24
Peak memory 206300 kb
Host smart-d0bdae80-5031-47d5-8bca-615dc8915032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1170408479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1170408479
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.126076410
Short name T2836
Test name
Test status
Simulation time 77857127 ps
CPU time 0.74 seconds
Started Jul 15 06:13:00 PM PDT 24
Finished Jul 15 06:13:01 PM PDT 24
Peak memory 206356 kb
Host smart-9405ba66-4592-4fcf-82fc-ca905b2717cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126076410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.126076410
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3305241746
Short name T2762
Test name
Test status
Simulation time 35561958 ps
CPU time 0.64 seconds
Started Jul 15 06:12:59 PM PDT 24
Finished Jul 15 06:13:00 PM PDT 24
Peak memory 206276 kb
Host smart-4e821e23-81bd-4e97-8b7c-7fe7a9b54a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3305241746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3305241746
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3024471983
Short name T2817
Test name
Test status
Simulation time 44184010 ps
CPU time 0.66 seconds
Started Jul 15 06:13:05 PM PDT 24
Finished Jul 15 06:13:06 PM PDT 24
Peak memory 206264 kb
Host smart-5a017cea-eaf9-4ca0-8317-6f88464463ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3024471983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3024471983
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2168963354
Short name T2769
Test name
Test status
Simulation time 54791525 ps
CPU time 0.83 seconds
Started Jul 15 06:13:02 PM PDT 24
Finished Jul 15 06:13:03 PM PDT 24
Peak memory 206272 kb
Host smart-7b82fbd8-def4-4776-ba2e-9167de3e4aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2168963354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2168963354
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4093030616
Short name T263
Test name
Test status
Simulation time 61451956 ps
CPU time 0.71 seconds
Started Jul 15 06:13:03 PM PDT 24
Finished Jul 15 06:13:04 PM PDT 24
Peak memory 206248 kb
Host smart-5b47d3b9-15f9-4162-bdf7-3c8da2996e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4093030616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.4093030616
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4186663590
Short name T248
Test name
Test status
Simulation time 370959423 ps
CPU time 3.53 seconds
Started Jul 15 06:12:14 PM PDT 24
Finished Jul 15 06:12:18 PM PDT 24
Peak memory 205932 kb
Host smart-b9b7c649-7912-44b3-accb-82b23fa5009c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4186663590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.4186663590
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3301473206
Short name T2829
Test name
Test status
Simulation time 661985140 ps
CPU time 6.95 seconds
Started Jul 15 06:12:12 PM PDT 24
Finished Jul 15 06:12:20 PM PDT 24
Peak memory 206424 kb
Host smart-2b16e3a5-1335-46ea-80f1-83f294a6a02b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3301473206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3301473206
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1400835661
Short name T260
Test name
Test status
Simulation time 101466787 ps
CPU time 0.92 seconds
Started Jul 15 06:12:13 PM PDT 24
Finished Jul 15 06:12:14 PM PDT 24
Peak memory 206304 kb
Host smart-e2fa1c2d-fd9c-4117-9b7d-efd2abf59b5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1400835661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1400835661
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3688964833
Short name T2787
Test name
Test status
Simulation time 128296060 ps
CPU time 1.99 seconds
Started Jul 15 06:12:14 PM PDT 24
Finished Jul 15 06:12:16 PM PDT 24
Peak memory 214820 kb
Host smart-9f0b2dfc-65fe-40a5-8528-d72cf1ceb4a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688964833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3688964833
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1844632489
Short name T2756
Test name
Test status
Simulation time 75076304 ps
CPU time 0.86 seconds
Started Jul 15 06:12:12 PM PDT 24
Finished Jul 15 06:12:13 PM PDT 24
Peak memory 206320 kb
Host smart-ba26ceba-7afc-44ec-8669-26a88d22265e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1844632489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1844632489
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4019177714
Short name T2822
Test name
Test status
Simulation time 56238703 ps
CPU time 0.69 seconds
Started Jul 15 06:12:12 PM PDT 24
Finished Jul 15 06:12:13 PM PDT 24
Peak memory 206300 kb
Host smart-2dafe83b-f680-4fe5-8567-f87c09e891ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4019177714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.4019177714
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1689512322
Short name T2800
Test name
Test status
Simulation time 270207005 ps
CPU time 2.5 seconds
Started Jul 15 06:12:15 PM PDT 24
Finished Jul 15 06:12:18 PM PDT 24
Peak memory 214608 kb
Host smart-3579fb7c-9736-4104-8d0e-c8cc9b78a6ab
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1689512322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1689512322
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.270558596
Short name T2843
Test name
Test status
Simulation time 158950235 ps
CPU time 4.06 seconds
Started Jul 15 06:12:12 PM PDT 24
Finished Jul 15 06:12:16 PM PDT 24
Peak memory 206332 kb
Host smart-59036cb6-c9c7-4142-b5bb-637df79fc12a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=270558596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.270558596
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4112742059
Short name T2764
Test name
Test status
Simulation time 137593568 ps
CPU time 1.55 seconds
Started Jul 15 06:12:14 PM PDT 24
Finished Jul 15 06:12:16 PM PDT 24
Peak memory 206232 kb
Host smart-07c804fa-7193-4199-a90e-727a7de8cb85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4112742059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.4112742059
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2094158120
Short name T222
Test name
Test status
Simulation time 244147672 ps
CPU time 2.68 seconds
Started Jul 15 06:12:14 PM PDT 24
Finished Jul 15 06:12:17 PM PDT 24
Peak memory 214812 kb
Host smart-588c534a-1f0f-4942-a47b-8ed7193c994d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2094158120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2094158120
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1069607781
Short name T2767
Test name
Test status
Simulation time 61490826 ps
CPU time 0.68 seconds
Started Jul 15 06:13:01 PM PDT 24
Finished Jul 15 06:13:02 PM PDT 24
Peak memory 206320 kb
Host smart-45ada101-3e30-4314-93f5-f662cb013d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1069607781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1069607781
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3987190086
Short name T2766
Test name
Test status
Simulation time 50290939 ps
CPU time 0.72 seconds
Started Jul 15 06:13:00 PM PDT 24
Finished Jul 15 06:13:02 PM PDT 24
Peak memory 206260 kb
Host smart-8079483b-113c-4a98-bf42-94fb2070c0f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3987190086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3987190086
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1737591967
Short name T192
Test name
Test status
Simulation time 69019314 ps
CPU time 0.73 seconds
Started Jul 15 06:13:03 PM PDT 24
Finished Jul 15 06:13:05 PM PDT 24
Peak memory 206248 kb
Host smart-969213d3-dce9-4403-9973-64b958dad3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1737591967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1737591967
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.246319166
Short name T271
Test name
Test status
Simulation time 50325378 ps
CPU time 0.68 seconds
Started Jul 15 06:13:02 PM PDT 24
Finished Jul 15 06:13:04 PM PDT 24
Peak memory 206328 kb
Host smart-7191b616-d018-4a8e-b59d-779bbfb0318b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=246319166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.246319166
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2995900342
Short name T2821
Test name
Test status
Simulation time 49862556 ps
CPU time 0.69 seconds
Started Jul 15 06:13:13 PM PDT 24
Finished Jul 15 06:13:14 PM PDT 24
Peak memory 206276 kb
Host smart-3d47ea83-fd59-48af-ae80-12cab55e0d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2995900342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2995900342
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1277638120
Short name T2777
Test name
Test status
Simulation time 43840975 ps
CPU time 0.65 seconds
Started Jul 15 06:13:13 PM PDT 24
Finished Jul 15 06:13:14 PM PDT 24
Peak memory 206256 kb
Host smart-f07add66-b186-4570-a361-83f08a673114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1277638120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1277638120
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3522151973
Short name T272
Test name
Test status
Simulation time 72406969 ps
CPU time 0.71 seconds
Started Jul 15 06:13:16 PM PDT 24
Finished Jul 15 06:13:17 PM PDT 24
Peak memory 206232 kb
Host smart-ff90a31a-2f4c-4ba5-87b1-75d12b596151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3522151973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3522151973
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1323962463
Short name T266
Test name
Test status
Simulation time 52365002 ps
CPU time 0.67 seconds
Started Jul 15 06:13:14 PM PDT 24
Finished Jul 15 06:13:15 PM PDT 24
Peak memory 206304 kb
Host smart-59e47739-0239-4d05-ae01-6af371133797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1323962463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1323962463
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2455688928
Short name T2803
Test name
Test status
Simulation time 41478581 ps
CPU time 0.68 seconds
Started Jul 15 06:13:14 PM PDT 24
Finished Jul 15 06:13:15 PM PDT 24
Peak memory 206312 kb
Host smart-97ed8218-5e7c-4bef-9559-809b743abeb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2455688928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2455688928
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.48588444
Short name T240
Test name
Test status
Simulation time 89319724 ps
CPU time 1.97 seconds
Started Jul 15 06:12:20 PM PDT 24
Finished Jul 15 06:12:22 PM PDT 24
Peak memory 206484 kb
Host smart-7b0477d4-5a3d-46c8-ab79-54bdcee6918b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=48588444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.48588444
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.541818564
Short name T2757
Test name
Test status
Simulation time 883256720 ps
CPU time 4.45 seconds
Started Jul 15 06:12:27 PM PDT 24
Finished Jul 15 06:12:32 PM PDT 24
Peak memory 206404 kb
Host smart-27d0eb3f-b9d4-457b-a64c-f8462e5d993f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=541818564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.541818564
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2530804878
Short name T2813
Test name
Test status
Simulation time 101686499 ps
CPU time 0.92 seconds
Started Jul 15 06:12:21 PM PDT 24
Finished Jul 15 06:12:23 PM PDT 24
Peak memory 206272 kb
Host smart-311c1013-1269-4a66-9115-829f4e83387f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2530804878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2530804878
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1672162967
Short name T2812
Test name
Test status
Simulation time 150083736 ps
CPU time 2.81 seconds
Started Jul 15 06:12:20 PM PDT 24
Finished Jul 15 06:12:23 PM PDT 24
Peak memory 214704 kb
Host smart-9c4cf919-d026-4c1d-b042-1cc1f9853fc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672162967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1672162967
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1597329354
Short name T2792
Test name
Test status
Simulation time 69650201 ps
CPU time 0.98 seconds
Started Jul 15 06:12:18 PM PDT 24
Finished Jul 15 06:12:19 PM PDT 24
Peak memory 206440 kb
Host smart-f642e61b-3843-495f-aecb-58b9c4db5cdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1597329354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1597329354
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.413517432
Short name T2788
Test name
Test status
Simulation time 46326594 ps
CPU time 0.67 seconds
Started Jul 15 06:12:20 PM PDT 24
Finished Jul 15 06:12:21 PM PDT 24
Peak memory 206268 kb
Host smart-92c53172-c989-41ac-bbc7-fa37274e88a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=413517432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.413517432
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.256161124
Short name T242
Test name
Test status
Simulation time 145214034 ps
CPU time 1.51 seconds
Started Jul 15 06:12:20 PM PDT 24
Finished Jul 15 06:12:21 PM PDT 24
Peak memory 214768 kb
Host smart-d1f65f8f-1e64-4bab-8905-4dbd69d95eef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=256161124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.256161124
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2018617631
Short name T2804
Test name
Test status
Simulation time 485412373 ps
CPU time 4.12 seconds
Started Jul 15 06:12:23 PM PDT 24
Finished Jul 15 06:12:28 PM PDT 24
Peak memory 206376 kb
Host smart-6856932c-c3a9-4ae5-8a98-36c4304d2ff5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2018617631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2018617631
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3345182861
Short name T184
Test name
Test status
Simulation time 208591139 ps
CPU time 1.7 seconds
Started Jul 15 06:12:23 PM PDT 24
Finished Jul 15 06:12:25 PM PDT 24
Peak memory 206548 kb
Host smart-d8ba818e-fed2-4070-aa1b-f6901d493bbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3345182861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3345182861
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.36655841
Short name T2796
Test name
Test status
Simulation time 75108297 ps
CPU time 1.62 seconds
Started Jul 15 06:12:23 PM PDT 24
Finished Jul 15 06:12:25 PM PDT 24
Peak memory 206628 kb
Host smart-07c550b0-b6ad-4caf-982c-34201de4f7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=36655841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.36655841
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2203922589
Short name T277
Test name
Test status
Simulation time 833804315 ps
CPU time 5.08 seconds
Started Jul 15 06:12:21 PM PDT 24
Finished Jul 15 06:12:27 PM PDT 24
Peak memory 206580 kb
Host smart-818df73c-adab-48f3-8ffb-829467da6fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2203922589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2203922589
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2993014516
Short name T2816
Test name
Test status
Simulation time 85732402 ps
CPU time 0.73 seconds
Started Jul 15 06:13:14 PM PDT 24
Finished Jul 15 06:13:15 PM PDT 24
Peak memory 206300 kb
Host smart-75f305a0-8944-454a-a236-0ed21992e528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2993014516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2993014516
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.416814517
Short name T2835
Test name
Test status
Simulation time 57469540 ps
CPU time 0.67 seconds
Started Jul 15 06:13:14 PM PDT 24
Finished Jul 15 06:13:15 PM PDT 24
Peak memory 206312 kb
Host smart-d1ed7998-d1fd-4d77-8797-738625558583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=416814517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.416814517
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1993577450
Short name T2758
Test name
Test status
Simulation time 37724948 ps
CPU time 0.63 seconds
Started Jul 15 06:13:14 PM PDT 24
Finished Jul 15 06:13:15 PM PDT 24
Peak memory 206312 kb
Host smart-b4d6bfe1-8ae0-4817-ac65-9e1b6830e29d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1993577450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1993577450
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3019971248
Short name T2814
Test name
Test status
Simulation time 52752322 ps
CPU time 0.71 seconds
Started Jul 15 06:13:14 PM PDT 24
Finished Jul 15 06:13:16 PM PDT 24
Peak memory 206312 kb
Host smart-4745c9f8-d318-432c-a3fb-2ac4df9544a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3019971248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3019971248
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1690349232
Short name T2820
Test name
Test status
Simulation time 85006478 ps
CPU time 0.7 seconds
Started Jul 15 06:13:14 PM PDT 24
Finished Jul 15 06:13:15 PM PDT 24
Peak memory 206340 kb
Host smart-9de4e66d-c0d3-4db1-a886-1b042f0e5768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1690349232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1690349232
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4190066416
Short name T2848
Test name
Test status
Simulation time 46399888 ps
CPU time 0.66 seconds
Started Jul 15 06:13:13 PM PDT 24
Finished Jul 15 06:13:14 PM PDT 24
Peak memory 206312 kb
Host smart-b3f51e49-79a4-4294-8016-75f5f6ed10ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4190066416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.4190066416
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3474680252
Short name T2840
Test name
Test status
Simulation time 47613747 ps
CPU time 0.65 seconds
Started Jul 15 06:13:15 PM PDT 24
Finished Jul 15 06:13:16 PM PDT 24
Peak memory 206272 kb
Host smart-4233a862-b139-48dd-aab2-4dc2bb2cbf9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3474680252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3474680252
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3160562481
Short name T2789
Test name
Test status
Simulation time 88218879 ps
CPU time 0.74 seconds
Started Jul 15 06:13:17 PM PDT 24
Finished Jul 15 06:13:18 PM PDT 24
Peak memory 206320 kb
Host smart-0d046a6d-75a6-4737-8013-ed3a29150729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3160562481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3160562481
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3188561054
Short name T2752
Test name
Test status
Simulation time 74036602 ps
CPU time 0.71 seconds
Started Jul 15 06:13:17 PM PDT 24
Finished Jul 15 06:13:19 PM PDT 24
Peak memory 206304 kb
Host smart-33efa522-0b63-4f58-9046-dfe63bc3d4e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3188561054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3188561054
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2969844074
Short name T2853
Test name
Test status
Simulation time 49130866 ps
CPU time 0.68 seconds
Started Jul 15 06:13:17 PM PDT 24
Finished Jul 15 06:13:18 PM PDT 24
Peak memory 206312 kb
Host smart-01f99570-929e-4c1d-aa3c-b9a04b184277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2969844074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2969844074
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3132113895
Short name T2847
Test name
Test status
Simulation time 254153501 ps
CPU time 1.64 seconds
Started Jul 15 06:12:29 PM PDT 24
Finished Jul 15 06:12:31 PM PDT 24
Peak memory 214820 kb
Host smart-29a5937b-f94f-4c82-8a5a-6345ef165f7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132113895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.3132113895
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3780479166
Short name T2765
Test name
Test status
Simulation time 65577028 ps
CPU time 0.71 seconds
Started Jul 15 06:12:20 PM PDT 24
Finished Jul 15 06:12:21 PM PDT 24
Peak memory 206280 kb
Host smart-b2c0f76b-98ab-469c-97f7-2300b164a9f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3780479166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3780479166
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1458452979
Short name T2794
Test name
Test status
Simulation time 70692915 ps
CPU time 1.03 seconds
Started Jul 15 06:12:22 PM PDT 24
Finished Jul 15 06:12:23 PM PDT 24
Peak memory 206548 kb
Host smart-73590a10-0c11-4ad6-8e2d-27dc9ea426ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1458452979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1458452979
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2718410236
Short name T226
Test name
Test status
Simulation time 134980272 ps
CPU time 1.72 seconds
Started Jul 15 06:12:23 PM PDT 24
Finished Jul 15 06:12:25 PM PDT 24
Peak memory 222028 kb
Host smart-5c803708-0fa2-42c6-a5c7-91c989c848fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2718410236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2718410236
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1474824689
Short name T273
Test name
Test status
Simulation time 414893599 ps
CPU time 2.95 seconds
Started Jul 15 06:12:22 PM PDT 24
Finished Jul 15 06:12:25 PM PDT 24
Peak memory 206456 kb
Host smart-d478fd0c-9430-40e0-b053-00f30589f546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1474824689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1474824689
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3031225849
Short name T2802
Test name
Test status
Simulation time 77633706 ps
CPU time 1.58 seconds
Started Jul 15 06:12:31 PM PDT 24
Finished Jul 15 06:12:33 PM PDT 24
Peak memory 214756 kb
Host smart-6fc5004b-9ed0-4204-8891-80da2de628b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031225849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3031225849
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2495945085
Short name T2832
Test name
Test status
Simulation time 76640501 ps
CPU time 1.02 seconds
Started Jul 15 06:12:28 PM PDT 24
Finished Jul 15 06:12:29 PM PDT 24
Peak memory 206420 kb
Host smart-6672c809-eecc-4a3d-a76f-683eed012649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2495945085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2495945085
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2622480165
Short name T2793
Test name
Test status
Simulation time 37184317 ps
CPU time 0.63 seconds
Started Jul 15 06:12:27 PM PDT 24
Finished Jul 15 06:12:28 PM PDT 24
Peak memory 206292 kb
Host smart-8a9494c3-a73f-436e-811a-7c240002c5e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2622480165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2622480165
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3248382323
Short name T256
Test name
Test status
Simulation time 234793068 ps
CPU time 1.64 seconds
Started Jul 15 06:12:26 PM PDT 24
Finished Jul 15 06:12:28 PM PDT 24
Peak memory 206468 kb
Host smart-22a2c982-98f2-419b-9fdf-8c37a6c7a07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3248382323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3248382323
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1633095143
Short name T2828
Test name
Test status
Simulation time 97554140 ps
CPU time 2.74 seconds
Started Jul 15 06:12:27 PM PDT 24
Finished Jul 15 06:12:30 PM PDT 24
Peak memory 222312 kb
Host smart-57583583-12ee-4d27-909e-51aa32d5c83c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1633095143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1633095143
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.506258445
Short name T276
Test name
Test status
Simulation time 370728235 ps
CPU time 2.4 seconds
Started Jul 15 06:12:26 PM PDT 24
Finished Jul 15 06:12:29 PM PDT 24
Peak memory 206448 kb
Host smart-c4460f5d-4c95-40bb-a11f-46539d0f607b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=506258445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.506258445
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1341995067
Short name T2775
Test name
Test status
Simulation time 159489963 ps
CPU time 1.2 seconds
Started Jul 15 06:12:28 PM PDT 24
Finished Jul 15 06:12:29 PM PDT 24
Peak memory 214720 kb
Host smart-67670aa1-9cfe-4505-9a79-0637cb958901
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341995067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1341995067
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.363713701
Short name T252
Test name
Test status
Simulation time 53795825 ps
CPU time 0.86 seconds
Started Jul 15 06:12:25 PM PDT 24
Finished Jul 15 06:12:27 PM PDT 24
Peak memory 206356 kb
Host smart-a4c1d56f-7fe5-4a3a-97a6-e87f433dcf54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=363713701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.363713701
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4138324529
Short name T264
Test name
Test status
Simulation time 52164872 ps
CPU time 0.67 seconds
Started Jul 15 06:12:28 PM PDT 24
Finished Jul 15 06:12:30 PM PDT 24
Peak memory 206284 kb
Host smart-f47916b7-5ba5-4c2f-b9d1-677e2b14a7e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4138324529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4138324529
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.189971319
Short name T254
Test name
Test status
Simulation time 57751094 ps
CPU time 1.08 seconds
Started Jul 15 06:12:31 PM PDT 24
Finished Jul 15 06:12:33 PM PDT 24
Peak memory 206492 kb
Host smart-6f822cdc-7fba-4fe2-b0ad-848395231782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=189971319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.189971319
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1980462280
Short name T2776
Test name
Test status
Simulation time 120476898 ps
CPU time 2.88 seconds
Started Jul 15 06:12:25 PM PDT 24
Finished Jul 15 06:12:29 PM PDT 24
Peak memory 214896 kb
Host smart-b7307dfb-7bdf-4068-bd0f-b5d3eefef143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1980462280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1980462280
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3111872495
Short name T2846
Test name
Test status
Simulation time 524387666 ps
CPU time 2.84 seconds
Started Jul 15 06:12:26 PM PDT 24
Finished Jul 15 06:12:29 PM PDT 24
Peak memory 206412 kb
Host smart-3de68b00-a8fe-443e-ba10-8c31f510a549
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3111872495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3111872495
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2173386709
Short name T2759
Test name
Test status
Simulation time 94935888 ps
CPU time 1.19 seconds
Started Jul 15 06:12:36 PM PDT 24
Finished Jul 15 06:12:38 PM PDT 24
Peak memory 214756 kb
Host smart-6a17c9ef-54bd-4192-ad45-a30471848bf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173386709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2173386709
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2456555056
Short name T2783
Test name
Test status
Simulation time 56424055 ps
CPU time 0.79 seconds
Started Jul 15 06:12:27 PM PDT 24
Finished Jul 15 06:12:28 PM PDT 24
Peak memory 206332 kb
Host smart-30099ec3-ea54-4a49-b8d8-1c5458b80aa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2456555056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2456555056
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3670687831
Short name T2808
Test name
Test status
Simulation time 45160642 ps
CPU time 0.69 seconds
Started Jul 15 06:12:26 PM PDT 24
Finished Jul 15 06:12:27 PM PDT 24
Peak memory 206240 kb
Host smart-bbb64fc3-e033-4200-82d4-689ad0411cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3670687831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3670687831
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.502960086
Short name T2755
Test name
Test status
Simulation time 224543211 ps
CPU time 1.77 seconds
Started Jul 15 06:12:27 PM PDT 24
Finished Jul 15 06:12:29 PM PDT 24
Peak memory 206544 kb
Host smart-59c5eafa-7806-4a15-8809-f3984ec186f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=502960086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.502960086
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3868988256
Short name T2805
Test name
Test status
Simulation time 65565714 ps
CPU time 1.32 seconds
Started Jul 15 06:12:26 PM PDT 24
Finished Jul 15 06:12:28 PM PDT 24
Peak memory 214724 kb
Host smart-2c9f6c5d-2585-4072-b3c7-e8da2dde104c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3868988256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3868988256
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1188470719
Short name T280
Test name
Test status
Simulation time 691311427 ps
CPU time 3.48 seconds
Started Jul 15 06:12:28 PM PDT 24
Finished Jul 15 06:12:32 PM PDT 24
Peak memory 206480 kb
Host smart-60a71d32-9ea5-4a53-8f46-0ede742c93e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1188470719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1188470719
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1786369738
Short name T2770
Test name
Test status
Simulation time 93429613 ps
CPU time 1.21 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:36 PM PDT 24
Peak memory 214760 kb
Host smart-58ab8607-8e2c-4aec-a13d-49c96693f0cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786369738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1786369738
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.362301600
Short name T2819
Test name
Test status
Simulation time 58181060 ps
CPU time 0.79 seconds
Started Jul 15 06:12:33 PM PDT 24
Finished Jul 15 06:12:35 PM PDT 24
Peak memory 206320 kb
Host smart-9af08de8-3852-4437-9c58-b2751764f8d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=362301600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.362301600
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2303809426
Short name T2810
Test name
Test status
Simulation time 87274390 ps
CPU time 0.71 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:36 PM PDT 24
Peak memory 206308 kb
Host smart-36abda21-e890-4c87-8feb-122491da1f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2303809426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2303809426
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2587336102
Short name T2772
Test name
Test status
Simulation time 211033552 ps
CPU time 1.18 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:35 PM PDT 24
Peak memory 206508 kb
Host smart-8c47b2f4-65d4-4637-bdc9-941c9385ec07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2587336102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2587336102
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2435736253
Short name T224
Test name
Test status
Simulation time 245700847 ps
CPU time 2.62 seconds
Started Jul 15 06:12:33 PM PDT 24
Finished Jul 15 06:12:36 PM PDT 24
Peak memory 206620 kb
Host smart-627294b9-5cfe-4bae-90da-bb0f8b8b4dea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2435736253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2435736253
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3638351259
Short name T279
Test name
Test status
Simulation time 711741646 ps
CPU time 4.41 seconds
Started Jul 15 06:12:34 PM PDT 24
Finished Jul 15 06:12:39 PM PDT 24
Peak memory 206488 kb
Host smart-ea044dd4-440e-46cd-8148-380606b91750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3638351259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3638351259
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.236513061
Short name T1660
Test name
Test status
Simulation time 3705905639 ps
CPU time 4.14 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:30 PM PDT 24
Peak memory 206868 kb
Host smart-33c0a644-a86f-44ae-9a21-11758567df1b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=236513061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.236513061
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1802449366
Short name T1379
Test name
Test status
Simulation time 13393426354 ps
CPU time 14.45 seconds
Started Jul 15 07:02:25 PM PDT 24
Finished Jul 15 07:02:40 PM PDT 24
Peak memory 206868 kb
Host smart-f16ab1f0-7b57-4353-b874-2e32f424ad35
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1802449366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1802449366
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.965649843
Short name T951
Test name
Test status
Simulation time 23358020024 ps
CPU time 26.84 seconds
Started Jul 15 07:02:31 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 207008 kb
Host smart-9c4ac8bc-55ac-4267-aa2e-38489ca3c8bd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=965649843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.965649843
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3466327346
Short name T1034
Test name
Test status
Simulation time 200870121 ps
CPU time 0.81 seconds
Started Jul 15 07:02:32 PM PDT 24
Finished Jul 15 07:02:34 PM PDT 24
Peak memory 206804 kb
Host smart-51972a2b-3431-460a-a850-f3e33f44d4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34663
27346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3466327346
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2186309962
Short name T2705
Test name
Test status
Simulation time 145539030 ps
CPU time 0.74 seconds
Started Jul 15 07:02:37 PM PDT 24
Finished Jul 15 07:02:38 PM PDT 24
Peak memory 206812 kb
Host smart-d6542df7-47a1-44c5-afb5-651521409fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21863
09962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2186309962
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.399278870
Short name T1826
Test name
Test status
Simulation time 277976633 ps
CPU time 1.04 seconds
Started Jul 15 07:02:29 PM PDT 24
Finished Jul 15 07:02:30 PM PDT 24
Peak memory 206832 kb
Host smart-2d06ef57-b3b1-4a14-a7a8-c4d9418cffab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
8870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.399278870
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2180720572
Short name T98
Test name
Test status
Simulation time 1165143097 ps
CPU time 2.67 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:02:34 PM PDT 24
Peak memory 206996 kb
Host smart-907dac1d-d743-4f03-be67-c3cb76636570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21807
20572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2180720572
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2005726942
Short name T2312
Test name
Test status
Simulation time 6032652070 ps
CPU time 11.87 seconds
Started Jul 15 07:02:31 PM PDT 24
Finished Jul 15 07:02:44 PM PDT 24
Peak memory 207072 kb
Host smart-b9a65f03-3d7f-4a96-92b7-cb853f6b5f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20057
26942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2005726942
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3660154774
Short name T1062
Test name
Test status
Simulation time 430072739 ps
CPU time 1.18 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:02:32 PM PDT 24
Peak memory 206812 kb
Host smart-b1a6b469-5e06-4777-975b-e002908074ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36601
54774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3660154774
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3056202845
Short name T1161
Test name
Test status
Simulation time 165669282 ps
CPU time 0.8 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:02:31 PM PDT 24
Peak memory 206840 kb
Host smart-fb58c9ec-6863-4073-aa67-b9d815af0d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30562
02845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3056202845
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2724306426
Short name T1396
Test name
Test status
Simulation time 5111986566 ps
CPU time 134.74 seconds
Started Jul 15 07:02:31 PM PDT 24
Finished Jul 15 07:04:46 PM PDT 24
Peak memory 207184 kb
Host smart-4d0ed354-f2da-4408-be57-110e34ba69eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
06426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2724306426
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.3185138442
Short name T1213
Test name
Test status
Simulation time 51258764 ps
CPU time 0.66 seconds
Started Jul 15 07:02:38 PM PDT 24
Finished Jul 15 07:02:39 PM PDT 24
Peak memory 206836 kb
Host smart-5796f673-777a-4828-9a5f-e7e1125417d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31851
38442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3185138442
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3527953915
Short name T1481
Test name
Test status
Simulation time 949825293 ps
CPU time 2.34 seconds
Started Jul 15 07:02:32 PM PDT 24
Finished Jul 15 07:02:35 PM PDT 24
Peak memory 206984 kb
Host smart-0f777f0a-79e1-45fe-8c03-d48d4d5b3326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35279
53915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3527953915
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2952958490
Short name T2346
Test name
Test status
Simulation time 255004585 ps
CPU time 1.83 seconds
Started Jul 15 07:02:33 PM PDT 24
Finished Jul 15 07:02:35 PM PDT 24
Peak memory 207012 kb
Host smart-6aed2e42-3a70-418c-91dc-2df379865126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29529
58490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2952958490
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.1088066333
Short name T1994
Test name
Test status
Simulation time 109187385283 ps
CPU time 138.41 seconds
Started Jul 15 07:02:33 PM PDT 24
Finished Jul 15 07:04:52 PM PDT 24
Peak memory 206996 kb
Host smart-d7d2bcef-9bc7-418e-a88e-03a2f329934c
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1088066333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.1088066333
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2159993585
Short name T1119
Test name
Test status
Simulation time 87197643968 ps
CPU time 118.23 seconds
Started Jul 15 07:02:32 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 207028 kb
Host smart-67469595-537c-4bc7-aa86-559710b2b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159993585 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2159993585
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1599863650
Short name T2534
Test name
Test status
Simulation time 100104139322 ps
CPU time 137.6 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:04:48 PM PDT 24
Peak memory 207036 kb
Host smart-aa74fa1e-6ace-4616-99d5-359b5dcdf27d
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1599863650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1599863650
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.2020405407
Short name T375
Test name
Test status
Simulation time 85261069851 ps
CPU time 119.07 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:04:37 PM PDT 24
Peak memory 207004 kb
Host smart-6adf6be1-5764-40b5-9a3d-49de51ea46c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020405407 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2020405407
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.86733010
Short name T1486
Test name
Test status
Simulation time 91155998010 ps
CPU time 116.46 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:04:27 PM PDT 24
Peak memory 206964 kb
Host smart-ccc6a02a-683d-460f-816a-cc6e954b7559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86733
010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.86733010
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2868271446
Short name T2663
Test name
Test status
Simulation time 203790737 ps
CPU time 0.85 seconds
Started Jul 15 07:02:38 PM PDT 24
Finished Jul 15 07:02:40 PM PDT 24
Peak memory 206840 kb
Host smart-db2412b0-f737-43aa-b201-2f5ca9bf4b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28682
71446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2868271446
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.507113255
Short name T1113
Test name
Test status
Simulation time 172409498 ps
CPU time 0.8 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:02:38 PM PDT 24
Peak memory 206808 kb
Host smart-27ed1b3b-c1be-423a-b94d-cb35755dd0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50711
3255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.507113255
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2912298856
Short name T1491
Test name
Test status
Simulation time 273485759 ps
CPU time 0.96 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:02:32 PM PDT 24
Peak memory 206800 kb
Host smart-484d2b83-ef3a-43a4-b34b-ae70f7da890b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29122
98856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2912298856
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.2979235677
Short name T593
Test name
Test status
Simulation time 6131811412 ps
CPU time 59.97 seconds
Started Jul 15 07:02:31 PM PDT 24
Finished Jul 15 07:03:32 PM PDT 24
Peak memory 207072 kb
Host smart-b73b087d-bc8c-4b3f-a435-a8da151612d3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2979235677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.2979235677
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1334118408
Short name T1933
Test name
Test status
Simulation time 12276055597 ps
CPU time 42 seconds
Started Jul 15 07:02:31 PM PDT 24
Finished Jul 15 07:03:14 PM PDT 24
Peak memory 207012 kb
Host smart-54131f98-9211-4a64-a2bd-b1368b52b1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13341
18408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1334118408
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3633928345
Short name T2226
Test name
Test status
Simulation time 242848633 ps
CPU time 0.93 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:02:32 PM PDT 24
Peak memory 206824 kb
Host smart-51e1da96-a8fa-4a6b-aa37-2609ce8735cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36339
28345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3633928345
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1207738238
Short name T64
Test name
Test status
Simulation time 425706404 ps
CPU time 1.24 seconds
Started Jul 15 07:02:38 PM PDT 24
Finished Jul 15 07:02:39 PM PDT 24
Peak memory 206840 kb
Host smart-75f36581-d47c-474a-b1fb-d08c4c68e85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
38238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1207738238
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2762250880
Short name T743
Test name
Test status
Simulation time 23281349562 ps
CPU time 25.85 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:03:03 PM PDT 24
Peak memory 206836 kb
Host smart-d5c24e77-06e9-4cf6-8937-1a983b05bf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27622
50880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2762250880
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.825026632
Short name T2610
Test name
Test status
Simulation time 3329737625 ps
CPU time 3.99 seconds
Started Jul 15 07:02:39 PM PDT 24
Finished Jul 15 07:02:43 PM PDT 24
Peak memory 206904 kb
Host smart-63dcc35a-8511-4a88-8022-87657fe406ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82502
6632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.825026632
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3203841438
Short name T2488
Test name
Test status
Simulation time 8309511182 ps
CPU time 81.87 seconds
Started Jul 15 07:02:32 PM PDT 24
Finished Jul 15 07:03:54 PM PDT 24
Peak memory 207084 kb
Host smart-ee11b894-6e3c-4ec7-800c-4d608824ac66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32038
41438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3203841438
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.919664289
Short name T2132
Test name
Test status
Simulation time 4197232784 ps
CPU time 41.36 seconds
Started Jul 15 07:02:30 PM PDT 24
Finished Jul 15 07:03:12 PM PDT 24
Peak memory 207016 kb
Host smart-3fbea234-84b9-4596-938e-8626873798b0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=919664289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.919664289
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.4278750952
Short name T335
Test name
Test status
Simulation time 237504432 ps
CPU time 0.98 seconds
Started Jul 15 07:02:33 PM PDT 24
Finished Jul 15 07:02:35 PM PDT 24
Peak memory 206796 kb
Host smart-73df965e-12dc-46a5-b3c0-d720d2b72541
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4278750952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.4278750952
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2100753526
Short name T547
Test name
Test status
Simulation time 186617747 ps
CPU time 0.84 seconds
Started Jul 15 07:02:34 PM PDT 24
Finished Jul 15 07:02:36 PM PDT 24
Peak memory 206792 kb
Host smart-ba116934-cd84-4b0b-b688-48085de9b655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21007
53526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2100753526
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2892991747
Short name T2219
Test name
Test status
Simulation time 3493000928 ps
CPU time 24.35 seconds
Started Jul 15 07:02:33 PM PDT 24
Finished Jul 15 07:02:58 PM PDT 24
Peak memory 207000 kb
Host smart-358f13cb-e612-4627-96f2-7006f08c9302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28929
91747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2892991747
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3176704306
Short name T1167
Test name
Test status
Simulation time 5198179204 ps
CPU time 47.61 seconds
Started Jul 15 07:02:38 PM PDT 24
Finished Jul 15 07:03:27 PM PDT 24
Peak memory 207040 kb
Host smart-ad03e7cf-e8d9-4b25-a370-142ffc752983
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3176704306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3176704306
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.270726790
Short name T2171
Test name
Test status
Simulation time 164230706 ps
CPU time 0.82 seconds
Started Jul 15 07:02:34 PM PDT 24
Finished Jul 15 07:02:36 PM PDT 24
Peak memory 206780 kb
Host smart-fed0c096-1a24-464f-9008-d9401532f591
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=270726790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.270726790
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3797449960
Short name T3
Test name
Test status
Simulation time 160221882 ps
CPU time 0.82 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:02:38 PM PDT 24
Peak memory 206808 kb
Host smart-b1abb8cf-8905-43dc-8b1e-9b05af0ab4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37974
49960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3797449960
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1042288297
Short name T62
Test name
Test status
Simulation time 427951095 ps
CPU time 1.23 seconds
Started Jul 15 07:02:35 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 206800 kb
Host smart-de36837f-cb21-452b-bd1e-df92c9ce6b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10422
88297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1042288297
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.787735661
Short name T1706
Test name
Test status
Simulation time 163844220 ps
CPU time 0.81 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 206816 kb
Host smart-457348fb-b308-4d96-aa3b-e467ec0c84e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78773
5661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.787735661
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.4146504427
Short name T1029
Test name
Test status
Simulation time 198493121 ps
CPU time 0.78 seconds
Started Jul 15 07:02:37 PM PDT 24
Finished Jul 15 07:02:39 PM PDT 24
Peak memory 206836 kb
Host smart-fe3fbfae-927a-4c11-a0c1-47022b67dcb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41465
04427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.4146504427
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1180622231
Short name T1220
Test name
Test status
Simulation time 160877115 ps
CPU time 0.8 seconds
Started Jul 15 07:02:38 PM PDT 24
Finished Jul 15 07:02:39 PM PDT 24
Peak memory 206812 kb
Host smart-a5cf7e54-97a0-4e6f-9000-e5b51904205e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11806
22231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1180622231
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1284108685
Short name T971
Test name
Test status
Simulation time 210376269 ps
CPU time 0.84 seconds
Started Jul 15 07:02:35 PM PDT 24
Finished Jul 15 07:02:36 PM PDT 24
Peak memory 206760 kb
Host smart-4fa65eca-9c48-4568-8f90-85c716cceed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841
08685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1284108685
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1674593018
Short name T1054
Test name
Test status
Simulation time 236264069 ps
CPU time 0.87 seconds
Started Jul 15 07:02:35 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 206828 kb
Host smart-ecbe8ee2-ad2d-4433-9d98-14de703d25e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16745
93018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1674593018
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2669998316
Short name T1855
Test name
Test status
Simulation time 306151054 ps
CPU time 0.99 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 206840 kb
Host smart-b8eb93e4-8c15-4803-9765-a3f57964da53
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2669998316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2669998316
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1870610535
Short name T2600
Test name
Test status
Simulation time 251814354 ps
CPU time 1.03 seconds
Started Jul 15 07:02:37 PM PDT 24
Finished Jul 15 07:02:39 PM PDT 24
Peak memory 206832 kb
Host smart-d9045b49-098e-49db-9d65-3458bee75269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18706
10535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1870610535
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1846125361
Short name T185
Test name
Test status
Simulation time 254659938 ps
CPU time 0.98 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 206772 kb
Host smart-202b31ae-7dc6-46a0-ad89-099c1e4ad890
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1846125361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1846125361
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2352952860
Short name T1646
Test name
Test status
Simulation time 144875672 ps
CPU time 0.74 seconds
Started Jul 15 07:02:35 PM PDT 24
Finished Jul 15 07:02:36 PM PDT 24
Peak memory 206820 kb
Host smart-69b67d47-117e-4370-befc-573a152c1d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23529
52860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2352952860
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2690360367
Short name T877
Test name
Test status
Simulation time 9342934607 ps
CPU time 22.82 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:03:00 PM PDT 24
Peak memory 207124 kb
Host smart-dc2b0532-708c-41e7-ac66-296649a17a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26903
60367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2690360367
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1548274991
Short name T562
Test name
Test status
Simulation time 169460102 ps
CPU time 0.76 seconds
Started Jul 15 07:02:34 PM PDT 24
Finished Jul 15 07:02:35 PM PDT 24
Peak memory 206812 kb
Host smart-fadec81e-6fd0-4967-9a6b-6f0ad4c83a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15482
74991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1548274991
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2150066618
Short name T1330
Test name
Test status
Simulation time 177988940 ps
CPU time 0.83 seconds
Started Jul 15 07:02:35 PM PDT 24
Finished Jul 15 07:02:37 PM PDT 24
Peak memory 206816 kb
Host smart-5a19ab4c-2eed-40f1-88fc-9d4b2633088f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21500
66618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2150066618
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.491724769
Short name T2491
Test name
Test status
Simulation time 5363120664 ps
CPU time 41.25 seconds
Started Jul 15 07:02:35 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 207128 kb
Host smart-857c4dce-ca2e-4cbb-a9d0-367e7cf31727
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=491724769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.491724769
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3599076423
Short name T2315
Test name
Test status
Simulation time 12363404242 ps
CPU time 83.15 seconds
Started Jul 15 07:02:42 PM PDT 24
Finished Jul 15 07:04:05 PM PDT 24
Peak memory 207000 kb
Host smart-c5357c8d-d10f-4f53-84ac-0a6269d2b555
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3599076423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3599076423
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.266211228
Short name T422
Test name
Test status
Simulation time 268992030 ps
CPU time 0.94 seconds
Started Jul 15 07:02:36 PM PDT 24
Finished Jul 15 07:02:38 PM PDT 24
Peak memory 206792 kb
Host smart-f2e4de37-5e71-4f5a-8c43-dcfb2bb39cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26621
1228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.266211228
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1394538068
Short name T2549
Test name
Test status
Simulation time 171723248 ps
CPU time 0.86 seconds
Started Jul 15 07:02:35 PM PDT 24
Finished Jul 15 07:02:36 PM PDT 24
Peak memory 206804 kb
Host smart-dd3145a4-1cda-4517-af46-8ccd8a235b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13945
38068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1394538068
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.892084075
Short name T195
Test name
Test status
Simulation time 227390752 ps
CPU time 1.03 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:02:51 PM PDT 24
Peak memory 224476 kb
Host smart-d905de39-1d12-4b19-a5c0-b2f0479e5474
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=892084075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.892084075
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3389652527
Short name T1445
Test name
Test status
Simulation time 143112644 ps
CPU time 0.78 seconds
Started Jul 15 07:02:40 PM PDT 24
Finished Jul 15 07:02:41 PM PDT 24
Peak memory 206788 kb
Host smart-1781a565-2a05-4a75-ad19-a02204a88988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33896
52527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3389652527
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.182215752
Short name T1291
Test name
Test status
Simulation time 176960704 ps
CPU time 0.82 seconds
Started Jul 15 07:02:41 PM PDT 24
Finished Jul 15 07:02:42 PM PDT 24
Peak memory 206844 kb
Host smart-e5dab3cb-bd3d-42c9-ab46-0a5a36001fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18221
5752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.182215752
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3720946841
Short name T626
Test name
Test status
Simulation time 253721889 ps
CPU time 0.97 seconds
Started Jul 15 07:02:45 PM PDT 24
Finished Jul 15 07:02:46 PM PDT 24
Peak memory 206840 kb
Host smart-b9d80ee9-27f8-4675-bf90-8d1661452e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37209
46841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3720946841
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3209813676
Short name T2046
Test name
Test status
Simulation time 6486535837 ps
CPU time 63.71 seconds
Started Jul 15 07:02:42 PM PDT 24
Finished Jul 15 07:03:46 PM PDT 24
Peak memory 207124 kb
Host smart-1e51d00e-bb84-4602-9078-792074e1f210
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3209813676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3209813676
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1805614268
Short name T1986
Test name
Test status
Simulation time 163298179 ps
CPU time 0.8 seconds
Started Jul 15 07:02:43 PM PDT 24
Finished Jul 15 07:02:44 PM PDT 24
Peak memory 206828 kb
Host smart-45d24016-091c-40e9-8dd3-fd1bf48eb80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
14268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1805614268
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3694182043
Short name T1031
Test name
Test status
Simulation time 182243221 ps
CPU time 0.82 seconds
Started Jul 15 07:02:45 PM PDT 24
Finished Jul 15 07:02:46 PM PDT 24
Peak memory 206824 kb
Host smart-f2a87276-3d19-4e28-b5f0-f38b3ecc43a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941
82043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3694182043
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1420124622
Short name T2125
Test name
Test status
Simulation time 1324912398 ps
CPU time 2.71 seconds
Started Jul 15 07:02:44 PM PDT 24
Finished Jul 15 07:02:47 PM PDT 24
Peak memory 206972 kb
Host smart-913d7d83-784a-4d92-a4fb-42fe7e11426e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14201
24622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1420124622
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.4006669164
Short name T619
Test name
Test status
Simulation time 6581122333 ps
CPU time 45.41 seconds
Started Jul 15 07:02:42 PM PDT 24
Finished Jul 15 07:03:28 PM PDT 24
Peak memory 206956 kb
Host smart-c4219b2f-326b-4336-b7b2-9c86233d720e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066
69164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.4006669164
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3160302503
Short name T153
Test name
Test status
Simulation time 10974251483 ps
CPU time 70.54 seconds
Started Jul 15 07:02:44 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 207004 kb
Host smart-7d4f596c-446c-47d2-978f-8b88250de520
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3160302503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3160302503
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1281569024
Short name T1368
Test name
Test status
Simulation time 88983233 ps
CPU time 0.69 seconds
Started Jul 15 07:02:55 PM PDT 24
Finished Jul 15 07:02:57 PM PDT 24
Peak memory 206860 kb
Host smart-dc0d9aba-eb89-4b1a-a326-46e2a6a0145a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1281569024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1281569024
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2684832364
Short name T770
Test name
Test status
Simulation time 4094695198 ps
CPU time 4.87 seconds
Started Jul 15 07:02:47 PM PDT 24
Finished Jul 15 07:02:52 PM PDT 24
Peak memory 206856 kb
Host smart-7e2c6eb4-346f-45e5-b93e-384f9d0a219e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2684832364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.2684832364
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3838982401
Short name T894
Test name
Test status
Simulation time 13314665249 ps
CPU time 12.36 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:03:03 PM PDT 24
Peak memory 207016 kb
Host smart-7449ac6b-43b3-4489-b9bc-10a4834cfc9e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3838982401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3838982401
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.176719482
Short name T2142
Test name
Test status
Simulation time 23329095321 ps
CPU time 23.99 seconds
Started Jul 15 07:02:48 PM PDT 24
Finished Jul 15 07:03:13 PM PDT 24
Peak memory 206744 kb
Host smart-ad8c0056-4d45-44fd-8db5-731cc79117ef
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=176719482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.176719482
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1219045589
Short name T397
Test name
Test status
Simulation time 152456962 ps
CPU time 0.82 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:02:54 PM PDT 24
Peak memory 206784 kb
Host smart-0a62cc6f-4aa6-48b2-815b-3cf2d4306236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12190
45589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1219045589
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2201966539
Short name T51
Test name
Test status
Simulation time 152769983 ps
CPU time 0.77 seconds
Started Jul 15 07:02:45 PM PDT 24
Finished Jul 15 07:02:46 PM PDT 24
Peak memory 206812 kb
Host smart-ebe7d7d1-148f-40a7-bf37-0f3128d02003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22019
66539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2201966539
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1364667677
Short name T2089
Test name
Test status
Simulation time 168602935 ps
CPU time 0.78 seconds
Started Jul 15 07:02:45 PM PDT 24
Finished Jul 15 07:02:47 PM PDT 24
Peak memory 206832 kb
Host smart-ea7a2d99-18d1-4f33-88d8-8967948d2053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13646
67677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1364667677
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1532387641
Short name T100
Test name
Test status
Simulation time 410847583 ps
CPU time 1.35 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:02:51 PM PDT 24
Peak memory 206772 kb
Host smart-750fad49-5b4c-4387-bf50-1de7c850765f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
87641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1532387641
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1153625976
Short name T825
Test name
Test status
Simulation time 296526001 ps
CPU time 1.08 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:02:51 PM PDT 24
Peak memory 206816 kb
Host smart-d5331762-948d-47cf-a41b-3ecd8bc65c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11536
25976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1153625976
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.850120799
Short name T786
Test name
Test status
Simulation time 21901865252 ps
CPU time 45.87 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:03:36 PM PDT 24
Peak memory 206984 kb
Host smart-11d12b83-d655-40e4-892b-968bc27c59c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85012
0799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.850120799
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2563840683
Short name T1633
Test name
Test status
Simulation time 322895704 ps
CPU time 1.19 seconds
Started Jul 15 07:02:46 PM PDT 24
Finished Jul 15 07:02:47 PM PDT 24
Peak memory 206804 kb
Host smart-da7d7831-b97a-4d85-b731-e797b24139cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25638
40683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2563840683
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3738549296
Short name T2597
Test name
Test status
Simulation time 142576036 ps
CPU time 0.73 seconds
Started Jul 15 07:02:46 PM PDT 24
Finished Jul 15 07:02:47 PM PDT 24
Peak memory 206828 kb
Host smart-777b8a71-e47a-478d-823d-ee47321757b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385
49296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3738549296
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.727044387
Short name T1607
Test name
Test status
Simulation time 50904282 ps
CPU time 0.67 seconds
Started Jul 15 07:02:48 PM PDT 24
Finished Jul 15 07:02:49 PM PDT 24
Peak memory 206792 kb
Host smart-8eb06374-18d3-4144-b170-93ef46314612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72704
4387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.727044387
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.4246742355
Short name T1712
Test name
Test status
Simulation time 859768793 ps
CPU time 2.22 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:02:52 PM PDT 24
Peak memory 206980 kb
Host smart-339bdfbf-80d2-44e4-b41c-25712d966e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42467
42355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.4246742355
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1398828714
Short name T1550
Test name
Test status
Simulation time 114190425701 ps
CPU time 139.69 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:05:12 PM PDT 24
Peak memory 207028 kb
Host smart-519994c0-136a-4fda-ae15-10201b691d60
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1398828714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1398828714
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1781181627
Short name T651
Test name
Test status
Simulation time 85271503928 ps
CPU time 110.97 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 206976 kb
Host smart-3e360bd6-7308-4f92-8e47-ebd75976f0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781181627 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1781181627
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2275753259
Short name T2103
Test name
Test status
Simulation time 101113354628 ps
CPU time 147.39 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:05:17 PM PDT 24
Peak memory 206888 kb
Host smart-8b2284fd-ed1f-4b73-b8ea-459604428cd2
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2275753259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2275753259
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.3048085665
Short name T719
Test name
Test status
Simulation time 90022403869 ps
CPU time 116.22 seconds
Started Jul 15 07:02:52 PM PDT 24
Finished Jul 15 07:04:49 PM PDT 24
Peak memory 207044 kb
Host smart-a9eb685f-f1b7-4440-a9d3-fc2b990f2533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048085665 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3048085665
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.738593125
Short name T996
Test name
Test status
Simulation time 83134668673 ps
CPU time 113.65 seconds
Started Jul 15 07:02:47 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 207036 kb
Host smart-02b94478-85b3-427e-a995-a6ccfacfe7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73859
3125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.738593125
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2878537616
Short name T2119
Test name
Test status
Simulation time 198027929 ps
CPU time 0.85 seconds
Started Jul 15 07:02:47 PM PDT 24
Finished Jul 15 07:02:48 PM PDT 24
Peak memory 206812 kb
Host smart-ebf71e20-2be4-4050-be00-d5c2831f5dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28785
37616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2878537616
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.969812669
Short name T944
Test name
Test status
Simulation time 143868431 ps
CPU time 0.79 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:02:50 PM PDT 24
Peak memory 206796 kb
Host smart-404b4ffd-1268-4dc5-8e48-cff16c84352f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96981
2669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.969812669
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1058297261
Short name T2607
Test name
Test status
Simulation time 225449993 ps
CPU time 0.9 seconds
Started Jul 15 07:02:48 PM PDT 24
Finished Jul 15 07:02:49 PM PDT 24
Peak memory 206704 kb
Host smart-ae1dc212-e429-45b0-9274-b20902dd8744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10582
97261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1058297261
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.59069281
Short name T1425
Test name
Test status
Simulation time 6078835939 ps
CPU time 56.44 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:03:46 PM PDT 24
Peak memory 207096 kb
Host smart-26b64fbe-9aa6-45c7-8acc-02e8868f34af
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=59069281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.59069281
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.1062501514
Short name T1178
Test name
Test status
Simulation time 6120589378 ps
CPU time 45.99 seconds
Started Jul 15 07:02:47 PM PDT 24
Finished Jul 15 07:03:34 PM PDT 24
Peak memory 207000 kb
Host smart-34b21cf5-2e57-4be1-b520-ef4fd6274de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10625
01514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.1062501514
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.4158510956
Short name T1684
Test name
Test status
Simulation time 235650054 ps
CPU time 0.86 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:02:54 PM PDT 24
Peak memory 206764 kb
Host smart-987bf37e-4d0d-48e1-84b9-18ec478d0b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41585
10956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.4158510956
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.1781495392
Short name T744
Test name
Test status
Simulation time 23265662849 ps
CPU time 24.76 seconds
Started Jul 15 07:02:47 PM PDT 24
Finished Jul 15 07:03:12 PM PDT 24
Peak memory 206884 kb
Host smart-5474c98c-c7ee-42db-baab-9f89d13bc670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17814
95392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.1781495392
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1441363980
Short name T2234
Test name
Test status
Simulation time 3370496684 ps
CPU time 4.01 seconds
Started Jul 15 07:02:46 PM PDT 24
Finished Jul 15 07:02:50 PM PDT 24
Peak memory 206864 kb
Host smart-250c7847-b737-4014-a9a8-6d026f027455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14413
63980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1441363980
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.339273815
Short name T589
Test name
Test status
Simulation time 7047660600 ps
CPU time 66.58 seconds
Started Jul 15 07:02:50 PM PDT 24
Finished Jul 15 07:03:58 PM PDT 24
Peak memory 207132 kb
Host smart-fc0e1448-1cbc-4007-9967-ffcd52f3da09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
3815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.339273815
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1448168840
Short name T1892
Test name
Test status
Simulation time 5058290950 ps
CPU time 35.81 seconds
Started Jul 15 07:02:53 PM PDT 24
Finished Jul 15 07:03:29 PM PDT 24
Peak memory 207072 kb
Host smart-aa9a22f6-d890-4274-bfef-9948ad477ae5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1448168840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1448168840
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3479326726
Short name T1207
Test name
Test status
Simulation time 261658486 ps
CPU time 0.97 seconds
Started Jul 15 07:02:50 PM PDT 24
Finished Jul 15 07:02:53 PM PDT 24
Peak memory 206824 kb
Host smart-c7fbf3c3-9094-4b62-919a-402f34bb21e5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3479326726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3479326726
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2966379755
Short name T1000
Test name
Test status
Simulation time 200524225 ps
CPU time 0.89 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 206792 kb
Host smart-2ad2c5ec-d34a-44e5-8307-5d2a2fb80067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29663
79755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2966379755
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.75009480
Short name T491
Test name
Test status
Simulation time 4479150345 ps
CPU time 33.28 seconds
Started Jul 15 07:02:52 PM PDT 24
Finished Jul 15 07:03:27 PM PDT 24
Peak memory 207092 kb
Host smart-2604f909-6d0c-46b5-9e4b-ba330ba4b9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75009
480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.75009480
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3607991404
Short name T602
Test name
Test status
Simulation time 4360147083 ps
CPU time 41.14 seconds
Started Jul 15 07:02:52 PM PDT 24
Finished Jul 15 07:03:34 PM PDT 24
Peak memory 207076 kb
Host smart-94108a68-8e4b-4038-80d3-db719fde48fe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3607991404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3607991404
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2487840950
Short name T2304
Test name
Test status
Simulation time 222468838 ps
CPU time 0.84 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:02:53 PM PDT 24
Peak memory 206824 kb
Host smart-8829c4d2-96f0-4011-b0a8-6ede14a76132
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2487840950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2487840950
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1061999526
Short name T2588
Test name
Test status
Simulation time 154119118 ps
CPU time 0.78 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:02:51 PM PDT 24
Peak memory 206800 kb
Host smart-074e7a03-249c-49ad-b90e-63477be95b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10619
99526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1061999526
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3055908426
Short name T1620
Test name
Test status
Simulation time 189767649 ps
CPU time 0.84 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:02:53 PM PDT 24
Peak memory 206820 kb
Host smart-875a5239-7265-4599-8e5e-9540e6ba77a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30559
08426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3055908426
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.626411952
Short name T1315
Test name
Test status
Simulation time 182820938 ps
CPU time 0.78 seconds
Started Jul 15 07:02:50 PM PDT 24
Finished Jul 15 07:02:52 PM PDT 24
Peak memory 206800 kb
Host smart-962b27ec-48d7-465c-b472-51da6e2e8741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62641
1952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.626411952
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.654590677
Short name T678
Test name
Test status
Simulation time 216748905 ps
CPU time 0.85 seconds
Started Jul 15 07:02:50 PM PDT 24
Finished Jul 15 07:02:52 PM PDT 24
Peak memory 206800 kb
Host smart-c0da6d67-ee9d-4631-aa25-613e626a5a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65459
0677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.654590677
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2085681955
Short name T1694
Test name
Test status
Simulation time 159701504 ps
CPU time 0.83 seconds
Started Jul 15 07:02:52 PM PDT 24
Finished Jul 15 07:02:54 PM PDT 24
Peak memory 206788 kb
Host smart-40b31c36-1416-46b6-89c3-92d5ddd67ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20856
81955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2085681955
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.4132864838
Short name T73
Test name
Test status
Simulation time 305655006 ps
CPU time 0.99 seconds
Started Jul 15 07:02:49 PM PDT 24
Finished Jul 15 07:02:51 PM PDT 24
Peak memory 206808 kb
Host smart-94631cdd-6011-41bf-8fd6-13b84cc242b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4132864838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.4132864838
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1997910119
Short name T186
Test name
Test status
Simulation time 273656039 ps
CPU time 1 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:02:53 PM PDT 24
Peak memory 206776 kb
Host smart-02eab70b-9e60-4b15-90f2-26e75bd79ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19979
10119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1997910119
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3295676129
Short name T1038
Test name
Test status
Simulation time 192873355 ps
CPU time 0.8 seconds
Started Jul 15 07:02:50 PM PDT 24
Finished Jul 15 07:02:52 PM PDT 24
Peak memory 206828 kb
Host smart-2dbbdd7e-97d0-4b6f-a16e-5a6b3bbd993c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956
76129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3295676129
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.129143528
Short name T1280
Test name
Test status
Simulation time 40222110 ps
CPU time 0.65 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:02:53 PM PDT 24
Peak memory 206796 kb
Host smart-7d396018-3d89-473b-854b-e2b6fe0c8ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12914
3528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.129143528
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3106465094
Short name T764
Test name
Test status
Simulation time 10126114882 ps
CPU time 24.53 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 207120 kb
Host smart-fc52c234-6fe1-4ba8-bed6-9733db1be3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31064
65094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3106465094
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3781133681
Short name T478
Test name
Test status
Simulation time 157579408 ps
CPU time 0.89 seconds
Started Jul 15 07:02:50 PM PDT 24
Finished Jul 15 07:02:51 PM PDT 24
Peak memory 206844 kb
Host smart-91e292af-ee14-4959-82a6-3b2224954a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37811
33681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3781133681
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3742674773
Short name T1858
Test name
Test status
Simulation time 230326447 ps
CPU time 0.92 seconds
Started Jul 15 07:02:55 PM PDT 24
Finished Jul 15 07:02:56 PM PDT 24
Peak memory 206812 kb
Host smart-f91900e7-bff2-41a4-9708-2b987ab91e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37426
74773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3742674773
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.3072811540
Short name T163
Test name
Test status
Simulation time 10693900358 ps
CPU time 201.41 seconds
Started Jul 15 07:02:50 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 207040 kb
Host smart-9be0fa97-6963-4507-99c2-d3380da11876
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3072811540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3072811540
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2940929148
Short name T828
Test name
Test status
Simulation time 8425763537 ps
CPU time 52.17 seconds
Started Jul 15 07:02:50 PM PDT 24
Finished Jul 15 07:03:44 PM PDT 24
Peak memory 206972 kb
Host smart-60bc645d-55c6-458a-b354-5caf31f30caa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2940929148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2940929148
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1729510426
Short name T880
Test name
Test status
Simulation time 22463548892 ps
CPU time 533.2 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 207092 kb
Host smart-67292d6a-6253-48cf-8114-d8f593d652d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1729510426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1729510426
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.758301237
Short name T1683
Test name
Test status
Simulation time 239631172 ps
CPU time 0.9 seconds
Started Jul 15 07:02:51 PM PDT 24
Finished Jul 15 07:02:54 PM PDT 24
Peak memory 206792 kb
Host smart-0d61da36-7a96-4fe0-9e08-55d2853ef5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75830
1237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.758301237
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2886182868
Short name T654
Test name
Test status
Simulation time 193694185 ps
CPU time 0.92 seconds
Started Jul 15 07:02:52 PM PDT 24
Finished Jul 15 07:02:54 PM PDT 24
Peak memory 206808 kb
Host smart-14fbf263-ba4e-41ee-bf0d-aa5962051c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28861
82868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2886182868
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2993831461
Short name T2140
Test name
Test status
Simulation time 179866750 ps
CPU time 0.86 seconds
Started Jul 15 07:02:58 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 206788 kb
Host smart-d65ca556-a5ad-421d-ab0e-e90e81674ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29938
31461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2993831461
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2378489983
Short name T68
Test name
Test status
Simulation time 189712288 ps
CPU time 0.89 seconds
Started Jul 15 07:02:59 PM PDT 24
Finished Jul 15 07:03:00 PM PDT 24
Peak memory 206288 kb
Host smart-8634fd10-7cf7-4d70-9eb2-39f1badfe611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23784
89983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2378489983
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.4081978475
Short name T46
Test name
Test status
Simulation time 370171791 ps
CPU time 1.24 seconds
Started Jul 15 07:02:58 PM PDT 24
Finished Jul 15 07:03:00 PM PDT 24
Peak memory 206824 kb
Host smart-cb96b0f8-c521-4913-9698-af3f8d79eb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40819
78475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.4081978475
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.4028856752
Short name T1864
Test name
Test status
Simulation time 295366555 ps
CPU time 0.96 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 206804 kb
Host smart-4af972b2-64e4-40ac-80be-800e8a876b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40288
56752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.4028856752
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.23635163
Short name T1527
Test name
Test status
Simulation time 145892957 ps
CPU time 0.76 seconds
Started Jul 15 07:02:59 PM PDT 24
Finished Jul 15 07:03:00 PM PDT 24
Peak memory 206792 kb
Host smart-45497859-514d-4b19-999b-be9fdef8180b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23635
163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.23635163
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.4281475121
Short name T2545
Test name
Test status
Simulation time 147951757 ps
CPU time 0.79 seconds
Started Jul 15 07:02:58 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 206816 kb
Host smart-d9e0635b-5261-4cda-a91e-f6da919d077a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42814
75121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.4281475121
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.864573927
Short name T2350
Test name
Test status
Simulation time 190593444 ps
CPU time 0.89 seconds
Started Jul 15 07:02:56 PM PDT 24
Finished Jul 15 07:02:58 PM PDT 24
Peak memory 206760 kb
Host smart-cd6d4319-4edf-483a-ae44-a7ffdc4707ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86457
3927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.864573927
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2855406621
Short name T2231
Test name
Test status
Simulation time 4538456989 ps
CPU time 41.62 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:03:40 PM PDT 24
Peak memory 207016 kb
Host smart-ec33439a-972d-4972-97b5-6cf9a0a331a7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2855406621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2855406621
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1517204437
Short name T601
Test name
Test status
Simulation time 160817128 ps
CPU time 0.77 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:02:58 PM PDT 24
Peak memory 206844 kb
Host smart-0e92c06a-d40e-4e6c-8975-798d71d20b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15172
04437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1517204437
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1877145794
Short name T29
Test name
Test status
Simulation time 178793019 ps
CPU time 0.87 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:02:58 PM PDT 24
Peak memory 206792 kb
Host smart-baf9dd08-4c85-42c8-ba04-3995b5478080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18771
45794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1877145794
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1006832555
Short name T1472
Test name
Test status
Simulation time 1026011567 ps
CPU time 2.24 seconds
Started Jul 15 07:03:00 PM PDT 24
Finished Jul 15 07:03:03 PM PDT 24
Peak memory 207012 kb
Host smart-a773bc17-c4ad-43b5-be0b-48232006f988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10068
32555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1006832555
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2705110386
Short name T1973
Test name
Test status
Simulation time 4815987361 ps
CPU time 46.97 seconds
Started Jul 15 07:02:59 PM PDT 24
Finished Jul 15 07:03:46 PM PDT 24
Peak memory 207080 kb
Host smart-144c3241-0c34-483c-8b91-63224691f764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27051
10386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2705110386
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3018871562
Short name T2326
Test name
Test status
Simulation time 8972325777 ps
CPU time 81.62 seconds
Started Jul 15 07:02:55 PM PDT 24
Finished Jul 15 07:04:17 PM PDT 24
Peak memory 207092 kb
Host smart-1da27e5f-419c-4977-96dc-c07911dea61e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3018871562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3018871562
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.2209651502
Short name T1426
Test name
Test status
Simulation time 52265461 ps
CPU time 0.69 seconds
Started Jul 15 07:04:51 PM PDT 24
Finished Jul 15 07:04:52 PM PDT 24
Peak memory 206832 kb
Host smart-6c7e9c22-e545-4940-9d14-758bb5ebe732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2209651502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2209651502
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2330984978
Short name T2155
Test name
Test status
Simulation time 3748846149 ps
CPU time 5.3 seconds
Started Jul 15 07:04:36 PM PDT 24
Finished Jul 15 07:04:42 PM PDT 24
Peak memory 206984 kb
Host smart-c8f4eb6b-c097-43ff-9d45-857202624a54
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2330984978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2330984978
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2266055012
Short name T783
Test name
Test status
Simulation time 13443878645 ps
CPU time 12.84 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:04:51 PM PDT 24
Peak memory 207008 kb
Host smart-e4d26317-dd9b-4104-931a-deda885dfcaf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2266055012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2266055012
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.652896457
Short name T1085
Test name
Test status
Simulation time 23371566826 ps
CPU time 23.41 seconds
Started Jul 15 07:04:40 PM PDT 24
Finished Jul 15 07:05:04 PM PDT 24
Peak memory 207040 kb
Host smart-fd47da8e-9873-4474-80b0-be4c1f628dcf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=652896457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.652896457
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3903745220
Short name T1711
Test name
Test status
Simulation time 169179173 ps
CPU time 0.82 seconds
Started Jul 15 07:04:36 PM PDT 24
Finished Jul 15 07:04:37 PM PDT 24
Peak memory 206812 kb
Host smart-6e24a7d2-fc29-4021-a2ae-f375eaeff871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39037
45220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3903745220
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1335055423
Short name T1738
Test name
Test status
Simulation time 175542653 ps
CPU time 0.82 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:04:39 PM PDT 24
Peak memory 206840 kb
Host smart-a9581825-ab99-4d4f-aadf-b592c75ecc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13350
55423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1335055423
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.504755230
Short name T2064
Test name
Test status
Simulation time 361223175 ps
CPU time 1.12 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:04:39 PM PDT 24
Peak memory 206828 kb
Host smart-3181b539-97be-4a6e-8a51-410055433ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50475
5230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.504755230
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.954956583
Short name T96
Test name
Test status
Simulation time 731281360 ps
CPU time 1.74 seconds
Started Jul 15 07:04:36 PM PDT 24
Finished Jul 15 07:04:38 PM PDT 24
Peak memory 207008 kb
Host smart-cebcb621-02b3-4bb2-b574-152f8535748c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95495
6583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.954956583
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3625754813
Short name T2656
Test name
Test status
Simulation time 14639988043 ps
CPU time 27.34 seconds
Started Jul 15 07:04:36 PM PDT 24
Finished Jul 15 07:05:04 PM PDT 24
Peak memory 207012 kb
Host smart-5df682a1-5bac-4ce8-9c36-84573708d51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36257
54813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3625754813
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.741027610
Short name T1563
Test name
Test status
Simulation time 454045043 ps
CPU time 1.42 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:04:39 PM PDT 24
Peak memory 206828 kb
Host smart-ed91c91f-7ec1-4bd1-8c92-2abeab9daffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74102
7610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.741027610
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.15857365
Short name T2409
Test name
Test status
Simulation time 133744942 ps
CPU time 0.73 seconds
Started Jul 15 07:04:40 PM PDT 24
Finished Jul 15 07:04:42 PM PDT 24
Peak memory 206832 kb
Host smart-9ebb96b9-5077-4484-818c-85785c5af2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15857
365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.15857365
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.2795107731
Short name T1233
Test name
Test status
Simulation time 107304411 ps
CPU time 0.71 seconds
Started Jul 15 07:04:39 PM PDT 24
Finished Jul 15 07:04:40 PM PDT 24
Peak memory 206756 kb
Host smart-228b979f-ae3e-4736-9659-39b255f4656a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27951
07731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2795107731
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3771319162
Short name T670
Test name
Test status
Simulation time 852007290 ps
CPU time 2.24 seconds
Started Jul 15 07:04:40 PM PDT 24
Finished Jul 15 07:04:43 PM PDT 24
Peak memory 207024 kb
Host smart-98328ab5-8851-4a9f-bfaf-50e889682621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37713
19162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3771319162
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1186764053
Short name T2593
Test name
Test status
Simulation time 169228273 ps
CPU time 1.48 seconds
Started Jul 15 07:04:38 PM PDT 24
Finished Jul 15 07:04:40 PM PDT 24
Peak memory 206968 kb
Host smart-0a843aec-5cf0-4849-ae9d-c1b607020d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11867
64053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1186764053
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3395284977
Short name T1803
Test name
Test status
Simulation time 172874698 ps
CPU time 0.83 seconds
Started Jul 15 07:04:42 PM PDT 24
Finished Jul 15 07:04:43 PM PDT 24
Peak memory 206784 kb
Host smart-880da5eb-9a3c-45e4-95c8-996cd34c51bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
84977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3395284977
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.280546018
Short name T473
Test name
Test status
Simulation time 149256384 ps
CPU time 0.77 seconds
Started Jul 15 07:04:46 PM PDT 24
Finished Jul 15 07:04:47 PM PDT 24
Peak memory 206788 kb
Host smart-62bcb403-2f84-4109-b6a3-791886329a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28054
6018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.280546018
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3697545875
Short name T2454
Test name
Test status
Simulation time 212059636 ps
CPU time 0.88 seconds
Started Jul 15 07:04:46 PM PDT 24
Finished Jul 15 07:04:48 PM PDT 24
Peak memory 206824 kb
Host smart-db996e1d-0339-4dd4-811d-ea3befb3fbb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36975
45875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3697545875
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3805856726
Short name T464
Test name
Test status
Simulation time 247476513 ps
CPU time 1.02 seconds
Started Jul 15 07:04:45 PM PDT 24
Finished Jul 15 07:04:46 PM PDT 24
Peak memory 206808 kb
Host smart-0d0e8356-6439-4170-a9fb-9f366361d046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38058
56726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3805856726
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3226121554
Short name T1701
Test name
Test status
Simulation time 23358917341 ps
CPU time 21.08 seconds
Started Jul 15 07:04:45 PM PDT 24
Finished Jul 15 07:05:07 PM PDT 24
Peak memory 206872 kb
Host smart-45da202c-d197-41bc-b2be-6cd8b0d9c487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32261
21554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3226121554
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3411440267
Short name T1369
Test name
Test status
Simulation time 3323181721 ps
CPU time 4.18 seconds
Started Jul 15 07:04:43 PM PDT 24
Finished Jul 15 07:04:48 PM PDT 24
Peak memory 206824 kb
Host smart-7ae67b9d-424c-422a-b96e-f8bd8bfcc734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34114
40267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3411440267
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2373875928
Short name T465
Test name
Test status
Simulation time 10919354433 ps
CPU time 102.88 seconds
Started Jul 15 07:04:43 PM PDT 24
Finished Jul 15 07:06:26 PM PDT 24
Peak memory 207108 kb
Host smart-436f8186-8301-4f09-9940-be200ae49a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23738
75928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2373875928
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3208858049
Short name T1593
Test name
Test status
Simulation time 6274968087 ps
CPU time 64.06 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 207064 kb
Host smart-2319b62e-a7b3-47c0-b87d-7626fef253dd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3208858049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3208858049
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.847354921
Short name T814
Test name
Test status
Simulation time 265072142 ps
CPU time 0.99 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:04:46 PM PDT 24
Peak memory 206776 kb
Host smart-c32c2a22-1fde-46fd-b54e-d705f52a795a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=847354921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.847354921
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1809144241
Short name T2554
Test name
Test status
Simulation time 184695135 ps
CPU time 0.85 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 206788 kb
Host smart-66a1d07e-271c-4044-88b3-061865952ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18091
44241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1809144241
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2011977407
Short name T152
Test name
Test status
Simulation time 6413195956 ps
CPU time 178.69 seconds
Started Jul 15 07:04:46 PM PDT 24
Finished Jul 15 07:07:46 PM PDT 24
Peak memory 207060 kb
Host smart-57633683-85ab-48e6-9d80-e5f49b95b32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20119
77407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2011977407
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1460375716
Short name T2578
Test name
Test status
Simulation time 5004825230 ps
CPU time 144.72 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:07:10 PM PDT 24
Peak memory 206984 kb
Host smart-fdb2bd2c-df01-4469-825f-2a6b3a21d1c7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1460375716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1460375716
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3574191150
Short name T2487
Test name
Test status
Simulation time 161244751 ps
CPU time 0.79 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 206824 kb
Host smart-27f0835b-6a71-4abc-8f85-438db0b3a11b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3574191150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3574191150
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.933372203
Short name T289
Test name
Test status
Simulation time 181169678 ps
CPU time 0.81 seconds
Started Jul 15 07:04:43 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 206808 kb
Host smart-fa2535ab-89b6-49b2-9465-b53f3b79f420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93337
2203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.933372203
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.88652896
Short name T1677
Test name
Test status
Simulation time 213601475 ps
CPU time 0.88 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 206808 kb
Host smart-653b3c4d-9ac9-42cd-8f59-722b2e700383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88652
896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.88652896
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3158307263
Short name T1722
Test name
Test status
Simulation time 247193248 ps
CPU time 0.88 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 206820 kb
Host smart-042e6582-1484-4f0b-adc8-b9c27c175820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31583
07263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3158307263
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1849481702
Short name T1502
Test name
Test status
Simulation time 202100430 ps
CPU time 0.81 seconds
Started Jul 15 07:04:45 PM PDT 24
Finished Jul 15 07:04:47 PM PDT 24
Peak memory 206816 kb
Host smart-113d3489-9ae1-4f96-8d2f-1155b1c67601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18494
81702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1849481702
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.823632397
Short name T738
Test name
Test status
Simulation time 225556913 ps
CPU time 0.84 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 206828 kb
Host smart-35d05ae9-547b-479d-a153-0e4569ae7d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82363
2397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.823632397
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1325346965
Short name T1024
Test name
Test status
Simulation time 238819148 ps
CPU time 1 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 206804 kb
Host smart-97d6516b-e13b-4d81-b27f-f502a16e0dff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1325346965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1325346965
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.330673511
Short name T1528
Test name
Test status
Simulation time 165283263 ps
CPU time 0.81 seconds
Started Jul 15 07:04:45 PM PDT 24
Finished Jul 15 07:04:47 PM PDT 24
Peak memory 206824 kb
Host smart-6c03ccc7-67da-4d09-9ff2-7f6f80d2d222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33067
3511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.330673511
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4043727935
Short name T24
Test name
Test status
Simulation time 46416542 ps
CPU time 0.67 seconds
Started Jul 15 07:04:45 PM PDT 24
Finished Jul 15 07:04:46 PM PDT 24
Peak memory 206740 kb
Host smart-25c66ad4-863b-4b6f-8456-fc854e564336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40437
27935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4043727935
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.851027914
Short name T2502
Test name
Test status
Simulation time 9108191093 ps
CPU time 22.84 seconds
Started Jul 15 07:04:44 PM PDT 24
Finished Jul 15 07:05:08 PM PDT 24
Peak memory 207092 kb
Host smart-d86847c1-1217-427b-a7c8-b4cc581ad3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85102
7914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.851027914
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2278301870
Short name T2633
Test name
Test status
Simulation time 208512974 ps
CPU time 0.83 seconds
Started Jul 15 07:04:47 PM PDT 24
Finished Jul 15 07:04:48 PM PDT 24
Peak memory 206828 kb
Host smart-99f9b1df-40aa-44fd-849f-8e4eea915bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
01870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2278301870
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.4159747307
Short name T2387
Test name
Test status
Simulation time 180323913 ps
CPU time 0.85 seconds
Started Jul 15 07:04:45 PM PDT 24
Finished Jul 15 07:04:47 PM PDT 24
Peak memory 206808 kb
Host smart-63f54f1c-1b37-4b4e-9b10-73b632f390d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
47307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.4159747307
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2449963307
Short name T1084
Test name
Test status
Simulation time 228343431 ps
CPU time 0.91 seconds
Started Jul 15 07:04:43 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 206760 kb
Host smart-8f8c19d2-8112-400f-a0b9-5e4c58b7eed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24499
63307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2449963307
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3015360576
Short name T1245
Test name
Test status
Simulation time 172488744 ps
CPU time 0.83 seconds
Started Jul 15 07:04:46 PM PDT 24
Finished Jul 15 07:04:48 PM PDT 24
Peak memory 206848 kb
Host smart-e83505a7-028c-465c-9bad-b784ee79e558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30153
60576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3015360576
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.853713690
Short name T1075
Test name
Test status
Simulation time 156948521 ps
CPU time 0.73 seconds
Started Jul 15 07:04:42 PM PDT 24
Finished Jul 15 07:04:43 PM PDT 24
Peak memory 206828 kb
Host smart-fde14ad0-8ebd-4108-bbde-b521163a1899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85371
3690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.853713690
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3813249386
Short name T1617
Test name
Test status
Simulation time 183672221 ps
CPU time 0.76 seconds
Started Jul 15 07:04:45 PM PDT 24
Finished Jul 15 07:04:47 PM PDT 24
Peak memory 206808 kb
Host smart-4a3ae58e-eb4b-4b46-936d-e0df7054b5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38132
49386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3813249386
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.882036571
Short name T197
Test name
Test status
Simulation time 151286907 ps
CPU time 0.78 seconds
Started Jul 15 07:04:42 PM PDT 24
Finished Jul 15 07:04:44 PM PDT 24
Peak memory 206808 kb
Host smart-d190c558-3d6e-4b20-a5f7-9e85ff854035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88203
6571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.882036571
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2330078276
Short name T599
Test name
Test status
Simulation time 196551915 ps
CPU time 0.87 seconds
Started Jul 15 07:04:45 PM PDT 24
Finished Jul 15 07:04:46 PM PDT 24
Peak memory 206824 kb
Host smart-9a46d9c9-9d9a-464e-9e32-c074f3691cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23300
78276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2330078276
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.1011542854
Short name T1974
Test name
Test status
Simulation time 4651590141 ps
CPU time 43.11 seconds
Started Jul 15 07:04:55 PM PDT 24
Finished Jul 15 07:05:38 PM PDT 24
Peak memory 207076 kb
Host smart-e7905f64-2829-4b14-a448-78320ca17171
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1011542854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.1011542854
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.4270167801
Short name T1239
Test name
Test status
Simulation time 158472666 ps
CPU time 0.75 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:04:54 PM PDT 24
Peak memory 206844 kb
Host smart-97ddc8be-0b26-4668-87bc-707a43eba6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
67801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.4270167801
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1683286564
Short name T2695
Test name
Test status
Simulation time 170643133 ps
CPU time 0.78 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:04:53 PM PDT 24
Peak memory 206808 kb
Host smart-09ed66af-a44f-42b7-9a3c-0d4415b622df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
86564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1683286564
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1190530
Short name T429
Test name
Test status
Simulation time 1391928858 ps
CPU time 2.88 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:04:55 PM PDT 24
Peak memory 206900 kb
Host smart-53cc6a19-0e8e-4df6-9da2-e500e5d62a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11905
30 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1190530
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2623840272
Short name T1817
Test name
Test status
Simulation time 4973300070 ps
CPU time 36.93 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 207104 kb
Host smart-6691f749-61be-493d-8593-fd540d39c5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26238
40272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2623840272
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3562307576
Short name T1596
Test name
Test status
Simulation time 38335169 ps
CPU time 0.67 seconds
Started Jul 15 07:05:01 PM PDT 24
Finished Jul 15 07:05:03 PM PDT 24
Peak memory 206860 kb
Host smart-18a6f071-fc8c-4ffe-8014-7fa361183d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3562307576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3562307576
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.4131213923
Short name T1734
Test name
Test status
Simulation time 3934749771 ps
CPU time 4.57 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:04:57 PM PDT 24
Peak memory 207032 kb
Host smart-c4f93203-d66d-4a7a-a118-9bc00e6fe1c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4131213923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.4131213923
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2413133028
Short name T864
Test name
Test status
Simulation time 13404975687 ps
CPU time 13.82 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:05:07 PM PDT 24
Peak memory 206908 kb
Host smart-1fc1d266-0e56-42ad-bce6-ef6c33b7ee5b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2413133028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2413133028
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3469833329
Short name T1150
Test name
Test status
Simulation time 162623201 ps
CPU time 0.82 seconds
Started Jul 15 07:04:53 PM PDT 24
Finished Jul 15 07:04:54 PM PDT 24
Peak memory 206808 kb
Host smart-c412cc77-983f-4fb4-ab06-4f03ced2555b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34698
33329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3469833329
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3484367619
Short name T726
Test name
Test status
Simulation time 150064077 ps
CPU time 0.81 seconds
Started Jul 15 07:04:54 PM PDT 24
Finished Jul 15 07:04:55 PM PDT 24
Peak memory 206812 kb
Host smart-94c21b3d-14a3-4a5d-beed-00683353a470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34843
67619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3484367619
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3248514831
Short name T962
Test name
Test status
Simulation time 278333562 ps
CPU time 0.99 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:04:54 PM PDT 24
Peak memory 206824 kb
Host smart-20dccbe2-be5a-406c-9294-5f2360e9edf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32485
14831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3248514831
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3691046656
Short name T2564
Test name
Test status
Simulation time 1083277660 ps
CPU time 2.38 seconds
Started Jul 15 07:04:54 PM PDT 24
Finished Jul 15 07:04:57 PM PDT 24
Peak memory 207028 kb
Host smart-6c6bd637-f44d-4dd8-b631-172d4c807e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36910
46656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3691046656
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2569529644
Short name T2415
Test name
Test status
Simulation time 418242452 ps
CPU time 1.32 seconds
Started Jul 15 07:04:53 PM PDT 24
Finished Jul 15 07:04:55 PM PDT 24
Peak memory 206816 kb
Host smart-923776dd-48fe-4434-9eec-a3594c0fb39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25695
29644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2569529644
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_enable.48641531
Short name T2087
Test name
Test status
Simulation time 60720648 ps
CPU time 0.69 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:04:53 PM PDT 24
Peak memory 206784 kb
Host smart-c86edc20-acf9-4d49-852a-a19b00d4d646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48641
531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.48641531
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3701907845
Short name T1318
Test name
Test status
Simulation time 1015804844 ps
CPU time 2.01 seconds
Started Jul 15 07:04:53 PM PDT 24
Finished Jul 15 07:04:56 PM PDT 24
Peak memory 206936 kb
Host smart-b860d158-d375-4d07-ae53-a0084c9ec9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
07845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3701907845
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3015795500
Short name T1822
Test name
Test status
Simulation time 257392816 ps
CPU time 1.84 seconds
Started Jul 15 07:04:53 PM PDT 24
Finished Jul 15 07:04:55 PM PDT 24
Peak memory 207020 kb
Host smart-a0cbb4ae-7491-49f2-b6c1-217bb4f1f6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30157
95500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3015795500
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2895261970
Short name T627
Test name
Test status
Simulation time 230582291 ps
CPU time 0.89 seconds
Started Jul 15 07:04:54 PM PDT 24
Finished Jul 15 07:04:55 PM PDT 24
Peak memory 206812 kb
Host smart-2fc32b4b-eb56-4bb9-b6ba-10aa75a49b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28952
61970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2895261970
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2735404326
Short name T2388
Test name
Test status
Simulation time 134103817 ps
CPU time 0.73 seconds
Started Jul 15 07:04:51 PM PDT 24
Finished Jul 15 07:04:52 PM PDT 24
Peak memory 206820 kb
Host smart-92419a71-4ef1-44e5-a897-623a0eceee7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27354
04326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2735404326
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3587300864
Short name T1413
Test name
Test status
Simulation time 211579811 ps
CPU time 0.88 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:04:53 PM PDT 24
Peak memory 206824 kb
Host smart-080f2d2e-ae76-408d-99a5-d90c2617d168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
00864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3587300864
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.3050020523
Short name T632
Test name
Test status
Simulation time 5192774656 ps
CPU time 42.86 seconds
Started Jul 15 07:04:53 PM PDT 24
Finished Jul 15 07:05:37 PM PDT 24
Peak memory 207084 kb
Host smart-5da28f22-ae43-4060-9dd1-d6c7250787bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
20523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.3050020523
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1194669436
Short name T1260
Test name
Test status
Simulation time 255737588 ps
CPU time 0.98 seconds
Started Jul 15 07:04:51 PM PDT 24
Finished Jul 15 07:04:52 PM PDT 24
Peak memory 206764 kb
Host smart-d7753ce2-fce6-4f82-b1ea-94d30395ea62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11946
69436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1194669436
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1795853724
Short name T2185
Test name
Test status
Simulation time 23393090164 ps
CPU time 25.93 seconds
Started Jul 15 07:04:52 PM PDT 24
Finished Jul 15 07:05:18 PM PDT 24
Peak memory 206884 kb
Host smart-025f5cf2-ba5c-424d-b051-d7046aa3c991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17958
53724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1795853724
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1461152046
Short name T2030
Test name
Test status
Simulation time 3335643742 ps
CPU time 3.91 seconds
Started Jul 15 07:04:53 PM PDT 24
Finished Jul 15 07:04:57 PM PDT 24
Peak memory 206864 kb
Host smart-25a35295-6162-4f5e-a2aa-ba0763a4a0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14611
52046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1461152046
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.4268570731
Short name T1659
Test name
Test status
Simulation time 9800004341 ps
CPU time 87.86 seconds
Started Jul 15 07:05:02 PM PDT 24
Finished Jul 15 07:06:31 PM PDT 24
Peak memory 207080 kb
Host smart-16ab2d0f-7825-4127-aa8f-c973d4cac285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42685
70731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.4268570731
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2351929530
Short name T1623
Test name
Test status
Simulation time 5457392453 ps
CPU time 146.7 seconds
Started Jul 15 07:05:03 PM PDT 24
Finished Jul 15 07:07:31 PM PDT 24
Peak memory 206952 kb
Host smart-11682651-2631-447b-8f1c-ff48e2a03bff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2351929530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2351929530
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1098844610
Short name T2533
Test name
Test status
Simulation time 239643375 ps
CPU time 0.86 seconds
Started Jul 15 07:04:58 PM PDT 24
Finished Jul 15 07:05:00 PM PDT 24
Peak memory 206796 kb
Host smart-0ae80147-a888-4f58-9041-dfb4ad63be64
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1098844610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1098844610
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3989470092
Short name T2077
Test name
Test status
Simulation time 195482776 ps
CPU time 0.84 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:00 PM PDT 24
Peak memory 206824 kb
Host smart-0c4e5775-7bd0-481a-a18b-0bd6a73e9c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39894
70092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3989470092
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2320707698
Short name T2070
Test name
Test status
Simulation time 6839945335 ps
CPU time 191.47 seconds
Started Jul 15 07:04:58 PM PDT 24
Finished Jul 15 07:08:10 PM PDT 24
Peak memory 207064 kb
Host smart-7993d72b-c682-4403-9dcc-3175bdb63c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23207
07698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2320707698
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.604041540
Short name T2661
Test name
Test status
Simulation time 6614875260 ps
CPU time 63.3 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 207036 kb
Host smart-7613bbea-61fa-4344-a947-d635871286a6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=604041540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.604041540
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2030359379
Short name T432
Test name
Test status
Simulation time 160010575 ps
CPU time 0.8 seconds
Started Jul 15 07:04:58 PM PDT 24
Finished Jul 15 07:04:59 PM PDT 24
Peak memory 206828 kb
Host smart-ec2a36d7-91c0-42f5-8384-9f921c0305a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2030359379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2030359379
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3851758199
Short name T528
Test name
Test status
Simulation time 156858293 ps
CPU time 0.87 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:02 PM PDT 24
Peak memory 206804 kb
Host smart-2f069fde-a7c0-4a3d-8d04-b6d0d934d588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
58199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3851758199
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2450592412
Short name T2311
Test name
Test status
Simulation time 234040478 ps
CPU time 0.95 seconds
Started Jul 15 07:05:03 PM PDT 24
Finished Jul 15 07:05:05 PM PDT 24
Peak memory 206808 kb
Host smart-c3490b5c-da50-4f46-9aff-41dee00fd5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24505
92412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2450592412
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3531531068
Short name T1760
Test name
Test status
Simulation time 177565530 ps
CPU time 0.79 seconds
Started Jul 15 07:04:58 PM PDT 24
Finished Jul 15 07:04:59 PM PDT 24
Peak memory 206808 kb
Host smart-d23be1a2-8958-4801-abb3-0cc96c30df55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35315
31068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3531531068
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.229395404
Short name T1309
Test name
Test status
Simulation time 189204337 ps
CPU time 0.8 seconds
Started Jul 15 07:05:03 PM PDT 24
Finished Jul 15 07:05:05 PM PDT 24
Peak memory 206756 kb
Host smart-5aeca64a-861e-46dc-b379-55e103ed5c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22939
5404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.229395404
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2574084896
Short name T1553
Test name
Test status
Simulation time 200934691 ps
CPU time 0.83 seconds
Started Jul 15 07:04:58 PM PDT 24
Finished Jul 15 07:04:59 PM PDT 24
Peak memory 206848 kb
Host smart-157cd59d-35ba-49d1-9726-389bfdc7f25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25740
84896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2574084896
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2369361758
Short name T1782
Test name
Test status
Simulation time 170061539 ps
CPU time 0.87 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:01 PM PDT 24
Peak memory 206784 kb
Host smart-e3a19b6a-4362-4101-8410-0c79d6cfbde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23693
61758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2369361758
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3125123243
Short name T1618
Test name
Test status
Simulation time 264246765 ps
CPU time 0.94 seconds
Started Jul 15 07:04:57 PM PDT 24
Finished Jul 15 07:04:59 PM PDT 24
Peak memory 206784 kb
Host smart-6e16e2c2-f36b-4163-b650-9eda2fb313bb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3125123243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3125123243
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3331292944
Short name T902
Test name
Test status
Simulation time 146655491 ps
CPU time 0.76 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:01 PM PDT 24
Peak memory 206804 kb
Host smart-92cb2ccb-2e3a-4844-8d69-44f3e23d22b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33312
92944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3331292944
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3105355489
Short name T1076
Test name
Test status
Simulation time 57584862 ps
CPU time 0.67 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:00 PM PDT 24
Peak memory 206772 kb
Host smart-ab36b10b-47d2-4187-b188-b0d0e0aa28cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31053
55489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3105355489
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4252468929
Short name T259
Test name
Test status
Simulation time 14431467913 ps
CPU time 30.5 seconds
Started Jul 15 07:05:01 PM PDT 24
Finished Jul 15 07:05:32 PM PDT 24
Peak memory 215236 kb
Host smart-926ddd00-434a-4a6a-9aba-14040e47e639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42524
68929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4252468929
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.522826861
Short name T419
Test name
Test status
Simulation time 192264488 ps
CPU time 0.83 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:01 PM PDT 24
Peak memory 206808 kb
Host smart-137a24b7-2479-4b84-bb79-e75c56678b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52282
6861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.522826861
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3602713415
Short name T1294
Test name
Test status
Simulation time 227460853 ps
CPU time 0.91 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:02 PM PDT 24
Peak memory 206800 kb
Host smart-a67907ac-7c61-48d1-9e5d-d92b5ca052ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36027
13415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3602713415
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2342504182
Short name T852
Test name
Test status
Simulation time 183299226 ps
CPU time 0.83 seconds
Started Jul 15 07:05:01 PM PDT 24
Finished Jul 15 07:05:03 PM PDT 24
Peak memory 206816 kb
Host smart-7a7ae6c0-e5cb-4358-97a5-6603439fc1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23425
04182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2342504182
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.4069936409
Short name T1714
Test name
Test status
Simulation time 223984822 ps
CPU time 0.81 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:00 PM PDT 24
Peak memory 206792 kb
Host smart-3576e277-9142-4529-a7f8-6e8e7b5020a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40699
36409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.4069936409
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2993498862
Short name T787
Test name
Test status
Simulation time 223060651 ps
CPU time 0.94 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:01 PM PDT 24
Peak memory 206700 kb
Host smart-ed777547-6a75-4d12-85ce-d6de0341b3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29934
98862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2993498862
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1020364693
Short name T2106
Test name
Test status
Simulation time 155276363 ps
CPU time 0.78 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:02 PM PDT 24
Peak memory 206808 kb
Host smart-333d0068-baa4-44c2-8707-0eee80ff18c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10203
64693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1020364693
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.357792248
Short name T1308
Test name
Test status
Simulation time 152342616 ps
CPU time 0.83 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:01 PM PDT 24
Peak memory 206796 kb
Host smart-57832383-196a-4ae6-967b-add9875e01da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35779
2248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.357792248
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1280076117
Short name T2492
Test name
Test status
Simulation time 239975264 ps
CPU time 1 seconds
Started Jul 15 07:05:02 PM PDT 24
Finished Jul 15 07:05:04 PM PDT 24
Peak memory 206812 kb
Host smart-b89618f1-da50-4b9d-a22d-8a0c8d20b85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12800
76117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1280076117
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2499262922
Short name T2716
Test name
Test status
Simulation time 3211727601 ps
CPU time 30.97 seconds
Started Jul 15 07:04:58 PM PDT 24
Finished Jul 15 07:05:29 PM PDT 24
Peak memory 207040 kb
Host smart-dc35bde1-44fc-4f91-909d-0284b839bc59
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2499262922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2499262922
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.827315312
Short name T1201
Test name
Test status
Simulation time 186430084 ps
CPU time 0.85 seconds
Started Jul 15 07:05:01 PM PDT 24
Finished Jul 15 07:05:03 PM PDT 24
Peak memory 206832 kb
Host smart-8a7cc4c5-953d-4eb2-827c-b2c31df5bd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82731
5312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.827315312
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1745358022
Short name T658
Test name
Test status
Simulation time 192020609 ps
CPU time 0.86 seconds
Started Jul 15 07:05:02 PM PDT 24
Finished Jul 15 07:05:04 PM PDT 24
Peak memory 206808 kb
Host smart-26604a15-c859-4715-9f2d-caba2db3de7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17453
58022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1745358022
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.433992761
Short name T2320
Test name
Test status
Simulation time 393452474 ps
CPU time 1.13 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:01 PM PDT 24
Peak memory 206808 kb
Host smart-9e8f966c-f7d1-4bdb-afd3-2d63ff1d8678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43399
2761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.433992761
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3568921118
Short name T860
Test name
Test status
Simulation time 6942790352 ps
CPU time 62.74 seconds
Started Jul 15 07:05:03 PM PDT 24
Finished Jul 15 07:06:07 PM PDT 24
Peak memory 207080 kb
Host smart-45aaf026-d00b-4b46-a464-284f5a0644bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35689
21118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3568921118
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.877006373
Short name T1187
Test name
Test status
Simulation time 74607807 ps
CPU time 0.71 seconds
Started Jul 15 07:05:09 PM PDT 24
Finished Jul 15 07:05:11 PM PDT 24
Peak memory 206844 kb
Host smart-c6d7a405-8ada-47ad-a7c4-6301972e7244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=877006373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.877006373
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.951335923
Short name T2691
Test name
Test status
Simulation time 3767588564 ps
CPU time 4.2 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:05 PM PDT 24
Peak memory 207060 kb
Host smart-252ec012-af1c-43eb-8592-da6cacd429c4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=951335923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.951335923
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3554260847
Short name T2044
Test name
Test status
Simulation time 13409605075 ps
CPU time 12.82 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:14 PM PDT 24
Peak memory 207020 kb
Host smart-5f0e785b-965a-4ab7-90ef-16b3d7e3e53f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3554260847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3554260847
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1521279933
Short name T404
Test name
Test status
Simulation time 23303532834 ps
CPU time 23.04 seconds
Started Jul 15 07:05:03 PM PDT 24
Finished Jul 15 07:05:27 PM PDT 24
Peak memory 206880 kb
Host smart-e55c3f1c-2248-4cd7-a9b3-73ae68d74644
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1521279933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1521279933
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.679432149
Short name T389
Test name
Test status
Simulation time 150681666 ps
CPU time 0.81 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:02 PM PDT 24
Peak memory 206808 kb
Host smart-696c6b79-4827-4a49-ac92-f224a04d0b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67943
2149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.679432149
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2923940968
Short name T834
Test name
Test status
Simulation time 158626687 ps
CPU time 0.79 seconds
Started Jul 15 07:05:03 PM PDT 24
Finished Jul 15 07:05:04 PM PDT 24
Peak memory 206808 kb
Host smart-406c7c7c-3e3e-46ed-bbce-80f7517b67dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239
40968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2923940968
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.4265541552
Short name T2180
Test name
Test status
Simulation time 281368104 ps
CPU time 1.03 seconds
Started Jul 15 07:04:58 PM PDT 24
Finished Jul 15 07:05:00 PM PDT 24
Peak memory 206820 kb
Host smart-8f5ed098-feb1-4aa1-8022-9627531d5be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
41552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.4265541552
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3591232529
Short name T1302
Test name
Test status
Simulation time 1378563159 ps
CPU time 3.5 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:05 PM PDT 24
Peak memory 206948 kb
Host smart-b63bbcc7-e271-4e79-abb2-76aa07bdce5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
32529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3591232529
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.271341891
Short name T1346
Test name
Test status
Simulation time 8727752399 ps
CPU time 15.2 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:16 PM PDT 24
Peak memory 207020 kb
Host smart-1750bf50-62cd-4afb-985b-fbe76186d9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27134
1891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.271341891
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3516946106
Short name T2349
Test name
Test status
Simulation time 340038724 ps
CPU time 1.2 seconds
Started Jul 15 07:05:01 PM PDT 24
Finished Jul 15 07:05:03 PM PDT 24
Peak memory 206824 kb
Host smart-f95a8f30-c1e2-4ff7-84f8-9d96959d4dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35169
46106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3516946106
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.266921109
Short name T1649
Test name
Test status
Simulation time 142141537 ps
CPU time 0.83 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:02 PM PDT 24
Peak memory 206800 kb
Host smart-3c6cb9d8-18a3-411f-8bd7-5178c76be7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26692
1109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.266921109
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2106327728
Short name T1025
Test name
Test status
Simulation time 49863962 ps
CPU time 0.68 seconds
Started Jul 15 07:05:00 PM PDT 24
Finished Jul 15 07:05:02 PM PDT 24
Peak memory 206800 kb
Host smart-77ab0efb-3b7b-4a4d-ae7a-383454c6c544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21063
27728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2106327728
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3095437456
Short name T2558
Test name
Test status
Simulation time 916690780 ps
CPU time 2.18 seconds
Started Jul 15 07:04:59 PM PDT 24
Finished Jul 15 07:05:02 PM PDT 24
Peak memory 206944 kb
Host smart-3012c2c3-9038-47dd-9c46-645d17f2271f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30954
37456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3095437456
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2659578168
Short name T1912
Test name
Test status
Simulation time 234710078 ps
CPU time 1.91 seconds
Started Jul 15 07:05:01 PM PDT 24
Finished Jul 15 07:05:04 PM PDT 24
Peak memory 206932 kb
Host smart-f7731f44-659f-41a1-be28-8f1c1c3f702c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26595
78168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2659578168
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.764890377
Short name T312
Test name
Test status
Simulation time 151091128 ps
CPU time 0.85 seconds
Started Jul 15 07:05:02 PM PDT 24
Finished Jul 15 07:05:04 PM PDT 24
Peak memory 206840 kb
Host smart-b51b5374-7670-42cc-9dd5-12cc148eb271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76489
0377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.764890377
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3895682913
Short name T716
Test name
Test status
Simulation time 174482325 ps
CPU time 0.86 seconds
Started Jul 15 07:05:01 PM PDT 24
Finished Jul 15 07:05:04 PM PDT 24
Peak memory 206780 kb
Host smart-1e4106b9-6d66-4dd4-a968-e76dcb464148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38956
82913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3895682913
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2777602790
Short name T367
Test name
Test status
Simulation time 249095653 ps
CPU time 1.03 seconds
Started Jul 15 07:05:09 PM PDT 24
Finished Jul 15 07:05:11 PM PDT 24
Peak memory 206812 kb
Host smart-d93013f0-3f98-4f4e-a45f-da7d13b93d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27776
02790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2777602790
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1754990359
Short name T1522
Test name
Test status
Simulation time 7199355238 ps
CPU time 186.96 seconds
Started Jul 15 07:05:04 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 206960 kb
Host smart-46ac8c10-e932-406e-a351-91fe650e16a6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1754990359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1754990359
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.81830497
Short name T1057
Test name
Test status
Simulation time 7459775359 ps
CPU time 29.26 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:38 PM PDT 24
Peak memory 207084 kb
Host smart-e88a992f-245e-44ef-b56b-6195f304b3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81830
497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.81830497
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3642662881
Short name T1599
Test name
Test status
Simulation time 178067418 ps
CPU time 0.88 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:09 PM PDT 24
Peak memory 206800 kb
Host smart-a54f20ca-5466-40a2-a295-8c63ed70c11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36426
62881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3642662881
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2791534715
Short name T291
Test name
Test status
Simulation time 23323468550 ps
CPU time 20.46 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:29 PM PDT 24
Peak memory 206872 kb
Host smart-7c3ea694-d27f-4911-86e9-eb42529bf3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915
34715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2791534715
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.4217697975
Short name T2366
Test name
Test status
Simulation time 3388131676 ps
CPU time 4.06 seconds
Started Jul 15 07:05:10 PM PDT 24
Finished Jul 15 07:05:15 PM PDT 24
Peak memory 206864 kb
Host smart-d029728e-3d42-430a-ae21-93fd22f00ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42176
97975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.4217697975
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2797405998
Short name T1412
Test name
Test status
Simulation time 6230186485 ps
CPU time 171.79 seconds
Started Jul 15 07:05:10 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 207108 kb
Host smart-aedbce25-e4fd-421f-b397-d3642fe145f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974
05998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2797405998
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.1871124288
Short name T1358
Test name
Test status
Simulation time 3269263545 ps
CPU time 23.48 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:33 PM PDT 24
Peak memory 206800 kb
Host smart-6086ac98-15b7-42df-a26f-447dbbc0195b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1871124288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.1871124288
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3638314379
Short name T1432
Test name
Test status
Simulation time 247298056 ps
CPU time 0.95 seconds
Started Jul 15 07:05:06 PM PDT 24
Finished Jul 15 07:05:07 PM PDT 24
Peak memory 206808 kb
Host smart-21ed3980-9473-40c9-99db-44154784d8ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3638314379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3638314379
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2878963299
Short name T758
Test name
Test status
Simulation time 193847508 ps
CPU time 0.84 seconds
Started Jul 15 07:05:06 PM PDT 24
Finished Jul 15 07:05:08 PM PDT 24
Peak memory 206792 kb
Host smart-2a2993a1-bea8-411f-937c-97f099968e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
63299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2878963299
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4283264595
Short name T2432
Test name
Test status
Simulation time 4424170520 ps
CPU time 123.68 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:07:13 PM PDT 24
Peak memory 207044 kb
Host smart-f8989539-ce1b-46b7-8da0-86b751200b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42832
64595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4283264595
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.2964977874
Short name T1469
Test name
Test status
Simulation time 5377650563 ps
CPU time 155.58 seconds
Started Jul 15 07:05:11 PM PDT 24
Finished Jul 15 07:07:47 PM PDT 24
Peak memory 207060 kb
Host smart-7232d636-d134-448b-91cd-a79f3dff3000
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2964977874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2964977874
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3504833118
Short name T837
Test name
Test status
Simulation time 151179861 ps
CPU time 0.76 seconds
Started Jul 15 07:05:04 PM PDT 24
Finished Jul 15 07:05:05 PM PDT 24
Peak memory 206804 kb
Host smart-0c4d9706-17e6-435c-93f1-aace0e3a8bde
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3504833118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3504833118
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3351639131
Short name T2696
Test name
Test status
Simulation time 140745481 ps
CPU time 0.82 seconds
Started Jul 15 07:05:10 PM PDT 24
Finished Jul 15 07:05:11 PM PDT 24
Peak memory 206840 kb
Host smart-ed34ba9f-1b0c-465a-94aa-2d0e573dd71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33516
39131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3351639131
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3577774765
Short name T2677
Test name
Test status
Simulation time 164527073 ps
CPU time 0.82 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:09 PM PDT 24
Peak memory 206812 kb
Host smart-2b924a95-9245-4187-b739-7e83136f2462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35777
74765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3577774765
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1801842533
Short name T1040
Test name
Test status
Simulation time 168565948 ps
CPU time 0.81 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:10 PM PDT 24
Peak memory 206800 kb
Host smart-8350c65d-f22d-4f65-b25c-85feacac67d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18018
42533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1801842533
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.4059147163
Short name T687
Test name
Test status
Simulation time 172620796 ps
CPU time 0.89 seconds
Started Jul 15 07:05:10 PM PDT 24
Finished Jul 15 07:05:12 PM PDT 24
Peak memory 206768 kb
Host smart-816fe3cc-a46b-4625-ab79-b600d0ea1704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40591
47163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.4059147163
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.843194767
Short name T2172
Test name
Test status
Simulation time 189121173 ps
CPU time 0.81 seconds
Started Jul 15 07:05:06 PM PDT 24
Finished Jul 15 07:05:08 PM PDT 24
Peak memory 206800 kb
Host smart-109b5979-f5d6-461f-af5c-61eadf52d134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84319
4767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.843194767
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1921877003
Short name T1921
Test name
Test status
Simulation time 219631203 ps
CPU time 0.96 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:10 PM PDT 24
Peak memory 206796 kb
Host smart-26f226eb-106b-4765-81b6-ff5a1c58381a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1921877003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1921877003
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1993028295
Short name T1002
Test name
Test status
Simulation time 42828633 ps
CPU time 0.67 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:10 PM PDT 24
Peak memory 206792 kb
Host smart-2b88cb16-6d21-4ff5-bfa4-7cd335b3f74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19930
28295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1993028295
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.931219445
Short name T1371
Test name
Test status
Simulation time 9784260365 ps
CPU time 20.81 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 207056 kb
Host smart-3a14c34d-9a50-4688-b00c-200531d256e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93121
9445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.931219445
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.4143265338
Short name T454
Test name
Test status
Simulation time 149266487 ps
CPU time 0.78 seconds
Started Jul 15 07:05:06 PM PDT 24
Finished Jul 15 07:05:08 PM PDT 24
Peak memory 206832 kb
Host smart-8d4a0427-1ebf-4d34-92db-0290c128459f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41432
65338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.4143265338
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.4165768498
Short name T319
Test name
Test status
Simulation time 153927583 ps
CPU time 0.78 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:11 PM PDT 24
Peak memory 206808 kb
Host smart-981ef356-6afe-4a69-bec2-6a7a30ba2588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41657
68498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.4165768498
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.4228657488
Short name T1319
Test name
Test status
Simulation time 268096724 ps
CPU time 0.99 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:11 PM PDT 24
Peak memory 206796 kb
Host smart-523f8813-77d8-42a8-b693-d248bd3ff1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42286
57488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.4228657488
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2368496415
Short name T1902
Test name
Test status
Simulation time 184345297 ps
CPU time 0.84 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:09 PM PDT 24
Peak memory 206800 kb
Host smart-9cff6189-1373-43a3-a980-8bd0466fccd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23684
96415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2368496415
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.565173452
Short name T65
Test name
Test status
Simulation time 151984989 ps
CPU time 0.76 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:10 PM PDT 24
Peak memory 206508 kb
Host smart-019007c3-48e0-4464-ac63-f2e01161bedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56517
3452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.565173452
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.680115080
Short name T2620
Test name
Test status
Simulation time 173981384 ps
CPU time 0.78 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:08 PM PDT 24
Peak memory 206752 kb
Host smart-46b81866-3c6b-4fbc-9e2a-4637cd350a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68011
5080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.680115080
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1748096960
Short name T2276
Test name
Test status
Simulation time 156671381 ps
CPU time 0.79 seconds
Started Jul 15 07:05:10 PM PDT 24
Finished Jul 15 07:05:12 PM PDT 24
Peak memory 206836 kb
Host smart-bd7f6bc5-b6c7-4220-afe0-9a344116006e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17480
96960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1748096960
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.490876017
Short name T2583
Test name
Test status
Simulation time 258968842 ps
CPU time 1.07 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:05:11 PM PDT 24
Peak memory 206772 kb
Host smart-e9aa4d91-f009-4c84-a9a1-01854cc72cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49087
6017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.490876017
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2999796249
Short name T1981
Test name
Test status
Simulation time 5024806424 ps
CPU time 141.19 seconds
Started Jul 15 07:05:09 PM PDT 24
Finished Jul 15 07:07:31 PM PDT 24
Peak memory 207064 kb
Host smart-c1541293-b29b-4d4d-a2eb-e7b4a5cf614b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2999796249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2999796249
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2913276933
Short name T2503
Test name
Test status
Simulation time 182803718 ps
CPU time 0.8 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:09 PM PDT 24
Peak memory 206808 kb
Host smart-56636cb6-8eac-44f9-a1a3-d543063eaeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29132
76933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2913276933
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.290545234
Short name T688
Test name
Test status
Simulation time 181729604 ps
CPU time 0.81 seconds
Started Jul 15 07:05:09 PM PDT 24
Finished Jul 15 07:05:11 PM PDT 24
Peak memory 206784 kb
Host smart-61b8915a-f0dd-49c3-9764-918374958a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29054
5234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.290545234
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.2853975130
Short name T868
Test name
Test status
Simulation time 854448384 ps
CPU time 1.88 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:10 PM PDT 24
Peak memory 207008 kb
Host smart-c6fac168-74fc-4abe-bb6a-4482287fad3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
75130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.2853975130
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1912090209
Short name T1815
Test name
Test status
Simulation time 6345350294 ps
CPU time 174.76 seconds
Started Jul 15 07:05:08 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 207016 kb
Host smart-b4e590fd-4c89-4e8f-bc41-b791d785b0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19120
90209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1912090209
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.2654981672
Short name T2662
Test name
Test status
Simulation time 55431145 ps
CPU time 0.72 seconds
Started Jul 15 07:05:25 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206868 kb
Host smart-b540d4ad-31e9-4cc9-bb64-63cf52be3380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2654981672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2654981672
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.186763278
Short name T2649
Test name
Test status
Simulation time 4366297629 ps
CPU time 4.78 seconds
Started Jul 15 07:05:10 PM PDT 24
Finished Jul 15 07:05:16 PM PDT 24
Peak memory 206976 kb
Host smart-11553e49-def0-4738-8802-72880be05d19
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=186763278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.186763278
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.359665965
Short name T9
Test name
Test status
Simulation time 13295125136 ps
CPU time 11.95 seconds
Started Jul 15 07:05:07 PM PDT 24
Finished Jul 15 07:05:21 PM PDT 24
Peak memory 206856 kb
Host smart-210cf661-a257-4ec0-8bcb-c91bed293819
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=359665965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.359665965
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.631784778
Short name T2652
Test name
Test status
Simulation time 23387505455 ps
CPU time 23.79 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:47 PM PDT 24
Peak memory 206896 kb
Host smart-c8c29865-3ccc-4660-a152-4f583de36f9f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=631784778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.631784778
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.84474025
Short name T976
Test name
Test status
Simulation time 192567364 ps
CPU time 0.86 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:23 PM PDT 24
Peak memory 206824 kb
Host smart-56de407f-2709-4da7-a56d-cead68f96160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84474
025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.84474025
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3230893776
Short name T671
Test name
Test status
Simulation time 165419240 ps
CPU time 0.82 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:22 PM PDT 24
Peak memory 206808 kb
Host smart-c3c57a9d-0dee-4462-ad7e-fdb638b1a01a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32308
93776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3230893776
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2944756574
Short name T1919
Test name
Test status
Simulation time 393515888 ps
CPU time 1.36 seconds
Started Jul 15 07:05:21 PM PDT 24
Finished Jul 15 07:05:24 PM PDT 24
Peak memory 206812 kb
Host smart-14ba309c-7c6f-40ec-b958-d4b50763a5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29447
56574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2944756574
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3760947926
Short name T2271
Test name
Test status
Simulation time 1168674883 ps
CPU time 2.73 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206992 kb
Host smart-b551de8a-3c9c-4306-8c86-f97d1fffc1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
47926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3760947926
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.701827835
Short name T817
Test name
Test status
Simulation time 6852840968 ps
CPU time 15.85 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:37 PM PDT 24
Peak memory 207020 kb
Host smart-16df6077-1426-494d-b076-6c8f19c7cc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70182
7835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.701827835
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1088300021
Short name T1699
Test name
Test status
Simulation time 425588982 ps
CPU time 1.3 seconds
Started Jul 15 07:05:21 PM PDT 24
Finished Jul 15 07:05:24 PM PDT 24
Peak memory 206800 kb
Host smart-99c390a3-3207-4a4f-b8fd-c618ad434fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
00021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1088300021
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.759126981
Short name T1373
Test name
Test status
Simulation time 146274276 ps
CPU time 0.78 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:22 PM PDT 24
Peak memory 206784 kb
Host smart-46e0b060-a05b-40b5-b261-220abb675e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75912
6981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.759126981
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.892994578
Short name T2237
Test name
Test status
Simulation time 35764272 ps
CPU time 0.67 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:21 PM PDT 24
Peak memory 206832 kb
Host smart-42be6a42-f021-4dfe-b8aa-f81a122d3253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89299
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.892994578
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.444007270
Short name T306
Test name
Test status
Simulation time 871067994 ps
CPU time 2.04 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:24 PM PDT 24
Peak memory 206948 kb
Host smart-e34cfb8d-10f1-4596-8940-c06020795178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44400
7270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.444007270
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.4060599988
Short name T1278
Test name
Test status
Simulation time 195074287 ps
CPU time 2.19 seconds
Started Jul 15 07:05:19 PM PDT 24
Finished Jul 15 07:05:22 PM PDT 24
Peak memory 207000 kb
Host smart-d500b5c0-3dec-49e7-a781-4193e2d81387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40605
99988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.4060599988
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.323503952
Short name T2738
Test name
Test status
Simulation time 269956603 ps
CPU time 0.95 seconds
Started Jul 15 07:05:19 PM PDT 24
Finished Jul 15 07:05:21 PM PDT 24
Peak memory 206824 kb
Host smart-d0afb5f5-99f2-4b3c-aec2-a3447e8a8fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32350
3952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.323503952
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2463266913
Short name T1606
Test name
Test status
Simulation time 152828704 ps
CPU time 0.78 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:21 PM PDT 24
Peak memory 206796 kb
Host smart-c660aa63-7a2e-44cf-aa00-2b8094fd2cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24632
66913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2463266913
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1976172195
Short name T945
Test name
Test status
Simulation time 220117892 ps
CPU time 0.91 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:23 PM PDT 24
Peak memory 206800 kb
Host smart-9d80365c-21e3-4f5f-a8a4-6b8731a6dde3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19761
72195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1976172195
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.3601955337
Short name T2233
Test name
Test status
Simulation time 7407525642 ps
CPU time 61.63 seconds
Started Jul 15 07:05:19 PM PDT 24
Finished Jul 15 07:06:21 PM PDT 24
Peak memory 207020 kb
Host smart-f760affb-b8e7-48d0-b674-af8888cb7893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36019
55337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3601955337
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3256589709
Short name T382
Test name
Test status
Simulation time 207390358 ps
CPU time 0.9 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:23 PM PDT 24
Peak memory 206792 kb
Host smart-33f8f2fa-894d-4002-bc69-203ca9740e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32565
89709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3256589709
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.1916560721
Short name T1125
Test name
Test status
Simulation time 23297682885 ps
CPU time 22.78 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:45 PM PDT 24
Peak memory 206872 kb
Host smart-589abbf6-0ed9-4a4c-8523-953be9577b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19165
60721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.1916560721
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2026562151
Short name T553
Test name
Test status
Simulation time 3329330984 ps
CPU time 3.93 seconds
Started Jul 15 07:05:21 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206888 kb
Host smart-b976e2d5-f6a4-42ea-b868-72f64c249b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20265
62151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2026562151
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3982050460
Short name T896
Test name
Test status
Simulation time 14280445107 ps
CPU time 101.96 seconds
Started Jul 15 07:05:19 PM PDT 24
Finished Jul 15 07:07:02 PM PDT 24
Peak memory 207064 kb
Host smart-97bbf07c-be43-4590-8769-710a6c47787f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39820
50460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3982050460
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2875106318
Short name T2699
Test name
Test status
Simulation time 4776075957 ps
CPU time 138.03 seconds
Started Jul 15 07:05:21 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 207012 kb
Host smart-565722f3-299a-4211-996e-18e7567467f1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2875106318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2875106318
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2604073083
Short name T893
Test name
Test status
Simulation time 243294320 ps
CPU time 0.9 seconds
Started Jul 15 07:05:21 PM PDT 24
Finished Jul 15 07:05:23 PM PDT 24
Peak memory 206832 kb
Host smart-f938d6a8-f015-48c4-8214-b465e46f740d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2604073083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2604073083
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2678944309
Short name T1192
Test name
Test status
Simulation time 189060044 ps
CPU time 0.86 seconds
Started Jul 15 07:05:18 PM PDT 24
Finished Jul 15 07:05:20 PM PDT 24
Peak memory 206780 kb
Host smart-424eefd5-d0dc-4502-a8f4-6ecaea900d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26789
44309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2678944309
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1762875188
Short name T969
Test name
Test status
Simulation time 6451369090 ps
CPU time 182.43 seconds
Started Jul 15 07:05:21 PM PDT 24
Finished Jul 15 07:08:24 PM PDT 24
Peak memory 206988 kb
Host smart-472f7f3f-65a1-4784-a325-2f2fdab227e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17628
75188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1762875188
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.1974106680
Short name T639
Test name
Test status
Simulation time 3361780118 ps
CPU time 24.58 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206980 kb
Host smart-9478f74f-7968-46ca-9da3-7ce3eff155a2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1974106680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.1974106680
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2139160920
Short name T1069
Test name
Test status
Simulation time 165246262 ps
CPU time 0.77 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206824 kb
Host smart-c1dbbf4a-6815-48ca-9a5a-676abadeff49
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2139160920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2139160920
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3918341464
Short name T1241
Test name
Test status
Simulation time 150968262 ps
CPU time 0.81 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:22 PM PDT 24
Peak memory 206844 kb
Host smart-789a1776-af0d-4db3-a2fd-48f331811cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39183
41464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3918341464
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3904927763
Short name T1664
Test name
Test status
Simulation time 185268929 ps
CPU time 0.84 seconds
Started Jul 15 07:05:19 PM PDT 24
Finished Jul 15 07:05:20 PM PDT 24
Peak memory 206828 kb
Host smart-748e48dd-84b2-4d22-a53e-dba1bdf83efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39049
27763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3904927763
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3846200190
Short name T2654
Test name
Test status
Simulation time 187722680 ps
CPU time 0.81 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:21 PM PDT 24
Peak memory 206804 kb
Host smart-83114097-c95f-47a7-aabc-ba6ca329f4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38462
00190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3846200190
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3435320002
Short name T2711
Test name
Test status
Simulation time 177019176 ps
CPU time 0.83 seconds
Started Jul 15 07:05:19 PM PDT 24
Finished Jul 15 07:05:20 PM PDT 24
Peak memory 206760 kb
Host smart-8724abfc-9c0d-480d-97f2-417dc0ac25b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34353
20002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3435320002
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.520193012
Short name T2466
Test name
Test status
Simulation time 173456921 ps
CPU time 0.85 seconds
Started Jul 15 07:05:21 PM PDT 24
Finished Jul 15 07:05:23 PM PDT 24
Peak memory 206780 kb
Host smart-9b6289c7-8ce8-4112-bd04-c227426dabb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52019
3012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.520193012
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3745378895
Short name T2037
Test name
Test status
Simulation time 154146768 ps
CPU time 0.79 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206764 kb
Host smart-ad230bd1-cf98-46db-b952-ee3c4b27fde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37453
78895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3745378895
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.1538977097
Short name T1943
Test name
Test status
Simulation time 279584719 ps
CPU time 1.01 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206772 kb
Host smart-c70841df-4617-444e-9815-6bdee474a8f9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1538977097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.1538977097
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.4121099866
Short name T1984
Test name
Test status
Simulation time 144413444 ps
CPU time 0.79 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206828 kb
Host smart-c2b8ccea-5b89-4b95-bbc2-2d9ce36d1c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41210
99866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.4121099866
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1392427942
Short name T483
Test name
Test status
Simulation time 48529918 ps
CPU time 0.64 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206776 kb
Host smart-3e5d9a72-c085-49dd-891f-05db26b7cf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13924
27942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1392427942
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3328694201
Short name T2712
Test name
Test status
Simulation time 6162795933 ps
CPU time 13.39 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:39 PM PDT 24
Peak memory 207044 kb
Host smart-6a3a2a93-6a28-4cb5-b6f9-e7751b437422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33286
94201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3328694201
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1793719046
Short name T2118
Test name
Test status
Simulation time 150254966 ps
CPU time 0.77 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206800 kb
Host smart-df549623-38a6-4c78-a76f-8dc8cb0e948d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937
19046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1793719046
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.488573620
Short name T1642
Test name
Test status
Simulation time 227396198 ps
CPU time 0.86 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206832 kb
Host smart-850faef0-10b8-4409-af92-1e6aa92a3546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48857
3620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.488573620
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.1193060531
Short name T345
Test name
Test status
Simulation time 220537029 ps
CPU time 0.89 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:05:24 PM PDT 24
Peak memory 206828 kb
Host smart-852beb93-5aee-405a-b201-7c37b7553c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11930
60531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1193060531
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2633981426
Short name T1880
Test name
Test status
Simulation time 155839478 ps
CPU time 0.86 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:22 PM PDT 24
Peak memory 206800 kb
Host smart-2814a1b1-1cc0-4765-baa6-cf3574f783bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339
81426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2633981426
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.502056923
Short name T2238
Test name
Test status
Simulation time 135286151 ps
CPU time 0.79 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206604 kb
Host smart-824c51e8-fb96-4ba6-af5b-9bf0e3e385c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50205
6923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.502056923
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2063486306
Short name T1979
Test name
Test status
Simulation time 149560106 ps
CPU time 0.78 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:05:24 PM PDT 24
Peak memory 206780 kb
Host smart-fe99301e-8489-4e13-a21a-10a8c20b6422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20634
86306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2063486306
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3872821806
Short name T2178
Test name
Test status
Simulation time 180987914 ps
CPU time 0.79 seconds
Started Jul 15 07:05:27 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206804 kb
Host smart-c3ce8639-bb4f-41ae-ad11-9b5b32740731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38728
21806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3872821806
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.271120079
Short name T700
Test name
Test status
Simulation time 220819431 ps
CPU time 0.85 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:27 PM PDT 24
Peak memory 206800 kb
Host smart-73d00515-bdf7-4aff-9db5-03c3f9c18a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27112
0079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.271120079
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1331546048
Short name T692
Test name
Test status
Simulation time 4098372419 ps
CPU time 113.41 seconds
Started Jul 15 07:05:21 PM PDT 24
Finished Jul 15 07:07:15 PM PDT 24
Peak memory 207004 kb
Host smart-5b6086b6-0476-4c4a-804f-690275d7d9ae
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1331546048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1331546048
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1352586455
Short name T576
Test name
Test status
Simulation time 204494245 ps
CPU time 0.86 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:05:21 PM PDT 24
Peak memory 206756 kb
Host smart-adc05ac1-8e81-4319-aa3b-ce542591ae2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13525
86455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1352586455
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2110150532
Short name T2327
Test name
Test status
Simulation time 179074838 ps
CPU time 0.81 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206808 kb
Host smart-1f23cb5e-38c3-49c7-8e22-bbb0b42c01d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21101
50532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2110150532
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1172640600
Short name T2205
Test name
Test status
Simulation time 262008403 ps
CPU time 1.02 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206796 kb
Host smart-ac6a3d92-5b82-48d5-bdd6-a9f827518857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11726
40600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1172640600
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2492268703
Short name T2241
Test name
Test status
Simulation time 6104389687 ps
CPU time 43.37 seconds
Started Jul 15 07:05:20 PM PDT 24
Finished Jul 15 07:06:05 PM PDT 24
Peak memory 207084 kb
Host smart-553f3169-7214-4d89-a10c-0e317015cff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24922
68703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2492268703
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2229152929
Short name T1545
Test name
Test status
Simulation time 54266296 ps
CPU time 0.68 seconds
Started Jul 15 07:05:30 PM PDT 24
Finished Jul 15 07:05:32 PM PDT 24
Peak memory 206864 kb
Host smart-7fdf0629-90b0-42b1-a84c-c3ac6450f29d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2229152929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2229152929
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1778715063
Short name T2351
Test name
Test status
Simulation time 3992900792 ps
CPU time 4.96 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206768 kb
Host smart-7714aea0-d93d-4457-ae9e-568fa93ffea8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1778715063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1778715063
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1465029031
Short name T2212
Test name
Test status
Simulation time 13395231741 ps
CPU time 13.25 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:05:36 PM PDT 24
Peak memory 206772 kb
Host smart-f1d88618-a211-480a-9059-d0ae2d44e9c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1465029031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1465029031
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1982295687
Short name T2458
Test name
Test status
Simulation time 23304980425 ps
CPU time 23.34 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:50 PM PDT 24
Peak memory 206832 kb
Host smart-aef1fc12-cf48-4f26-aba5-08144f094186
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1982295687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1982295687
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3726469997
Short name T1353
Test name
Test status
Simulation time 158583415 ps
CPU time 0.82 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206824 kb
Host smart-e44616b6-0f7a-44bb-8d88-5f10152d2b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37264
69997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3726469997
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.639364640
Short name T2505
Test name
Test status
Simulation time 159732059 ps
CPU time 0.78 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:05:24 PM PDT 24
Peak memory 206828 kb
Host smart-47885962-926c-412e-8e48-11a019e58502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63936
4640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.639364640
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3237344692
Short name T1145
Test name
Test status
Simulation time 300276059 ps
CPU time 1.09 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206788 kb
Host smart-ee12d331-ba0d-4711-ba90-7ccca9589875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32373
44692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3237344692
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2560662442
Short name T2008
Test name
Test status
Simulation time 986747775 ps
CPU time 2.27 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:27 PM PDT 24
Peak memory 206956 kb
Host smart-0c68b583-00ab-49e4-b9dd-4b451bb6b01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25606
62442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2560662442
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.555109506
Short name T2537
Test name
Test status
Simulation time 6665253313 ps
CPU time 12.29 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:38 PM PDT 24
Peak memory 207080 kb
Host smart-36ca84db-1c9e-449a-8530-14efecb98af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55510
9506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.555109506
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1825701167
Short name T1819
Test name
Test status
Simulation time 507874028 ps
CPU time 1.5 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:25 PM PDT 24
Peak memory 206832 kb
Host smart-98c8a4f9-4c92-4283-b660-5b5deae06304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18257
01167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1825701167
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3978661497
Short name T467
Test name
Test status
Simulation time 149807768 ps
CPU time 0.76 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:05:24 PM PDT 24
Peak memory 206828 kb
Host smart-5fba8e22-0482-4359-b7f0-d6db85c13cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39786
61497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3978661497
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.4180840432
Short name T2114
Test name
Test status
Simulation time 28729849 ps
CPU time 0.63 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:25 PM PDT 24
Peak memory 206608 kb
Host smart-e4ad2934-9359-4605-896c-539fa1e214b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41808
40432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.4180840432
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3761544678
Short name T1026
Test name
Test status
Simulation time 853957664 ps
CPU time 1.93 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 207012 kb
Host smart-a77c5d7d-39df-4f56-b82c-c6e757487463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
44678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3761544678
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.339800010
Short name T2358
Test name
Test status
Simulation time 223209233 ps
CPU time 1.52 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:27 PM PDT 24
Peak memory 207008 kb
Host smart-391ddf5b-6f7c-498a-9ef2-68968952382d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33980
0010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.339800010
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.4088764269
Short name T2062
Test name
Test status
Simulation time 263504325 ps
CPU time 0.98 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206824 kb
Host smart-9d6e02f9-d163-4ed1-85a2-f34331b73c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40887
64269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.4088764269
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2658656150
Short name T105
Test name
Test status
Simulation time 148968568 ps
CPU time 0.77 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206816 kb
Host smart-1a8a126d-8d8b-498d-bc8f-722557679f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26586
56150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2658656150
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1546744032
Short name T1117
Test name
Test status
Simulation time 210941082 ps
CPU time 0.92 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:05:24 PM PDT 24
Peak memory 206820 kb
Host smart-b6fa0b7c-ef72-449a-afc3-bdf7ff4fbc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15467
44032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1546744032
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.1179432649
Short name T102
Test name
Test status
Simulation time 5004748580 ps
CPU time 46.78 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 207060 kb
Host smart-db732dfa-9e8e-4326-843b-859344d823c4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1179432649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1179432649
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.3709182414
Short name T2023
Test name
Test status
Simulation time 13664856826 ps
CPU time 106.38 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:07:11 PM PDT 24
Peak memory 207008 kb
Host smart-7855bcee-14ef-40f7-90b7-a49f651ba0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37091
82414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3709182414
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2510174186
Short name T2589
Test name
Test status
Simulation time 196660648 ps
CPU time 0.86 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206772 kb
Host smart-59a5d316-3782-4745-8cac-a72885060045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25101
74186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2510174186
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3296450941
Short name T2390
Test name
Test status
Simulation time 23342572941 ps
CPU time 23 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206884 kb
Host smart-5702044a-8882-4ca0-b969-942d30eec022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32964
50941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3296450941
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.4256870838
Short name T2457
Test name
Test status
Simulation time 3414762257 ps
CPU time 3.99 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206856 kb
Host smart-2140700f-69d5-47bd-855a-1c2e3da0b5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42568
70838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.4256870838
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.725547561
Short name T965
Test name
Test status
Simulation time 8938070089 ps
CPU time 248.73 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:09:33 PM PDT 24
Peak memory 207064 kb
Host smart-5607554a-19d9-4fa8-9218-a8c361af8587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72554
7561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.725547561
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2134668465
Short name T1455
Test name
Test status
Simulation time 4592290109 ps
CPU time 43.22 seconds
Started Jul 15 07:05:22 PM PDT 24
Finished Jul 15 07:06:07 PM PDT 24
Peak memory 207036 kb
Host smart-05313970-21c4-4dbc-bad6-4b13e1c6b844
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2134668465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2134668465
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1085440063
Short name T287
Test name
Test status
Simulation time 290074203 ps
CPU time 0.96 seconds
Started Jul 15 07:05:28 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206784 kb
Host smart-34b04413-5b49-48a6-bd9c-23f8e94ec91f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1085440063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1085440063
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.411259948
Short name T2377
Test name
Test status
Simulation time 236043426 ps
CPU time 0.9 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:25 PM PDT 24
Peak memory 206812 kb
Host smart-ea5f21e6-1f1c-43d4-afa6-360c69101144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41125
9948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.411259948
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3209899244
Short name T1508
Test name
Test status
Simulation time 5803492974 ps
CPU time 40.37 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:06:05 PM PDT 24
Peak memory 206980 kb
Host smart-63a28bf8-37de-49f2-ac8f-3fff5ad33ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32098
99244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3209899244
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2547356205
Short name T1969
Test name
Test status
Simulation time 5010538428 ps
CPU time 35.27 seconds
Started Jul 15 07:05:27 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 207060 kb
Host smart-eb4b21a1-f0d5-4209-8050-82ea4aed3829
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2547356205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2547356205
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.536804725
Short name T448
Test name
Test status
Simulation time 186387134 ps
CPU time 0.81 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206648 kb
Host smart-512034be-8dce-46f9-9124-44f2251a77fa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=536804725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.536804725
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1071924096
Short name T723
Test name
Test status
Simulation time 138869569 ps
CPU time 0.77 seconds
Started Jul 15 07:05:26 PM PDT 24
Finished Jul 15 07:05:28 PM PDT 24
Peak memory 206816 kb
Host smart-6581ed18-7f72-4296-a4d4-9375bfcb6f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10719
24096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1071924096
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1868350770
Short name T1661
Test name
Test status
Simulation time 151363062 ps
CPU time 0.79 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:25 PM PDT 24
Peak memory 206676 kb
Host smart-4abfd52c-810b-4c7f-8ca2-86c2e01a1edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18683
50770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1868350770
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3078432663
Short name T2120
Test name
Test status
Simulation time 188249010 ps
CPU time 0.82 seconds
Started Jul 15 07:05:23 PM PDT 24
Finished Jul 15 07:05:25 PM PDT 24
Peak memory 206804 kb
Host smart-e461964d-f4ec-49e2-bab3-2baa74c4b0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30784
32663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3078432663
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.212863704
Short name T2063
Test name
Test status
Simulation time 182694973 ps
CPU time 0.81 seconds
Started Jul 15 07:05:24 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 206772 kb
Host smart-3d60978d-7847-4235-95e7-b3fbace9a908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21286
3704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.212863704
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3369448716
Short name T1561
Test name
Test status
Simulation time 158911496 ps
CPU time 0.8 seconds
Started Jul 15 07:05:28 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206816 kb
Host smart-b5e0179a-b9e4-4009-8cfa-4661a268e559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33694
48716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3369448716
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1606343413
Short name T624
Test name
Test status
Simulation time 211056905 ps
CPU time 0.91 seconds
Started Jul 15 07:05:28 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206812 kb
Host smart-5ac55925-e215-4724-8ae1-dc481b018992
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1606343413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1606343413
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3434068483
Short name T2694
Test name
Test status
Simulation time 142036283 ps
CPU time 0.78 seconds
Started Jul 15 07:05:29 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206968 kb
Host smart-e1305aab-a4ea-42fa-8ef7-dc09eba24019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34340
68483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3434068483
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.995616061
Short name T2158
Test name
Test status
Simulation time 75281929 ps
CPU time 0.71 seconds
Started Jul 15 07:05:29 PM PDT 24
Finished Jul 15 07:05:31 PM PDT 24
Peak memory 206804 kb
Host smart-48abd0b6-8a4f-44dd-bbc5-6b43dff0efb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99561
6061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.995616061
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1167355284
Short name T2673
Test name
Test status
Simulation time 22361239831 ps
CPU time 44.19 seconds
Started Jul 15 07:05:34 PM PDT 24
Finished Jul 15 07:06:19 PM PDT 24
Peak memory 207064 kb
Host smart-0fe615d3-216a-402e-9a2c-49e5bfb75f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11673
55284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1167355284
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3560362716
Short name T614
Test name
Test status
Simulation time 152343998 ps
CPU time 0.81 seconds
Started Jul 15 07:05:28 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206704 kb
Host smart-67d5d2ce-18f7-40d5-b419-6b56c98ae3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35603
62716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3560362716
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1097568089
Short name T381
Test name
Test status
Simulation time 198744532 ps
CPU time 0.87 seconds
Started Jul 15 07:05:27 PM PDT 24
Finished Jul 15 07:05:29 PM PDT 24
Peak memory 206800 kb
Host smart-87a20986-2dc6-4737-b578-cb1666786427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10975
68089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1097568089
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.1461516747
Short name T2278
Test name
Test status
Simulation time 160103381 ps
CPU time 0.84 seconds
Started Jul 15 07:05:30 PM PDT 24
Finished Jul 15 07:05:32 PM PDT 24
Peak memory 206824 kb
Host smart-cce15a4f-1d95-43fa-b4ad-ea62fc5ed545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14615
16747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.1461516747
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1538683173
Short name T2455
Test name
Test status
Simulation time 159309931 ps
CPU time 0.82 seconds
Started Jul 15 07:05:31 PM PDT 24
Finished Jul 15 07:05:33 PM PDT 24
Peak memory 206828 kb
Host smart-c39f31ef-6241-4c00-b575-443011feed76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15386
83173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1538683173
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2420402132
Short name T1293
Test name
Test status
Simulation time 194790029 ps
CPU time 0.86 seconds
Started Jul 15 07:05:30 PM PDT 24
Finished Jul 15 07:05:32 PM PDT 24
Peak memory 206820 kb
Host smart-c825907f-f5d9-44e1-881d-adc8fb9234c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24204
02132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2420402132
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2519073767
Short name T556
Test name
Test status
Simulation time 152285872 ps
CPU time 0.93 seconds
Started Jul 15 07:05:28 PM PDT 24
Finished Jul 15 07:05:29 PM PDT 24
Peak memory 206760 kb
Host smart-78c1dbd6-90ac-4625-b41f-fab4cd39f90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25190
73767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2519073767
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.901144831
Short name T415
Test name
Test status
Simulation time 154722301 ps
CPU time 0.79 seconds
Started Jul 15 07:05:30 PM PDT 24
Finished Jul 15 07:05:32 PM PDT 24
Peak memory 206792 kb
Host smart-c839f284-9fc3-41d0-88d5-d9de78585bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90114
4831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.901144831
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1120608487
Short name T1764
Test name
Test status
Simulation time 266383265 ps
CPU time 1.01 seconds
Started Jul 15 07:05:28 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206784 kb
Host smart-32dec651-c875-4c8c-b608-fe9f81c47ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11206
08487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1120608487
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.4014107262
Short name T1509
Test name
Test status
Simulation time 5058720395 ps
CPU time 47.26 seconds
Started Jul 15 07:05:31 PM PDT 24
Finished Jul 15 07:06:19 PM PDT 24
Peak memory 207004 kb
Host smart-58139a24-b446-47ee-90c9-2f50e2e031ff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4014107262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.4014107262
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2506936168
Short name T2079
Test name
Test status
Simulation time 175693113 ps
CPU time 0.84 seconds
Started Jul 15 07:05:30 PM PDT 24
Finished Jul 15 07:05:32 PM PDT 24
Peak memory 206828 kb
Host smart-0f34bdee-8ba5-4496-ae94-214ab7f25f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25069
36168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2506936168
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3446656763
Short name T31
Test name
Test status
Simulation time 193698303 ps
CPU time 0.82 seconds
Started Jul 15 07:05:29 PM PDT 24
Finished Jul 15 07:05:31 PM PDT 24
Peak memory 206840 kb
Host smart-1d2ee113-0eb8-41f3-978e-d6225c616ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34466
56763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3446656763
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.706162774
Short name T2075
Test name
Test status
Simulation time 202049439 ps
CPU time 0.89 seconds
Started Jul 15 07:05:32 PM PDT 24
Finished Jul 15 07:05:33 PM PDT 24
Peak memory 206828 kb
Host smart-5539213e-ec4d-46b1-b458-6fe70d2a73b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70616
2774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.706162774
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.304176563
Short name T1924
Test name
Test status
Simulation time 5139521159 ps
CPU time 44.59 seconds
Started Jul 15 07:05:30 PM PDT 24
Finished Jul 15 07:06:15 PM PDT 24
Peak memory 207016 kb
Host smart-f365999b-02fa-4970-bf5c-a0e90e31f7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30417
6563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.304176563
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.522616736
Short name T1585
Test name
Test status
Simulation time 51924942 ps
CPU time 0.68 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:44 PM PDT 24
Peak memory 206836 kb
Host smart-05840ac0-cff8-4f43-bea3-de08535dcbca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=522616736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.522616736
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.4021498116
Short name T2365
Test name
Test status
Simulation time 3785181963 ps
CPU time 4.29 seconds
Started Jul 15 07:05:32 PM PDT 24
Finished Jul 15 07:05:37 PM PDT 24
Peak memory 207092 kb
Host smart-432c3fc9-9400-4275-98d9-a6b4ad543140
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4021498116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.4021498116
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.4155106382
Short name T2018
Test name
Test status
Simulation time 13506120317 ps
CPU time 13.72 seconds
Started Jul 15 07:05:27 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 207064 kb
Host smart-a1b53fac-2a0c-441b-9b45-5b0dce7f78c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4155106382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.4155106382
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.997614876
Short name T1583
Test name
Test status
Simulation time 23343813430 ps
CPU time 25.07 seconds
Started Jul 15 07:05:30 PM PDT 24
Finished Jul 15 07:05:56 PM PDT 24
Peak memory 206832 kb
Host smart-f232ec5a-431a-40b0-99e7-54aedc75288b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=997614876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.997614876
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2837978909
Short name T1047
Test name
Test status
Simulation time 162723295 ps
CPU time 0.83 seconds
Started Jul 15 07:05:31 PM PDT 24
Finished Jul 15 07:05:33 PM PDT 24
Peak memory 206820 kb
Host smart-37bb1230-65ef-4785-8d46-e1f58863aefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28379
78909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2837978909
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3278042694
Short name T819
Test name
Test status
Simulation time 147108587 ps
CPU time 0.74 seconds
Started Jul 15 07:05:28 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206824 kb
Host smart-aa793055-1397-4ef4-bf41-c88eedb48aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32780
42694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3278042694
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.924599427
Short name T2623
Test name
Test status
Simulation time 428953979 ps
CPU time 1.42 seconds
Started Jul 15 07:05:27 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206816 kb
Host smart-9612b363-887d-420c-b5a6-172853856271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92459
9427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.924599427
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2023903591
Short name T829
Test name
Test status
Simulation time 757002707 ps
CPU time 1.8 seconds
Started Jul 15 07:05:29 PM PDT 24
Finished Jul 15 07:05:31 PM PDT 24
Peak memory 207028 kb
Host smart-a421cda4-1816-46a8-8b58-3df71db99ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20239
03591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2023903591
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2017386054
Short name T2629
Test name
Test status
Simulation time 6770906771 ps
CPU time 12.01 seconds
Started Jul 15 07:05:28 PM PDT 24
Finished Jul 15 07:05:41 PM PDT 24
Peak memory 206992 kb
Host smart-b91677d0-d967-4c60-8809-22ba99a568fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20173
86054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2017386054
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3213890715
Short name T1343
Test name
Test status
Simulation time 386892274 ps
CPU time 1.41 seconds
Started Jul 15 07:05:27 PM PDT 24
Finished Jul 15 07:05:30 PM PDT 24
Peak memory 206788 kb
Host smart-49a6e7f9-6e4b-4153-8a72-019c2186f595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138
90715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3213890715
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1040247038
Short name T1831
Test name
Test status
Simulation time 137831609 ps
CPU time 0.78 seconds
Started Jul 15 07:05:29 PM PDT 24
Finished Jul 15 07:05:31 PM PDT 24
Peak memory 206812 kb
Host smart-bfff745c-2a9a-453e-b265-1a88d31d2c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10402
47038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1040247038
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3974953653
Short name T774
Test name
Test status
Simulation time 33976473 ps
CPU time 0.65 seconds
Started Jul 15 07:05:35 PM PDT 24
Finished Jul 15 07:05:36 PM PDT 24
Peak memory 206816 kb
Host smart-3cdccda0-a95e-468c-a092-028af6844fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39749
53653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3974953653
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1275531097
Short name T1124
Test name
Test status
Simulation time 801848239 ps
CPU time 1.86 seconds
Started Jul 15 07:05:41 PM PDT 24
Finished Jul 15 07:05:45 PM PDT 24
Peak memory 206960 kb
Host smart-94f309d1-21dd-47a2-a5bf-561e5c9fd7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12755
31097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1275531097
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3500567521
Short name T79
Test name
Test status
Simulation time 151514944 ps
CPU time 1.27 seconds
Started Jul 15 07:05:34 PM PDT 24
Finished Jul 15 07:05:36 PM PDT 24
Peak memory 207044 kb
Host smart-86c6f498-cf43-4328-9557-8911bfac8d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35005
67521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3500567521
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3667637171
Short name T2036
Test name
Test status
Simulation time 230114668 ps
CPU time 0.9 seconds
Started Jul 15 07:05:33 PM PDT 24
Finished Jul 15 07:05:34 PM PDT 24
Peak memory 206804 kb
Host smart-bc516b55-0800-4c81-9717-9258f551b78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
37171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3667637171
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.4211584848
Short name T1384
Test name
Test status
Simulation time 154607217 ps
CPU time 0.81 seconds
Started Jul 15 07:05:35 PM PDT 24
Finished Jul 15 07:05:37 PM PDT 24
Peak memory 206828 kb
Host smart-5a131c6f-9a13-4bce-8878-e49cc66ff6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42115
84848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.4211584848
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1305830908
Short name T400
Test name
Test status
Simulation time 265978867 ps
CPU time 0.91 seconds
Started Jul 15 07:05:41 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 206780 kb
Host smart-5547b3d2-ebe7-493a-85aa-1b003c1d602c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13058
30908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1305830908
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.1304457737
Short name T1525
Test name
Test status
Simulation time 9302426010 ps
CPU time 88.2 seconds
Started Jul 15 07:05:35 PM PDT 24
Finished Jul 15 07:07:04 PM PDT 24
Peak memory 207052 kb
Host smart-df3994d5-5d9f-409f-8ad3-2b4b78eeb636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13044
57737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.1304457737
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3428611377
Short name T2584
Test name
Test status
Simulation time 236431601 ps
CPU time 0.89 seconds
Started Jul 15 07:05:36 PM PDT 24
Finished Jul 15 07:05:37 PM PDT 24
Peak memory 206844 kb
Host smart-5fb529b1-aecf-4228-a0f6-ccd6e7856e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34286
11377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3428611377
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.935499840
Short name T383
Test name
Test status
Simulation time 3278693835 ps
CPU time 3.6 seconds
Started Jul 15 07:05:34 PM PDT 24
Finished Jul 15 07:05:38 PM PDT 24
Peak memory 206888 kb
Host smart-45000739-430e-4da1-a391-6b6abef03b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93549
9840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.935499840
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.3006605706
Short name T2110
Test name
Test status
Simulation time 8988648680 ps
CPU time 85.37 seconds
Started Jul 15 07:05:33 PM PDT 24
Finished Jul 15 07:06:59 PM PDT 24
Peak memory 207076 kb
Host smart-684d9b65-c395-42d9-b9a1-4d63c7caa8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30066
05706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.3006605706
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.224499729
Short name T1303
Test name
Test status
Simulation time 5599486128 ps
CPU time 154.64 seconds
Started Jul 15 07:05:33 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 207012 kb
Host smart-01343645-73ab-45db-b341-eb298e035e9c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=224499729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.224499729
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1971689574
Short name T763
Test name
Test status
Simulation time 280733583 ps
CPU time 0.97 seconds
Started Jul 15 07:05:37 PM PDT 24
Finished Jul 15 07:05:38 PM PDT 24
Peak memory 206764 kb
Host smart-1903e96d-c09b-4548-abb5-87b347d25c5f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1971689574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1971689574
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3111328805
Short name T416
Test name
Test status
Simulation time 192137303 ps
CPU time 0.82 seconds
Started Jul 15 07:05:33 PM PDT 24
Finished Jul 15 07:05:35 PM PDT 24
Peak memory 206824 kb
Host smart-0585e71d-b9d7-479e-baf0-e18f1e1a023c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31113
28805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3111328805
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1021092320
Short name T2051
Test name
Test status
Simulation time 5574750299 ps
CPU time 159.11 seconds
Started Jul 15 07:05:43 PM PDT 24
Finished Jul 15 07:08:24 PM PDT 24
Peak memory 207068 kb
Host smart-4cb6043b-c2c8-4f69-b0ba-321f3f00d995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10210
92320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1021092320
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.608256658
Short name T2166
Test name
Test status
Simulation time 6582113590 ps
CPU time 184.09 seconds
Started Jul 15 07:05:40 PM PDT 24
Finished Jul 15 07:08:45 PM PDT 24
Peak memory 207008 kb
Host smart-e92bfba2-4c2d-4b55-8525-20675ccd1ab3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=608256658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.608256658
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3320744931
Short name T202
Test name
Test status
Simulation time 174592135 ps
CPU time 0.84 seconds
Started Jul 15 07:05:43 PM PDT 24
Finished Jul 15 07:05:46 PM PDT 24
Peak memory 206824 kb
Host smart-673548e6-a909-4663-9ffd-1dce9b3f0686
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3320744931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3320744931
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2413701697
Short name T1340
Test name
Test status
Simulation time 150389624 ps
CPU time 0.86 seconds
Started Jul 15 07:05:41 PM PDT 24
Finished Jul 15 07:05:43 PM PDT 24
Peak memory 206784 kb
Host smart-5caedab1-a543-470e-b4d5-d8bc0b522e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24137
01697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2413701697
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.947745944
Short name T2317
Test name
Test status
Simulation time 177504478 ps
CPU time 0.85 seconds
Started Jul 15 07:05:33 PM PDT 24
Finished Jul 15 07:05:34 PM PDT 24
Peak memory 206820 kb
Host smart-63f7fd8e-cc77-4fd0-9caa-e4686d51e847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94774
5944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.947745944
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.4161908428
Short name T904
Test name
Test status
Simulation time 152921982 ps
CPU time 0.8 seconds
Started Jul 15 07:05:40 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 206700 kb
Host smart-f558923d-09b6-41fb-8b67-15d09161bb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41619
08428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4161908428
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.47013038
Short name T1219
Test name
Test status
Simulation time 248943719 ps
CPU time 0.87 seconds
Started Jul 15 07:05:32 PM PDT 24
Finished Jul 15 07:05:34 PM PDT 24
Peak memory 206764 kb
Host smart-890557fc-1643-436b-97dd-99e5ec8eae1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47013
038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.47013038
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.146219842
Short name T1046
Test name
Test status
Simulation time 153730426 ps
CPU time 0.79 seconds
Started Jul 15 07:05:43 PM PDT 24
Finished Jul 15 07:05:45 PM PDT 24
Peak memory 206972 kb
Host smart-22a509c7-5cad-4dd1-a465-efa68497c746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14621
9842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.146219842
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1988299024
Short name T2617
Test name
Test status
Simulation time 217711022 ps
CPU time 0.93 seconds
Started Jul 15 07:05:34 PM PDT 24
Finished Jul 15 07:05:35 PM PDT 24
Peak memory 206836 kb
Host smart-437e9960-524a-4dc8-ae94-08186a9e53f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1988299024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1988299024
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.4119946838
Short name T40
Test name
Test status
Simulation time 152502899 ps
CPU time 0.75 seconds
Started Jul 15 07:05:35 PM PDT 24
Finished Jul 15 07:05:37 PM PDT 24
Peak memory 206776 kb
Host smart-35eb16bb-ccdd-4dcb-b321-ff9c611ac638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41199
46838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.4119946838
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3280827851
Short name T1564
Test name
Test status
Simulation time 32851819 ps
CPU time 0.67 seconds
Started Jul 15 07:05:40 PM PDT 24
Finished Jul 15 07:05:41 PM PDT 24
Peak memory 206824 kb
Host smart-73d47768-63c5-43d7-bef4-2dc2bb653182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32808
27851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3280827851
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2341839811
Short name T1183
Test name
Test status
Simulation time 19253903406 ps
CPU time 41.13 seconds
Started Jul 15 07:05:34 PM PDT 24
Finished Jul 15 07:06:16 PM PDT 24
Peak memory 207104 kb
Host smart-8af39815-6e4d-442c-9e7f-06389c5d1e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23418
39811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2341839811
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.771805570
Short name T462
Test name
Test status
Simulation time 155987145 ps
CPU time 0.82 seconds
Started Jul 15 07:05:41 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 206800 kb
Host smart-d55e9654-df4d-40fe-af58-e1a263c00899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77180
5570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.771805570
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3935754111
Short name T1769
Test name
Test status
Simulation time 167530729 ps
CPU time 0.79 seconds
Started Jul 15 07:05:41 PM PDT 24
Finished Jul 15 07:05:43 PM PDT 24
Peak memory 206824 kb
Host smart-6365f53d-7d85-4e2b-94ff-2409e8aff56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39357
54111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3935754111
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2192501595
Short name T914
Test name
Test status
Simulation time 172922707 ps
CPU time 0.8 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:44 PM PDT 24
Peak memory 206820 kb
Host smart-27164e58-6dae-4b0c-8c26-341463f869b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21925
01595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2192501595
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1725248824
Short name T2481
Test name
Test status
Simulation time 192091895 ps
CPU time 0.83 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:50 PM PDT 24
Peak memory 206816 kb
Host smart-0a08f6fb-a5e2-4cb3-ac6a-435a612cda3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17252
48824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1725248824
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.4200514308
Short name T2289
Test name
Test status
Simulation time 136594337 ps
CPU time 0.75 seconds
Started Jul 15 07:05:41 PM PDT 24
Finished Jul 15 07:05:43 PM PDT 24
Peak memory 206788 kb
Host smart-389a79fe-286e-4c64-b21f-8cf949915b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42005
14308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.4200514308
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.214794689
Short name T2638
Test name
Test status
Simulation time 166137339 ps
CPU time 0.8 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:44 PM PDT 24
Peak memory 206788 kb
Host smart-d925ab4c-406b-4616-a4f0-2630423f874c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21479
4689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.214794689
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1829832417
Short name T2399
Test name
Test status
Simulation time 158608995 ps
CPU time 0.79 seconds
Started Jul 15 07:05:39 PM PDT 24
Finished Jul 15 07:05:40 PM PDT 24
Peak memory 206840 kb
Host smart-3a5259ba-5c94-421e-8e3e-355a80668af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18298
32417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1829832417
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2383638417
Short name T1703
Test name
Test status
Simulation time 232624374 ps
CPU time 0.95 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:45 PM PDT 24
Peak memory 206812 kb
Host smart-1fd5e801-4abe-4c7d-acfe-1b1d9764ec15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
38417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2383638417
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3516421563
Short name T2417
Test name
Test status
Simulation time 4635692162 ps
CPU time 31.16 seconds
Started Jul 15 07:05:44 PM PDT 24
Finished Jul 15 07:06:16 PM PDT 24
Peak memory 207016 kb
Host smart-98b07769-0e6a-4518-ab02-b3dc709bac5b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3516421563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3516421563
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.4125748455
Short name T1917
Test name
Test status
Simulation time 175398719 ps
CPU time 0.82 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:44 PM PDT 24
Peak memory 206816 kb
Host smart-723ac73c-c8c9-49ac-8b0c-ebd2a1bf3e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
48455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.4125748455
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3441581782
Short name T2563
Test name
Test status
Simulation time 178524727 ps
CPU time 0.81 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:50 PM PDT 24
Peak memory 206808 kb
Host smart-7e7d93f5-74cb-4459-bc5f-12eb593b621a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34415
81782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3441581782
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.1125447254
Short name T1154
Test name
Test status
Simulation time 1071245884 ps
CPU time 2.62 seconds
Started Jul 15 07:05:38 PM PDT 24
Finished Jul 15 07:05:41 PM PDT 24
Peak memory 207016 kb
Host smart-89e6094a-e29d-4d1d-9aa3-2722567ef2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11254
47254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.1125447254
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3577289110
Short name T1940
Test name
Test status
Simulation time 4349102157 ps
CPU time 30.11 seconds
Started Jul 15 07:05:41 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 207016 kb
Host smart-cce5919d-3c94-477e-8ddb-390fbe3300ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
89110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3577289110
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2630655057
Short name T172
Test name
Test status
Simulation time 44192381 ps
CPU time 0.7 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:50 PM PDT 24
Peak memory 206836 kb
Host smart-f6f79f85-864e-4b36-be42-55032b625435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2630655057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2630655057
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3935395323
Short name T198
Test name
Test status
Simulation time 3493443127 ps
CPU time 4.03 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:52 PM PDT 24
Peak memory 206864 kb
Host smart-e7889944-f57d-46b5-9457-d6dc53d1ddb3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3935395323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3935395323
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.4168315892
Short name T10
Test name
Test status
Simulation time 13316409642 ps
CPU time 13.64 seconds
Started Jul 15 07:05:43 PM PDT 24
Finished Jul 15 07:05:58 PM PDT 24
Peak memory 206852 kb
Host smart-32af9510-b6cc-483e-945d-fc9c61fb0468
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4168315892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.4168315892
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.210645772
Short name T898
Test name
Test status
Simulation time 23407424620 ps
CPU time 23.06 seconds
Started Jul 15 07:05:45 PM PDT 24
Finished Jul 15 07:06:10 PM PDT 24
Peak memory 207032 kb
Host smart-81403eee-1f8f-4f38-80a4-d9c6e984c608
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=210645772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.210645772
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.943663493
Short name T1314
Test name
Test status
Simulation time 190588285 ps
CPU time 0.85 seconds
Started Jul 15 07:05:40 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 206816 kb
Host smart-6ee18547-645a-4048-9549-abf8a4e3df49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94366
3493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.943663493
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.2782553399
Short name T1860
Test name
Test status
Simulation time 173675494 ps
CPU time 0.8 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:45 PM PDT 24
Peak memory 206824 kb
Host smart-2475da47-2443-4820-b217-716f0217f49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27825
53399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.2782553399
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2992598590
Short name T869
Test name
Test status
Simulation time 262032263 ps
CPU time 1.02 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:48 PM PDT 24
Peak memory 206808 kb
Host smart-e1577fb9-29d7-4681-9106-b91e20a309f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29925
98590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2992598590
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1003660442
Short name T1477
Test name
Test status
Simulation time 1489025835 ps
CPU time 2.99 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:47 PM PDT 24
Peak memory 206972 kb
Host smart-82f8a188-53c5-423e-9ec8-40f2b6027a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036
60442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1003660442
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.70843348
Short name T1283
Test name
Test status
Simulation time 21565809377 ps
CPU time 37.12 seconds
Started Jul 15 07:05:44 PM PDT 24
Finished Jul 15 07:06:23 PM PDT 24
Peak memory 207076 kb
Host smart-c7628869-31d0-4858-b28d-73b4dbfc7887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70843
348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.70843348
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.771344985
Short name T1097
Test name
Test status
Simulation time 438088628 ps
CPU time 1.34 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:45 PM PDT 24
Peak memory 206796 kb
Host smart-d085b274-c588-4a51-a0d0-18bface6764e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77134
4985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.771344985
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2449598945
Short name T1721
Test name
Test status
Simulation time 141776317 ps
CPU time 0.77 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:44 PM PDT 24
Peak memory 206792 kb
Host smart-155d41f9-51d2-4446-b4cb-936474d4d6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24495
98945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2449598945
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3095805490
Short name T1723
Test name
Test status
Simulation time 38348680 ps
CPU time 0.65 seconds
Started Jul 15 07:05:43 PM PDT 24
Finished Jul 15 07:05:46 PM PDT 24
Peak memory 206804 kb
Host smart-b10800d3-3089-4c51-a40b-63458208cb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30958
05490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3095805490
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3537756579
Short name T1404
Test name
Test status
Simulation time 942079094 ps
CPU time 2.26 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:46 PM PDT 24
Peak memory 207020 kb
Host smart-d97e2fd8-f754-45a6-bcd1-606969cec874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377
56579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3537756579
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.541709231
Short name T2245
Test name
Test status
Simulation time 233772239 ps
CPU time 1.86 seconds
Started Jul 15 07:05:40 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 207032 kb
Host smart-629e4a21-a04d-4260-b6c8-d7bb4351fdea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54170
9231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.541709231
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.4061549615
Short name T1424
Test name
Test status
Simulation time 180072799 ps
CPU time 0.8 seconds
Started Jul 15 07:05:45 PM PDT 24
Finished Jul 15 07:05:47 PM PDT 24
Peak memory 206804 kb
Host smart-2b96ba42-5ec2-436d-bdd5-e440d5ed433c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40615
49615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.4061549615
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1586665480
Short name T683
Test name
Test status
Simulation time 138261311 ps
CPU time 0.78 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:48 PM PDT 24
Peak memory 206816 kb
Host smart-70647857-cc92-4a8d-896d-f611bcf6c4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15866
65480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1586665480
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1549121554
Short name T672
Test name
Test status
Simulation time 215668095 ps
CPU time 0.88 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:44 PM PDT 24
Peak memory 206828 kb
Host smart-7d8f4de9-ca66-4875-9d52-353af6ea309a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15491
21554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1549121554
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.445598032
Short name T1175
Test name
Test status
Simulation time 10882011741 ps
CPU time 90.92 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:07:15 PM PDT 24
Peak memory 207020 kb
Host smart-2d14af70-e0b8-4c2c-b1e4-0f423dea53b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44559
8032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.445598032
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3321526415
Short name T2640
Test name
Test status
Simulation time 164332646 ps
CPU time 0.84 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:45 PM PDT 24
Peak memory 206808 kb
Host smart-96dc9146-9444-472c-b74b-4842481b7b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33215
26415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3321526415
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3980162302
Short name T1883
Test name
Test status
Simulation time 23333250450 ps
CPU time 25.55 seconds
Started Jul 15 07:05:45 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206880 kb
Host smart-ad8d600b-7b26-46ad-b400-5f0ccdffbe0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39801
62302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3980162302
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3787125795
Short name T1536
Test name
Test status
Simulation time 3317755220 ps
CPU time 3.81 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:47 PM PDT 24
Peak memory 206864 kb
Host smart-7d34add9-b530-4a63-8e70-12bf4df20683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37871
25795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3787125795
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2828325986
Short name T2024
Test name
Test status
Simulation time 9131076395 ps
CPU time 87.28 seconds
Started Jul 15 07:05:49 PM PDT 24
Finished Jul 15 07:07:18 PM PDT 24
Peak memory 207096 kb
Host smart-b488c83f-04c1-419b-a89d-d423b9533e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28283
25986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2828325986
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.223751040
Short name T979
Test name
Test status
Simulation time 3195439430 ps
CPU time 21.95 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 207060 kb
Host smart-43812561-fdae-46cd-b62e-679f6597eb2d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=223751040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.223751040
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1294708379
Short name T2102
Test name
Test status
Simulation time 285420278 ps
CPU time 0.94 seconds
Started Jul 15 07:05:43 PM PDT 24
Finished Jul 15 07:05:46 PM PDT 24
Peak memory 206812 kb
Host smart-b33686c4-b8b4-4e77-89bd-e0a1d6249b0c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1294708379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1294708379
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1688006015
Short name T1235
Test name
Test status
Simulation time 201009434 ps
CPU time 0.93 seconds
Started Jul 15 07:05:43 PM PDT 24
Finished Jul 15 07:05:46 PM PDT 24
Peak memory 206836 kb
Host smart-29789774-8636-457e-b753-bde1d2a033fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16880
06015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1688006015
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2172964851
Short name T217
Test name
Test status
Simulation time 7701438721 ps
CPU time 73.79 seconds
Started Jul 15 07:05:40 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 207048 kb
Host smart-893c0f4e-00e7-4428-a208-bdb2f807785e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21729
64851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2172964851
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3648598790
Short name T2105
Test name
Test status
Simulation time 6593984895 ps
CPU time 183.75 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 207004 kb
Host smart-a50dee9b-7273-4b5c-bffb-db0bc03e0269
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3648598790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3648598790
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3317766678
Short name T2628
Test name
Test status
Simulation time 186187934 ps
CPU time 0.82 seconds
Started Jul 15 07:05:42 PM PDT 24
Finished Jul 15 07:05:44 PM PDT 24
Peak memory 206768 kb
Host smart-d8d89b27-035f-4b47-926d-8d70459421ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3317766678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3317766678
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3951537623
Short name T1037
Test name
Test status
Simulation time 159576301 ps
CPU time 0.81 seconds
Started Jul 15 07:05:49 PM PDT 24
Finished Jul 15 07:05:51 PM PDT 24
Peak memory 206828 kb
Host smart-69dd3f06-085a-4a85-a120-6622c37ad18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515
37623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3951537623
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1663983513
Short name T1526
Test name
Test status
Simulation time 178287710 ps
CPU time 0.76 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206812 kb
Host smart-ded13293-dfd3-476f-b13d-ff4a0c1e94b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
83513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1663983513
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.839543679
Short name T1688
Test name
Test status
Simulation time 176966659 ps
CPU time 0.82 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206644 kb
Host smart-8237203f-d007-4dae-9019-3c7a5a676b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83954
3679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.839543679
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.169457337
Short name T2054
Test name
Test status
Simulation time 216207879 ps
CPU time 0.83 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:05:51 PM PDT 24
Peak memory 206800 kb
Host smart-1f05c8d9-6aef-4b8e-912e-9888f543fbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16945
7337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.169457337
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1883670350
Short name T571
Test name
Test status
Simulation time 157469512 ps
CPU time 0.75 seconds
Started Jul 15 07:05:45 PM PDT 24
Finished Jul 15 07:05:47 PM PDT 24
Peak memory 206756 kb
Host smart-910983bd-3931-4875-af29-5a03822f0ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18836
70350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1883670350
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.697522811
Short name T28
Test name
Test status
Simulation time 262238880 ps
CPU time 0.96 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:01 PM PDT 24
Peak memory 206616 kb
Host smart-e1f62a66-5a23-4026-a9c9-75fecf9f8be2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=697522811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.697522811
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.125823194
Short name T1980
Test name
Test status
Simulation time 141860358 ps
CPU time 0.79 seconds
Started Jul 15 07:05:45 PM PDT 24
Finished Jul 15 07:05:48 PM PDT 24
Peak memory 206804 kb
Host smart-3693eb0d-0402-42f5-bd0b-f7ca5f802e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
3194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.125823194
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1551419818
Short name T2723
Test name
Test status
Simulation time 36605153 ps
CPU time 0.65 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206804 kb
Host smart-c66b6f7d-9c8a-4edf-abe6-8056b4d6111c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15514
19818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1551419818
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1078787461
Short name T2727
Test name
Test status
Simulation time 13768745030 ps
CPU time 31.82 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:06:22 PM PDT 24
Peak memory 207136 kb
Host smart-4cdd3f21-0fef-4b47-8f7f-2eabc583f1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787
87461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1078787461
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2071204159
Short name T1005
Test name
Test status
Simulation time 182885948 ps
CPU time 0.88 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206804 kb
Host smart-ff87f14c-c9c0-4fc3-a956-8a03053d9e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
04159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2071204159
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3489954152
Short name T2582
Test name
Test status
Simulation time 201251212 ps
CPU time 0.83 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206652 kb
Host smart-903714b8-6ff9-4245-8ea3-f912d978d70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34899
54152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3489954152
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.4222670208
Short name T1376
Test name
Test status
Simulation time 222993585 ps
CPU time 0.89 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206820 kb
Host smart-e387b76f-e300-4354-8e13-ec7968bae636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42226
70208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.4222670208
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1609795674
Short name T1148
Test name
Test status
Simulation time 144109839 ps
CPU time 0.78 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:05:51 PM PDT 24
Peak memory 206812 kb
Host smart-98e4ba99-2e6c-4202-b32f-2633004d9667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16097
95674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1609795674
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2455319064
Short name T803
Test name
Test status
Simulation time 175671818 ps
CPU time 0.75 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:01 PM PDT 24
Peak memory 206592 kb
Host smart-1dcc0615-c07d-476d-83ee-badb2641b752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24553
19064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2455319064
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2210192497
Short name T2189
Test name
Test status
Simulation time 190998645 ps
CPU time 0.82 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:50 PM PDT 24
Peak memory 206828 kb
Host smart-b5d27e39-4313-491e-b4ef-91e94d146743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22101
92497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2210192497
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3169969433
Short name T1059
Test name
Test status
Simulation time 155650449 ps
CPU time 0.76 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:05:51 PM PDT 24
Peak memory 206828 kb
Host smart-9678e909-5bc7-4443-bd0b-98d08c29e18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31699
69433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3169969433
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1329237348
Short name T895
Test name
Test status
Simulation time 232196239 ps
CPU time 0.94 seconds
Started Jul 15 07:05:50 PM PDT 24
Finished Jul 15 07:05:52 PM PDT 24
Peak memory 206824 kb
Host smart-0e99c8a6-05a4-42db-86ab-e72fe160cfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13292
37348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1329237348
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.995570230
Short name T2541
Test name
Test status
Simulation time 5193330631 ps
CPU time 35.81 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:06:25 PM PDT 24
Peak memory 206896 kb
Host smart-e83d0603-6b95-4159-a0aa-4c4f04591926
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=995570230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.995570230
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.4055822264
Short name T795
Test name
Test status
Simulation time 186016830 ps
CPU time 0.89 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206804 kb
Host smart-f1bf4da8-b63e-46ab-8d7c-270ee860493c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40558
22264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.4055822264
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.667694006
Short name T1669
Test name
Test status
Simulation time 178787473 ps
CPU time 0.78 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206780 kb
Host smart-4b578be8-d924-409d-854b-7d200ebc1b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66769
4006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.667694006
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.158186648
Short name T318
Test name
Test status
Simulation time 1013185610 ps
CPU time 2.31 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:52 PM PDT 24
Peak memory 206908 kb
Host smart-74668796-772e-45f2-ad6b-8076291db22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15818
6648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.158186648
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.918749629
Short name T2624
Test name
Test status
Simulation time 3859764284 ps
CPU time 27.83 seconds
Started Jul 15 07:05:49 PM PDT 24
Finished Jul 15 07:06:18 PM PDT 24
Peak memory 207016 kb
Host smart-359bdc3b-cd78-4279-8ac3-ea24da0d2fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91874
9629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.918749629
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3981333393
Short name T2386
Test name
Test status
Simulation time 38270492 ps
CPU time 0.64 seconds
Started Jul 15 07:05:58 PM PDT 24
Finished Jul 15 07:05:59 PM PDT 24
Peak memory 206776 kb
Host smart-da743e9f-2d39-4458-94d0-35debf607b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3981333393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3981333393
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3128693112
Short name T1326
Test name
Test status
Simulation time 3626379724 ps
CPU time 4.14 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:53 PM PDT 24
Peak memory 206868 kb
Host smart-b84a94e0-b50a-4b07-b8cf-392fa06e277d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3128693112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3128693112
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1638577894
Short name T2410
Test name
Test status
Simulation time 13417597232 ps
CPU time 12.45 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206864 kb
Host smart-5dd5ab3a-86c1-484f-b906-dc00a5feae47
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1638577894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1638577894
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3750792480
Short name T487
Test name
Test status
Simulation time 23438189978 ps
CPU time 24.7 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206940 kb
Host smart-3f90a743-c5e0-495a-923c-e8f6ae498d8c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3750792480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3750792480
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.4261313106
Short name T2267
Test name
Test status
Simulation time 165428265 ps
CPU time 0.76 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206824 kb
Host smart-6cc6a383-584f-4227-ab16-9e221a2d3894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42613
13106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.4261313106
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.805992081
Short name T2674
Test name
Test status
Simulation time 192861783 ps
CPU time 0.85 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:05:51 PM PDT 24
Peak memory 206796 kb
Host smart-caae32b0-92fb-4ed6-b9c4-d2a9649305d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80599
2081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.805992081
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2160858419
Short name T2310
Test name
Test status
Simulation time 483267900 ps
CPU time 1.39 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:05:51 PM PDT 24
Peak memory 206808 kb
Host smart-a4f3948d-c493-4235-a6ff-16e3e414ca3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21608
58419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2160858419
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1546833563
Short name T585
Test name
Test status
Simulation time 448427900 ps
CPU time 1.27 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:05:51 PM PDT 24
Peak memory 206840 kb
Host smart-878018fe-c86c-4d97-b870-38f4ba81c969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15468
33563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1546833563
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2032696617
Short name T86
Test name
Test status
Simulation time 6560357733 ps
CPU time 12.76 seconds
Started Jul 15 07:05:49 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 207068 kb
Host smart-01ac9456-fd27-4c68-8b0f-3421eb5ed34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20326
96617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2032696617
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.3635878350
Short name T545
Test name
Test status
Simulation time 376536603 ps
CPU time 1.25 seconds
Started Jul 15 07:05:46 PM PDT 24
Finished Jul 15 07:05:49 PM PDT 24
Peak memory 206816 kb
Host smart-4b9ad77d-eb9a-4a22-ad47-dbef198a740e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36358
78350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.3635878350
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3079904588
Short name T2203
Test name
Test status
Simulation time 197663372 ps
CPU time 0.82 seconds
Started Jul 15 07:05:44 PM PDT 24
Finished Jul 15 07:05:47 PM PDT 24
Peak memory 206764 kb
Host smart-32af94a0-4734-4ed3-bb66-c8a416ddb63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30799
04588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3079904588
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.163638724
Short name T1708
Test name
Test status
Simulation time 74973412 ps
CPU time 0.69 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206640 kb
Host smart-2263dec8-bb36-44f2-a3ee-718beb5184a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16363
8724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.163638724
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1566750894
Short name T2383
Test name
Test status
Simulation time 848714646 ps
CPU time 2.2 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206772 kb
Host smart-015df0c0-c12e-4e15-8a44-63977affbdbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15667
50894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1566750894
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2349264729
Short name T1629
Test name
Test status
Simulation time 186323516 ps
CPU time 2.15 seconds
Started Jul 15 07:05:48 PM PDT 24
Finished Jul 15 07:05:52 PM PDT 24
Peak memory 206956 kb
Host smart-6c31e94e-7a43-46b3-846b-94c45143046d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23492
64729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2349264729
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.790910598
Short name T778
Test name
Test status
Simulation time 289432596 ps
CPU time 0.98 seconds
Started Jul 15 07:05:47 PM PDT 24
Finished Jul 15 07:05:50 PM PDT 24
Peak memory 206804 kb
Host smart-d22913f9-0715-4c5b-af15-6269561dd8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79091
0598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.790910598
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3511767194
Short name T637
Test name
Test status
Simulation time 142446776 ps
CPU time 0.78 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206636 kb
Host smart-1fc32998-05dd-46d1-8a91-ff113e34d948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35117
67194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3511767194
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3611433339
Short name T901
Test name
Test status
Simulation time 253291012 ps
CPU time 1 seconds
Started Jul 15 07:05:52 PM PDT 24
Finished Jul 15 07:05:53 PM PDT 24
Peak memory 206800 kb
Host smart-c81b2428-d3f0-49c1-a7dd-f14021aabe46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36114
33339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3611433339
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.823288745
Short name T851
Test name
Test status
Simulation time 4040386032 ps
CPU time 15.29 seconds
Started Jul 15 07:05:52 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 207052 kb
Host smart-3fdc5d3c-bf20-476f-b7e2-c555b39c1262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82328
8745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.823288745
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2225535872
Short name T888
Test name
Test status
Simulation time 282759864 ps
CPU time 0.92 seconds
Started Jul 15 07:05:51 PM PDT 24
Finished Jul 15 07:05:52 PM PDT 24
Peak memory 206764 kb
Host smart-5fa20e47-5d68-4081-a4cd-a7e7906d63f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22255
35872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2225535872
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.1769395233
Short name T858
Test name
Test status
Simulation time 23329323168 ps
CPU time 21.36 seconds
Started Jul 15 07:05:51 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206872 kb
Host smart-20909dd8-bc3a-4374-b199-f5a115c5625c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17693
95233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1769395233
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1443066113
Short name T2592
Test name
Test status
Simulation time 3256049980 ps
CPU time 4.26 seconds
Started Jul 15 07:05:52 PM PDT 24
Finished Jul 15 07:05:57 PM PDT 24
Peak memory 206844 kb
Host smart-850a2e4a-233b-47e4-a36a-2267b6c17d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14430
66113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1443066113
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1946491675
Short name T1490
Test name
Test status
Simulation time 9629614771 ps
CPU time 76.92 seconds
Started Jul 15 07:05:53 PM PDT 24
Finished Jul 15 07:07:10 PM PDT 24
Peak memory 207108 kb
Host smart-a1f17e5a-2fb4-44f6-84ae-91a180f8dfc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19464
91675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1946491675
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.199787070
Short name T1955
Test name
Test status
Simulation time 4595607610 ps
CPU time 41.02 seconds
Started Jul 15 07:05:51 PM PDT 24
Finished Jul 15 07:06:33 PM PDT 24
Peak memory 207056 kb
Host smart-f588f271-b2da-4efb-bbbb-fcfee7b3a43b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=199787070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.199787070
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1559491958
Short name T2005
Test name
Test status
Simulation time 237382922 ps
CPU time 0.93 seconds
Started Jul 15 07:05:51 PM PDT 24
Finished Jul 15 07:05:52 PM PDT 24
Peak memory 206776 kb
Host smart-81d219ce-7a6c-484a-94ce-e99fb196389f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1559491958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1559491958
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.122324824
Short name T438
Test name
Test status
Simulation time 199613103 ps
CPU time 0.89 seconds
Started Jul 15 07:05:51 PM PDT 24
Finished Jul 15 07:05:53 PM PDT 24
Peak memory 206760 kb
Host smart-dfcd56bf-31db-4032-9211-99197394cc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
4824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.122324824
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.3873999569
Short name T349
Test name
Test status
Simulation time 5673595999 ps
CPU time 162.19 seconds
Started Jul 15 07:05:53 PM PDT 24
Finished Jul 15 07:08:36 PM PDT 24
Peak memory 207024 kb
Host smart-1632a239-7024-4cc0-84ce-aac8a82c59c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38739
99569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.3873999569
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3882261947
Short name T2143
Test name
Test status
Simulation time 5332062017 ps
CPU time 37.78 seconds
Started Jul 15 07:05:56 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 207092 kb
Host smart-c23e606a-2ea7-4f2c-85be-91dc803e4632
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3882261947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3882261947
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1946824623
Short name T583
Test name
Test status
Simulation time 151200020 ps
CPU time 0.83 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206648 kb
Host smart-63976c55-7589-43d4-a256-1b68f3ad6679
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1946824623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1946824623
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1244038233
Short name T2420
Test name
Test status
Simulation time 157474198 ps
CPU time 0.79 seconds
Started Jul 15 07:05:52 PM PDT 24
Finished Jul 15 07:05:53 PM PDT 24
Peak memory 206792 kb
Host smart-f29e1baf-1039-4b18-90ff-a944f3115fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12440
38233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1244038233
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2121185200
Short name T123
Test name
Test status
Simulation time 167187978 ps
CPU time 0.9 seconds
Started Jul 15 07:05:52 PM PDT 24
Finished Jul 15 07:05:53 PM PDT 24
Peak memory 206800 kb
Host smart-6cbcbc02-a4b6-48de-9af6-af30291f0544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21211
85200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2121185200
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2534694632
Short name T838
Test name
Test status
Simulation time 152296470 ps
CPU time 0.78 seconds
Started Jul 15 07:05:53 PM PDT 24
Finished Jul 15 07:05:54 PM PDT 24
Peak memory 206832 kb
Host smart-638a687a-d685-4c2c-80c7-90a316a20177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25346
94632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2534694632
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2357424522
Short name T2703
Test name
Test status
Simulation time 218536752 ps
CPU time 0.82 seconds
Started Jul 15 07:05:53 PM PDT 24
Finished Jul 15 07:05:54 PM PDT 24
Peak memory 206828 kb
Host smart-4e90274e-7041-40f4-8619-71bfe044f862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23574
24522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2357424522
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1678558984
Short name T1109
Test name
Test status
Simulation time 236314721 ps
CPU time 0.84 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206648 kb
Host smart-c2f57442-d083-48b1-9a71-475c52268fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16785
58984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1678558984
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.787820742
Short name T1895
Test name
Test status
Simulation time 155292784 ps
CPU time 0.84 seconds
Started Jul 15 07:05:53 PM PDT 24
Finished Jul 15 07:05:54 PM PDT 24
Peak memory 206820 kb
Host smart-6ef1ba90-13c8-4222-bde9-4725a09aa79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78782
0742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.787820742
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1806928843
Short name T342
Test name
Test status
Simulation time 222222917 ps
CPU time 0.9 seconds
Started Jul 15 07:05:57 PM PDT 24
Finished Jul 15 07:05:59 PM PDT 24
Peak memory 206824 kb
Host smart-e00d3105-7e81-4371-9fa0-dd82df3ba431
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1806928843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1806928843
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.421840952
Short name T1051
Test name
Test status
Simulation time 154644506 ps
CPU time 0.8 seconds
Started Jul 15 07:05:58 PM PDT 24
Finished Jul 15 07:05:59 PM PDT 24
Peak memory 206804 kb
Host smart-5df09d7c-4359-4098-a44c-8eefe9d29242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42184
0952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.421840952
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3559261484
Short name T1878
Test name
Test status
Simulation time 40806862 ps
CPU time 0.66 seconds
Started Jul 15 07:05:58 PM PDT 24
Finished Jul 15 07:05:59 PM PDT 24
Peak memory 206824 kb
Host smart-d9ba9edc-ed2a-47e6-a68b-ed40f011ef75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35592
61484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3559261484
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3717238877
Short name T1172
Test name
Test status
Simulation time 8707688405 ps
CPU time 19.6 seconds
Started Jul 15 07:05:59 PM PDT 24
Finished Jul 15 07:06:19 PM PDT 24
Peak memory 207084 kb
Host smart-e6a5dd47-6573-442e-ac28-ff89dc0c5b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37172
38877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3717238877
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.801614233
Short name T1015
Test name
Test status
Simulation time 184367534 ps
CPU time 0.84 seconds
Started Jul 15 07:05:58 PM PDT 24
Finished Jul 15 07:06:00 PM PDT 24
Peak memory 206776 kb
Host smart-7f1f2cf1-36f8-4816-8501-0ccdaaa44d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80161
4233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.801614233
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3830380928
Short name T520
Test name
Test status
Simulation time 186550391 ps
CPU time 0.86 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:01 PM PDT 24
Peak memory 206824 kb
Host smart-6737efb8-4405-470b-bbdb-01191c000c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38303
80928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3830380928
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1848539356
Short name T841
Test name
Test status
Simulation time 193924660 ps
CPU time 0.87 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206708 kb
Host smart-a48849a4-c289-4644-84cf-51c1ab4c1d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18485
39356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1848539356
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2971630769
Short name T2011
Test name
Test status
Simulation time 271745891 ps
CPU time 0.97 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206824 kb
Host smart-5100399e-cb3e-4998-9e58-0c7f0e60afd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29716
30769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2971630769
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.334973435
Short name T800
Test name
Test status
Simulation time 152921023 ps
CPU time 0.76 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 206780 kb
Host smart-344849f6-9620-47e5-ab4e-4269f8803013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33497
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.334973435
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1546144404
Short name T704
Test name
Test status
Simulation time 162027261 ps
CPU time 0.77 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:01 PM PDT 24
Peak memory 206812 kb
Host smart-6f1b6817-07dc-4810-a864-dcb8c71cdaed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15461
44404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1546144404
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.480813007
Short name T2045
Test name
Test status
Simulation time 149762813 ps
CPU time 0.77 seconds
Started Jul 15 07:05:59 PM PDT 24
Finished Jul 15 07:06:00 PM PDT 24
Peak memory 206836 kb
Host smart-5833bea2-1bca-4a96-a20e-5e73a0a5c4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48081
3007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.480813007
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2130212231
Short name T2348
Test name
Test status
Simulation time 230162694 ps
CPU time 0.93 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:01 PM PDT 24
Peak memory 206824 kb
Host smart-270393e2-1ac5-4968-82aa-c5c62afe71f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21302
12231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2130212231
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.1846511401
Short name T1039
Test name
Test status
Simulation time 4977511042 ps
CPU time 45.55 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 207024 kb
Host smart-9d6c2dcb-0716-44da-b693-977c1473be76
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1846511401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1846511401
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1164527955
Short name T882
Test name
Test status
Simulation time 148358680 ps
CPU time 0.77 seconds
Started Jul 15 07:06:02 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206816 kb
Host smart-7c032eae-b751-4791-8ab2-f17a2fa9e6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645
27955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1164527955
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1983619400
Short name T566
Test name
Test status
Simulation time 162765596 ps
CPU time 0.85 seconds
Started Jul 15 07:05:58 PM PDT 24
Finished Jul 15 07:06:00 PM PDT 24
Peak memory 206792 kb
Host smart-edb0a525-7640-4613-a5b2-2fae996a7264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19836
19400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1983619400
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1600923055
Short name T588
Test name
Test status
Simulation time 847949053 ps
CPU time 1.89 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:04 PM PDT 24
Peak memory 206980 kb
Host smart-fbd312e0-2832-49ca-a01e-380db0d118d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
23055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1600923055
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3792603714
Short name T736
Test name
Test status
Simulation time 4525633041 ps
CPU time 31.3 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:33 PM PDT 24
Peak memory 207080 kb
Host smart-c20238f7-90aa-4cc7-b9ac-fbcd0c337432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37926
03714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3792603714
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.36835241
Short name T509
Test name
Test status
Simulation time 57132264 ps
CPU time 0.7 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 206856 kb
Host smart-716ddb83-483f-4019-b12b-14d2b208cd00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=36835241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.36835241
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.4016155781
Short name T1055
Test name
Test status
Simulation time 4223224210 ps
CPU time 4.94 seconds
Started Jul 15 07:05:58 PM PDT 24
Finished Jul 15 07:06:04 PM PDT 24
Peak memory 207060 kb
Host smart-49594767-9135-43a3-baf8-3ecc5dc51390
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4016155781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.4016155781
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3209496111
Short name T1197
Test name
Test status
Simulation time 13442357364 ps
CPU time 14.34 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:16 PM PDT 24
Peak memory 207084 kb
Host smart-a0783d78-7c13-4720-8a0c-037bd30e53ab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3209496111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3209496111
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3105687146
Short name T2636
Test name
Test status
Simulation time 23534293958 ps
CPU time 28.96 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:38 PM PDT 24
Peak memory 207000 kb
Host smart-b174ee85-a7f4-4a59-a4f0-6194852413c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3105687146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3105687146
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.922717831
Short name T1419
Test name
Test status
Simulation time 147982140 ps
CPU time 0.77 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 206784 kb
Host smart-aef90ede-5d02-4dfa-a334-d7d4a1dca1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92271
7831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.922717831
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3214716607
Short name T1137
Test name
Test status
Simulation time 194865628 ps
CPU time 0.85 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206840 kb
Host smart-310ec611-121a-47db-bbe2-71cc2f5ba3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
16607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3214716607
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1017499309
Short name T1104
Test name
Test status
Simulation time 235085581 ps
CPU time 0.96 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:10 PM PDT 24
Peak memory 206800 kb
Host smart-97b70553-ddbf-49c6-b9e1-eff13f6dccc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10174
99309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1017499309
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1393788361
Short name T2746
Test name
Test status
Simulation time 557567173 ps
CPU time 1.4 seconds
Started Jul 15 07:05:59 PM PDT 24
Finished Jul 15 07:06:01 PM PDT 24
Peak memory 206824 kb
Host smart-f915cdd2-0589-4671-ad70-fa53135bc096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13937
88361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1393788361
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.160625066
Short name T541
Test name
Test status
Simulation time 18928864850 ps
CPU time 32.85 seconds
Started Jul 15 07:06:01 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 207080 kb
Host smart-a7bc6d2d-d9a1-4961-9970-a5293b1ae17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16062
5066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.160625066
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1866602612
Short name T529
Test name
Test status
Simulation time 337629722 ps
CPU time 1.26 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:02 PM PDT 24
Peak memory 206828 kb
Host smart-3909988d-d758-40eb-93f4-f347ee88ee59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18666
02612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1866602612
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1013017916
Short name T595
Test name
Test status
Simulation time 139262927 ps
CPU time 0.75 seconds
Started Jul 15 07:05:57 PM PDT 24
Finished Jul 15 07:05:58 PM PDT 24
Peak memory 206812 kb
Host smart-8c0225d9-ccd6-4fe6-809e-aa4cc978bf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10130
17916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1013017916
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3872339865
Short name T2043
Test name
Test status
Simulation time 38958858 ps
CPU time 0.71 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 206716 kb
Host smart-aa8be5c9-cc94-4667-be23-eba8c28c47b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38723
39865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3872339865
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3789579135
Short name T2679
Test name
Test status
Simulation time 826673901 ps
CPU time 2.13 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:02 PM PDT 24
Peak memory 206964 kb
Host smart-38b3f6d1-f1eb-4924-994b-6634d91891b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37895
79135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3789579135
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2300393188
Short name T1056
Test name
Test status
Simulation time 217134728 ps
CPU time 1.58 seconds
Started Jul 15 07:06:00 PM PDT 24
Finished Jul 15 07:06:03 PM PDT 24
Peak memory 206964 kb
Host smart-0ca89719-c379-49e8-884b-ad2fe97ad1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23003
93188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2300393188
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3032565663
Short name T1019
Test name
Test status
Simulation time 164065521 ps
CPU time 0.83 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 206832 kb
Host smart-370317f3-ad9e-4ea8-b7de-a56157b547f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30325
65663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3032565663
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2685809125
Short name T1516
Test name
Test status
Simulation time 150601765 ps
CPU time 0.83 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 206816 kb
Host smart-97bba760-1158-4e51-9340-b998280796a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26858
09125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2685809125
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1157838005
Short name T1558
Test name
Test status
Simulation time 198724627 ps
CPU time 0.83 seconds
Started Jul 15 07:06:04 PM PDT 24
Finished Jul 15 07:06:05 PM PDT 24
Peak memory 206808 kb
Host smart-13f3254b-4b2b-4ef9-8e23-73b11bb7e257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11578
38005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1157838005
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.1749819938
Short name T2194
Test name
Test status
Simulation time 8158848401 ps
CPU time 232.09 seconds
Started Jul 15 07:06:05 PM PDT 24
Finished Jul 15 07:09:58 PM PDT 24
Peak memory 207012 kb
Host smart-86bfcfad-22b6-4e8a-ab5d-dcc128b241e4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1749819938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.1749819938
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.2361287361
Short name T1520
Test name
Test status
Simulation time 6853093593 ps
CPU time 54.23 seconds
Started Jul 15 07:06:05 PM PDT 24
Finished Jul 15 07:07:00 PM PDT 24
Peak memory 207036 kb
Host smart-8a5cb6d7-fa50-456c-b2af-28713f197003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23612
87361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.2361287361
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3676191295
Short name T1658
Test name
Test status
Simulation time 253096068 ps
CPU time 0.89 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 206812 kb
Host smart-1a3a4321-588a-4de9-90fc-6671b9413779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36761
91295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3676191295
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1941868339
Short name T1301
Test name
Test status
Simulation time 23296784924 ps
CPU time 21.93 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:29 PM PDT 24
Peak memory 206888 kb
Host smart-b9ce7963-2d9b-4a12-a43d-9ade553ab116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19418
68339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1941868339
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2223078327
Short name T2553
Test name
Test status
Simulation time 3377700584 ps
CPU time 4.02 seconds
Started Jul 15 07:06:04 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 206832 kb
Host smart-96c3ba79-19c5-4f78-831d-8b54077a1c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22230
78327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2223078327
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3964514098
Short name T2061
Test name
Test status
Simulation time 7436979418 ps
CPU time 204 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:09:33 PM PDT 24
Peak memory 207064 kb
Host smart-362cb7c5-0fe7-4f80-8f19-ddddc845871d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39645
14098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3964514098
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2631581534
Short name T1821
Test name
Test status
Simulation time 2817682984 ps
CPU time 27.37 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:36 PM PDT 24
Peak memory 207076 kb
Host smart-d09ccbdd-f23f-49c7-9b05-71d62933d6d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2631581534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2631581534
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3473242792
Short name T346
Test name
Test status
Simulation time 237024232 ps
CPU time 0.9 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:07 PM PDT 24
Peak memory 206796 kb
Host smart-c0062e23-5e80-479a-b9ee-1ab0cd634e88
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3473242792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3473242792
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2832937898
Short name T2404
Test name
Test status
Simulation time 198797902 ps
CPU time 0.88 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:12 PM PDT 24
Peak memory 206764 kb
Host smart-c397aa28-10e8-4eb7-98f0-999da4948c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28329
37898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2832937898
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.70062313
Short name T2468
Test name
Test status
Simulation time 4528579948 ps
CPU time 32.13 seconds
Started Jul 15 07:06:05 PM PDT 24
Finished Jul 15 07:06:38 PM PDT 24
Peak memory 207048 kb
Host smart-1f0de6ad-023a-40f1-90b4-b47658db8bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70062
313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.70062313
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.4111692976
Short name T1668
Test name
Test status
Simulation time 4215244054 ps
CPU time 40.99 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:49 PM PDT 24
Peak memory 207008 kb
Host smart-6e6901c5-c905-4e51-a8ff-50567c22c543
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4111692976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.4111692976
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.337099115
Short name T2635
Test name
Test status
Simulation time 193052698 ps
CPU time 0.82 seconds
Started Jul 15 07:06:05 PM PDT 24
Finished Jul 15 07:06:07 PM PDT 24
Peak memory 206784 kb
Host smart-42d0f4aa-85d5-42e2-b746-4b43f438afd4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=337099115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.337099115
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2314158038
Short name T963
Test name
Test status
Simulation time 217919179 ps
CPU time 0.9 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 206820 kb
Host smart-c4c32514-4ad9-4528-b379-fd46733cc0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23141
58038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2314158038
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.70905284
Short name T691
Test name
Test status
Simulation time 158843672 ps
CPU time 0.89 seconds
Started Jul 15 07:06:10 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 206820 kb
Host smart-194be920-66c9-42b1-a2ad-f1a26debd5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70905
284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.70905284
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1338630159
Short name T1719
Test name
Test status
Simulation time 165570194 ps
CPU time 0.78 seconds
Started Jul 15 07:06:04 PM PDT 24
Finished Jul 15 07:06:06 PM PDT 24
Peak memory 206800 kb
Host smart-eec91da0-3c71-42b4-a70b-266367409f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13386
30159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1338630159
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3173594673
Short name T399
Test name
Test status
Simulation time 178888459 ps
CPU time 0.8 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 206820 kb
Host smart-c07ff3c4-1f64-4ba4-bbfe-f188ecc06467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31735
94673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3173594673
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2459672975
Short name T2184
Test name
Test status
Simulation time 145515901 ps
CPU time 0.88 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 206816 kb
Host smart-00b14627-25d4-457d-afe6-81130187528f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24596
72975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2459672975
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1183224787
Short name T2671
Test name
Test status
Simulation time 206938579 ps
CPU time 0.99 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 206804 kb
Host smart-fca2653f-94eb-465d-a663-e87c5a10fdbd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1183224787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1183224787
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.6841634
Short name T978
Test name
Test status
Simulation time 163048382 ps
CPU time 0.79 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 206804 kb
Host smart-25f9b6ab-4ca6-4635-9aa2-e3d83b80f8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68416
34 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.6841634
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.165477105
Short name T2308
Test name
Test status
Simulation time 31090406 ps
CPU time 0.67 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 206832 kb
Host smart-69295968-71c5-450c-abb4-a6853301bb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16547
7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.165477105
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2321593451
Short name T1344
Test name
Test status
Simulation time 11690731730 ps
CPU time 25.87 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 207028 kb
Host smart-75d457ef-0046-4b1e-8ff6-30ea8fa2caa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23215
93451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2321593451
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.517157252
Short name T952
Test name
Test status
Simulation time 190210906 ps
CPU time 0.87 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:12 PM PDT 24
Peak memory 206764 kb
Host smart-6161f54f-fcdd-4468-92ba-34678c9ec645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51715
7252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.517157252
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1884569437
Short name T2395
Test name
Test status
Simulation time 160213155 ps
CPU time 0.79 seconds
Started Jul 15 07:06:05 PM PDT 24
Finished Jul 15 07:06:07 PM PDT 24
Peak memory 206828 kb
Host smart-2929012c-d83d-4536-bcb7-3dc21485f58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845
69437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1884569437
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.4071824561
Short name T1957
Test name
Test status
Simulation time 245058896 ps
CPU time 0.97 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 206824 kb
Host smart-c5a945c2-14f4-4bb9-a550-8fd915011f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40718
24561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.4071824561
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2215218517
Short name T2552
Test name
Test status
Simulation time 215270887 ps
CPU time 0.93 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 206816 kb
Host smart-e373fce7-5471-4e26-9d47-dc3bf9ff263d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22152
18517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2215218517
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3392183764
Short name T2748
Test name
Test status
Simulation time 149453955 ps
CPU time 0.77 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 206804 kb
Host smart-e6e97345-e5a3-4480-b220-99fc3db6d32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33921
83764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3392183764
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.514656977
Short name T568
Test name
Test status
Simulation time 158936552 ps
CPU time 0.8 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 206768 kb
Host smart-073e7cf7-99b9-4060-bce8-c87bd0c31d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51465
6977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.514656977
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1266636920
Short name T495
Test name
Test status
Simulation time 211941658 ps
CPU time 0.83 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:12 PM PDT 24
Peak memory 206844 kb
Host smart-375da19a-eab4-4f19-9ae2-12be9981d04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12666
36920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1266636920
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2026596234
Short name T2337
Test name
Test status
Simulation time 228109559 ps
CPU time 0.94 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 206784 kb
Host smart-7e3c8fc1-f1bd-4e4a-b151-8ad6f3dfb908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20265
96234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2026596234
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2532922915
Short name T1780
Test name
Test status
Simulation time 6376607278 ps
CPU time 171.16 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 207112 kb
Host smart-3b880597-0f02-43aa-97dc-6b5398763f28
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2532922915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2532922915
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2061710108
Short name T1096
Test name
Test status
Simulation time 190178613 ps
CPU time 0.81 seconds
Started Jul 15 07:06:04 PM PDT 24
Finished Jul 15 07:06:05 PM PDT 24
Peak memory 206824 kb
Host smart-9d4d8fcf-05e6-439f-831e-315f19629428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20617
10108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2061710108
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.687054251
Short name T425
Test name
Test status
Simulation time 172221804 ps
CPU time 0.78 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 206700 kb
Host smart-464072ca-9d8e-4f5f-88e3-c6ba1c59cb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68705
4251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.687054251
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3018761197
Short name T1752
Test name
Test status
Simulation time 634798989 ps
CPU time 1.56 seconds
Started Jul 15 07:06:05 PM PDT 24
Finished Jul 15 07:06:07 PM PDT 24
Peak memory 206828 kb
Host smart-d29867fd-ccb0-423a-ba2f-7d55ac71c84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
61197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3018761197
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.643945225
Short name T855
Test name
Test status
Simulation time 6896584479 ps
CPU time 182.32 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:09:11 PM PDT 24
Peak memory 207052 kb
Host smart-5faf0c16-c630-4d2c-aba3-fa0a71f47875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64394
5225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.643945225
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.1697399457
Short name T1899
Test name
Test status
Simulation time 44768660 ps
CPU time 0.68 seconds
Started Jul 15 07:06:10 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206868 kb
Host smart-059184ab-efd6-4e36-81a0-2d0196543739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1697399457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1697399457
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.739901141
Short name T555
Test name
Test status
Simulation time 3885469992 ps
CPU time 5.03 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:15 PM PDT 24
Peak memory 206852 kb
Host smart-7756d081-1f4e-4318-9c93-6f93a44cc540
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=739901141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.739901141
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.4202978388
Short name T590
Test name
Test status
Simulation time 13393268135 ps
CPU time 12 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:22 PM PDT 24
Peak memory 206860 kb
Host smart-deaed81e-257c-4e8c-8ce4-8a2ad661f321
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4202978388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.4202978388
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3348756762
Short name T920
Test name
Test status
Simulation time 23406094404 ps
CPU time 23.5 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:33 PM PDT 24
Peak memory 206852 kb
Host smart-2da8298c-5522-4105-9a44-63f9fa335874
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3348756762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.3348756762
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1558768969
Short name T1267
Test name
Test status
Simulation time 200103316 ps
CPU time 0.85 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206772 kb
Host smart-30bb3555-d4a0-4f0d-b5ea-03b0571c6334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15587
68969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1558768969
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.876735410
Short name T2645
Test name
Test status
Simulation time 148394976 ps
CPU time 0.85 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 206772 kb
Host smart-1305261e-dd8c-4f1d-8e1a-8e552fb9974e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87673
5410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.876735410
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1611817619
Short name T2294
Test name
Test status
Simulation time 249376829 ps
CPU time 0.93 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:12 PM PDT 24
Peak memory 206752 kb
Host smart-7bc63588-01b0-4246-a9ae-2dc579796987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16118
17619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1611817619
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3585130769
Short name T2191
Test name
Test status
Simulation time 694850914 ps
CPU time 1.72 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206992 kb
Host smart-052be6f9-bfca-4323-b2f4-cf6d3a95efb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35851
30769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3585130769
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2089563249
Short name T878
Test name
Test status
Simulation time 22147854106 ps
CPU time 39.57 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 207076 kb
Host smart-a1510cb6-ed87-446b-a33e-b0e3e63573da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895
63249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2089563249
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1467514890
Short name T1121
Test name
Test status
Simulation time 481069235 ps
CPU time 1.51 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206768 kb
Host smart-cd246d5d-f61e-488a-b974-be74a3931f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14675
14890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1467514890
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.949708989
Short name T2507
Test name
Test status
Simulation time 147654554 ps
CPU time 0.76 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 206704 kb
Host smart-f5bc0d95-f0d4-4ae8-b071-125c250743dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94970
8989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.949708989
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.68299453
Short name T1387
Test name
Test status
Simulation time 38648782 ps
CPU time 0.67 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:10 PM PDT 24
Peak memory 206840 kb
Host smart-78d5a8e7-9056-436f-a41b-90b6c6d7ea1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68299
453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.68299453
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3627371961
Short name T2031
Test name
Test status
Simulation time 871918234 ps
CPU time 1.93 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:06:12 PM PDT 24
Peak memory 206996 kb
Host smart-072f7c96-1419-43b4-a232-934b8049be38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36273
71961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3627371961
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.521304049
Short name T676
Test name
Test status
Simulation time 376257325 ps
CPU time 2.13 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:09 PM PDT 24
Peak memory 207016 kb
Host smart-f1fe594c-cfb0-43f2-93f3-208f53c63045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52130
4049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.521304049
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3420390067
Short name T2082
Test name
Test status
Simulation time 215531178 ps
CPU time 0.89 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:12 PM PDT 24
Peak memory 206524 kb
Host smart-926a232f-ac5a-4c4c-955b-f4c69142037e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34203
90067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3420390067
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.4146899967
Short name T903
Test name
Test status
Simulation time 139142375 ps
CPU time 0.8 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:12 PM PDT 24
Peak memory 206780 kb
Host smart-61a25bd2-fceb-4ed8-91e6-5a0e931773f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41468
99967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.4146899967
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1679040504
Short name T1908
Test name
Test status
Simulation time 221714956 ps
CPU time 0.9 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:10 PM PDT 24
Peak memory 206824 kb
Host smart-a20476a0-f762-4b94-ad6a-bfc950d047ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16790
40504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1679040504
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.3062610615
Short name T667
Test name
Test status
Simulation time 6401759952 ps
CPU time 182.21 seconds
Started Jul 15 07:06:05 PM PDT 24
Finished Jul 15 07:09:07 PM PDT 24
Peak memory 207012 kb
Host smart-29201929-4537-410f-802b-80783ae9f1ec
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3062610615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.3062610615
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.607784255
Short name T332
Test name
Test status
Simulation time 10855719758 ps
CPU time 88.31 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:07:39 PM PDT 24
Peak memory 207060 kb
Host smart-8621da7a-3663-498c-b415-6badea12186f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60778
4255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.607784255
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3648079944
Short name T2229
Test name
Test status
Simulation time 200048788 ps
CPU time 0.86 seconds
Started Jul 15 07:06:06 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 206784 kb
Host smart-d95e3989-5564-4e5c-8458-5228f8dcf86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36480
79944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3648079944
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3740678453
Short name T1252
Test name
Test status
Simulation time 23281642628 ps
CPU time 24.18 seconds
Started Jul 15 07:06:07 PM PDT 24
Finished Jul 15 07:06:33 PM PDT 24
Peak memory 206888 kb
Host smart-6c6e8877-6d87-4d0e-810b-17891c48012a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37406
78453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3740678453
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3117517584
Short name T2710
Test name
Test status
Simulation time 3316721478 ps
CPU time 3.74 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:15 PM PDT 24
Peak memory 206620 kb
Host smart-5e2a8555-4c46-4a8f-8112-c2d048e27947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31175
17584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3117517584
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1847573978
Short name T1359
Test name
Test status
Simulation time 9310335273 ps
CPU time 92.4 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:07:46 PM PDT 24
Peak memory 207084 kb
Host smart-4c805109-0b34-48a0-8025-8d9e29152cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18475
73978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1847573978
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3708145112
Short name T1342
Test name
Test status
Simulation time 4331741328 ps
CPU time 39.51 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 207064 kb
Host smart-3e2a05ce-fb35-44f1-9194-03951776f9bb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3708145112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3708145112
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3728402870
Short name T1049
Test name
Test status
Simulation time 245858975 ps
CPU time 0.93 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 206828 kb
Host smart-ff801b63-aa6d-4a47-b115-4feb7da1ef87
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3728402870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3728402870
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3338144760
Short name T1083
Test name
Test status
Simulation time 191351166 ps
CPU time 0.87 seconds
Started Jul 15 07:06:12 PM PDT 24
Finished Jul 15 07:06:16 PM PDT 24
Peak memory 206828 kb
Host smart-6cdec26b-614a-4c02-a4b3-5460bc262b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33381
44760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3338144760
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2370886106
Short name T777
Test name
Test status
Simulation time 3968762161 ps
CPU time 99.64 seconds
Started Jul 15 07:06:08 PM PDT 24
Finished Jul 15 07:07:50 PM PDT 24
Peak memory 207024 kb
Host smart-d29e2b1e-114e-49be-8a43-8f8cd17cb39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
86106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2370886106
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1576201380
Short name T1498
Test name
Test status
Simulation time 4221803545 ps
CPU time 38.03 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 207032 kb
Host smart-275e96ca-c096-41f6-bda1-05ff7b55dbbd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1576201380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1576201380
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.3207647443
Short name T1459
Test name
Test status
Simulation time 158620058 ps
CPU time 0.77 seconds
Started Jul 15 07:06:09 PM PDT 24
Finished Jul 15 07:06:12 PM PDT 24
Peak memory 206824 kb
Host smart-311598da-ed76-4eef-ab7d-32e249602ae0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3207647443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.3207647443
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3802378839
Short name T1893
Test name
Test status
Simulation time 198875573 ps
CPU time 0.84 seconds
Started Jul 15 07:06:12 PM PDT 24
Finished Jul 15 07:06:16 PM PDT 24
Peak memory 206816 kb
Host smart-1a0d9d18-8a32-4415-901c-5b3407edb54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38023
78839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3802378839
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3045073639
Short name T1715
Test name
Test status
Simulation time 150915119 ps
CPU time 0.79 seconds
Started Jul 15 07:06:13 PM PDT 24
Finished Jul 15 07:06:17 PM PDT 24
Peak memory 206760 kb
Host smart-b6093444-c2e3-4c43-ae5c-0a3caa533c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30450
73639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3045073639
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2991495089
Short name T690
Test name
Test status
Simulation time 175212414 ps
CPU time 0.9 seconds
Started Jul 15 07:06:13 PM PDT 24
Finished Jul 15 07:06:18 PM PDT 24
Peak memory 206804 kb
Host smart-120c8219-069b-4c92-aeb0-cba172cc803e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29914
95089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2991495089
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3723749595
Short name T2490
Test name
Test status
Simulation time 224384286 ps
CPU time 0.83 seconds
Started Jul 15 07:06:10 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206792 kb
Host smart-f30a6ada-e549-4f6d-a5eb-0aa1ece8ff7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37237
49595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3723749595
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3432812669
Short name T2157
Test name
Test status
Simulation time 152584526 ps
CPU time 0.78 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 206808 kb
Host smart-f2b43693-33a9-44c5-b4c3-ee2811762bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34328
12669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3432812669
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2198081623
Short name T22
Test name
Test status
Simulation time 226328029 ps
CPU time 0.93 seconds
Started Jul 15 07:06:10 PM PDT 24
Finished Jul 15 07:06:13 PM PDT 24
Peak memory 206832 kb
Host smart-92068e91-4842-425c-9c18-dcd7361ce16a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2198081623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2198081623
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3818715149
Short name T1345
Test name
Test status
Simulation time 158145042 ps
CPU time 0.75 seconds
Started Jul 15 07:06:14 PM PDT 24
Finished Jul 15 07:06:19 PM PDT 24
Peak memory 206788 kb
Host smart-2a63990d-5c97-4b13-ad67-59b0179a517c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38187
15149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3818715149
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3257668786
Short name T2650
Test name
Test status
Simulation time 32430369 ps
CPU time 0.65 seconds
Started Jul 15 07:06:12 PM PDT 24
Finished Jul 15 07:06:15 PM PDT 24
Peak memory 206796 kb
Host smart-ac51e6df-3ab8-47ac-92ac-c7b2bbe5dbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
68786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3257668786
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.4202886210
Short name T1322
Test name
Test status
Simulation time 21987712487 ps
CPU time 48.8 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 207052 kb
Host smart-2b893da4-125c-4537-9553-c3fe7e1ad79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42028
86210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.4202886210
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1923597443
Short name T1483
Test name
Test status
Simulation time 188131567 ps
CPU time 0.91 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 206796 kb
Host smart-ba7db571-e133-4d6c-8660-cb2c3d0d1d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
97443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1923597443
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3534601427
Short name T336
Test name
Test status
Simulation time 215113036 ps
CPU time 0.91 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 206820 kb
Host smart-4af82c2f-f0dc-406a-b8ae-39c07fb74981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35346
01427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3534601427
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3570938157
Short name T2022
Test name
Test status
Simulation time 224584429 ps
CPU time 0.85 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 206848 kb
Host smart-666fe920-eb84-4763-b700-e280dfb2cabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35709
38157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3570938157
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.369297360
Short name T1573
Test name
Test status
Simulation time 196087016 ps
CPU time 0.9 seconds
Started Jul 15 07:06:13 PM PDT 24
Finished Jul 15 07:06:17 PM PDT 24
Peak memory 206816 kb
Host smart-515eb2c9-9869-4106-bd2d-492bdf07a5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36929
7360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.369297360
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3769130355
Short name T790
Test name
Test status
Simulation time 196150983 ps
CPU time 0.84 seconds
Started Jul 15 07:06:12 PM PDT 24
Finished Jul 15 07:06:16 PM PDT 24
Peak memory 206700 kb
Host smart-0584af54-8467-4b9d-96d6-2f42570f4d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691
30355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3769130355
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.4233792320
Short name T2187
Test name
Test status
Simulation time 164786648 ps
CPU time 0.8 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:14 PM PDT 24
Peak memory 206768 kb
Host smart-aeadf614-a9f1-4a1c-989d-7cff6d386219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42337
92320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.4233792320
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3950904497
Short name T2369
Test name
Test status
Simulation time 198819305 ps
CPU time 0.81 seconds
Started Jul 15 07:06:12 PM PDT 24
Finished Jul 15 07:06:16 PM PDT 24
Peak memory 206824 kb
Host smart-3b3bf524-1538-498d-8330-e90287eef635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
04497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3950904497
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3875670388
Short name T908
Test name
Test status
Simulation time 226540650 ps
CPU time 0.94 seconds
Started Jul 15 07:06:12 PM PDT 24
Finished Jul 15 07:06:17 PM PDT 24
Peak memory 206832 kb
Host smart-90d1e162-9427-47ae-b48b-a115edfbe3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756
70388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3875670388
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.124957733
Short name T711
Test name
Test status
Simulation time 6249965451 ps
CPU time 58.57 seconds
Started Jul 15 07:06:13 PM PDT 24
Finished Jul 15 07:07:15 PM PDT 24
Peak memory 207028 kb
Host smart-2a190b0a-e51e-4bb6-a4b8-e5bc8068166c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=124957733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.124957733
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1884931645
Short name T2500
Test name
Test status
Simulation time 181830253 ps
CPU time 0.8 seconds
Started Jul 15 07:06:13 PM PDT 24
Finished Jul 15 07:06:17 PM PDT 24
Peak memory 206808 kb
Host smart-e18c23eb-d2b3-46ce-ab13-5c97d27060a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18849
31645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1884931645
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.545743138
Short name T2725
Test name
Test status
Simulation time 167391900 ps
CPU time 0.8 seconds
Started Jul 15 07:06:12 PM PDT 24
Finished Jul 15 07:06:17 PM PDT 24
Peak memory 206800 kb
Host smart-c52a6a1e-7f6e-4b04-8411-3236af25f30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54574
3138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.545743138
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.2524208684
Short name T430
Test name
Test status
Simulation time 453395207 ps
CPU time 1.32 seconds
Started Jul 15 07:06:11 PM PDT 24
Finished Jul 15 07:06:15 PM PDT 24
Peak memory 206756 kb
Host smart-b78959fe-8d2b-4755-8571-a9f44df50d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25242
08684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2524208684
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1622804002
Short name T1313
Test name
Test status
Simulation time 5675942159 ps
CPU time 165.01 seconds
Started Jul 15 07:06:13 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 207032 kb
Host smart-9ebeeb90-b103-4f94-9f99-ca37eff9953b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
04002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1622804002
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.4046862708
Short name T2334
Test name
Test status
Simulation time 41703802 ps
CPU time 0.64 seconds
Started Jul 15 07:03:07 PM PDT 24
Finished Jul 15 07:03:08 PM PDT 24
Peak memory 206776 kb
Host smart-9553edca-12a4-4021-a4ac-b3fe535ebaca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4046862708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.4046862708
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3301705121
Short name T2556
Test name
Test status
Simulation time 13334399688 ps
CPU time 12.35 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 206832 kb
Host smart-37ba22bc-8825-41f4-b6cc-7097b4c76262
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3301705121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3301705121
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.414559914
Short name T911
Test name
Test status
Simulation time 23368877416 ps
CPU time 21.36 seconds
Started Jul 15 07:02:56 PM PDT 24
Finished Jul 15 07:03:18 PM PDT 24
Peak memory 206960 kb
Host smart-50110e48-9bdc-4ab6-b9f6-12d0bacee28f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=414559914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.414559914
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2777483136
Short name T2108
Test name
Test status
Simulation time 187752798 ps
CPU time 0.81 seconds
Started Jul 15 07:02:55 PM PDT 24
Finished Jul 15 07:02:56 PM PDT 24
Peak memory 206756 kb
Host smart-2354e6ca-b9d2-4fc4-8682-3a1361f54f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27774
83136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2777483136
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.3555125150
Short name T57
Test name
Test status
Simulation time 138125659 ps
CPU time 0.79 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:04 PM PDT 24
Peak memory 206812 kb
Host smart-30d4e5aa-fecf-4c78-8b3e-3cc8a8ab228b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551
25150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.3555125150
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3282898562
Short name T1985
Test name
Test status
Simulation time 139418444 ps
CPU time 0.78 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 206816 kb
Host smart-cf7e87e6-7474-41f4-bc86-d10e939ef1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32828
98562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3282898562
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.831556880
Short name T1089
Test name
Test status
Simulation time 432150303 ps
CPU time 1.52 seconds
Started Jul 15 07:02:59 PM PDT 24
Finished Jul 15 07:03:01 PM PDT 24
Peak memory 206336 kb
Host smart-39008360-9efa-4add-8516-b451017f1eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83155
6880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.831556880
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3735749735
Short name T1427
Test name
Test status
Simulation time 1113072482 ps
CPU time 2.52 seconds
Started Jul 15 07:02:59 PM PDT 24
Finished Jul 15 07:03:02 PM PDT 24
Peak memory 206960 kb
Host smart-16a8bcbd-9488-442b-adb0-dcdd25b84480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37357
49735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3735749735
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1138028826
Short name T891
Test name
Test status
Simulation time 17047771079 ps
CPU time 30.86 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:36 PM PDT 24
Peak memory 207008 kb
Host smart-c066e05d-5320-412e-a3c6-ae84dc2bdb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11380
28826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1138028826
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.4055176694
Short name T1537
Test name
Test status
Simulation time 411643826 ps
CPU time 1.3 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:05 PM PDT 24
Peak memory 206836 kb
Host smart-966e48cb-8de6-4c74-ab0b-04cfa53143cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40551
76694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.4055176694
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3936858912
Short name T2292
Test name
Test status
Simulation time 140231117 ps
CPU time 0.76 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 206796 kb
Host smart-e261cfe6-4d79-4907-a7c4-a6c0aaf85eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39368
58912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3936858912
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.84034907
Short name T1861
Test name
Test status
Simulation time 43905466 ps
CPU time 0.65 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:06 PM PDT 24
Peak memory 206760 kb
Host smart-2488e247-f92c-4606-aec3-f91f33415d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84034
907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.84034907
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3795722774
Short name T620
Test name
Test status
Simulation time 816400907 ps
CPU time 1.87 seconds
Started Jul 15 07:02:59 PM PDT 24
Finished Jul 15 07:03:01 PM PDT 24
Peak memory 206952 kb
Host smart-6d828823-3320-4912-abe8-ea210445a0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37957
22774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3795722774
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.717455598
Short name T872
Test name
Test status
Simulation time 219818883 ps
CPU time 1.51 seconds
Started Jul 15 07:02:57 PM PDT 24
Finished Jul 15 07:02:59 PM PDT 24
Peak memory 207004 kb
Host smart-82fe5d73-68bb-4834-bad7-703b2e09aa7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71745
5598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.717455598
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1922483687
Short name T748
Test name
Test status
Simulation time 95187957217 ps
CPU time 137.4 seconds
Started Jul 15 07:03:01 PM PDT 24
Finished Jul 15 07:05:19 PM PDT 24
Peak memory 207048 kb
Host smart-9ef09e21-29c0-4a2f-942d-9e3f4e92fdf5
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1922483687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1922483687
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.696256054
Short name T392
Test name
Test status
Simulation time 117311748048 ps
CPU time 155.7 seconds
Started Jul 15 07:02:56 PM PDT 24
Finished Jul 15 07:05:32 PM PDT 24
Peak memory 207124 kb
Host smart-8de4836a-84a1-4ab8-8e2c-5b7562bd183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696256054 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.696256054
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.3264892602
Short name T2146
Test name
Test status
Simulation time 119093919644 ps
CPU time 160.58 seconds
Started Jul 15 07:03:01 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 206980 kb
Host smart-b265c064-4870-45e8-9033-bb33d143a990
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3264892602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.3264892602
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1877626062
Short name T1692
Test name
Test status
Simulation time 96188956763 ps
CPU time 128.95 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:05:12 PM PDT 24
Peak memory 207052 kb
Host smart-d7979873-b444-4f24-90e6-9458b0c758c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877626062 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1877626062
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.1297562503
Short name T1674
Test name
Test status
Simulation time 101199991573 ps
CPU time 123.08 seconds
Started Jul 15 07:03:05 PM PDT 24
Finished Jul 15 07:05:09 PM PDT 24
Peak memory 207076 kb
Host smart-beeb4aa4-92ad-4f45-ad5e-508c8a09ecbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12975
62503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.1297562503
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1495468288
Short name T772
Test name
Test status
Simulation time 222291013 ps
CPU time 0.92 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:03 PM PDT 24
Peak memory 206840 kb
Host smart-0098a8b9-76e2-4cdf-8031-7be9455e59df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14954
68288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1495468288
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2764960615
Short name T1186
Test name
Test status
Simulation time 136587931 ps
CPU time 0.76 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:03 PM PDT 24
Peak memory 206792 kb
Host smart-f30d1d61-a0ee-47d1-bfda-76fd5f578c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27649
60615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2764960615
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.4277522295
Short name T2199
Test name
Test status
Simulation time 207342002 ps
CPU time 1.01 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:04 PM PDT 24
Peak memory 206816 kb
Host smart-70a1166b-ad96-4de4-baf8-616cd4a03be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42775
22295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.4277522295
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.1500072232
Short name T2557
Test name
Test status
Simulation time 5426916566 ps
CPU time 139.21 seconds
Started Jul 15 07:03:05 PM PDT 24
Finished Jul 15 07:05:25 PM PDT 24
Peak memory 207008 kb
Host smart-169f7893-1e4c-40e1-9dd2-859401beb6d1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1500072232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.1500072232
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3910098594
Short name T643
Test name
Test status
Simulation time 248871397 ps
CPU time 0.95 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:04 PM PDT 24
Peak memory 206568 kb
Host smart-b65535df-0f8d-4097-8f87-4b14a052b987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39100
98594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3910098594
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.678987107
Short name T961
Test name
Test status
Simulation time 23323589523 ps
CPU time 22.81 seconds
Started Jul 15 07:03:05 PM PDT 24
Finished Jul 15 07:03:29 PM PDT 24
Peak memory 206896 kb
Host smart-fb5c8f1f-ed25-4f95-b190-aedd7602bb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67898
7107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.678987107
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.276786911
Short name T1228
Test name
Test status
Simulation time 3386584771 ps
CPU time 4.07 seconds
Started Jul 15 07:03:00 PM PDT 24
Finished Jul 15 07:03:05 PM PDT 24
Peak memory 206764 kb
Host smart-94cd30f6-f2d9-4031-a2d4-7dd10a034014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
6911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.276786911
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2306839878
Short name T4
Test name
Test status
Simulation time 14027706877 ps
CPU time 134.87 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:05:20 PM PDT 24
Peak memory 207076 kb
Host smart-772cf3bd-aedf-4cb3-8212-d4c133ddd2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23068
39878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2306839878
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.420782585
Short name T1437
Test name
Test status
Simulation time 4650317400 ps
CPU time 130.99 seconds
Started Jul 15 07:03:03 PM PDT 24
Finished Jul 15 07:05:15 PM PDT 24
Peak memory 207092 kb
Host smart-16e1db68-4cce-4494-aad5-a31e507a488b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=420782585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.420782585
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3913396188
Short name T1296
Test name
Test status
Simulation time 244841397 ps
CPU time 0.99 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:06 PM PDT 24
Peak memory 206828 kb
Host smart-75fda2f3-3943-4f35-871a-f09cba505863
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3913396188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3913396188
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1432100016
Short name T199
Test name
Test status
Simulation time 220871801 ps
CPU time 0.88 seconds
Started Jul 15 07:03:01 PM PDT 24
Finished Jul 15 07:03:02 PM PDT 24
Peak memory 206808 kb
Host smart-76afdc13-c9c9-4c30-a065-be3b74f01acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14321
00016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1432100016
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2751842872
Short name T1911
Test name
Test status
Simulation time 5521290411 ps
CPU time 51.97 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 207044 kb
Host smart-b3faa932-f633-4a25-aeaa-950143413a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27518
42872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2751842872
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3880580838
Short name T909
Test name
Test status
Simulation time 5534632587 ps
CPU time 159.49 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:05:43 PM PDT 24
Peak memory 207040 kb
Host smart-02a398a9-7286-467c-beed-dc9f8138708d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3880580838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3880580838
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.608706373
Short name T607
Test name
Test status
Simulation time 161810645 ps
CPU time 0.85 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:06 PM PDT 24
Peak memory 206796 kb
Host smart-fc8fd096-15bc-491a-a918-7bd6cb6ed8f2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=608706373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.608706373
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3660499453
Short name T2361
Test name
Test status
Simulation time 148528155 ps
CPU time 0.79 seconds
Started Jul 15 07:03:05 PM PDT 24
Finished Jul 15 07:03:07 PM PDT 24
Peak memory 206784 kb
Host smart-2ffd2fbc-074a-4050-a210-9a3dba4dd205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36604
99453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3660499453
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4281097732
Short name T116
Test name
Test status
Simulation time 189610957 ps
CPU time 0.86 seconds
Started Jul 15 07:03:05 PM PDT 24
Finished Jul 15 07:03:07 PM PDT 24
Peak memory 206840 kb
Host smart-e183249f-ca85-42a5-ad26-541a3a04e73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42810
97732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4281097732
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1363113486
Short name T91
Test name
Test status
Simulation time 190665125 ps
CPU time 0.9 seconds
Started Jul 15 07:03:03 PM PDT 24
Finished Jul 15 07:03:05 PM PDT 24
Peak memory 206812 kb
Host smart-19433cab-f840-403f-8830-dbe680eda0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13631
13486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1363113486
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2083594780
Short name T2565
Test name
Test status
Simulation time 152836911 ps
CPU time 0.8 seconds
Started Jul 15 07:03:05 PM PDT 24
Finished Jul 15 07:03:07 PM PDT 24
Peak memory 206824 kb
Host smart-b4936310-707a-485d-9f62-8c2f0891bf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20835
94780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2083594780
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3922841871
Short name T1551
Test name
Test status
Simulation time 165749831 ps
CPU time 0.87 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:04 PM PDT 24
Peak memory 206796 kb
Host smart-355f8408-3ed4-4565-a53d-8c5e818513ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39228
41871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3922841871
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3688213788
Short name T1556
Test name
Test status
Simulation time 154313171 ps
CPU time 0.81 seconds
Started Jul 15 07:03:03 PM PDT 24
Finished Jul 15 07:03:05 PM PDT 24
Peak memory 206836 kb
Host smart-40781607-958d-406b-a524-0169c89e3e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36882
13788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3688213788
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1215130530
Short name T618
Test name
Test status
Simulation time 202791147 ps
CPU time 0.85 seconds
Started Jul 15 07:03:03 PM PDT 24
Finished Jul 15 07:03:05 PM PDT 24
Peak memory 206784 kb
Host smart-befe133d-c9fa-49b7-b6dc-52b0f6e2dd87
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1215130530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1215130530
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.597621206
Short name T2706
Test name
Test status
Simulation time 264862528 ps
CPU time 1.02 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:04 PM PDT 24
Peak memory 206760 kb
Host smart-123975c6-4477-45c3-a474-d9dbff3a9b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59762
1206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.597621206
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.961584809
Short name T544
Test name
Test status
Simulation time 146344062 ps
CPU time 0.77 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:05 PM PDT 24
Peak memory 206824 kb
Host smart-25d83a69-733b-45b1-8f16-33f61c69528c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96158
4809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.961584809
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.532767773
Short name T499
Test name
Test status
Simulation time 38928483 ps
CPU time 0.7 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:03 PM PDT 24
Peak memory 206824 kb
Host smart-74bc7147-340c-4a62-ad7f-1b28bdea8cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53276
7773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.532767773
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3195887620
Short name T1857
Test name
Test status
Simulation time 23789015321 ps
CPU time 51.29 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:54 PM PDT 24
Peak memory 206876 kb
Host smart-e0043eaf-8163-4176-99df-644a0132e926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31958
87620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3195887620
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2579004833
Short name T598
Test name
Test status
Simulation time 170748994 ps
CPU time 0.87 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:04 PM PDT 24
Peak memory 206796 kb
Host smart-a4bce1b3-f853-4cea-9615-749696334029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25790
04833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2579004833
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2634209638
Short name T811
Test name
Test status
Simulation time 256808533 ps
CPU time 0.92 seconds
Started Jul 15 07:03:03 PM PDT 24
Finished Jul 15 07:03:05 PM PDT 24
Peak memory 206808 kb
Host smart-7960b554-582d-4c44-9ff8-bb77acbf0744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26342
09638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2634209638
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.2539529157
Short name T2258
Test name
Test status
Simulation time 11044258439 ps
CPU time 57.51 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:04:03 PM PDT 24
Peak memory 207108 kb
Host smart-2a813249-a70a-4cf7-a0fd-b42f0d8ac96d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2539529157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2539529157
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3503754671
Short name T356
Test name
Test status
Simulation time 7205444586 ps
CPU time 37.04 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:43 PM PDT 24
Peak memory 207088 kb
Host smart-80acc03c-93ca-48ed-a8d9-c7394f39bda1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3503754671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3503754671
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.1616217236
Short name T873
Test name
Test status
Simulation time 11919408849 ps
CPU time 234.29 seconds
Started Jul 15 07:03:12 PM PDT 24
Finished Jul 15 07:07:07 PM PDT 24
Peak memory 207100 kb
Host smart-ea80fa6d-3d4e-4c08-babc-a2cde4728c7d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1616217236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1616217236
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2607619305
Short name T321
Test name
Test status
Simulation time 172406265 ps
CPU time 0.78 seconds
Started Jul 15 07:03:04 PM PDT 24
Finished Jul 15 07:03:06 PM PDT 24
Peak memory 206756 kb
Host smart-5b31df10-cf7e-46fd-b2ab-ab7176180f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
19305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2607619305
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1579217323
Short name T788
Test name
Test status
Simulation time 204227620 ps
CPU time 0.86 seconds
Started Jul 15 07:03:02 PM PDT 24
Finished Jul 15 07:03:03 PM PDT 24
Peak memory 206768 kb
Host smart-78218a61-5062-4a4d-bbeb-59022fd6c990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15792
17323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1579217323
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1324829706
Short name T2407
Test name
Test status
Simulation time 144986958 ps
CPU time 0.77 seconds
Started Jul 15 07:03:06 PM PDT 24
Finished Jul 15 07:03:08 PM PDT 24
Peak memory 206776 kb
Host smart-3046e91f-4a6b-48d2-bedb-2774a95e9083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13248
29706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1324829706
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2739441888
Short name T1915
Test name
Test status
Simulation time 169370647 ps
CPU time 0.78 seconds
Started Jul 15 07:03:09 PM PDT 24
Finished Jul 15 07:03:10 PM PDT 24
Peak memory 206736 kb
Host smart-7adb1dbf-2faf-455f-87a0-a79aeca65140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
41888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2739441888
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2407549674
Short name T178
Test name
Test status
Simulation time 609421221 ps
CPU time 1.44 seconds
Started Jul 15 07:03:08 PM PDT 24
Finished Jul 15 07:03:10 PM PDT 24
Peak memory 224444 kb
Host smart-e8fc9719-623e-4adc-8877-35de5ab61dbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2407549674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2407549674
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2614309807
Short name T2485
Test name
Test status
Simulation time 400540600 ps
CPU time 1.18 seconds
Started Jul 15 07:03:06 PM PDT 24
Finished Jul 15 07:03:08 PM PDT 24
Peak memory 206828 kb
Host smart-31245cd0-adb2-4e9a-93c3-58636511a564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26143
09807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2614309807
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2520152387
Short name T755
Test name
Test status
Simulation time 304454193 ps
CPU time 0.98 seconds
Started Jul 15 07:03:07 PM PDT 24
Finished Jul 15 07:03:08 PM PDT 24
Peak memory 206836 kb
Host smart-3992b83e-b457-4de2-bd1c-9ae5048da647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
52387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2520152387
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2782661949
Short name T2440
Test name
Test status
Simulation time 144108743 ps
CPU time 0.78 seconds
Started Jul 15 07:03:09 PM PDT 24
Finished Jul 15 07:03:11 PM PDT 24
Peak memory 206808 kb
Host smart-776aab94-0343-47de-b9c1-7ca0e2dc8246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27826
61949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2782661949
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.361270233
Short name T1184
Test name
Test status
Simulation time 162858701 ps
CPU time 0.82 seconds
Started Jul 15 07:03:08 PM PDT 24
Finished Jul 15 07:03:10 PM PDT 24
Peak memory 206808 kb
Host smart-b17be63d-8e12-4d5f-9ec6-512c88e46ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127
0233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.361270233
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.749553030
Short name T1655
Test name
Test status
Simulation time 229958637 ps
CPU time 0.98 seconds
Started Jul 15 07:03:07 PM PDT 24
Finished Jul 15 07:03:08 PM PDT 24
Peak memory 206788 kb
Host smart-1ac7ce73-b4d3-4083-a3d8-35b36367bb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74955
3030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.749553030
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1995807303
Short name T2268
Test name
Test status
Simulation time 5140577715 ps
CPU time 51.97 seconds
Started Jul 15 07:03:08 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 207096 kb
Host smart-4bcd6644-b214-4edd-ba17-d78b2a94d59a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1995807303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1995807303
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2674771357
Short name T358
Test name
Test status
Simulation time 168437585 ps
CPU time 0.85 seconds
Started Jul 15 07:03:08 PM PDT 24
Finished Jul 15 07:03:09 PM PDT 24
Peak memory 206788 kb
Host smart-3c13bebf-dc91-42c2-96fc-1637c5501d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
71357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2674771357
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.476569295
Short name T1704
Test name
Test status
Simulation time 182115873 ps
CPU time 0.85 seconds
Started Jul 15 07:03:08 PM PDT 24
Finished Jul 15 07:03:09 PM PDT 24
Peak memory 206844 kb
Host smart-bd9b1be0-ae34-48c9-944c-a8d8f9a92c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47656
9295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.476569295
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1516492321
Short name T424
Test name
Test status
Simulation time 1092553768 ps
CPU time 2.36 seconds
Started Jul 15 07:03:08 PM PDT 24
Finished Jul 15 07:03:11 PM PDT 24
Peak memory 207000 kb
Host smart-5b80a558-ff28-42fb-b265-759be9b4abc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15164
92321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1516492321
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.3636334664
Short name T517
Test name
Test status
Simulation time 4802682768 ps
CPU time 134.26 seconds
Started Jul 15 07:03:08 PM PDT 24
Finished Jul 15 07:05:22 PM PDT 24
Peak memory 207080 kb
Host smart-444e4041-6db5-4337-9553-583022e38eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36363
34664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.3636334664
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1492074324
Short name T2613
Test name
Test status
Simulation time 15063927288 ps
CPU time 81.71 seconds
Started Jul 15 07:03:08 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 207092 kb
Host smart-b3b503ad-f6c7-48db-aee9-e6f108fbda8c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1492074324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1492074324
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2848921489
Short name T885
Test name
Test status
Simulation time 41810136 ps
CPU time 0.7 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:36 PM PDT 24
Peak memory 206840 kb
Host smart-b234ca88-fee9-4d5a-b9be-f331ca205434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2848921489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2848921489
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.4053817782
Short name T1956
Test name
Test status
Simulation time 4383536476 ps
CPU time 5.06 seconds
Started Jul 15 07:06:10 PM PDT 24
Finished Jul 15 07:06:18 PM PDT 24
Peak memory 207056 kb
Host smart-8371163a-3044-4cf8-bf07-ee68bf3d3e2f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4053817782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.4053817782
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.378847330
Short name T820
Test name
Test status
Simulation time 13336319742 ps
CPU time 12.49 seconds
Started Jul 15 07:06:16 PM PDT 24
Finished Jul 15 07:06:32 PM PDT 24
Peak memory 207004 kb
Host smart-2211a9a5-306a-4baa-b482-3fe2227f048f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=378847330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.378847330
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.373578971
Short name T7
Test name
Test status
Simulation time 23354836883 ps
CPU time 26.28 seconds
Started Jul 15 07:06:17 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206872 kb
Host smart-a84867e9-344d-4826-90c2-33e04208761f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=373578971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.373578971
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2553611411
Short name T857
Test name
Test status
Simulation time 232265225 ps
CPU time 0.86 seconds
Started Jul 15 07:06:24 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 206824 kb
Host smart-1f7acad3-fe83-49a6-afba-240f76bb20f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25536
11411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2553611411
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1032378435
Short name T2669
Test name
Test status
Simulation time 143274079 ps
CPU time 0.77 seconds
Started Jul 15 07:06:18 PM PDT 24
Finished Jul 15 07:06:23 PM PDT 24
Peak memory 206824 kb
Host smart-68908c32-bd06-480c-8909-fafead50cc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10323
78435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1032378435
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1319736920
Short name T2340
Test name
Test status
Simulation time 557384849 ps
CPU time 1.66 seconds
Started Jul 15 07:06:17 PM PDT 24
Finished Jul 15 07:06:22 PM PDT 24
Peak memory 206956 kb
Host smart-0556d0a3-a08c-4b4c-8e2f-c4d8ab19273c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197
36920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1319736920
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.718361877
Short name T629
Test name
Test status
Simulation time 792616189 ps
CPU time 1.88 seconds
Started Jul 15 07:06:16 PM PDT 24
Finished Jul 15 07:06:21 PM PDT 24
Peak memory 206964 kb
Host smart-ef37620d-ad93-413c-81a7-8d65688c1b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71836
1877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.718361877
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2280808258
Short name T1930
Test name
Test status
Simulation time 21531334729 ps
CPU time 39.22 seconds
Started Jul 15 07:06:24 PM PDT 24
Finished Jul 15 07:07:13 PM PDT 24
Peak memory 207032 kb
Host smart-cd1eb3a6-9e9e-4c8f-8f4f-6abf23b402a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22808
08258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2280808258
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.962128169
Short name T2339
Test name
Test status
Simulation time 460384226 ps
CPU time 1.55 seconds
Started Jul 15 07:06:21 PM PDT 24
Finished Jul 15 07:06:30 PM PDT 24
Peak memory 206844 kb
Host smart-7b2db9e1-13c9-4b46-8caa-87681acc080f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96212
8169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.962128169
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1348765024
Short name T2412
Test name
Test status
Simulation time 144078474 ps
CPU time 0.78 seconds
Started Jul 15 07:06:17 PM PDT 24
Finished Jul 15 07:06:21 PM PDT 24
Peak memory 206760 kb
Host smart-a7c3c7cd-717c-4377-a8c0-34ad774b1dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13487
65024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1348765024
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3354531591
Short name T1218
Test name
Test status
Simulation time 68381475 ps
CPU time 0.7 seconds
Started Jul 15 07:06:18 PM PDT 24
Finished Jul 15 07:06:22 PM PDT 24
Peak memory 206832 kb
Host smart-ca339fc9-c3b2-4205-8c28-1503446fe2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
31591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3354531591
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.353235048
Short name T431
Test name
Test status
Simulation time 1052106138 ps
CPU time 2.74 seconds
Started Jul 15 07:06:21 PM PDT 24
Finished Jul 15 07:06:31 PM PDT 24
Peak memory 206988 kb
Host smart-3bf7fe7f-78f9-40c9-9396-f3cc4c5b5b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35323
5048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.353235048
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3053129480
Short name T2336
Test name
Test status
Simulation time 251345681 ps
CPU time 1.56 seconds
Started Jul 15 07:06:18 PM PDT 24
Finished Jul 15 07:06:23 PM PDT 24
Peak memory 207016 kb
Host smart-2d771aae-9d8f-4130-8431-f3218065ea06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30531
29480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3053129480
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3804085372
Short name T1246
Test name
Test status
Simulation time 203322275 ps
CPU time 0.9 seconds
Started Jul 15 07:06:19 PM PDT 24
Finished Jul 15 07:06:24 PM PDT 24
Peak memory 206772 kb
Host smart-45b7f30b-5603-432c-9a05-c70732ffc3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38040
85372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3804085372
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4215773739
Short name T337
Test name
Test status
Simulation time 174085325 ps
CPU time 0.84 seconds
Started Jul 15 07:06:19 PM PDT 24
Finished Jul 15 07:06:25 PM PDT 24
Peak memory 206820 kb
Host smart-20433957-b68c-4687-9cd3-cf8c414a8398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42157
73739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4215773739
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.868479339
Short name T724
Test name
Test status
Simulation time 220248494 ps
CPU time 0.87 seconds
Started Jul 15 07:06:18 PM PDT 24
Finished Jul 15 07:06:22 PM PDT 24
Peak memory 206820 kb
Host smart-41e24f51-b461-40de-a8a0-61e61336c7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86847
9339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.868479339
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.3678683422
Short name T207
Test name
Test status
Simulation time 8044800528 ps
CPU time 56.99 seconds
Started Jul 15 07:06:18 PM PDT 24
Finished Jul 15 07:07:18 PM PDT 24
Peak memory 207052 kb
Host smart-883c3146-f043-410c-91c3-c39210b2ecb6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3678683422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.3678683422
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.1568781090
Short name T344
Test name
Test status
Simulation time 4897862751 ps
CPU time 17.43 seconds
Started Jul 15 07:06:18 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206972 kb
Host smart-26dc5650-9121-4e58-8a4a-cd132deb6e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15687
81090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.1568781090
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1070191766
Short name T1951
Test name
Test status
Simulation time 214533972 ps
CPU time 0.94 seconds
Started Jul 15 07:06:16 PM PDT 24
Finished Jul 15 07:06:21 PM PDT 24
Peak memory 206792 kb
Host smart-b79c274b-56b9-4f62-ad7b-9d4ad023818e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701
91766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1070191766
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.499890038
Short name T2643
Test name
Test status
Simulation time 23290467443 ps
CPU time 29.07 seconds
Started Jul 15 07:06:18 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 206884 kb
Host smart-8ad9f452-65ba-4bba-b9ce-8bd245d68968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49989
0038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.499890038
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.172568865
Short name T476
Test name
Test status
Simulation time 3292828493 ps
CPU time 4.32 seconds
Started Jul 15 07:06:23 PM PDT 24
Finished Jul 15 07:06:38 PM PDT 24
Peak memory 206896 kb
Host smart-69155c85-f7fc-440f-8948-01c49f5d8ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17256
8865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.172568865
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.1052975874
Short name T701
Test name
Test status
Simulation time 9420191636 ps
CPU time 83.05 seconds
Started Jul 15 07:06:24 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 207096 kb
Host smart-9d77ff33-4046-4e89-ac7a-7eb5030a844b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10529
75874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1052975874
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.3550638681
Short name T1032
Test name
Test status
Simulation time 5019326032 ps
CPU time 45.51 seconds
Started Jul 15 07:06:19 PM PDT 24
Finished Jul 15 07:07:09 PM PDT 24
Peak memory 207012 kb
Host smart-80c2eb17-edcc-451b-9a70-e9a89843f321
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3550638681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.3550638681
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3366022076
Short name T1169
Test name
Test status
Simulation time 239913960 ps
CPU time 0.97 seconds
Started Jul 15 07:06:18 PM PDT 24
Finished Jul 15 07:06:23 PM PDT 24
Peak memory 206944 kb
Host smart-7346e05c-4a9a-43ad-bbef-779e646b7a1b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3366022076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3366022076
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.543389937
Short name T1355
Test name
Test status
Simulation time 196761308 ps
CPU time 0.86 seconds
Started Jul 15 07:06:16 PM PDT 24
Finished Jul 15 07:06:20 PM PDT 24
Peak memory 206832 kb
Host smart-ed5dcef8-0e65-474a-930a-f695ec85d970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54338
9937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.543389937
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.2475742466
Short name T1166
Test name
Test status
Simulation time 5702944892 ps
CPU time 51.96 seconds
Started Jul 15 07:06:23 PM PDT 24
Finished Jul 15 07:07:25 PM PDT 24
Peak memory 207040 kb
Host smart-aedb7ea9-f0ad-4cb0-9f70-c17880dbcd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24757
42466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.2475742466
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.3624121260
Short name T940
Test name
Test status
Simulation time 5551855035 ps
CPU time 52.67 seconds
Started Jul 15 07:06:23 PM PDT 24
Finished Jul 15 07:07:26 PM PDT 24
Peak memory 207076 kb
Host smart-4d35948d-f3cf-4c67-b0b0-65321c78cfcc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3624121260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.3624121260
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1809428326
Short name T32
Test name
Test status
Simulation time 168580947 ps
CPU time 0.83 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:36 PM PDT 24
Peak memory 206804 kb
Host smart-d50c80a5-7469-4ce5-bd34-7fec9e4c351a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1809428326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1809428326
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2897753127
Short name T1028
Test name
Test status
Simulation time 176857989 ps
CPU time 0.81 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206784 kb
Host smart-014f90b8-e2f4-48a8-a8d0-96bd34175648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28977
53127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2897753127
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2575155158
Short name T1999
Test name
Test status
Simulation time 196082943 ps
CPU time 0.86 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206832 kb
Host smart-c8e170cb-383a-420e-9765-ce9a9e8d03c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25751
55158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2575155158
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1223623171
Short name T347
Test name
Test status
Simulation time 189364061 ps
CPU time 0.88 seconds
Started Jul 15 07:06:31 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206756 kb
Host smart-147dc651-11e1-46e8-95ac-82c69446c516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12236
23171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1223623171
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2246016779
Short name T1749
Test name
Test status
Simulation time 150657037 ps
CPU time 0.8 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:38 PM PDT 24
Peak memory 206812 kb
Host smart-fef74b87-552b-498e-91a7-cc6f8bd31664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22460
16779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2246016779
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.4135057663
Short name T2236
Test name
Test status
Simulation time 148256114 ps
CPU time 0.77 seconds
Started Jul 15 07:06:23 PM PDT 24
Finished Jul 15 07:06:34 PM PDT 24
Peak memory 206788 kb
Host smart-25996a76-c502-4140-9683-5a71bd2cb1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41350
57663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.4135057663
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.764933117
Short name T2551
Test name
Test status
Simulation time 229023231 ps
CPU time 0.94 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:37 PM PDT 24
Peak memory 206800 kb
Host smart-f17a0e3a-e0b0-4609-8517-24b0590e0347
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=764933117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.764933117
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.333603499
Short name T1259
Test name
Test status
Simulation time 155434401 ps
CPU time 0.76 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:37 PM PDT 24
Peak memory 206812 kb
Host smart-2dee0673-42e2-47dd-8316-fcc55cc0af6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
3499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.333603499
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2864488351
Short name T2056
Test name
Test status
Simulation time 39393861 ps
CPU time 0.68 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:36 PM PDT 24
Peak memory 206772 kb
Host smart-b648180c-c643-4b2d-95f2-b78fc7f9eb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
88351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2864488351
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3132997125
Short name T257
Test name
Test status
Simulation time 7504675841 ps
CPU time 16.28 seconds
Started Jul 15 07:06:24 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 206976 kb
Host smart-6c6cb3fd-8feb-40d3-a1d9-fe246a829f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31329
97125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3132997125
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.17631378
Short name T1162
Test name
Test status
Simulation time 161943024 ps
CPU time 0.81 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:37 PM PDT 24
Peak memory 206792 kb
Host smart-f817a9e3-5c7d-45c0-ae6a-c6029d6b869c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17631
378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.17631378
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3804918732
Short name T781
Test name
Test status
Simulation time 225343189 ps
CPU time 0.87 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206784 kb
Host smart-ae5a3f9b-1cd4-49ae-b0ee-f2a519094954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38049
18732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3804918732
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.269025114
Short name T293
Test name
Test status
Simulation time 195731610 ps
CPU time 0.9 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206704 kb
Host smart-47cceeca-d328-4532-8aa6-465bab5cd74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26902
5114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.269025114
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3004590710
Short name T1625
Test name
Test status
Simulation time 154156062 ps
CPU time 0.76 seconds
Started Jul 15 07:06:31 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206832 kb
Host smart-5da28942-7e2d-4a7b-8e5d-11e8f29ec810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30045
90710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3004590710
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.638591174
Short name T2073
Test name
Test status
Simulation time 143587709 ps
CPU time 0.81 seconds
Started Jul 15 07:06:24 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 206812 kb
Host smart-f2372feb-7596-4e60-a8b7-d654e5ba3112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63859
1174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.638591174
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2523801533
Short name T2017
Test name
Test status
Simulation time 160054410 ps
CPU time 0.78 seconds
Started Jul 15 07:06:27 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206788 kb
Host smart-0906c1a3-0bd2-402c-a2cd-efc9752d1ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25238
01533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2523801533
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.113624244
Short name T2167
Test name
Test status
Simulation time 202932180 ps
CPU time 0.8 seconds
Started Jul 15 07:06:27 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206796 kb
Host smart-5baa2b0e-815e-44bb-b0ec-b861df693800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
4244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.113624244
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1722323336
Short name T440
Test name
Test status
Simulation time 227500204 ps
CPU time 0.98 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206968 kb
Host smart-46f043a3-2914-40a9-897c-201a5d757642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17223
23336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1722323336
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.3142923880
Short name T773
Test name
Test status
Simulation time 3408519689 ps
CPU time 31.59 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:07:09 PM PDT 24
Peak memory 207088 kb
Host smart-84319881-3690-4144-b9ba-03aec4c6ebe9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3142923880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3142923880
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1885884690
Short name T900
Test name
Test status
Simulation time 218841121 ps
CPU time 0.87 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206712 kb
Host smart-4c3913d7-b623-4f59-9159-dd6262eb525c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858
84690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1885884690
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.681402215
Short name T2165
Test name
Test status
Simulation time 232021907 ps
CPU time 0.86 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:39 PM PDT 24
Peak memory 206788 kb
Host smart-3cd00132-e04a-448a-943b-482e02110652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68140
2215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.681402215
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2170713762
Short name T948
Test name
Test status
Simulation time 814667442 ps
CPU time 1.92 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:38 PM PDT 24
Peak memory 207016 kb
Host smart-46dffafc-4a70-4eb4-bb92-91f693534831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21707
13762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2170713762
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.516316425
Short name T2092
Test name
Test status
Simulation time 4701626431 ps
CPU time 32.59 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:07:08 PM PDT 24
Peak memory 207000 kb
Host smart-95bacf19-3aea-4189-995b-e5cfd4e7bea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51631
6425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.516316425
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.4257316562
Short name T779
Test name
Test status
Simulation time 48603446 ps
CPU time 0.74 seconds
Started Jul 15 07:06:31 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206864 kb
Host smart-f74a5b3d-9ef5-4f1d-9dfa-2d9a70ae4923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4257316562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.4257316562
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2900341406
Short name T974
Test name
Test status
Simulation time 3454048344 ps
CPU time 4.49 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206892 kb
Host smart-323bc075-6802-469a-ba32-289c853a96cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2900341406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2900341406
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1095357902
Short name T831
Test name
Test status
Simulation time 13355968751 ps
CPU time 15.79 seconds
Started Jul 15 07:06:24 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 207068 kb
Host smart-b15b259e-d0a3-4bb2-b415-cd358fadcf6c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1095357902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1095357902
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3436989291
Short name T1414
Test name
Test status
Simulation time 23442590040 ps
CPU time 24.2 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:07:02 PM PDT 24
Peak memory 206984 kb
Host smart-1a39f552-7f18-4b23-8bf7-b97d76ddbe7b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3436989291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.3436989291
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.494402735
Short name T2198
Test name
Test status
Simulation time 199421745 ps
CPU time 0.9 seconds
Started Jul 15 07:06:36 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 206824 kb
Host smart-04de5815-98f4-4fe2-b70a-fcc69c12adff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49440
2735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.494402735
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3388259963
Short name T2123
Test name
Test status
Simulation time 140389419 ps
CPU time 0.82 seconds
Started Jul 15 07:06:23 PM PDT 24
Finished Jul 15 07:06:34 PM PDT 24
Peak memory 206812 kb
Host smart-a510fd2a-8218-49a5-b66f-36a8165d7d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33882
59963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3388259963
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1756228198
Short name T2215
Test name
Test status
Simulation time 598199136 ps
CPU time 1.75 seconds
Started Jul 15 07:06:23 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 206932 kb
Host smart-c850a409-2011-4cce-bb49-e061e207b966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17562
28198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1756228198
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.837516934
Short name T1729
Test name
Test status
Simulation time 1219919566 ps
CPU time 2.62 seconds
Started Jul 15 07:06:26 PM PDT 24
Finished Jul 15 07:06:40 PM PDT 24
Peak memory 206932 kb
Host smart-110c974a-2ffc-4ddb-9cf7-c1433cf27672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83751
6934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.837516934
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2924694371
Short name T2321
Test name
Test status
Simulation time 17819523892 ps
CPU time 32.51 seconds
Started Jul 15 07:06:30 PM PDT 24
Finished Jul 15 07:07:13 PM PDT 24
Peak memory 207076 kb
Host smart-9aff3b74-afa0-47c0-8736-a5c6d8104c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29246
94371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2924694371
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3826389154
Short name T2486
Test name
Test status
Simulation time 408055735 ps
CPU time 1.18 seconds
Started Jul 15 07:06:31 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206832 kb
Host smart-6c50765b-cd7c-4f23-b4db-584f3554a5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38263
89154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3826389154
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1980891747
Short name T2100
Test name
Test status
Simulation time 135311651 ps
CPU time 0.75 seconds
Started Jul 15 07:06:31 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206760 kb
Host smart-e33732ac-f429-41e6-bb2b-e78715b86f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19808
91747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1980891747
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3131930050
Short name T228
Test name
Test status
Simulation time 32311736 ps
CPU time 0.67 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 206788 kb
Host smart-44e79b95-c354-47a9-83cd-7e290fab0c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31319
30050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3131930050
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2531619700
Short name T2298
Test name
Test status
Simulation time 1017200906 ps
CPU time 2.66 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:40 PM PDT 24
Peak memory 206908 kb
Host smart-1103d11a-d1f4-4765-87e2-555411187457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25316
19700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2531619700
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.666260426
Short name T2280
Test name
Test status
Simulation time 337053429 ps
CPU time 1.78 seconds
Started Jul 15 07:06:24 PM PDT 24
Finished Jul 15 07:06:36 PM PDT 24
Peak memory 206948 kb
Host smart-033172e3-938d-489a-b363-849534cd151b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66626
0426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.666260426
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.4242818540
Short name T2344
Test name
Test status
Simulation time 251333833 ps
CPU time 0.88 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:38 PM PDT 24
Peak memory 206832 kb
Host smart-1ce34d73-3b4f-452f-8ecb-d310db7a8ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42428
18540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.4242818540
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3383515244
Short name T2094
Test name
Test status
Simulation time 145356955 ps
CPU time 0.78 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:37 PM PDT 24
Peak memory 206764 kb
Host smart-8193173c-10fb-45b2-8423-447ca29b1bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33835
15244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3383515244
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3967390092
Short name T1338
Test name
Test status
Simulation time 219101972 ps
CPU time 0.88 seconds
Started Jul 15 07:06:24 PM PDT 24
Finished Jul 15 07:06:35 PM PDT 24
Peak memory 206812 kb
Host smart-923a4395-e323-45b0-bc3b-20dbe996d8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39673
90092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3967390092
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1375334663
Short name T2296
Test name
Test status
Simulation time 194414463 ps
CPU time 0.87 seconds
Started Jul 15 07:06:25 PM PDT 24
Finished Jul 15 07:06:38 PM PDT 24
Peak memory 206800 kb
Host smart-50fe52fb-ffb9-4d8b-b997-6e493606b815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
34663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1375334663
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.1063639884
Short name T1270
Test name
Test status
Simulation time 23273505485 ps
CPU time 29.64 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:07:12 PM PDT 24
Peak memory 206872 kb
Host smart-d31fe448-bf5a-4e0b-9029-5c6c9c65cf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10636
39884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1063639884
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3888053910
Short name T2653
Test name
Test status
Simulation time 3300155355 ps
CPU time 3.91 seconds
Started Jul 15 07:06:39 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206876 kb
Host smart-3caf56db-c213-4fbf-8b7d-5c4a3011ee61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38880
53910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3888053910
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.69317455
Short name T2612
Test name
Test status
Simulation time 9540491735 ps
CPU time 67.23 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:07:49 PM PDT 24
Peak memory 207112 kb
Host smart-38c377aa-70c1-4480-ad81-4a2ac575f5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69317
455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.69317455
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2980977748
Short name T551
Test name
Test status
Simulation time 5300107873 ps
CPU time 152.74 seconds
Started Jul 15 07:06:34 PM PDT 24
Finished Jul 15 07:09:15 PM PDT 24
Peak memory 207016 kb
Host smart-5564ba0b-bfd3-4e03-b67e-86f0e4196d2b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2980977748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2980977748
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.108126225
Short name T2135
Test name
Test status
Simulation time 236709071 ps
CPU time 0.89 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206808 kb
Host smart-68ba485e-264c-4905-b4da-98d5d126a86b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=108126225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.108126225
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1227419845
Short name T653
Test name
Test status
Simulation time 199674557 ps
CPU time 0.95 seconds
Started Jul 15 07:06:31 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206812 kb
Host smart-2405fabc-ea02-4646-8563-e7c828c98178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12274
19845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1227419845
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2690848450
Short name T512
Test name
Test status
Simulation time 3753992154 ps
CPU time 27.05 seconds
Started Jul 15 07:06:40 PM PDT 24
Finished Jul 15 07:07:12 PM PDT 24
Peak memory 207092 kb
Host smart-52d15daa-ae08-4fb0-b9ec-04922e3b140e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26908
48450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2690848450
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3730292903
Short name T1763
Test name
Test status
Simulation time 3281521146 ps
CPU time 32.75 seconds
Started Jul 15 07:06:39 PM PDT 24
Finished Jul 15 07:07:17 PM PDT 24
Peak memory 207016 kb
Host smart-ade04eb5-80e3-492c-bee6-d5ef2a597d2c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3730292903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3730292903
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2890145246
Short name T1535
Test name
Test status
Simulation time 144169524 ps
CPU time 0.82 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206828 kb
Host smart-f0018027-e502-4bdb-8cee-6f64331cd30c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2890145246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2890145246
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.392919770
Short name T707
Test name
Test status
Simulation time 141931413 ps
CPU time 0.76 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206764 kb
Host smart-991fca2f-151f-442e-a81d-2115398594e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39291
9770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.392919770
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1097241768
Short name T110
Test name
Test status
Simulation time 255962248 ps
CPU time 0.86 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206800 kb
Host smart-da82d642-fd89-4d32-bf7b-5a381fca0862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10972
41768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1097241768
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.899259376
Short name T1333
Test name
Test status
Simulation time 179343208 ps
CPU time 0.82 seconds
Started Jul 15 07:06:32 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 205952 kb
Host smart-7f93e462-02bf-472b-8cb4-e8b71a2b352b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89925
9376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.899259376
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3853253213
Short name T2305
Test name
Test status
Simulation time 187869628 ps
CPU time 0.85 seconds
Started Jul 15 07:06:29 PM PDT 24
Finished Jul 15 07:06:41 PM PDT 24
Peak memory 206792 kb
Host smart-f8558371-696a-4b54-8160-b1f7ca6e6bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38532
53213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3853253213
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.648170101
Short name T1627
Test name
Test status
Simulation time 175580901 ps
CPU time 0.86 seconds
Started Jul 15 07:06:33 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206836 kb
Host smart-5eb72fe9-4373-41e5-91fa-dfd6fbfed04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64817
0101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.648170101
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.518169028
Short name T2107
Test name
Test status
Simulation time 152575628 ps
CPU time 0.81 seconds
Started Jul 15 07:06:36 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 206760 kb
Host smart-c2cddb78-ccd3-46b8-9108-bd1de167577f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51816
9028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.518169028
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1838113665
Short name T2467
Test name
Test status
Simulation time 233377448 ps
CPU time 0.96 seconds
Started Jul 15 07:06:32 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206816 kb
Host smart-f78a625b-2b44-46b6-b5c8-b62391fc30fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1838113665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1838113665
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.157074700
Short name T1705
Test name
Test status
Simulation time 138409199 ps
CPU time 0.76 seconds
Started Jul 15 07:06:36 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 206804 kb
Host smart-f114ce9b-382e-494d-a5f6-dc5f03c1cc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15707
4700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.157074700
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.772975541
Short name T2285
Test name
Test status
Simulation time 104302183 ps
CPU time 0.75 seconds
Started Jul 15 07:06:31 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206820 kb
Host smart-bc35ec6c-b33d-44d2-b3eb-9a3876f8fb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77297
5541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.772975541
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.46391730
Short name T2717
Test name
Test status
Simulation time 15535915303 ps
CPU time 32.35 seconds
Started Jul 15 07:06:35 PM PDT 24
Finished Jul 15 07:07:15 PM PDT 24
Peak memory 207052 kb
Host smart-b1ad9626-b49f-4204-b909-9373bba1c75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46391
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.46391730
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3762369766
Short name T994
Test name
Test status
Simulation time 191676051 ps
CPU time 0.82 seconds
Started Jul 15 07:06:32 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206796 kb
Host smart-7e7ec7dc-1107-4132-bbe7-7cfb03b7ff1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37623
69766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3762369766
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.552780183
Short name T702
Test name
Test status
Simulation time 220296137 ps
CPU time 0.92 seconds
Started Jul 15 07:06:34 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 206820 kb
Host smart-ff6defda-917e-4c7e-8f2a-de8bccb9f980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55278
0183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.552780183
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1883902331
Short name T354
Test name
Test status
Simulation time 198431253 ps
CPU time 0.84 seconds
Started Jul 15 07:06:34 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206828 kb
Host smart-0bab9d99-6171-4973-8068-817043a5cf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
02331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1883902331
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2048963585
Short name T1621
Test name
Test status
Simulation time 159347876 ps
CPU time 0.77 seconds
Started Jul 15 07:06:32 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206844 kb
Host smart-4aaec7de-c176-4ff3-b61c-72b4d34eb03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20489
63585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2048963585
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.231481490
Short name T665
Test name
Test status
Simulation time 138312683 ps
CPU time 0.77 seconds
Started Jul 15 07:06:37 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 206788 kb
Host smart-6b3d585e-f205-4961-bcee-a28937383135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23148
1490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.231481490
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2767381557
Short name T2574
Test name
Test status
Simulation time 194547690 ps
CPU time 0.81 seconds
Started Jul 15 07:06:35 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 206808 kb
Host smart-c1bd0c53-d263-464d-bc8e-280db22627c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27673
81557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2767381557
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3893871835
Short name T2456
Test name
Test status
Simulation time 193275750 ps
CPU time 0.86 seconds
Started Jul 15 07:06:34 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206796 kb
Host smart-e0f21dc4-6e16-4013-8fd7-4eb601ebf882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38938
71835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3893871835
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2786711541
Short name T2039
Test name
Test status
Simulation time 249292441 ps
CPU time 0.94 seconds
Started Jul 15 07:06:36 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 206792 kb
Host smart-77c11b7f-c30a-4042-834f-3c4ac7f5f7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
11541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2786711541
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1999826702
Short name T876
Test name
Test status
Simulation time 6463990109 ps
CPU time 178.28 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:09:42 PM PDT 24
Peak memory 206992 kb
Host smart-fd4c783c-8306-4e31-8270-d4124e4140ac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1999826702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1999826702
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.972190993
Short name T1574
Test name
Test status
Simulation time 167039169 ps
CPU time 0.78 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:06:45 PM PDT 24
Peak memory 206828 kb
Host smart-a1cf73e9-bf5c-40ed-9b47-9ef47a794fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97219
0993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.972190993
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3364289672
Short name T617
Test name
Test status
Simulation time 155907168 ps
CPU time 0.81 seconds
Started Jul 15 07:06:31 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206812 kb
Host smart-54d48455-e07c-49be-8c1b-754bdfea6f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33642
89672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3364289672
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3122884703
Short name T966
Test name
Test status
Simulation time 211619178 ps
CPU time 0.87 seconds
Started Jul 15 07:06:30 PM PDT 24
Finished Jul 15 07:06:42 PM PDT 24
Peak memory 206792 kb
Host smart-9cc17659-0aa8-45cf-ba3e-dca2895a9063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31228
84703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3122884703
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2052890975
Short name T2477
Test name
Test status
Simulation time 4491665006 ps
CPU time 31 seconds
Started Jul 15 07:06:32 PM PDT 24
Finished Jul 15 07:07:13 PM PDT 24
Peak memory 207068 kb
Host smart-f04edf0a-1c63-468d-9112-08848deb8edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20528
90975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2052890975
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1473970671
Short name T2354
Test name
Test status
Simulation time 44707524 ps
CPU time 0.75 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 206860 kb
Host smart-ebbe7539-a524-4ba4-8355-3a4e193b5528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1473970671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1473970671
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2598979830
Short name T13
Test name
Test status
Simulation time 4070295256 ps
CPU time 4.52 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:06:49 PM PDT 24
Peak memory 206880 kb
Host smart-021c37fe-e692-4bea-ab12-f8ab4da11be8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2598979830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2598979830
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.2807374999
Short name T1199
Test name
Test status
Simulation time 13439685516 ps
CPU time 12.7 seconds
Started Jul 15 07:06:32 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206844 kb
Host smart-d0984d90-08ac-4a70-a60c-618fadb574d9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2807374999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2807374999
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.792169441
Short name T1122
Test name
Test status
Simulation time 23330458076 ps
CPU time 21.26 seconds
Started Jul 15 07:06:36 PM PDT 24
Finished Jul 15 07:07:05 PM PDT 24
Peak memory 207052 kb
Host smart-580dffc6-260e-4aaf-aa53-cb2258b16a30
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=792169441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.792169441
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1713422137
Short name T2301
Test name
Test status
Simulation time 160159507 ps
CPU time 0.77 seconds
Started Jul 15 07:06:40 PM PDT 24
Finished Jul 15 07:06:45 PM PDT 24
Peak memory 206824 kb
Host smart-2bb98100-9586-4a8a-b7c7-32674164df59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17134
22137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1713422137
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2818953114
Short name T1515
Test name
Test status
Simulation time 145606530 ps
CPU time 0.77 seconds
Started Jul 15 07:06:32 PM PDT 24
Finished Jul 15 07:06:43 PM PDT 24
Peak memory 206176 kb
Host smart-c07f4f78-84df-4d90-8254-7dce12235f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28189
53114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2818953114
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1084529204
Short name T2175
Test name
Test status
Simulation time 503721569 ps
CPU time 1.58 seconds
Started Jul 15 07:06:37 PM PDT 24
Finished Jul 15 07:06:45 PM PDT 24
Peak memory 206800 kb
Host smart-db2062a7-844f-49c3-a150-a9dab55b35da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10845
29204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1084529204
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3118943067
Short name T1680
Test name
Test status
Simulation time 1371207754 ps
CPU time 2.81 seconds
Started Jul 15 07:06:36 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206968 kb
Host smart-8b7c133c-888f-404f-9c9b-710d2456bbde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
43067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3118943067
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2327050682
Short name T2328
Test name
Test status
Simulation time 22307797120 ps
CPU time 38.14 seconds
Started Jul 15 07:06:36 PM PDT 24
Finished Jul 15 07:07:22 PM PDT 24
Peak memory 207012 kb
Host smart-71b175c1-f989-4e55-9197-58a847703ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23270
50682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2327050682
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2415592857
Short name T2025
Test name
Test status
Simulation time 459125782 ps
CPU time 1.32 seconds
Started Jul 15 07:06:40 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206832 kb
Host smart-e6ccf3bf-57fd-4993-8ff2-b1a74bb40104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24155
92857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2415592857
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.4187877489
Short name T1632
Test name
Test status
Simulation time 158575682 ps
CPU time 0.79 seconds
Started Jul 15 07:06:42 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206792 kb
Host smart-4ce46bad-879d-4e7d-a082-d7baec019e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41878
77489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.4187877489
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2168615188
Short name T549
Test name
Test status
Simulation time 35836186 ps
CPU time 0.67 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:06:45 PM PDT 24
Peak memory 206788 kb
Host smart-02be7452-88be-4a83-bd8e-cad97a061b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21686
15188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2168615188
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2775196007
Short name T2193
Test name
Test status
Simulation time 935682231 ps
CPU time 2.18 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206996 kb
Host smart-a87120c1-5e8b-45de-ab1b-7900274f8bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27751
96007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2775196007
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2205818565
Short name T168
Test name
Test status
Simulation time 217037492 ps
CPU time 1.87 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206916 kb
Host smart-86fa5d32-330b-4402-9334-2df779d6e3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22058
18565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2205818565
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3870584888
Short name T1017
Test name
Test status
Simulation time 197190658 ps
CPU time 0.87 seconds
Started Jul 15 07:06:42 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206812 kb
Host smart-9b912099-7542-4f55-83c6-bb1d489f92e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38705
84888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3870584888
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3597932040
Short name T463
Test name
Test status
Simulation time 136276444 ps
CPU time 0.71 seconds
Started Jul 15 07:06:40 PM PDT 24
Finished Jul 15 07:06:45 PM PDT 24
Peak memory 206824 kb
Host smart-3bf65fcc-ef5b-4668-b2e2-a5d428007dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35979
32040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3597932040
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.772784465
Short name T2095
Test name
Test status
Simulation time 174080655 ps
CPU time 0.9 seconds
Started Jul 15 07:06:37 PM PDT 24
Finished Jul 15 07:06:44 PM PDT 24
Peak memory 206820 kb
Host smart-f25da53c-8ee6-4a02-88f6-2668c2c7a2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77278
4465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.772784465
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1703913793
Short name T101
Test name
Test status
Simulation time 7637324452 ps
CPU time 51.74 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:07:36 PM PDT 24
Peak memory 207048 kb
Host smart-e3666916-67af-45e3-8f24-7428b4d8bd2c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1703913793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1703913793
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.4146800956
Short name T2206
Test name
Test status
Simulation time 9516829010 ps
CPU time 39.76 seconds
Started Jul 15 07:06:42 PM PDT 24
Finished Jul 15 07:07:25 PM PDT 24
Peak memory 207012 kb
Host smart-3ac7914c-f494-469f-9018-e82636958ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41468
00956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.4146800956
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.203511127
Short name T1120
Test name
Test status
Simulation time 209780077 ps
CPU time 0.93 seconds
Started Jul 15 07:06:39 PM PDT 24
Finished Jul 15 07:06:45 PM PDT 24
Peak memory 206792 kb
Host smart-6f322f27-4e76-4b11-9188-e342726b76af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20351
1127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.203511127
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1025122083
Short name T1856
Test name
Test status
Simulation time 23424518876 ps
CPU time 26.21 seconds
Started Jul 15 07:06:37 PM PDT 24
Finished Jul 15 07:07:10 PM PDT 24
Peak memory 206844 kb
Host smart-c20b2e6a-9906-450a-91ff-88aa83c43c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10251
22083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1025122083
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3227401258
Short name T370
Test name
Test status
Simulation time 3331257908 ps
CPU time 4.18 seconds
Started Jul 15 07:06:39 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206880 kb
Host smart-acb3cfeb-3641-42c2-9eed-7312e8c9e5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32274
01258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3227401258
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1657548030
Short name T1348
Test name
Test status
Simulation time 7186626821 ps
CPU time 48.93 seconds
Started Jul 15 07:06:43 PM PDT 24
Finished Jul 15 07:07:35 PM PDT 24
Peak memory 207080 kb
Host smart-8ea37baf-9589-43ab-8e6f-6d06e80ebedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16575
48030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1657548030
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.449206003
Short name T865
Test name
Test status
Simulation time 4804556856 ps
CPU time 135.06 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 207052 kb
Host smart-d180a3ca-513e-4d04-9499-15716cc9c530
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=449206003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.449206003
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2555470978
Short name T1211
Test name
Test status
Simulation time 242776822 ps
CPU time 0.92 seconds
Started Jul 15 07:06:41 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206836 kb
Host smart-45ba6968-6303-4cd5-b64b-2a792ce811d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2555470978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2555470978
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2743675353
Short name T2253
Test name
Test status
Simulation time 222223911 ps
CPU time 0.95 seconds
Started Jul 15 07:06:38 PM PDT 24
Finished Jul 15 07:06:45 PM PDT 24
Peak memory 206760 kb
Host smart-1f17506c-a8c7-4daf-8ebf-39181abe4772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27436
75353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2743675353
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.861099364
Short name T2053
Test name
Test status
Simulation time 4572626518 ps
CPU time 124.81 seconds
Started Jul 15 07:06:43 PM PDT 24
Finished Jul 15 07:08:50 PM PDT 24
Peak memory 207016 kb
Host smart-fb3cba51-ef23-41e4-85cd-f1e6c2a98896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86109
9364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.861099364
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1284586172
Short name T2513
Test name
Test status
Simulation time 5145000970 ps
CPU time 139.19 seconds
Started Jul 15 07:06:37 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 207036 kb
Host smart-afa9713e-ad1b-4ab4-b1df-1fe8c57ab440
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1284586172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1284586172
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.701941575
Short name T1288
Test name
Test status
Simulation time 155475839 ps
CPU time 0.85 seconds
Started Jul 15 07:06:46 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206792 kb
Host smart-6b4889dc-f679-46fe-9c57-a70af7b1d48b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=701941575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.701941575
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1206085021
Short name T1657
Test name
Test status
Simulation time 146641728 ps
CPU time 0.79 seconds
Started Jul 15 07:06:44 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 206812 kb
Host smart-38b309dc-b756-4e63-a1c6-d20224035021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060
85021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1206085021
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1025126419
Short name T134
Test name
Test status
Simulation time 251192396 ps
CPU time 0.88 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206824 kb
Host smart-7c3e28ce-1e65-4a5f-bda8-2f36c677c64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10251
26419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1025126419
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.108017349
Short name T728
Test name
Test status
Simulation time 230237218 ps
CPU time 0.85 seconds
Started Jul 15 07:06:42 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206800 kb
Host smart-ef8d681e-d8b7-463d-aee5-4fc9cbeffabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10801
7349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.108017349
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.770437256
Short name T1132
Test name
Test status
Simulation time 204140711 ps
CPU time 0.85 seconds
Started Jul 15 07:06:47 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206820 kb
Host smart-dfe7a8ef-32e4-4af8-b969-681cc2f0bc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77043
7256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.770437256
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2927762425
Short name T1795
Test name
Test status
Simulation time 157069448 ps
CPU time 0.75 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206824 kb
Host smart-44c09951-898c-4812-af8c-2875ca2c0b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29277
62425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2927762425
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3824883324
Short name T147
Test name
Test status
Simulation time 173277366 ps
CPU time 0.81 seconds
Started Jul 15 07:06:41 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206792 kb
Host smart-1b82f542-ad7b-4f67-9d5c-acedb0ff3968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38248
83324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3824883324
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2357615890
Short name T2509
Test name
Test status
Simulation time 269114971 ps
CPU time 0.93 seconds
Started Jul 15 07:06:43 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 206796 kb
Host smart-6ffce408-9a34-4723-b112-110f1903e5d6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2357615890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2357615890
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.804896725
Short name T1223
Test name
Test status
Simulation time 140142983 ps
CPU time 0.77 seconds
Started Jul 15 07:06:45 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 206800 kb
Host smart-c22b486e-9838-486b-8f81-7dc7dcd2a531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80489
6725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.804896725
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1189052511
Short name T2546
Test name
Test status
Simulation time 37718034 ps
CPU time 0.68 seconds
Started Jul 15 07:06:43 PM PDT 24
Finished Jul 15 07:06:46 PM PDT 24
Peak memory 206808 kb
Host smart-6abfb5d2-d82a-47c8-b825-1647e38bec8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
52511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1189052511
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.612114251
Short name T2127
Test name
Test status
Simulation time 7312620355 ps
CPU time 16.81 seconds
Started Jul 15 07:06:44 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 207036 kb
Host smart-bbcae425-9c40-48e7-90b5-37817383eb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61211
4251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.612114251
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3927367064
Short name T1021
Test name
Test status
Simulation time 176861436 ps
CPU time 0.81 seconds
Started Jul 15 07:06:43 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 206816 kb
Host smart-cfb32e0d-63a5-4e93-9681-c21c7ab59e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39273
67064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3927367064
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3173765619
Short name T314
Test name
Test status
Simulation time 160952603 ps
CPU time 0.84 seconds
Started Jul 15 07:06:50 PM PDT 24
Finished Jul 15 07:06:52 PM PDT 24
Peak memory 206824 kb
Host smart-61f739e4-af66-4bbe-9ddd-ce81e8ab2439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
65619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3173765619
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.4249113346
Short name T401
Test name
Test status
Simulation time 261916211 ps
CPU time 0.92 seconds
Started Jul 15 07:06:46 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206824 kb
Host smart-02d2ac7c-4e0f-408a-b680-63e4db39da66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42491
13346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.4249113346
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1183357103
Short name T1547
Test name
Test status
Simulation time 168971496 ps
CPU time 0.8 seconds
Started Jul 15 07:06:47 PM PDT 24
Finished Jul 15 07:06:49 PM PDT 24
Peak memory 206828 kb
Host smart-f968c51e-fbd5-4288-b305-92bf670a2860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11833
57103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1183357103
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1388873219
Short name T1595
Test name
Test status
Simulation time 162566403 ps
CPU time 0.79 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:53 PM PDT 24
Peak memory 206780 kb
Host smart-a0000f89-1efb-4e1d-8152-6bfdbe26b65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13888
73219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1388873219
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.598066495
Short name T2138
Test name
Test status
Simulation time 172028771 ps
CPU time 0.81 seconds
Started Jul 15 07:06:49 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 206820 kb
Host smart-e47bca96-3ec5-4b21-8189-0f1fb4ee95fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59806
6495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.598066495
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3549090661
Short name T2067
Test name
Test status
Simulation time 178859283 ps
CPU time 0.79 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 206092 kb
Host smart-8d4600fb-64ae-47af-86ab-54d4eeef4ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35490
90661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3549090661
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.273887989
Short name T889
Test name
Test status
Simulation time 193063773 ps
CPU time 0.87 seconds
Started Jul 15 07:06:50 PM PDT 24
Finished Jul 15 07:06:52 PM PDT 24
Peak memory 206820 kb
Host smart-4aec99c2-d6d2-4395-a1b9-3745e3f500f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27388
7989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.273887989
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.366169069
Short name T2228
Test name
Test status
Simulation time 5178549906 ps
CPU time 50.24 seconds
Started Jul 15 07:06:50 PM PDT 24
Finished Jul 15 07:07:42 PM PDT 24
Peak memory 207012 kb
Host smart-8a794ccb-ae7d-45d1-80bc-5d536fafbd79
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=366169069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.366169069
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1577102709
Short name T1836
Test name
Test status
Simulation time 167185352 ps
CPU time 0.87 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 206212 kb
Host smart-e10c3727-7c3b-4d60-bb46-8c495d7ec493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15771
02709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1577102709
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.4155686581
Short name T925
Test name
Test status
Simulation time 178165106 ps
CPU time 0.79 seconds
Started Jul 15 07:06:43 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 206836 kb
Host smart-449cc4a1-0fb9-4c93-9894-fec84ed5b3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41556
86581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.4155686581
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1865008852
Short name T1626
Test name
Test status
Simulation time 629092313 ps
CPU time 1.7 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206784 kb
Host smart-2df909ba-5df5-48fa-9e9d-e48ac322d736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18650
08852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1865008852
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2399547379
Short name T1168
Test name
Test status
Simulation time 5693977301 ps
CPU time 54.41 seconds
Started Jul 15 07:06:50 PM PDT 24
Finished Jul 15 07:07:46 PM PDT 24
Peak memory 207104 kb
Host smart-b637f868-fdae-4093-af7a-609b8d5718c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23995
47379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2399547379
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2853094001
Short name T685
Test name
Test status
Simulation time 55041124 ps
CPU time 0.69 seconds
Started Jul 15 07:06:49 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 206844 kb
Host smart-346b5f0a-9167-40c5-8ef4-e90cecf3ee32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2853094001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2853094001
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2233862323
Short name T2523
Test name
Test status
Simulation time 3928372236 ps
CPU time 4.48 seconds
Started Jul 15 07:06:46 PM PDT 24
Finished Jul 15 07:06:52 PM PDT 24
Peak memory 207028 kb
Host smart-1c2a1bef-e3b4-48a3-9ed6-57ef8a4dba01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2233862323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2233862323
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3901698134
Short name T1409
Test name
Test status
Simulation time 23374654682 ps
CPU time 22.42 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:07:12 PM PDT 24
Peak memory 206840 kb
Host smart-ebed89b5-41a8-4f2e-8730-91c8ae6fbe16
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3901698134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3901698134
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3962575509
Short name T2489
Test name
Test status
Simulation time 160748364 ps
CPU time 0.79 seconds
Started Jul 15 07:06:43 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 206824 kb
Host smart-f47e99c9-7d39-4ad7-bc0c-9dc33e41631f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39625
75509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3962575509
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.769481557
Short name T638
Test name
Test status
Simulation time 209306400 ps
CPU time 0.83 seconds
Started Jul 15 07:06:45 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206808 kb
Host smart-d33d07e6-88e1-4954-b445-ea092d1a8c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76948
1557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.769481557
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2812394895
Short name T844
Test name
Test status
Simulation time 424174356 ps
CPU time 1.2 seconds
Started Jul 15 07:06:43 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 206820 kb
Host smart-9086bd0d-b201-4263-b5a9-df05a74d8935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28123
94895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2812394895
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.320255918
Short name T1243
Test name
Test status
Simulation time 755743464 ps
CPU time 1.74 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 207044 kb
Host smart-ae9813f5-a314-4a05-9555-42d161f51215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32025
5918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.320255918
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.3838596545
Short name T2083
Test name
Test status
Simulation time 20438095671 ps
CPU time 33.1 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:07:22 PM PDT 24
Peak memory 207036 kb
Host smart-952d4f8a-69ca-4aac-bb98-8c47f7121232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38385
96545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.3838596545
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2931590440
Short name T769
Test name
Test status
Simulation time 361711487 ps
CPU time 1.37 seconds
Started Jul 15 07:06:45 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206808 kb
Host smart-7ac6b997-765e-4bb6-868f-0f1aa773ebde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29315
90440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2931590440
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.339114451
Short name T1751
Test name
Test status
Simulation time 141678795 ps
CPU time 0.81 seconds
Started Jul 15 07:06:44 PM PDT 24
Finished Jul 15 07:06:47 PM PDT 24
Peak memory 206700 kb
Host smart-306f69c9-1f57-40dc-ab9f-caa6e2b5723f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33911
4451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.339114451
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.285365442
Short name T1654
Test name
Test status
Simulation time 36950980 ps
CPU time 0.68 seconds
Started Jul 15 07:06:46 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206800 kb
Host smart-48b41fab-cec3-4d75-a42b-e7bcae0ebd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28536
5442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.285365442
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.4082330473
Short name T2186
Test name
Test status
Simulation time 855112650 ps
CPU time 1.93 seconds
Started Jul 15 07:06:47 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 207012 kb
Host smart-36b2f376-91e8-48dc-8f31-f3ab37260838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40823
30473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.4082330473
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.938433224
Short name T2084
Test name
Test status
Simulation time 190128884 ps
CPU time 2.09 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 206924 kb
Host smart-bb012820-8dc6-4080-aac9-328a6d5014ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93843
3224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.938433224
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3252074314
Short name T991
Test name
Test status
Simulation time 220283382 ps
CPU time 0.93 seconds
Started Jul 15 07:06:45 PM PDT 24
Finished Jul 15 07:06:48 PM PDT 24
Peak memory 206812 kb
Host smart-8446c2bf-773a-4765-873e-377e2a525eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520
74314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3252074314
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3820421256
Short name T1879
Test name
Test status
Simulation time 159203926 ps
CPU time 0.78 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 206808 kb
Host smart-545f50da-256e-4a01-8c10-a545fc7ad9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38204
21256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3820421256
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2363808872
Short name T810
Test name
Test status
Simulation time 248160248 ps
CPU time 0.96 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:06:49 PM PDT 24
Peak memory 206824 kb
Host smart-8c339e78-8377-48ff-b1ac-5caa8f94c1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23638
08872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2363808872
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.3040286618
Short name T414
Test name
Test status
Simulation time 6245765645 ps
CPU time 23.05 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:07:12 PM PDT 24
Peak memory 207020 kb
Host smart-14be92b8-fbc0-492f-8edc-6905c3832e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30402
86618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.3040286618
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1964504949
Short name T2495
Test name
Test status
Simulation time 218493079 ps
CPU time 0.87 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 206764 kb
Host smart-9084eb9b-eeb5-4ced-9ed5-fd47de995397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19645
04949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1964504949
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2882185217
Short name T1370
Test name
Test status
Simulation time 23256186451 ps
CPU time 24.1 seconds
Started Jul 15 07:06:47 PM PDT 24
Finished Jul 15 07:07:12 PM PDT 24
Peak memory 206848 kb
Host smart-adf0645d-bd8f-450d-84cf-c056ef12d928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28821
85217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2882185217
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2980412624
Short name T2434
Test name
Test status
Simulation time 3300988083 ps
CPU time 4.63 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 206888 kb
Host smart-49d49313-bab4-4304-ab25-095b036bf637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29804
12624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2980412624
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.2234950466
Short name T1159
Test name
Test status
Simulation time 13033244618 ps
CPU time 371.32 seconds
Started Jul 15 07:06:50 PM PDT 24
Finished Jul 15 07:13:02 PM PDT 24
Peak memory 207084 kb
Host smart-8aa8146a-1cf7-4116-982c-b01a72bd77a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22349
50466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.2234950466
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.923736883
Short name T1289
Test name
Test status
Simulation time 6883145985 ps
CPU time 66.91 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:07:59 PM PDT 24
Peak memory 207072 kb
Host smart-c7a1361c-812d-4249-982a-9875e017b374
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=923736883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.923736883
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.981809097
Short name T2614
Test name
Test status
Simulation time 243213264 ps
CPU time 0.88 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:53 PM PDT 24
Peak memory 206784 kb
Host smart-9e846425-aa8b-4906-b364-b097fd4deada
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=981809097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.981809097
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.382247711
Short name T2059
Test name
Test status
Simulation time 212517854 ps
CPU time 0.94 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206972 kb
Host smart-8cf17359-26a9-49c5-9cca-20ff0257a34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38224
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.382247711
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1327227615
Short name T922
Test name
Test status
Simulation time 4706833541 ps
CPU time 135.63 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:09:08 PM PDT 24
Peak memory 207040 kb
Host smart-ab5cff94-58ac-4fd6-81e8-5846ed905a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13272
27615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1327227615
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.805671955
Short name T338
Test name
Test status
Simulation time 4277322138 ps
CPU time 120.92 seconds
Started Jul 15 07:06:50 PM PDT 24
Finished Jul 15 07:08:53 PM PDT 24
Peak memory 206916 kb
Host smart-d3d920bf-671e-471e-922c-56c932c9e5ae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=805671955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.805671955
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.3817552711
Short name T2078
Test name
Test status
Simulation time 194499912 ps
CPU time 0.81 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206592 kb
Host smart-bff3af80-bd87-4018-9be9-ec3d9a872e11
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3817552711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.3817552711
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1681718573
Short name T2091
Test name
Test status
Simulation time 206109269 ps
CPU time 0.81 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:53 PM PDT 24
Peak memory 206812 kb
Host smart-2a28edf2-d48f-4a95-bf07-d697e40d33f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16817
18573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1681718573
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2070036782
Short name T133
Test name
Test status
Simulation time 159990740 ps
CPU time 0.81 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 206812 kb
Host smart-a3aefbcf-6018-40ec-90f0-69a0d9295f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20700
36782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2070036782
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3349681951
Short name T2742
Test name
Test status
Simulation time 162786513 ps
CPU time 0.9 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206784 kb
Host smart-da662610-2484-4781-b558-ffa7296ac89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33496
81951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3349681951
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2706827117
Short name T801
Test name
Test status
Simulation time 144947359 ps
CPU time 0.79 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 206764 kb
Host smart-e005fb88-c2ca-457d-b0eb-dfafa0fbb48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27068
27117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2706827117
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.817016737
Short name T407
Test name
Test status
Simulation time 182859858 ps
CPU time 0.78 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206800 kb
Host smart-a2414bda-461e-44e9-aaaa-89d4a5feb4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81701
6737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.817016737
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1968729993
Short name T1898
Test name
Test status
Simulation time 146018382 ps
CPU time 0.81 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206788 kb
Host smart-4d4b6c47-2bcc-4087-882e-33031e0e7928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19687
29993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1968729993
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1836150572
Short name T1206
Test name
Test status
Simulation time 253852059 ps
CPU time 0.94 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206924 kb
Host smart-9e11c85a-6005-4893-8906-c79482f292a5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1836150572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1836150572
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.268711419
Short name T1208
Test name
Test status
Simulation time 206329054 ps
CPU time 0.82 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 206840 kb
Host smart-8a0d3972-fef7-4f0a-ad19-05e76931f51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
1419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.268711419
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1957611666
Short name T2408
Test name
Test status
Simulation time 47398050 ps
CPU time 0.67 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 206804 kb
Host smart-c83860b5-4f2f-43d3-bdc4-e83b96dd24de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
11666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1957611666
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1607740186
Short name T1597
Test name
Test status
Simulation time 23190136498 ps
CPU time 55.2 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:07:49 PM PDT 24
Peak memory 207124 kb
Host smart-54ffaf03-94d9-427c-9419-dd4d02057886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16077
40186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1607740186
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1170487019
Short name T625
Test name
Test status
Simulation time 177327790 ps
CPU time 0.83 seconds
Started Jul 15 07:06:49 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 206828 kb
Host smart-443c2741-87ee-4823-bd99-319159cfb1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11704
87019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1170487019
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.693202574
Short name T1164
Test name
Test status
Simulation time 221363456 ps
CPU time 0.86 seconds
Started Jul 15 07:06:50 PM PDT 24
Finished Jul 15 07:06:53 PM PDT 24
Peak memory 206832 kb
Host smart-c977c14e-bff0-42ba-aa68-1e549b811f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69320
2574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.693202574
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.238046076
Short name T486
Test name
Test status
Simulation time 192850761 ps
CPU time 0.84 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 206768 kb
Host smart-35ddae2e-fe3b-43bc-865c-5551d962a10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23804
6076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.238046076
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3791968438
Short name T623
Test name
Test status
Simulation time 186807304 ps
CPU time 0.84 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206832 kb
Host smart-a4764710-1f6a-48e6-a7f0-c91db711715e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37919
68438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3791968438
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.161292294
Short name T1628
Test name
Test status
Simulation time 140021915 ps
CPU time 0.76 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 206812 kb
Host smart-f5c8840f-ab29-4b82-b4fe-1246d451dc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16129
2294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.161292294
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3795340351
Short name T1909
Test name
Test status
Simulation time 174139247 ps
CPU time 0.83 seconds
Started Jul 15 07:06:53 PM PDT 24
Finished Jul 15 07:06:56 PM PDT 24
Peak memory 206812 kb
Host smart-6f7ff32c-dfef-4027-ae06-b8e985d20f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37953
40351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3795340351
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2281886563
Short name T2473
Test name
Test status
Simulation time 156643088 ps
CPU time 0.77 seconds
Started Jul 15 07:06:49 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 206772 kb
Host smart-d9ce3e89-09a8-495e-af9f-e41a76aae904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22818
86563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2281886563
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3470163163
Short name T2360
Test name
Test status
Simulation time 200611139 ps
CPU time 0.89 seconds
Started Jul 15 07:06:49 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 206820 kb
Host smart-69780f84-e17b-4d91-97dc-cfc29f111308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34701
63163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3470163163
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1246879072
Short name T1742
Test name
Test status
Simulation time 4519014961 ps
CPU time 32.56 seconds
Started Jul 15 07:06:48 PM PDT 24
Finished Jul 15 07:07:22 PM PDT 24
Peak memory 207072 kb
Host smart-c9c7889e-d85e-4b96-ba4b-9ed51d2b0c4a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1246879072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1246879072
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1063022513
Short name T2530
Test name
Test status
Simulation time 175478849 ps
CPU time 0.79 seconds
Started Jul 15 07:06:49 PM PDT 24
Finished Jul 15 07:06:51 PM PDT 24
Peak memory 206772 kb
Host smart-2378f70e-92de-4ebd-a741-671e0cb2860f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10630
22513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1063022513
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1075001865
Short name T360
Test name
Test status
Simulation time 171805506 ps
CPU time 0.8 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 206800 kb
Host smart-119d22aa-be27-4601-a165-78d476a2cab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10750
01865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1075001865
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.729414821
Short name T921
Test name
Test status
Simulation time 211033820 ps
CPU time 0.98 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 206844 kb
Host smart-da6f7f87-6fe9-4771-bab6-62b7e11a4344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72941
4821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.729414821
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.989770958
Short name T1464
Test name
Test status
Simulation time 7353463738 ps
CPU time 198.83 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:10:13 PM PDT 24
Peak memory 207052 kb
Host smart-2a4a89f4-b74d-4670-99f3-b265b462a79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98977
0958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.989770958
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2537475964
Short name T2371
Test name
Test status
Simulation time 44203099 ps
CPU time 0.69 seconds
Started Jul 15 07:07:00 PM PDT 24
Finished Jul 15 07:07:02 PM PDT 24
Peak memory 206880 kb
Host smart-2ec261d2-f48d-4059-97da-57346e99f12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2537475964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2537475964
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3076605808
Short name T2389
Test name
Test status
Simulation time 3738150171 ps
CPU time 4.24 seconds
Started Jul 15 07:06:49 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 207092 kb
Host smart-0101775f-9a47-48d8-a7ff-c685d76fa073
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3076605808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3076605808
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.91684493
Short name T664
Test name
Test status
Simulation time 13305241595 ps
CPU time 12.57 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:07:07 PM PDT 24
Peak memory 206908 kb
Host smart-e653468c-1c9b-43bc-8cf5-e5c584d65744
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=91684493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.91684493
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2247030506
Short name T1948
Test name
Test status
Simulation time 23469595473 ps
CPU time 25.09 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:07:23 PM PDT 24
Peak memory 207056 kb
Host smart-ac74c41e-73cf-4736-916e-37191caca6da
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2247030506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2247030506
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1499929687
Short name T1605
Test name
Test status
Simulation time 194204013 ps
CPU time 0.86 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:59 PM PDT 24
Peak memory 206756 kb
Host smart-50d5abcd-9586-4a13-9129-33128a968ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14999
29687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1499929687
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1804722710
Short name T2364
Test name
Test status
Simulation time 177529942 ps
CPU time 0.8 seconds
Started Jul 15 07:06:49 PM PDT 24
Finished Jul 15 07:06:50 PM PDT 24
Peak memory 206848 kb
Host smart-14a04205-6986-4a40-88c5-e0fec28924da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18047
22710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1804722710
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1953329473
Short name T776
Test name
Test status
Simulation time 372152610 ps
CPU time 1.38 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 206752 kb
Host smart-52f6f3b7-d89b-4ad5-8ee4-08106c144cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533
29473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1953329473
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.981408313
Short name T1156
Test name
Test status
Simulation time 413789260 ps
CPU time 1.21 seconds
Started Jul 15 07:06:53 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 206820 kb
Host smart-b1eb62b5-614f-4669-8767-9f5870941935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98140
8313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.981408313
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.4243088286
Short name T1364
Test name
Test status
Simulation time 20439373212 ps
CPU time 39.28 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:07:36 PM PDT 24
Peak memory 207168 kb
Host smart-126baf12-ad00-4c01-8b2e-b6167e6c48b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42430
88286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.4243088286
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.4156728427
Short name T581
Test name
Test status
Simulation time 463274261 ps
CPU time 1.44 seconds
Started Jul 15 07:06:53 PM PDT 24
Finished Jul 15 07:06:56 PM PDT 24
Peak memory 206844 kb
Host smart-e82fdcd0-7be0-499c-8316-683ff33007ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
28427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.4156728427
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2933933841
Short name T1173
Test name
Test status
Simulation time 158513161 ps
CPU time 0.77 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206812 kb
Host smart-c2c38d35-965b-41f7-9e9a-58285c957b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
33841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2933933841
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1753628872
Short name T2680
Test name
Test status
Simulation time 41789835 ps
CPU time 0.72 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206780 kb
Host smart-9aeeb0ad-9f3a-473f-8d5a-b334710f080b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17536
28872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1753628872
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1421761052
Short name T1276
Test name
Test status
Simulation time 877883326 ps
CPU time 2.15 seconds
Started Jul 15 07:06:51 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 206972 kb
Host smart-be0e6aa0-1bf0-4726-be66-4cd01bce26e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14217
61052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1421761052
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1401071905
Short name T2397
Test name
Test status
Simulation time 172204287 ps
CPU time 1.9 seconds
Started Jul 15 07:06:53 PM PDT 24
Finished Jul 15 07:06:56 PM PDT 24
Peak memory 207040 kb
Host smart-96954ef7-dee4-4e97-b04c-d48d9fb390a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14010
71905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1401071905
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.861468285
Short name T1418
Test name
Test status
Simulation time 201830465 ps
CPU time 0.88 seconds
Started Jul 15 07:06:52 PM PDT 24
Finished Jul 15 07:06:55 PM PDT 24
Peak memory 206756 kb
Host smart-9646f010-446b-451f-bd46-1bfdad96cc7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86146
8285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.861468285
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1892958529
Short name T1854
Test name
Test status
Simulation time 145409115 ps
CPU time 0.74 seconds
Started Jul 15 07:06:53 PM PDT 24
Finished Jul 15 07:06:56 PM PDT 24
Peak memory 206792 kb
Host smart-844358cd-fa1c-4558-828a-4ffbab98638c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18929
58529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1892958529
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.4240941320
Short name T913
Test name
Test status
Simulation time 213986865 ps
CPU time 0.9 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 206844 kb
Host smart-746b2bf9-b3bc-49e9-8866-d47a60a1d77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42409
41320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.4240941320
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1624225425
Short name T1903
Test name
Test status
Simulation time 8592448948 ps
CPU time 225.85 seconds
Started Jul 15 07:06:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 207080 kb
Host smart-d478f2b2-a8ec-4467-b7e6-a750bc893dd4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1624225425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1624225425
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.2080876820
Short name T928
Test name
Test status
Simulation time 8423323819 ps
CPU time 73.95 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 206956 kb
Host smart-88831a44-3e80-4397-9084-b631b030236e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
76820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.2080876820
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.321849929
Short name T1920
Test name
Test status
Simulation time 233856768 ps
CPU time 0.91 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:06:59 PM PDT 24
Peak memory 206772 kb
Host smart-86a987b3-d202-407d-ad6c-2fd29d3bd880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32184
9929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.321849929
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.199894840
Short name T220
Test name
Test status
Simulation time 23341441948 ps
CPU time 23.98 seconds
Started Jul 15 07:06:57 PM PDT 24
Finished Jul 15 07:07:23 PM PDT 24
Peak memory 206872 kb
Host smart-535ad437-a917-4e82-8f97-17c94ab26614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19989
4840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.199894840
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2692823001
Short name T1842
Test name
Test status
Simulation time 3336608286 ps
CPU time 3.79 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:07:02 PM PDT 24
Peak memory 206876 kb
Host smart-96ca4fed-1b93-4ec0-8d14-bc4723a0653c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26928
23001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2692823001
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.4199721376
Short name T2134
Test name
Test status
Simulation time 9727344298 ps
CPU time 64.45 seconds
Started Jul 15 07:06:53 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 207048 kb
Host smart-190576e5-9aec-45df-88c6-22bfb54ecb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41997
21376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.4199721376
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1807418338
Short name T2026
Test name
Test status
Simulation time 3328046505 ps
CPU time 89.97 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:08:27 PM PDT 24
Peak memory 207092 kb
Host smart-7d1c6d1e-47ff-498d-bce9-6384cfc79e3d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1807418338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1807418338
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1555517181
Short name T1774
Test name
Test status
Simulation time 333745593 ps
CPU time 0.93 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206804 kb
Host smart-912b5cc4-62ff-4145-bccd-c6a552e60ade
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1555517181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1555517181
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.846003154
Short name T1725
Test name
Test status
Simulation time 239903133 ps
CPU time 0.97 seconds
Started Jul 15 07:06:58 PM PDT 24
Finished Jul 15 07:07:01 PM PDT 24
Peak memory 206812 kb
Host smart-621d6aa4-c17b-4ba1-90f5-6133aefa3848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84600
3154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.846003154
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3758565177
Short name T572
Test name
Test status
Simulation time 4296371658 ps
CPU time 31.98 seconds
Started Jul 15 07:06:59 PM PDT 24
Finished Jul 15 07:07:33 PM PDT 24
Peak memory 207088 kb
Host smart-5e254aaf-65d8-4e05-8cd5-dd6145ab1721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37585
65177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3758565177
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3630469814
Short name T2144
Test name
Test status
Simulation time 4646890763 ps
CPU time 123.92 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:09:00 PM PDT 24
Peak memory 207020 kb
Host smart-35fc154e-25cf-4d9e-a086-73ae30b7fe61
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3630469814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3630469814
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.1159746908
Short name T1179
Test name
Test status
Simulation time 148287742 ps
CPU time 0.78 seconds
Started Jul 15 07:06:56 PM PDT 24
Finished Jul 15 07:07:00 PM PDT 24
Peak memory 206800 kb
Host smart-4d051816-9854-4aaa-b0af-bdbee4fdb71c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1159746908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.1159746908
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1516268574
Short name T1990
Test name
Test status
Simulation time 144470435 ps
CPU time 0.77 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:06:59 PM PDT 24
Peak memory 206812 kb
Host smart-315def75-6c94-4e40-b19d-d1f77598e1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15162
68574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1516268574
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.4113864054
Short name T2216
Test name
Test status
Simulation time 191572643 ps
CPU time 0.84 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 206756 kb
Host smart-d79370d9-0a79-4942-b7ed-1e347bbdb5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41138
64054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.4113864054
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1243235141
Short name T1716
Test name
Test status
Simulation time 148624515 ps
CPU time 0.79 seconds
Started Jul 15 07:06:58 PM PDT 24
Finished Jul 15 07:07:01 PM PDT 24
Peak memory 206812 kb
Host smart-90c403fa-672d-4485-9c14-14d49939b8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12432
35141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1243235141
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3342432625
Short name T621
Test name
Test status
Simulation time 168088853 ps
CPU time 0.93 seconds
Started Jul 15 07:06:56 PM PDT 24
Finished Jul 15 07:07:00 PM PDT 24
Peak memory 206816 kb
Host smart-286ed18d-7975-4d61-bc72-70198f4febc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33424
32625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3342432625
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3584299820
Short name T1812
Test name
Test status
Simulation time 167656105 ps
CPU time 0.79 seconds
Started Jul 15 07:06:56 PM PDT 24
Finished Jul 15 07:07:00 PM PDT 24
Peak memory 206824 kb
Host smart-20442181-c642-4fb4-a814-3daa110c05c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35842
99820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3584299820
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.536944735
Short name T2197
Test name
Test status
Simulation time 153048041 ps
CPU time 0.96 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206816 kb
Host smart-a71511c4-a00e-4148-af62-e9e36d5df08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53694
4735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.536944735
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3616285827
Short name T2033
Test name
Test status
Simulation time 194151559 ps
CPU time 0.89 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206828 kb
Host smart-f41649df-aaf7-4b9b-802b-69ca909f5dea
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3616285827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3616285827
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3232193364
Short name T1676
Test name
Test status
Simulation time 144533745 ps
CPU time 0.78 seconds
Started Jul 15 07:06:58 PM PDT 24
Finished Jul 15 07:07:00 PM PDT 24
Peak memory 206788 kb
Host smart-1520921f-20df-4c3a-97a2-7db83e16bd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32321
93364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3232193364
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3151551109
Short name T1286
Test name
Test status
Simulation time 46391988 ps
CPU time 0.67 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:06:59 PM PDT 24
Peak memory 206700 kb
Host smart-4fe0ee6d-1c75-43c3-934e-f337127e57b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31515
51109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3151551109
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.4003871946
Short name T1290
Test name
Test status
Simulation time 15561401719 ps
CPU time 33.55 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:07:32 PM PDT 24
Peak memory 207060 kb
Host smart-f81533ed-d50b-4630-aff4-5720bf7f3859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40038
71946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.4003871946
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3560694764
Short name T2088
Test name
Test status
Simulation time 184197968 ps
CPU time 0.81 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206836 kb
Host smart-560d57ee-1882-4662-8214-372559f3ec6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
94764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3560694764
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.2178009749
Short name T542
Test name
Test status
Simulation time 201426458 ps
CPU time 0.87 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 206828 kb
Host smart-315450ad-39d6-49cd-a06e-0c3b2736f1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21780
09749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2178009749
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3479677533
Short name T519
Test name
Test status
Simulation time 235640234 ps
CPU time 0.89 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206812 kb
Host smart-6f26f454-a215-4412-8cc5-74b82aa99ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34796
77533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3479677533
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.2916674237
Short name T1542
Test name
Test status
Simulation time 147968708 ps
CPU time 0.76 seconds
Started Jul 15 07:06:57 PM PDT 24
Finished Jul 15 07:07:00 PM PDT 24
Peak memory 206776 kb
Host smart-bc0600b9-5bad-41f8-9b1c-520ff9897b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29166
74237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.2916674237
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1353113153
Short name T1727
Test name
Test status
Simulation time 160532378 ps
CPU time 0.75 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206832 kb
Host smart-3e7b224f-9bf8-45aa-b19b-729361921182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
13153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1353113153
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1710792088
Short name T2667
Test name
Test status
Simulation time 151285734 ps
CPU time 0.78 seconds
Started Jul 15 07:06:55 PM PDT 24
Finished Jul 15 07:06:59 PM PDT 24
Peak memory 206816 kb
Host smart-108d25a9-b3b9-4bc4-a236-8d1ff37b98da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17107
92088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1710792088
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.4254667826
Short name T2002
Test name
Test status
Simulation time 249438654 ps
CPU time 0.93 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:06:58 PM PDT 24
Peak memory 206756 kb
Host smart-aad31178-b8ca-401a-ac0d-1aa167754a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42546
67826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.4254667826
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.433242276
Short name T954
Test name
Test status
Simulation time 4446340466 ps
CPU time 127.74 seconds
Started Jul 15 07:06:54 PM PDT 24
Finished Jul 15 07:09:05 PM PDT 24
Peak memory 207060 kb
Host smart-0bd778ee-8987-4182-9d2f-fe1c848b3b09
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=433242276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.433242276
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2889084508
Short name T2396
Test name
Test status
Simulation time 145773750 ps
CPU time 0.82 seconds
Started Jul 15 07:07:01 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 206816 kb
Host smart-2407a245-8f54-4fe5-8c0e-1c427b2c2c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28890
84508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2889084508
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3150004712
Short name T1250
Test name
Test status
Simulation time 163619997 ps
CPU time 0.77 seconds
Started Jul 15 07:07:04 PM PDT 24
Finished Jul 15 07:07:05 PM PDT 24
Peak memory 206784 kb
Host smart-5c7f29cb-455a-4e30-bc75-f3015e20e482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31500
04712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3150004712
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.2000865236
Short name T1386
Test name
Test status
Simulation time 671180311 ps
CPU time 1.58 seconds
Started Jul 15 07:07:00 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 206992 kb
Host smart-aa637114-00e3-4825-be5f-ce44ab4e331e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20008
65236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.2000865236
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.833056593
Short name T299
Test name
Test status
Simulation time 6716961277 ps
CPU time 192.01 seconds
Started Jul 15 07:07:00 PM PDT 24
Finished Jul 15 07:10:13 PM PDT 24
Peak memory 207056 kb
Host smart-3159820d-f984-491e-81b6-709e33b2f438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83305
6593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.833056593
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.671845866
Short name T1894
Test name
Test status
Simulation time 32995438 ps
CPU time 0.68 seconds
Started Jul 15 07:07:15 PM PDT 24
Finished Jul 15 07:07:17 PM PDT 24
Peak memory 206804 kb
Host smart-f16bc702-9999-4ec5-af99-de1afcdfbdd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=671845866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.671845866
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2722396124
Short name T612
Test name
Test status
Simulation time 3571854871 ps
CPU time 5.02 seconds
Started Jul 15 07:06:59 PM PDT 24
Finished Jul 15 07:07:06 PM PDT 24
Peak memory 206888 kb
Host smart-129569f2-b369-4965-9ee1-df4e71ffe147
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2722396124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2722396124
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3532184799
Short name T953
Test name
Test status
Simulation time 13387568475 ps
CPU time 14.59 seconds
Started Jul 15 07:06:59 PM PDT 24
Finished Jul 15 07:07:15 PM PDT 24
Peak memory 207096 kb
Host smart-acfcea36-0ee2-4426-b13e-4f0e9bc5d0cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3532184799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3532184799
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.792328490
Short name T2704
Test name
Test status
Simulation time 23454755912 ps
CPU time 23.18 seconds
Started Jul 15 07:06:59 PM PDT 24
Finished Jul 15 07:07:24 PM PDT 24
Peak memory 207068 kb
Host smart-e551c7be-eef7-4e92-80e2-709fbd6e786f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=792328490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.792328490
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.383285553
Short name T1489
Test name
Test status
Simulation time 155888020 ps
CPU time 0.81 seconds
Started Jul 15 07:07:00 PM PDT 24
Finished Jul 15 07:07:02 PM PDT 24
Peak memory 206792 kb
Host smart-b91794b1-4640-4a1b-b7fd-c0d121bc65b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38328
5553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.383285553
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.918960157
Short name T1949
Test name
Test status
Simulation time 217543503 ps
CPU time 0.82 seconds
Started Jul 15 07:07:03 PM PDT 24
Finished Jul 15 07:07:04 PM PDT 24
Peak memory 206824 kb
Host smart-efbee865-d9ef-48a7-b18a-a16e424f8d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91896
0157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.918960157
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.407578768
Short name T1108
Test name
Test status
Simulation time 203206457 ps
CPU time 0.86 seconds
Started Jul 15 07:06:59 PM PDT 24
Finished Jul 15 07:07:01 PM PDT 24
Peak memory 206812 kb
Host smart-bbb1712f-1546-4987-bdce-9cee4c5f4372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40757
8768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.407578768
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.3301518320
Short name T1685
Test name
Test status
Simulation time 1115204454 ps
CPU time 2.32 seconds
Started Jul 15 07:07:01 PM PDT 24
Finished Jul 15 07:07:05 PM PDT 24
Peak memory 206980 kb
Host smart-cfa27388-0adf-4e46-a47a-f3f543a1a93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015
18320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.3301518320
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.1665528933
Short name T155
Test name
Test status
Simulation time 20795360921 ps
CPU time 34.69 seconds
Started Jul 15 07:07:02 PM PDT 24
Finished Jul 15 07:07:38 PM PDT 24
Peak memory 207012 kb
Host smart-31b6930a-36a2-41ba-8396-28085e517d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16655
28933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.1665528933
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3347750385
Short name T2179
Test name
Test status
Simulation time 431353269 ps
CPU time 1.39 seconds
Started Jul 15 07:06:59 PM PDT 24
Finished Jul 15 07:07:02 PM PDT 24
Peak memory 206828 kb
Host smart-75a60504-6971-4495-98c5-9392662a3a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33477
50385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3347750385
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1698990691
Short name T2014
Test name
Test status
Simulation time 185488230 ps
CPU time 0.8 seconds
Started Jul 15 07:07:01 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 206808 kb
Host smart-8ae4078b-40c9-43b4-98fb-1d4c07dfa94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16989
90691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1698990691
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.411364299
Short name T1058
Test name
Test status
Simulation time 36349039 ps
CPU time 0.7 seconds
Started Jul 15 07:07:01 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 206808 kb
Host smart-eb7b16c4-0ac9-4a7b-aa05-da0c9aef09e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41136
4299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.411364299
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1978849635
Short name T2414
Test name
Test status
Simulation time 883909818 ps
CPU time 2.04 seconds
Started Jul 15 07:07:01 PM PDT 24
Finished Jul 15 07:07:04 PM PDT 24
Peak memory 206952 kb
Host smart-46305a66-8878-4b53-951d-1f39cf21b679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19788
49635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1978849635
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2041991206
Short name T608
Test name
Test status
Simulation time 266019941 ps
CPU time 1.59 seconds
Started Jul 15 07:06:59 PM PDT 24
Finished Jul 15 07:07:02 PM PDT 24
Peak memory 206956 kb
Host smart-7c306abf-6fee-475c-a65b-9f02bca1c623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20419
91206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2041991206
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2899427962
Short name T21
Test name
Test status
Simulation time 224067598 ps
CPU time 0.87 seconds
Started Jul 15 07:07:00 PM PDT 24
Finished Jul 15 07:07:02 PM PDT 24
Peak memory 206824 kb
Host smart-dd4c7580-81cd-47d7-914d-0d85f8c5e516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28994
27962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2899427962
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1317704268
Short name T1128
Test name
Test status
Simulation time 199432194 ps
CPU time 0.86 seconds
Started Jul 15 07:07:01 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 206796 kb
Host smart-a87fb3ac-113e-45c6-9347-f7cf53446512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13177
04268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1317704268
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1971231365
Short name T413
Test name
Test status
Simulation time 233674015 ps
CPU time 0.91 seconds
Started Jul 15 07:07:00 PM PDT 24
Finished Jul 15 07:07:03 PM PDT 24
Peak memory 206700 kb
Host smart-2d2de68f-7ec4-4669-aa2e-a4e218faca4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19712
31365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1971231365
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.106997171
Short name T1753
Test name
Test status
Simulation time 165823059 ps
CPU time 0.89 seconds
Started Jul 15 07:07:05 PM PDT 24
Finished Jul 15 07:07:07 PM PDT 24
Peak memory 206792 kb
Host smart-1d29b740-cfe5-4f17-97f0-79fd46d7f0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699
7171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.106997171
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1935288340
Short name T2446
Test name
Test status
Simulation time 23339766159 ps
CPU time 23.27 seconds
Started Jul 15 07:07:12 PM PDT 24
Finished Jul 15 07:07:36 PM PDT 24
Peak memory 206884 kb
Host smart-d7981808-295f-4bfd-858d-2801a1561ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19352
88340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1935288340
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.482524846
Short name T333
Test name
Test status
Simulation time 3302786644 ps
CPU time 3.8 seconds
Started Jul 15 07:07:07 PM PDT 24
Finished Jul 15 07:07:12 PM PDT 24
Peak memory 207048 kb
Host smart-9ee31800-ec17-4a90-b9e5-ef9a1b2e49aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48252
4846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.482524846
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.1679606872
Short name T2291
Test name
Test status
Simulation time 10438689612 ps
CPU time 75.46 seconds
Started Jul 15 07:07:14 PM PDT 24
Finished Jul 15 07:08:31 PM PDT 24
Peak memory 207072 kb
Host smart-23697851-69f7-4dce-8a3e-7c882152e1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
06872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.1679606872
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.200287888
Short name T1922
Test name
Test status
Simulation time 4255869633 ps
CPU time 115.84 seconds
Started Jul 15 07:07:07 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 207000 kb
Host smart-70fabedf-6305-4589-b756-fa1bb20f1b5f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=200287888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.200287888
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3643124153
Short name T1750
Test name
Test status
Simulation time 234067581 ps
CPU time 0.89 seconds
Started Jul 15 07:07:05 PM PDT 24
Finished Jul 15 07:07:07 PM PDT 24
Peak memory 206828 kb
Host smart-2e711ecf-ff21-40ef-b79f-b0b3aa0e5c2e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3643124153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3643124153
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2093565444
Short name T310
Test name
Test status
Simulation time 185685755 ps
CPU time 0.83 seconds
Started Jul 15 07:07:13 PM PDT 24
Finished Jul 15 07:07:15 PM PDT 24
Peak memory 206792 kb
Host smart-df4f68fe-453b-446a-b10a-9a9bab498ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20935
65444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2093565444
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2241720621
Short name T1411
Test name
Test status
Simulation time 5173470939 ps
CPU time 37.68 seconds
Started Jul 15 07:07:08 PM PDT 24
Finished Jul 15 07:07:47 PM PDT 24
Peak memory 207016 kb
Host smart-aa6d3977-74dd-46a9-b1a1-947fcf1f5a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22417
20621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2241720621
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1261764692
Short name T1478
Test name
Test status
Simulation time 4616198811 ps
CPU time 32.36 seconds
Started Jul 15 07:07:06 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 207060 kb
Host smart-e7eef6ae-b739-4879-bf37-0a15117a496e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1261764692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1261764692
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.1883116565
Short name T530
Test name
Test status
Simulation time 148592608 ps
CPU time 0.86 seconds
Started Jul 15 07:07:06 PM PDT 24
Finished Jul 15 07:07:08 PM PDT 24
Peak memory 206944 kb
Host smart-82cd1ff7-f643-4886-962a-e7245c379b16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1883116565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.1883116565
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1828944638
Short name T597
Test name
Test status
Simulation time 138253813 ps
CPU time 0.84 seconds
Started Jul 15 07:07:07 PM PDT 24
Finished Jul 15 07:07:10 PM PDT 24
Peak memory 206800 kb
Host smart-336d5f57-ea95-410d-86b9-525937e8d079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289
44638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1828944638
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1194742801
Short name T1809
Test name
Test status
Simulation time 156513349 ps
CPU time 0.8 seconds
Started Jul 15 07:07:10 PM PDT 24
Finished Jul 15 07:07:12 PM PDT 24
Peak memory 206796 kb
Host smart-f5d71893-0ffc-46e7-886d-5a90de0f8844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
42801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1194742801
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3150796902
Short name T1253
Test name
Test status
Simulation time 173238076 ps
CPU time 0.85 seconds
Started Jul 15 07:07:05 PM PDT 24
Finished Jul 15 07:07:06 PM PDT 24
Peak memory 206792 kb
Host smart-275cff61-6b36-49c7-b6f8-628a9d3d9aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507
96902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3150796902
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.841502886
Short name T284
Test name
Test status
Simulation time 157146427 ps
CPU time 0.8 seconds
Started Jul 15 07:07:08 PM PDT 24
Finished Jul 15 07:07:10 PM PDT 24
Peak memory 206792 kb
Host smart-8758ca0b-b7a1-4ff3-8542-7dae95acee81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84150
2886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.841502886
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1278482255
Short name T1886
Test name
Test status
Simulation time 149003981 ps
CPU time 0.74 seconds
Started Jul 15 07:07:12 PM PDT 24
Finished Jul 15 07:07:14 PM PDT 24
Peak memory 206832 kb
Host smart-4155a077-369f-41ac-a151-2f2ac6d2ca67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12784
82255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1278482255
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.653037257
Short name T1978
Test name
Test status
Simulation time 205108397 ps
CPU time 0.94 seconds
Started Jul 15 07:07:16 PM PDT 24
Finished Jul 15 07:07:20 PM PDT 24
Peak memory 206804 kb
Host smart-ba1d3d80-4e4d-43bb-aa71-60033d68d637
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=653037257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.653037257
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.126625378
Short name T2609
Test name
Test status
Simulation time 160644929 ps
CPU time 0.8 seconds
Started Jul 15 07:07:15 PM PDT 24
Finished Jul 15 07:07:18 PM PDT 24
Peak memory 206796 kb
Host smart-a5a66783-2100-4a4d-b7bd-dfe5ec543f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12662
5378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.126625378
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.456460749
Short name T37
Test name
Test status
Simulation time 65949147 ps
CPU time 0.69 seconds
Started Jul 15 07:07:12 PM PDT 24
Finished Jul 15 07:07:14 PM PDT 24
Peak memory 206804 kb
Host smart-8dbf62f0-0d24-47e2-865e-5b0c59cbe2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45646
0749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.456460749
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3239947285
Short name T916
Test name
Test status
Simulation time 10387791831 ps
CPU time 22.97 seconds
Started Jul 15 07:07:14 PM PDT 24
Finished Jul 15 07:07:39 PM PDT 24
Peak memory 207088 kb
Host smart-627a9fae-dff1-4cc7-83df-f42bacf20aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32399
47285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3239947285
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2742638150
Short name T362
Test name
Test status
Simulation time 158818172 ps
CPU time 0.77 seconds
Started Jul 15 07:07:16 PM PDT 24
Finished Jul 15 07:07:20 PM PDT 24
Peak memory 206784 kb
Host smart-e169abe9-0c6c-4614-848c-49d614a30110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27426
38150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2742638150
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1729705621
Short name T2299
Test name
Test status
Simulation time 171667861 ps
CPU time 0.91 seconds
Started Jul 15 07:07:13 PM PDT 24
Finished Jul 15 07:07:16 PM PDT 24
Peak memory 206792 kb
Host smart-a5bad59e-3fae-41e2-a554-2c09e61dca3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17297
05621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1729705621
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2914974552
Short name T372
Test name
Test status
Simulation time 184624676 ps
CPU time 0.84 seconds
Started Jul 15 07:07:13 PM PDT 24
Finished Jul 15 07:07:15 PM PDT 24
Peak memory 206816 kb
Host smart-d7f73b5c-a60d-4232-91a6-47e4e044eee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29149
74552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2914974552
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2522298488
Short name T300
Test name
Test status
Simulation time 156603034 ps
CPU time 0.84 seconds
Started Jul 15 07:07:14 PM PDT 24
Finished Jul 15 07:07:16 PM PDT 24
Peak memory 206820 kb
Host smart-b6005af8-f6a6-49a8-814e-a00f8c95cf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25222
98488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2522298488
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.2792857067
Short name T1116
Test name
Test status
Simulation time 195777673 ps
CPU time 0.81 seconds
Started Jul 15 07:07:16 PM PDT 24
Finished Jul 15 07:07:19 PM PDT 24
Peak memory 206748 kb
Host smart-c91e54e2-fa31-43d7-83af-27be4b1b3fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27928
57067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.2792857067
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3516273334
Short name T1958
Test name
Test status
Simulation time 181759645 ps
CPU time 0.81 seconds
Started Jul 15 07:07:12 PM PDT 24
Finished Jul 15 07:07:14 PM PDT 24
Peak memory 206824 kb
Host smart-46864e40-5865-4e66-a468-dab0aa62d381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35162
73334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3516273334
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1075984116
Short name T1195
Test name
Test status
Simulation time 168824097 ps
CPU time 0.78 seconds
Started Jul 15 07:07:14 PM PDT 24
Finished Jul 15 07:07:17 PM PDT 24
Peak memory 206768 kb
Host smart-fcaff352-95b5-4be1-98b0-5d9dfab0ca5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10759
84116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1075984116
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.825588770
Short name T1648
Test name
Test status
Simulation time 237064215 ps
CPU time 0.99 seconds
Started Jul 15 07:07:16 PM PDT 24
Finished Jul 15 07:07:20 PM PDT 24
Peak memory 206796 kb
Host smart-8962f706-327b-4dde-adca-a72e5f46a23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82558
8770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.825588770
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3611894723
Short name T480
Test name
Test status
Simulation time 3376954173 ps
CPU time 91.79 seconds
Started Jul 15 07:07:14 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 206960 kb
Host smart-f23a0ea0-86c5-4e70-9219-255f6c33a79b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3611894723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3611894723
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3178139136
Short name T2159
Test name
Test status
Simulation time 157906230 ps
CPU time 0.79 seconds
Started Jul 15 07:07:14 PM PDT 24
Finished Jul 15 07:07:17 PM PDT 24
Peak memory 206828 kb
Host smart-32f35286-384d-4e84-9b79-80e613f3ba39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31781
39136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3178139136
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2278120461
Short name T2169
Test name
Test status
Simulation time 224382188 ps
CPU time 0.83 seconds
Started Jul 15 07:07:14 PM PDT 24
Finished Jul 15 07:07:17 PM PDT 24
Peak memory 206784 kb
Host smart-b6fcb160-c03e-4edb-89b5-6b681fc5160c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
20461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2278120461
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.2308874288
Short name T1962
Test name
Test status
Simulation time 1237245494 ps
CPU time 2.49 seconds
Started Jul 15 07:07:12 PM PDT 24
Finished Jul 15 07:07:16 PM PDT 24
Peak memory 206984 kb
Host smart-fa2003ce-c7db-4a11-aa8f-857c17de2066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23088
74288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2308874288
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2742249617
Short name T1724
Test name
Test status
Simulation time 5397986724 ps
CPU time 39.46 seconds
Started Jul 15 07:07:13 PM PDT 24
Finished Jul 15 07:07:54 PM PDT 24
Peak memory 207028 kb
Host smart-f160031f-0407-4fb9-b8e8-5ae07ec996c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
49617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2742249617
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2468096367
Short name T975
Test name
Test status
Simulation time 39030175 ps
CPU time 0.69 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:32 PM PDT 24
Peak memory 206872 kb
Host smart-8ce838b2-dcf1-49fc-b435-5af782ace1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2468096367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2468096367
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1619527677
Short name T812
Test name
Test status
Simulation time 4353184498 ps
CPU time 4.96 seconds
Started Jul 15 07:07:12 PM PDT 24
Finished Jul 15 07:07:18 PM PDT 24
Peak memory 207068 kb
Host smart-6627a5f0-4750-4fee-ba02-a44f7f0125d7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1619527677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1619527677
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.902097570
Short name T543
Test name
Test status
Simulation time 13368178507 ps
CPU time 12.18 seconds
Started Jul 15 07:07:14 PM PDT 24
Finished Jul 15 07:07:28 PM PDT 24
Peak memory 206872 kb
Host smart-e4926969-1dd9-40a2-99df-2e24be7f3d8e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=902097570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.902097570
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2664472449
Short name T1853
Test name
Test status
Simulation time 23355819437 ps
CPU time 22.94 seconds
Started Jul 15 07:07:21 PM PDT 24
Finished Jul 15 07:07:47 PM PDT 24
Peak memory 206868 kb
Host smart-a6621cdd-d2c6-44da-a041-1dcd66d88fc8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2664472449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2664472449
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.4059444706
Short name T2007
Test name
Test status
Simulation time 156553970 ps
CPU time 0.88 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:29 PM PDT 24
Peak memory 206820 kb
Host smart-6c6d4bd7-434f-4749-a36e-006572059d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
44706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.4059444706
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3937276434
Short name T1789
Test name
Test status
Simulation time 148001911 ps
CPU time 0.78 seconds
Started Jul 15 07:07:21 PM PDT 24
Finished Jul 15 07:07:24 PM PDT 24
Peak memory 206784 kb
Host smart-1d7d8876-3a18-41dd-9766-d2a8b97cc301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39372
76434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3937276434
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2395258047
Short name T1182
Test name
Test status
Simulation time 484237514 ps
CPU time 1.49 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:32 PM PDT 24
Peak memory 206952 kb
Host smart-8b6316ac-0ee2-4f8f-bd8a-849247b42c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952
58047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2395258047
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1928539861
Short name T2080
Test name
Test status
Simulation time 344737355 ps
CPU time 1.03 seconds
Started Jul 15 07:07:27 PM PDT 24
Finished Jul 15 07:07:38 PM PDT 24
Peak memory 206796 kb
Host smart-2925ee85-a680-408f-b2a0-f6e534102f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19285
39861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1928539861
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2919576233
Short name T2659
Test name
Test status
Simulation time 18650826133 ps
CPU time 36.19 seconds
Started Jul 15 07:07:22 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 207088 kb
Host smart-189a7de9-89fb-4bbd-b1fc-4e03ddcea72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29195
76233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2919576233
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.366167638
Short name T1932
Test name
Test status
Simulation time 396737742 ps
CPU time 1.18 seconds
Started Jul 15 07:07:27 PM PDT 24
Finished Jul 15 07:07:37 PM PDT 24
Peak memory 206800 kb
Host smart-f05509fe-5998-4b0f-8e11-201aeba26a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36616
7638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.366167638
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.510247391
Short name T1044
Test name
Test status
Simulation time 145025366 ps
CPU time 0.76 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:32 PM PDT 24
Peak memory 206788 kb
Host smart-f994619a-2680-4d83-9775-8e77c8e5fe1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51024
7391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.510247391
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.4160673785
Short name T739
Test name
Test status
Simulation time 68028047 ps
CPU time 0.75 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:30 PM PDT 24
Peak memory 206828 kb
Host smart-b1eba32c-e442-416f-83bc-d65c03b278be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41606
73785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.4160673785
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.1800287134
Short name T1937
Test name
Test status
Simulation time 956131624 ps
CPU time 1.97 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:34 PM PDT 24
Peak memory 206992 kb
Host smart-1c318474-770f-4ee4-9208-509ea0399727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
87134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.1800287134
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3426109822
Short name T1662
Test name
Test status
Simulation time 187569921 ps
CPU time 1.15 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:33 PM PDT 24
Peak memory 207044 kb
Host smart-53740c91-c801-4908-a784-7d7c70872c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34261
09822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3426109822
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2781066770
Short name T565
Test name
Test status
Simulation time 232198788 ps
CPU time 0.86 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:31 PM PDT 24
Peak memory 206840 kb
Host smart-2f729a12-5152-44f9-b840-8d75cf8753a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27810
66770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2781066770
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1645999380
Short name T1594
Test name
Test status
Simulation time 154270065 ps
CPU time 0.8 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:30 PM PDT 24
Peak memory 206796 kb
Host smart-aa9be387-298c-4704-b2d1-3b7a593cdf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16459
99380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1645999380
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2176228082
Short name T1755
Test name
Test status
Simulation time 174869870 ps
CPU time 0.83 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:31 PM PDT 24
Peak memory 206800 kb
Host smart-d77220bc-8d7a-439e-89fa-51a0d328dc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762
28082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2176228082
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.3614457759
Short name T1312
Test name
Test status
Simulation time 11510029746 ps
CPU time 99.95 seconds
Started Jul 15 07:07:21 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 207004 kb
Host smart-83b17f2a-c906-4cfa-8170-6a9e9e262643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
57759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3614457759
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.234748707
Short name T1645
Test name
Test status
Simulation time 220217800 ps
CPU time 0.85 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:38 PM PDT 24
Peak memory 206824 kb
Host smart-78187205-e2c5-4df0-8c5d-a8427757f18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23474
8707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.234748707
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.165180367
Short name T2286
Test name
Test status
Simulation time 23293824992 ps
CPU time 21.3 seconds
Started Jul 15 07:07:21 PM PDT 24
Finished Jul 15 07:07:45 PM PDT 24
Peak memory 206844 kb
Host smart-3adae1b0-7b7b-4135-9c1f-f40f2b9e34fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16518
0367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.165180367
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2654924211
Short name T1226
Test name
Test status
Simulation time 3351381935 ps
CPU time 3.86 seconds
Started Jul 15 07:07:25 PM PDT 24
Finished Jul 15 07:07:38 PM PDT 24
Peak memory 206888 kb
Host smart-56ff1ecc-8508-4bf4-85b6-b29cad9bd877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26549
24211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2654924211
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3849982531
Short name T1825
Test name
Test status
Simulation time 11582297331 ps
CPU time 311.19 seconds
Started Jul 15 07:07:22 PM PDT 24
Finished Jul 15 07:12:40 PM PDT 24
Peak memory 207108 kb
Host smart-87f51b8d-744f-4215-9c5c-b76364583b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38499
82531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3849982531
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1306440622
Short name T1622
Test name
Test status
Simulation time 4693184863 ps
CPU time 44.16 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:08:16 PM PDT 24
Peak memory 207076 kb
Host smart-867cc70f-a45b-4428-b5de-b3bbe25b6e46
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1306440622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1306440622
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1535443723
Short name T2460
Test name
Test status
Simulation time 251115686 ps
CPU time 0.92 seconds
Started Jul 15 07:07:21 PM PDT 24
Finished Jul 15 07:07:25 PM PDT 24
Peak memory 206828 kb
Host smart-5e985732-7aec-4d39-aca4-a2c0d90f5429
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1535443723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1535443723
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2156258067
Short name T2295
Test name
Test status
Simulation time 193499726 ps
CPU time 0.85 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:30 PM PDT 24
Peak memory 206800 kb
Host smart-441e9f83-363f-4c14-8ebe-0794ba553ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21562
58067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2156258067
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.4021382285
Short name T1102
Test name
Test status
Simulation time 5867977189 ps
CPU time 159.59 seconds
Started Jul 15 07:07:20 PM PDT 24
Finished Jul 15 07:10:00 PM PDT 24
Peak memory 207180 kb
Host smart-48d4d8a3-3f2d-4df7-a159-b996af971410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40213
82285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.4021382285
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3952452061
Short name T1560
Test name
Test status
Simulation time 7279456534 ps
CPU time 50.76 seconds
Started Jul 15 07:07:25 PM PDT 24
Finished Jul 15 07:08:25 PM PDT 24
Peak memory 207028 kb
Host smart-f9557121-e378-4148-a1e3-417ca330e32b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3952452061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3952452061
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.2086982849
Short name T2690
Test name
Test status
Simulation time 204177013 ps
CPU time 0.85 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:38 PM PDT 24
Peak memory 206812 kb
Host smart-31e785c7-73d6-49a7-a4d9-508dc4eab655
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2086982849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.2086982849
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3413945828
Short name T2272
Test name
Test status
Simulation time 150563807 ps
CPU time 0.79 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:33 PM PDT 24
Peak memory 206792 kb
Host smart-e643ea56-90ca-4694-b2aa-89fe43c54c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34139
45828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3413945828
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2906110897
Short name T1910
Test name
Test status
Simulation time 214549142 ps
CPU time 0.92 seconds
Started Jul 15 07:07:26 PM PDT 24
Finished Jul 15 07:07:36 PM PDT 24
Peak memory 206812 kb
Host smart-e0c5dbb7-5708-498e-ac9c-527ff2613248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29061
10897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2906110897
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.356329574
Short name T2603
Test name
Test status
Simulation time 196023208 ps
CPU time 0.9 seconds
Started Jul 15 07:07:22 PM PDT 24
Finished Jul 15 07:07:28 PM PDT 24
Peak memory 206792 kb
Host smart-dfdf06d9-cf49-4b33-bd00-6c0c774f46e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35632
9574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.356329574
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2655593185
Short name T2722
Test name
Test status
Simulation time 184897652 ps
CPU time 0.8 seconds
Started Jul 15 07:07:19 PM PDT 24
Finished Jul 15 07:07:21 PM PDT 24
Peak memory 206808 kb
Host smart-cb8b80d4-d39d-4849-b797-4a90332e7aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26555
93185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2655593185
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3946992222
Short name T1636
Test name
Test status
Simulation time 238847912 ps
CPU time 0.84 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:33 PM PDT 24
Peak memory 206228 kb
Host smart-b724b890-87e4-4fc3-a6a1-dd6052af8cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39469
92222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3946992222
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3175427920
Short name T2743
Test name
Test status
Simulation time 149309193 ps
CPU time 0.79 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:33 PM PDT 24
Peak memory 206840 kb
Host smart-8407d6fe-80af-49b1-89c3-27898673b715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31754
27920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3175427920
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.3539401730
Short name T2182
Test name
Test status
Simulation time 266213665 ps
CPU time 0.93 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:31 PM PDT 24
Peak memory 206808 kb
Host smart-dd874a8a-7f9e-41f0-824b-0d3fcd615b05
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3539401730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.3539401730
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.4267915634
Short name T2402
Test name
Test status
Simulation time 150643863 ps
CPU time 0.76 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:31 PM PDT 24
Peak memory 206764 kb
Host smart-3e8cb46a-b41a-420a-8208-dc3bfbdd9461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679
15634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.4267915634
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2324843080
Short name T2259
Test name
Test status
Simulation time 31598709 ps
CPU time 0.61 seconds
Started Jul 15 07:07:20 PM PDT 24
Finished Jul 15 07:07:21 PM PDT 24
Peak memory 206808 kb
Host smart-cccc76bf-99f6-4f88-8b19-20fff5d678fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23248
43080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2324843080
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2569061188
Short name T1690
Test name
Test status
Simulation time 20514770858 ps
CPU time 49.96 seconds
Started Jul 15 07:07:22 PM PDT 24
Finished Jul 15 07:08:18 PM PDT 24
Peak memory 207132 kb
Host smart-1e2816d2-4dd8-4cc1-b714-93a60ea2b36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
61188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2569061188
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.4282981438
Short name T1262
Test name
Test status
Simulation time 164145434 ps
CPU time 0.83 seconds
Started Jul 15 07:07:22 PM PDT 24
Finished Jul 15 07:07:25 PM PDT 24
Peak memory 206792 kb
Host smart-3ba3bc73-8551-463e-bb2c-0310637b5666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42829
81438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.4282981438
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.4015060966
Short name T2058
Test name
Test status
Simulation time 299969791 ps
CPU time 0.98 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:31 PM PDT 24
Peak memory 206816 kb
Host smart-842a59b8-34ef-4e3b-bc49-80d1045bce0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40150
60966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.4015060966
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3667629083
Short name T2693
Test name
Test status
Simulation time 222129392 ps
CPU time 0.9 seconds
Started Jul 15 07:07:26 PM PDT 24
Finished Jul 15 07:07:36 PM PDT 24
Peak memory 206760 kb
Host smart-0b35e444-7384-4833-a557-9e04e1428814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
29083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3667629083
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4259617846
Short name T2174
Test name
Test status
Simulation time 182183740 ps
CPU time 0.82 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:32 PM PDT 24
Peak memory 206580 kb
Host smart-40cc173b-4b65-4a43-b3dc-e37fc7a3df34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42596
17846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4259617846
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2968329866
Short name T1009
Test name
Test status
Simulation time 154110909 ps
CPU time 0.82 seconds
Started Jul 15 07:07:20 PM PDT 24
Finished Jul 15 07:07:22 PM PDT 24
Peak memory 206808 kb
Host smart-efe54087-5e34-4fb9-9d9e-606857cf1174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29683
29866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2968329866
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3254755916
Short name T1304
Test name
Test status
Simulation time 208748527 ps
CPU time 0.78 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:07:41 PM PDT 24
Peak memory 206788 kb
Host smart-bc7fc908-f26d-4140-8b2a-e438c39c368b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32547
55916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3254755916
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2809671477
Short name T603
Test name
Test status
Simulation time 177089281 ps
CPU time 0.82 seconds
Started Jul 15 07:07:21 PM PDT 24
Finished Jul 15 07:07:23 PM PDT 24
Peak memory 206792 kb
Host smart-c2bc1bff-047a-45f8-9aca-9126f83a9b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28096
71477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2809671477
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.148573869
Short name T145
Test name
Test status
Simulation time 198983119 ps
CPU time 0.89 seconds
Started Jul 15 07:07:25 PM PDT 24
Finished Jul 15 07:07:34 PM PDT 24
Peak memory 206764 kb
Host smart-aebb6205-c584-4376-bb4e-bd3b4056934a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14857
3869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.148573869
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.4185415335
Short name T1158
Test name
Test status
Simulation time 3757688755 ps
CPU time 106.65 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:09:17 PM PDT 24
Peak memory 206992 kb
Host smart-b5271b26-9f32-4838-8e08-190c651c1969
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4185415335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.4185415335
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3938360535
Short name T329
Test name
Test status
Simulation time 187948335 ps
CPU time 0.8 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:32 PM PDT 24
Peak memory 206612 kb
Host smart-a8eaa184-0941-4603-a54f-b508c343e1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39383
60535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3938360535
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.195840635
Short name T1447
Test name
Test status
Simulation time 154081225 ps
CPU time 0.76 seconds
Started Jul 15 07:07:21 PM PDT 24
Finished Jul 15 07:07:24 PM PDT 24
Peak memory 206776 kb
Host smart-1f5b4138-276d-4598-980e-3e9dc053ce8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19584
0635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.195840635
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.1717787136
Short name T2631
Test name
Test status
Simulation time 683407415 ps
CPU time 1.67 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:30 PM PDT 24
Peak memory 206904 kb
Host smart-c7a8f316-0bb8-4cdd-858c-4bf5866bd3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17177
87136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1717787136
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2614411411
Short name T717
Test name
Test status
Simulation time 5151604888 ps
CPU time 141.12 seconds
Started Jul 15 07:07:22 PM PDT 24
Finished Jul 15 07:09:49 PM PDT 24
Peak memory 207036 kb
Host smart-76126c6a-203e-4125-aa24-bcbeb30bb96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26144
11411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2614411411
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2412651141
Short name T782
Test name
Test status
Simulation time 32175987 ps
CPU time 0.72 seconds
Started Jul 15 07:07:33 PM PDT 24
Finished Jul 15 07:07:44 PM PDT 24
Peak memory 206804 kb
Host smart-dcd59973-34dd-43e5-a0ca-90c649c71ed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2412651141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2412651141
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.4286015041
Short name T2745
Test name
Test status
Simulation time 3642058408 ps
CPU time 4.01 seconds
Started Jul 15 07:07:25 PM PDT 24
Finished Jul 15 07:07:37 PM PDT 24
Peak memory 207032 kb
Host smart-ebc15104-5ddc-4011-983f-28ee423b3e2c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4286015041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.4286015041
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.3067336740
Short name T11
Test name
Test status
Simulation time 13321959854 ps
CPU time 14.53 seconds
Started Jul 15 07:07:22 PM PDT 24
Finished Jul 15 07:07:42 PM PDT 24
Peak memory 206864 kb
Host smart-7f4ac456-5ccc-4d09-917e-7eba45082cf7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3067336740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.3067336740
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3375184347
Short name T1670
Test name
Test status
Simulation time 23449278811 ps
CPU time 22.61 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 207112 kb
Host smart-85b3b41c-4314-442f-bd58-5baed5d3c7d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3375184347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.3375184347
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1940105104
Short name T1739
Test name
Test status
Simulation time 150498335 ps
CPU time 0.77 seconds
Started Jul 15 07:07:22 PM PDT 24
Finished Jul 15 07:07:29 PM PDT 24
Peak memory 206824 kb
Host smart-2c5fd4e8-2e84-45fa-a7b8-b5d6603e39fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19401
05104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1940105104
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.514472768
Short name T1205
Test name
Test status
Simulation time 179577621 ps
CPU time 0.82 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:34 PM PDT 24
Peak memory 206816 kb
Host smart-8e56f81f-4987-42ef-95aa-f2b50da357e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51447
2768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.514472768
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.737147100
Short name T1838
Test name
Test status
Simulation time 540279602 ps
CPU time 1.44 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:31 PM PDT 24
Peak memory 206944 kb
Host smart-cf3bcf45-5aa8-4f56-9ecb-ebb722f3097e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73714
7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.737147100
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_device_address.948242022
Short name T1335
Test name
Test status
Simulation time 21577751676 ps
CPU time 39.24 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 206536 kb
Host smart-5796c67e-dc12-465d-abeb-0d356218bb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94824
2022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.948242022
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.294393622
Short name T927
Test name
Test status
Simulation time 341120442 ps
CPU time 1.07 seconds
Started Jul 15 07:07:25 PM PDT 24
Finished Jul 15 07:07:35 PM PDT 24
Peak memory 206828 kb
Host smart-b7d7402a-ec62-40af-a157-bb528fce5d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29439
3622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.294393622
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.43995268
Short name T1266
Test name
Test status
Simulation time 147783372 ps
CPU time 0.79 seconds
Started Jul 15 07:07:24 PM PDT 24
Finished Jul 15 07:07:32 PM PDT 24
Peak memory 206784 kb
Host smart-646ff941-067f-4edd-9f7e-565818987d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43995
268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.43995268
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1733870326
Short name T2514
Test name
Test status
Simulation time 43955210 ps
CPU time 0.68 seconds
Started Jul 15 07:07:23 PM PDT 24
Finished Jul 15 07:07:30 PM PDT 24
Peak memory 206792 kb
Host smart-5f872b48-eb77-4035-a130-b113e12779ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17338
70326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1733870326
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.792621519
Short name T1718
Test name
Test status
Simulation time 939523024 ps
CPU time 2.24 seconds
Started Jul 15 07:07:28 PM PDT 24
Finished Jul 15 07:07:41 PM PDT 24
Peak memory 206940 kb
Host smart-b027271a-1760-4d5f-8d18-7a787d1e93fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79262
1519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.792621519
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.4039870496
Short name T2621
Test name
Test status
Simulation time 357960156 ps
CPU time 2.23 seconds
Started Jul 15 07:07:28 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 206932 kb
Host smart-bc28a22b-920f-49af-bcf3-64a28600f7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40398
70496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.4039870496
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.24232272
Short name T493
Test name
Test status
Simulation time 194580977 ps
CPU time 0.86 seconds
Started Jul 15 07:07:32 PM PDT 24
Finished Jul 15 07:07:43 PM PDT 24
Peak memory 206792 kb
Host smart-f82c889b-c36a-4c62-822d-942740d7cf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24232
272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.24232272
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2034321260
Short name T870
Test name
Test status
Simulation time 138675931 ps
CPU time 0.74 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 206796 kb
Host smart-8f857861-40da-40cf-81b9-855ba3b77695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20343
21260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2034321260
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1823980987
Short name T1832
Test name
Test status
Simulation time 169669993 ps
CPU time 0.84 seconds
Started Jul 15 07:07:28 PM PDT 24
Finished Jul 15 07:07:44 PM PDT 24
Peak memory 206848 kb
Host smart-2e431435-76c6-460e-bc08-30cd79a43d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18239
80987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1823980987
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.185131008
Short name T2211
Test name
Test status
Simulation time 5375891854 ps
CPU time 36.81 seconds
Started Jul 15 07:07:43 PM PDT 24
Finished Jul 15 07:08:33 PM PDT 24
Peak memory 207104 kb
Host smart-1f814f91-d564-43eb-8bf5-deafd06ba6bb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=185131008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.185131008
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3556395005
Short name T709
Test name
Test status
Simulation time 233140010 ps
CPU time 0.87 seconds
Started Jul 15 07:07:29 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 206792 kb
Host smart-4cbcc541-fe10-428b-a0af-f8fefa7f4667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35563
95005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3556395005
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.1220784408
Short name T1811
Test name
Test status
Simulation time 23299349335 ps
CPU time 23.31 seconds
Started Jul 15 07:07:28 PM PDT 24
Finished Jul 15 07:08:02 PM PDT 24
Peak memory 206876 kb
Host smart-626dd2af-78d2-4acc-a3fc-77838d2ba299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12207
84408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.1220784408
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.3731375569
Short name T1222
Test name
Test status
Simulation time 3355461171 ps
CPU time 4 seconds
Started Jul 15 07:07:31 PM PDT 24
Finished Jul 15 07:07:45 PM PDT 24
Peak memory 206856 kb
Host smart-7620b6b7-cbec-4933-8713-8ba1242c95a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37313
75569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.3731375569
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2382613249
Short name T892
Test name
Test status
Simulation time 9248059983 ps
CPU time 86.67 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:09:06 PM PDT 24
Peak memory 207080 kb
Host smart-36d5f71a-b25f-45a1-9e0c-64acb4148c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23826
13249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2382613249
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.4176995061
Short name T1036
Test name
Test status
Simulation time 4821342625 ps
CPU time 134.34 seconds
Started Jul 15 07:07:28 PM PDT 24
Finished Jul 15 07:09:53 PM PDT 24
Peak memory 206992 kb
Host smart-4bdd2f26-fdac-4c7e-a414-aad2abede26b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4176995061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.4176995061
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.3879321272
Short name T460
Test name
Test status
Simulation time 246847182 ps
CPU time 0.93 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 206800 kb
Host smart-43b9988f-bfa8-46ed-8658-86ab951b22d1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3879321272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.3879321272
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1011716650
Short name T554
Test name
Test status
Simulation time 195211592 ps
CPU time 0.92 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:07:41 PM PDT 24
Peak memory 206812 kb
Host smart-ef8abfed-bf39-42c3-a81c-db636f4d6abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117
16650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1011716650
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.4057015445
Short name T2437
Test name
Test status
Simulation time 4071994243 ps
CPU time 111.26 seconds
Started Jul 15 07:07:28 PM PDT 24
Finished Jul 15 07:09:29 PM PDT 24
Peak memory 206984 kb
Host smart-48b312e8-0435-400b-9ddb-02fde6c6f8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40570
15445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.4057015445
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1988570602
Short name T1033
Test name
Test status
Simulation time 7050930505 ps
CPU time 188.32 seconds
Started Jul 15 07:07:36 PM PDT 24
Finished Jul 15 07:10:56 PM PDT 24
Peak memory 207036 kb
Host smart-7a33d7b0-2b37-4007-b7d8-3bb5792a2e85
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1988570602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1988570602
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3573044341
Short name T418
Test name
Test status
Simulation time 155209248 ps
CPU time 0.79 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 206804 kb
Host smart-48e065ee-11e1-4ee7-9c38-34da4dc00c05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3573044341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3573044341
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1008747398
Short name T2021
Test name
Test status
Simulation time 150299620 ps
CPU time 0.77 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 206776 kb
Host smart-5137517d-7b4f-4b2b-82b2-fc2658711894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
47398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1008747398
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.186586334
Short name T989
Test name
Test status
Simulation time 261272536 ps
CPU time 0.96 seconds
Started Jul 15 07:07:32 PM PDT 24
Finished Jul 15 07:07:44 PM PDT 24
Peak memory 206792 kb
Host smart-f5bb9edc-5382-44bf-89a4-4e9437569a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18658
6334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.186586334
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2316313684
Short name T1797
Test name
Test status
Simulation time 206460737 ps
CPU time 0.94 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 206792 kb
Host smart-7546c607-deb5-4517-bb77-0447ab790b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
13684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2316313684
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.4210990447
Short name T481
Test name
Test status
Simulation time 189975463 ps
CPU time 0.82 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:07:52 PM PDT 24
Peak memory 206796 kb
Host smart-5a94d698-bd52-456c-ad68-f7b562c01a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
90447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.4210990447
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2423178016
Short name T1987
Test name
Test status
Simulation time 203011037 ps
CPU time 0.86 seconds
Started Jul 15 07:07:32 PM PDT 24
Finished Jul 15 07:07:44 PM PDT 24
Peak memory 206812 kb
Host smart-e7e92d5e-b023-48c9-9435-6c19c1b50517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24231
78016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2423178016
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.429818395
Short name T1098
Test name
Test status
Simulation time 158815105 ps
CPU time 0.81 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206768 kb
Host smart-70a27005-b6b9-4fcf-86a5-0d90d7ac5b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42981
8395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.429818395
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.1197555799
Short name T863
Test name
Test status
Simulation time 238622547 ps
CPU time 0.97 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:07:52 PM PDT 24
Peak memory 206792 kb
Host smart-242cc4b0-0402-4b00-9924-f7784ddcfe5c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1197555799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1197555799
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2722331318
Short name T2566
Test name
Test status
Simulation time 155804022 ps
CPU time 0.77 seconds
Started Jul 15 07:07:45 PM PDT 24
Finished Jul 15 07:07:58 PM PDT 24
Peak memory 206836 kb
Host smart-0ccad56b-6d61-45e4-bc70-b5da992b5e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27223
31318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2722331318
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3755862230
Short name T712
Test name
Test status
Simulation time 73418167 ps
CPU time 0.67 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:07:41 PM PDT 24
Peak memory 206700 kb
Host smart-c503fce7-bec7-4b0b-9b3b-1dc528fba8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37558
62230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3755862230
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.950161600
Short name T2726
Test name
Test status
Simulation time 22423249005 ps
CPU time 54.63 seconds
Started Jul 15 07:07:31 PM PDT 24
Finished Jul 15 07:08:37 PM PDT 24
Peak memory 207060 kb
Host smart-7f04eba5-2b48-442a-bab9-6019d236bf1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95016
1600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.950161600
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3608280068
Short name T433
Test name
Test status
Simulation time 170929211 ps
CPU time 0.78 seconds
Started Jul 15 07:07:33 PM PDT 24
Finished Jul 15 07:07:44 PM PDT 24
Peak memory 206828 kb
Host smart-6bca5a32-5ebb-4232-a020-18bb197c4ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36082
80068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3608280068
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3621360738
Short name T409
Test name
Test status
Simulation time 233800595 ps
CPU time 0.96 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 206824 kb
Host smart-08a34e87-0993-460e-90a5-8df522bba9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36213
60738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3621360738
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.789137149
Short name T998
Test name
Test status
Simulation time 234778308 ps
CPU time 0.9 seconds
Started Jul 15 07:07:46 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206824 kb
Host smart-de753b04-db01-43bf-a5f9-71663d9f965f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78913
7149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.789137149
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.4104382483
Short name T450
Test name
Test status
Simulation time 183215392 ps
CPU time 0.86 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:07:41 PM PDT 24
Peak memory 206828 kb
Host smart-931346cb-f009-4f2c-9efa-fdf675db8d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41043
82483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.4104382483
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1091049345
Short name T2570
Test name
Test status
Simulation time 139731305 ps
CPU time 0.8 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 206820 kb
Host smart-b1671356-5953-4b16-a71b-57358fd2c8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10910
49345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1091049345
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1880046989
Short name T1572
Test name
Test status
Simulation time 149222095 ps
CPU time 0.75 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 206792 kb
Host smart-c7594a2d-706b-47e4-ab38-111295e0c4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18800
46989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1880046989
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2533490990
Short name T1961
Test name
Test status
Simulation time 148544334 ps
CPU time 0.81 seconds
Started Jul 15 07:07:31 PM PDT 24
Finished Jul 15 07:07:43 PM PDT 24
Peak memory 206812 kb
Host smart-dca48e12-16b9-493f-bdc1-f555fa10a39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
90990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2533490990
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3149803739
Short name T1324
Test name
Test status
Simulation time 235569732 ps
CPU time 0.97 seconds
Started Jul 15 07:07:55 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206784 kb
Host smart-aae8724e-78dc-4579-8eff-5f7780a9347f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31498
03739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3149803739
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2996886133
Short name T874
Test name
Test status
Simulation time 4856600287 ps
CPU time 36.77 seconds
Started Jul 15 07:07:31 PM PDT 24
Finished Jul 15 07:08:19 PM PDT 24
Peak memory 207052 kb
Host smart-6584f6e0-8dbe-467d-b88b-0fa59f309471
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2996886133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2996886133
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3723870608
Short name T1461
Test name
Test status
Simulation time 180674886 ps
CPU time 0.82 seconds
Started Jul 15 07:07:52 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 206800 kb
Host smart-ed3545ff-e023-4bfb-9588-0c8d7c909516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
70608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3723870608
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.4070656199
Short name T1174
Test name
Test status
Simulation time 176219972 ps
CPU time 0.85 seconds
Started Jul 15 07:07:37 PM PDT 24
Finished Jul 15 07:07:50 PM PDT 24
Peak memory 206784 kb
Host smart-4e6c4631-a30a-46ce-8b8c-e97cced67862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40706
56199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.4070656199
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.1661192934
Short name T1247
Test name
Test status
Simulation time 688600326 ps
CPU time 1.68 seconds
Started Jul 15 07:07:33 PM PDT 24
Finished Jul 15 07:07:46 PM PDT 24
Peak memory 206968 kb
Host smart-00a0a991-7cc2-48b7-9e8d-6a457bf76d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16611
92934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.1661192934
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1570680854
Short name T2288
Test name
Test status
Simulation time 3567533998 ps
CPU time 101.5 seconds
Started Jul 15 07:07:56 PM PDT 24
Finished Jul 15 07:09:45 PM PDT 24
Peak memory 207008 kb
Host smart-eb2e54f4-681d-4385-8a3c-b25fcb9b4f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15706
80854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1570680854
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.4039816149
Short name T1073
Test name
Test status
Simulation time 109438032 ps
CPU time 0.74 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 206856 kb
Host smart-fb8add2a-2eac-4882-8040-e28bd4cbf75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4039816149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.4039816149
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1905119032
Short name T959
Test name
Test status
Simulation time 4217407998 ps
CPU time 4.62 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 207080 kb
Host smart-d73685cc-c432-4793-98b6-67477046b5c4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1905119032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1905119032
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3218580393
Short name T1495
Test name
Test status
Simulation time 13498338458 ps
CPU time 15.78 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 207072 kb
Host smart-f7fd8938-6c40-4019-852a-9631e0f94032
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3218580393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3218580393
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3594681203
Short name T2501
Test name
Test status
Simulation time 23416319950 ps
CPU time 22.28 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 207012 kb
Host smart-92b7860e-c35f-45c5-9a8b-5b37412f7103
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3594681203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3594681203
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1294223797
Short name T635
Test name
Test status
Simulation time 190788987 ps
CPU time 0.82 seconds
Started Jul 15 07:07:32 PM PDT 24
Finished Jul 15 07:07:43 PM PDT 24
Peak memory 206820 kb
Host smart-64c8bc5c-1bf5-4615-a8ee-41377bfd2a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12942
23797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1294223797
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.4239650942
Short name T1538
Test name
Test status
Simulation time 157308367 ps
CPU time 0.78 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206800 kb
Host smart-37bdcf87-76d4-4338-9e9d-787b6d53f7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42396
50942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.4239650942
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.262088058
Short name T1431
Test name
Test status
Simulation time 366136686 ps
CPU time 1.18 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206800 kb
Host smart-a1f61897-944e-4463-9bbb-3e919761c241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26208
8058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.262088058
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.905962464
Short name T674
Test name
Test status
Simulation time 1236041843 ps
CPU time 2.66 seconds
Started Jul 15 07:07:34 PM PDT 24
Finished Jul 15 07:07:48 PM PDT 24
Peak memory 206976 kb
Host smart-6080dbe8-721a-4225-ba48-3caef2a37c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90596
2464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.905962464
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1836838351
Short name T917
Test name
Test status
Simulation time 12888170304 ps
CPU time 22.31 seconds
Started Jul 15 07:07:35 PM PDT 24
Finished Jul 15 07:08:08 PM PDT 24
Peak memory 206988 kb
Host smart-219e1ee1-3b48-4c9b-9da9-a0f460ef642b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18368
38351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1836838351
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1990003410
Short name T840
Test name
Test status
Simulation time 509249762 ps
CPU time 1.38 seconds
Started Jul 15 07:07:27 PM PDT 24
Finished Jul 15 07:07:38 PM PDT 24
Peak memory 206812 kb
Host smart-331625e1-ddf9-4914-8d8b-cbb2afc3571b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19900
03410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1990003410
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3521307338
Short name T1107
Test name
Test status
Simulation time 139309702 ps
CPU time 0.75 seconds
Started Jul 15 07:07:27 PM PDT 24
Finished Jul 15 07:07:37 PM PDT 24
Peak memory 206820 kb
Host smart-882ac72b-1cc7-4d6e-9913-8a5bde7ddcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35213
07338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3521307338
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.900754760
Short name T379
Test name
Test status
Simulation time 89553275 ps
CPU time 0.69 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 206784 kb
Host smart-aa4e07d1-37b8-4373-88a2-c85c5787c052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90075
4760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.900754760
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.136364008
Short name T2567
Test name
Test status
Simulation time 899084779 ps
CPU time 1.99 seconds
Started Jul 15 07:07:29 PM PDT 24
Finished Jul 15 07:07:41 PM PDT 24
Peak memory 206968 kb
Host smart-c9eafa37-f10e-407c-8f75-731a93eff176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13636
4008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.136364008
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2776461136
Short name T2670
Test name
Test status
Simulation time 167794025 ps
CPU time 1.72 seconds
Started Jul 15 07:07:29 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 207024 kb
Host smart-df605e2e-90d6-4e5c-9d2f-3b4d645ce872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27764
61136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2776461136
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.4046939912
Short name T1736
Test name
Test status
Simulation time 162696331 ps
CPU time 0.81 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206808 kb
Host smart-273d0509-e981-435e-9361-134909c8ffd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40469
39912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.4046939912
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2312847599
Short name T1929
Test name
Test status
Simulation time 141080190 ps
CPU time 0.81 seconds
Started Jul 15 07:07:29 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 206812 kb
Host smart-8ba48817-78bb-44af-b2ce-bf3691a424d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23128
47599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2312847599
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2072332132
Short name T2137
Test name
Test status
Simulation time 179881053 ps
CPU time 1.1 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206816 kb
Host smart-77dbbd96-ba40-4022-adbb-1202b2af8151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20723
32132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2072332132
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.1207358687
Short name T206
Test name
Test status
Simulation time 9067934613 ps
CPU time 251.43 seconds
Started Jul 15 07:07:28 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 207020 kb
Host smart-f8a0dbe1-57b3-4653-9a62-6b738365b281
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1207358687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.1207358687
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.2272539555
Short name T97
Test name
Test status
Simulation time 7960781515 ps
CPU time 28.03 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:08:20 PM PDT 24
Peak memory 207048 kb
Host smart-ae7f681e-95ec-4d95-b74a-5a0550e119bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22725
39555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.2272539555
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.228058565
Short name T385
Test name
Test status
Simulation time 183444002 ps
CPU time 0.86 seconds
Started Jul 15 07:07:31 PM PDT 24
Finished Jul 15 07:07:42 PM PDT 24
Peak memory 206836 kb
Host smart-d1b89953-aa52-4519-a65a-fd4685f82eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22805
8565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.228058565
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.4092298186
Short name T1460
Test name
Test status
Simulation time 23291808880 ps
CPU time 23.98 seconds
Started Jul 15 07:07:32 PM PDT 24
Finished Jul 15 07:08:07 PM PDT 24
Peak memory 206868 kb
Host smart-3100c5b8-0c6c-41e2-9f13-9fae2f8594d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
98186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.4092298186
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3911376591
Short name T323
Test name
Test status
Simulation time 3305742283 ps
CPU time 3.55 seconds
Started Jul 15 07:07:45 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206908 kb
Host smart-e9ae7643-a91d-4efb-8708-c4ac59cc91eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39113
76591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3911376591
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2593663397
Short name T443
Test name
Test status
Simulation time 11199955616 ps
CPU time 315.83 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:13:10 PM PDT 24
Peak memory 207120 kb
Host smart-1b15e50c-8239-44ee-97b6-9d83bf8f94e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25936
63397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2593663397
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2231368263
Short name T1576
Test name
Test status
Simulation time 3441950961 ps
CPU time 95.76 seconds
Started Jul 15 07:07:31 PM PDT 24
Finished Jul 15 07:09:18 PM PDT 24
Peak memory 206996 kb
Host smart-83f02e48-cb44-4af4-88ca-d54bd475b133
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2231368263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2231368263
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.4044344290
Short name T498
Test name
Test status
Simulation time 268829723 ps
CPU time 1.02 seconds
Started Jul 15 07:07:29 PM PDT 24
Finished Jul 15 07:07:40 PM PDT 24
Peak memory 206808 kb
Host smart-636eeb83-e33a-4fce-905c-4cf16ce2493f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4044344290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.4044344290
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2294036250
Short name T2544
Test name
Test status
Simulation time 196107969 ps
CPU time 0.87 seconds
Started Jul 15 07:07:35 PM PDT 24
Finished Jul 15 07:07:48 PM PDT 24
Peak memory 206804 kb
Host smart-72565a92-5978-4857-8047-8c043faab3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22940
36250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2294036250
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2332684429
Short name T804
Test name
Test status
Simulation time 4209514934 ps
CPU time 38 seconds
Started Jul 15 07:07:30 PM PDT 24
Finished Jul 15 07:08:19 PM PDT 24
Peak memory 207036 kb
Host smart-822c7f49-1902-445c-bfd3-2df92cb8a329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23326
84429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2332684429
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1365900587
Short name T1395
Test name
Test status
Simulation time 4141444721 ps
CPU time 38.7 seconds
Started Jul 15 07:07:43 PM PDT 24
Finished Jul 15 07:08:35 PM PDT 24
Peak memory 207080 kb
Host smart-318ba34f-6c3f-430e-99c8-0f5de38edbe7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1365900587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1365900587
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2559956277
Short name T816
Test name
Test status
Simulation time 162147280 ps
CPU time 0.79 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206792 kb
Host smart-7f5c5252-2ed6-430b-afbc-ffec10fa173c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2559956277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2559956277
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1141424759
Short name T631
Test name
Test status
Simulation time 141823609 ps
CPU time 0.75 seconds
Started Jul 15 07:07:43 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206824 kb
Host smart-8b477968-d411-47e7-beea-4c65da1e226d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11414
24759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1141424759
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.53617953
Short name T124
Test name
Test status
Simulation time 226106721 ps
CPU time 0.87 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:07:52 PM PDT 24
Peak memory 206808 kb
Host smart-3e99e6fa-601e-4425-b785-b9e179a1e80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53617
953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.53617953
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.979990448
Short name T348
Test name
Test status
Simulation time 163905275 ps
CPU time 0.76 seconds
Started Jul 15 07:07:36 PM PDT 24
Finished Jul 15 07:07:48 PM PDT 24
Peak memory 206824 kb
Host smart-9f0f21fa-babc-4d88-8876-b9cf08b56843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97999
0448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.979990448
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3413209790
Short name T2162
Test name
Test status
Simulation time 149427561 ps
CPU time 0.74 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:07:52 PM PDT 24
Peak memory 206784 kb
Host smart-7c2b861e-f887-4ee3-99a3-42ae07aee254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34132
09790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3413209790
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3410408227
Short name T2672
Test name
Test status
Simulation time 206025092 ps
CPU time 0.83 seconds
Started Jul 15 07:07:39 PM PDT 24
Finished Jul 15 07:07:54 PM PDT 24
Peak memory 206748 kb
Host smart-d81a07b5-23ed-49f2-811b-c8e2bfb81944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34104
08227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3410408227
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.223224591
Short name T2683
Test name
Test status
Simulation time 147725681 ps
CPU time 0.85 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206768 kb
Host smart-0824d2c9-af08-4cba-a793-3de07daf5248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322
4591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.223224591
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.787961930
Short name T2411
Test name
Test status
Simulation time 206366849 ps
CPU time 0.93 seconds
Started Jul 15 07:07:36 PM PDT 24
Finished Jul 15 07:07:49 PM PDT 24
Peak memory 206832 kb
Host smart-b6d4d809-6d99-4ac9-a1ee-54834973322c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=787961930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.787961930
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2857198084
Short name T725
Test name
Test status
Simulation time 149909456 ps
CPU time 0.77 seconds
Started Jul 15 07:07:45 PM PDT 24
Finished Jul 15 07:07:59 PM PDT 24
Peak memory 206800 kb
Host smart-8d8866bf-227d-4824-8e27-a809571a8969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28571
98084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2857198084
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1405166918
Short name T886
Test name
Test status
Simulation time 40401772 ps
CPU time 0.65 seconds
Started Jul 15 07:07:39 PM PDT 24
Finished Jul 15 07:07:53 PM PDT 24
Peak memory 206780 kb
Host smart-fe2152bd-ffc8-4459-9b43-c0bfaa5fa2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14051
66918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1405166918
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1646616767
Short name T1188
Test name
Test status
Simulation time 239628306 ps
CPU time 0.87 seconds
Started Jul 15 07:07:39 PM PDT 24
Finished Jul 15 07:07:53 PM PDT 24
Peak memory 206784 kb
Host smart-11b120b4-f695-48cf-83c9-c52cf1421355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16466
16767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1646616767
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.156444140
Short name T320
Test name
Test status
Simulation time 221157986 ps
CPU time 0.85 seconds
Started Jul 15 07:07:46 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206844 kb
Host smart-b39b2f3e-3fcb-4255-b709-338e4f827f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15644
4140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.156444140
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2923170665
Short name T369
Test name
Test status
Simulation time 243219066 ps
CPU time 0.89 seconds
Started Jul 15 07:07:39 PM PDT 24
Finished Jul 15 07:07:53 PM PDT 24
Peak memory 206808 kb
Host smart-8ce5e856-6508-402b-a306-feb136161cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29231
70665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2923170665
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1352130510
Short name T1717
Test name
Test status
Simulation time 153476290 ps
CPU time 0.77 seconds
Started Jul 15 07:07:37 PM PDT 24
Finished Jul 15 07:07:50 PM PDT 24
Peak memory 206788 kb
Host smart-6ee4e5a5-5fd2-4c96-8ff8-aabcab8d6afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13521
30510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1352130510
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1683918417
Short name T1377
Test name
Test status
Simulation time 146068710 ps
CPU time 0.78 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206808 kb
Host smart-51a599b7-a7f2-4a25-b96a-f718095fdcff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16839
18417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1683918417
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.4285688582
Short name T2512
Test name
Test status
Simulation time 166038840 ps
CPU time 0.77 seconds
Started Jul 15 07:07:43 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206824 kb
Host smart-8c985f40-0b15-4626-ad18-9e7775872561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42856
88582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.4285688582
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2547288713
Short name T2687
Test name
Test status
Simulation time 148550112 ps
CPU time 0.78 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206836 kb
Host smart-94d7f1b8-8f73-4fe0-b481-0adebba4f9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25472
88713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2547288713
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.591668028
Short name T659
Test name
Test status
Simulation time 228261924 ps
CPU time 0.95 seconds
Started Jul 15 07:07:39 PM PDT 24
Finished Jul 15 07:07:53 PM PDT 24
Peak memory 206840 kb
Host smart-22c722bc-0c27-40c1-8eb4-a3e6ce90968d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59166
8028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.591668028
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.602743649
Short name T2627
Test name
Test status
Simulation time 5381835140 ps
CPU time 42.17 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:08:34 PM PDT 24
Peak memory 207056 kb
Host smart-0cfb7579-7f2a-42d8-b336-e3161a04678d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=602743649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.602743649
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2984351021
Short name T1548
Test name
Test status
Simulation time 173148328 ps
CPU time 0.8 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 206796 kb
Host smart-5594e924-f971-4a5b-8600-4a72e2ddb290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29843
51021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2984351021
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1594920978
Short name T713
Test name
Test status
Simulation time 176997934 ps
CPU time 0.81 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206844 kb
Host smart-156185ba-4970-47a3-8ca4-eca7da7488db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15949
20978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1594920978
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.1318410501
Short name T1397
Test name
Test status
Simulation time 570297752 ps
CPU time 1.56 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 206796 kb
Host smart-183b6a92-f425-4640-852c-cc85ea6e8a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13184
10501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1318410501
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3039120296
Short name T1614
Test name
Test status
Simulation time 6446059679 ps
CPU time 45.4 seconds
Started Jul 15 07:07:39 PM PDT 24
Finished Jul 15 07:08:37 PM PDT 24
Peak memory 207088 kb
Host smart-72a89698-6bae-424e-bbaa-cf6b4ab83b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30391
20296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3039120296
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3305948451
Short name T1562
Test name
Test status
Simulation time 75887981 ps
CPU time 0.71 seconds
Started Jul 15 07:07:49 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206884 kb
Host smart-c2956754-8f19-48bf-98a2-9dbfd37b7cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3305948451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3305948451
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.3045191416
Short name T2129
Test name
Test status
Simulation time 3417479773 ps
CPU time 4.31 seconds
Started Jul 15 07:07:46 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 206996 kb
Host smart-a4e6838d-6716-4c37-a6a2-dc46ddcad543
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3045191416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.3045191416
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.57722107
Short name T669
Test name
Test status
Simulation time 13371180268 ps
CPU time 13.96 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:08:08 PM PDT 24
Peak memory 206828 kb
Host smart-7d72b683-d4a2-4ab7-9cf2-7f028257f47a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=57722107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.57722107
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3830273121
Short name T1081
Test name
Test status
Simulation time 23444401120 ps
CPU time 21.73 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 207036 kb
Host smart-982dd407-fb83-4c58-9329-384548c0f952
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3830273121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3830273121
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2170530840
Short name T368
Test name
Test status
Simulation time 245985707 ps
CPU time 0.88 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206836 kb
Host smart-98f877b3-48cf-4957-879a-aa073ba6e6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21705
30840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2170530840
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3170744472
Short name T1405
Test name
Test status
Simulation time 154768682 ps
CPU time 0.82 seconds
Started Jul 15 07:07:56 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206764 kb
Host smart-cb064b7b-ff2c-4e13-8dc5-932e9a79c820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31707
44472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3170744472
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3920300441
Short name T1362
Test name
Test status
Simulation time 508204145 ps
CPU time 1.51 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206952 kb
Host smart-04819642-fb57-4349-a137-9562f1632a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39203
00441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3920300441
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3612040106
Short name T2590
Test name
Test status
Simulation time 436801444 ps
CPU time 1.37 seconds
Started Jul 15 07:07:52 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 206756 kb
Host smart-c9f6598e-248c-4aa7-bc82-38f196d81603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
40106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3612040106
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.2360800877
Short name T2255
Test name
Test status
Simulation time 19045462773 ps
CPU time 40.85 seconds
Started Jul 15 07:07:35 PM PDT 24
Finished Jul 15 07:08:28 PM PDT 24
Peak memory 207088 kb
Host smart-433c7dda-15f2-4882-a1b5-bc3c447671d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23608
00877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2360800877
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.630583067
Short name T2718
Test name
Test status
Simulation time 334227069 ps
CPU time 1.1 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 206816 kb
Host smart-fc40c209-2634-4995-a03e-bf44b4baac14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63058
3067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.630583067
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3957846275
Short name T2353
Test name
Test status
Simulation time 144745610 ps
CPU time 0.72 seconds
Started Jul 15 07:07:43 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206828 kb
Host smart-2cfa560a-f957-489a-9bca-e2252c041176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39578
46275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3957846275
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.352585656
Short name T2244
Test name
Test status
Simulation time 55963159 ps
CPU time 0.7 seconds
Started Jul 15 07:07:55 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206808 kb
Host smart-02889ce5-d55f-449d-902e-e7bdcfe16509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35258
5656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.352585656
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3758832669
Short name T946
Test name
Test status
Simulation time 996883024 ps
CPU time 2.34 seconds
Started Jul 15 07:07:37 PM PDT 24
Finished Jul 15 07:07:51 PM PDT 24
Peak memory 206960 kb
Host smart-49c1b8ec-b9c7-4c03-a2f6-a6546a38b818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37588
32669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3758832669
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.75226881
Short name T1341
Test name
Test status
Simulation time 246239744 ps
CPU time 2.06 seconds
Started Jul 15 07:07:37 PM PDT 24
Finished Jul 15 07:07:52 PM PDT 24
Peak memory 206960 kb
Host smart-ab9d5fcd-8e5b-4d92-980a-614fd0feeb5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75226
881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.75226881
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2216541867
Short name T714
Test name
Test status
Simulation time 187138794 ps
CPU time 0.9 seconds
Started Jul 15 07:07:55 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206756 kb
Host smart-ea829064-0564-4fc3-aa4f-c3e8be7ae213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22165
41867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2216541867
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.330115113
Short name T2634
Test name
Test status
Simulation time 134144332 ps
CPU time 0.76 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 206752 kb
Host smart-c9d6fbb0-6f5b-4793-9376-8d74ab311eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33011
5113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.330115113
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.4156496478
Short name T2602
Test name
Test status
Simulation time 206445570 ps
CPU time 0.83 seconds
Started Jul 15 07:07:44 PM PDT 24
Finished Jul 15 07:07:58 PM PDT 24
Peak memory 206764 kb
Host smart-54bd2c82-0ec3-44e2-9231-f69d374b057d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41564
96478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4156496478
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1325675672
Short name T1217
Test name
Test status
Simulation time 10617928366 ps
CPU time 42.48 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:08:33 PM PDT 24
Peak memory 207012 kb
Host smart-c4a7862a-4f43-4197-ab4f-8eeef78e3924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
75672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1325675672
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1414109484
Short name T52
Test name
Test status
Simulation time 274827448 ps
CPU time 0.9 seconds
Started Jul 15 07:07:38 PM PDT 24
Finished Jul 15 07:07:53 PM PDT 24
Peak memory 206812 kb
Host smart-de89c660-73a7-40ab-a2b5-e39261166d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141
09484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1414109484
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1982296037
Short name T1541
Test name
Test status
Simulation time 23315202894 ps
CPU time 22.04 seconds
Started Jul 15 07:07:45 PM PDT 24
Finished Jul 15 07:08:20 PM PDT 24
Peak memory 206908 kb
Host smart-81180d34-8f88-4d6b-a5a6-2d11d87f1126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
96037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1982296037
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3389769505
Short name T1873
Test name
Test status
Simulation time 3316668586 ps
CPU time 3.74 seconds
Started Jul 15 07:07:39 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 207048 kb
Host smart-240a4f57-1941-4862-b354-1a27bb187d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33897
69505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3389769505
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.230965530
Short name T2451
Test name
Test status
Simulation time 8905842128 ps
CPU time 82.83 seconds
Started Jul 15 07:07:53 PM PDT 24
Finished Jul 15 07:09:25 PM PDT 24
Peak memory 207084 kb
Host smart-58031fa0-b451-4611-b018-dfdfdd36c941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23096
5530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.230965530
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.328399850
Short name T794
Test name
Test status
Simulation time 5554287471 ps
CPU time 159.35 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:10:34 PM PDT 24
Peak memory 207008 kb
Host smart-35333fa2-bb37-4be1-bccd-784d26d549f6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=328399850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.328399850
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3713155764
Short name T2209
Test name
Test status
Simulation time 240355332 ps
CPU time 0.88 seconds
Started Jul 15 07:07:37 PM PDT 24
Finished Jul 15 07:07:50 PM PDT 24
Peak memory 206784 kb
Host smart-fbfad8ab-2d32-470b-b684-7edcabf699d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3713155764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3713155764
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2809224313
Short name T1193
Test name
Test status
Simulation time 222982549 ps
CPU time 0.94 seconds
Started Jul 15 07:08:00 PM PDT 24
Finished Jul 15 07:08:06 PM PDT 24
Peak memory 206788 kb
Host smart-9900bed6-4f8a-47f9-81db-be99b1fdcad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28092
24313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2809224313
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3806471849
Short name T2637
Test name
Test status
Simulation time 3792903280 ps
CPU time 36.25 seconds
Started Jul 15 07:07:44 PM PDT 24
Finished Jul 15 07:08:33 PM PDT 24
Peak memory 206960 kb
Host smart-3da13613-55c8-485e-bf0f-b3e89459ebfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38064
71849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3806471849
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3378790542
Short name T1091
Test name
Test status
Simulation time 3247568852 ps
CPU time 30.32 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:08:26 PM PDT 24
Peak memory 207008 kb
Host smart-a7045a76-6c42-44b7-a065-ca664d8901b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3378790542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3378790542
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2134161207
Short name T471
Test name
Test status
Simulation time 164130258 ps
CPU time 0.79 seconds
Started Jul 15 07:07:53 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 206808 kb
Host smart-b5f59df5-42ff-46ac-9901-9b26c588da15
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2134161207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2134161207
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1468857587
Short name T2040
Test name
Test status
Simulation time 220183065 ps
CPU time 0.81 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 206844 kb
Host smart-1569e3b9-4f7f-4fb5-9d14-3af3e9559b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14688
57587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1468857587
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3109815422
Short name T122
Test name
Test status
Simulation time 209174828 ps
CPU time 0.87 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 206812 kb
Host smart-0070b58b-755e-471e-a09a-38f5162a5ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31098
15422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3109815422
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1205951822
Short name T2529
Test name
Test status
Simulation time 156285773 ps
CPU time 0.75 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206832 kb
Host smart-de7bddbb-df8d-4591-a3aa-4e9ff702b5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059
51822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1205951822
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.445749761
Short name T95
Test name
Test status
Simulation time 180636046 ps
CPU time 0.77 seconds
Started Jul 15 07:07:53 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 206808 kb
Host smart-8e638304-dfba-4952-b882-47fdbc787403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44574
9761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.445749761
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.659171094
Short name T1518
Test name
Test status
Simulation time 197415813 ps
CPU time 0.8 seconds
Started Jul 15 07:07:49 PM PDT 24
Finished Jul 15 07:08:02 PM PDT 24
Peak memory 206984 kb
Host smart-381b5f78-7204-488a-ab6a-09295a6aca67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65917
1094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.659171094
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.588268473
Short name T2596
Test name
Test status
Simulation time 162483325 ps
CPU time 0.8 seconds
Started Jul 15 07:07:51 PM PDT 24
Finished Jul 15 07:08:02 PM PDT 24
Peak memory 206792 kb
Host smart-68536989-aaa7-4457-94f1-3268ca847e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58826
8473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.588268473
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2379444978
Short name T1598
Test name
Test status
Simulation time 216210251 ps
CPU time 1.06 seconds
Started Jul 15 07:07:57 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206832 kb
Host smart-d8f36165-d662-40ab-ad55-bbecba95406f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2379444978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2379444978
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3146694332
Short name T2577
Test name
Test status
Simulation time 145462290 ps
CPU time 0.78 seconds
Started Jul 15 07:07:43 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206820 kb
Host smart-f8591ddb-5fe1-407f-9dac-1e9ef703b88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31466
94332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3146694332
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1129579426
Short name T36
Test name
Test status
Simulation time 58479580 ps
CPU time 0.67 seconds
Started Jul 15 07:07:45 PM PDT 24
Finished Jul 15 07:07:59 PM PDT 24
Peak memory 206788 kb
Host smart-f7cc83d4-4661-4836-b766-14aebe620446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11295
79426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1129579426
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.983740779
Short name T234
Test name
Test status
Simulation time 15080342878 ps
CPU time 34.61 seconds
Started Jul 15 07:07:51 PM PDT 24
Finished Jul 15 07:08:36 PM PDT 24
Peak memory 207112 kb
Host smart-fd487658-95bb-45d7-a9e1-ba35bbc9e813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98374
0779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.983740779
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1762002826
Short name T1531
Test name
Test status
Simulation time 198469567 ps
CPU time 0.86 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 206812 kb
Host smart-2ffb3d22-6a8d-450f-9b05-802147e5771e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17620
02826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1762002826
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1658044896
Short name T1747
Test name
Test status
Simulation time 189951597 ps
CPU time 0.83 seconds
Started Jul 15 07:07:58 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206800 kb
Host smart-2bca0048-a247-4b1c-b758-30befc8a02c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16580
44896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1658044896
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2328215755
Short name T2729
Test name
Test status
Simulation time 219797752 ps
CPU time 0.86 seconds
Started Jul 15 07:07:42 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206760 kb
Host smart-0c1c8ff9-f540-415f-a2b4-869d5b5b4c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
15755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2328215755
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.616638498
Short name T1013
Test name
Test status
Simulation time 170401704 ps
CPU time 0.87 seconds
Started Jul 15 07:07:56 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206792 kb
Host smart-b99f59c6-c6fc-46b6-93c1-cfdbb4271f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61663
8498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.616638498
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1531337564
Short name T2391
Test name
Test status
Simulation time 148499051 ps
CPU time 0.75 seconds
Started Jul 15 07:07:43 PM PDT 24
Finished Jul 15 07:07:57 PM PDT 24
Peak memory 206792 kb
Host smart-fbeae4be-bd70-45ed-b8a2-87e1dcdff105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15313
37564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1531337564
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.175321684
Short name T2435
Test name
Test status
Simulation time 145206742 ps
CPU time 0.8 seconds
Started Jul 15 07:07:43 PM PDT 24
Finished Jul 15 07:07:58 PM PDT 24
Peak memory 206816 kb
Host smart-b7e7893c-d90b-4ff5-a14b-6d6a3aee484d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17532
1684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.175321684
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2592257265
Short name T89
Test name
Test status
Simulation time 145577395 ps
CPU time 0.79 seconds
Started Jul 15 07:07:45 PM PDT 24
Finished Jul 15 07:07:58 PM PDT 24
Peak memory 206824 kb
Host smart-a8f1d598-8368-479f-96f4-5df27a7a0311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25922
57265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2592257265
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2124066674
Short name T470
Test name
Test status
Simulation time 219944196 ps
CPU time 1.02 seconds
Started Jul 15 07:07:53 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 206832 kb
Host smart-737e435d-8dc5-4f83-8962-09ae897362ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21240
66674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2124066674
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.71896673
Short name T1189
Test name
Test status
Simulation time 3586393283 ps
CPU time 36.57 seconds
Started Jul 15 07:07:51 PM PDT 24
Finished Jul 15 07:08:38 PM PDT 24
Peak memory 207052 kb
Host smart-9c88d38c-d47f-48ab-90d7-4e808ee9c24c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=71896673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.71896673
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2940786824
Short name T1261
Test name
Test status
Simulation time 202274098 ps
CPU time 0.84 seconds
Started Jul 15 07:07:40 PM PDT 24
Finished Jul 15 07:07:55 PM PDT 24
Peak memory 206708 kb
Host smart-e42115a5-7a7e-4ec8-baaf-aae22be771b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29407
86824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2940786824
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1294569374
Short name T605
Test name
Test status
Simulation time 162129045 ps
CPU time 0.8 seconds
Started Jul 15 07:07:49 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206824 kb
Host smart-47c49c47-400a-471d-bbee-820f8d568558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12945
69374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1294569374
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.4014039580
Short name T645
Test name
Test status
Simulation time 259421927 ps
CPU time 1.04 seconds
Started Jul 15 07:07:51 PM PDT 24
Finished Jul 15 07:08:02 PM PDT 24
Peak memory 206784 kb
Host smart-f0c91223-4cde-421a-a0e6-b81ad1f64c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40140
39580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.4014039580
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1625621369
Short name T2150
Test name
Test status
Simulation time 4420725956 ps
CPU time 40.62 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:40 PM PDT 24
Peak memory 207016 kb
Host smart-404f010e-0224-4030-8d9a-66f0789e2f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
21369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1625621369
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2157511177
Short name T1204
Test name
Test status
Simulation time 32543168 ps
CPU time 0.68 seconds
Started Jul 15 07:03:24 PM PDT 24
Finished Jul 15 07:03:25 PM PDT 24
Peak memory 206840 kb
Host smart-d9e700d8-1268-4477-bead-430b4d7163af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2157511177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2157511177
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3150605380
Short name T2181
Test name
Test status
Simulation time 4383779155 ps
CPU time 4.88 seconds
Started Jul 15 07:03:10 PM PDT 24
Finished Jul 15 07:03:15 PM PDT 24
Peak memory 207036 kb
Host smart-75974955-0f90-440f-b653-edd8f0567fae
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3150605380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3150605380
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1839693766
Short name T1152
Test name
Test status
Simulation time 13350211537 ps
CPU time 13.23 seconds
Started Jul 15 07:03:06 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206892 kb
Host smart-382e9a62-7f1f-4752-9f3c-eb59d18949a9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1839693766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1839693766
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.247939924
Short name T2608
Test name
Test status
Simulation time 23339141448 ps
CPU time 23.59 seconds
Started Jul 15 07:03:10 PM PDT 24
Finished Jul 15 07:03:34 PM PDT 24
Peak memory 207100 kb
Host smart-3b8eec3a-9f59-44b4-846e-5c487e1cc06a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=247939924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.247939924
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.652115397
Short name T1449
Test name
Test status
Simulation time 181261449 ps
CPU time 0.84 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 206968 kb
Host smart-ccc2aed8-73be-4418-ad7b-add62ac93ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65211
5397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.652115397
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1054359394
Short name T44
Test name
Test status
Simulation time 160020258 ps
CPU time 0.8 seconds
Started Jul 15 07:03:13 PM PDT 24
Finished Jul 15 07:03:15 PM PDT 24
Peak memory 206788 kb
Host smart-cf22825c-14e7-49ed-8ea5-a9cdd522323b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543
59394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1054359394
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.1669183020
Short name T80
Test name
Test status
Simulation time 135931359 ps
CPU time 0.76 seconds
Started Jul 15 07:03:14 PM PDT 24
Finished Jul 15 07:03:15 PM PDT 24
Peak memory 206804 kb
Host smart-e939e7ca-5f86-4bff-89a7-7e47a8cb9e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16691
83020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.1669183020
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3451464818
Short name T2511
Test name
Test status
Simulation time 180168630 ps
CPU time 0.83 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 206820 kb
Host smart-d865a098-f343-4bed-b44c-6391b2bf8a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34514
64818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3451464818
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2536639845
Short name T703
Test name
Test status
Simulation time 269463243 ps
CPU time 1.06 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 206820 kb
Host smart-991fa9b7-c161-4cc3-bd89-7cc108e82fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25366
39845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2536639845
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1108034404
Short name T1305
Test name
Test status
Simulation time 1098576897 ps
CPU time 2.47 seconds
Started Jul 15 07:03:18 PM PDT 24
Finished Jul 15 07:03:21 PM PDT 24
Peak memory 206980 kb
Host smart-1a62a4fc-c9cf-47a7-af1d-eea23191bb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11080
34404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1108034404
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3251158908
Short name T1210
Test name
Test status
Simulation time 7163735086 ps
CPU time 14.34 seconds
Started Jul 15 07:03:14 PM PDT 24
Finished Jul 15 07:03:29 PM PDT 24
Peak memory 207072 kb
Host smart-9a93ce34-f0e4-450e-962f-052f55141dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32511
58908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3251158908
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.4213580074
Short name T2170
Test name
Test status
Simulation time 473316313 ps
CPU time 1.36 seconds
Started Jul 15 07:03:13 PM PDT 24
Finished Jul 15 07:03:15 PM PDT 24
Peak memory 206796 kb
Host smart-0391f66d-b2a0-41ca-9304-b71171147935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
80074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.4213580074
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.72320230
Short name T2443
Test name
Test status
Simulation time 151494540 ps
CPU time 0.81 seconds
Started Jul 15 07:03:17 PM PDT 24
Finished Jul 15 07:03:19 PM PDT 24
Peak memory 206804 kb
Host smart-d75c697a-fba5-4017-a888-6d7d2c2c80d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72320
230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.72320230
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.936801901
Short name T1820
Test name
Test status
Simulation time 93368258 ps
CPU time 0.7 seconds
Started Jul 15 07:03:17 PM PDT 24
Finished Jul 15 07:03:18 PM PDT 24
Peak memory 206820 kb
Host smart-7ded4724-626d-426c-8a28-96913e016aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93680
1901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.936801901
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2981941114
Short name T2363
Test name
Test status
Simulation time 722463439 ps
CPU time 1.85 seconds
Started Jul 15 07:03:17 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206936 kb
Host smart-422d870e-d6b4-4bf9-8e51-33c9a5d8d893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29819
41114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2981941114
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1254154382
Short name T564
Test name
Test status
Simulation time 254511076 ps
CPU time 1.99 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:03:18 PM PDT 24
Peak memory 206924 kb
Host smart-f17f58e5-39c6-4105-98e2-482a19e6dbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12541
54382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1254154382
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.398860022
Short name T2034
Test name
Test status
Simulation time 96200601248 ps
CPU time 118.55 seconds
Started Jul 15 07:03:16 PM PDT 24
Finished Jul 15 07:05:15 PM PDT 24
Peak memory 207028 kb
Host smart-a8b3fa8f-3a58-4407-adfb-4ce782512f07
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=398860022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.398860022
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.700253783
Short name T1944
Test name
Test status
Simulation time 115303531867 ps
CPU time 153.38 seconds
Started Jul 15 07:03:12 PM PDT 24
Finished Jul 15 07:05:45 PM PDT 24
Peak memory 207032 kb
Host smart-f83a4e66-5e1c-42c1-badc-3a99ac161570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700253783 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.700253783
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.1325289080
Short name T501
Test name
Test status
Simulation time 93147895935 ps
CPU time 137.96 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:05:34 PM PDT 24
Peak memory 207024 kb
Host smart-6856c17f-0140-4a01-9889-b1350042111b
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1325289080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.1325289080
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1373531051
Short name T1257
Test name
Test status
Simulation time 89040405317 ps
CPU time 135.96 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:05:31 PM PDT 24
Peak memory 207028 kb
Host smart-0623cfe7-2197-422a-bfc4-41760d19ed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373531051 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1373531051
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.3089402574
Short name T861
Test name
Test status
Simulation time 113140326592 ps
CPU time 154.4 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:05:50 PM PDT 24
Peak memory 207088 kb
Host smart-fb77147a-9f12-4296-9ee1-916cb8fdef44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30894
02574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.3089402574
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.4105695193
Short name T1965
Test name
Test status
Simulation time 206572615 ps
CPU time 0.83 seconds
Started Jul 15 07:03:12 PM PDT 24
Finished Jul 15 07:03:14 PM PDT 24
Peak memory 206800 kb
Host smart-bd13595a-e5a3-4d2c-84ba-6a73558b4e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41056
95193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.4105695193
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2549130698
Short name T1221
Test name
Test status
Simulation time 148346794 ps
CPU time 0.77 seconds
Started Jul 15 07:03:14 PM PDT 24
Finished Jul 15 07:03:15 PM PDT 24
Peak memory 206704 kb
Host smart-41c486f0-8bc4-4559-952b-07f2a995bfc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25491
30698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2549130698
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3629849296
Short name T1238
Test name
Test status
Simulation time 212562182 ps
CPU time 0.87 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 206776 kb
Host smart-0221e986-2fc9-4546-8c41-21d454727eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36298
49296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3629849296
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.2281138400
Short name T827
Test name
Test status
Simulation time 6063709125 ps
CPU time 172.27 seconds
Started Jul 15 07:03:18 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 206668 kb
Host smart-7566ecb9-e7d6-41a7-a2b5-d5c082821b54
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2281138400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2281138400
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.3012622236
Short name T907
Test name
Test status
Simulation time 10673888290 ps
CPU time 90.53 seconds
Started Jul 15 07:03:14 PM PDT 24
Finished Jul 15 07:04:45 PM PDT 24
Peak memory 207072 kb
Host smart-55130e8d-d04e-409d-baa3-3469b31e9d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30126
22236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.3012622236
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1036852379
Short name T960
Test name
Test status
Simulation time 198510990 ps
CPU time 0.89 seconds
Started Jul 15 07:03:18 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206480 kb
Host smart-f8493cb7-f031-499f-88f8-b160c04990b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10368
52379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1036852379
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2081458792
Short name T525
Test name
Test status
Simulation time 23302729345 ps
CPU time 24.28 seconds
Started Jul 15 07:03:14 PM PDT 24
Finished Jul 15 07:03:39 PM PDT 24
Peak memory 206840 kb
Host smart-d17b0192-9556-42a4-82fe-f6ffc43f8429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20814
58792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2081458792
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.16864730
Short name T1964
Test name
Test status
Simulation time 3279967968 ps
CPU time 3.97 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206908 kb
Host smart-ad06fb56-936d-4b16-91c0-6c13928aa4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16864
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.16864730
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.992158956
Short name T1783
Test name
Test status
Simulation time 10113822219 ps
CPU time 282.41 seconds
Started Jul 15 07:03:13 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 207080 kb
Host smart-5aee4e40-1374-4686-8942-5f1e6e40dcba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99215
8956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.992158956
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3639184790
Short name T835
Test name
Test status
Simulation time 4853757895 ps
CPU time 136.05 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:05:32 PM PDT 24
Peak memory 207024 kb
Host smart-a4608225-ccf3-4c05-a9e8-6d4ccd48f78c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3639184790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3639184790
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.321072507
Short name T1756
Test name
Test status
Simulation time 264319428 ps
CPU time 0.95 seconds
Started Jul 15 07:03:13 PM PDT 24
Finished Jul 15 07:03:15 PM PDT 24
Peak memory 206824 kb
Host smart-cae69563-a8d2-46ce-8dba-49e38b8de9e5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=321072507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.321072507
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2474091670
Short name T2630
Test name
Test status
Simulation time 189778184 ps
CPU time 0.86 seconds
Started Jul 15 07:03:13 PM PDT 24
Finished Jul 15 07:03:15 PM PDT 24
Peak memory 206820 kb
Host smart-75ce0c67-6691-4327-8505-f432dca3c004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24740
91670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2474091670
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2751569943
Short name T1807
Test name
Test status
Simulation time 4999663746 ps
CPU time 46.15 seconds
Started Jul 15 07:03:12 PM PDT 24
Finished Jul 15 07:03:58 PM PDT 24
Peak memory 207040 kb
Host smart-4f79f3ec-74d4-4dcc-9dfc-93bb7563614c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515
69943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2751569943
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.404018166
Short name T579
Test name
Test status
Simulation time 4799401174 ps
CPU time 45.04 seconds
Started Jul 15 07:03:18 PM PDT 24
Finished Jul 15 07:04:04 PM PDT 24
Peak memory 207092 kb
Host smart-6b7d934d-aebb-4735-9828-051cc2ab35f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=404018166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.404018166
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2702567197
Short name T1827
Test name
Test status
Simulation time 163839296 ps
CPU time 0.74 seconds
Started Jul 15 07:03:17 PM PDT 24
Finished Jul 15 07:03:19 PM PDT 24
Peak memory 206832 kb
Host smart-b1c3acf2-8cb6-45b7-9971-7aec9170b6df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2702567197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2702567197
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3897948491
Short name T1959
Test name
Test status
Simulation time 161574701 ps
CPU time 0.81 seconds
Started Jul 15 07:03:15 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 206828 kb
Host smart-d613b37d-bf1e-417a-a518-e5e4c1620d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38979
48491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3897948491
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3399900278
Short name T2447
Test name
Test status
Simulation time 199475190 ps
CPU time 0.83 seconds
Started Jul 15 07:03:14 PM PDT 24
Finished Jul 15 07:03:16 PM PDT 24
Peak memory 206808 kb
Host smart-43911917-3999-4b7f-9d19-e442e87fb5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33999
00278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3399900278
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1934933015
Short name T1400
Test name
Test status
Simulation time 195215295 ps
CPU time 0.88 seconds
Started Jul 15 07:03:16 PM PDT 24
Finished Jul 15 07:03:17 PM PDT 24
Peak memory 206800 kb
Host smart-77932658-e0a9-41dc-b369-8aa15336a708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19349
33015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1934933015
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.146991420
Short name T660
Test name
Test status
Simulation time 175827309 ps
CPU time 0.75 seconds
Started Jul 15 07:03:17 PM PDT 24
Finished Jul 15 07:03:19 PM PDT 24
Peak memory 206836 kb
Host smart-fea705dc-89c6-479f-8627-034fd5adf007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14699
1420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.146991420
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3115655422
Short name T2658
Test name
Test status
Simulation time 183261872 ps
CPU time 0.83 seconds
Started Jul 15 07:03:21 PM PDT 24
Finished Jul 15 07:03:23 PM PDT 24
Peak memory 206816 kb
Host smart-4f84bb62-c83b-42c4-8da0-6ecd3ef3711f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31156
55422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3115655422
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.971374467
Short name T2572
Test name
Test status
Simulation time 151317103 ps
CPU time 0.82 seconds
Started Jul 15 07:03:19 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206816 kb
Host smart-7758227b-dec2-4793-a982-a59f0da8ffa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97137
4467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.971374467
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.1443860729
Short name T881
Test name
Test status
Simulation time 284202477 ps
CPU time 1.15 seconds
Started Jul 15 07:03:23 PM PDT 24
Finished Jul 15 07:03:25 PM PDT 24
Peak memory 206796 kb
Host smart-c1a7d05b-11fb-4010-82d4-8ee96a1382dc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1443860729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.1443860729
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3536586438
Short name T187
Test name
Test status
Simulation time 244745349 ps
CPU time 0.99 seconds
Started Jul 15 07:03:22 PM PDT 24
Finished Jul 15 07:03:24 PM PDT 24
Peak memory 206796 kb
Host smart-06cd80f8-e2a5-4191-ba33-a0b684300fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35365
86438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3536586438
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2667152991
Short name T1833
Test name
Test status
Simulation time 145855861 ps
CPU time 0.8 seconds
Started Jul 15 07:03:22 PM PDT 24
Finished Jul 15 07:03:23 PM PDT 24
Peak memory 206760 kb
Host smart-83b2a1e1-5fdf-4842-809c-0ab7371e7ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26671
52991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2667152991
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1733101151
Short name T1202
Test name
Test status
Simulation time 82175094 ps
CPU time 0.71 seconds
Started Jul 15 07:03:21 PM PDT 24
Finished Jul 15 07:03:22 PM PDT 24
Peak memory 206756 kb
Host smart-b867c654-f2c8-4a14-b25b-72a43514efde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17331
01151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1733101151
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.711661018
Short name T2550
Test name
Test status
Simulation time 8038622135 ps
CPU time 16.95 seconds
Started Jul 15 07:03:19 PM PDT 24
Finished Jul 15 07:03:36 PM PDT 24
Peak memory 214720 kb
Host smart-3230016e-62b6-4d2d-94c8-cb26afcde99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71166
1018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.711661018
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1949117948
Short name T1843
Test name
Test status
Simulation time 169975597 ps
CPU time 0.77 seconds
Started Jul 15 07:03:21 PM PDT 24
Finished Jul 15 07:03:22 PM PDT 24
Peak memory 206824 kb
Host smart-25be5718-d75f-4090-b938-07518b2d8f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19491
17948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1949117948
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1707265910
Short name T1457
Test name
Test status
Simulation time 203843327 ps
CPU time 0.98 seconds
Started Jul 15 07:03:18 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206816 kb
Host smart-12a1c5f4-f603-49eb-95e5-8967944a399b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17072
65910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1707265910
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1192831646
Short name T159
Test name
Test status
Simulation time 6927885059 ps
CPU time 187.66 seconds
Started Jul 15 07:03:20 PM PDT 24
Finished Jul 15 07:06:28 PM PDT 24
Peak memory 207112 kb
Host smart-a198ea44-3a92-4b32-aa0b-f39a2f6f16f4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1192831646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1192831646
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2460363090
Short name T1403
Test name
Test status
Simulation time 17269996594 ps
CPU time 97.37 seconds
Started Jul 15 07:03:22 PM PDT 24
Finished Jul 15 07:05:00 PM PDT 24
Peak memory 206964 kb
Host smart-f27a980b-54d6-4147-8baf-34358c4e1b25
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2460363090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2460363090
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2226878175
Short name T1867
Test name
Test status
Simulation time 15445336770 ps
CPU time 79.54 seconds
Started Jul 15 07:03:21 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 207096 kb
Host smart-f6b85f28-0803-40ab-b7f7-ddaa6f94309f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2226878175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2226878175
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.4015824221
Short name T721
Test name
Test status
Simulation time 183672700 ps
CPU time 0.86 seconds
Started Jul 15 07:03:22 PM PDT 24
Finished Jul 15 07:03:24 PM PDT 24
Peak memory 206792 kb
Host smart-5cc3674f-3095-4c1a-9747-abe4d9c2da83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40158
24221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.4015824221
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2534222119
Short name T456
Test name
Test status
Simulation time 156915302 ps
CPU time 0.78 seconds
Started Jul 15 07:03:20 PM PDT 24
Finished Jul 15 07:03:21 PM PDT 24
Peak memory 206792 kb
Host smart-9006e78c-1998-4ca6-8f66-762fdc66a134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25342
22119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2534222119
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1921377750
Short name T652
Test name
Test status
Simulation time 149799751 ps
CPU time 0.78 seconds
Started Jul 15 07:03:21 PM PDT 24
Finished Jul 15 07:03:23 PM PDT 24
Peak memory 206812 kb
Host smart-a1990e0e-e11c-4805-af7c-ae0261b62de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19213
77750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1921377750
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.1570300177
Short name T216
Test name
Test status
Simulation time 175769382 ps
CPU time 0.8 seconds
Started Jul 15 07:03:20 PM PDT 24
Finished Jul 15 07:03:22 PM PDT 24
Peak memory 206792 kb
Host smart-bdb12388-2a62-4c18-9b4f-1399556b2133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15703
00177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.1570300177
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1954201667
Short name T196
Test name
Test status
Simulation time 326587760 ps
CPU time 1.07 seconds
Started Jul 15 07:03:26 PM PDT 24
Finished Jul 15 07:03:28 PM PDT 24
Peak memory 224528 kb
Host smart-4e82a754-d53d-4ac2-98e0-c26ceaae766c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1954201667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1954201667
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.301851790
Short name T1934
Test name
Test status
Simulation time 424133769 ps
CPU time 1.26 seconds
Started Jul 15 07:03:18 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206828 kb
Host smart-31fb5a09-6128-49ec-b8ea-8e97f102f25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30185
1790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.301851790
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.401379965
Short name T2423
Test name
Test status
Simulation time 210243967 ps
CPU time 0.95 seconds
Started Jul 15 07:03:20 PM PDT 24
Finished Jul 15 07:03:21 PM PDT 24
Peak memory 206796 kb
Host smart-cc661680-4fc1-436c-b986-06f0631db445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40137
9965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.401379965
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1058271792
Short name T1428
Test name
Test status
Simulation time 147358118 ps
CPU time 0.75 seconds
Started Jul 15 07:03:19 PM PDT 24
Finished Jul 15 07:03:21 PM PDT 24
Peak memory 206780 kb
Host smart-f6f94914-172e-405c-8485-d359cbbb672e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10582
71792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1058271792
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1413194658
Short name T1971
Test name
Test status
Simulation time 210754495 ps
CPU time 0.83 seconds
Started Jul 15 07:03:21 PM PDT 24
Finished Jul 15 07:03:23 PM PDT 24
Peak memory 206812 kb
Host smart-7a98dc9b-a318-494c-8c4f-edbe4b2b1d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14131
94658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1413194658
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2199866882
Short name T2029
Test name
Test status
Simulation time 206335086 ps
CPU time 0.88 seconds
Started Jul 15 07:03:18 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206828 kb
Host smart-18059c14-a2be-4108-8bdd-fec240aaa3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21998
66882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2199866882
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3795941105
Short name T697
Test name
Test status
Simulation time 4513854404 ps
CPU time 122.28 seconds
Started Jul 15 07:03:23 PM PDT 24
Finished Jul 15 07:05:26 PM PDT 24
Peak memory 207040 kb
Host smart-3d686a19-a216-4e2d-a4d1-ccf17b0d20a5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3795941105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3795941105
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2734891548
Short name T526
Test name
Test status
Simulation time 206983790 ps
CPU time 0.85 seconds
Started Jul 15 07:03:23 PM PDT 24
Finished Jul 15 07:03:25 PM PDT 24
Peak memory 206816 kb
Host smart-80e51474-00c1-4ecf-988a-9a4e9bc5f1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
91548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2734891548
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1369737710
Short name T2104
Test name
Test status
Simulation time 150943539 ps
CPU time 0.78 seconds
Started Jul 15 07:03:19 PM PDT 24
Finished Jul 15 07:03:20 PM PDT 24
Peak memory 206260 kb
Host smart-1d0fd9d1-0a4e-4c57-84f8-8bf4b2ddf157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13697
37710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1369737710
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.780521094
Short name T1480
Test name
Test status
Simulation time 1377102932 ps
CPU time 2.74 seconds
Started Jul 15 07:03:26 PM PDT 24
Finished Jul 15 07:03:29 PM PDT 24
Peak memory 207008 kb
Host smart-711ec2e8-3bdd-40b3-ae42-1f2923d3469a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78052
1094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.780521094
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2122200426
Short name T2651
Test name
Test status
Simulation time 4426817093 ps
CPU time 114.33 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:05:31 PM PDT 24
Peak memory 207012 kb
Host smart-faf04684-7888-4d94-832f-28316ab86318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21222
00426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2122200426
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.747424633
Short name T527
Test name
Test status
Simulation time 42730377 ps
CPU time 0.66 seconds
Started Jul 15 07:08:00 PM PDT 24
Finished Jul 15 07:08:06 PM PDT 24
Peak memory 206852 kb
Host smart-aed8940c-9c9c-49e8-bf29-488a1a72d15a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=747424633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.747424633
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.827556942
Short name T684
Test name
Test status
Simulation time 3950289422 ps
CPU time 5.36 seconds
Started Jul 15 07:07:46 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206868 kb
Host smart-5075e919-2e23-43b9-a9ea-68268196f0ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=827556942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.827556942
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2086094255
Short name T633
Test name
Test status
Simulation time 13351374006 ps
CPU time 13.33 seconds
Started Jul 15 07:07:46 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 206900 kb
Host smart-af690158-c29f-4dfa-9b4a-995f8b9431ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2086094255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2086094255
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.4230001569
Short name T2515
Test name
Test status
Simulation time 23327344290 ps
CPU time 22.33 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:22 PM PDT 24
Peak memory 207064 kb
Host smart-ae69d92f-f0d7-4d1b-baab-e700c76a340b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4230001569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.4230001569
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1316973484
Short name T1788
Test name
Test status
Simulation time 160638509 ps
CPU time 0.79 seconds
Started Jul 15 07:07:44 PM PDT 24
Finished Jul 15 07:07:58 PM PDT 24
Peak memory 206828 kb
Host smart-2810e5da-e7fb-4192-a316-24c25cbe89a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13169
73484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1316973484
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1441123454
Short name T862
Test name
Test status
Simulation time 193576043 ps
CPU time 0.83 seconds
Started Jul 15 07:07:41 PM PDT 24
Finished Jul 15 07:07:56 PM PDT 24
Peak memory 206812 kb
Host smart-e39c4419-eba2-4599-9ad5-4dc87d7ca3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411
23454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1441123454
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1740445857
Short name T1191
Test name
Test status
Simulation time 357628455 ps
CPU time 1.23 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206780 kb
Host smart-79d41a8c-d39d-4e81-905f-2a486cd9b0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17404
45857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1740445857
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.416725244
Short name T2356
Test name
Test status
Simulation time 1166215668 ps
CPU time 2.96 seconds
Started Jul 15 07:07:55 PM PDT 24
Finished Jul 15 07:08:06 PM PDT 24
Peak memory 206936 kb
Host smart-fb41f30b-5ff9-4dce-85aa-4b15d2ad4e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41672
5244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.416725244
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1820689617
Short name T2318
Test name
Test status
Simulation time 16938434417 ps
CPU time 33.32 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:32 PM PDT 24
Peak memory 207020 kb
Host smart-ece8463a-0e76-4c8b-b040-3becd0251aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18206
89617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1820689617
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.489836189
Short name T821
Test name
Test status
Simulation time 527524197 ps
CPU time 1.57 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206816 kb
Host smart-ecb02590-5c56-42dc-8258-9393e5ac5c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48983
6189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.489836189
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1391155198
Short name T730
Test name
Test status
Simulation time 177002630 ps
CPU time 0.78 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206824 kb
Host smart-c40f9f45-cc2d-49ac-93be-101cfc961147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911
55198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1391155198
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.19974348
Short name T2297
Test name
Test status
Simulation time 48440044 ps
CPU time 0.69 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206804 kb
Host smart-2478e038-040c-4aa4-bcab-80b7a0d2b060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19974
348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.19974348
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3263130791
Short name T1295
Test name
Test status
Simulation time 993290723 ps
CPU time 2.81 seconds
Started Jul 15 07:07:49 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 207032 kb
Host smart-dde85968-9b14-47b8-8115-56a7702626c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32631
30791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3263130791
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.512743782
Short name T1010
Test name
Test status
Simulation time 229312699 ps
CPU time 1.34 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 207016 kb
Host smart-5d7c0baa-b739-47a6-937e-cfe8fecbec64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51274
3782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.512743782
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3005280775
Short name T2618
Test name
Test status
Simulation time 266857637 ps
CPU time 0.89 seconds
Started Jul 15 07:07:49 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206812 kb
Host smart-0508d952-30be-436e-b9d0-550a68b33ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30052
80775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3005280775
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1929444377
Short name T2728
Test name
Test status
Simulation time 157092567 ps
CPU time 0.74 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206820 kb
Host smart-2586f692-9648-4f75-9470-9a890b5783a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19294
44377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1929444377
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.396167224
Short name T2449
Test name
Test status
Simulation time 201207436 ps
CPU time 0.91 seconds
Started Jul 15 07:07:46 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206824 kb
Host smart-b46f1772-ccb6-4371-85a7-21edeeb065df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
7224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.396167224
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2516077160
Short name T1094
Test name
Test status
Simulation time 5677551626 ps
CPU time 49.33 seconds
Started Jul 15 07:08:03 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 207068 kb
Host smart-1328a0e1-86f5-420c-815d-81b0f65c7ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
77160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2516077160
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1906638139
Short name T352
Test name
Test status
Simulation time 206019829 ps
CPU time 0.96 seconds
Started Jul 15 07:07:49 PM PDT 24
Finished Jul 15 07:08:02 PM PDT 24
Peak memory 206968 kb
Host smart-0910b0cd-00b7-485b-a485-c0634c80efb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19066
38139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1906638139
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3048401422
Short name T574
Test name
Test status
Simulation time 23329168531 ps
CPU time 25.59 seconds
Started Jul 15 07:07:59 PM PDT 24
Finished Jul 15 07:08:30 PM PDT 24
Peak memory 206904 kb
Host smart-64fa6e9f-1cdc-4224-a1e9-68e3325b64f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30484
01422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3048401422
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3566846440
Short name T285
Test name
Test status
Simulation time 3352922294 ps
CPU time 4.32 seconds
Started Jul 15 07:08:01 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 206856 kb
Host smart-0938a401-b7ce-4960-8d29-853c9537724a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35668
46440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3566846440
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.3574729062
Short name T1492
Test name
Test status
Simulation time 10134074938 ps
CPU time 288.59 seconds
Started Jul 15 07:08:01 PM PDT 24
Finished Jul 15 07:12:54 PM PDT 24
Peak memory 207104 kb
Host smart-5712d90d-8a81-4439-b5b7-cdbbc3a68f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35747
29062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.3574729062
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.519902825
Short name T288
Test name
Test status
Simulation time 5839346595 ps
CPU time 42.52 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:43 PM PDT 24
Peak memory 207032 kb
Host smart-439c5177-7085-4a90-a81e-c6eb5f86c6a9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=519902825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.519902825
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3282895302
Short name T2591
Test name
Test status
Simulation time 237561364 ps
CPU time 0.97 seconds
Started Jul 15 07:08:04 PM PDT 24
Finished Jul 15 07:08:07 PM PDT 24
Peak memory 206820 kb
Host smart-29eee398-2893-401b-ba5c-7bcbd22c5a42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3282895302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3282895302
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.377246197
Short name T1866
Test name
Test status
Simulation time 211324121 ps
CPU time 0.85 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206800 kb
Host smart-2cdd22a9-3587-4aea-82b2-1588c696bedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37724
6197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.377246197
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2479227385
Short name T140
Test name
Test status
Simulation time 3337660396 ps
CPU time 23.26 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:24 PM PDT 24
Peak memory 207056 kb
Host smart-b28d8845-7d12-4ffa-9217-997d45d77419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24792
27385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2479227385
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1530640047
Short name T423
Test name
Test status
Simulation time 5326410717 ps
CPU time 53.65 seconds
Started Jul 15 07:07:46 PM PDT 24
Finished Jul 15 07:08:52 PM PDT 24
Peak memory 206988 kb
Host smart-a6bbefa2-ed21-4707-b4e7-406170443c03
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1530640047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1530640047
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3770976295
Short name T2214
Test name
Test status
Simulation time 153904998 ps
CPU time 0.8 seconds
Started Jul 15 07:07:53 PM PDT 24
Finished Jul 15 07:08:03 PM PDT 24
Peak memory 206812 kb
Host smart-102a4976-ab6b-4fb9-9350-f63473f50a5e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3770976295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3770976295
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1317754530
Short name T1258
Test name
Test status
Simulation time 144887291 ps
CPU time 0.73 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206804 kb
Host smart-62483162-842a-4989-a909-a18ed4d511b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13177
54530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1317754530
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2875001488
Short name T2719
Test name
Test status
Simulation time 172690508 ps
CPU time 0.77 seconds
Started Jul 15 07:07:49 PM PDT 24
Finished Jul 15 07:08:02 PM PDT 24
Peak memory 206824 kb
Host smart-9b8685db-d75a-4bdb-818f-b92246e43216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28750
01488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2875001488
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1531435801
Short name T1913
Test name
Test status
Simulation time 148109075 ps
CPU time 0.79 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206824 kb
Host smart-b140b0c7-6f4c-4a68-a941-ae8c806b279d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15314
35801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1531435801
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.4205155289
Short name T305
Test name
Test status
Simulation time 151977375 ps
CPU time 0.79 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206792 kb
Host smart-8da11888-ea01-4bc9-af9f-3ed07d2b8b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42051
55289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.4205155289
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.419810552
Short name T1600
Test name
Test status
Simulation time 172348941 ps
CPU time 0.82 seconds
Started Jul 15 07:07:57 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206788 kb
Host smart-efcebc50-940f-4ead-a52a-fb3cc7d246df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41981
0552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.419810552
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1506962014
Short name T850
Test name
Test status
Simulation time 152189060 ps
CPU time 0.78 seconds
Started Jul 15 07:07:50 PM PDT 24
Finished Jul 15 07:08:02 PM PDT 24
Peak memory 206832 kb
Host smart-22f8fd82-e2f2-4fad-9108-acb25b14891f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15069
62014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1506962014
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3309715596
Short name T2425
Test name
Test status
Simulation time 220815333 ps
CPU time 0.95 seconds
Started Jul 15 07:07:59 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206824 kb
Host smart-fe235527-adda-4dd4-b2ae-f481cd02db0f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3309715596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3309715596
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.48502218
Short name T2504
Test name
Test status
Simulation time 138660805 ps
CPU time 0.75 seconds
Started Jul 15 07:07:55 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206812 kb
Host smart-cb361593-a8c9-48c8-9feb-cefccdc1df45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48502
218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.48502218
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1625658693
Short name T1138
Test name
Test status
Simulation time 104188512 ps
CPU time 0.7 seconds
Started Jul 15 07:07:57 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206780 kb
Host smart-2d3961b2-01d3-46f7-aaae-e9a5cca854ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
58693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1625658693
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3737925185
Short name T233
Test name
Test status
Simulation time 5763195783 ps
CPU time 13.08 seconds
Started Jul 15 07:07:59 PM PDT 24
Finished Jul 15 07:08:17 PM PDT 24
Peak memory 207036 kb
Host smart-508ac12d-a0a1-4ade-9642-6209427a0b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37379
25185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3737925185
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.743061118
Short name T350
Test name
Test status
Simulation time 162877207 ps
CPU time 0.82 seconds
Started Jul 15 07:08:00 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206812 kb
Host smart-7116c154-ffd3-421b-8b47-478f4bcae9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74306
1118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.743061118
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.10267768
Short name T1514
Test name
Test status
Simulation time 192586220 ps
CPU time 0.87 seconds
Started Jul 15 07:07:48 PM PDT 24
Finished Jul 15 07:08:01 PM PDT 24
Peak memory 206784 kb
Host smart-f2e99ada-0383-4313-b04b-d690d6f3e3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10267
768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.10267768
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.871405128
Short name T1450
Test name
Test status
Simulation time 181426414 ps
CPU time 0.83 seconds
Started Jul 15 07:07:59 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206792 kb
Host smart-8e7a6a7e-802f-4450-8351-d511a9f42c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87140
5128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.871405128
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.3981590754
Short name T2210
Test name
Test status
Simulation time 225345925 ps
CPU time 0.96 seconds
Started Jul 15 07:07:47 PM PDT 24
Finished Jul 15 07:08:00 PM PDT 24
Peak memory 206828 kb
Host smart-a03edad1-d04e-4669-bdc6-436ba6e1ab97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39815
90754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3981590754
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3609819782
Short name T533
Test name
Test status
Simulation time 139169937 ps
CPU time 0.74 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 206776 kb
Host smart-c5af9a89-8331-4e3d-ad2a-3f6562e207f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
19782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3609819782
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3402612554
Short name T2270
Test name
Test status
Simulation time 160463369 ps
CPU time 0.82 seconds
Started Jul 15 07:07:58 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206784 kb
Host smart-03cf71ea-628b-4156-ba94-948120c13532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34026
12554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3402612554
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1377298197
Short name T661
Test name
Test status
Simulation time 168612578 ps
CPU time 0.81 seconds
Started Jul 15 07:08:05 PM PDT 24
Finished Jul 15 07:08:07 PM PDT 24
Peak memory 206824 kb
Host smart-94f906f6-33d0-48da-8f33-de60a354ff79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13772
98197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1377298197
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3314609699
Short name T1456
Test name
Test status
Simulation time 236837692 ps
CPU time 0.95 seconds
Started Jul 15 07:07:56 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206820 kb
Host smart-98df0d2f-d1b7-4df8-9a19-0c1d8ba18f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
09699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3314609699
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.120289067
Short name T1927
Test name
Test status
Simulation time 6145521912 ps
CPU time 60.84 seconds
Started Jul 15 07:07:54 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 207032 kb
Host smart-35ac3fb2-d6de-468e-95b0-fec7924ea427
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=120289067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.120289067
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3894185326
Short name T304
Test name
Test status
Simulation time 226931403 ps
CPU time 0.9 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:08 PM PDT 24
Peak memory 206748 kb
Host smart-ad041ca6-e469-49c5-afd8-6980323edc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38941
85326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3894185326
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3859021602
Short name T806
Test name
Test status
Simulation time 213221031 ps
CPU time 0.81 seconds
Started Jul 15 07:08:01 PM PDT 24
Finished Jul 15 07:08:06 PM PDT 24
Peak memory 206820 kb
Host smart-8eb8d2dc-5f02-455f-8bf5-0391c72feaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38590
21602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3859021602
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.279800804
Short name T2099
Test name
Test status
Simulation time 1058830400 ps
CPU time 2.17 seconds
Started Jul 15 07:07:58 PM PDT 24
Finished Jul 15 07:08:06 PM PDT 24
Peak memory 207024 kb
Host smart-48b34f7c-5569-40b2-a8de-b8e72533498b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27980
0804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.279800804
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.3792259476
Short name T2573
Test name
Test status
Simulation time 7524106105 ps
CPU time 206.83 seconds
Started Jul 15 07:07:56 PM PDT 24
Finished Jul 15 07:11:30 PM PDT 24
Peak memory 207016 kb
Host smart-86fba578-cff4-452e-a3be-0e830b992729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37922
59476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3792259476
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.189717357
Short name T616
Test name
Test status
Simulation time 58814314 ps
CPU time 0.74 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 206884 kb
Host smart-73dd3185-19a4-43a1-a647-0556e3772226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=189717357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.189717357
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2950045302
Short name T1790
Test name
Test status
Simulation time 4263673168 ps
CPU time 4.83 seconds
Started Jul 15 07:08:06 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 207064 kb
Host smart-d6085e2a-855d-4902-9382-fc9e72389577
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2950045302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2950045302
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3174140167
Short name T622
Test name
Test status
Simulation time 13343219722 ps
CPU time 12.81 seconds
Started Jul 15 07:07:59 PM PDT 24
Finished Jul 15 07:08:17 PM PDT 24
Peak memory 206880 kb
Host smart-a94bbee5-fbdf-45e6-8541-ce84cf99dbdf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3174140167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3174140167
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3410670142
Short name T984
Test name
Test status
Simulation time 23472956550 ps
CPU time 27.21 seconds
Started Jul 15 07:07:54 PM PDT 24
Finished Jul 15 07:08:30 PM PDT 24
Peak memory 207080 kb
Host smart-0a510955-435d-4ab9-bdf1-486b00b2ba48
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3410670142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.3410670142
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4133085190
Short name T930
Test name
Test status
Simulation time 196376717 ps
CPU time 0.88 seconds
Started Jul 15 07:07:58 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206796 kb
Host smart-33eb0554-7b21-4add-8b63-f386a30776d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41330
85190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4133085190
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3371915641
Short name T2594
Test name
Test status
Simulation time 144628545 ps
CPU time 0.8 seconds
Started Jul 15 07:07:57 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206792 kb
Host smart-09448d40-1d9f-443d-bb68-bf38d0a36b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33719
15641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3371915641
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.162540192
Short name T2204
Test name
Test status
Simulation time 1456325302 ps
CPU time 3.39 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 206964 kb
Host smart-4b5165e7-283a-4a33-9b24-6b6d27da0901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16254
0192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.162540192
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.2143276102
Short name T710
Test name
Test status
Simulation time 14472572305 ps
CPU time 26.33 seconds
Started Jul 15 07:08:01 PM PDT 24
Finished Jul 15 07:08:31 PM PDT 24
Peak memory 207012 kb
Host smart-b6fba7a7-fdf1-4792-a953-94cc3a3012fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21432
76102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.2143276102
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2169383761
Short name T1679
Test name
Test status
Simulation time 415177373 ps
CPU time 1.27 seconds
Started Jul 15 07:07:57 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206828 kb
Host smart-9259b912-cbe0-4ecf-a555-8b23280c06e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
83761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2169383761
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2188012920
Short name T1798
Test name
Test status
Simulation time 142802619 ps
CPU time 0.79 seconds
Started Jul 15 07:07:57 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206812 kb
Host smart-2d23ce67-2dc1-4326-8add-2fff3f2d66ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21880
12920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2188012920
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2510627452
Short name T1068
Test name
Test status
Simulation time 43278700 ps
CPU time 0.73 seconds
Started Jul 15 07:07:57 PM PDT 24
Finished Jul 15 07:08:04 PM PDT 24
Peak memory 206832 kb
Host smart-16b8cede-33af-45d2-8f31-aa23f61cef8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25106
27452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2510627452
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1854994385
Short name T2015
Test name
Test status
Simulation time 927521127 ps
CPU time 2.21 seconds
Started Jul 15 07:08:05 PM PDT 24
Finished Jul 15 07:08:08 PM PDT 24
Peak memory 207012 kb
Host smart-847e798b-a94a-4c35-91a9-c460a167a54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18549
94385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1854994385
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.880566641
Short name T765
Test name
Test status
Simulation time 248050803 ps
CPU time 1.5 seconds
Started Jul 15 07:07:55 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206956 kb
Host smart-dd67c6b2-f823-468d-86f1-114c854eca5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88056
6641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.880566641
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1225868476
Short name T2227
Test name
Test status
Simulation time 217369764 ps
CPU time 0.9 seconds
Started Jul 15 07:07:57 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206812 kb
Host smart-5cd78556-4a0e-408f-bf7f-1c3780422442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12258
68476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1225868476
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.199726809
Short name T1888
Test name
Test status
Simulation time 152948075 ps
CPU time 0.79 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 206820 kb
Host smart-b90630fe-f506-4e4b-bd48-1216ecce0ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
6809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.199726809
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1382663867
Short name T592
Test name
Test status
Simulation time 190803081 ps
CPU time 0.85 seconds
Started Jul 15 07:07:59 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206832 kb
Host smart-c2a214f5-1270-4ae7-b302-2ec4bd1def5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13826
63867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1382663867
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1504125540
Short name T932
Test name
Test status
Simulation time 205273599 ps
CPU time 0.88 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 206784 kb
Host smart-5ec056d1-1bbd-440b-8098-a010356fe150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15041
25540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1504125540
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.4172078421
Short name T447
Test name
Test status
Simulation time 23271540264 ps
CPU time 21.07 seconds
Started Jul 15 07:08:05 PM PDT 24
Finished Jul 15 07:08:28 PM PDT 24
Peak memory 206872 kb
Host smart-104c4ea5-886e-4144-99ba-995da306350a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
78421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.4172078421
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2851789575
Short name T205
Test name
Test status
Simulation time 3266529884 ps
CPU time 3.99 seconds
Started Jul 15 07:08:09 PM PDT 24
Finished Jul 15 07:08:14 PM PDT 24
Peak memory 206900 kb
Host smart-de4c5d56-5a8b-4466-a19e-5079d56830f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28517
89575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2851789575
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2791740789
Short name T1578
Test name
Test status
Simulation time 5413959999 ps
CPU time 51.85 seconds
Started Jul 15 07:08:01 PM PDT 24
Finished Jul 15 07:08:57 PM PDT 24
Peak memory 207056 kb
Host smart-c3161c43-88c1-4ed0-9623-3bc2ed30966b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27917
40789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2791740789
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.687163942
Short name T802
Test name
Test status
Simulation time 4724373471 ps
CPU time 45.34 seconds
Started Jul 15 07:08:08 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 207012 kb
Host smart-a3c1e5c9-da58-429b-9709-5e4d120ce426
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=687163942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.687163942
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2459539950
Short name T317
Test name
Test status
Simulation time 279246835 ps
CPU time 0.94 seconds
Started Jul 15 07:08:10 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 206800 kb
Host smart-ab3221eb-9cd4-4319-afd7-0be1125343d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2459539950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2459539950
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.374463195
Short name T2060
Test name
Test status
Simulation time 201102520 ps
CPU time 0.9 seconds
Started Jul 15 07:08:01 PM PDT 24
Finished Jul 15 07:08:06 PM PDT 24
Peak memory 206808 kb
Host smart-f7584908-d285-4859-a42d-ebd9ad529aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37446
3195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.374463195
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1460022620
Short name T2071
Test name
Test status
Simulation time 6242192922 ps
CPU time 58.47 seconds
Started Jul 15 07:08:09 PM PDT 24
Finished Jul 15 07:09:08 PM PDT 24
Peak memory 206944 kb
Host smart-47a59033-1dd3-4499-bf3a-eeb0a6d3ff58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14600
22620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1460022620
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.1847742805
Short name T1897
Test name
Test status
Simulation time 3369082303 ps
CPU time 31.38 seconds
Started Jul 15 07:08:08 PM PDT 24
Finished Jul 15 07:08:40 PM PDT 24
Peak memory 207036 kb
Host smart-7a8453f3-1bac-4f9a-8d6f-ebabdcf041cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1847742805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.1847742805
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1944539391
Short name T1643
Test name
Test status
Simulation time 151163070 ps
CPU time 0.77 seconds
Started Jul 15 07:08:09 PM PDT 24
Finished Jul 15 07:08:10 PM PDT 24
Peak memory 206836 kb
Host smart-9f3da207-ee1e-4a0e-9e34-310c652fba13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1944539391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1944539391
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1419831741
Short name T290
Test name
Test status
Simulation time 143654796 ps
CPU time 0.73 seconds
Started Jul 15 07:07:59 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206796 kb
Host smart-45019bd5-b391-4542-a842-2b2ba1ebc5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14198
31741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1419831741
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3026760365
Short name T120
Test name
Test status
Simulation time 241893115 ps
CPU time 0.99 seconds
Started Jul 15 07:08:01 PM PDT 24
Finished Jul 15 07:08:06 PM PDT 24
Peak memory 206808 kb
Host smart-98413578-8c0f-4bd0-a489-3f782c47a137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267
60365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3026760365
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.775547295
Short name T1847
Test name
Test status
Simulation time 198959554 ps
CPU time 0.81 seconds
Started Jul 15 07:08:04 PM PDT 24
Finished Jul 15 07:08:07 PM PDT 24
Peak memory 206808 kb
Host smart-868df7e2-a0e0-483d-9c93-f58d9f0eab5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77554
7295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.775547295
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4051116458
Short name T1746
Test name
Test status
Simulation time 165585531 ps
CPU time 0.79 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 206820 kb
Host smart-fd0dbd19-1a69-4d23-9c6b-b159842ce6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511
16458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4051116458
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1794900497
Short name T93
Test name
Test status
Simulation time 148569211 ps
CPU time 0.76 seconds
Started Jul 15 07:08:12 PM PDT 24
Finished Jul 15 07:08:14 PM PDT 24
Peak memory 206816 kb
Host smart-6605309b-2f3f-4b35-aae7-f482b8dd78a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17949
00497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1794900497
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3091542953
Short name T2306
Test name
Test status
Simulation time 151738562 ps
CPU time 0.76 seconds
Started Jul 15 07:07:59 PM PDT 24
Finished Jul 15 07:08:05 PM PDT 24
Peak memory 206984 kb
Host smart-47907053-b368-4c06-8667-63756fa58440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30915
42953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3091542953
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3798432831
Short name T1586
Test name
Test status
Simulation time 266715398 ps
CPU time 1.03 seconds
Started Jul 15 07:08:02 PM PDT 24
Finished Jul 15 07:08:06 PM PDT 24
Peak memory 206784 kb
Host smart-7432e409-5b41-46e2-989e-e04a52041930
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3798432831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3798432831
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.4086408608
Short name T507
Test name
Test status
Simulation time 138584828 ps
CPU time 0.77 seconds
Started Jul 15 07:08:12 PM PDT 24
Finished Jul 15 07:08:14 PM PDT 24
Peak memory 206792 kb
Host smart-704fd531-4fdd-4dfb-aa7d-3c185eab761a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40864
08608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.4086408608
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3986006065
Short name T1967
Test name
Test status
Simulation time 37461325 ps
CPU time 0.66 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 206804 kb
Host smart-923727c3-6901-428a-9791-cc33f3acad27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39860
06065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3986006065
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.527210116
Short name T2136
Test name
Test status
Simulation time 8109444466 ps
CPU time 17.72 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:25 PM PDT 24
Peak memory 207096 kb
Host smart-6ac86779-a519-4b5a-a2ec-4567fca57fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52721
0116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.527210116
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2671585386
Short name T2277
Test name
Test status
Simulation time 200150693 ps
CPU time 0.84 seconds
Started Jul 15 07:08:08 PM PDT 24
Finished Jul 15 07:08:10 PM PDT 24
Peak memory 206824 kb
Host smart-989b1cb5-02c4-419b-90dd-14e51e62dd1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26715
85386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2671585386
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2629298424
Short name T384
Test name
Test status
Simulation time 226384407 ps
CPU time 0.87 seconds
Started Jul 15 07:08:13 PM PDT 24
Finished Jul 15 07:08:15 PM PDT 24
Peak memory 206836 kb
Host smart-a1e3beb7-5927-4d5c-8e2b-79b4287288bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26292
98424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2629298424
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.179335371
Short name T2374
Test name
Test status
Simulation time 186160536 ps
CPU time 0.82 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 206836 kb
Host smart-223bb816-6763-406e-83c1-d9dcd30c0bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933
5371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.179335371
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1467354819
Short name T514
Test name
Test status
Simulation time 157020540 ps
CPU time 0.77 seconds
Started Jul 15 07:08:10 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 206808 kb
Host smart-10c4a0b5-9a72-4144-9f45-942274a5d96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14673
54819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1467354819
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2174470694
Short name T1691
Test name
Test status
Simulation time 201084269 ps
CPU time 0.83 seconds
Started Jul 15 07:08:12 PM PDT 24
Finished Jul 15 07:08:14 PM PDT 24
Peak memory 206824 kb
Host smart-c07aff38-b7cf-4feb-9251-b8ccdfcdeeab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21744
70694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2174470694
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4262909972
Short name T1269
Test name
Test status
Simulation time 193982142 ps
CPU time 0.84 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:09 PM PDT 24
Peak memory 206056 kb
Host smart-3f04b2e0-23ae-40fa-9d6d-1e4636d78c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42629
09972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4262909972
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3743610198
Short name T1462
Test name
Test status
Simulation time 177821218 ps
CPU time 0.81 seconds
Started Jul 15 07:08:09 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 206828 kb
Host smart-358f7528-c2ac-4703-ae78-8c964b0a77d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37436
10198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3743610198
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3788226592
Short name T1130
Test name
Test status
Simulation time 235179638 ps
CPU time 1.03 seconds
Started Jul 15 07:08:06 PM PDT 24
Finished Jul 15 07:08:08 PM PDT 24
Peak memory 206800 kb
Host smart-85023313-12fb-4b79-abb5-008082355659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37882
26592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3788226592
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3752971875
Short name T1423
Test name
Test status
Simulation time 3129581312 ps
CPU time 24.25 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:32 PM PDT 24
Peak memory 206280 kb
Host smart-3be301fa-8745-4142-8e6e-e873075d05cf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3752971875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3752971875
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2789857977
Short name T1952
Test name
Test status
Simulation time 178627879 ps
CPU time 0.84 seconds
Started Jul 15 07:08:05 PM PDT 24
Finished Jul 15 07:08:08 PM PDT 24
Peak memory 206828 kb
Host smart-93da4d66-593b-40ba-9c40-89211fabd09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27898
57977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2789857977
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1410797317
Short name T1035
Test name
Test status
Simulation time 154587794 ps
CPU time 0.8 seconds
Started Jul 15 07:08:10 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 206816 kb
Host smart-32fa9d12-73f9-46cb-9451-16e798f69840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14107
97317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1410797317
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.3926495577
Short name T386
Test name
Test status
Simulation time 1143284603 ps
CPU time 2.41 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 206968 kb
Host smart-df2cf795-1d67-4f9f-bdbd-9c01512fbd84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39264
95577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.3926495577
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.207998578
Short name T2065
Test name
Test status
Simulation time 4178351805 ps
CPU time 39.76 seconds
Started Jul 15 07:08:09 PM PDT 24
Finished Jul 15 07:08:49 PM PDT 24
Peak memory 207092 kb
Host smart-cb428c21-1e4f-49ff-8cdf-9140122a5bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20799
8578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.207998578
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.555400222
Short name T393
Test name
Test status
Simulation time 88487480 ps
CPU time 0.73 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:20 PM PDT 24
Peak memory 206884 kb
Host smart-e72aa7fd-8924-4b3d-a62b-f1bf359601d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=555400222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.555400222
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2817736249
Short name T1374
Test name
Test status
Simulation time 4360133794 ps
CPU time 5.68 seconds
Started Jul 15 07:08:05 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 207052 kb
Host smart-2e4caea2-cc30-4fea-af8b-2da19083593a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2817736249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2817736249
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2934576405
Short name T1781
Test name
Test status
Simulation time 13357549075 ps
CPU time 12.36 seconds
Started Jul 15 07:08:06 PM PDT 24
Finished Jul 15 07:08:20 PM PDT 24
Peak memory 207032 kb
Host smart-57c564b5-8289-4823-9b6e-7ae4f639fdf1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2934576405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2934576405
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.4005679008
Short name T1906
Test name
Test status
Simulation time 23386495842 ps
CPU time 30.45 seconds
Started Jul 15 07:08:07 PM PDT 24
Finished Jul 15 07:08:39 PM PDT 24
Peak memory 206900 kb
Host smart-a006f271-fcff-4a7f-900c-66e59091c4c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4005679008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.4005679008
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.115008576
Short name T1849
Test name
Test status
Simulation time 207271523 ps
CPU time 0.83 seconds
Started Jul 15 07:08:08 PM PDT 24
Finished Jul 15 07:08:10 PM PDT 24
Peak memory 206808 kb
Host smart-3a7e346a-871c-4f1b-a6a8-b01e69477271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11500
8576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.115008576
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2028194840
Short name T2595
Test name
Test status
Simulation time 159361671 ps
CPU time 0.76 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 206836 kb
Host smart-14557f25-40e7-4bd6-93aa-58a980ff555a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20281
94840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2028194840
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2334552678
Short name T760
Test name
Test status
Simulation time 172666214 ps
CPU time 0.85 seconds
Started Jul 15 07:08:12 PM PDT 24
Finished Jul 15 07:08:14 PM PDT 24
Peak memory 206812 kb
Host smart-3e621b1c-8c6e-47bc-a5db-5f24fa20ef1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23345
52678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2334552678
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1556362859
Short name T391
Test name
Test status
Simulation time 801932435 ps
CPU time 1.9 seconds
Started Jul 15 07:08:15 PM PDT 24
Finished Jul 15 07:08:17 PM PDT 24
Peak memory 207012 kb
Host smart-fdc9784a-1895-495d-9002-085bb4be29cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15563
62859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1556362859
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.1102229437
Short name T1743
Test name
Test status
Simulation time 21738646658 ps
CPU time 42.58 seconds
Started Jul 15 07:08:12 PM PDT 24
Finished Jul 15 07:08:56 PM PDT 24
Peak memory 207060 kb
Host smart-00054a14-fdee-44c1-9300-bcd5f7abb7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11022
29437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1102229437
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.1472645914
Short name T1580
Test name
Test status
Simulation time 446628885 ps
CPU time 1.4 seconds
Started Jul 15 07:08:10 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 206844 kb
Host smart-649a396f-c0ad-42a8-813e-0c616f985474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14726
45914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.1472645914
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1834895707
Short name T387
Test name
Test status
Simulation time 149621017 ps
CPU time 0.84 seconds
Started Jul 15 07:08:13 PM PDT 24
Finished Jul 15 07:08:15 PM PDT 24
Peak memory 206812 kb
Host smart-dbd2a94c-40be-40ef-81c4-45fd31e9bacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
95707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1834895707
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.440418415
Short name T1185
Test name
Test status
Simulation time 44615859 ps
CPU time 0.66 seconds
Started Jul 15 07:08:14 PM PDT 24
Finished Jul 15 07:08:15 PM PDT 24
Peak memory 206692 kb
Host smart-bff57df9-a8bf-4233-a048-befdf22021e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44041
8415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.440418415
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1930237812
Short name T1337
Test name
Test status
Simulation time 840570816 ps
CPU time 2.28 seconds
Started Jul 15 07:08:15 PM PDT 24
Finished Jul 15 07:08:18 PM PDT 24
Peak memory 207008 kb
Host smart-b539462f-90f5-442d-9024-469a773d67e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19302
37812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1930237812
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1845163486
Short name T1505
Test name
Test status
Simulation time 254082386 ps
CPU time 1.57 seconds
Started Jul 15 07:08:13 PM PDT 24
Finished Jul 15 07:08:16 PM PDT 24
Peak memory 207008 kb
Host smart-2458007f-b260-4605-abed-f0509945a0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18451
63486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1845163486
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3455668435
Short name T2028
Test name
Test status
Simulation time 185705027 ps
CPU time 0.87 seconds
Started Jul 15 07:08:12 PM PDT 24
Finished Jul 15 07:08:14 PM PDT 24
Peak memory 206828 kb
Host smart-12871265-07c9-43bc-a1d7-b8c3622a74dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34556
68435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3455668435
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.693815529
Short name T327
Test name
Test status
Simulation time 199953002 ps
CPU time 0.82 seconds
Started Jul 15 07:08:16 PM PDT 24
Finished Jul 15 07:08:17 PM PDT 24
Peak memory 206752 kb
Host smart-6a74bb0f-be86-42e6-95e1-fa7a058925b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69381
5529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.693815529
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.364685641
Short name T521
Test name
Test status
Simulation time 163528663 ps
CPU time 0.83 seconds
Started Jul 15 07:08:13 PM PDT 24
Finished Jul 15 07:08:15 PM PDT 24
Peak memory 206792 kb
Host smart-93b9119c-b4fa-4472-829b-cc593dc6da7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36468
5641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.364685641
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.927409365
Short name T1249
Test name
Test status
Simulation time 7815444983 ps
CPU time 56.33 seconds
Started Jul 15 07:08:17 PM PDT 24
Finished Jul 15 07:09:14 PM PDT 24
Peak memory 206972 kb
Host smart-32380208-13bf-4400-a3ea-0f484e605ee7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=927409365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.927409365
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.897419785
Short name T2049
Test name
Test status
Simulation time 13418322468 ps
CPU time 46.74 seconds
Started Jul 15 07:08:12 PM PDT 24
Finished Jul 15 07:09:00 PM PDT 24
Peak memory 206984 kb
Host smart-9f046fd4-df5c-4ea7-a2cb-d99309c1d2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89741
9785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.897419785
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3332322153
Short name T2293
Test name
Test status
Simulation time 221108450 ps
CPU time 0.88 seconds
Started Jul 15 07:08:13 PM PDT 24
Finished Jul 15 07:08:15 PM PDT 24
Peak memory 206840 kb
Host smart-655b8157-e874-4fc6-880b-92e5cf53d85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33323
22153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3332322153
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3898697007
Short name T1696
Test name
Test status
Simulation time 23335166427 ps
CPU time 30.63 seconds
Started Jul 15 07:08:15 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 206888 kb
Host smart-45048110-1c58-4c17-aa42-c682ba5b7fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38986
97007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3898697007
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1007836584
Short name T351
Test name
Test status
Simulation time 3321691980 ps
CPU time 4.73 seconds
Started Jul 15 07:08:15 PM PDT 24
Finished Jul 15 07:08:21 PM PDT 24
Peak memory 206892 kb
Host smart-c81ee099-0053-4519-93dd-b6b690c1b34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10078
36584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1007836584
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2562818050
Short name T1816
Test name
Test status
Simulation time 8138899009 ps
CPU time 61.24 seconds
Started Jul 15 07:08:12 PM PDT 24
Finished Jul 15 07:09:15 PM PDT 24
Peak memory 207068 kb
Host smart-dfc25f7d-1aef-4901-aa53-2ca13cbfea4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25628
18050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2562818050
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2880308221
Short name T1177
Test name
Test status
Simulation time 4266516193 ps
CPU time 30.05 seconds
Started Jul 15 07:08:13 PM PDT 24
Finished Jul 15 07:08:44 PM PDT 24
Peak memory 206976 kb
Host smart-25331486-d826-48e9-bdd2-22f926d824fe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2880308221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2880308221
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1869241547
Short name T2682
Test name
Test status
Simulation time 239134373 ps
CPU time 0.99 seconds
Started Jul 15 07:08:10 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 206796 kb
Host smart-88a7edcf-56ad-40fe-9117-a83081bcb7e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1869241547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1869241547
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1134381114
Short name T1570
Test name
Test status
Simulation time 187650251 ps
CPU time 0.82 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 206816 kb
Host smart-fe5ebf11-9048-4ed6-ba52-3c3f57732dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11343
81114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1134381114
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1811187013
Short name T150
Test name
Test status
Simulation time 5388536689 ps
CPU time 143.4 seconds
Started Jul 15 07:08:16 PM PDT 24
Finished Jul 15 07:10:40 PM PDT 24
Peak memory 206988 kb
Host smart-e7d99404-dc0a-4a0e-9414-8d00e9643ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18111
87013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1811187013
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1349125059
Short name T747
Test name
Test status
Simulation time 7598920433 ps
CPU time 204.88 seconds
Started Jul 15 07:08:17 PM PDT 24
Finished Jul 15 07:11:43 PM PDT 24
Peak memory 207036 kb
Host smart-adfdf989-832d-4f3d-865e-206a4b83b828
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1349125059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1349125059
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1724142365
Short name T1846
Test name
Test status
Simulation time 152085292 ps
CPU time 0.76 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 206976 kb
Host smart-fcf29cd0-bd5a-492a-828a-b0ff41a96e69
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1724142365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1724142365
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1623561420
Short name T1859
Test name
Test status
Simulation time 155306018 ps
CPU time 0.81 seconds
Started Jul 15 07:08:18 PM PDT 24
Finished Jul 15 07:08:20 PM PDT 24
Peak memory 206820 kb
Host smart-9e8152e4-800c-456a-9637-8714c735756a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16235
61420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1623561420
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2586550950
Short name T1336
Test name
Test status
Simulation time 237110579 ps
CPU time 0.98 seconds
Started Jul 15 07:08:15 PM PDT 24
Finished Jul 15 07:08:16 PM PDT 24
Peak memory 206808 kb
Host smart-09d77e2f-5132-4400-9c83-5146e5bc17de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25865
50950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2586550950
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.671108750
Short name T1092
Test name
Test status
Simulation time 209074181 ps
CPU time 0.85 seconds
Started Jul 15 07:08:15 PM PDT 24
Finished Jul 15 07:08:16 PM PDT 24
Peak memory 206844 kb
Host smart-c63e4f3c-917c-493a-8c91-95201d42ba5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67110
8750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.671108750
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3343405255
Short name T315
Test name
Test status
Simulation time 154756519 ps
CPU time 0.84 seconds
Started Jul 15 07:08:18 PM PDT 24
Finished Jul 15 07:08:19 PM PDT 24
Peak memory 206820 kb
Host smart-ad7b19d0-c120-4a1d-95ed-91186c4e1695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33434
05255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3343405255
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.992280203
Short name T2139
Test name
Test status
Simulation time 179707774 ps
CPU time 0.82 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 206836 kb
Host smart-033f0d57-19f6-4a10-ab0e-47a39284f0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99228
0203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.992280203
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.19919400
Short name T158
Test name
Test status
Simulation time 155194985 ps
CPU time 0.78 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:13 PM PDT 24
Peak memory 206828 kb
Host smart-421b0bbf-1272-4e1d-8cb9-af651e44a722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19919
400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.19919400
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.82657036
Short name T1229
Test name
Test status
Simulation time 188375389 ps
CPU time 0.85 seconds
Started Jul 15 07:08:16 PM PDT 24
Finished Jul 15 07:08:18 PM PDT 24
Peak memory 206800 kb
Host smart-4dd65ffa-1ffc-40de-b8a0-55d25666af3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=82657036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.82657036
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3383451882
Short name T524
Test name
Test status
Simulation time 174595546 ps
CPU time 0.77 seconds
Started Jul 15 07:08:11 PM PDT 24
Finished Jul 15 07:08:12 PM PDT 24
Peak memory 206784 kb
Host smart-8183dbf2-71d9-475e-a658-f0824a650c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33834
51882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3383451882
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.393736916
Short name T494
Test name
Test status
Simulation time 16043908743 ps
CPU time 39 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:58 PM PDT 24
Peak memory 207068 kb
Host smart-dbaa3da0-0003-4e15-a47e-d6d7fbeb6ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39373
6916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.393736916
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.4183985848
Short name T2398
Test name
Test status
Simulation time 171488728 ps
CPU time 0.84 seconds
Started Jul 15 07:08:17 PM PDT 24
Finished Jul 15 07:08:19 PM PDT 24
Peak memory 206776 kb
Host smart-dbdea078-d4c3-427a-b5a8-11efae6229ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41839
85848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.4183985848
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2480481519
Short name T326
Test name
Test status
Simulation time 156261979 ps
CPU time 0.87 seconds
Started Jul 15 07:08:21 PM PDT 24
Finished Jul 15 07:08:22 PM PDT 24
Peak memory 206784 kb
Host smart-cca8e47e-a52a-4350-92e9-6f96848b17a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24804
81519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2480481519
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.705569476
Short name T1060
Test name
Test status
Simulation time 229733710 ps
CPU time 0.92 seconds
Started Jul 15 07:08:18 PM PDT 24
Finished Jul 15 07:08:20 PM PDT 24
Peak memory 206796 kb
Host smart-4ac69a7f-0f1f-4331-a88f-1e6e551c1dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70556
9476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.705569476
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.3604212300
Short name T569
Test name
Test status
Simulation time 171319891 ps
CPU time 0.85 seconds
Started Jul 15 07:08:22 PM PDT 24
Finished Jul 15 07:08:23 PM PDT 24
Peak memory 206744 kb
Host smart-2bb7f2b3-cbe5-4ea1-ab63-7a01c19e3e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36042
12300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.3604212300
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1252708535
Short name T1112
Test name
Test status
Simulation time 158591536 ps
CPU time 0.85 seconds
Started Jul 15 07:08:23 PM PDT 24
Finished Jul 15 07:08:24 PM PDT 24
Peak memory 206792 kb
Host smart-cdf992dc-cc02-4f26-9cdf-d7cc893d4ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12527
08535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1252708535
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2546916890
Short name T2247
Test name
Test status
Simulation time 164562195 ps
CPU time 0.76 seconds
Started Jul 15 07:08:22 PM PDT 24
Finished Jul 15 07:08:23 PM PDT 24
Peak memory 206752 kb
Host smart-9d707799-7093-4e57-b7e6-9e69705b7bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25469
16890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2546916890
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.60093598
Short name T309
Test name
Test status
Simulation time 161444597 ps
CPU time 0.94 seconds
Started Jul 15 07:08:21 PM PDT 24
Finished Jul 15 07:08:23 PM PDT 24
Peak memory 206812 kb
Host smart-1782f73e-7233-4e3a-a955-0e03eef1fc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60093
598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.60093598
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2539731400
Short name T2606
Test name
Test status
Simulation time 239725906 ps
CPU time 0.92 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:21 PM PDT 24
Peak memory 206820 kb
Host smart-8ec421da-64d1-4e1e-951d-8745a41254be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25397
31400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2539731400
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3229436832
Short name T1281
Test name
Test status
Simulation time 6918914562 ps
CPU time 181.1 seconds
Started Jul 15 07:08:18 PM PDT 24
Finished Jul 15 07:11:20 PM PDT 24
Peak memory 207056 kb
Host smart-b77f62f9-1c8d-4572-aca4-1d46616474ba
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3229436832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3229436832
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2292912272
Short name T1862
Test name
Test status
Simulation time 172706846 ps
CPU time 0.81 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:21 PM PDT 24
Peak memory 206808 kb
Host smart-bcc8f64c-0aa2-4969-a62b-3fbbb739c61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929
12272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2292912272
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.334093904
Short name T2112
Test name
Test status
Simulation time 199891149 ps
CPU time 0.85 seconds
Started Jul 15 07:08:18 PM PDT 24
Finished Jul 15 07:08:19 PM PDT 24
Peak memory 206808 kb
Host smart-08504016-5edc-433a-98b5-91c61adfcf61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33409
3904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.334093904
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.4166831152
Short name T324
Test name
Test status
Simulation time 1254508096 ps
CPU time 2.7 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:22 PM PDT 24
Peak memory 207016 kb
Host smart-e32bff82-9934-4a52-b51c-b1d365f1eead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41668
31152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.4166831152
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.4208701409
Short name T373
Test name
Test status
Simulation time 8120330525 ps
CPU time 77.46 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:09:37 PM PDT 24
Peak memory 207008 kb
Host smart-be33f61c-a8c7-4596-ae30-001f96b52f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42087
01409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.4208701409
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.4174018329
Short name T2482
Test name
Test status
Simulation time 62440120 ps
CPU time 0.69 seconds
Started Jul 15 07:08:35 PM PDT 24
Finished Jul 15 07:08:36 PM PDT 24
Peak memory 206868 kb
Host smart-267212c5-bc48-4598-9997-e9e562f1de1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4174018329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.4174018329
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.818208107
Short name T762
Test name
Test status
Simulation time 3491390543 ps
CPU time 4.77 seconds
Started Jul 15 07:08:22 PM PDT 24
Finished Jul 15 07:08:27 PM PDT 24
Peak memory 206836 kb
Host smart-ee5632e5-18f4-408a-b5ec-43bebfca0273
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=818208107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.818208107
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.750867070
Short name T2604
Test name
Test status
Simulation time 13333898821 ps
CPU time 12.72 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:33 PM PDT 24
Peak memory 206876 kb
Host smart-543fa2cf-5e5b-46ec-800b-919f91220396
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=750867070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.750867070
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3704638846
Short name T1731
Test name
Test status
Simulation time 23322583433 ps
CPU time 23.38 seconds
Started Jul 15 07:08:22 PM PDT 24
Finished Jul 15 07:08:46 PM PDT 24
Peak memory 207028 kb
Host smart-b57a7b6e-a58e-4c89-b9c6-ad24b64a3713
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3704638846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.3704638846
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1040418277
Short name T611
Test name
Test status
Simulation time 177340879 ps
CPU time 0.8 seconds
Started Jul 15 07:08:20 PM PDT 24
Finished Jul 15 07:08:21 PM PDT 24
Peak memory 206824 kb
Host smart-9ebc09f3-5f6d-4526-ae74-ab9cedcd7602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10404
18277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1040418277
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3963579193
Short name T2260
Test name
Test status
Simulation time 179030835 ps
CPU time 0.81 seconds
Started Jul 15 07:08:21 PM PDT 24
Finished Jul 15 07:08:22 PM PDT 24
Peak memory 206792 kb
Host smart-1ab0f306-dbd3-4fa8-9986-6a9b2584fbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39635
79193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3963579193
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.437011990
Short name T2200
Test name
Test status
Simulation time 497034915 ps
CPU time 1.57 seconds
Started Jul 15 07:08:18 PM PDT 24
Finished Jul 15 07:08:20 PM PDT 24
Peak memory 206992 kb
Host smart-dab81e0f-f9b4-4d30-a503-280589c489f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43701
1990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.437011990
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1318752567
Short name T2646
Test name
Test status
Simulation time 1213728719 ps
CPU time 2.87 seconds
Started Jul 15 07:08:21 PM PDT 24
Finished Jul 15 07:08:24 PM PDT 24
Peak memory 206988 kb
Host smart-381501ed-a0f7-4226-8fc6-76fca62e6989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13187
52567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1318752567
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.894155386
Short name T1988
Test name
Test status
Simulation time 10532446368 ps
CPU time 17.84 seconds
Started Jul 15 07:08:21 PM PDT 24
Finished Jul 15 07:08:40 PM PDT 24
Peak memory 207088 kb
Host smart-690daa8d-5310-4713-8fc6-bc69a81e2661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89415
5386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.894155386
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.3717462238
Short name T988
Test name
Test status
Simulation time 155544721 ps
CPU time 0.77 seconds
Started Jul 15 07:08:22 PM PDT 24
Finished Jul 15 07:08:23 PM PDT 24
Peak memory 206816 kb
Host smart-40b70fd9-58d3-4dac-a46e-86bf3c9c61b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37174
62238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3717462238
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3141399284
Short name T469
Test name
Test status
Simulation time 49574661 ps
CPU time 0.68 seconds
Started Jul 15 07:08:19 PM PDT 24
Finished Jul 15 07:08:21 PM PDT 24
Peak memory 206816 kb
Host smart-0f740cae-c9d8-4ce8-a160-1d439b7b8757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31413
99284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3141399284
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.558483172
Short name T705
Test name
Test status
Simulation time 866237203 ps
CPU time 2.09 seconds
Started Jul 15 07:08:21 PM PDT 24
Finished Jul 15 07:08:24 PM PDT 24
Peak memory 207012 kb
Host smart-834c9f23-e83a-45f5-80fb-de0db8211e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55848
3172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.558483172
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2513807783
Short name T2243
Test name
Test status
Simulation time 180311696 ps
CPU time 1.7 seconds
Started Jul 15 07:08:23 PM PDT 24
Finished Jul 15 07:08:25 PM PDT 24
Peak memory 206996 kb
Host smart-f327fc55-ec72-44e3-9669-a86bb0022511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25138
07783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2513807783
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.280697707
Short name T905
Test name
Test status
Simulation time 233580796 ps
CPU time 0.9 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:29 PM PDT 24
Peak memory 206792 kb
Host smart-f4847034-c28c-40df-88f3-c2b5f7840fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
7707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.280697707
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1144976548
Short name T2484
Test name
Test status
Simulation time 163588666 ps
CPU time 0.81 seconds
Started Jul 15 07:08:26 PM PDT 24
Finished Jul 15 07:08:27 PM PDT 24
Peak memory 206820 kb
Host smart-ce37b1be-67c4-470c-9ab3-8409783bbf1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11449
76548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1144976548
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3136813599
Short name T1443
Test name
Test status
Simulation time 199053819 ps
CPU time 0.87 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:29 PM PDT 24
Peak memory 206808 kb
Host smart-ff9f870c-e500-4e7f-9050-822b719ca382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31368
13599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3136813599
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2565304591
Short name T1735
Test name
Test status
Simulation time 11271550095 ps
CPU time 34.7 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 207052 kb
Host smart-556c36fb-0325-4a57-8e1c-77bb892a1749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25653
04591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2565304591
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3259620716
Short name T2478
Test name
Test status
Simulation time 224833031 ps
CPU time 0.91 seconds
Started Jul 15 07:08:25 PM PDT 24
Finished Jul 15 07:08:27 PM PDT 24
Peak memory 206780 kb
Host smart-63bf3867-64fe-47d1-822c-2330985ccefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32596
20716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3259620716
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.696798319
Short name T720
Test name
Test status
Simulation time 23281371502 ps
CPU time 20.48 seconds
Started Jul 15 07:08:26 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 206904 kb
Host smart-92fb05ed-4e6d-4524-b0a8-62cbf905cf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69679
8319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.696798319
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1345442814
Short name T941
Test name
Test status
Simulation time 3319526824 ps
CPU time 4.4 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:33 PM PDT 24
Peak memory 206856 kb
Host smart-40e1acb3-2ee0-4d68-8c26-e447d714fc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13454
42814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1345442814
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1562373957
Short name T2329
Test name
Test status
Simulation time 8888088004 ps
CPU time 66.24 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:09:35 PM PDT 24
Peak memory 207072 kb
Host smart-0539d5a9-4363-4395-abd2-4884c2af52f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15623
73957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1562373957
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2739577073
Short name T2702
Test name
Test status
Simulation time 5973033012 ps
CPU time 56.5 seconds
Started Jul 15 07:08:25 PM PDT 24
Finished Jul 15 07:09:22 PM PDT 24
Peak memory 207020 kb
Host smart-e02649fe-9f52-4625-ac27-d4b9743dc178
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2739577073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2739577073
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1821529173
Short name T331
Test name
Test status
Simulation time 249777488 ps
CPU time 1 seconds
Started Jul 15 07:08:26 PM PDT 24
Finished Jul 15 07:08:28 PM PDT 24
Peak memory 206840 kb
Host smart-64459756-933a-416b-bb3f-5044f90e7e9f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1821529173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1821529173
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3704401396
Short name T298
Test name
Test status
Simulation time 185273825 ps
CPU time 0.9 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:28 PM PDT 24
Peak memory 206812 kb
Host smart-19feda83-9513-416e-8a09-da5bc4d0fec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37044
01396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3704401396
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1530806038
Short name T1209
Test name
Test status
Simulation time 4238097616 ps
CPU time 41.34 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:09:09 PM PDT 24
Peak memory 207008 kb
Host smart-5a9b997e-eea2-492c-8544-98634f101500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15308
06038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1530806038
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.4140491957
Short name T1317
Test name
Test status
Simulation time 5083165665 ps
CPU time 134.03 seconds
Started Jul 15 07:08:25 PM PDT 24
Finished Jul 15 07:10:40 PM PDT 24
Peak memory 207056 kb
Host smart-134d1774-5453-40f4-a282-04247ebd9508
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4140491957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.4140491957
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3424843533
Short name T754
Test name
Test status
Simulation time 174261083 ps
CPU time 0.84 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:29 PM PDT 24
Peak memory 206824 kb
Host smart-44e52aca-1d08-484c-8532-55664bc65dff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3424843533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3424843533
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.652183266
Short name T753
Test name
Test status
Simulation time 180181422 ps
CPU time 0.89 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:29 PM PDT 24
Peak memory 206784 kb
Host smart-981c41ba-dc7f-4ca5-89b6-e8911d9b6c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65218
3266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.652183266
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.801499794
Short name T108
Test name
Test status
Simulation time 220790029 ps
CPU time 0.92 seconds
Started Jul 15 07:08:26 PM PDT 24
Finished Jul 15 07:08:27 PM PDT 24
Peak memory 206700 kb
Host smart-59b7c85f-2997-44d7-9bd1-b9ff88929730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80149
9794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.801499794
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2640340187
Short name T2685
Test name
Test status
Simulation time 189589885 ps
CPU time 1.03 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:29 PM PDT 24
Peak memory 206832 kb
Host smart-1a8cdf05-4e47-4d9c-8559-eb1213543efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26403
40187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2640340187
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3115996676
Short name T1829
Test name
Test status
Simulation time 245476926 ps
CPU time 0.9 seconds
Started Jul 15 07:08:26 PM PDT 24
Finished Jul 15 07:08:27 PM PDT 24
Peak memory 206756 kb
Host smart-c208e229-95ee-48fa-a98b-a5e73608bfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31159
96676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3115996676
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2920741350
Short name T1546
Test name
Test status
Simulation time 158313822 ps
CPU time 0.85 seconds
Started Jul 15 07:08:28 PM PDT 24
Finished Jul 15 07:08:30 PM PDT 24
Peak memory 206972 kb
Host smart-b8a5eb8d-5dab-48a5-b1ba-fb4260b9c599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207
41350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2920741350
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3718734278
Short name T2222
Test name
Test status
Simulation time 173139374 ps
CPU time 0.79 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:29 PM PDT 24
Peak memory 206812 kb
Host smart-3ab72ecd-4f5c-4cd7-a5d8-b0e3a5e88a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37187
34278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3718734278
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.4034396012
Short name T2196
Test name
Test status
Simulation time 270923317 ps
CPU time 0.96 seconds
Started Jul 15 07:08:27 PM PDT 24
Finished Jul 15 07:08:29 PM PDT 24
Peak memory 206796 kb
Host smart-9b8a2f84-f55a-413b-b573-c0b7038418a8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4034396012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.4034396012
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.446769135
Short name T1090
Test name
Test status
Simulation time 160204269 ps
CPU time 0.74 seconds
Started Jul 15 07:08:24 PM PDT 24
Finished Jul 15 07:08:25 PM PDT 24
Peak memory 206824 kb
Host smart-cf5d2ea7-ea9d-4600-85b3-d15438fd8f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44676
9135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.446769135
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.39961534
Short name T25
Test name
Test status
Simulation time 33320898 ps
CPU time 0.71 seconds
Started Jul 15 07:08:26 PM PDT 24
Finished Jul 15 07:08:27 PM PDT 24
Peak memory 206824 kb
Host smart-b0a5dc9c-1f79-4126-aaa6-62118e8ec349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39961
534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.39961534
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3412121921
Short name T1936
Test name
Test status
Simulation time 14492149704 ps
CPU time 35.73 seconds
Started Jul 15 07:08:35 PM PDT 24
Finished Jul 15 07:09:11 PM PDT 24
Peak memory 207144 kb
Host smart-4a884df3-40c1-4994-946f-842abdf72f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34121
21921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3412121921
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.944139641
Short name T824
Test name
Test status
Simulation time 205162895 ps
CPU time 0.87 seconds
Started Jul 15 07:08:32 PM PDT 24
Finished Jul 15 07:08:34 PM PDT 24
Peak memory 206812 kb
Host smart-02e2e4a6-1646-4482-ac2c-b4778c3c6f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94413
9641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.944139641
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3449100817
Short name T1041
Test name
Test status
Simulation time 217051593 ps
CPU time 0.92 seconds
Started Jul 15 07:08:33 PM PDT 24
Finished Jul 15 07:08:35 PM PDT 24
Peak memory 206764 kb
Host smart-49f1fd46-a514-49b5-8303-a213f42f374e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
00817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3449100817
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2335707532
Short name T1466
Test name
Test status
Simulation time 165190267 ps
CPU time 0.8 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206764 kb
Host smart-c1ec59a6-31a6-41cf-96ef-a86478c7eb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23357
07532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2335707532
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3757518774
Short name T557
Test name
Test status
Simulation time 182830293 ps
CPU time 0.83 seconds
Started Jul 15 07:08:34 PM PDT 24
Finished Jul 15 07:08:36 PM PDT 24
Peak memory 206832 kb
Host smart-0793354a-8961-4d64-98ba-269a1d3195c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37575
18774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3757518774
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2423496529
Short name T2418
Test name
Test status
Simulation time 220489679 ps
CPU time 0.92 seconds
Started Jul 15 07:08:33 PM PDT 24
Finished Jul 15 07:08:34 PM PDT 24
Peak memory 206824 kb
Host smart-913bc1f9-2aeb-40c3-8ba1-d017f60d1a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24234
96529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2423496529
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.578321081
Short name T582
Test name
Test status
Simulation time 178127796 ps
CPU time 0.78 seconds
Started Jul 15 07:08:39 PM PDT 24
Finished Jul 15 07:08:40 PM PDT 24
Peak memory 206788 kb
Host smart-fad15184-1665-4289-a1c9-0d2f7c55a931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57832
1081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.578321081
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1070542776
Short name T1375
Test name
Test status
Simulation time 163590145 ps
CPU time 0.78 seconds
Started Jul 15 07:08:32 PM PDT 24
Finished Jul 15 07:08:34 PM PDT 24
Peak memory 206824 kb
Host smart-fcfb0338-3268-462c-9ff8-ed05139a33d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
42776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1070542776
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.904419562
Short name T2006
Test name
Test status
Simulation time 203273314 ps
CPU time 0.9 seconds
Started Jul 15 07:08:33 PM PDT 24
Finished Jul 15 07:08:35 PM PDT 24
Peak memory 206808 kb
Host smart-ada76474-e290-4190-94af-5d19a3876802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90441
9562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.904419562
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.608796447
Short name T1506
Test name
Test status
Simulation time 3537907064 ps
CPU time 26.99 seconds
Started Jul 15 07:08:39 PM PDT 24
Finished Jul 15 07:09:07 PM PDT 24
Peak memory 207092 kb
Host smart-76184a54-b97e-40c9-a99d-fb1a97cb6bbc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=608796447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.608796447
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.464227557
Short name T2331
Test name
Test status
Simulation time 161356011 ps
CPU time 0.77 seconds
Started Jul 15 07:08:36 PM PDT 24
Finished Jul 15 07:08:38 PM PDT 24
Peak memory 206816 kb
Host smart-e7748907-b6c9-4e93-8fef-44c1e9aa890a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46422
7557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.464227557
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.536518588
Short name T359
Test name
Test status
Simulation time 177534092 ps
CPU time 0.8 seconds
Started Jul 15 07:08:33 PM PDT 24
Finished Jul 15 07:08:35 PM PDT 24
Peak memory 206764 kb
Host smart-679181b0-5dce-4afc-aebe-69e24b9fb1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53651
8588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.536518588
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1728932872
Short name T2535
Test name
Test status
Simulation time 196200380 ps
CPU time 0.89 seconds
Started Jul 15 07:08:36 PM PDT 24
Finished Jul 15 07:08:37 PM PDT 24
Peak memory 206760 kb
Host smart-e60b8ed7-dbd1-4696-aace-3a5b7279c66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
32872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1728932872
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1986499470
Short name T1814
Test name
Test status
Simulation time 3110788754 ps
CPU time 85.38 seconds
Started Jul 15 07:08:32 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 207100 kb
Host smart-c2b3e9c5-43e1-4ddb-bd87-477eaf7021c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19864
99470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1986499470
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.803841274
Short name T1372
Test name
Test status
Simulation time 35676868 ps
CPU time 0.68 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206840 kb
Host smart-b8e22141-5dec-4d31-bd08-1c0549adab57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=803841274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.803841274
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3856442376
Short name T1454
Test name
Test status
Simulation time 3525452121 ps
CPU time 4.21 seconds
Started Jul 15 07:08:32 PM PDT 24
Finished Jul 15 07:08:38 PM PDT 24
Peak memory 206852 kb
Host smart-e1d08a33-afb9-4efa-bf11-5e6020d8dca4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3856442376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3856442376
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.2765888775
Short name T1700
Test name
Test status
Simulation time 13382148528 ps
CPU time 12.81 seconds
Started Jul 15 07:08:34 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 207052 kb
Host smart-ed36c670-d940-4c6a-a536-86df28a91cda
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2765888775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.2765888775
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1565213547
Short name T2733
Test name
Test status
Simulation time 23386431673 ps
CPU time 24.51 seconds
Started Jul 15 07:08:38 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206880 kb
Host smart-11192cd7-7db6-45f5-a18d-39517eec6b62
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1565213547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.1565213547
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2073824517
Short name T1901
Test name
Test status
Simulation time 188156767 ps
CPU time 0.86 seconds
Started Jul 15 07:08:38 PM PDT 24
Finished Jul 15 07:08:39 PM PDT 24
Peak memory 206844 kb
Host smart-d74fc0b9-a8b5-4178-a6c9-02378cc4795d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20738
24517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2073824517
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.159814207
Short name T2230
Test name
Test status
Simulation time 151566630 ps
CPU time 0.77 seconds
Started Jul 15 07:08:38 PM PDT 24
Finished Jul 15 07:08:40 PM PDT 24
Peak memory 206788 kb
Host smart-844a38aa-751c-4edb-bfcc-3f5945af91ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15981
4207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.159814207
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.575688951
Short name T1275
Test name
Test status
Simulation time 235678883 ps
CPU time 0.96 seconds
Started Jul 15 07:08:33 PM PDT 24
Finished Jul 15 07:08:35 PM PDT 24
Peak memory 206792 kb
Host smart-01c01c2a-7677-498c-9706-fb1acf50a6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57568
8951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.575688951
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.875096590
Short name T1631
Test name
Test status
Simulation time 1164968443 ps
CPU time 2.83 seconds
Started Jul 15 07:08:39 PM PDT 24
Finished Jul 15 07:08:43 PM PDT 24
Peak memory 207032 kb
Host smart-e35b91c6-c1b9-4d36-81c9-78bdd39a7753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87509
6590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.875096590
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.42359335
Short name T871
Test name
Test status
Simulation time 10422197406 ps
CPU time 20.45 seconds
Started Jul 15 07:08:32 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 207068 kb
Host smart-fc686f41-98cf-4670-ada3-5b8921163a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42359
335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.42359335
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2892445087
Short name T2678
Test name
Test status
Simulation time 392973224 ps
CPU time 1.39 seconds
Started Jul 15 07:08:33 PM PDT 24
Finished Jul 15 07:08:35 PM PDT 24
Peak memory 206708 kb
Host smart-73a48cc0-11f5-4365-96a3-c85cf1f16de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28924
45087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2892445087
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1953672012
Short name T646
Test name
Test status
Simulation time 151467732 ps
CPU time 0.79 seconds
Started Jul 15 07:08:37 PM PDT 24
Finished Jul 15 07:08:39 PM PDT 24
Peak memory 206848 kb
Host smart-34802c6c-dc04-4710-9f66-1d93ee2c737d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19536
72012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1953672012
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2814024203
Short name T1993
Test name
Test status
Simulation time 65160097 ps
CPU time 0.69 seconds
Started Jul 15 07:08:36 PM PDT 24
Finished Jul 15 07:08:38 PM PDT 24
Peak memory 206808 kb
Host smart-351ca951-c99f-438d-b64e-719099f028df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
24203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2814024203
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.428969726
Short name T2116
Test name
Test status
Simulation time 920905519 ps
CPU time 2.01 seconds
Started Jul 15 07:08:45 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 206940 kb
Host smart-f2aee2b0-f2cf-43cd-b602-9630ccf26d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42896
9726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.428969726
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.252457352
Short name T859
Test name
Test status
Simulation time 225552124 ps
CPU time 1.54 seconds
Started Jul 15 07:08:44 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 206992 kb
Host smart-4557bd0b-5652-4f77-9613-250cd957688a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
7352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.252457352
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.4276746767
Short name T2681
Test name
Test status
Simulation time 206344074 ps
CPU time 0.93 seconds
Started Jul 15 07:08:39 PM PDT 24
Finished Jul 15 07:08:41 PM PDT 24
Peak memory 206792 kb
Host smart-c4568464-41e9-4b04-a0ae-0504ddcf6c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42767
46767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.4276746767
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3554938370
Short name T875
Test name
Test status
Simulation time 147289348 ps
CPU time 0.72 seconds
Started Jul 15 07:08:47 PM PDT 24
Finished Jul 15 07:08:49 PM PDT 24
Peak memory 206792 kb
Host smart-ebf2eab1-aa86-48e2-88c0-727930eadbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35549
38370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3554938370
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1451900017
Short name T420
Test name
Test status
Simulation time 170469839 ps
CPU time 0.82 seconds
Started Jul 15 07:08:34 PM PDT 24
Finished Jul 15 07:08:36 PM PDT 24
Peak memory 206812 kb
Host smart-75bbd4ac-fbc1-4993-8083-d8073861e543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14519
00017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1451900017
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.3821605475
Short name T1008
Test name
Test status
Simulation time 9797597442 ps
CPU time 76.22 seconds
Started Jul 15 07:08:36 PM PDT 24
Finished Jul 15 07:09:53 PM PDT 24
Peak memory 207048 kb
Host smart-5ed2e037-de99-4fdb-9bd1-d9c30aa2a2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38216
05475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3821605475
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3760901550
Short name T2057
Test name
Test status
Simulation time 252338835 ps
CPU time 0.96 seconds
Started Jul 15 07:08:34 PM PDT 24
Finished Jul 15 07:08:36 PM PDT 24
Peak memory 206780 kb
Host smart-65f03a8f-b977-4e7e-8c40-a0dd7893ebda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
01550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3760901550
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3679504494
Short name T1767
Test name
Test status
Simulation time 23347621359 ps
CPU time 24.09 seconds
Started Jul 15 07:08:37 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 206856 kb
Host smart-e6da41b0-cd72-4474-8055-23e0a33e5eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36795
04494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3679504494
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1571073696
Short name T813
Test name
Test status
Simulation time 3354129866 ps
CPU time 3.94 seconds
Started Jul 15 07:08:36 PM PDT 24
Finished Jul 15 07:08:41 PM PDT 24
Peak memory 206824 kb
Host smart-0bcff5ae-08cd-4963-8805-5539c899dba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710
73696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1571073696
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3447424869
Short name T1231
Test name
Test status
Simulation time 10941650600 ps
CPU time 310.63 seconds
Started Jul 15 07:08:36 PM PDT 24
Finished Jul 15 07:13:47 PM PDT 24
Peak memory 207056 kb
Host smart-a85cf452-c46f-4286-9737-e2d9e7ebdef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34474
24869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3447424869
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2867868032
Short name T2536
Test name
Test status
Simulation time 4378385971 ps
CPU time 41.87 seconds
Started Jul 15 07:08:34 PM PDT 24
Finished Jul 15 07:09:17 PM PDT 24
Peak memory 207016 kb
Host smart-ff37c938-6c47-42be-9db1-0af511a99450
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2867868032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2867868032
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.4182554342
Short name T1992
Test name
Test status
Simulation time 320513373 ps
CPU time 0.94 seconds
Started Jul 15 07:08:36 PM PDT 24
Finished Jul 15 07:08:37 PM PDT 24
Peak memory 206764 kb
Host smart-d6788a15-b4ec-44b5-9e45-e453e71c8a19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4182554342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.4182554342
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3829228942
Short name T2461
Test name
Test status
Simulation time 188614473 ps
CPU time 0.85 seconds
Started Jul 15 07:08:31 PM PDT 24
Finished Jul 15 07:08:32 PM PDT 24
Peak memory 206800 kb
Host smart-d5da236e-3edd-4934-8ba1-15fd6ad07434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292
28942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3829228942
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.666687815
Short name T459
Test name
Test status
Simulation time 2997203136 ps
CPU time 21.86 seconds
Started Jul 15 07:08:32 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 207088 kb
Host smart-726034d5-cab1-4a66-b766-11b5b4275ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66668
7815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.666687815
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.167135411
Short name T1950
Test name
Test status
Simulation time 5240899694 ps
CPU time 38.45 seconds
Started Jul 15 07:08:38 PM PDT 24
Finished Jul 15 07:09:17 PM PDT 24
Peak memory 207012 kb
Host smart-b2d0f65c-6b0a-4f80-8437-5cde90ffe478
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=167135411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.167135411
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1311567724
Short name T793
Test name
Test status
Simulation time 153483663 ps
CPU time 0.82 seconds
Started Jul 15 07:08:39 PM PDT 24
Finished Jul 15 07:08:40 PM PDT 24
Peak memory 206808 kb
Host smart-3680511c-8db5-46f0-9ae9-8b65d4a435f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1311567724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1311567724
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.341590001
Short name T2090
Test name
Test status
Simulation time 142996551 ps
CPU time 0.8 seconds
Started Jul 15 07:08:40 PM PDT 24
Finished Jul 15 07:08:42 PM PDT 24
Peak memory 206800 kb
Host smart-3a07be91-4a28-480e-a856-eff0436b375b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34159
0001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.341590001
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1056783042
Short name T128
Test name
Test status
Simulation time 186805065 ps
CPU time 0.85 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:44 PM PDT 24
Peak memory 206816 kb
Host smart-94583d0c-bf9e-4563-9070-c7dc636e2593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
83042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1056783042
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1277524697
Short name T584
Test name
Test status
Simulation time 184475112 ps
CPU time 0.83 seconds
Started Jul 15 07:08:59 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 206792 kb
Host smart-5f65a345-f273-49ae-ba67-6457a0d9bb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12775
24697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1277524697
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.4204995757
Short name T1624
Test name
Test status
Simulation time 228685594 ps
CPU time 0.84 seconds
Started Jul 15 07:08:44 PM PDT 24
Finished Jul 15 07:08:46 PM PDT 24
Peak memory 206800 kb
Host smart-220d9582-89ff-4d4a-9aaf-67a4197e1539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42049
95757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.4204995757
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2207160510
Short name T1863
Test name
Test status
Simulation time 185382188 ps
CPU time 0.83 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:08:44 PM PDT 24
Peak memory 206968 kb
Host smart-89ef0ce7-4a82-4438-aa16-36c113547aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22071
60510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2207160510
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.778459034
Short name T1144
Test name
Test status
Simulation time 181847900 ps
CPU time 0.81 seconds
Started Jul 15 07:08:40 PM PDT 24
Finished Jul 15 07:08:41 PM PDT 24
Peak memory 206792 kb
Host smart-e6a59c72-d64b-43c4-94be-5c8e9b02c987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77845
9034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.778459034
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2929155038
Short name T2284
Test name
Test status
Simulation time 241220951 ps
CPU time 1 seconds
Started Jul 15 07:08:48 PM PDT 24
Finished Jul 15 07:08:51 PM PDT 24
Peak memory 206828 kb
Host smart-bcafa00b-4d21-4b55-bab4-35557f609a02
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2929155038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2929155038
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3327480341
Short name T1787
Test name
Test status
Simulation time 175030300 ps
CPU time 0.85 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:08:42 PM PDT 24
Peak memory 206792 kb
Host smart-77a10186-e63c-4697-9530-c48fb31ca476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33274
80341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3327480341
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3499064145
Short name T1143
Test name
Test status
Simulation time 84737777 ps
CPU time 0.71 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:08:45 PM PDT 24
Peak memory 206800 kb
Host smart-ab975804-3836-4d26-a382-99fbc3ab9652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
64145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3499064145
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3416259006
Short name T2401
Test name
Test status
Simulation time 12751951349 ps
CPU time 27.43 seconds
Started Jul 15 07:08:40 PM PDT 24
Finished Jul 15 07:09:08 PM PDT 24
Peak memory 207000 kb
Host smart-3840184c-193d-47b0-ac2b-0c610253a659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34162
59006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3416259006
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.816026552
Short name T269
Test name
Test status
Simulation time 150817114 ps
CPU time 0.77 seconds
Started Jul 15 07:08:58 PM PDT 24
Finished Jul 15 07:09:01 PM PDT 24
Peak memory 206800 kb
Host smart-22f5fa69-36e0-471d-afa1-a0909eb3e27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81602
6552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.816026552
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.783881776
Short name T1613
Test name
Test status
Simulation time 231757856 ps
CPU time 0.92 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:08:46 PM PDT 24
Peak memory 206800 kb
Host smart-530a04cd-29c6-4abe-9e20-695bca4d87e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78388
1776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.783881776
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3463810116
Short name T523
Test name
Test status
Simulation time 249139752 ps
CPU time 0.87 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:08:43 PM PDT 24
Peak memory 206840 kb
Host smart-315cdab8-1ee6-4743-ad0d-73ed855dbc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34638
10116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3463810116
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.483625867
Short name T856
Test name
Test status
Simulation time 207286992 ps
CPU time 0.88 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:44 PM PDT 24
Peak memory 206812 kb
Host smart-993b232f-3d79-413d-bc0f-30b86b193726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48362
5867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.483625867
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3771493664
Short name T1299
Test name
Test status
Simulation time 146275839 ps
CPU time 0.79 seconds
Started Jul 15 07:08:55 PM PDT 24
Finished Jul 15 07:08:57 PM PDT 24
Peak memory 206824 kb
Host smart-1b9bb029-388d-4ef6-b8b0-bee83b3b35aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37714
93664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3771493664
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2083760767
Short name T1232
Test name
Test status
Simulation time 155374696 ps
CPU time 0.77 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:44 PM PDT 24
Peak memory 206808 kb
Host smart-46fca5d6-0240-4a4d-9758-88308f13ca22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20837
60767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2083760767
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1498356425
Short name T2616
Test name
Test status
Simulation time 182225378 ps
CPU time 0.79 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:08:43 PM PDT 24
Peak memory 206816 kb
Host smart-bd87a4bb-366c-433c-975b-3aabcf10aedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14983
56425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1498356425
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2676015202
Short name T502
Test name
Test status
Simulation time 250578742 ps
CPU time 1 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:08:43 PM PDT 24
Peak memory 206820 kb
Host smart-2edc072e-1e9c-484d-b180-74dedc25a242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26760
15202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2676015202
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2581372137
Short name T2625
Test name
Test status
Simulation time 3466670902 ps
CPU time 24.69 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:09:09 PM PDT 24
Peak memory 207072 kb
Host smart-9a81060c-01b1-4df7-8e40-a9b7ffdda221
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2581372137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2581372137
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2118603007
Short name T1571
Test name
Test status
Simulation time 164905697 ps
CPU time 0.8 seconds
Started Jul 15 07:08:47 PM PDT 24
Finished Jul 15 07:08:50 PM PDT 24
Peak memory 206832 kb
Host smart-4208d3ae-0dd4-4cf5-8224-5ecb6265a477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21186
03007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2118603007
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3835378009
Short name T1131
Test name
Test status
Simulation time 142827781 ps
CPU time 0.76 seconds
Started Jul 15 07:08:40 PM PDT 24
Finished Jul 15 07:08:42 PM PDT 24
Peak memory 206700 kb
Host smart-eb968edd-ed4d-4597-8ee0-6912d7744bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38353
78009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3835378009
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1774619653
Short name T2516
Test name
Test status
Simulation time 589273164 ps
CPU time 1.46 seconds
Started Jul 15 07:08:40 PM PDT 24
Finished Jul 15 07:08:42 PM PDT 24
Peak memory 206748 kb
Host smart-e26d327e-7132-4b24-af6d-e0bf6dbd9503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17746
19653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1774619653
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1117562340
Short name T2381
Test name
Test status
Simulation time 7125295644 ps
CPU time 203.18 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:12:05 PM PDT 24
Peak memory 207008 kb
Host smart-2db17cea-e275-43fb-a2c8-b45a29b73bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11175
62340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1117562340
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.266199308
Short name T1759
Test name
Test status
Simulation time 89570774 ps
CPU time 0.77 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:22 PM PDT 24
Peak memory 206848 kb
Host smart-1837207e-b124-451d-b975-5d9aff98253f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=266199308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.266199308
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2690027560
Short name T668
Test name
Test status
Simulation time 4008678128 ps
CPU time 4.5 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206900 kb
Host smart-68a26db2-80c9-482e-be11-79d8db9f73c1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2690027560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2690027560
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1458934187
Short name T2688
Test name
Test status
Simulation time 13429501641 ps
CPU time 12.26 seconds
Started Jul 15 07:08:46 PM PDT 24
Finished Jul 15 07:09:00 PM PDT 24
Peak memory 207064 kb
Host smart-98916e16-4f37-4fe7-afdd-34046263e8c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1458934187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1458934187
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1449397559
Short name T2342
Test name
Test status
Simulation time 23390662073 ps
CPU time 22.61 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:09:06 PM PDT 24
Peak memory 206892 kb
Host smart-d08f1b79-9dbd-4ad0-aad9-fbc22fc2eec7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1449397559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.1449397559
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1657505182
Short name T2562
Test name
Test status
Simulation time 159575944 ps
CPU time 0.81 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206844 kb
Host smart-b30413cd-3293-4ae9-b4b8-2392772131ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16575
05182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1657505182
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.4063107095
Short name T1876
Test name
Test status
Simulation time 162049374 ps
CPU time 0.77 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:45 PM PDT 24
Peak memory 206812 kb
Host smart-0a21f9e1-ce44-4409-99a4-921eb38b1514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40631
07095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.4063107095
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1750073011
Short name T99
Test name
Test status
Simulation time 317225103 ps
CPU time 1.04 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:45 PM PDT 24
Peak memory 206804 kb
Host smart-ee1e72a3-061e-4002-b0cf-7154400d9912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17500
73011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1750073011
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1694369463
Short name T1018
Test name
Test status
Simulation time 473448895 ps
CPU time 1.34 seconds
Started Jul 15 07:08:47 PM PDT 24
Finished Jul 15 07:08:50 PM PDT 24
Peak memory 206784 kb
Host smart-d95d3a2d-747b-418b-a83f-280f3b226d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16943
69463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1694369463
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.2162727872
Short name T1555
Test name
Test status
Simulation time 19203721631 ps
CPU time 39.46 seconds
Started Jul 15 07:08:40 PM PDT 24
Finished Jul 15 07:09:20 PM PDT 24
Peak memory 207060 kb
Host smart-ad0da70f-5dbf-40ef-aac5-c795922ec609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21627
27872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.2162727872
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.3403002890
Short name T761
Test name
Test status
Simulation time 432081224 ps
CPU time 1.28 seconds
Started Jul 15 07:08:46 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 206828 kb
Host smart-56644765-6942-4691-bcf8-9e68c9c385cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34030
02890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.3403002890
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2276168596
Short name T1840
Test name
Test status
Simulation time 137518228 ps
CPU time 0.74 seconds
Started Jul 15 07:08:44 PM PDT 24
Finished Jul 15 07:08:46 PM PDT 24
Peak memory 206812 kb
Host smart-f8beaca4-e532-47d6-a1d4-31f28b1feecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22761
68596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2276168596
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.2735377090
Short name T2274
Test name
Test status
Simulation time 77056445 ps
CPU time 0.78 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206812 kb
Host smart-4f1f7c77-7f5b-4c18-905c-0f7408aa3717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27353
77090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2735377090
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2932148749
Short name T550
Test name
Test status
Simulation time 1083655913 ps
CPU time 2.33 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:45 PM PDT 24
Peak memory 206988 kb
Host smart-75c52ac3-381d-4c0e-b4ea-6afe2b9efa49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29321
48749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2932148749
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.649744446
Short name T1100
Test name
Test status
Simulation time 151038826 ps
CPU time 1.25 seconds
Started Jul 15 07:08:47 PM PDT 24
Finished Jul 15 07:08:50 PM PDT 24
Peak memory 207012 kb
Host smart-fda92a0b-5e0f-4b3e-b5cb-8b74f29f5115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64974
4446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.649744446
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.212542275
Short name T2148
Test name
Test status
Simulation time 162681282 ps
CPU time 0.84 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206808 kb
Host smart-4db833c3-aede-4795-a322-08683ef696f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21254
2275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.212542275
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.279114878
Short name T1234
Test name
Test status
Simulation time 172272416 ps
CPU time 0.78 seconds
Started Jul 15 07:08:48 PM PDT 24
Finished Jul 15 07:08:50 PM PDT 24
Peak memory 206848 kb
Host smart-60173215-876a-4002-867b-377d56112fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27911
4878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.279114878
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1836818798
Short name T2141
Test name
Test status
Simulation time 225675254 ps
CPU time 0.93 seconds
Started Jul 15 07:08:40 PM PDT 24
Finished Jul 15 07:08:41 PM PDT 24
Peak memory 206828 kb
Host smart-1a4a1e65-a7e1-49e3-a909-dc5a43388981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18368
18798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1836818798
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.618937823
Short name T1
Test name
Test status
Simulation time 4536946730 ps
CPU time 41.12 seconds
Started Jul 15 07:08:58 PM PDT 24
Finished Jul 15 07:09:41 PM PDT 24
Peak memory 207028 kb
Host smart-cc1fdc68-ec85-4eea-a54b-e3f336bd40f1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=618937823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.618937823
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3381144994
Short name T1989
Test name
Test status
Simulation time 314414029 ps
CPU time 0.97 seconds
Started Jul 15 07:08:48 PM PDT 24
Finished Jul 15 07:08:56 PM PDT 24
Peak memory 206792 kb
Host smart-d3fb70ec-f9bf-437f-ab37-e335ceb7db4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33811
44994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3381144994
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1744221279
Short name T1941
Test name
Test status
Simulation time 23292779395 ps
CPU time 21.61 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:09:16 PM PDT 24
Peak memory 206864 kb
Host smart-017237bc-9248-40ac-947e-abf1171824ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17442
21279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1744221279
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1757932737
Short name T283
Test name
Test status
Simulation time 3318543502 ps
CPU time 4.63 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:09:00 PM PDT 24
Peak memory 206856 kb
Host smart-d09dfe30-b18c-47b2-b961-750fba45cc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17579
32737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1757932737
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1635930986
Short name T847
Test name
Test status
Simulation time 8102492751 ps
CPU time 59.42 seconds
Started Jul 15 07:08:47 PM PDT 24
Finished Jul 15 07:09:48 PM PDT 24
Peak memory 207092 kb
Host smart-e9c04b62-2223-4af5-878d-3dd4642b1abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16359
30986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1635930986
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.399124974
Short name T2251
Test name
Test status
Simulation time 2956383276 ps
CPU time 82.77 seconds
Started Jul 15 07:08:49 PM PDT 24
Finished Jul 15 07:10:13 PM PDT 24
Peak memory 207036 kb
Host smart-614a9a77-5006-4353-91dd-d6e8b075dc7b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=399124974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.399124974
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2130526215
Short name T374
Test name
Test status
Simulation time 242927934 ps
CPU time 0.97 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:44 PM PDT 24
Peak memory 206812 kb
Host smart-bea94d78-765d-4a37-842b-635d1a0e8dde
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2130526215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2130526215
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1857060762
Short name T596
Test name
Test status
Simulation time 234946019 ps
CPU time 1.02 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206832 kb
Host smart-9cee4aab-166c-468d-8294-fe51778eaa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18570
60762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1857060762
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.4068491153
Short name T2314
Test name
Test status
Simulation time 3854546800 ps
CPU time 35.31 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:09:20 PM PDT 24
Peak memory 207088 kb
Host smart-7091c011-a21d-44d3-8bff-8a8683c0d6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40684
91153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.4068491153
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.418624975
Short name T1421
Test name
Test status
Simulation time 6182277371 ps
CPU time 57.8 seconds
Started Jul 15 07:08:44 PM PDT 24
Finished Jul 15 07:09:43 PM PDT 24
Peak memory 207040 kb
Host smart-cc7eafa1-5511-463e-98e1-7cdf6b426fb2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=418624975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.418624975
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.966142633
Short name T1126
Test name
Test status
Simulation time 152046434 ps
CPU time 0.8 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:45 PM PDT 24
Peak memory 206836 kb
Host smart-e83b0190-196e-413d-aa91-29ee7fa57e0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=966142633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.966142633
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3293164703
Short name T1284
Test name
Test status
Simulation time 217287806 ps
CPU time 0.94 seconds
Started Jul 15 07:08:56 PM PDT 24
Finished Jul 15 07:08:58 PM PDT 24
Peak memory 206792 kb
Host smart-0f412364-fb5a-416e-b292-a994dae4c851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32931
64703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3293164703
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1918316598
Short name T111
Test name
Test status
Simulation time 226808892 ps
CPU time 0.91 seconds
Started Jul 15 07:08:49 PM PDT 24
Finished Jul 15 07:08:51 PM PDT 24
Peak memory 206756 kb
Host smart-f79388fe-fa5b-40c9-91c6-9d23c7935a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19183
16598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1918316598
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.4095492596
Short name T1991
Test name
Test status
Simulation time 211113812 ps
CPU time 0.84 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:08:46 PM PDT 24
Peak memory 206812 kb
Host smart-011fec21-0f0f-49f8-8c33-11b4c25f65b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40954
92596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.4095492596
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3834486954
Short name T303
Test name
Test status
Simulation time 218817264 ps
CPU time 0.81 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206812 kb
Host smart-cfc7223c-79b1-4008-ba46-f572f5da2f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38344
86954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3834486954
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3838130712
Short name T1440
Test name
Test status
Simulation time 205107597 ps
CPU time 0.86 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:08:46 PM PDT 24
Peak memory 206828 kb
Host smart-3e42b209-d60d-4444-9760-b319f19b2764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38381
30712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3838130712
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.599903592
Short name T1101
Test name
Test status
Simulation time 179595483 ps
CPU time 0.81 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:08:43 PM PDT 24
Peak memory 206808 kb
Host smart-5252d974-2add-4deb-9319-5472d919bf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59990
3592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.599903592
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.787102472
Short name T1918
Test name
Test status
Simulation time 228219381 ps
CPU time 0.95 seconds
Started Jul 15 07:08:56 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206804 kb
Host smart-1e7eae36-251b-4aca-95a9-31a405dfb25d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=787102472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.787102472
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2385762537
Short name T992
Test name
Test status
Simulation time 169147037 ps
CPU time 0.77 seconds
Started Jul 15 07:08:59 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 206808 kb
Host smart-5404c44c-4246-4643-84e0-41d1e54a233c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23857
62537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2385762537
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.885318007
Short name T38
Test name
Test status
Simulation time 44816851 ps
CPU time 0.65 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:08:45 PM PDT 24
Peak memory 206820 kb
Host smart-7adc90b2-e694-4a33-a4d6-a300479592ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88531
8007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.885318007
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1213891009
Short name T912
Test name
Test status
Simulation time 12110958797 ps
CPU time 27.27 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:35 PM PDT 24
Peak memory 206996 kb
Host smart-28659c4b-d6b7-4ba2-8cd2-1eeae1d9c052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12138
91009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1213891009
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1549026252
Short name T1332
Test name
Test status
Simulation time 170179941 ps
CPU time 0.79 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206764 kb
Host smart-cf7bbd4b-8d7e-42a4-9c88-995e03aea50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15490
26252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1549026252
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2139929853
Short name T294
Test name
Test status
Simulation time 254166617 ps
CPU time 0.93 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:44 PM PDT 24
Peak memory 206800 kb
Host smart-24019646-910d-48ae-8eac-b1a0842380b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21399
29853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2139929853
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2486284321
Short name T2666
Test name
Test status
Simulation time 261882939 ps
CPU time 0.97 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:08:43 PM PDT 24
Peak memory 206816 kb
Host smart-c2df39e2-f392-4b79-bea4-55020f63fb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24862
84321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2486284321
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2581759727
Short name T2115
Test name
Test status
Simulation time 180995743 ps
CPU time 0.9 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206820 kb
Host smart-30a2982a-af8c-45e1-9895-c33be4fdaa15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25817
59727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2581759727
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.273777748
Short name T990
Test name
Test status
Simulation time 172191721 ps
CPU time 0.79 seconds
Started Jul 15 07:08:41 PM PDT 24
Finished Jul 15 07:08:43 PM PDT 24
Peak memory 206776 kb
Host smart-910b4e58-0228-49bf-b355-346d967fc2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27377
7748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.273777748
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.522289895
Short name T2641
Test name
Test status
Simulation time 170891710 ps
CPU time 0.79 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206804 kb
Host smart-4260485e-ce85-4080-8f98-980ea231793c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52228
9895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.522289895
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3219439539
Short name T1350
Test name
Test status
Simulation time 173412595 ps
CPU time 0.84 seconds
Started Jul 15 07:08:49 PM PDT 24
Finished Jul 15 07:08:51 PM PDT 24
Peak memory 206828 kb
Host smart-56f4abd7-7cce-4ede-a6a1-371a21dc3196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32194
39539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3219439539
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2046433813
Short name T2153
Test name
Test status
Simulation time 282155257 ps
CPU time 1.05 seconds
Started Jul 15 07:08:46 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 206808 kb
Host smart-ac1c48c3-a584-4543-8f20-cbabcb6d1c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20464
33813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2046433813
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2970692242
Short name T1103
Test name
Test status
Simulation time 4992060274 ps
CPU time 43.34 seconds
Started Jul 15 07:08:47 PM PDT 24
Finished Jul 15 07:09:33 PM PDT 24
Peak memory 207008 kb
Host smart-790aa8ad-2eed-413c-8760-b4e4df0f64d3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2970692242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2970692242
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2731706948
Short name T1147
Test name
Test status
Simulation time 154123743 ps
CPU time 0.79 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:08:46 PM PDT 24
Peak memory 206828 kb
Host smart-420d3831-999b-49d1-aadf-490f19b799d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27317
06948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2731706948
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.426741424
Short name T492
Test name
Test status
Simulation time 203073705 ps
CPU time 0.83 seconds
Started Jul 15 07:08:54 PM PDT 24
Finished Jul 15 07:08:57 PM PDT 24
Peak memory 206780 kb
Host smart-f556b84b-d7e1-413b-a091-7f299ec4b85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42674
1424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.426741424
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.3160301898
Short name T1118
Test name
Test status
Simulation time 335430036 ps
CPU time 1.08 seconds
Started Jul 15 07:08:47 PM PDT 24
Finished Jul 15 07:08:50 PM PDT 24
Peak memory 206812 kb
Host smart-da1a843b-5bed-476f-a670-281105bfb0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
01898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.3160301898
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1722473540
Short name T578
Test name
Test status
Simulation time 5106601355 ps
CPU time 45.73 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:48 PM PDT 24
Peak memory 207052 kb
Host smart-87bb95f5-e948-487e-a30a-011834c4a3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
73540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1722473540
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1679384237
Short name T1802
Test name
Test status
Simulation time 36314545 ps
CPU time 0.66 seconds
Started Jul 15 07:08:50 PM PDT 24
Finished Jul 15 07:08:52 PM PDT 24
Peak memory 206868 kb
Host smart-5e23ff12-8b52-4be6-bc03-4fc3e09adc54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1679384237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1679384237
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1708950259
Short name T212
Test name
Test status
Simulation time 4230702367 ps
CPU time 4.85 seconds
Started Jul 15 07:08:42 PM PDT 24
Finished Jul 15 07:08:49 PM PDT 24
Peak memory 207032 kb
Host smart-cb86a894-f9af-4ba1-b057-b01f0f85b11f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1708950259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.1708950259
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3132384501
Short name T8
Test name
Test status
Simulation time 13361101905 ps
CPU time 12.96 seconds
Started Jul 15 07:08:44 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206904 kb
Host smart-6de285a9-94c7-47a7-b306-c54439db05bc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3132384501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3132384501
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.435515280
Short name T2531
Test name
Test status
Simulation time 23439253261 ps
CPU time 29.06 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:09:34 PM PDT 24
Peak memory 207000 kb
Host smart-eeb8922c-0fd4-4336-9091-2d7e97bcff37
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=435515280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.435515280
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2944674641
Short name T2575
Test name
Test status
Simulation time 183351428 ps
CPU time 0.9 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:10 PM PDT 24
Peak memory 206844 kb
Host smart-221f092b-dd2a-48e0-8060-2669e8101b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29446
74641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2944674641
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.726967868
Short name T2483
Test name
Test status
Simulation time 158493944 ps
CPU time 0.79 seconds
Started Jul 15 07:08:50 PM PDT 24
Finished Jul 15 07:08:52 PM PDT 24
Peak memory 206796 kb
Host smart-5b312e0a-f08f-4846-96c8-ffc1579e796f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72696
7868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.726967868
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3720527781
Short name T1470
Test name
Test status
Simulation time 365180399 ps
CPU time 1.24 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:09:06 PM PDT 24
Peak memory 206812 kb
Host smart-1a921962-314e-4ed5-bb40-7adb7f7ff17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37205
27781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3720527781
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3204301369
Short name T1074
Test name
Test status
Simulation time 1532644166 ps
CPU time 3.44 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 207004 kb
Host smart-d0d6fa13-d383-431b-bfd7-82993f747b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32043
01369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3204301369
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.3753341071
Short name T1612
Test name
Test status
Simulation time 10268939216 ps
CPU time 18.3 seconds
Started Jul 15 07:08:56 PM PDT 24
Finished Jul 15 07:09:15 PM PDT 24
Peak memory 207068 kb
Host smart-608433e6-45dc-4dcb-80d9-844d8f49fd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37533
41071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3753341071
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.1507696633
Short name T169
Test name
Test status
Simulation time 441490022 ps
CPU time 1.3 seconds
Started Jul 15 07:08:44 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 206804 kb
Host smart-1aa10e18-d686-49e0-bda2-6ef44015892c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15076
96633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.1507696633
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.764480064
Short name T2639
Test name
Test status
Simulation time 133756975 ps
CPU time 0.73 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206812 kb
Host smart-59634385-eae7-4bc1-8f76-50e5ef63757d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76448
0064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.764480064
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3927015740
Short name T1136
Test name
Test status
Simulation time 37453742 ps
CPU time 0.66 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206980 kb
Host smart-ad22a17c-9c60-41d0-b76c-577bdd5cb047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39270
15740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3927015740
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3908030116
Short name T2362
Test name
Test status
Simulation time 863785464 ps
CPU time 2.02 seconds
Started Jul 15 07:09:01 PM PDT 24
Finished Jul 15 07:09:05 PM PDT 24
Peak memory 206996 kb
Host smart-95834cb2-b0c3-4464-bda7-306341795e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39080
30116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3908030116
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3777387756
Short name T1230
Test name
Test status
Simulation time 205387198 ps
CPU time 1.82 seconds
Started Jul 15 07:08:48 PM PDT 24
Finished Jul 15 07:08:51 PM PDT 24
Peak memory 206960 kb
Host smart-3f1a4a14-848e-4712-a355-734ff0b10611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37773
87756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3777387756
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.494122104
Short name T204
Test name
Test status
Simulation time 223373897 ps
CPU time 0.9 seconds
Started Jul 15 07:09:01 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 206812 kb
Host smart-e559d155-824d-41d4-951f-482565063dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49412
2104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.494122104
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.40046237
Short name T410
Test name
Test status
Simulation time 149656140 ps
CPU time 0.82 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:08:56 PM PDT 24
Peak memory 206812 kb
Host smart-27c45a74-ce85-4f2e-b9a2-03fa5a77f1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40046
237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.40046237
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.4018651858
Short name T479
Test name
Test status
Simulation time 203873883 ps
CPU time 0.95 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:09:06 PM PDT 24
Peak memory 206832 kb
Host smart-18c8677d-3a58-479b-a376-29ed15d23218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40186
51858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.4018651858
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.1958297328
Short name T2433
Test name
Test status
Simulation time 4414767007 ps
CPU time 42.17 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:09:36 PM PDT 24
Peak memory 207048 kb
Host smart-fc5ff45e-08f5-4a8c-ab9d-3ba9d7cd02a0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1958297328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1958297328
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.90949253
Short name T1285
Test name
Test status
Simulation time 9298096664 ps
CPU time 27.34 seconds
Started Jul 15 07:08:59 PM PDT 24
Finished Jul 15 07:09:28 PM PDT 24
Peak memory 207088 kb
Host smart-6b068985-6b5e-4dc7-bebf-6a035e8f116f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90949
253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.90949253
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2538358392
Short name T1110
Test name
Test status
Simulation time 170459001 ps
CPU time 0.85 seconds
Started Jul 15 07:08:46 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 206808 kb
Host smart-d9026d29-e9cd-4ce4-9da3-d4fdfbf34130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25383
58392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2538358392
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3667697985
Short name T141
Test name
Test status
Simulation time 23310405555 ps
CPU time 21.27 seconds
Started Jul 15 07:09:08 PM PDT 24
Finished Jul 15 07:09:36 PM PDT 24
Peak memory 206868 kb
Host smart-285456c3-ea66-4e46-854b-1d5d6026e070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
97985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3667697985
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3339133625
Short name T2721
Test name
Test status
Simulation time 3330499138 ps
CPU time 4.04 seconds
Started Jul 15 07:08:44 PM PDT 24
Finished Jul 15 07:08:50 PM PDT 24
Peak memory 206888 kb
Host smart-2403696c-9af3-4812-89ca-0c83540ee45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33391
33625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3339133625
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.1980710100
Short name T1784
Test name
Test status
Simulation time 5321287378 ps
CPU time 38.92 seconds
Started Jul 15 07:09:04 PM PDT 24
Finished Jul 15 07:09:46 PM PDT 24
Peak memory 207284 kb
Host smart-5bb3a04a-ba7b-4837-8b3c-657800b43af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19807
10100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1980710100
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.768210723
Short name T1320
Test name
Test status
Simulation time 5182808019 ps
CPU time 143.67 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:11:18 PM PDT 24
Peak memory 207004 kb
Host smart-e9b1a5f9-a11e-42d6-a93d-a4728a746dfb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=768210723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.768210723
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.4040272957
Short name T2426
Test name
Test status
Simulation time 256782449 ps
CPU time 0.91 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:56 PM PDT 24
Peak memory 206816 kb
Host smart-cd2c345f-c5bd-4817-bce5-9951dcf1d7a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4040272957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.4040272957
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.514966772
Short name T1052
Test name
Test status
Simulation time 209493275 ps
CPU time 0.97 seconds
Started Jul 15 07:09:04 PM PDT 24
Finished Jul 15 07:09:08 PM PDT 24
Peak memory 206788 kb
Host smart-e159f46f-e604-4189-abd0-8d40e26b7930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51496
6772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.514966772
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.218962374
Short name T1363
Test name
Test status
Simulation time 3840001616 ps
CPU time 27.16 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:09:22 PM PDT 24
Peak memory 207088 kb
Host smart-15c6ef2f-24cf-4e7c-8d68-d981fed3c4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21896
2374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.218962374
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.625334162
Short name T535
Test name
Test status
Simulation time 4674743344 ps
CPU time 35.53 seconds
Started Jul 15 07:08:59 PM PDT 24
Finished Jul 15 07:09:37 PM PDT 24
Peak memory 207100 kb
Host smart-b281c204-30aa-47c5-9796-194708e9a68f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=625334162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.625334162
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3162736568
Short name T558
Test name
Test status
Simulation time 217080551 ps
CPU time 0.85 seconds
Started Jul 15 07:08:45 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 206812 kb
Host smart-6af60d33-0cbe-450f-8e73-159cc24a8091
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3162736568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3162736568
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1797724571
Short name T1474
Test name
Test status
Simulation time 141748907 ps
CPU time 0.77 seconds
Started Jul 15 07:08:44 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 206796 kb
Host smart-bc0452d9-9bf6-4f8d-b922-d34c985bbf36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977
24571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1797724571
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2348597150
Short name T112
Test name
Test status
Simulation time 222636008 ps
CPU time 0.84 seconds
Started Jul 15 07:08:50 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206824 kb
Host smart-fab968e2-73a3-44e3-9ac1-741647a7d965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23485
97150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2348597150
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.2212790056
Short name T1785
Test name
Test status
Simulation time 153860448 ps
CPU time 0.8 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206784 kb
Host smart-2bee2178-a4b3-4d98-bae7-0bbf2ae624e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22127
90056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.2212790056
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2032339877
Short name T1406
Test name
Test status
Simulation time 174269256 ps
CPU time 0.8 seconds
Started Jul 15 07:08:49 PM PDT 24
Finished Jul 15 07:08:51 PM PDT 24
Peak memory 206824 kb
Host smart-88cea164-76d2-419c-8c72-bed4c045f2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20323
39877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2032339877
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3765766213
Short name T455
Test name
Test status
Simulation time 220540377 ps
CPU time 0.86 seconds
Started Jul 15 07:08:56 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206820 kb
Host smart-cc593928-8de7-4a23-a4b8-3772bd7e835a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37657
66213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3765766213
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3528754964
Short name T1728
Test name
Test status
Simulation time 156512700 ps
CPU time 0.8 seconds
Started Jul 15 07:08:46 PM PDT 24
Finished Jul 15 07:08:48 PM PDT 24
Peak memory 206812 kb
Host smart-f019069a-2bb3-40be-81dd-73d23e8c6fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35287
54964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3528754964
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1123219235
Short name T2664
Test name
Test status
Simulation time 229058967 ps
CPU time 0.91 seconds
Started Jul 15 07:09:04 PM PDT 24
Finished Jul 15 07:09:07 PM PDT 24
Peak memory 206832 kb
Host smart-b1570421-4a4f-4160-bfe8-4b2ac0ea62a1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1123219235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1123219235
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.859253316
Short name T970
Test name
Test status
Simulation time 150331820 ps
CPU time 0.79 seconds
Started Jul 15 07:08:45 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 206824 kb
Host smart-646adda6-82b7-4449-a3c8-c06b659b854a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85925
3316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.859253316
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.4073623682
Short name T1248
Test name
Test status
Simulation time 44692336 ps
CPU time 0.64 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206812 kb
Host smart-82613030-c281-46c2-a2ad-877d1d8b9f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40736
23682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.4073623682
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2549479900
Short name T1799
Test name
Test status
Simulation time 17995050346 ps
CPU time 42.83 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:09:37 PM PDT 24
Peak memory 207052 kb
Host smart-a5b3146f-6ebe-4d45-851e-9d7077d82492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25494
79900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2549479900
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3481084932
Short name T340
Test name
Test status
Simulation time 163645789 ps
CPU time 0.79 seconds
Started Jul 15 07:08:45 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 206812 kb
Host smart-b494ba9f-3924-4362-9238-12d18b110478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34810
84932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3481084932
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.333445493
Short name T1339
Test name
Test status
Simulation time 198830227 ps
CPU time 0.89 seconds
Started Jul 15 07:08:45 PM PDT 24
Finished Jul 15 07:08:47 PM PDT 24
Peak memory 206784 kb
Host smart-272662b8-1767-4d78-9aee-066f86a203be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
5493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.333445493
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2006305602
Short name T20
Test name
Test status
Simulation time 154308333 ps
CPU time 0.78 seconds
Started Jul 15 07:08:43 PM PDT 24
Finished Jul 15 07:08:46 PM PDT 24
Peak memory 206828 kb
Host smart-5bb2276e-7f36-4921-92bf-10628d8f7cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20063
05602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2006305602
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3534514940
Short name T1383
Test name
Test status
Simulation time 170807711 ps
CPU time 0.82 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206804 kb
Host smart-19f6dabc-1296-4b3e-9c49-aadd309915fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35345
14940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3534514940
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2621237809
Short name T2527
Test name
Test status
Simulation time 146019620 ps
CPU time 0.78 seconds
Started Jul 15 07:09:04 PM PDT 24
Finished Jul 15 07:09:07 PM PDT 24
Peak memory 206812 kb
Host smart-6dc1c758-1e5b-4f62-b20d-fbf47b4d3939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26212
37809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2621237809
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2518729378
Short name T434
Test name
Test status
Simulation time 173455814 ps
CPU time 0.77 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206784 kb
Host smart-20d106f7-d9c2-4901-a3ac-78bc9527c447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25187
29378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2518729378
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3481278058
Short name T322
Test name
Test status
Simulation time 207035239 ps
CPU time 0.82 seconds
Started Jul 15 07:08:50 PM PDT 24
Finished Jul 15 07:08:53 PM PDT 24
Peak memory 206820 kb
Host smart-ffebe8b8-ca3e-44b0-88db-cda41dc413c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34812
78058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3481278058
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.186673369
Short name T72
Test name
Test status
Simulation time 239543643 ps
CPU time 0.99 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:00 PM PDT 24
Peak memory 206840 kb
Host smart-22aeff41-bc35-41d1-9424-a050b3a9d436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18667
3369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.186673369
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2864179390
Short name T1273
Test name
Test status
Simulation time 4053746407 ps
CPU time 29.55 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:51 PM PDT 24
Peak memory 207108 kb
Host smart-70bdda8d-7fb0-400e-9fec-8dd609b5a49c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2864179390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2864179390
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2052706636
Short name T1393
Test name
Test status
Simulation time 156670914 ps
CPU time 0.79 seconds
Started Jul 15 07:08:58 PM PDT 24
Finished Jul 15 07:09:01 PM PDT 24
Peak memory 206804 kb
Host smart-b3c24a9b-c0e1-43a3-b6b6-be6c5785f1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20527
06636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2052706636
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.4099138965
Short name T482
Test name
Test status
Simulation time 167410253 ps
CPU time 0.83 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206984 kb
Host smart-de749183-7570-48fe-ad7b-a15fb97f121d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40991
38965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.4099138965
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.3554202109
Short name T2480
Test name
Test status
Simulation time 1184255264 ps
CPU time 2.56 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:08:58 PM PDT 24
Peak memory 206992 kb
Host smart-64ab5bbb-d1b7-4c70-bcdd-b43cb6f12d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
02109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3554202109
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3087857846
Short name T435
Test name
Test status
Simulation time 5841935262 ps
CPU time 41.47 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:40 PM PDT 24
Peak memory 207088 kb
Host smart-664078ea-8abf-429c-a983-5e532f61f0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30878
57846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3087857846
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2034924808
Short name T2419
Test name
Test status
Simulation time 47794455 ps
CPU time 0.69 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:23 PM PDT 24
Peak memory 206852 kb
Host smart-4a4c637b-93fd-4a97-8d41-009c76b52662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2034924808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2034924808
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2857477237
Short name T1697
Test name
Test status
Simulation time 3886529999 ps
CPU time 5.32 seconds
Started Jul 15 07:09:08 PM PDT 24
Finished Jul 15 07:09:21 PM PDT 24
Peak memory 207088 kb
Host smart-ae847e74-72b3-431e-ae8c-4d0a9245e34d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2857477237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.2857477237
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.239627640
Short name T649
Test name
Test status
Simulation time 13354129863 ps
CPU time 12.05 seconds
Started Jul 15 07:08:50 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 206864 kb
Host smart-550619ea-9f5d-47c8-997d-f5045096552b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=239627640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.239627640
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.4107758787
Short name T666
Test name
Test status
Simulation time 23381249973 ps
CPU time 25.71 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:09:31 PM PDT 24
Peak memory 207008 kb
Host smart-383dba89-6630-4a63-8ae1-0b30f836b78a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4107758787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.4107758787
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3619858181
Short name T1165
Test name
Test status
Simulation time 175773762 ps
CPU time 0.77 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:08:57 PM PDT 24
Peak memory 206980 kb
Host smart-af3b02f0-45e7-494f-927f-88625a5160e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36198
58181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3619858181
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.2370119540
Short name T1524
Test name
Test status
Simulation time 145322103 ps
CPU time 0.73 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206784 kb
Host smart-6a09061c-d597-443d-ab7f-a6830baff98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23701
19540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.2370119540
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3501259412
Short name T2207
Test name
Test status
Simulation time 400243385 ps
CPU time 1.19 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206780 kb
Host smart-cc8a590f-2924-4545-b438-f844444688e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35012
59412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3501259412
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.289574239
Short name T2525
Test name
Test status
Simulation time 1101016257 ps
CPU time 2.56 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206960 kb
Host smart-ef40dccb-c9c3-4355-be41-ca9faf6cee44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28957
4239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.289574239
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.438293111
Short name T1610
Test name
Test status
Simulation time 12716622567 ps
CPU time 24.25 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:09:19 PM PDT 24
Peak memory 207044 kb
Host smart-4ca7d349-fc4a-4088-8568-955f7fba4fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43829
3111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.438293111
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2754653348
Short name T1263
Test name
Test status
Simulation time 301697857 ps
CPU time 1.16 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:09:05 PM PDT 24
Peak memory 206812 kb
Host smart-5db9f0df-3d65-430f-a5ec-6ba64d0d23eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27546
53348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2754653348
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2106428539
Short name T947
Test name
Test status
Simulation time 148608145 ps
CPU time 0.84 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:08:57 PM PDT 24
Peak memory 206812 kb
Host smart-de5a56be-e985-4923-933d-fb7fba5cf22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21064
28539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2106428539
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.747774394
Short name T218
Test name
Test status
Simulation time 30263427 ps
CPU time 0.66 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206828 kb
Host smart-abd38f91-915b-4a7e-8d9d-bae07070766e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74777
4394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.747774394
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.250038961
Short name T750
Test name
Test status
Simulation time 1014540566 ps
CPU time 2.07 seconds
Started Jul 15 07:08:58 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 206936 kb
Host smart-20ec4d0b-a509-460c-933f-09d1fc27534c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003
8961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.250038961
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3574168201
Short name T2740
Test name
Test status
Simulation time 298360904 ps
CPU time 1.97 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:08:57 PM PDT 24
Peak memory 206960 kb
Host smart-efdd1d9e-a0b0-43e4-8add-381046e00700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35741
68201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3574168201
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.328041050
Short name T1123
Test name
Test status
Simulation time 191404078 ps
CPU time 0.82 seconds
Started Jul 15 07:08:58 PM PDT 24
Finished Jul 15 07:09:01 PM PDT 24
Peak memory 206796 kb
Host smart-1bcee253-22d3-4af8-a887-5ac56fe8fee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
1050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.328041050
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.99827037
Short name T2542
Test name
Test status
Simulation time 159237617 ps
CPU time 0.9 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206820 kb
Host smart-8940a0f5-4c91-4af4-9535-14daedf1dfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99827
037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.99827037
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1074821538
Short name T1212
Test name
Test status
Simulation time 222398895 ps
CPU time 0.85 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:00 PM PDT 24
Peak memory 206824 kb
Host smart-ba12a0d9-896d-4707-8bcc-a675c595bd9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10748
21538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1074821538
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.1660686860
Short name T1900
Test name
Test status
Simulation time 8425217704 ps
CPU time 28.33 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:09:21 PM PDT 24
Peak memory 207096 kb
Host smart-b0f71c94-4f1c-4f75-aac5-01b248838e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16606
86860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.1660686860
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.14448132
Short name T2462
Test name
Test status
Simulation time 182693880 ps
CPU time 0.82 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:08:56 PM PDT 24
Peak memory 206828 kb
Host smart-695d430c-9602-4780-aa4e-01f8b8fb69fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448
132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.14448132
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.3085387831
Short name T2367
Test name
Test status
Simulation time 23312431645 ps
CPU time 20.92 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:20 PM PDT 24
Peak memory 206888 kb
Host smart-b7ed7653-9b09-478b-884d-4c6518bd8125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
87831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3085387831
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.382041026
Short name T2496
Test name
Test status
Simulation time 3360484197 ps
CPU time 4.87 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 206888 kb
Host smart-fc17054b-0acf-471e-b831-71e9a649591a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38204
1026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.382041026
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.3561722965
Short name T1510
Test name
Test status
Simulation time 5058058377 ps
CPU time 135.31 seconds
Started Jul 15 07:09:07 PM PDT 24
Finished Jul 15 07:11:28 PM PDT 24
Peak memory 207084 kb
Host smart-a80fa4b0-527c-44fa-b702-dcc947328549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35617
22965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.3561722965
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.4102913229
Short name T1865
Test name
Test status
Simulation time 5263145904 ps
CPU time 134.63 seconds
Started Jul 15 07:09:12 PM PDT 24
Finished Jul 15 07:11:37 PM PDT 24
Peak memory 206988 kb
Host smart-a8e58af4-39bc-4a40-8b0f-e9acb32ff77e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4102913229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.4102913229
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.436210881
Short name T330
Test name
Test status
Simulation time 250685954 ps
CPU time 0.89 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:17 PM PDT 24
Peak memory 206812 kb
Host smart-ae62429a-d763-40a1-afe7-010cd6ecd772
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=436210881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.436210881
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.4206904551
Short name T845
Test name
Test status
Simulation time 189276938 ps
CPU time 0.89 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206704 kb
Host smart-cea923d7-6ab7-46ad-a53b-0611d394fdb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42069
04551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.4206904551
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.338730199
Short name T1082
Test name
Test status
Simulation time 4357899457 ps
CPU time 32.56 seconds
Started Jul 15 07:08:59 PM PDT 24
Finished Jul 15 07:09:34 PM PDT 24
Peak memory 207024 kb
Host smart-32d658f1-2e75-47d5-a234-497ed72d8615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33873
0199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.338730199
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2241191752
Short name T1134
Test name
Test status
Simulation time 5978068234 ps
CPU time 43.04 seconds
Started Jul 15 07:08:53 PM PDT 24
Finished Jul 15 07:09:39 PM PDT 24
Peak memory 207008 kb
Host smart-8806fb18-1cde-4ddd-89e0-48535696a7d8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2241191752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2241191752
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.128804324
Short name T1042
Test name
Test status
Simulation time 169792537 ps
CPU time 0.86 seconds
Started Jul 15 07:08:51 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206824 kb
Host smart-e0a8844c-63b6-4702-bd2b-13068a518f07
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=128804324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.128804324
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1856793275
Short name T1791
Test name
Test status
Simulation time 144344731 ps
CPU time 0.8 seconds
Started Jul 15 07:08:50 PM PDT 24
Finished Jul 15 07:08:54 PM PDT 24
Peak memory 206828 kb
Host smart-6d4d5eae-b4f8-4731-9f5a-4105179d6800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18567
93275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1856793275
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3827875997
Short name T1279
Test name
Test status
Simulation time 227493151 ps
CPU time 0.88 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:09:06 PM PDT 24
Peak memory 206836 kb
Host smart-c51f6d51-ef62-47ad-a369-e1c4cadec55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38278
75997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3827875997
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2362651736
Short name T1678
Test name
Test status
Simulation time 159652606 ps
CPU time 0.81 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206760 kb
Host smart-9625fa40-e347-4337-9aa0-a2a4a309fa14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23626
51736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2362651736
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3076480282
Short name T2698
Test name
Test status
Simulation time 154326026 ps
CPU time 0.82 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206812 kb
Host smart-a6f4c369-e59c-4a8a-a3ee-a5d9529b1ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30764
80282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3076480282
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1299707081
Short name T1765
Test name
Test status
Simulation time 272496501 ps
CPU time 0.91 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:10 PM PDT 24
Peak memory 206820 kb
Host smart-7a467b62-ed96-4e2b-bc74-5c626142866e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12997
07081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1299707081
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2516725275
Short name T1872
Test name
Test status
Simulation time 159720929 ps
CPU time 0.81 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:56 PM PDT 24
Peak memory 206788 kb
Host smart-87af729e-6104-4fb7-9824-321d6bc69886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25167
25275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2516725275
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.4094801529
Short name T452
Test name
Test status
Simulation time 237417692 ps
CPU time 0.87 seconds
Started Jul 15 07:08:50 PM PDT 24
Finished Jul 15 07:08:52 PM PDT 24
Peak memory 206784 kb
Host smart-7bf0fffb-deaf-4372-9453-9264c890b8b9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4094801529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.4094801529
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3032710937
Short name T2684
Test name
Test status
Simulation time 140124142 ps
CPU time 0.73 seconds
Started Jul 15 07:08:54 PM PDT 24
Finished Jul 15 07:08:57 PM PDT 24
Peak memory 206828 kb
Host smart-114def6d-dcfc-48e3-b79a-be851a1ce7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30327
10937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3032710937
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.807419008
Short name T1766
Test name
Test status
Simulation time 37881342 ps
CPU time 0.72 seconds
Started Jul 15 07:08:52 PM PDT 24
Finished Jul 15 07:08:55 PM PDT 24
Peak memory 206836 kb
Host smart-5a1111f1-cf22-4133-ba52-4d7c003b3879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80741
9008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.807419008
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2236523065
Short name T232
Test name
Test status
Simulation time 6458772374 ps
CPU time 14.2 seconds
Started Jul 15 07:08:59 PM PDT 24
Finished Jul 15 07:09:16 PM PDT 24
Peak memory 206976 kb
Host smart-b15292c1-a2c4-4aa6-8ac8-6b7191c63d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
23065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2236523065
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3625973112
Short name T791
Test name
Test status
Simulation time 180568027 ps
CPU time 0.84 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206800 kb
Host smart-4e867098-7887-4872-93ce-1051b5a595a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36259
73112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3625973112
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1394889331
Short name T606
Test name
Test status
Simulation time 220751627 ps
CPU time 0.93 seconds
Started Jul 15 07:09:02 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 206848 kb
Host smart-3b9f5ed4-f478-4457-9d54-5f879d223d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13948
89331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1394889331
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.401315197
Short name T1824
Test name
Test status
Simulation time 194047112 ps
CPU time 0.81 seconds
Started Jul 15 07:08:56 PM PDT 24
Finished Jul 15 07:08:58 PM PDT 24
Peak memory 206828 kb
Host smart-da30bbf2-3aa7-4a70-b0b1-99e7886fa789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40131
5197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.401315197
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.927375633
Short name T2715
Test name
Test status
Simulation time 189550564 ps
CPU time 0.88 seconds
Started Jul 15 07:09:02 PM PDT 24
Finished Jul 15 07:09:05 PM PDT 24
Peak memory 206816 kb
Host smart-c2ac9e4d-9960-496f-a38f-6e1cd0e5dd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92737
5633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.927375633
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1864915220
Short name T2732
Test name
Test status
Simulation time 147786756 ps
CPU time 0.83 seconds
Started Jul 15 07:08:58 PM PDT 24
Finished Jul 15 07:09:01 PM PDT 24
Peak memory 206824 kb
Host smart-609f4c13-40ce-4574-8680-771e9ff81330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
15220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1864915220
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1551509260
Short name T1754
Test name
Test status
Simulation time 194375170 ps
CPU time 0.85 seconds
Started Jul 15 07:08:56 PM PDT 24
Finished Jul 15 07:08:58 PM PDT 24
Peak memory 206816 kb
Host smart-1f6b921e-930d-4f29-b963-331a2f6b64ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15515
09260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1551509260
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2753048951
Short name T636
Test name
Test status
Simulation time 150986254 ps
CPU time 0.81 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:00 PM PDT 24
Peak memory 206840 kb
Host smart-eb3fdb20-3821-461b-8147-11a047cba1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27530
48951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2753048951
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3953898327
Short name T931
Test name
Test status
Simulation time 219504016 ps
CPU time 0.93 seconds
Started Jul 15 07:09:07 PM PDT 24
Finished Jul 15 07:09:14 PM PDT 24
Peak memory 206844 kb
Host smart-d8a128e1-69df-4c5e-bc0e-4a29899d4ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39538
98327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3953898327
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1960076925
Short name T2465
Test name
Test status
Simulation time 5885613657 ps
CPU time 39.32 seconds
Started Jul 15 07:09:04 PM PDT 24
Finished Jul 15 07:09:45 PM PDT 24
Peak memory 207036 kb
Host smart-65e9b319-3072-4a0b-9471-e3632152a8f7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1960076925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1960076925
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1561911046
Short name T1087
Test name
Test status
Simulation time 194454962 ps
CPU time 0.84 seconds
Started Jul 15 07:09:02 PM PDT 24
Finished Jul 15 07:09:05 PM PDT 24
Peak memory 206792 kb
Host smart-acb5d5c7-b451-404b-89d4-40f78ef27feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15619
11046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1561911046
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3220159174
Short name T1323
Test name
Test status
Simulation time 139596327 ps
CPU time 0.79 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206816 kb
Host smart-4d1b1fcc-d121-48b3-89cd-9edb2dc6fd49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32201
59174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3220159174
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.1848313727
Short name T468
Test name
Test status
Simulation time 1267167098 ps
CPU time 2.82 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:01 PM PDT 24
Peak memory 207012 kb
Host smart-cb9b7d01-d8e5-43ae-ba86-89ced8061f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18483
13727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1848313727
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2660586281
Short name T1796
Test name
Test status
Simulation time 6718780602 ps
CPU time 181.61 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 207032 kb
Host smart-a6a4123d-6b33-4f01-92c5-61244d56c081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26605
86281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2660586281
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.342866282
Short name T1966
Test name
Test status
Simulation time 44764190 ps
CPU time 0.71 seconds
Started Jul 15 07:09:14 PM PDT 24
Finished Jul 15 07:09:28 PM PDT 24
Peak memory 206848 kb
Host smart-56a5e429-1dab-4102-8e0e-761e1aeaa8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=342866282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.342866282
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.704589619
Short name T213
Test name
Test status
Simulation time 4182745997 ps
CPU time 4.69 seconds
Started Jul 15 07:08:54 PM PDT 24
Finished Jul 15 07:09:01 PM PDT 24
Peak memory 206996 kb
Host smart-174f7d78-c421-4fd5-adc8-52bd45e4e135
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=704589619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.704589619
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3120282515
Short name T884
Test name
Test status
Simulation time 13425553807 ps
CPU time 12.07 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:21 PM PDT 24
Peak memory 207036 kb
Host smart-613110ff-85c0-454e-94ef-1b25e76c09a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3120282515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3120282515
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.842921069
Short name T967
Test name
Test status
Simulation time 23325314495 ps
CPU time 22.34 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:40 PM PDT 24
Peak memory 206868 kb
Host smart-7947c9e9-90d2-47ff-a333-d6b1890a305b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=842921069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.842921069
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3661519790
Short name T403
Test name
Test status
Simulation time 213817701 ps
CPU time 0.94 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206808 kb
Host smart-0cec54d4-fabe-4ef1-8948-8d39dd183bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36615
19790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3661519790
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2675051511
Short name T1352
Test name
Test status
Simulation time 152247914 ps
CPU time 0.77 seconds
Started Jul 15 07:09:01 PM PDT 24
Finished Jul 15 07:09:04 PM PDT 24
Peak memory 206772 kb
Host smart-981035d3-e026-4cbb-a89b-4edb093ca105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26750
51511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2675051511
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1975956697
Short name T2283
Test name
Test status
Simulation time 333875049 ps
CPU time 1.16 seconds
Started Jul 15 07:08:56 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206824 kb
Host smart-04e8a66d-577a-47f0-a2bd-42d0a86f36c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19759
56697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1975956697
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.973737465
Short name T355
Test name
Test status
Simulation time 490884981 ps
CPU time 1.2 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:18 PM PDT 24
Peak memory 206820 kb
Host smart-52988ab4-ecd4-457b-bd8a-8004a5b8977a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97373
7465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.973737465
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3803360234
Short name T1043
Test name
Test status
Simulation time 15348517383 ps
CPU time 33.88 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:52 PM PDT 24
Peak memory 207024 kb
Host smart-d5cfb0b9-58a2-4a6d-878f-0d35b9fa263b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38033
60234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3803360234
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2769635671
Short name T1200
Test name
Test status
Simulation time 402212513 ps
CPU time 1.15 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206812 kb
Host smart-7488547c-7ba1-4582-9fb8-ae383ac95e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27696
35671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2769635671
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3083807278
Short name T2519
Test name
Test status
Simulation time 136886880 ps
CPU time 0.75 seconds
Started Jul 15 07:08:59 PM PDT 24
Finished Jul 15 07:09:02 PM PDT 24
Peak memory 206808 kb
Host smart-e06592d5-9aac-43ca-a493-deb0d1f91f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30838
07278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3083807278
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2089426286
Short name T2316
Test name
Test status
Simulation time 71506936 ps
CPU time 0.7 seconds
Started Jul 15 07:08:55 PM PDT 24
Finished Jul 15 07:08:57 PM PDT 24
Peak memory 206832 kb
Host smart-36a634a3-6911-4944-94a6-d5c2bfadbba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20894
26286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2089426286
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2933528556
Short name T402
Test name
Test status
Simulation time 759127796 ps
CPU time 1.84 seconds
Started Jul 15 07:09:10 PM PDT 24
Finished Jul 15 07:09:22 PM PDT 24
Peak memory 207016 kb
Host smart-811fd02d-b90b-4a37-a5ac-ce6ffd095d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29335
28556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2933528556
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1917625364
Short name T1695
Test name
Test status
Simulation time 224182476 ps
CPU time 1.88 seconds
Started Jul 15 07:09:12 PM PDT 24
Finished Jul 15 07:09:24 PM PDT 24
Peak memory 207016 kb
Host smart-8bdb593a-07ce-41ba-8f2e-0236f242d16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19176
25364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1917625364
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2106485875
Short name T1938
Test name
Test status
Simulation time 246617447 ps
CPU time 0.95 seconds
Started Jul 15 07:09:00 PM PDT 24
Finished Jul 15 07:09:03 PM PDT 24
Peak memory 206800 kb
Host smart-2d9548b3-b586-42fa-8913-5dfc1ddaf6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21064
85875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2106485875
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.474340060
Short name T1946
Test name
Test status
Simulation time 162516814 ps
CPU time 0.77 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:17 PM PDT 24
Peak memory 206840 kb
Host smart-6f68b5e4-5cb0-4396-a42c-6034d9da2f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47434
0060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.474340060
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1749811669
Short name T1433
Test name
Test status
Simulation time 195641088 ps
CPU time 0.87 seconds
Started Jul 15 07:08:56 PM PDT 24
Finished Jul 15 07:08:59 PM PDT 24
Peak memory 206776 kb
Host smart-ff3d50d9-a06e-46d1-9539-ba5ddcbca20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17498
11669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1749811669
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.474234017
Short name T84
Test name
Test status
Simulation time 5661397850 ps
CPU time 50.32 seconds
Started Jul 15 07:08:57 PM PDT 24
Finished Jul 15 07:09:49 PM PDT 24
Peak memory 206864 kb
Host smart-5aec3aad-52c7-4767-80cc-0b0b22104a2c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=474234017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.474234017
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.445867736
Short name T1135
Test name
Test status
Simulation time 12198420300 ps
CPU time 44.06 seconds
Started Jul 15 07:09:04 PM PDT 24
Finished Jul 15 07:09:50 PM PDT 24
Peak memory 206996 kb
Host smart-19cc2f3a-bf97-443d-a8ba-67156f4c53ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44586
7736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.445867736
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.777758898
Short name T531
Test name
Test status
Simulation time 231603608 ps
CPU time 0.93 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:11 PM PDT 24
Peak memory 206756 kb
Host smart-e3c9e2b9-60d8-4b69-bfd2-0c52d65ff814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77775
8898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.777758898
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.937624524
Short name T2453
Test name
Test status
Simulation time 23380123079 ps
CPU time 23.41 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:45 PM PDT 24
Peak memory 206848 kb
Host smart-d266b804-9473-4e89-8a8d-eaeefe68c94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93762
4524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.937624524
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2528902084
Short name T2086
Test name
Test status
Simulation time 3264063739 ps
CPU time 3.5 seconds
Started Jul 15 07:09:08 PM PDT 24
Finished Jul 15 07:09:18 PM PDT 24
Peak memory 206876 kb
Host smart-e366cc13-fde1-4557-8c20-a6333f890647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
02084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2528902084
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2334830130
Short name T2470
Test name
Test status
Simulation time 12395358266 ps
CPU time 120.62 seconds
Started Jul 15 07:09:04 PM PDT 24
Finished Jul 15 07:11:08 PM PDT 24
Peak memory 207080 kb
Host smart-496a9213-12a4-436f-88f5-3869631ba547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23348
30130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2334830130
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3234529687
Short name T1644
Test name
Test status
Simulation time 2969113689 ps
CPU time 22.31 seconds
Started Jul 15 07:09:08 PM PDT 24
Finished Jul 15 07:09:38 PM PDT 24
Peak memory 207012 kb
Host smart-5822851e-74a4-4041-a46c-a3a1121eb9f1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3234529687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3234529687
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3707916958
Short name T461
Test name
Test status
Simulation time 242074191 ps
CPU time 0.95 seconds
Started Jul 15 07:09:08 PM PDT 24
Finished Jul 15 07:09:17 PM PDT 24
Peak memory 206812 kb
Host smart-0d94069a-2114-43ef-8012-25b799b7090a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3707916958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3707916958
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3674230256
Short name T2517
Test name
Test status
Simulation time 192599136 ps
CPU time 0.86 seconds
Started Jul 15 07:09:02 PM PDT 24
Finished Jul 15 07:09:05 PM PDT 24
Peak memory 206832 kb
Host smart-4ff80e9a-6157-400e-b4c1-de58848c14d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36742
30256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3674230256
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.694063985
Short name T1300
Test name
Test status
Simulation time 5076810306 ps
CPU time 130.06 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:11:28 PM PDT 24
Peak memory 207028 kb
Host smart-e0cd91ad-915f-46f1-b9d2-2b18faecef61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69406
3985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.694063985
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.668170895
Short name T732
Test name
Test status
Simulation time 6039089529 ps
CPU time 45.88 seconds
Started Jul 15 07:09:07 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 207096 kb
Host smart-bddfea2a-7ad4-4b0a-989f-162bdf8daf0f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=668170895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.668170895
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3696832589
Short name T1720
Test name
Test status
Simulation time 156738961 ps
CPU time 0.83 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:23 PM PDT 24
Peak memory 206820 kb
Host smart-02ba1af0-18cc-42c7-b7ee-8b24d0d4bc4d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3696832589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3696832589
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2574530801
Short name T2177
Test name
Test status
Simulation time 145742052 ps
CPU time 0.77 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:08 PM PDT 24
Peak memory 206828 kb
Host smart-9ab1dfef-60c8-4fda-ac08-f06b996c8506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25745
30801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2574530801
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3085311748
Short name T130
Test name
Test status
Simulation time 192488911 ps
CPU time 0.82 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:22 PM PDT 24
Peak memory 206772 kb
Host smart-9b64a34e-6e6a-4f26-85b0-b74b83a66d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
11748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3085311748
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1198025448
Short name T1045
Test name
Test status
Simulation time 198338467 ps
CPU time 0.84 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:08 PM PDT 24
Peak memory 206820 kb
Host smart-4104147f-64a0-4f2e-9fc6-46cf73ee0c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11980
25448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1198025448
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2893993594
Short name T2176
Test name
Test status
Simulation time 177217645 ps
CPU time 0.78 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:11 PM PDT 24
Peak memory 206808 kb
Host smart-53c6e993-6c85-4276-b3be-180e5dd508c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28939
93594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2893993594
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.336987697
Short name T1014
Test name
Test status
Simulation time 203684331 ps
CPU time 0.89 seconds
Started Jul 15 07:09:12 PM PDT 24
Finished Jul 15 07:09:24 PM PDT 24
Peak memory 206748 kb
Host smart-28fb8800-4598-4214-950f-080c64f7f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33698
7697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.336987697
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.4033496335
Short name T148
Test name
Test status
Simulation time 195330043 ps
CPU time 0.85 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:09:06 PM PDT 24
Peak memory 206828 kb
Host smart-651637de-3e3c-429c-aacc-113eb224b23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
96335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.4033496335
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.762747695
Short name T1151
Test name
Test status
Simulation time 221518687 ps
CPU time 0.99 seconds
Started Jul 15 07:09:07 PM PDT 24
Finished Jul 15 07:09:14 PM PDT 24
Peak memory 206780 kb
Host smart-980f79c5-556a-4813-a1bd-cac8be035045
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=762747695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.762747695
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1062923299
Short name T1458
Test name
Test status
Simulation time 155356498 ps
CPU time 0.82 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:10 PM PDT 24
Peak memory 206820 kb
Host smart-406c72af-a5f0-47a6-a03c-3e10a7c2458f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10629
23299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1062923299
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2843733929
Short name T1665
Test name
Test status
Simulation time 47286192 ps
CPU time 0.68 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:23 PM PDT 24
Peak memory 206804 kb
Host smart-3eb46cb6-6337-44e2-9274-b92cb7a779f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28437
33929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2843733929
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.259946532
Short name T2246
Test name
Test status
Simulation time 21260575192 ps
CPU time 46.08 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:55 PM PDT 24
Peak memory 207040 kb
Host smart-c1d56b59-0f30-47e9-8ffe-6eba406d1312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25994
6532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.259946532
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.196875714
Short name T673
Test name
Test status
Simulation time 144946505 ps
CPU time 0.78 seconds
Started Jul 15 07:09:13 PM PDT 24
Finished Jul 15 07:09:25 PM PDT 24
Peak memory 206792 kb
Host smart-9603cb34-befd-431a-b688-21d2304bd518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19687
5714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.196875714
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3178914982
Short name T1881
Test name
Test status
Simulation time 168135486 ps
CPU time 0.81 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:09 PM PDT 24
Peak memory 206824 kb
Host smart-44434966-c675-40d4-851d-01bb4926b435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31789
14982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3178914982
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2278814733
Short name T1475
Test name
Test status
Simulation time 164687017 ps
CPU time 0.82 seconds
Started Jul 15 07:09:08 PM PDT 24
Finished Jul 15 07:09:17 PM PDT 24
Peak memory 206824 kb
Host smart-90508d0c-32d8-48f7-bfeb-1420deba2ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22788
14733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2278814733
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.759390239
Short name T610
Test name
Test status
Simulation time 181551337 ps
CPU time 0.81 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:23 PM PDT 24
Peak memory 206812 kb
Host smart-7ac0f7f8-ad97-4722-9593-af67f76cfad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75939
0239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.759390239
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3389516868
Short name T2047
Test name
Test status
Simulation time 245225043 ps
CPU time 0.82 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:22 PM PDT 24
Peak memory 206772 kb
Host smart-1be1b3ad-2e68-40b9-b0ec-5b76b502ad27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
16868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3389516868
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2447309795
Short name T826
Test name
Test status
Simulation time 164182808 ps
CPU time 0.78 seconds
Started Jul 15 07:09:08 PM PDT 24
Finished Jul 15 07:09:16 PM PDT 24
Peak memory 206808 kb
Host smart-e6c0b7d1-dc08-45c6-ba5e-765cffe1f89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24473
09795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2447309795
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.513894664
Short name T1256
Test name
Test status
Simulation time 222760882 ps
CPU time 0.83 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:23 PM PDT 24
Peak memory 206764 kb
Host smart-dc3c624f-ce96-4ee8-9a3a-ed150730000b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51389
4664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.513894664
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3006845621
Short name T2154
Test name
Test status
Simulation time 239076396 ps
CPU time 0.92 seconds
Started Jul 15 07:09:13 PM PDT 24
Finished Jul 15 07:09:25 PM PDT 24
Peak memory 206772 kb
Host smart-9ed83815-2376-4375-b2a6-b1868eb0cb4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30068
45621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3006845621
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.4209349429
Short name T1022
Test name
Test status
Simulation time 4787672156 ps
CPU time 32.42 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:09:37 PM PDT 24
Peak memory 206764 kb
Host smart-605a77d6-af56-4c6c-8c6a-e8f445cade1e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4209349429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.4209349429
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3378073490
Short name T1467
Test name
Test status
Simulation time 181188735 ps
CPU time 0.88 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:23 PM PDT 24
Peak memory 206792 kb
Host smart-66e81c04-dbf0-439b-a3e1-d2438a2a77f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33780
73490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3378073490
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2209130935
Short name T2539
Test name
Test status
Simulation time 197522285 ps
CPU time 0.81 seconds
Started Jul 15 07:09:05 PM PDT 24
Finished Jul 15 07:09:10 PM PDT 24
Peak memory 206792 kb
Host smart-d3298fa7-7f7e-4d56-a661-49709626f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22091
30935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2209130935
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.1052716806
Short name T2235
Test name
Test status
Simulation time 1154755257 ps
CPU time 2.34 seconds
Started Jul 15 07:09:14 PM PDT 24
Finished Jul 15 07:09:30 PM PDT 24
Peak memory 206972 kb
Host smart-fd713a91-ace4-4f47-bc07-efd17e86354c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10527
16806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.1052716806
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.125426114
Short name T836
Test name
Test status
Simulation time 4763099562 ps
CPU time 130.42 seconds
Started Jul 15 07:09:03 PM PDT 24
Finished Jul 15 07:11:15 PM PDT 24
Peak memory 206832 kb
Host smart-aec346a5-8c02-4a21-be80-4407addcf2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12542
6114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.125426114
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.4171105600
Short name T2526
Test name
Test status
Simulation time 42286128 ps
CPU time 0.66 seconds
Started Jul 15 07:09:23 PM PDT 24
Finished Jul 15 07:09:45 PM PDT 24
Peak memory 206884 kb
Host smart-0c758709-4b55-4250-a80e-ecdc2f726088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4171105600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.4171105600
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2495051583
Short name T1306
Test name
Test status
Simulation time 3727784995 ps
CPU time 4.53 seconds
Started Jul 15 07:09:19 PM PDT 24
Finished Jul 15 07:09:41 PM PDT 24
Peak memory 206856 kb
Host smart-40f0f09d-793c-489e-99ec-ca7f89c7999f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2495051583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2495051583
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2878459370
Short name T2392
Test name
Test status
Simulation time 13314721939 ps
CPU time 14.52 seconds
Started Jul 15 07:09:13 PM PDT 24
Finished Jul 15 07:09:39 PM PDT 24
Peak memory 206772 kb
Host smart-441e9c1b-b9e0-4fc7-a207-49282142d9fa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2878459370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2878459370
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2324916855
Short name T484
Test name
Test status
Simulation time 23406753930 ps
CPU time 22.86 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:40 PM PDT 24
Peak memory 206880 kb
Host smart-5ed8fc58-971a-4799-9a50-d65b253a675e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2324916855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.2324916855
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2195873566
Short name T2647
Test name
Test status
Simulation time 152624852 ps
CPU time 0.79 seconds
Started Jul 15 07:09:12 PM PDT 24
Finished Jul 15 07:09:24 PM PDT 24
Peak memory 206968 kb
Host smart-245c5333-c27c-44a9-9b77-489774f0c9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21958
73566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2195873566
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1890247567
Short name T2439
Test name
Test status
Simulation time 149196495 ps
CPU time 0.78 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:17 PM PDT 24
Peak memory 206796 kb
Host smart-1b544b5a-c48a-4382-99e6-3978c44903da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18902
47567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1890247567
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.759148233
Short name T2385
Test name
Test status
Simulation time 152826826 ps
CPU time 0.81 seconds
Started Jul 15 07:09:13 PM PDT 24
Finished Jul 15 07:09:25 PM PDT 24
Peak memory 206784 kb
Host smart-8a732a9b-2072-4c32-9d27-b9629fb9c6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75914
8233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.759148233
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.269393013
Short name T1429
Test name
Test status
Simulation time 1386904216 ps
CPU time 3.1 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:24 PM PDT 24
Peak memory 206984 kb
Host smart-cce9cb2b-856c-491d-84c8-c9448e662102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26939
3013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.269393013
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.65242750
Short name T2547
Test name
Test status
Simulation time 7410274394 ps
CPU time 14.47 seconds
Started Jul 15 07:09:10 PM PDT 24
Finished Jul 15 07:09:42 PM PDT 24
Peak memory 207080 kb
Host smart-8ea6006e-6940-4437-a3fd-a73da5c0ec50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65242
750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.65242750
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2649893632
Short name T740
Test name
Test status
Simulation time 367541057 ps
CPU time 1.18 seconds
Started Jul 15 07:09:20 PM PDT 24
Finished Jul 15 07:09:39 PM PDT 24
Peak memory 206824 kb
Host smart-50d421c5-1c57-46f6-bee2-c8c5908f448e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
93632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2649893632
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1331155219
Short name T1582
Test name
Test status
Simulation time 145953785 ps
CPU time 0.79 seconds
Started Jul 15 07:09:14 PM PDT 24
Finished Jul 15 07:09:28 PM PDT 24
Peak memory 206772 kb
Host smart-fcf1bb6d-eb92-46ba-ad71-f59e7d5e9b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311
55219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1331155219
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3884582012
Short name T1590
Test name
Test status
Simulation time 69848452 ps
CPU time 0.72 seconds
Started Jul 15 07:09:10 PM PDT 24
Finished Jul 15 07:09:20 PM PDT 24
Peak memory 206812 kb
Host smart-ddf9c38a-ca95-47cf-95b8-8946f4816f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38845
82012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3884582012
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.536769634
Short name T2403
Test name
Test status
Simulation time 888697520 ps
CPU time 2.43 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:21 PM PDT 24
Peak memory 206952 kb
Host smart-55c14fb2-b624-4ea0-b8cd-7f0e1e67c239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53676
9634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.536769634
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.394667727
Short name T441
Test name
Test status
Simulation time 282848415 ps
CPU time 1.62 seconds
Started Jul 15 07:09:18 PM PDT 24
Finished Jul 15 07:09:36 PM PDT 24
Peak memory 206984 kb
Host smart-ea25c968-96a3-40a3-872d-966e405e9780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39466
7727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.394667727
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2716944466
Short name T796
Test name
Test status
Simulation time 163338598 ps
CPU time 0.91 seconds
Started Jul 15 07:09:10 PM PDT 24
Finished Jul 15 07:09:20 PM PDT 24
Peak memory 206824 kb
Host smart-ee8c7d29-1499-4a1c-9344-a845498da393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27169
44466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2716944466
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1110103075
Short name T2003
Test name
Test status
Simulation time 186875281 ps
CPU time 0.82 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:09:25 PM PDT 24
Peak memory 206832 kb
Host smart-f1585f8d-ae0d-4522-bd1c-7bd1fcdd41a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101
03075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1110103075
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3868284121
Short name T325
Test name
Test status
Simulation time 234564053 ps
CPU time 0.96 seconds
Started Jul 15 07:09:12 PM PDT 24
Finished Jul 15 07:09:24 PM PDT 24
Peak memory 206820 kb
Host smart-f7effdcb-23a1-4d2a-a082-9b98df4b05b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38682
84121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3868284121
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.455671176
Short name T2343
Test name
Test status
Simulation time 210444901 ps
CPU time 0.84 seconds
Started Jul 15 07:09:14 PM PDT 24
Finished Jul 15 07:09:28 PM PDT 24
Peak memory 206772 kb
Host smart-cf985277-7e58-45e7-964c-5e5ce06abf9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45567
1176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.455671176
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.242039517
Short name T477
Test name
Test status
Simulation time 23319508443 ps
CPU time 22.51 seconds
Started Jul 15 07:09:13 PM PDT 24
Finished Jul 15 07:09:48 PM PDT 24
Peak memory 206884 kb
Host smart-7927f1b2-dd59-452f-9fc7-ca87cf2b1602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
9517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.242039517
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1272644098
Short name T2257
Test name
Test status
Simulation time 3274154038 ps
CPU time 3.58 seconds
Started Jul 15 07:09:11 PM PDT 24
Finished Jul 15 07:09:25 PM PDT 24
Peak memory 206820 kb
Host smart-882c89bd-8bc9-4f2b-89c2-8b96a99a4144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
44098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1272644098
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1601666424
Short name T1127
Test name
Test status
Simulation time 8442036788 ps
CPU time 79.23 seconds
Started Jul 15 07:09:09 PM PDT 24
Finished Jul 15 07:10:37 PM PDT 24
Peak memory 207072 kb
Host smart-77c2191f-64dc-4e46-88dc-2932668f1949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16016
66424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1601666424
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3067856107
Short name T2160
Test name
Test status
Simulation time 4102470515 ps
CPU time 110.74 seconds
Started Jul 15 07:09:18 PM PDT 24
Finished Jul 15 07:11:23 PM PDT 24
Peak memory 206896 kb
Host smart-32d4ce3a-b3cb-474c-8f8b-a8cd9e245ccc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3067856107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3067856107
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3028349422
Short name T2147
Test name
Test status
Simulation time 273743242 ps
CPU time 0.97 seconds
Started Jul 15 07:09:20 PM PDT 24
Finished Jul 15 07:09:39 PM PDT 24
Peak memory 206812 kb
Host smart-b9d05164-591d-4680-905d-402c8fab556e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3028349422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3028349422
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.4040302337
Short name T497
Test name
Test status
Simulation time 241520441 ps
CPU time 0.89 seconds
Started Jul 15 07:09:18 PM PDT 24
Finished Jul 15 07:09:34 PM PDT 24
Peak memory 206828 kb
Host smart-4eeebd6f-e9d1-46e9-b306-0314b456ff2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40403
02337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.4040302337
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1592105751
Short name T733
Test name
Test status
Simulation time 4761975175 ps
CPU time 129.5 seconds
Started Jul 15 07:09:17 PM PDT 24
Finished Jul 15 07:11:41 PM PDT 24
Peak memory 207036 kb
Host smart-db83622f-02c1-4697-8bff-adcd2538c59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15921
05751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1592105751
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3888383562
Short name T1567
Test name
Test status
Simulation time 3612467082 ps
CPU time 33.43 seconds
Started Jul 15 07:09:20 PM PDT 24
Finished Jul 15 07:10:11 PM PDT 24
Peak memory 207024 kb
Host smart-a1345f75-79e2-4335-87a2-ad6c2abed02a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3888383562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3888383562
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3919918043
Short name T2250
Test name
Test status
Simulation time 160039585 ps
CPU time 0.8 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:09:45 PM PDT 24
Peak memory 206824 kb
Host smart-e724d20a-b9d5-4b67-9e67-d23d6391a46b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3919918043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3919918043
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1244122346
Short name T1808
Test name
Test status
Simulation time 147546564 ps
CPU time 0.8 seconds
Started Jul 15 07:09:23 PM PDT 24
Finished Jul 15 07:09:43 PM PDT 24
Peak memory 206792 kb
Host smart-9d62231c-e796-4e8d-9c1d-3e3e721f5aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
22346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1244122346
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.14349741
Short name T33
Test name
Test status
Simulation time 211524249 ps
CPU time 0.85 seconds
Started Jul 15 07:09:28 PM PDT 24
Finished Jul 15 07:09:53 PM PDT 24
Peak memory 206800 kb
Host smart-273a916b-0c1b-4d73-a824-6c0b8951824c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14349
741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.14349741
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1048303081
Short name T364
Test name
Test status
Simulation time 193203572 ps
CPU time 0.85 seconds
Started Jul 15 07:09:20 PM PDT 24
Finished Jul 15 07:09:39 PM PDT 24
Peak memory 206808 kb
Host smart-5b68425e-9979-4fbc-ba60-e374111be8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10483
03081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1048303081
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.729081848
Short name T853
Test name
Test status
Simulation time 234561970 ps
CPU time 0.84 seconds
Started Jul 15 07:09:16 PM PDT 24
Finished Jul 15 07:09:31 PM PDT 24
Peak memory 206812 kb
Host smart-69e7d2af-c0e6-4538-a275-84e5ff573712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72908
1848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.729081848
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.400147637
Short name T680
Test name
Test status
Simulation time 194583122 ps
CPU time 0.84 seconds
Started Jul 15 07:09:22 PM PDT 24
Finished Jul 15 07:09:41 PM PDT 24
Peak memory 206824 kb
Host smart-1ac92872-2a86-441e-be19-b255022eb1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40014
7637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.400147637
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.346083153
Short name T2611
Test name
Test status
Simulation time 156206559 ps
CPU time 0.78 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:09:47 PM PDT 24
Peak memory 206824 kb
Host smart-4e00184f-f352-40b5-a4df-4200f424b76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608
3153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.346083153
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1106484804
Short name T1194
Test name
Test status
Simulation time 273301220 ps
CPU time 1.13 seconds
Started Jul 15 07:09:26 PM PDT 24
Finished Jul 15 07:09:50 PM PDT 24
Peak memory 206812 kb
Host smart-6ae808e1-b7f1-434d-904e-6fbb1e681fa0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1106484804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1106484804
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1988088479
Short name T175
Test name
Test status
Simulation time 163817959 ps
CPU time 0.84 seconds
Started Jul 15 07:09:28 PM PDT 24
Finished Jul 15 07:09:55 PM PDT 24
Peak memory 206816 kb
Host smart-38bdb547-9356-4462-950e-cfdbe38c6d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19880
88479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1988088479
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1935782663
Short name T2076
Test name
Test status
Simulation time 39359065 ps
CPU time 0.65 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:09:45 PM PDT 24
Peak memory 206776 kb
Host smart-b043d1e5-c61c-4d9e-bbae-ae00ea84a1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19357
82663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1935782663
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.753997395
Short name T842
Test name
Test status
Simulation time 20176453835 ps
CPU time 42.68 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 207060 kb
Host smart-f25f9fb2-c80d-4481-bebe-d4bbf7c9362f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75399
7395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.753997395
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3792088779
Short name T1444
Test name
Test status
Simulation time 180716558 ps
CPU time 0.87 seconds
Started Jul 15 07:09:19 PM PDT 24
Finished Jul 15 07:09:35 PM PDT 24
Peak memory 206848 kb
Host smart-4d57c54a-f249-41cf-98dd-ca4fbc59af5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37920
88779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3792088779
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3983452001
Short name T2459
Test name
Test status
Simulation time 234779428 ps
CPU time 0.91 seconds
Started Jul 15 07:09:16 PM PDT 24
Finished Jul 15 07:09:31 PM PDT 24
Peak memory 206760 kb
Host smart-89090ff6-fd6e-4b6e-84bf-c702631b614a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39834
52001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3983452001
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.83056514
Short name T1608
Test name
Test status
Simulation time 158667250 ps
CPU time 0.77 seconds
Started Jul 15 07:09:19 PM PDT 24
Finished Jul 15 07:09:37 PM PDT 24
Peak memory 206816 kb
Host smart-d17d760c-0127-4bae-83c4-ce67957f00f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83056
514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.83056514
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2711689695
Short name T2130
Test name
Test status
Simulation time 173488466 ps
CPU time 0.82 seconds
Started Jul 15 07:09:18 PM PDT 24
Finished Jul 15 07:09:35 PM PDT 24
Peak memory 206772 kb
Host smart-e62c4c2b-055b-464d-b284-5c8fd8d80a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27116
89695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2711689695
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.4224179106
Short name T23
Test name
Test status
Simulation time 194864147 ps
CPU time 0.83 seconds
Started Jul 15 07:09:19 PM PDT 24
Finished Jul 15 07:09:35 PM PDT 24
Peak memory 206700 kb
Host smart-fda5e3bb-618b-4650-bd14-09f835a53773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42241
79106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.4224179106
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1474709116
Short name T1687
Test name
Test status
Simulation time 164921005 ps
CPU time 0.78 seconds
Started Jul 15 07:09:17 PM PDT 24
Finished Jul 15 07:09:32 PM PDT 24
Peak memory 206800 kb
Host smart-786efeae-8c9f-477d-bbd6-dd017bd5e3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14747
09116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1474709116
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2159739026
Short name T2445
Test name
Test status
Simulation time 236083152 ps
CPU time 0.83 seconds
Started Jul 15 07:09:19 PM PDT 24
Finished Jul 15 07:09:37 PM PDT 24
Peak memory 206812 kb
Host smart-6c86c042-7185-4e83-b84a-8f1dc3e46f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
39026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2159739026
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1353177229
Short name T780
Test name
Test status
Simulation time 250649928 ps
CPU time 1.01 seconds
Started Jul 15 07:09:26 PM PDT 24
Finished Jul 15 07:09:50 PM PDT 24
Peak memory 206840 kb
Host smart-e2d96711-99fe-41e8-b0e4-043cbac55ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
77229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1353177229
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1602234452
Short name T1365
Test name
Test status
Simulation time 5561624512 ps
CPU time 51.74 seconds
Started Jul 15 07:09:17 PM PDT 24
Finished Jul 15 07:10:23 PM PDT 24
Peak memory 207132 kb
Host smart-3d13117e-9105-48e0-b726-6153c867f261
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1602234452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1602234452
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3309271038
Short name T1890
Test name
Test status
Simulation time 179467516 ps
CPU time 0.79 seconds
Started Jul 15 07:09:38 PM PDT 24
Finished Jul 15 07:10:18 PM PDT 24
Peak memory 206800 kb
Host smart-02894167-ba32-4d36-95be-76c7bb7e2079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33092
71038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3309271038
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3754026011
Short name T2576
Test name
Test status
Simulation time 173801382 ps
CPU time 0.78 seconds
Started Jul 15 07:09:26 PM PDT 24
Finished Jul 15 07:09:50 PM PDT 24
Peak memory 206788 kb
Host smart-4e87d3bd-1ea4-47fd-ad48-430dbdd103a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37540
26011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3754026011
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1781794809
Short name T968
Test name
Test status
Simulation time 357426887 ps
CPU time 1.14 seconds
Started Jul 15 07:09:17 PM PDT 24
Finished Jul 15 07:09:34 PM PDT 24
Peak memory 206808 kb
Host smart-ab83358f-d8cf-4aeb-84e7-2b769eca404c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17817
94809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1781794809
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3983957327
Short name T1297
Test name
Test status
Simulation time 7595432063 ps
CPU time 51.76 seconds
Started Jul 15 07:09:28 PM PDT 24
Finished Jul 15 07:10:44 PM PDT 24
Peak memory 207056 kb
Host smart-6012180b-1f78-4a26-b793-1028eb2a12cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39839
57327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3983957327
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3366157297
Short name T2281
Test name
Test status
Simulation time 41965683 ps
CPU time 0.67 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:03:40 PM PDT 24
Peak memory 206792 kb
Host smart-2d1da156-3e52-4e41-9223-39039602217f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3366157297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3366157297
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3299932297
Short name T1153
Test name
Test status
Simulation time 4154207611 ps
CPU time 5.26 seconds
Started Jul 15 07:03:24 PM PDT 24
Finished Jul 15 07:03:30 PM PDT 24
Peak memory 207060 kb
Host smart-43d4100b-a794-486a-a59a-bd5915916db0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3299932297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.3299932297
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1197875945
Short name T1402
Test name
Test status
Simulation time 13485114031 ps
CPU time 13.44 seconds
Started Jul 15 07:03:24 PM PDT 24
Finished Jul 15 07:03:38 PM PDT 24
Peak memory 207096 kb
Host smart-69d8b2ea-16b7-4086-8926-912028d6e7e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1197875945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1197875945
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.4174432639
Short name T718
Test name
Test status
Simulation time 23383516441 ps
CPU time 21.49 seconds
Started Jul 15 07:03:28 PM PDT 24
Finished Jul 15 07:03:50 PM PDT 24
Peak memory 207096 kb
Host smart-603cc2f0-c06f-472c-a753-cb7a8e802340
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4174432639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.4174432639
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.225430800
Short name T1133
Test name
Test status
Simulation time 183193347 ps
CPU time 0.81 seconds
Started Jul 15 07:03:25 PM PDT 24
Finished Jul 15 07:03:26 PM PDT 24
Peak memory 206808 kb
Host smart-5807868c-7a4b-4e14-bd39-fe61a42f80b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22543
0800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.225430800
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3094071529
Short name T45
Test name
Test status
Simulation time 163887369 ps
CPU time 0.87 seconds
Started Jul 15 07:03:25 PM PDT 24
Finished Jul 15 07:03:26 PM PDT 24
Peak memory 206824 kb
Host smart-579769d8-881b-4039-bb17-6cfecef2170d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30940
71529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3094071529
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.305966131
Short name T77
Test name
Test status
Simulation time 133646226 ps
CPU time 0.73 seconds
Started Jul 15 07:03:26 PM PDT 24
Finished Jul 15 07:03:28 PM PDT 24
Peak memory 206804 kb
Host smart-6604d190-a7a1-46e1-ba27-f45cc8ef2ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30596
6131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.305966131
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3343375203
Short name T2164
Test name
Test status
Simulation time 161736164 ps
CPU time 0.77 seconds
Started Jul 15 07:03:26 PM PDT 24
Finished Jul 15 07:03:28 PM PDT 24
Peak memory 206808 kb
Host smart-b3833739-1af6-4d67-8ba2-d8036acecf02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33433
75203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3343375203
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2707926471
Short name T76
Test name
Test status
Simulation time 238813330 ps
CPU time 1 seconds
Started Jul 15 07:03:25 PM PDT 24
Finished Jul 15 07:03:26 PM PDT 24
Peak memory 206812 kb
Host smart-3d64a396-721d-412d-b831-0ecdda86aeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27079
26471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2707926471
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1232429613
Short name T982
Test name
Test status
Simulation time 1439390314 ps
CPU time 3.84 seconds
Started Jul 15 07:03:27 PM PDT 24
Finished Jul 15 07:03:31 PM PDT 24
Peak memory 207024 kb
Host smart-8514b247-7053-4235-b4a9-df67fa33eb36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12324
29613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1232429613
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1605002366
Short name T1392
Test name
Test status
Simulation time 17471683794 ps
CPU time 38.09 seconds
Started Jul 15 07:03:24 PM PDT 24
Finished Jul 15 07:04:02 PM PDT 24
Peak memory 207088 kb
Host smart-fd6ef079-4619-4f7f-a525-6f578aa9b63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16050
02366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1605002366
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.81024417
Short name T1837
Test name
Test status
Simulation time 335747262 ps
CPU time 1.13 seconds
Started Jul 15 07:03:26 PM PDT 24
Finished Jul 15 07:03:28 PM PDT 24
Peak memory 206844 kb
Host smart-5c9c03ae-458d-4906-a529-10e573eda92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81024
417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.81024417
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1389918341
Short name T1523
Test name
Test status
Simulation time 153819204 ps
CPU time 0.78 seconds
Started Jul 15 07:03:33 PM PDT 24
Finished Jul 15 07:03:35 PM PDT 24
Peak memory 206804 kb
Host smart-9eb0b2a3-8248-4089-823a-9c29cceaecb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13899
18341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1389918341
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2972998474
Short name T1647
Test name
Test status
Simulation time 55477331 ps
CPU time 0.69 seconds
Started Jul 15 07:03:25 PM PDT 24
Finished Jul 15 07:03:26 PM PDT 24
Peak memory 206804 kb
Host smart-6c1e625c-8d33-4e2c-94b8-0222851d84fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29729
98474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2972998474
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2818356383
Short name T1227
Test name
Test status
Simulation time 807378359 ps
CPU time 1.94 seconds
Started Jul 15 07:03:24 PM PDT 24
Finished Jul 15 07:03:27 PM PDT 24
Peak memory 206932 kb
Host smart-fa933a1c-09f1-4df2-aa8c-722ca6f45339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28183
56383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2818356383
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3477322565
Short name T655
Test name
Test status
Simulation time 147134978 ps
CPU time 1.09 seconds
Started Jul 15 07:03:30 PM PDT 24
Finished Jul 15 07:03:32 PM PDT 24
Peak memory 206948 kb
Host smart-0ffc97c0-42a0-40f0-bb2f-6ca183db87a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34773
22565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3477322565
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2569781339
Short name T395
Test name
Test status
Simulation time 82199455882 ps
CPU time 108.67 seconds
Started Jul 15 07:03:33 PM PDT 24
Finished Jul 15 07:05:22 PM PDT 24
Peak memory 206996 kb
Host smart-038e12f2-d65c-4759-aedc-9174554e9a21
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2569781339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2569781339
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.1574550677
Short name T2012
Test name
Test status
Simulation time 89305391355 ps
CPU time 127.67 seconds
Started Jul 15 07:03:30 PM PDT 24
Finished Jul 15 07:05:39 PM PDT 24
Peak memory 207016 kb
Host smart-0f44ff0d-d101-4d2f-a61e-74589221260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574550677 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.1574550677
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.2746493842
Short name T490
Test name
Test status
Simulation time 120149342680 ps
CPU time 145.98 seconds
Started Jul 15 07:03:34 PM PDT 24
Finished Jul 15 07:06:00 PM PDT 24
Peak memory 207068 kb
Host smart-d376b985-475f-4058-9d73-87468fa6fc8c
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2746493842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.2746493842
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.4099381759
Short name T854
Test name
Test status
Simulation time 119932063682 ps
CPU time 167.74 seconds
Started Jul 15 07:03:32 PM PDT 24
Finished Jul 15 07:06:21 PM PDT 24
Peak memory 207036 kb
Host smart-04118066-429d-4ca4-a6fc-dcf9776e2a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099381759 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.4099381759
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.291665111
Short name T1675
Test name
Test status
Simulation time 114155004953 ps
CPU time 165.65 seconds
Started Jul 15 07:03:31 PM PDT 24
Finished Jul 15 07:06:18 PM PDT 24
Peak memory 207012 kb
Host smart-edb4e16c-4e00-4fc0-b358-241c84f2dee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29166
5111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.291665111
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.912895149
Short name T334
Test name
Test status
Simulation time 268804687 ps
CPU time 0.89 seconds
Started Jul 15 07:03:31 PM PDT 24
Finished Jul 15 07:03:33 PM PDT 24
Peak memory 206808 kb
Host smart-72f3be82-0b6e-42f4-a8c9-1013d6ee3635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91289
5149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.912895149
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3964537297
Short name T1805
Test name
Test status
Simulation time 132315942 ps
CPU time 0.73 seconds
Started Jul 15 07:03:31 PM PDT 24
Finished Jul 15 07:03:32 PM PDT 24
Peak memory 206820 kb
Host smart-0a19abd5-510c-442f-acbf-ff452d3440f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39645
37297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3964537297
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3379280468
Short name T818
Test name
Test status
Simulation time 217409868 ps
CPU time 1.08 seconds
Started Jul 15 07:03:32 PM PDT 24
Finished Jul 15 07:03:34 PM PDT 24
Peak memory 206812 kb
Host smart-7150f10f-ab5c-4665-8852-19fff84efa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33792
80468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3379280468
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3318038516
Short name T1839
Test name
Test status
Simulation time 6637046700 ps
CPU time 58.98 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:04:36 PM PDT 24
Peak memory 207092 kb
Host smart-1686eec0-b36c-4e5b-a9bc-ba3905ab504b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3318038516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3318038516
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3570225341
Short name T2264
Test name
Test status
Simulation time 6592392594 ps
CPU time 58.09 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:04:36 PM PDT 24
Peak memory 206804 kb
Host smart-e445a119-a217-42b6-979b-6122f032aa10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35702
25341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3570225341
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1812717039
Short name T2739
Test name
Test status
Simulation time 217406167 ps
CPU time 0.85 seconds
Started Jul 15 07:03:31 PM PDT 24
Finished Jul 15 07:03:33 PM PDT 24
Peak memory 206788 kb
Host smart-a2e71875-8a40-4986-830d-1b75d322078f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
17039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1812717039
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.861975495
Short name T2261
Test name
Test status
Simulation time 23308177287 ps
CPU time 20.43 seconds
Started Jul 15 07:03:31 PM PDT 24
Finished Jul 15 07:03:52 PM PDT 24
Peak memory 206844 kb
Host smart-e01bb483-ea01-4177-aedb-a067f4db92e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86197
5495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.861975495
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2055017095
Short name T1310
Test name
Test status
Simulation time 3290870311 ps
CPU time 3.52 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:03:41 PM PDT 24
Peak memory 206684 kb
Host smart-7e73b951-45b0-43b3-82ae-a34494929b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20550
17095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2055017095
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2329721498
Short name T307
Test name
Test status
Simulation time 13224362743 ps
CPU time 103.75 seconds
Started Jul 15 07:03:32 PM PDT 24
Finished Jul 15 07:05:17 PM PDT 24
Peak memory 207096 kb
Host smart-c4c68ad3-00f7-4b4e-b3d2-429f1a492eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23297
21498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2329721498
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2169192675
Short name T2149
Test name
Test status
Simulation time 3757468341 ps
CPU time 26.83 seconds
Started Jul 15 07:03:33 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 207024 kb
Host smart-2f9163b4-5ef4-4bbb-9bc8-b1a1cd13ec95
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2169192675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2169192675
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1600679835
Short name T729
Test name
Test status
Simulation time 284427894 ps
CPU time 0.92 seconds
Started Jul 15 07:03:32 PM PDT 24
Finished Jul 15 07:03:34 PM PDT 24
Peak memory 206824 kb
Host smart-d7eb58b4-1fb5-45cd-905f-482c5b375c58
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1600679835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1600679835
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2587459700
Short name T745
Test name
Test status
Simulation time 207371077 ps
CPU time 0.86 seconds
Started Jul 15 07:03:34 PM PDT 24
Finished Jul 15 07:03:35 PM PDT 24
Peak memory 206800 kb
Host smart-04c13b58-0b08-4d0e-bfca-b88d3f86835b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25874
59700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2587459700
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2959564826
Short name T1225
Test name
Test status
Simulation time 4554794028 ps
CPU time 44.7 seconds
Started Jul 15 07:03:32 PM PDT 24
Finished Jul 15 07:04:17 PM PDT 24
Peak memory 207040 kb
Host smart-7961b0d9-d42c-40a2-b304-ba059c2a2c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29595
64826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2959564826
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2487503270
Short name T1071
Test name
Test status
Simulation time 3155617617 ps
CPU time 31.19 seconds
Started Jul 15 07:03:31 PM PDT 24
Finished Jul 15 07:04:03 PM PDT 24
Peak memory 207040 kb
Host smart-265efa60-ced6-4956-ad48-5ec3ec4302eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2487503270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2487503270
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.129937831
Short name T316
Test name
Test status
Simulation time 158259560 ps
CPU time 0.79 seconds
Started Jul 15 07:03:33 PM PDT 24
Finished Jul 15 07:03:35 PM PDT 24
Peak memory 206820 kb
Host smart-e5f4084f-291b-4091-aaf8-7b47807aad9e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=129937831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.129937831
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2453127627
Short name T604
Test name
Test status
Simulation time 169179956 ps
CPU time 0.81 seconds
Started Jul 15 07:03:31 PM PDT 24
Finished Jul 15 07:03:32 PM PDT 24
Peak memory 206708 kb
Host smart-5f78a367-50fc-4ba1-8f41-1a85a1513bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24531
27627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2453127627
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3904152688
Short name T114
Test name
Test status
Simulation time 225068293 ps
CPU time 0.91 seconds
Started Jul 15 07:03:32 PM PDT 24
Finished Jul 15 07:03:34 PM PDT 24
Peak memory 206816 kb
Host smart-e100c0b3-fa69-4f25-a15e-5580652877a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39041
52688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3904152688
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.708719232
Short name T1274
Test name
Test status
Simulation time 227897304 ps
CPU time 0.89 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:03:39 PM PDT 24
Peak memory 206376 kb
Host smart-72900174-0115-4a28-9b9d-7d2632e948d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70871
9232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.708719232
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1164194766
Short name T396
Test name
Test status
Simulation time 175760468 ps
CPU time 0.82 seconds
Started Jul 15 07:03:30 PM PDT 24
Finished Jul 15 07:03:32 PM PDT 24
Peak memory 206816 kb
Host smart-9004f0a0-4ef1-492d-b41a-bc050bdc9942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11641
94766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1164194766
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3813718014
Short name T926
Test name
Test status
Simulation time 187366094 ps
CPU time 0.83 seconds
Started Jul 15 07:03:30 PM PDT 24
Finished Jul 15 07:03:31 PM PDT 24
Peak memory 206820 kb
Host smart-2088e0c9-a5ae-4d73-b65d-51de8a034b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137
18014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3813718014
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3701491482
Short name T2524
Test name
Test status
Simulation time 152409457 ps
CPU time 0.8 seconds
Started Jul 15 07:03:32 PM PDT 24
Finished Jul 15 07:03:34 PM PDT 24
Peak memory 206840 kb
Host smart-ca4f231b-b05b-43e0-83e0-e4c9ffbb78cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37014
91482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3701491482
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1573855486
Short name T879
Test name
Test status
Simulation time 223126819 ps
CPU time 0.92 seconds
Started Jul 15 07:03:31 PM PDT 24
Finished Jul 15 07:03:32 PM PDT 24
Peak memory 206836 kb
Host smart-7ba15355-fdc3-4cff-a281-49300af3c5b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1573855486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1573855486
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3539928338
Short name T2303
Test name
Test status
Simulation time 201847377 ps
CPU time 0.95 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:03:39 PM PDT 24
Peak memory 206420 kb
Host smart-59a7ba18-eef1-45b8-93d4-ba74085e9059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35399
28338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3539928338
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2142516368
Short name T1347
Test name
Test status
Simulation time 151629321 ps
CPU time 0.74 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:03:37 PM PDT 24
Peak memory 206788 kb
Host smart-075fc0ab-8cd4-4fb0-bba5-acd820ec40b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21425
16368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2142516368
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3835766816
Short name T2020
Test name
Test status
Simulation time 64324797 ps
CPU time 0.69 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:03:40 PM PDT 24
Peak memory 206800 kb
Host smart-a78b3b7d-cf13-4bab-93d6-0062955fe41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38357
66816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3835766816
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1140696250
Short name T2302
Test name
Test status
Simulation time 11500452906 ps
CPU time 23.99 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 207084 kb
Host smart-a0b3e5bd-ccf9-42b8-ac6f-137997e1fb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11406
96250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1140696250
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.737752855
Short name T406
Test name
Test status
Simulation time 187980256 ps
CPU time 0.86 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:03:37 PM PDT 24
Peak memory 206780 kb
Host smart-e816ecd3-e723-45f7-920d-4b2358558d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73775
2855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.737752855
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.450170000
Short name T1142
Test name
Test status
Simulation time 253482722 ps
CPU time 0.99 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:03:37 PM PDT 24
Peak memory 206792 kb
Host smart-c80e39a9-16f6-474c-a494-7186329cbf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45017
0000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.450170000
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1115251503
Short name T154
Test name
Test status
Simulation time 13661337314 ps
CPU time 88.98 seconds
Started Jul 15 07:03:40 PM PDT 24
Finished Jul 15 07:05:10 PM PDT 24
Peak memory 207008 kb
Host smart-dbd523c6-3cd5-464a-8416-fd24a2445d1f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1115251503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1115251503
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2876546864
Short name T161
Test name
Test status
Simulation time 7399771843 ps
CPU time 95.13 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:05:13 PM PDT 24
Peak memory 207036 kb
Host smart-692b3018-192b-4c81-bcb0-f46dfcbd6ce4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2876546864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2876546864
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1165718790
Short name T628
Test name
Test status
Simulation time 14028024149 ps
CPU time 73.99 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:04:53 PM PDT 24
Peak memory 207004 kb
Host smart-3fa912f6-1e73-41f5-b784-b4254dc4251c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1165718790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1165718790
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1279446838
Short name T513
Test name
Test status
Simulation time 239201387 ps
CPU time 0.91 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:03:40 PM PDT 24
Peak memory 206708 kb
Host smart-13375461-3fb2-4739-89b8-1d2b0d4f09b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12794
46838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1279446838
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3231216335
Short name T677
Test name
Test status
Simulation time 164420255 ps
CPU time 0.79 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:03:38 PM PDT 24
Peak memory 206808 kb
Host smart-0fe974ff-e869-4ee5-92c4-47d1f04b3d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32312
16335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3231216335
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1208649770
Short name T1757
Test name
Test status
Simulation time 247646584 ps
CPU time 0.86 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:03:39 PM PDT 24
Peak memory 206824 kb
Host smart-c80e989c-b659-4f93-9b7a-45ad3aaac57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12086
49770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1208649770
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1959628980
Short name T70
Test name
Test status
Simulation time 180651426 ps
CPU time 0.79 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:03:40 PM PDT 24
Peak memory 206772 kb
Host smart-2ed94991-e413-4095-864a-7c8abdfab547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19596
28980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1959628980
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.4085611697
Short name T179
Test name
Test status
Simulation time 1035545222 ps
CPU time 1.76 seconds
Started Jul 15 07:03:35 PM PDT 24
Finished Jul 15 07:03:37 PM PDT 24
Peak memory 225508 kb
Host smart-aedbc8e2-2796-433b-9c6e-e388dfb7bcc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4085611697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.4085611697
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2793411965
Short name T47
Test name
Test status
Simulation time 332894537 ps
CPU time 1.06 seconds
Started Jul 15 07:03:39 PM PDT 24
Finished Jul 15 07:03:41 PM PDT 24
Peak memory 206816 kb
Host smart-bc8c6918-7c0b-4d04-b225-d2a024a10e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27934
11965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2793411965
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.630869118
Short name T1841
Test name
Test status
Simulation time 208304166 ps
CPU time 0.87 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:03:38 PM PDT 24
Peak memory 206796 kb
Host smart-48237caf-bc9d-4fb5-b3c5-56b94bc49719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63086
9118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.630869118
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1233791665
Short name T457
Test name
Test status
Simulation time 163895969 ps
CPU time 0.82 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:03:38 PM PDT 24
Peak memory 206800 kb
Host smart-ee66bc1f-e0da-4928-9bef-d30be925421b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12337
91665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1233791665
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.717896554
Short name T2072
Test name
Test status
Simulation time 157602130 ps
CPU time 0.77 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:03:40 PM PDT 24
Peak memory 206808 kb
Host smart-dff48620-e32d-47c4-9d90-0c28d67a6b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71789
6554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.717896554
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1761965057
Short name T2469
Test name
Test status
Simulation time 203598785 ps
CPU time 0.92 seconds
Started Jul 15 07:03:40 PM PDT 24
Finished Jul 15 07:03:42 PM PDT 24
Peak memory 206804 kb
Host smart-2d3ff107-a776-4e31-829e-7e1e79861ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17619
65057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1761965057
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.4182685678
Short name T2586
Test name
Test status
Simulation time 6100395813 ps
CPU time 170.52 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:06:27 PM PDT 24
Peak memory 207004 kb
Host smart-1e4140f1-fecb-4fe6-9a02-ac7fab402cc0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4182685678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.4182685678
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3155556568
Short name T2188
Test name
Test status
Simulation time 177874758 ps
CPU time 0.8 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:03:40 PM PDT 24
Peak memory 206736 kb
Host smart-5c6f9288-2600-442e-92f8-785b0500dde4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31555
56568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3155556568
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3799666506
Short name T2332
Test name
Test status
Simulation time 177906920 ps
CPU time 0.82 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:03:39 PM PDT 24
Peak memory 206772 kb
Host smart-1accf244-4104-4b47-87f2-f7374b5b5fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
66506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3799666506
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2008494746
Short name T2708
Test name
Test status
Simulation time 669914901 ps
CPU time 1.63 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:03:41 PM PDT 24
Peak memory 206804 kb
Host smart-8f3ef61f-783f-4bcd-97bb-06347def9a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20084
94746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2008494746
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.881128164
Short name T1163
Test name
Test status
Simulation time 6765127177 ps
CPU time 60.89 seconds
Started Jul 15 07:03:39 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 207020 kb
Host smart-25a3963a-c1a2-40b5-ad8e-d3e3dc9d55c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88112
8164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.881128164
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3296082537
Short name T2569
Test name
Test status
Simulation time 10647245333 ps
CPU time 69.38 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:04:49 PM PDT 24
Peak memory 207012 kb
Host smart-b36d377e-ae4c-4976-9242-9e547eacde90
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3296082537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3296082537
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.240292080
Short name T1786
Test name
Test status
Simulation time 76801323 ps
CPU time 0.73 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:10:06 PM PDT 24
Peak memory 207008 kb
Host smart-7a82f901-ed65-4337-a1a8-f6b553368859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=240292080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.240292080
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2505288817
Short name T2543
Test name
Test status
Simulation time 3688329356 ps
CPU time 4.49 seconds
Started Jul 15 07:09:29 PM PDT 24
Finished Jul 15 07:10:00 PM PDT 24
Peak memory 206880 kb
Host smart-2898b58d-71fc-412f-aee8-64aed34bfb0c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2505288817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2505288817
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2373792010
Short name T1794
Test name
Test status
Simulation time 13342207717 ps
CPU time 13.59 seconds
Started Jul 15 07:09:21 PM PDT 24
Finished Jul 15 07:09:51 PM PDT 24
Peak memory 207052 kb
Host smart-cb2931b4-033d-48e6-b9d2-07bab5a90fe8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2373792010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2373792010
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.796354143
Short name T2585
Test name
Test status
Simulation time 23317135714 ps
CPU time 25.86 seconds
Started Jul 15 07:09:23 PM PDT 24
Finished Jul 15 07:10:08 PM PDT 24
Peak memory 206880 kb
Host smart-addc102c-a7b4-46f7-bac1-713a5a107514
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=796354143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.796354143
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3666515606
Short name T1215
Test name
Test status
Simulation time 196996829 ps
CPU time 0.91 seconds
Started Jul 15 07:09:20 PM PDT 24
Finished Jul 15 07:09:38 PM PDT 24
Peak memory 206824 kb
Host smart-3f01f79e-438c-40b3-b8b0-31349e893819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36665
15606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3666515606
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.453343865
Short name T1020
Test name
Test status
Simulation time 153564685 ps
CPU time 0.79 seconds
Started Jul 15 07:09:29 PM PDT 24
Finished Jul 15 07:09:55 PM PDT 24
Peak memory 206812 kb
Host smart-a693697d-1891-49cb-a81b-36db49b2019c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45334
3865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.453343865
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.4083567257
Short name T1473
Test name
Test status
Simulation time 417238160 ps
CPU time 1.39 seconds
Started Jul 15 07:09:17 PM PDT 24
Finished Jul 15 07:09:33 PM PDT 24
Peak memory 206828 kb
Host smart-2b1631e9-a90d-414c-9cd1-fea5093cc2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40835
67257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.4083567257
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2084546833
Short name T1420
Test name
Test status
Simulation time 1195054793 ps
CPU time 2.5 seconds
Started Jul 15 07:09:31 PM PDT 24
Finished Jul 15 07:10:01 PM PDT 24
Peak memory 206972 kb
Host smart-f95f2f76-22e0-46cf-b907-28945dc46fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20845
46833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2084546833
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3869521769
Short name T166
Test name
Test status
Simulation time 22810053708 ps
CPU time 40.27 seconds
Started Jul 15 07:09:29 PM PDT 24
Finished Jul 15 07:10:36 PM PDT 24
Peak memory 206948 kb
Host smart-ff6f1ea4-9eac-4d62-a4a6-ca3e67527b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38695
21769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3869521769
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.350267022
Short name T2644
Test name
Test status
Simulation time 349102382 ps
CPU time 1.21 seconds
Started Jul 15 07:09:22 PM PDT 24
Finished Jul 15 07:09:43 PM PDT 24
Peak memory 206824 kb
Host smart-577969cf-6e3c-445d-81c8-72c8ab287777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35026
7022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.350267022
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1065411530
Short name T1800
Test name
Test status
Simulation time 139601830 ps
CPU time 0.75 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206812 kb
Host smart-3320bfc6-f552-4807-96cf-ff550a26ad9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10654
11530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1065411530
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3239082776
Short name T1077
Test name
Test status
Simulation time 46843621 ps
CPU time 0.73 seconds
Started Jul 15 07:09:27 PM PDT 24
Finished Jul 15 07:09:53 PM PDT 24
Peak memory 206800 kb
Host smart-f4476be6-e752-4fa8-9999-1a6b473147d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32390
82776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3239082776
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2654920955
Short name T737
Test name
Test status
Simulation time 968348274 ps
CPU time 2.11 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:09:47 PM PDT 24
Peak memory 207020 kb
Host smart-ab284931-7469-48f6-aba0-ebed8f82d146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26549
20955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2654920955
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.7125926
Short name T849
Test name
Test status
Simulation time 215128271 ps
CPU time 1.87 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:10:15 PM PDT 24
Peak memory 206900 kb
Host smart-aa13049d-2690-432e-966d-9dddf9b302a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71259
26 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.7125926
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3766860549
Short name T1609
Test name
Test status
Simulation time 181945787 ps
CPU time 0.89 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 206804 kb
Host smart-82a407e1-1aec-4590-b794-c7b20443d944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37668
60549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3766860549
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3832434005
Short name T1511
Test name
Test status
Simulation time 167001657 ps
CPU time 0.8 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:03 PM PDT 24
Peak memory 206764 kb
Host smart-50302a78-5d7c-471f-95df-1306a8a1c080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38324
34005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3832434005
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2470010110
Short name T1737
Test name
Test status
Simulation time 216860425 ps
CPU time 0.84 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:56 PM PDT 24
Peak memory 206792 kb
Host smart-5c9844eb-3bb1-412b-a63c-2b70f5ae3a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24700
10110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2470010110
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2464134166
Short name T357
Test name
Test status
Simulation time 253765318 ps
CPU time 0.98 seconds
Started Jul 15 07:09:33 PM PDT 24
Finished Jul 15 07:10:06 PM PDT 24
Peak memory 206760 kb
Host smart-beaf5123-35c6-41de-8f95-042274fbc1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24641
34166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2464134166
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1324707282
Short name T1497
Test name
Test status
Simulation time 23306220668 ps
CPU time 21.65 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:23 PM PDT 24
Peak memory 206864 kb
Host smart-1ebcce81-347f-48f0-abd9-844ed9ad6950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247
07282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1324707282
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2377402314
Short name T2042
Test name
Test status
Simulation time 3330530333 ps
CPU time 3.7 seconds
Started Jul 15 07:09:33 PM PDT 24
Finished Jul 15 07:10:17 PM PDT 24
Peak memory 206888 kb
Host smart-4d0bceaf-bd05-4310-9302-f16f9b154bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23774
02314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2377402314
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1134965816
Short name T1048
Test name
Test status
Simulation time 9085294675 ps
CPU time 65.01 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:11:03 PM PDT 24
Peak memory 207084 kb
Host smart-8ce1e169-c066-453e-8428-64268a4c8518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11349
65816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1134965816
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1993084734
Short name T301
Test name
Test status
Simulation time 6682548741 ps
CPU time 46.63 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:10:31 PM PDT 24
Peak memory 207092 kb
Host smart-d67ee7fb-e176-48fc-a187-9b712ea2b561
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1993084734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1993084734
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.723316249
Short name T2240
Test name
Test status
Simulation time 251034486 ps
CPU time 0.94 seconds
Started Jul 15 07:09:29 PM PDT 24
Finished Jul 15 07:09:56 PM PDT 24
Peak memory 206772 kb
Host smart-c5374007-6ac3-4e2c-ad41-e34b3f581ca3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=723316249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.723316249
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.753510702
Short name T2675
Test name
Test status
Simulation time 186978887 ps
CPU time 0.92 seconds
Started Jul 15 07:09:28 PM PDT 24
Finished Jul 15 07:09:55 PM PDT 24
Peak memory 206788 kb
Host smart-f0e9a53a-c853-47fa-b833-be370b33e491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75351
0702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.753510702
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.853948872
Short name T1388
Test name
Test status
Simulation time 3352977057 ps
CPU time 29.51 seconds
Started Jul 15 07:09:22 PM PDT 24
Finished Jul 15 07:10:11 PM PDT 24
Peak memory 207036 kb
Host smart-b73157b0-9e45-4dc7-b4e1-54d2cdc478e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85394
8872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.853948872
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.3408416370
Short name T1517
Test name
Test status
Simulation time 4299188383 ps
CPU time 31.2 seconds
Started Jul 15 07:09:29 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 207032 kb
Host smart-05d8236d-864f-4679-8c9f-e49fa8f53fd8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3408416370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.3408416370
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3793886487
Short name T2066
Test name
Test status
Simulation time 146763767 ps
CPU time 0.81 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:56 PM PDT 24
Peak memory 206828 kb
Host smart-41f8de46-2241-4160-bfd3-92d259746080
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3793886487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3793886487
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2824467656
Short name T2561
Test name
Test status
Simulation time 151810678 ps
CPU time 0.8 seconds
Started Jul 15 07:09:27 PM PDT 24
Finished Jul 15 07:09:53 PM PDT 24
Peak memory 206828 kb
Host smart-267a2ad3-a58c-4312-9191-e2d75beda1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244
67656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2824467656
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1114761637
Short name T1356
Test name
Test status
Simulation time 249504445 ps
CPU time 0.9 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:10:06 PM PDT 24
Peak memory 206800 kb
Host smart-887105a3-6167-4f2d-b59e-2cf2db5f1405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11147
61637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1114761637
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2987111770
Short name T308
Test name
Test status
Simulation time 215097105 ps
CPU time 0.86 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:05 PM PDT 24
Peak memory 206792 kb
Host smart-d94456d6-1370-4229-add4-547534d8255b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29871
11770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2987111770
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.964966409
Short name T2347
Test name
Test status
Simulation time 206792648 ps
CPU time 0.83 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:56 PM PDT 24
Peak memory 206712 kb
Host smart-2ae05051-0975-4117-8641-c4bdfadd2117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96496
6409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.964966409
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.898876658
Short name T2747
Test name
Test status
Simulation time 149273511 ps
CPU time 0.78 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:09:45 PM PDT 24
Peak memory 206824 kb
Host smart-1b7d9506-963a-4c44-b5d0-6384ddf28fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89887
6658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.898876658
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1769279381
Short name T883
Test name
Test status
Simulation time 173684097 ps
CPU time 0.79 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:03 PM PDT 24
Peak memory 206764 kb
Host smart-3859333e-c3fe-4524-9fcc-6b034e70b5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17692
79381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1769279381
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2399681942
Short name T2265
Test name
Test status
Simulation time 283392254 ps
CPU time 0.97 seconds
Started Jul 15 07:09:29 PM PDT 24
Finished Jul 15 07:09:56 PM PDT 24
Peak memory 206840 kb
Host smart-ceddba8f-49e3-4a10-a9f2-c0da14550e1b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2399681942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2399681942
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.4272738549
Short name T176
Test name
Test status
Simulation time 154894656 ps
CPU time 0.76 seconds
Started Jul 15 07:09:26 PM PDT 24
Finished Jul 15 07:09:50 PM PDT 24
Peak memory 206840 kb
Host smart-c19cebcc-dd3a-4aee-876b-47d8e48e78c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42727
38549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.4272738549
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1814466238
Short name T1877
Test name
Test status
Simulation time 38618678 ps
CPU time 0.66 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:09:47 PM PDT 24
Peak memory 206780 kb
Host smart-47f60fd0-9ce8-421f-86f6-f18c7762ad09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18144
66238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1814466238
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.103688792
Short name T258
Test name
Test status
Simulation time 19624585579 ps
CPU time 42.91 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:48 PM PDT 24
Peak memory 207124 kb
Host smart-bc882e7f-7c1b-41e7-b664-7aadae498f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10368
8792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.103688792
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2467720822
Short name T2074
Test name
Test status
Simulation time 182310288 ps
CPU time 0.84 seconds
Started Jul 15 07:09:33 PM PDT 24
Finished Jul 15 07:10:06 PM PDT 24
Peak memory 206788 kb
Host smart-e0bc0ee4-9c9e-4c79-868b-ed2e5250a7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
20822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2467720822
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1244709982
Short name T34
Test name
Test status
Simulation time 247132430 ps
CPU time 0.86 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:03 PM PDT 24
Peak memory 206700 kb
Host smart-6b707557-4a16-4ac4-81a8-2e71feca7df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12447
09982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1244709982
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.386220960
Short name T1439
Test name
Test status
Simulation time 225097402 ps
CPU time 0.85 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:13 PM PDT 24
Peak memory 206828 kb
Host smart-50125fb0-9efa-4432-a5d4-343e5d3754b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
0960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.386220960
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.621768405
Short name T822
Test name
Test status
Simulation time 159089126 ps
CPU time 0.75 seconds
Started Jul 15 07:09:39 PM PDT 24
Finished Jul 15 07:10:21 PM PDT 24
Peak memory 206796 kb
Host smart-9769eeb3-064d-42d3-a329-f516bc9d8afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62176
8405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.621768405
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.4270146707
Short name T2355
Test name
Test status
Simulation time 140657351 ps
CPU time 0.75 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206828 kb
Host smart-01e4fcbd-1031-4543-8afd-61b1c138f6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
46707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.4270146707
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3139872044
Short name T634
Test name
Test status
Simulation time 173142124 ps
CPU time 0.76 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:56 PM PDT 24
Peak memory 206808 kb
Host smart-ae6675d7-3a06-40d7-9235-975eb4f2706f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31398
72044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3139872044
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2296388537
Short name T640
Test name
Test status
Simulation time 157824821 ps
CPU time 0.78 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:03 PM PDT 24
Peak memory 206768 kb
Host smart-42c12ba7-7573-46f4-b914-96262f1664ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22963
88537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2296388537
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.854765543
Short name T1928
Test name
Test status
Simulation time 215113035 ps
CPU time 0.89 seconds
Started Jul 15 07:09:38 PM PDT 24
Finished Jul 15 07:10:18 PM PDT 24
Peak memory 206828 kb
Host smart-1e26c841-e4d6-4bdd-95e8-2dc63ca76ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85476
5543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.854765543
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2139444434
Short name T899
Test name
Test status
Simulation time 5352084425 ps
CPU time 151.12 seconds
Started Jul 15 07:09:24 PM PDT 24
Finished Jul 15 07:12:16 PM PDT 24
Peak memory 207048 kb
Host smart-540d904f-78da-4f79-81ca-a8704efb68c2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2139444434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2139444434
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2848771191
Short name T2213
Test name
Test status
Simulation time 182580964 ps
CPU time 0.87 seconds
Started Jul 15 07:09:29 PM PDT 24
Finished Jul 15 07:09:55 PM PDT 24
Peak memory 206816 kb
Host smart-23ce327e-018e-48c1-89a1-6a25484763b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28487
71191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2848771191
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3627999340
Short name T570
Test name
Test status
Simulation time 228851024 ps
CPU time 0.84 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:10:06 PM PDT 24
Peak memory 206776 kb
Host smart-a475f49e-e29d-45a5-96e8-9407834449ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36279
99340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3627999340
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3860493425
Short name T1779
Test name
Test status
Simulation time 226586585 ps
CPU time 0.86 seconds
Started Jul 15 07:09:33 PM PDT 24
Finished Jul 15 07:10:06 PM PDT 24
Peak memory 206768 kb
Host smart-adbc4e98-ae79-4fc5-b2f9-582ea78a8d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38604
93425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3860493425
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2387349587
Short name T2019
Test name
Test status
Simulation time 4981443409 ps
CPU time 37.21 seconds
Started Jul 15 07:09:35 PM PDT 24
Finished Jul 15 07:10:47 PM PDT 24
Peak memory 207060 kb
Host smart-9a9e28bf-af99-4c92-b849-e194779c9b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23873
49587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2387349587
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3075143965
Short name T1408
Test name
Test status
Simulation time 62240552 ps
CPU time 0.65 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206800 kb
Host smart-d1cca8be-93b6-4cfb-bd6e-df5211affa22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3075143965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3075143965
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1507598033
Short name T1389
Test name
Test status
Simulation time 3968686965 ps
CPU time 4.37 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:10:10 PM PDT 24
Peak memory 206888 kb
Host smart-c5570a56-980b-4eb8-a00a-66a7c4e22cc1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1507598033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1507598033
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2625905360
Short name T2242
Test name
Test status
Simulation time 13356200660 ps
CPU time 12.61 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 207080 kb
Host smart-4d9b68f6-6814-46d0-b943-a79cfcafef78
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2625905360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2625905360
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.676103797
Short name T540
Test name
Test status
Simulation time 23435029319 ps
CPU time 23.54 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:37 PM PDT 24
Peak memory 207052 kb
Host smart-bd261a49-343c-45c1-bcc0-9040b5f7646d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=676103797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.676103797
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2490309006
Short name T143
Test name
Test status
Simulation time 178171637 ps
CPU time 0.83 seconds
Started Jul 15 07:09:27 PM PDT 24
Finished Jul 15 07:09:53 PM PDT 24
Peak memory 206804 kb
Host smart-b6262e74-b121-4482-89ce-7e11697a53fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24903
09006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2490309006
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2439511550
Short name T2382
Test name
Test status
Simulation time 194677260 ps
CPU time 0.81 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 206844 kb
Host smart-7f4cc3a2-60fd-4443-9e9c-0723f99fdedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24395
11550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2439511550
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.186021810
Short name T1196
Test name
Test status
Simulation time 254473269 ps
CPU time 0.98 seconds
Started Jul 15 07:09:29 PM PDT 24
Finished Jul 15 07:09:56 PM PDT 24
Peak memory 206824 kb
Host smart-6a2bf279-6e70-47fa-aec1-1713bfbc7a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18602
1810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.186021810
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1495421780
Short name T2506
Test name
Test status
Simulation time 643609686 ps
CPU time 1.56 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:10:07 PM PDT 24
Peak memory 206796 kb
Host smart-b8d2f046-4e8e-47a5-9990-5110933d71e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14954
21780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1495421780
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1188791982
Short name T1453
Test name
Test status
Simulation time 6402456308 ps
CPU time 11.81 seconds
Started Jul 15 07:09:31 PM PDT 24
Finished Jul 15 07:10:10 PM PDT 24
Peak memory 207012 kb
Host smart-79edf76c-13f3-41cf-9016-8d158bfcb3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11887
91982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1188791982
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2126947988
Short name T2262
Test name
Test status
Simulation time 401965330 ps
CPU time 1.27 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 206796 kb
Host smart-4294b9cd-30c0-4677-9fb8-6345455cbcd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21269
47988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2126947988
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1204360399
Short name T363
Test name
Test status
Simulation time 163751368 ps
CPU time 0.8 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:11 PM PDT 24
Peak memory 206812 kb
Host smart-e7ca048b-b509-4cd0-ab7b-63f7fefae50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12043
60399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1204360399
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.244045470
Short name T394
Test name
Test status
Simulation time 81472929 ps
CPU time 0.68 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 206748 kb
Host smart-effe8106-e196-4f35-a544-4110e405a027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24404
5470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.244045470
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3335165489
Short name T2568
Test name
Test status
Simulation time 794681184 ps
CPU time 2.09 seconds
Started Jul 15 07:09:33 PM PDT 24
Finished Jul 15 07:10:07 PM PDT 24
Peak memory 206948 kb
Host smart-08b8c56e-53f4-4a1f-bbae-7f6a84d5b4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33351
65489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3335165489
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2787909968
Short name T915
Test name
Test status
Simulation time 237095574 ps
CPU time 1.4 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206948 kb
Host smart-0a797973-0866-4dac-9a64-1c1717dca3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27879
09968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2787909968
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.420574854
Short name T1882
Test name
Test status
Simulation time 203546971 ps
CPU time 0.84 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 206816 kb
Host smart-de4df8f2-fb07-483b-888c-ff183b179b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42057
4854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.420574854
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.75597064
Short name T1775
Test name
Test status
Simulation time 149854065 ps
CPU time 0.77 seconds
Started Jul 15 07:09:40 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206816 kb
Host smart-9221320f-c880-45e5-a185-9d635b09e813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75597
064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.75597064
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.435206885
Short name T536
Test name
Test status
Simulation time 195777778 ps
CPU time 0.87 seconds
Started Jul 15 07:09:30 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 206824 kb
Host smart-74cf0846-3829-438e-a24e-fbd89a8841b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43520
6885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.435206885
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.4139031201
Short name T1549
Test name
Test status
Simulation time 5261573453 ps
CPU time 134.3 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:12:23 PM PDT 24
Peak memory 206996 kb
Host smart-4ddba863-e682-4896-b6a9-1a437fd1a706
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4139031201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.4139031201
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2774411360
Short name T1533
Test name
Test status
Simulation time 10411800313 ps
CPU time 38.43 seconds
Started Jul 15 07:09:35 PM PDT 24
Finished Jul 15 07:10:48 PM PDT 24
Peak memory 207048 kb
Host smart-302f0640-13ba-4bb9-83ed-3c242d478ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27744
11360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2774411360
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1462333592
Short name T797
Test name
Test status
Simulation time 205919168 ps
CPU time 0.83 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:10:10 PM PDT 24
Peak memory 206820 kb
Host smart-a839c09c-24d5-4cd2-bced-3482e8397e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
33592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1462333592
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.622328143
Short name T1442
Test name
Test status
Simulation time 23351631679 ps
CPU time 23.9 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:10:37 PM PDT 24
Peak memory 206884 kb
Host smart-7a3cac76-2926-4a67-8a54-52266a939c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62232
8143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.622328143
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1760424525
Short name T1651
Test name
Test status
Simulation time 3301835991 ps
CPU time 4.13 seconds
Started Jul 15 07:09:31 PM PDT 24
Finished Jul 15 07:10:06 PM PDT 24
Peak memory 206884 kb
Host smart-70a9b090-3542-42ef-8c64-b72211a9e97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17604
24525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1760424525
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3057837778
Short name T522
Test name
Test status
Simulation time 8380627847 ps
CPU time 56.79 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 207040 kb
Host smart-06b2c034-75cf-48f7-87a2-b9a2f318d440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30578
37778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3057837778
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.685299314
Short name T1399
Test name
Test status
Simulation time 3185476557 ps
CPU time 83.97 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:11:37 PM PDT 24
Peak memory 207024 kb
Host smart-35e3dcf4-8627-40a9-bad2-b55bd6a367ff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=685299314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.685299314
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3597370938
Short name T2599
Test name
Test status
Simulation time 236917792 ps
CPU time 0.89 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206804 kb
Host smart-468924b6-1aeb-4466-8d2a-6d33fd23f2a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3597370938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3597370938
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.454571356
Short name T1686
Test name
Test status
Simulation time 208480079 ps
CPU time 0.84 seconds
Started Jul 15 07:09:32 PM PDT 24
Finished Jul 15 07:10:03 PM PDT 24
Peak memory 206808 kb
Host smart-5b307da1-2626-4949-a271-5c06b231bc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45457
1356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.454571356
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3768332960
Short name T1591
Test name
Test status
Simulation time 5105114712 ps
CPU time 47.41 seconds
Started Jul 15 07:09:39 PM PDT 24
Finished Jul 15 07:11:08 PM PDT 24
Peak memory 206916 kb
Host smart-4ff16420-6661-4931-848e-4ac0f561a3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37683
32960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3768332960
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.115574665
Short name T2352
Test name
Test status
Simulation time 7003321847 ps
CPU time 47.34 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:11:01 PM PDT 24
Peak memory 207056 kb
Host smart-29e47e3c-9cbd-45fa-b930-34329bef297d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=115574665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.115574665
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3572193046
Short name T1441
Test name
Test status
Simulation time 161148926 ps
CPU time 0.77 seconds
Started Jul 15 07:09:31 PM PDT 24
Finished Jul 15 07:09:59 PM PDT 24
Peak memory 206816 kb
Host smart-63df88a3-6493-4e7d-92a9-1365bd529cb0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3572193046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3572193046
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3926547912
Short name T577
Test name
Test status
Simulation time 140954862 ps
CPU time 0.73 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206788 kb
Host smart-f1893f74-4300-438a-83ce-19fae77fbb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
47912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3926547912
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.4027790789
Short name T2307
Test name
Test status
Simulation time 191102177 ps
CPU time 0.82 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:10:10 PM PDT 24
Peak memory 206780 kb
Host smart-1d7cea89-7ec3-4014-ad35-2c397d78b7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40277
90789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.4027790789
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2117633500
Short name T1904
Test name
Test status
Simulation time 159564168 ps
CPU time 0.81 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206780 kb
Host smart-cf319dec-76d3-4a59-b32b-0e8647351b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21176
33500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2117633500
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3879139469
Short name T1793
Test name
Test status
Simulation time 226279341 ps
CPU time 0.84 seconds
Started Jul 15 07:09:39 PM PDT 24
Finished Jul 15 07:10:18 PM PDT 24
Peak memory 206800 kb
Host smart-70cd630c-a688-4e96-b5c2-4ce7a2538949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38791
39469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3879139469
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3741714360
Short name T1702
Test name
Test status
Simulation time 155155450 ps
CPU time 0.77 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206828 kb
Host smart-17453f79-8bed-4a87-accd-c9ab08980678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37417
14360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3741714360
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3680039919
Short name T474
Test name
Test status
Simulation time 215242374 ps
CPU time 0.95 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:11 PM PDT 24
Peak memory 206824 kb
Host smart-bbd1ee45-0dbd-45e9-bcd2-7f1f3a584592
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3680039919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3680039919
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.413176581
Short name T2032
Test name
Test status
Simulation time 147001416 ps
CPU time 0.8 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206828 kb
Host smart-9436c4bd-561b-4a82-9539-0f8d546f93de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41317
6581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.413176581
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2937436834
Short name T26
Test name
Test status
Simulation time 34947325 ps
CPU time 0.64 seconds
Started Jul 15 07:09:35 PM PDT 24
Finished Jul 15 07:10:10 PM PDT 24
Peak memory 206796 kb
Host smart-24ddb6ab-5bc7-4074-a824-f09421ea96c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29374
36834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2937436834
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.99786403
Short name T1390
Test name
Test status
Simulation time 15768276848 ps
CPU time 34.45 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:10:48 PM PDT 24
Peak memory 206912 kb
Host smart-316a6b50-cfd7-4d48-af7d-f3976fe82ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99786
403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.99786403
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3805326865
Short name T1896
Test name
Test status
Simulation time 147437786 ps
CPU time 0.77 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206824 kb
Host smart-f3e3a146-0008-4816-a7cd-fcfd894edf9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38053
26865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3805326865
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3414834903
Short name T408
Test name
Test status
Simulation time 217345641 ps
CPU time 0.87 seconds
Started Jul 15 07:09:35 PM PDT 24
Finished Jul 15 07:10:11 PM PDT 24
Peak memory 206820 kb
Host smart-f237b853-9448-441f-968a-38bf7489a203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34148
34903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3414834903
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3110881440
Short name T2429
Test name
Test status
Simulation time 217286585 ps
CPU time 0.84 seconds
Started Jul 15 07:09:34 PM PDT 24
Finished Jul 15 07:10:06 PM PDT 24
Peak memory 206816 kb
Host smart-763d9c52-55dd-4670-906e-a86b7cfba16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31108
81440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3110881440
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2099699834
Short name T1982
Test name
Test status
Simulation time 204075379 ps
CPU time 0.84 seconds
Started Jul 15 07:09:35 PM PDT 24
Finished Jul 15 07:10:10 PM PDT 24
Peak memory 206800 kb
Host smart-a661ceba-e076-4425-b9da-8aab9d64cd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20996
99834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2099699834
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.643260659
Short name T1155
Test name
Test status
Simulation time 147001693 ps
CPU time 0.78 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206792 kb
Host smart-091f4780-d897-4930-bb1a-b3dccf6b7dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64326
0659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.643260659
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1403240169
Short name T2
Test name
Test status
Simulation time 149350300 ps
CPU time 0.8 seconds
Started Jul 15 07:09:38 PM PDT 24
Finished Jul 15 07:10:18 PM PDT 24
Peak memory 206804 kb
Host smart-7b056d3b-94c2-4b5a-a25e-0d20c6090675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14032
40169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1403240169
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1433843238
Short name T88
Test name
Test status
Simulation time 146038346 ps
CPU time 0.78 seconds
Started Jul 15 07:09:35 PM PDT 24
Finished Jul 15 07:10:10 PM PDT 24
Peak memory 206824 kb
Host smart-565cebf7-4a4e-4352-9e6a-6e57b743db37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14338
43238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1433843238
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3016294531
Short name T2256
Test name
Test status
Simulation time 220211127 ps
CPU time 0.92 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206604 kb
Host smart-34c7012b-dba7-4d6d-862a-0c4c3e9d91ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30162
94531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3016294531
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2907404658
Short name T938
Test name
Test status
Simulation time 4731525718 ps
CPU time 34.23 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:11:07 PM PDT 24
Peak memory 206976 kb
Host smart-562b8499-0fc5-4f36-b0b5-6e11f26610cd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2907404658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2907404658
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1641206717
Short name T1652
Test name
Test status
Simulation time 174161695 ps
CPU time 0.78 seconds
Started Jul 15 07:09:38 PM PDT 24
Finished Jul 15 07:10:21 PM PDT 24
Peak memory 206832 kb
Host smart-ca25b92c-7cd4-4503-905f-1b03e7140b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16412
06717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1641206717
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2951802798
Short name T1448
Test name
Test status
Simulation time 192194615 ps
CPU time 0.86 seconds
Started Jul 15 07:09:35 PM PDT 24
Finished Jul 15 07:10:10 PM PDT 24
Peak memory 206844 kb
Host smart-638ba7bd-bd7a-4870-86da-d5fd3d9fc0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29518
02798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2951802798
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.2348931305
Short name T2217
Test name
Test status
Simulation time 955480174 ps
CPU time 2.02 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:28 PM PDT 24
Peak memory 206984 kb
Host smart-2d51bbcd-06af-4191-80e4-912ad2f9e7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23489
31305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2348931305
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2369312055
Short name T2338
Test name
Test status
Simulation time 2862327190 ps
CPU time 27.21 seconds
Started Jul 15 07:09:38 PM PDT 24
Finished Jul 15 07:10:44 PM PDT 24
Peak memory 207040 kb
Host smart-0c1446e9-f681-40fb-8ac2-9b4769976e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23693
12055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2369312055
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3820149847
Short name T1615
Test name
Test status
Simulation time 36631372 ps
CPU time 0.66 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206716 kb
Host smart-8e8e6c50-6cbe-4aa1-98bb-60f7a484625b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3820149847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3820149847
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2455510951
Short name T1063
Test name
Test status
Simulation time 4163399684 ps
CPU time 4.45 seconds
Started Jul 15 07:09:40 PM PDT 24
Finished Jul 15 07:10:26 PM PDT 24
Peak memory 207080 kb
Host smart-9ce2f34f-f6f1-4ee8-866f-f14e6dec487c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2455510951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.2455510951
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1489302556
Short name T1641
Test name
Test status
Simulation time 13354297365 ps
CPU time 15.14 seconds
Started Jul 15 07:09:39 PM PDT 24
Finished Jul 15 07:10:36 PM PDT 24
Peak memory 206892 kb
Host smart-c8247e65-0b12-4248-a25d-83b5d9f4979c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1489302556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1489302556
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1086298756
Short name T1328
Test name
Test status
Simulation time 23372960360 ps
CPU time 24.05 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:50 PM PDT 24
Peak memory 207068 kb
Host smart-24f2fe8d-8770-44f3-9dbf-b4ca197d3fc7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1086298756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1086298756
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.636447411
Short name T823
Test name
Test status
Simulation time 215442397 ps
CPU time 0.86 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206800 kb
Host smart-e27637bd-7be1-4806-87ea-af2d3da5c244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63644
7411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.636447411
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.843777352
Short name T1361
Test name
Test status
Simulation time 158926117 ps
CPU time 0.78 seconds
Started Jul 15 07:09:40 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206816 kb
Host smart-a7725fc8-6932-4610-bf60-702ced489852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84377
7352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.843777352
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.617704413
Short name T650
Test name
Test status
Simulation time 243730576 ps
CPU time 0.88 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206704 kb
Host smart-90a38a8d-0304-4c12-9aab-6944f31d6032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61770
4413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.617704413
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.2220343586
Short name T1931
Test name
Test status
Simulation time 837116916 ps
CPU time 1.91 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:10:23 PM PDT 24
Peak memory 206956 kb
Host smart-76a6d2f4-dadd-4c1e-96ab-86ed759876bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22203
43586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.2220343586
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.636467227
Short name T2004
Test name
Test status
Simulation time 15084384938 ps
CPU time 26.87 seconds
Started Jul 15 07:09:51 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 207020 kb
Host smart-852e6eb8-891c-4f9b-b067-8ec3fa6f9771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63646
7227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.636467227
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.14460635
Short name T2626
Test name
Test status
Simulation time 340940651 ps
CPU time 1.18 seconds
Started Jul 15 07:09:36 PM PDT 24
Finished Jul 15 07:10:14 PM PDT 24
Peak memory 206800 kb
Host smart-557bd7a3-996d-47b8-8e52-8489f6d5f529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14460
635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.14460635
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1967071756
Short name T1079
Test name
Test status
Simulation time 213321668 ps
CPU time 0.88 seconds
Started Jul 15 07:09:47 PM PDT 24
Finished Jul 15 07:10:35 PM PDT 24
Peak memory 206760 kb
Host smart-03097783-dde2-4199-9cd9-c8f4066f8b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19670
71756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1967071756
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.441990427
Short name T2580
Test name
Test status
Simulation time 43551835 ps
CPU time 0.65 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206780 kb
Host smart-c8790419-3bfe-4781-ba30-2c80990ea80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44199
0427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.441990427
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.642102880
Short name T442
Test name
Test status
Simulation time 859592762 ps
CPU time 2.14 seconds
Started Jul 15 07:09:39 PM PDT 24
Finished Jul 15 07:10:19 PM PDT 24
Peak memory 206976 kb
Host smart-3d3bd931-2387-463a-9284-c838c0b2d4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64210
2880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.642102880
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2469273277
Short name T918
Test name
Test status
Simulation time 326080732 ps
CPU time 2.04 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206992 kb
Host smart-fc085ebb-8107-4a56-8ba5-185cebaa80a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24692
73277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2469273277
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1016628057
Short name T1939
Test name
Test status
Simulation time 212424519 ps
CPU time 0.9 seconds
Started Jul 15 07:09:40 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206816 kb
Host smart-86a96b7d-276a-4aa2-95f7-385579704122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166
28057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1016628057
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1369724385
Short name T2035
Test name
Test status
Simulation time 144381838 ps
CPU time 0.77 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:10:29 PM PDT 24
Peak memory 206804 kb
Host smart-ca272f7a-cf16-4d0e-b906-8562e97ea354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13697
24385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1369724385
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.104295606
Short name T466
Test name
Test status
Simulation time 171922406 ps
CPU time 0.82 seconds
Started Jul 15 07:09:48 PM PDT 24
Finished Jul 15 07:10:35 PM PDT 24
Peak memory 206832 kb
Host smart-450a3516-7ad9-4274-afe6-f80683fa19fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10429
5606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.104295606
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1579561314
Short name T600
Test name
Test status
Simulation time 5329586423 ps
CPU time 51 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 207056 kb
Host smart-593d8e73-d804-44d2-aa19-1bac81b0f426
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1579561314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1579561314
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2723245967
Short name T1925
Test name
Test status
Simulation time 165811511 ps
CPU time 0.82 seconds
Started Jul 15 07:09:48 PM PDT 24
Finished Jul 15 07:10:35 PM PDT 24
Peak memory 206824 kb
Host smart-456adae7-b8fc-4d95-a6d1-140cb5e2b04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27232
45967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2723245967
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2265632471
Short name T973
Test name
Test status
Simulation time 23344844385 ps
CPU time 27.92 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:10:53 PM PDT 24
Peak memory 206856 kb
Host smart-5d21d8fe-d90e-44ff-acb7-5a3699e33c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22656
32471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2265632471
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1404935565
Short name T2442
Test name
Test status
Simulation time 3296978308 ps
CPU time 4.05 seconds
Started Jul 15 07:09:37 PM PDT 24
Finished Jul 15 07:10:17 PM PDT 24
Peak memory 206876 kb
Host smart-cf591c4b-5739-4581-b698-c9a7506d2cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14049
35565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1404935565
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.1473377821
Short name T1823
Test name
Test status
Simulation time 11419751417 ps
CPU time 109.08 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 207076 kb
Host smart-6a7bf38b-011c-4aa1-bbc6-b47d5c625db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14733
77821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.1473377821
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3830636235
Short name T488
Test name
Test status
Simulation time 3511990934 ps
CPU time 100.26 seconds
Started Jul 15 07:09:39 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 207016 kb
Host smart-3e25faae-4de0-46c8-b838-f8a06101f137
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3830636235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3830636235
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.3735029247
Short name T203
Test name
Test status
Simulation time 251934039 ps
CPU time 0.99 seconds
Started Jul 15 07:09:44 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206804 kb
Host smart-b8c1c5d1-2c2c-4bf0-9b8e-bb92712a0cf5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3735029247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.3735029247
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.44836452
Short name T2700
Test name
Test status
Simulation time 261546003 ps
CPU time 0.93 seconds
Started Jul 15 07:09:39 PM PDT 24
Finished Jul 15 07:10:18 PM PDT 24
Peak memory 206836 kb
Host smart-991dd9cc-c2ac-4a40-9519-c9f8191d7f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44836
452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.44836452
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.225203374
Short name T546
Test name
Test status
Simulation time 6041531290 ps
CPU time 163.16 seconds
Started Jul 15 07:09:44 PM PDT 24
Finished Jul 15 07:13:09 PM PDT 24
Peak memory 207064 kb
Host smart-2392f093-3692-4f43-8937-490e1e383b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22520
3374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.225203374
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1840728148
Short name T2208
Test name
Test status
Simulation time 3387496698 ps
CPU time 24.72 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:10:50 PM PDT 24
Peak memory 207012 kb
Host smart-7ad9bf90-be0a-42b6-9edc-fd258a2cd12f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1840728148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1840728148
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.4151229936
Short name T2522
Test name
Test status
Simulation time 147639111 ps
CPU time 0.81 seconds
Started Jul 15 07:09:40 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206836 kb
Host smart-55a622bf-ea74-49e1-bd74-e459016762ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4151229936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.4151229936
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.207518389
Short name T297
Test name
Test status
Simulation time 207799390 ps
CPU time 0.8 seconds
Started Jul 15 07:09:40 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206828 kb
Host smart-62f83196-38b7-4dd1-9a95-57b2125342ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20751
8389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.207518389
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.319182701
Short name T2707
Test name
Test status
Simulation time 187443945 ps
CPU time 0.87 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206784 kb
Host smart-44ede23e-728c-4f98-9641-e4a598f96693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31918
2701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.319182701
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.4094186977
Short name T2218
Test name
Test status
Simulation time 233117548 ps
CPU time 0.86 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206792 kb
Host smart-dd4efa29-cc8f-4a1a-9b8b-094c2d26ff06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40941
86977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.4094186977
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3677346102
Short name T2532
Test name
Test status
Simulation time 172781781 ps
CPU time 0.85 seconds
Started Jul 15 07:09:39 PM PDT 24
Finished Jul 15 07:10:18 PM PDT 24
Peak memory 206800 kb
Host smart-a2f2839d-d3bb-4ac2-b6c1-c78c841b0bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36773
46102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3677346102
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4068518416
Short name T2421
Test name
Test status
Simulation time 153206559 ps
CPU time 0.75 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 206748 kb
Host smart-970114a7-fc89-43cd-941f-118fd25d5cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40685
18416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4068518416
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3192000409
Short name T2068
Test name
Test status
Simulation time 169782713 ps
CPU time 0.8 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206828 kb
Host smart-de27667f-b15e-4c84-a00b-f524da88e8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31920
00409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3192000409
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3897248921
Short name T1465
Test name
Test status
Simulation time 318313547 ps
CPU time 1 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:34 PM PDT 24
Peak memory 206828 kb
Host smart-6d97c741-72f9-4190-99b3-5eda443e40e7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3897248921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3897248921
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2189949674
Short name T949
Test name
Test status
Simulation time 147503533 ps
CPU time 0.75 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206800 kb
Host smart-7ec2a21b-c8fc-4edc-a375-1a2885048e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21899
49674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2189949674
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3049811091
Short name T734
Test name
Test status
Simulation time 30859747 ps
CPU time 0.64 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206800 kb
Host smart-78c608cd-b140-48fa-b8d1-50be10266a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30498
11091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3049811091
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3779110605
Short name T2372
Test name
Test status
Simulation time 7725378263 ps
CPU time 17.52 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:10:42 PM PDT 24
Peak memory 207124 kb
Host smart-d7cd7189-6675-4d1b-bb42-a0630921e930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37791
10605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3779110605
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2530091524
Short name T2287
Test name
Test status
Simulation time 167218265 ps
CPU time 0.82 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206800 kb
Host smart-3bcae233-0385-46e2-95bb-3a3d6b8a47b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25300
91524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2530091524
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1294578229
Short name T1016
Test name
Test status
Simulation time 181148278 ps
CPU time 0.8 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 206836 kb
Host smart-6f349094-b0f1-4dca-8f96-9b591d22a259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12945
78229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1294578229
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.858551176
Short name T2081
Test name
Test status
Simulation time 231704717 ps
CPU time 0.86 seconds
Started Jul 15 07:09:44 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206804 kb
Host smart-7ee19b5f-cc08-46cb-8764-5fcf4e38335d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85855
1176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.858551176
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1503268934
Short name T1818
Test name
Test status
Simulation time 168436822 ps
CPU time 0.75 seconds
Started Jul 15 07:09:38 PM PDT 24
Finished Jul 15 07:10:18 PM PDT 24
Peak memory 206812 kb
Host smart-6676cbeb-e50c-48d8-8dde-b41009488ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15032
68934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1503268934
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1969788285
Short name T2452
Test name
Test status
Simulation time 151922332 ps
CPU time 0.77 seconds
Started Jul 15 07:09:41 PM PDT 24
Finished Jul 15 07:10:22 PM PDT 24
Peak memory 206836 kb
Host smart-374bda66-865c-4e2a-a1de-109f6c1694ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19697
88285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1969788285
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.562690555
Short name T798
Test name
Test status
Simulation time 168276070 ps
CPU time 0.79 seconds
Started Jul 15 07:09:47 PM PDT 24
Finished Jul 15 07:10:35 PM PDT 24
Peak memory 206820 kb
Host smart-8a2bc867-55f2-41fb-a6ad-9d90ce2a5323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56269
0555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.562690555
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3987099678
Short name T830
Test name
Test status
Simulation time 143404441 ps
CPU time 0.8 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:10:26 PM PDT 24
Peak memory 206792 kb
Host smart-1e5535c5-076e-4815-aee1-1b530803e93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39870
99678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3987099678
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3921585674
Short name T1713
Test name
Test status
Simulation time 206253535 ps
CPU time 0.87 seconds
Started Jul 15 07:09:48 PM PDT 24
Finished Jul 15 07:10:36 PM PDT 24
Peak memory 206824 kb
Host smart-8e6f5c64-973f-4f84-bc71-e9a5bf69ff8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
85674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3921585674
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1769581615
Short name T1834
Test name
Test status
Simulation time 5492278137 ps
CPU time 37.15 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:11:03 PM PDT 24
Peak memory 207044 kb
Host smart-24d2499e-7a38-49de-adf6-47cbd9627878
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1769581615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1769581615
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.437537123
Short name T1349
Test name
Test status
Simulation time 164466659 ps
CPU time 0.8 seconds
Started Jul 15 07:09:51 PM PDT 24
Finished Jul 15 07:10:38 PM PDT 24
Peak memory 206828 kb
Host smart-725a59f5-ec37-4447-86d1-bfa5a032600c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43753
7123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.437537123
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3508139990
Short name T1889
Test name
Test status
Simulation time 172875516 ps
CPU time 0.78 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 206824 kb
Host smart-28372d4b-85d8-4748-96e5-7a19c675cf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35081
39990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3508139990
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.1731939157
Short name T2345
Test name
Test status
Simulation time 364251840 ps
CPU time 1.09 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206828 kb
Host smart-bf1e150f-ae24-43bd-bf24-1be6d384b4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17319
39157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.1731939157
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1761561926
Short name T1726
Test name
Test status
Simulation time 8007610177 ps
CPU time 73.93 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:11:43 PM PDT 24
Peak memory 207024 kb
Host smart-eb27c5cd-ac95-4ae1-bf8f-e703afd22f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17615
61926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1761561926
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.4027502338
Short name T170
Test name
Test status
Simulation time 37528433 ps
CPU time 0.67 seconds
Started Jul 15 07:09:57 PM PDT 24
Finished Jul 15 07:10:45 PM PDT 24
Peak memory 206848 kb
Host smart-68daf391-bc58-49a0-b069-95bf29d589cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4027502338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.4027502338
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.633167242
Short name T1603
Test name
Test status
Simulation time 3552208058 ps
CPU time 4.01 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 207076 kb
Host smart-26c1b9de-7b70-4df1-a2b2-891189abbdb6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=633167242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.633167242
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.605180653
Short name T2341
Test name
Test status
Simulation time 13479897345 ps
CPU time 13.74 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:10:39 PM PDT 24
Peak memory 207096 kb
Host smart-3fb93efb-d749-4e81-a880-6cf4e12c1c5b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=605180653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.605180653
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3493187329
Short name T2248
Test name
Test status
Simulation time 23537115230 ps
CPU time 24.86 seconds
Started Jul 15 07:09:51 PM PDT 24
Finished Jul 15 07:11:02 PM PDT 24
Peak memory 207036 kb
Host smart-8b2c0363-ab97-4459-9768-d4e1bed7b80f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3493187329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3493187329
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1376802187
Short name T2413
Test name
Test status
Simulation time 211868487 ps
CPU time 0.86 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:34 PM PDT 24
Peak memory 206748 kb
Host smart-6ccafa1c-70d9-4cd9-bbb2-f545008bff0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13768
02187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1376802187
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.4155992649
Short name T1417
Test name
Test status
Simulation time 153097309 ps
CPU time 0.77 seconds
Started Jul 15 07:09:49 PM PDT 24
Finished Jul 15 07:10:37 PM PDT 24
Peak memory 206800 kb
Host smart-1b891f3a-4b6c-49fd-b9ef-34dcc907d54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41559
92649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.4155992649
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2663232317
Short name T1569
Test name
Test status
Simulation time 227053172 ps
CPU time 1.03 seconds
Started Jul 15 07:09:47 PM PDT 24
Finished Jul 15 07:10:34 PM PDT 24
Peak memory 206800 kb
Host smart-e313a55f-ba7a-4ad3-96d6-9a7d72c26f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26632
32317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2663232317
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.4247971561
Short name T1482
Test name
Test status
Simulation time 798836780 ps
CPU time 1.99 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:10:31 PM PDT 24
Peak memory 206984 kb
Host smart-867de29f-d065-415f-8592-2da9fdca6ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42479
71561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.4247971561
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.284650591
Short name T1996
Test name
Test status
Simulation time 11702963663 ps
CPU time 21.15 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:10:46 PM PDT 24
Peak memory 207088 kb
Host smart-c615acac-da42-4d82-b8f1-d9fd0a04e0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28465
0591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.284650591
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1286617174
Short name T1667
Test name
Test status
Simulation time 336702148 ps
CPU time 1.12 seconds
Started Jul 15 07:09:50 PM PDT 24
Finished Jul 15 07:10:37 PM PDT 24
Peak memory 206816 kb
Host smart-9e209c27-b1af-470e-aad5-f78cd90d2c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12866
17174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1286617174
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.337248500
Short name T1776
Test name
Test status
Simulation time 152972613 ps
CPU time 0.75 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:10:29 PM PDT 24
Peak memory 206816 kb
Host smart-b20b4a17-e14e-40e6-861c-a45e4dea8ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33724
8500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.337248500
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1443245547
Short name T1850
Test name
Test status
Simulation time 74111177 ps
CPU time 0.7 seconds
Started Jul 15 07:09:48 PM PDT 24
Finished Jul 15 07:10:35 PM PDT 24
Peak memory 206808 kb
Host smart-c618c541-abd0-4835-a692-8a8fd9cbd183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14432
45547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1443245547
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2480823484
Short name T539
Test name
Test status
Simulation time 836883664 ps
CPU time 1.99 seconds
Started Jul 15 07:09:48 PM PDT 24
Finished Jul 15 07:10:36 PM PDT 24
Peak memory 207012 kb
Host smart-13625641-6e13-4867-b6e6-75e2df1ae6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24808
23484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2480823484
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2653460177
Short name T2290
Test name
Test status
Simulation time 465247912 ps
CPU time 2.49 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:10:31 PM PDT 24
Peak memory 206988 kb
Host smart-f7ba42bf-44d3-40d6-b2ce-497fd7efc311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26534
60177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2653460177
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1056731336
Short name T485
Test name
Test status
Simulation time 180569762 ps
CPU time 0.78 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:33 PM PDT 24
Peak memory 206836 kb
Host smart-dbe2a387-83fc-4903-9006-a0f9393014fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
31336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1056731336
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1033421793
Short name T981
Test name
Test status
Simulation time 155533205 ps
CPU time 0.75 seconds
Started Jul 15 07:09:44 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206808 kb
Host smart-5ad4258f-e7f9-417c-9655-71f031c7fdb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
21793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1033421793
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.307927039
Short name T1638
Test name
Test status
Simulation time 170239820 ps
CPU time 0.95 seconds
Started Jul 15 07:09:47 PM PDT 24
Finished Jul 15 07:10:35 PM PDT 24
Peak memory 206844 kb
Host smart-f4a92e33-ae80-42ab-812a-311494c7659a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30792
7039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.307927039
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.778835844
Short name T500
Test name
Test status
Simulation time 4907063576 ps
CPU time 43.43 seconds
Started Jul 15 07:09:51 PM PDT 24
Finished Jul 15 07:11:20 PM PDT 24
Peak memory 207072 kb
Host smart-04908d3c-48a7-4529-a3df-752e02f246d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77883
5844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.778835844
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2878153686
Short name T292
Test name
Test status
Simulation time 190977892 ps
CPU time 0.79 seconds
Started Jul 15 07:09:56 PM PDT 24
Finished Jul 15 07:10:44 PM PDT 24
Peak memory 206800 kb
Host smart-7e07e0c7-217a-4077-b618-3947ca24e1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28781
53686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2878153686
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2665994894
Short name T708
Test name
Test status
Simulation time 23314027660 ps
CPU time 22 seconds
Started Jul 15 07:10:05 PM PDT 24
Finished Jul 15 07:11:15 PM PDT 24
Peak memory 206864 kb
Host smart-3420c733-1b0d-4a5e-a2a5-5dd384dd4bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
94894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2665994894
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.4145808141
Short name T1656
Test name
Test status
Simulation time 3299519857 ps
CPU time 3.74 seconds
Started Jul 15 07:10:04 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206864 kb
Host smart-4d39f0ff-cc76-4c84-9486-faebff19c037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41458
08141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.4145808141
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2690242523
Short name T139
Test name
Test status
Simulation time 10026036455 ps
CPU time 71.31 seconds
Started Jul 15 07:09:42 PM PDT 24
Finished Jul 15 07:11:36 PM PDT 24
Peak memory 207056 kb
Host smart-3e0d9be2-2fc9-4ac1-8259-dfb327e232bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26902
42523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2690242523
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2625588794
Short name T2121
Test name
Test status
Simulation time 7143669021 ps
CPU time 202.9 seconds
Started Jul 15 07:09:50 PM PDT 24
Finished Jul 15 07:13:59 PM PDT 24
Peak memory 207012 kb
Host smart-c9c45a56-00fa-469f-a974-3be8e02a2fc4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2625588794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2625588794
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3531511150
Short name T1129
Test name
Test status
Simulation time 282882016 ps
CPU time 0.87 seconds
Started Jul 15 07:09:54 PM PDT 24
Finished Jul 15 07:10:43 PM PDT 24
Peak memory 206800 kb
Host smart-ec6db37a-c2bd-46e7-8ef0-c64f7564ac76
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3531511150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3531511150
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.749581618
Short name T2145
Test name
Test status
Simulation time 203168434 ps
CPU time 0.86 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206792 kb
Host smart-32b9c0bd-b220-4f61-aa3f-af7b1842fef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74958
1618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.749581618
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2812059234
Short name T339
Test name
Test status
Simulation time 4531556623 ps
CPU time 43.27 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 207080 kb
Host smart-166b2ae2-2b9d-456f-8b4d-f0328000b11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28120
59234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2812059234
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.1857398723
Short name T2133
Test name
Test status
Simulation time 2956227732 ps
CPU time 19.97 seconds
Started Jul 15 07:10:03 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 207064 kb
Host smart-cee97d80-565b-4965-a888-e15267f2ab6b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1857398723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.1857398723
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1251382914
Short name T1331
Test name
Test status
Simulation time 231918727 ps
CPU time 0.84 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 206828 kb
Host smart-cd7db2f8-83e9-425a-84a0-4c7b44bac60f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1251382914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1251382914
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1105577612
Short name T1914
Test name
Test status
Simulation time 158286564 ps
CPU time 0.77 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 206800 kb
Host smart-bb58a5c9-01ef-479a-810b-7135049f9352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11055
77612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1105577612
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2645626061
Short name T119
Test name
Test status
Simulation time 243439427 ps
CPU time 0.89 seconds
Started Jul 15 07:09:52 PM PDT 24
Finished Jul 15 07:10:40 PM PDT 24
Peak memory 206808 kb
Host smart-56822282-7749-4db2-90e9-a59d7575a2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26456
26061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2645626061
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2902808588
Short name T548
Test name
Test status
Simulation time 215323379 ps
CPU time 0.82 seconds
Started Jul 15 07:09:51 PM PDT 24
Finished Jul 15 07:10:40 PM PDT 24
Peak memory 206792 kb
Host smart-1ac71dfd-8f32-4221-a57f-28acd9158522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29028
08588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2902808588
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3059857291
Short name T2428
Test name
Test status
Simulation time 160879283 ps
CPU time 0.75 seconds
Started Jul 15 07:10:02 PM PDT 24
Finished Jul 15 07:10:50 PM PDT 24
Peak memory 206800 kb
Host smart-dc3adb54-55b7-4210-b86b-8508e7ad676e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30598
57291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3059857291
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1462917015
Short name T768
Test name
Test status
Simulation time 153912663 ps
CPU time 0.76 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206648 kb
Host smart-8e46d4a6-7696-4b07-aa53-8f3964c131ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14629
17015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1462917015
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1220380134
Short name T2499
Test name
Test status
Simulation time 159438613 ps
CPU time 0.78 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 206800 kb
Host smart-c9fe87e6-cd91-42e0-8749-a210607f8c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12203
80134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1220380134
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3707766756
Short name T1438
Test name
Test status
Simulation time 206763432 ps
CPU time 0.88 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206804 kb
Host smart-67f3e944-bb39-47d9-b714-bf0940daad4e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3707766756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3707766756
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.189694781
Short name T1357
Test name
Test status
Simulation time 155083580 ps
CPU time 0.78 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206804 kb
Host smart-18ae162d-bc6b-4c04-b5c1-7cd6f5c21bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18969
4781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.189694781
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3020898352
Short name T1852
Test name
Test status
Simulation time 92725052 ps
CPU time 0.69 seconds
Started Jul 15 07:10:00 PM PDT 24
Finished Jul 15 07:10:47 PM PDT 24
Peak memory 206796 kb
Host smart-5f51c3cb-f8d7-47ac-91d5-0b57092ee6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30208
98352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3020898352
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2157063024
Short name T2642
Test name
Test status
Simulation time 8424740525 ps
CPU time 18.02 seconds
Started Jul 15 07:09:59 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 207040 kb
Host smart-8f54d6f3-5ddd-43d8-b74c-2d9b583faf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21570
63024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2157063024
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.940053423
Short name T2319
Test name
Test status
Simulation time 166826186 ps
CPU time 0.8 seconds
Started Jul 15 07:09:51 PM PDT 24
Finished Jul 15 07:10:37 PM PDT 24
Peak memory 206800 kb
Host smart-d7dd3b9d-f87d-4a20-a2dd-4a6aba778072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94005
3423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.940053423
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1062567040
Short name T2405
Test name
Test status
Simulation time 265850887 ps
CPU time 0.97 seconds
Started Jul 15 07:09:45 PM PDT 24
Finished Jul 15 07:10:30 PM PDT 24
Peak memory 206808 kb
Host smart-fdccfad8-a680-46cc-b117-fb4017ce2779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10625
67040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1062567040
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1001943265
Short name T286
Test name
Test status
Simulation time 189342345 ps
CPU time 0.8 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:33 PM PDT 24
Peak memory 206824 kb
Host smart-a2060d70-1f79-4cc8-800a-5fc15f2ca854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10019
43265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1001943265
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2229919956
Short name T2252
Test name
Test status
Simulation time 162260803 ps
CPU time 0.84 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206776 kb
Host smart-03710dc2-d5ae-4934-b463-9520975a2c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22299
19956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2229919956
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1999705232
Short name T1114
Test name
Test status
Simulation time 153283120 ps
CPU time 0.75 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:10:44 PM PDT 24
Peak memory 206800 kb
Host smart-30fd1844-cfad-4f78-aac7-993d13fa0869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19997
05232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1999705232
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2270789770
Short name T2254
Test name
Test status
Simulation time 151939331 ps
CPU time 0.75 seconds
Started Jul 15 07:09:59 PM PDT 24
Finished Jul 15 07:10:47 PM PDT 24
Peak memory 206800 kb
Host smart-f91c4a18-4b68-4628-98d7-23c44008054b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22707
89770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2270789770
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3347568089
Short name T1271
Test name
Test status
Simulation time 166196010 ps
CPU time 0.79 seconds
Started Jul 15 07:09:43 PM PDT 24
Finished Jul 15 07:10:27 PM PDT 24
Peak memory 206824 kb
Host smart-0f0f3c64-b7ea-4b26-8b3d-4f8eb7e01f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475
68089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3347568089
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1626516383
Short name T689
Test name
Test status
Simulation time 244708734 ps
CPU time 0.95 seconds
Started Jul 15 07:09:46 PM PDT 24
Finished Jul 15 07:10:34 PM PDT 24
Peak memory 206824 kb
Host smart-42c29232-1296-4c81-8f8c-cb785d735f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16265
16383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1626516383
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.3518909924
Short name T1983
Test name
Test status
Simulation time 5928769920 ps
CPU time 52.66 seconds
Started Jul 15 07:09:44 PM PDT 24
Finished Jul 15 07:11:21 PM PDT 24
Peak memory 207020 kb
Host smart-7e2f6046-ca18-4927-aaa3-4801785664bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3518909924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3518909924
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3982092009
Short name T657
Test name
Test status
Simulation time 188492538 ps
CPU time 0.8 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206776 kb
Host smart-c89524ee-f3a9-43a0-bbfd-c0fe5b6d2907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39820
92009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3982092009
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2165646898
Short name T1540
Test name
Test status
Simulation time 222285752 ps
CPU time 0.8 seconds
Started Jul 15 07:09:54 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206804 kb
Host smart-154428b3-3eed-426d-85c4-30618ca7be82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21656
46898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2165646898
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.2724036938
Short name T296
Test name
Test status
Simulation time 1315310952 ps
CPU time 2.57 seconds
Started Jul 15 07:09:58 PM PDT 24
Finished Jul 15 07:10:48 PM PDT 24
Peak memory 206956 kb
Host smart-8126a93a-15ca-4dbd-b19e-225c1ca0c778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27240
36938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.2724036938
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3734038572
Short name T510
Test name
Test status
Simulation time 5156125963 ps
CPU time 139.71 seconds
Started Jul 15 07:09:47 PM PDT 24
Finished Jul 15 07:12:53 PM PDT 24
Peak memory 207012 kb
Host smart-f948c2a6-1a87-4141-8d75-1e0834a3d464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37340
38572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3734038572
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3967370053
Short name T1410
Test name
Test status
Simulation time 46314314 ps
CPU time 0.67 seconds
Started Jul 15 07:10:04 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 206848 kb
Host smart-89e3e213-2764-4aed-8ec9-f54f3654a2b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3967370053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3967370053
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3827195497
Short name T1868
Test name
Test status
Simulation time 4035675789 ps
CPU time 5.12 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:10:48 PM PDT 24
Peak memory 206984 kb
Host smart-0ec8a326-7f4f-4e80-8631-cfb5d22fcb57
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3827195497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3827195497
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1429691980
Short name T2085
Test name
Test status
Simulation time 13354810101 ps
CPU time 11.97 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:10:55 PM PDT 24
Peak memory 206816 kb
Host smart-020e7e4a-68d6-4b6c-b175-15428293db6a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1429691980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1429691980
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.729879912
Short name T1693
Test name
Test status
Simulation time 23385790516 ps
CPU time 22.66 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206812 kb
Host smart-012b725c-e8b1-417c-8f03-a3bcf65df8aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=729879912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.729879912
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.464656568
Short name T1998
Test name
Test status
Simulation time 156677149 ps
CPU time 0.8 seconds
Started Jul 15 07:10:03 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 206836 kb
Host smart-4d8de83f-55ea-4a2b-b7f1-8c03a7157819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46465
6568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.464656568
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1094747559
Short name T1170
Test name
Test status
Simulation time 163425667 ps
CPU time 0.8 seconds
Started Jul 15 07:09:51 PM PDT 24
Finished Jul 15 07:10:38 PM PDT 24
Peak memory 206812 kb
Host smart-5426f901-d136-4db1-9876-2c9d1a575b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10947
47559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1094747559
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1175356478
Short name T587
Test name
Test status
Simulation time 270901644 ps
CPU time 0.92 seconds
Started Jul 15 07:09:52 PM PDT 24
Finished Jul 15 07:10:40 PM PDT 24
Peak memory 206772 kb
Host smart-be06ce00-e6e9-4a5a-ba6a-4a07e3731928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11753
56478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1175356478
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2594298785
Short name T2571
Test name
Test status
Simulation time 1148843591 ps
CPU time 2.33 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:10:45 PM PDT 24
Peak memory 206968 kb
Host smart-f25bec70-4be7-40a6-b093-f9e20e0aeac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25942
98785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2594298785
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1420626961
Short name T2508
Test name
Test status
Simulation time 7628396092 ps
CPU time 17.3 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:57 PM PDT 24
Peak memory 207064 kb
Host smart-f08e404e-e8b5-4a4c-8af5-bf4c71ecdcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14206
26961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1420626961
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1812893786
Short name T2744
Test name
Test status
Simulation time 320816913 ps
CPU time 1.05 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206804 kb
Host smart-22c7a3d5-518e-4fad-9052-d3e225549b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
93786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1812893786
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3973307287
Short name T18
Test name
Test status
Simulation time 180771234 ps
CPU time 0.77 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206828 kb
Host smart-7cebf415-37fb-4b07-8a98-3ceaa476fdd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39733
07287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3973307287
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2487105977
Short name T2736
Test name
Test status
Simulation time 32436667 ps
CPU time 0.65 seconds
Started Jul 15 07:09:59 PM PDT 24
Finished Jul 15 07:10:47 PM PDT 24
Peak memory 206792 kb
Host smart-81186d05-5215-460c-a8a3-b77314807ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24871
05977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2487105977
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2423409600
Short name T2379
Test name
Test status
Simulation time 860464172 ps
CPU time 1.88 seconds
Started Jul 15 07:09:59 PM PDT 24
Finished Jul 15 07:10:48 PM PDT 24
Peak memory 206968 kb
Host smart-9d970e3f-a1b9-4a37-b529-e745438cad81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24234
09600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2423409600
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.269959385
Short name T1255
Test name
Test status
Simulation time 183650166 ps
CPU time 1.51 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:10:45 PM PDT 24
Peak memory 206972 kb
Host smart-80e7ff09-e92d-4871-a7eb-4e0ec0f66d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26995
9385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.269959385
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.947307323
Short name T2275
Test name
Test status
Simulation time 189011925 ps
CPU time 0.84 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206820 kb
Host smart-dcbeb103-d8dd-4a1c-bee4-057a0737ebd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94730
7323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.947307323
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1948699259
Short name T2686
Test name
Test status
Simulation time 162666633 ps
CPU time 0.75 seconds
Started Jul 15 07:09:57 PM PDT 24
Finished Jul 15 07:10:45 PM PDT 24
Peak memory 206824 kb
Host smart-81927aac-bfeb-4102-b8da-6dc81d8aba3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19486
99259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1948699259
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3122783752
Short name T1111
Test name
Test status
Simulation time 282855395 ps
CPU time 0.95 seconds
Started Jul 15 07:09:56 PM PDT 24
Finished Jul 15 07:10:45 PM PDT 24
Peak memory 206792 kb
Host smart-6599bfe3-be86-4610-9587-d8552550f8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31227
83752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3122783752
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.1557243780
Short name T378
Test name
Test status
Simulation time 12131684058 ps
CPU time 39.83 seconds
Started Jul 15 07:10:00 PM PDT 24
Finished Jul 15 07:11:27 PM PDT 24
Peak memory 207172 kb
Host smart-b8404916-1a1f-4fa1-a4a9-15b3d160e42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
43780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.1557243780
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.3657281688
Short name T2009
Test name
Test status
Simulation time 197891499 ps
CPU time 0.8 seconds
Started Jul 15 07:09:59 PM PDT 24
Finished Jul 15 07:10:47 PM PDT 24
Peak memory 206820 kb
Host smart-6b036528-eba4-4fde-b1ce-872901d62845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36572
81688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.3657281688
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3449527857
Short name T1672
Test name
Test status
Simulation time 23284593325 ps
CPU time 21.3 seconds
Started Jul 15 07:09:58 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206840 kb
Host smart-284288a4-3736-4609-8f0b-9a9c7d73929c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34495
27857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3449527857
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.4081974605
Short name T1635
Test name
Test status
Simulation time 3344024290 ps
CPU time 3.97 seconds
Started Jul 15 07:09:58 PM PDT 24
Finished Jul 15 07:10:50 PM PDT 24
Peak memory 206888 kb
Host smart-d9cf4b0e-1d11-44e9-a99d-6f3271dd19ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40819
74605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.4081974605
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.947271551
Short name T496
Test name
Test status
Simulation time 5455056583 ps
CPU time 145.03 seconds
Started Jul 15 07:10:03 PM PDT 24
Finished Jul 15 07:13:15 PM PDT 24
Peak memory 207076 kb
Host smart-ae7b4e66-a9ee-43c0-a84f-74eb1545690f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94727
1551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.947271551
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3285260127
Short name T2052
Test name
Test status
Simulation time 7341710668 ps
CPU time 195.48 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:13:58 PM PDT 24
Peak memory 207044 kb
Host smart-b7ddb3eb-1a4a-4ce0-884d-7e42dfe83370
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3285260127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3285260127
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2826532117
Short name T2013
Test name
Test status
Simulation time 256159174 ps
CPU time 0.98 seconds
Started Jul 15 07:09:54 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206820 kb
Host smart-dabd3172-d685-4344-85aa-73f52329ba0b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2826532117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2826532117
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.104571795
Short name T1160
Test name
Test status
Simulation time 197585080 ps
CPU time 0.84 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:10:44 PM PDT 24
Peak memory 206820 kb
Host smart-afca36bb-aef7-4f5a-a174-eae190d3eb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
1795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.104571795
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.4029141817
Short name T1577
Test name
Test status
Simulation time 5107185313 ps
CPU time 132.49 seconds
Started Jul 15 07:09:55 PM PDT 24
Finished Jul 15 07:12:56 PM PDT 24
Peak memory 207032 kb
Host smart-44399b9a-0075-4007-a4e2-196c9317f570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40291
41817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.4029141817
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3287641200
Short name T997
Test name
Test status
Simulation time 4188575494 ps
CPU time 39.79 seconds
Started Jul 15 07:09:58 PM PDT 24
Finished Jul 15 07:11:25 PM PDT 24
Peak memory 207020 kb
Host smart-8b7d30a6-b525-4b66-953d-4c54be8d387b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3287641200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3287641200
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2629962724
Short name T964
Test name
Test status
Simulation time 159628545 ps
CPU time 0.77 seconds
Started Jul 15 07:09:54 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206828 kb
Host smart-83ede8f4-a7c3-4a3b-9165-7e5284e93f4a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2629962724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2629962724
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1128378763
Short name T1653
Test name
Test status
Simulation time 170375061 ps
CPU time 0.77 seconds
Started Jul 15 07:09:54 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206796 kb
Host smart-7164de56-c78e-4d20-aa2c-b59eef8f5775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11283
78763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1128378763
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3619727147
Short name T118
Test name
Test status
Simulation time 238431492 ps
CPU time 0.92 seconds
Started Jul 15 07:10:01 PM PDT 24
Finished Jul 15 07:10:48 PM PDT 24
Peak memory 206648 kb
Host smart-2d216cf2-af5f-4c50-b4cc-0dd273f6398d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197
27147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3619727147
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3251478561
Short name T1065
Test name
Test status
Simulation time 202056823 ps
CPU time 0.84 seconds
Started Jul 15 07:09:58 PM PDT 24
Finished Jul 15 07:10:47 PM PDT 24
Peak memory 206820 kb
Host smart-9c301935-feaa-42a9-974c-c34fe286b17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32514
78561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3251478561
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1949077167
Short name T1180
Test name
Test status
Simulation time 183074926 ps
CPU time 0.79 seconds
Started Jul 15 07:09:56 PM PDT 24
Finished Jul 15 07:10:44 PM PDT 24
Peak memory 206644 kb
Host smart-31e78f82-7627-4456-a1db-ed9d418d74e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19490
77167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1949077167
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2769016239
Short name T906
Test name
Test status
Simulation time 235408107 ps
CPU time 0.78 seconds
Started Jul 15 07:10:01 PM PDT 24
Finished Jul 15 07:10:49 PM PDT 24
Peak memory 206648 kb
Host smart-3e952f73-622a-4b27-a630-9b0545f05f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27690
16239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2769016239
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.5574373
Short name T149
Test name
Test status
Simulation time 163571109 ps
CPU time 0.77 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206812 kb
Host smart-588109f6-e70e-457b-8729-3de26c279748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55743
73 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.5574373
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3302745113
Short name T1916
Test name
Test status
Simulation time 194517561 ps
CPU time 0.87 seconds
Started Jul 15 07:10:06 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206824 kb
Host smart-6b8570ca-03be-4deb-8a36-6f16ed0c8a0c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3302745113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3302745113
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1776228892
Short name T1504
Test name
Test status
Simulation time 154536546 ps
CPU time 0.77 seconds
Started Jul 15 07:09:54 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206820 kb
Host smart-c943b0b3-67f7-4d47-808c-e02e4fff1a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17762
28892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1776228892
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.4154488307
Short name T887
Test name
Test status
Simulation time 39509056 ps
CPU time 0.69 seconds
Started Jul 15 07:09:53 PM PDT 24
Finished Jul 15 07:10:41 PM PDT 24
Peak memory 206788 kb
Host smart-7e34d07d-6f6d-4b0c-bcad-29722e06463e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41544
88307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.4154488307
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.426450693
Short name T235
Test name
Test status
Simulation time 23938355282 ps
CPU time 51.21 seconds
Started Jul 15 07:10:01 PM PDT 24
Finished Jul 15 07:11:40 PM PDT 24
Peak memory 207048 kb
Host smart-19fb239b-e2d7-4ad6-8997-8df8eae4fb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42645
0693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.426450693
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1587473740
Short name T1666
Test name
Test status
Simulation time 157234471 ps
CPU time 0.78 seconds
Started Jul 15 07:10:04 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 206808 kb
Host smart-1785f0c5-5487-4ecc-b61d-a6368d707a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15874
73740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1587473740
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1618197366
Short name T741
Test name
Test status
Simulation time 201458276 ps
CPU time 0.84 seconds
Started Jul 15 07:10:04 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 206820 kb
Host smart-700ea5da-710d-43b8-8540-e4a2277469f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16181
97366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1618197366
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2128043809
Short name T939
Test name
Test status
Simulation time 207774899 ps
CPU time 0.89 seconds
Started Jul 15 07:09:58 PM PDT 24
Finished Jul 15 07:10:46 PM PDT 24
Peak memory 206816 kb
Host smart-5fde3716-bb5d-4e0f-a6c1-113ce78e6eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21280
43809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2128043809
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3295845630
Short name T2587
Test name
Test status
Simulation time 161258764 ps
CPU time 0.8 seconds
Started Jul 15 07:10:04 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 206800 kb
Host smart-ad15b62e-a87c-47d5-bda2-064d70a6ee5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958
45630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3295845630
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2332986347
Short name T1095
Test name
Test status
Simulation time 213675701 ps
CPU time 0.84 seconds
Started Jul 15 07:10:05 PM PDT 24
Finished Jul 15 07:10:53 PM PDT 24
Peak memory 206820 kb
Host smart-02d11b78-c16d-4b64-955e-a6b9c9c8bff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23329
86347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2332986347
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.327163254
Short name T1748
Test name
Test status
Simulation time 164931684 ps
CPU time 0.79 seconds
Started Jul 15 07:10:07 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206816 kb
Host smart-b6e73b1a-660f-4324-af5a-bd32930736f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32716
3254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.327163254
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1647046982
Short name T1242
Test name
Test status
Simulation time 148954318 ps
CPU time 0.74 seconds
Started Jul 15 07:10:03 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 206804 kb
Host smart-9947fb03-d354-4b04-85df-095208ae57ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16470
46982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1647046982
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2259316227
Short name T427
Test name
Test status
Simulation time 255243709 ps
CPU time 0.98 seconds
Started Jul 15 07:10:07 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206820 kb
Host smart-f7b478e8-6ed6-4123-aaad-8879aa217d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
16227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2259316227
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1330605445
Short name T1845
Test name
Test status
Simulation time 5679694469 ps
CPU time 40.23 seconds
Started Jul 15 07:10:00 PM PDT 24
Finished Jul 15 07:11:27 PM PDT 24
Peak memory 207028 kb
Host smart-370c0730-81fc-4fa7-adea-a0436b5c4f5d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1330605445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1330605445
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2071529025
Short name T2038
Test name
Test status
Simulation time 169277421 ps
CPU time 0.81 seconds
Started Jul 15 07:10:05 PM PDT 24
Finished Jul 15 07:10:53 PM PDT 24
Peak memory 206804 kb
Host smart-b5e5e019-b051-4dc1-8bdb-7f4a8600f256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
29025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2071529025
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1671822094
Short name T2601
Test name
Test status
Simulation time 165541869 ps
CPU time 0.78 seconds
Started Jul 15 07:10:10 PM PDT 24
Finished Jul 15 07:10:57 PM PDT 24
Peak memory 206760 kb
Host smart-0a298e94-548d-4a1e-a2ab-89afdb32fded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16718
22094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1671822094
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.4242092481
Short name T1401
Test name
Test status
Simulation time 746999035 ps
CPU time 1.74 seconds
Started Jul 15 07:10:07 PM PDT 24
Finished Jul 15 07:10:55 PM PDT 24
Peak memory 206960 kb
Host smart-8cff7b14-cba5-405c-ac5f-e177f10483f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42420
92481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.4242092481
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.326624838
Short name T1619
Test name
Test status
Simulation time 6984583904 ps
CPU time 68.08 seconds
Started Jul 15 07:10:06 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 207080 kb
Host smart-eabe7ee8-ee7d-4330-8750-d54ceefe54bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
4838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.326624838
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.1815151793
Short name T1771
Test name
Test status
Simulation time 83279504 ps
CPU time 0.69 seconds
Started Jul 15 07:10:20 PM PDT 24
Finished Jul 15 07:11:03 PM PDT 24
Peak memory 206868 kb
Host smart-6886d21b-d858-492a-8f04-bb1483c42783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1815151793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1815151793
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2872993838
Short name T2050
Test name
Test status
Simulation time 4208237256 ps
CPU time 4.61 seconds
Started Jul 15 07:10:06 PM PDT 24
Finished Jul 15 07:10:57 PM PDT 24
Peak memory 207032 kb
Host smart-ece70a85-6c54-4e45-9599-3b9b9a668618
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2872993838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.2872993838
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1667408501
Short name T2540
Test name
Test status
Simulation time 13341180163 ps
CPU time 15.04 seconds
Started Jul 15 07:10:05 PM PDT 24
Finished Jul 15 07:11:08 PM PDT 24
Peak memory 206832 kb
Host smart-a281ba5e-84c8-460f-89fc-4a2ad10d6ba7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1667408501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1667408501
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3431223430
Short name T12
Test name
Test status
Simulation time 23361483258 ps
CPU time 23.71 seconds
Started Jul 15 07:09:59 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206868 kb
Host smart-763235dc-67ac-4bf2-b53c-d8b2857d9c22
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3431223430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3431223430
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.4248138285
Short name T1530
Test name
Test status
Simulation time 167981367 ps
CPU time 0.76 seconds
Started Jul 15 07:10:05 PM PDT 24
Finished Jul 15 07:10:53 PM PDT 24
Peak memory 206756 kb
Host smart-c714c7eb-a6b2-439f-8323-87f85e8d5b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42481
38285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.4248138285
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2064913998
Short name T2375
Test name
Test status
Simulation time 151296279 ps
CPU time 0.79 seconds
Started Jul 15 07:10:10 PM PDT 24
Finished Jul 15 07:10:57 PM PDT 24
Peak memory 206820 kb
Host smart-64c8e672-05a2-49fe-b19c-507d076ef875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20649
13998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2064913998
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.1023964740
Short name T2648
Test name
Test status
Simulation time 430371267 ps
CPU time 1.24 seconds
Started Jul 15 07:10:04 PM PDT 24
Finished Jul 15 07:10:51 PM PDT 24
Peak memory 206792 kb
Host smart-83b2a0bb-d7f4-4ab2-9336-75d6ccdd49b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10239
64740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.1023964740
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1313452076
Short name T2069
Test name
Test status
Simulation time 572136162 ps
CPU time 1.43 seconds
Started Jul 15 07:10:07 PM PDT 24
Finished Jul 15 07:10:55 PM PDT 24
Peak memory 206796 kb
Host smart-7bba531f-aab9-4a60-841f-0843c115ca08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
52076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1313452076
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1566063084
Short name T2097
Test name
Test status
Simulation time 13167346652 ps
CPU time 22.11 seconds
Started Jul 15 07:10:10 PM PDT 24
Finished Jul 15 07:11:18 PM PDT 24
Peak memory 207088 kb
Host smart-6fc6da23-c4c4-4ab0-888a-3533ac47f7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15660
63084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1566063084
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.716176848
Short name T792
Test name
Test status
Simulation time 398952040 ps
CPU time 1.28 seconds
Started Jul 15 07:10:05 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206832 kb
Host smart-cf519592-414f-4c60-878b-74f17e179b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71617
6848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.716176848
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2453288576
Short name T1552
Test name
Test status
Simulation time 184649149 ps
CPU time 0.77 seconds
Started Jul 15 07:10:05 PM PDT 24
Finished Jul 15 07:10:53 PM PDT 24
Peak memory 206756 kb
Host smart-d2f240da-883c-483f-b862-8f4bd786036d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24532
88576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2453288576
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2913765147
Short name T1945
Test name
Test status
Simulation time 41498215 ps
CPU time 0.65 seconds
Started Jul 15 07:10:07 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206800 kb
Host smart-ea6aec04-185a-437d-a7f9-afa53c66be5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29137
65147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2913765147
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1746667399
Short name T1003
Test name
Test status
Simulation time 944777913 ps
CPU time 2.36 seconds
Started Jul 15 07:10:00 PM PDT 24
Finished Jul 15 07:10:49 PM PDT 24
Peak memory 206952 kb
Host smart-ee341cd7-eba1-4e06-b58a-762d7542e394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17466
67399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1746667399
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1858287011
Short name T1463
Test name
Test status
Simulation time 187652590 ps
CPU time 1.94 seconds
Started Jul 15 07:10:06 PM PDT 24
Finished Jul 15 07:10:55 PM PDT 24
Peak memory 206928 kb
Host smart-780078c0-d9c6-42f8-8e22-85adc57f79f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18582
87011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1858287011
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.4869380
Short name T103
Test name
Test status
Simulation time 240252737 ps
CPU time 0.88 seconds
Started Jul 15 07:10:07 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206812 kb
Host smart-f2fda669-74b9-48bb-b707-a38608f999ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48693
80 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.4869380
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3354051757
Short name T2655
Test name
Test status
Simulation time 143856581 ps
CPU time 0.78 seconds
Started Jul 15 07:10:09 PM PDT 24
Finished Jul 15 07:10:56 PM PDT 24
Peak memory 206788 kb
Host smart-94cb2239-1b89-45c6-8ee2-e5eb766523b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33540
51757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3354051757
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.4157742046
Short name T1446
Test name
Test status
Simulation time 207910527 ps
CPU time 0.85 seconds
Started Jul 15 07:10:08 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206800 kb
Host smart-e86ab234-4ae3-4e30-aa82-6be988e69c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41577
42046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.4157742046
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2993020501
Short name T1630
Test name
Test status
Simulation time 7705148683 ps
CPU time 70.39 seconds
Started Jul 15 07:10:08 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 207044 kb
Host smart-457a5d7a-3190-48b0-a357-4111466d575a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2993020501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2993020501
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.2183232490
Short name T2126
Test name
Test status
Simulation time 14236933646 ps
CPU time 42.92 seconds
Started Jul 15 07:10:06 PM PDT 24
Finished Jul 15 07:11:36 PM PDT 24
Peak memory 207064 kb
Host smart-09ead95a-4297-4d9c-a302-a3cb1f38ba19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
32490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.2183232490
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3301852960
Short name T2370
Test name
Test status
Simulation time 187742652 ps
CPU time 0.79 seconds
Started Jul 15 07:10:09 PM PDT 24
Finished Jul 15 07:10:56 PM PDT 24
Peak memory 206808 kb
Host smart-5dfe5c8a-272a-41e2-a942-c45313bb2669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33018
52960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3301852960
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.664573333
Short name T1604
Test name
Test status
Simulation time 23342134028 ps
CPU time 23.07 seconds
Started Jul 15 07:10:10 PM PDT 24
Finished Jul 15 07:11:19 PM PDT 24
Peak memory 206888 kb
Host smart-02f8bec1-4ac9-4691-b819-4f55f11744e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66457
3333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.664573333
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.358534611
Short name T2697
Test name
Test status
Simulation time 3326468626 ps
CPU time 3.92 seconds
Started Jul 15 07:10:14 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206880 kb
Host smart-2f6cdd60-d7bc-4a0e-a2ed-00b76496a286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35853
4611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.358534611
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1511793917
Short name T613
Test name
Test status
Simulation time 10140606431 ps
CPU time 96.57 seconds
Started Jul 15 07:10:10 PM PDT 24
Finished Jul 15 07:12:33 PM PDT 24
Peak memory 207096 kb
Host smart-fed3a076-1126-4ea2-9144-5f2443b821a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15117
93917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1511793917
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.4192367855
Short name T1471
Test name
Test status
Simulation time 4051551667 ps
CPU time 38.8 seconds
Started Jul 15 07:10:06 PM PDT 24
Finished Jul 15 07:11:32 PM PDT 24
Peak memory 207064 kb
Host smart-b4df600a-3e0e-431e-8c89-7596f0821d47
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4192367855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.4192367855
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3093379826
Short name T843
Test name
Test status
Simulation time 248555047 ps
CPU time 0.9 seconds
Started Jul 15 07:10:06 PM PDT 24
Finished Jul 15 07:10:53 PM PDT 24
Peak memory 206800 kb
Host smart-917d3d0f-287a-48a5-bc75-2e9f0db02ba2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3093379826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3093379826
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1677386897
Short name T1733
Test name
Test status
Simulation time 193849805 ps
CPU time 0.86 seconds
Started Jul 15 07:10:07 PM PDT 24
Finished Jul 15 07:10:54 PM PDT 24
Peak memory 206824 kb
Host smart-c2a83f85-b05a-4504-8ece-4c1cd6fba9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16773
86897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1677386897
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2332189709
Short name T2528
Test name
Test status
Simulation time 7013553740 ps
CPU time 65.42 seconds
Started Jul 15 07:10:07 PM PDT 24
Finished Jul 15 07:11:59 PM PDT 24
Peak memory 207048 kb
Host smart-35abd678-b875-42e0-aa14-6e83ee539e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23321
89709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2332189709
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2114468462
Short name T910
Test name
Test status
Simulation time 6925883824 ps
CPU time 179.08 seconds
Started Jul 15 07:10:08 PM PDT 24
Finished Jul 15 07:13:52 PM PDT 24
Peak memory 207080 kb
Host smart-51593b8a-ac10-4809-baf9-0db8454ee89d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2114468462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2114468462
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.2234307195
Short name T641
Test name
Test status
Simulation time 177652671 ps
CPU time 0.79 seconds
Started Jul 15 07:10:14 PM PDT 24
Finished Jul 15 07:11:01 PM PDT 24
Peak memory 206756 kb
Host smart-a7b5cb57-c531-4014-860c-a5856c4f1e3d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2234307195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2234307195
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3792478996
Short name T2579
Test name
Test status
Simulation time 146938308 ps
CPU time 0.82 seconds
Started Jul 15 07:10:20 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206804 kb
Host smart-d80d38bb-6fa3-4c42-a71a-5a13c8f23af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37924
78996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3792478996
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2978187093
Short name T137
Test name
Test status
Simulation time 207184296 ps
CPU time 0.84 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206788 kb
Host smart-4cc2375b-7ee8-4eba-9ab5-122ebc480a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29781
87093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2978187093
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2011677470
Short name T1851
Test name
Test status
Simulation time 160632987 ps
CPU time 0.81 seconds
Started Jul 15 07:10:13 PM PDT 24
Finished Jul 15 07:11:00 PM PDT 24
Peak memory 206820 kb
Host smart-bed72694-121c-4d0c-abb4-38cd70560a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20116
77470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2011677470
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.138560611
Short name T446
Test name
Test status
Simulation time 214170298 ps
CPU time 0.93 seconds
Started Jul 15 07:10:24 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206848 kb
Host smart-3fc6101b-daa7-4c52-97a1-c2dbbf786e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
0611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.138560611
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1995350370
Short name T1559
Test name
Test status
Simulation time 178805405 ps
CPU time 0.76 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206764 kb
Host smart-08fa520e-4f54-4df4-9296-84eb0562be86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
50370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1995350370
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1961538373
Short name T162
Test name
Test status
Simulation time 233810520 ps
CPU time 0.88 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206828 kb
Host smart-e7634e2d-ae4a-4452-8f55-6b3204467565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
38373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1961538373
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3344622433
Short name T681
Test name
Test status
Simulation time 225665493 ps
CPU time 0.88 seconds
Started Jul 15 07:10:12 PM PDT 24
Finished Jul 15 07:10:59 PM PDT 24
Peak memory 206836 kb
Host smart-51ab9d6a-3a53-40ea-aaa6-4995df637a4a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3344622433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3344622433
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2432688366
Short name T437
Test name
Test status
Simulation time 154219146 ps
CPU time 0.8 seconds
Started Jul 15 07:10:19 PM PDT 24
Finished Jul 15 07:11:03 PM PDT 24
Peak memory 206808 kb
Host smart-19578a6c-b82b-49cd-83ce-30dccf15d255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24326
88366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2432688366
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3071399725
Short name T1972
Test name
Test status
Simulation time 36708422 ps
CPU time 0.66 seconds
Started Jul 15 07:10:14 PM PDT 24
Finished Jul 15 07:11:01 PM PDT 24
Peak memory 206784 kb
Host smart-c6979889-6f9a-468b-835f-3d73b5fefa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30713
99725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3071399725
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2520123320
Short name T2598
Test name
Test status
Simulation time 13745176681 ps
CPU time 32.97 seconds
Started Jul 15 07:10:18 PM PDT 24
Finished Jul 15 07:11:35 PM PDT 24
Peak memory 215332 kb
Host smart-b2fec964-383a-41cc-8dac-56ff1ca39da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
23320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2520123320
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2421359276
Short name T2249
Test name
Test status
Simulation time 153306087 ps
CPU time 0.77 seconds
Started Jul 15 07:10:17 PM PDT 24
Finished Jul 15 07:11:02 PM PDT 24
Peak memory 206804 kb
Host smart-8cf12169-e67d-4d61-a508-d6a6f793b79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24213
59276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2421359276
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.167041211
Short name T698
Test name
Test status
Simulation time 213329283 ps
CPU time 0.86 seconds
Started Jul 15 07:10:22 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206808 kb
Host smart-9d192fd9-b564-46a6-a890-a8397d51a2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16704
1211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.167041211
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.463365627
Short name T2010
Test name
Test status
Simulation time 190186099 ps
CPU time 0.87 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206828 kb
Host smart-f0a97cdf-6a7a-4a9d-9488-4cbcd412631d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46336
5627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.463365627
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3115999681
Short name T2657
Test name
Test status
Simulation time 190410928 ps
CPU time 0.79 seconds
Started Jul 15 07:10:22 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206800 kb
Host smart-d8ca42e2-f3c6-4fdd-9c7d-c3efac56db2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31159
99681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3115999681
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.999697449
Short name T2450
Test name
Test status
Simulation time 186498392 ps
CPU time 0.86 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206784 kb
Host smart-55f855ef-b1aa-4be4-965a-131e39317411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99969
7449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.999697449
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1012290770
Short name T2498
Test name
Test status
Simulation time 158409187 ps
CPU time 0.74 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:03 PM PDT 24
Peak memory 206808 kb
Host smart-776552a3-43d2-411d-90f3-8724603257cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10122
90770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1012290770
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.995214904
Short name T1334
Test name
Test status
Simulation time 166127395 ps
CPU time 0.81 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206816 kb
Host smart-2f5de2b1-2f68-4c4e-b387-24fda2443b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99521
4904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.995214904
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1847624892
Short name T2324
Test name
Test status
Simulation time 221134198 ps
CPU time 0.89 seconds
Started Jul 15 07:10:19 PM PDT 24
Finished Jul 15 07:11:03 PM PDT 24
Peak memory 206760 kb
Host smart-d950e9f6-ca7d-4ec2-9882-8351ef8192f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18476
24892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1847624892
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3906355855
Short name T2555
Test name
Test status
Simulation time 5890858451 ps
CPU time 55.82 seconds
Started Jul 15 07:10:13 PM PDT 24
Finished Jul 15 07:11:55 PM PDT 24
Peak memory 207064 kb
Host smart-b837d1f2-c6ca-44cb-bbeb-793d52aac885
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3906355855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3906355855
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.667667198
Short name T1499
Test name
Test status
Simulation time 161237137 ps
CPU time 0.81 seconds
Started Jul 15 07:10:19 PM PDT 24
Finished Jul 15 07:11:03 PM PDT 24
Peak memory 206824 kb
Host smart-fcfb4563-f5f1-4501-993a-c905df25bc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66766
7198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.667667198
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2728177497
Short name T2730
Test name
Test status
Simulation time 141751590 ps
CPU time 0.81 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206784 kb
Host smart-0e2e1891-8d8e-443e-893f-282ed3f4e8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27281
77497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2728177497
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.770400980
Short name T934
Test name
Test status
Simulation time 642595689 ps
CPU time 1.57 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206832 kb
Host smart-9103166b-9462-4d12-abc1-f5ae92718043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77040
0980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.770400980
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.4235985155
Short name T1006
Test name
Test status
Simulation time 4361666352 ps
CPU time 118.03 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:13:01 PM PDT 24
Peak memory 207036 kb
Host smart-8baa14a2-e257-4ca7-ac40-ffb3b5598fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42359
85155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.4235985155
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.801461456
Short name T995
Test name
Test status
Simulation time 68403435 ps
CPU time 0.72 seconds
Started Jul 15 07:10:33 PM PDT 24
Finished Jul 15 07:11:07 PM PDT 24
Peak memory 206740 kb
Host smart-bace29f8-178b-4354-8aa6-bb0e399ef4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=801461456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.801461456
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3698436421
Short name T839
Test name
Test status
Simulation time 4409422118 ps
CPU time 4.76 seconds
Started Jul 15 07:10:24 PM PDT 24
Finished Jul 15 07:11:08 PM PDT 24
Peak memory 207068 kb
Host smart-c7d8502c-fd15-4bc5-89c6-531cf3eb80ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3698436421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3698436421
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1651186149
Short name T2221
Test name
Test status
Simulation time 13361189799 ps
CPU time 12.35 seconds
Started Jul 15 07:10:22 PM PDT 24
Finished Jul 15 07:11:15 PM PDT 24
Peak memory 206852 kb
Host smart-adc61b69-59e7-4937-9817-609111af9233
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1651186149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1651186149
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3943762701
Short name T1012
Test name
Test status
Simulation time 23374033425 ps
CPU time 23.22 seconds
Started Jul 15 07:10:22 PM PDT 24
Finished Jul 15 07:11:26 PM PDT 24
Peak memory 206132 kb
Host smart-d2304b32-7409-4da2-9a13-b3c632fd52b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3943762701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3943762701
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2512533981
Short name T1773
Test name
Test status
Simulation time 155894116 ps
CPU time 0.77 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206776 kb
Host smart-04b6f901-cb4f-4c5d-9b59-2e017c0597e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25125
33981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2512533981
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2714847812
Short name T56
Test name
Test status
Simulation time 183260672 ps
CPU time 0.78 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206824 kb
Host smart-e8eae9fe-ed5b-4da1-900f-9bd46deaaf10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27148
47812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2714847812
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3752378802
Short name T937
Test name
Test status
Simulation time 444921772 ps
CPU time 1.31 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206820 kb
Host smart-dfa4ea0d-36df-4748-8236-4ca2bfd2a22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37523
78802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3752378802
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2005088387
Short name T942
Test name
Test status
Simulation time 1235909794 ps
CPU time 2.8 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206968 kb
Host smart-bed741cc-c02a-4c9b-ab86-c48d6e341c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20050
88387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2005088387
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.4167880686
Short name T85
Test name
Test status
Simulation time 13071726704 ps
CPU time 24.92 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:28 PM PDT 24
Peak memory 207020 kb
Host smart-1779642c-3dea-4489-9bbd-37f4cd0b785b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41678
80686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.4167880686
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1840681386
Short name T956
Test name
Test status
Simulation time 474533772 ps
CPU time 1.33 seconds
Started Jul 15 07:10:24 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206800 kb
Host smart-6caf075c-4250-4673-a8b3-58359fac3cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18406
81386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1840681386
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.4054320248
Short name T1072
Test name
Test status
Simulation time 144865354 ps
CPU time 0.74 seconds
Started Jul 15 07:10:22 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206236 kb
Host smart-6e523419-4942-4438-b742-cdb476ee7a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40543
20248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.4054320248
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2978047326
Short name T757
Test name
Test status
Simulation time 36587045 ps
CPU time 0.65 seconds
Started Jul 15 07:10:22 PM PDT 24
Finished Jul 15 07:11:03 PM PDT 24
Peak memory 206812 kb
Host smart-13a67ae2-13ce-4b8e-ac91-085b38e0802b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29780
47326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2978047326
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.319554293
Short name T2016
Test name
Test status
Simulation time 964176388 ps
CPU time 2.1 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206936 kb
Host smart-c7af45d8-ce09-4662-bd7d-b327af6379e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31955
4293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.319554293
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1639339920
Short name T559
Test name
Test status
Simulation time 175835262 ps
CPU time 1.81 seconds
Started Jul 15 07:10:24 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 207044 kb
Host smart-834ceaf2-37c4-4dd0-92f1-dfec697241cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16393
39920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1639339920
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3060911782
Short name T506
Test name
Test status
Simulation time 180329969 ps
CPU time 0.82 seconds
Started Jul 15 07:10:20 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206804 kb
Host smart-7c1654d5-a39e-40fc-8ac2-171c42cbbfc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
11782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3060911782
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1786116628
Short name T1354
Test name
Test status
Simulation time 144361620 ps
CPU time 0.75 seconds
Started Jul 15 07:10:24 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206804 kb
Host smart-adb17129-febc-47c2-945f-62fc27bcecf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17861
16628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1786116628
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.324433294
Short name T1080
Test name
Test status
Simulation time 218141083 ps
CPU time 0.86 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206788 kb
Host smart-82b8c514-1f12-4375-a3c1-54ac78bb00b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32443
3294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.324433294
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3254392323
Short name T2709
Test name
Test status
Simulation time 6596410699 ps
CPU time 46.07 seconds
Started Jul 15 07:10:19 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 207052 kb
Host smart-b82f07d9-e8eb-4d31-a696-0a0eeb6b693d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3254392323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3254392323
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.493365340
Short name T1970
Test name
Test status
Simulation time 4219718003 ps
CPU time 13.67 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:17 PM PDT 24
Peak memory 207000 kb
Host smart-f7e07b1a-eeb9-4c78-abb3-5b6693a7e923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49336
5340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.493365340
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.522949510
Short name T2225
Test name
Test status
Simulation time 184988824 ps
CPU time 0.86 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:04 PM PDT 24
Peak memory 206816 kb
Host smart-935744a5-da1b-4d94-aa63-450097003821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52294
9510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.522949510
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2645910755
Short name T1067
Test name
Test status
Simulation time 23305140667 ps
CPU time 26.65 seconds
Started Jul 15 07:10:23 PM PDT 24
Finished Jul 15 07:11:30 PM PDT 24
Peak memory 206888 kb
Host smart-3fe978c6-8ce4-481e-8fa3-68d86dad0f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26459
10755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2645910755
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3475028949
Short name T1963
Test name
Test status
Simulation time 3381276051 ps
CPU time 3.89 seconds
Started Jul 15 07:10:21 PM PDT 24
Finished Jul 15 07:11:07 PM PDT 24
Peak memory 206876 kb
Host smart-c83dc584-decf-4899-b570-9c8b7e6a28f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34750
28949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3475028949
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.522828487
Short name T1768
Test name
Test status
Simulation time 10601223939 ps
CPU time 79.84 seconds
Started Jul 15 07:10:27 PM PDT 24
Finished Jul 15 07:12:25 PM PDT 24
Peak memory 207036 kb
Host smart-545528d2-97e7-4943-a796-01f09c8b4e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52282
8487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.522828487
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2326312269
Short name T699
Test name
Test status
Simulation time 4853020670 ps
CPU time 36.67 seconds
Started Jul 15 07:10:24 PM PDT 24
Finished Jul 15 07:11:40 PM PDT 24
Peak memory 206980 kb
Host smart-40732d4c-154c-4619-8b29-a056caeedb02
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2326312269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2326312269
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.261898956
Short name T1378
Test name
Test status
Simulation time 247768499 ps
CPU time 0.92 seconds
Started Jul 15 07:10:27 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206808 kb
Host smart-d67f41a4-96b7-4f85-9b15-e4a3fa2eb695
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=261898956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.261898956
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2633292505
Short name T1366
Test name
Test status
Simulation time 195535370 ps
CPU time 0.87 seconds
Started Jul 15 07:10:25 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206796 kb
Host smart-4fb785bd-33e1-4230-b937-03b904837810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26332
92505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2633292505
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1767934613
Short name T1053
Test name
Test status
Simulation time 5951584361 ps
CPU time 43.73 seconds
Started Jul 15 07:10:25 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 207092 kb
Host smart-2fe2797c-2951-43ba-aae2-510772b52d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17679
34613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1767934613
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1881921182
Short name T1869
Test name
Test status
Simulation time 5277110853 ps
CPU time 50.94 seconds
Started Jul 15 07:10:29 PM PDT 24
Finished Jul 15 07:11:56 PM PDT 24
Peak memory 207024 kb
Host smart-57d73579-9eb0-48c7-b8dd-d4529f5882d9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1881921182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1881921182
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2899517164
Short name T715
Test name
Test status
Simulation time 204823406 ps
CPU time 0.81 seconds
Started Jul 15 07:10:27 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206824 kb
Host smart-d4b72c87-51c2-4d74-9db9-fc46f47df57c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2899517164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2899517164
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2532952247
Short name T2632
Test name
Test status
Simulation time 159048801 ps
CPU time 0.79 seconds
Started Jul 15 07:10:26 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206824 kb
Host smart-d0157157-413c-4477-9964-e18dc2b651fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
52247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2532952247
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.918753290
Short name T138
Test name
Test status
Simulation time 255291140 ps
CPU time 0.91 seconds
Started Jul 15 07:10:29 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206796 kb
Host smart-98570681-2287-4494-8fe6-1bf2ebc91155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91875
3290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.918753290
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2232190225
Short name T1512
Test name
Test status
Simulation time 152138070 ps
CPU time 0.77 seconds
Started Jul 15 07:10:27 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206788 kb
Host smart-a11d6789-c3a8-48ed-a095-b3ea2f311afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22321
90225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2232190225
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3051030048
Short name T1640
Test name
Test status
Simulation time 192562989 ps
CPU time 0.83 seconds
Started Jul 15 07:10:29 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206768 kb
Host smart-a27e3904-9308-477f-af45-f198d6cbbc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30510
30048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3051030048
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.412527815
Short name T1023
Test name
Test status
Simulation time 245056711 ps
CPU time 0.88 seconds
Started Jul 15 07:10:27 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206840 kb
Host smart-4561fc80-5d60-43ce-b4b9-ce3c0499b568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41252
7815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.412527815
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.815634881
Short name T1828
Test name
Test status
Simulation time 156246435 ps
CPU time 0.79 seconds
Started Jul 15 07:10:29 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206768 kb
Host smart-4a79e107-7bb6-4083-badf-77db7a08b0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81563
4881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.815634881
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1685053500
Short name T2000
Test name
Test status
Simulation time 263921755 ps
CPU time 0.91 seconds
Started Jul 15 07:10:25 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206820 kb
Host smart-86dbd07c-65d7-44e7-abab-7598fec82cc2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1685053500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1685053500
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.288888960
Short name T1954
Test name
Test status
Simulation time 149754466 ps
CPU time 0.75 seconds
Started Jul 15 07:10:30 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206768 kb
Host smart-03c954dc-738b-4fd3-9b97-4ef3eb20613a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28888
8960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.288888960
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2345111151
Short name T1926
Test name
Test status
Simulation time 28831399 ps
CPU time 0.63 seconds
Started Jul 15 07:10:27 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206820 kb
Host smart-376b643f-c55b-4c8b-9cb7-815c41c4a641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
11151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2345111151
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1198229947
Short name T82
Test name
Test status
Simulation time 14992843648 ps
CPU time 36.54 seconds
Started Jul 15 07:10:28 PM PDT 24
Finished Jul 15 07:11:41 PM PDT 24
Peak memory 207020 kb
Host smart-83acb295-4443-42c6-93a5-e37680dd6eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11982
29947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1198229947
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.752485605
Short name T1634
Test name
Test status
Simulation time 145993157 ps
CPU time 0.76 seconds
Started Jul 15 07:10:30 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206792 kb
Host smart-92823ce0-b8ad-4548-b718-7ff7a15da76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75248
5605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.752485605
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.57314874
Short name T1385
Test name
Test status
Simulation time 213205170 ps
CPU time 0.84 seconds
Started Jul 15 07:10:26 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206812 kb
Host smart-5fc4422a-56bf-45ba-90d9-faccf8876836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57314
874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.57314874
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3938147124
Short name T1830
Test name
Test status
Simulation time 194704869 ps
CPU time 0.81 seconds
Started Jul 15 07:10:25 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206820 kb
Host smart-7e29376f-3172-4c1b-a9bb-2f8028b5d6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39381
47124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3938147124
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.4140606688
Short name T436
Test name
Test status
Simulation time 173171081 ps
CPU time 0.81 seconds
Started Jul 15 07:10:27 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206972 kb
Host smart-c7cdadd0-7e3a-4e0e-b0f6-27031c7300ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41406
06688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.4140606688
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2325831978
Short name T2494
Test name
Test status
Simulation time 141794808 ps
CPU time 0.75 seconds
Started Jul 15 07:10:26 PM PDT 24
Finished Jul 15 07:11:05 PM PDT 24
Peak memory 206816 kb
Host smart-1ba149c6-9ad7-47ba-94d7-3fcfcca9d05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23258
31978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2325831978
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1314245938
Short name T1907
Test name
Test status
Simulation time 152330548 ps
CPU time 0.76 seconds
Started Jul 15 07:10:32 PM PDT 24
Finished Jul 15 07:11:07 PM PDT 24
Peak memory 206820 kb
Host smart-06911768-b31a-43d2-8b33-a1780b2e75ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13142
45938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1314245938
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3062515995
Short name T1224
Test name
Test status
Simulation time 182549343 ps
CPU time 0.83 seconds
Started Jul 15 07:10:32 PM PDT 24
Finished Jul 15 07:11:07 PM PDT 24
Peak memory 206824 kb
Host smart-bddb6a37-d35f-4be4-8a09-b27fc28ad081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30625
15995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3062515995
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3031575120
Short name T866
Test name
Test status
Simulation time 247141874 ps
CPU time 1 seconds
Started Jul 15 07:10:33 PM PDT 24
Finished Jul 15 07:11:08 PM PDT 24
Peak memory 206832 kb
Host smart-362b5fa8-bc27-4f54-b2e7-eed297ef379c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30315
75120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3031575120
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.1138201176
Short name T552
Test name
Test status
Simulation time 5562364400 ps
CPU time 42.18 seconds
Started Jul 15 07:10:31 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206940 kb
Host smart-e2740f57-c4ed-4659-8fca-7344e879a2f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1138201176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.1138201176
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2037251292
Short name T1099
Test name
Test status
Simulation time 187943625 ps
CPU time 0.8 seconds
Started Jul 15 07:10:30 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206788 kb
Host smart-2a207ef7-e79a-42b9-b0db-3d01d934c2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20372
51292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2037251292
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.291186914
Short name T1086
Test name
Test status
Simulation time 169128182 ps
CPU time 0.77 seconds
Started Jul 15 07:10:33 PM PDT 24
Finished Jul 15 07:11:07 PM PDT 24
Peak memory 206784 kb
Host smart-13e59759-b8e3-4235-8e8b-b5bd6d6de0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29118
6914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.291186914
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3560218906
Short name T1198
Test name
Test status
Simulation time 821611962 ps
CPU time 1.81 seconds
Started Jul 15 07:10:31 PM PDT 24
Finished Jul 15 07:11:08 PM PDT 24
Peak memory 206980 kb
Host smart-3ddd9a86-adc6-4292-b81d-348fcf2abdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35602
18906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3560218906
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3806003944
Short name T2560
Test name
Test status
Simulation time 5693650183 ps
CPU time 159.47 seconds
Started Jul 15 07:10:31 PM PDT 24
Finished Jul 15 07:13:45 PM PDT 24
Peak memory 207016 kb
Host smart-43ea413d-e100-40a5-8c30-3aebd13d9410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38060
03944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3806003944
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.48157351
Short name T1844
Test name
Test status
Simulation time 53801463 ps
CPU time 0.66 seconds
Started Jul 15 07:10:52 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206828 kb
Host smart-0209b755-1f08-4791-b305-a69bb705e1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=48157351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.48157351
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1143103994
Short name T2190
Test name
Test status
Simulation time 3701642170 ps
CPU time 4.22 seconds
Started Jul 15 07:10:31 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 207036 kb
Host smart-c0f6cf51-82e8-44c5-8bbe-d7a028fb65b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1143103994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.1143103994
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2808939534
Short name T380
Test name
Test status
Simulation time 13338185882 ps
CPU time 16.53 seconds
Started Jul 15 07:10:33 PM PDT 24
Finished Jul 15 07:11:23 PM PDT 24
Peak memory 206772 kb
Host smart-3495cbb6-6b0e-416f-ad5f-dd0096f0d9bf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2808939534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2808939534
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.309134126
Short name T428
Test name
Test status
Simulation time 23308611975 ps
CPU time 24.62 seconds
Started Jul 15 07:10:33 PM PDT 24
Finished Jul 15 07:11:31 PM PDT 24
Peak memory 206860 kb
Host smart-3e9cf210-f28c-4f9e-921d-27659bd66a91
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=309134126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.309134126
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.338972931
Short name T2093
Test name
Test status
Simulation time 161484323 ps
CPU time 0.82 seconds
Started Jul 15 07:10:30 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206808 kb
Host smart-20caf31f-4415-4628-9f7f-2e9bcff3ea98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33897
2931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.338972931
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1822815099
Short name T1181
Test name
Test status
Simulation time 190715951 ps
CPU time 0.79 seconds
Started Jul 15 07:10:31 PM PDT 24
Finished Jul 15 07:11:06 PM PDT 24
Peak memory 206816 kb
Host smart-8b16abf5-4015-43de-adde-9cee3b2e9555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18228
15099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1822815099
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2585693441
Short name T2416
Test name
Test status
Simulation time 310110303 ps
CPU time 1.07 seconds
Started Jul 15 07:10:32 PM PDT 24
Finished Jul 15 07:11:07 PM PDT 24
Peak memory 206828 kb
Host smart-41594f65-0620-4103-8f37-532b570c7cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25856
93441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2585693441
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.992256461
Short name T2538
Test name
Test status
Simulation time 319591323 ps
CPU time 0.98 seconds
Started Jul 15 07:10:32 PM PDT 24
Finished Jul 15 07:11:08 PM PDT 24
Peak memory 206804 kb
Host smart-a6c2e5d8-7ddd-44b6-abf4-2a5bd38146fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99225
6461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.992256461
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.1811525366
Short name T815
Test name
Test status
Simulation time 23626693271 ps
CPU time 51.26 seconds
Started Jul 15 07:10:37 PM PDT 24
Finished Jul 15 07:11:59 PM PDT 24
Peak memory 206944 kb
Host smart-2a583bb8-1915-4d25-a143-915a0fe8aca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18115
25366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1811525366
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3968472366
Short name T2232
Test name
Test status
Simulation time 347326534 ps
CPU time 1.23 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206708 kb
Host smart-c9e29580-925a-4c2f-a97e-a9898cd75946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39684
72366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3968472366
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3957468541
Short name T1874
Test name
Test status
Simulation time 170786572 ps
CPU time 0.78 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206836 kb
Host smart-a1171ac6-7b05-44a1-9745-30e0a1af0af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39574
68541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3957468541
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1790492855
Short name T489
Test name
Test status
Simulation time 114912432 ps
CPU time 0.71 seconds
Started Jul 15 07:10:39 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206808 kb
Host smart-2429cedf-8bf9-4932-98f5-6af98e8c1e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17904
92855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1790492855
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1728952220
Short name T663
Test name
Test status
Simulation time 698247471 ps
CPU time 1.71 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206992 kb
Host smart-a915f516-a81d-47bc-93bf-8d223ba50da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
52220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1728952220
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.26657448
Short name T167
Test name
Test status
Simulation time 291900742 ps
CPU time 1.66 seconds
Started Jul 15 07:10:47 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206784 kb
Host smart-54fe6ba3-feb7-4c98-a354-4c8150356f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26657
448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.26657448
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3926787124
Short name T1539
Test name
Test status
Simulation time 203463671 ps
CPU time 0.91 seconds
Started Jul 15 07:10:37 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206796 kb
Host smart-be19b9da-69b9-4834-a486-92eaa3de5ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39267
87124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3926787124
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1483120600
Short name T2368
Test name
Test status
Simulation time 189706895 ps
CPU time 0.77 seconds
Started Jul 15 07:10:40 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206792 kb
Host smart-7b573671-d873-4d98-a13f-1e5126330680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14831
20600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1483120600
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.4160915067
Short name T1891
Test name
Test status
Simulation time 220647375 ps
CPU time 0.9 seconds
Started Jul 15 07:10:37 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206792 kb
Host smart-eb635b04-eefc-434b-85ba-ded72215aafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609
15067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.4160915067
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.392179453
Short name T2720
Test name
Test status
Simulation time 5089076217 ps
CPU time 49.09 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:11:57 PM PDT 24
Peak memory 207064 kb
Host smart-1637a2eb-c33b-4aaf-9d1e-5668c0f4fab1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=392179453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.392179453
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.336205463
Short name T1587
Test name
Test status
Simulation time 5777940753 ps
CPU time 46.01 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:11:54 PM PDT 24
Peak memory 207076 kb
Host smart-7eabd6dd-aacb-45bc-bcb7-f13fa5ad06d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33620
5463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.336205463
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2699800424
Short name T1995
Test name
Test status
Simulation time 231550283 ps
CPU time 0.91 seconds
Started Jul 15 07:10:39 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206808 kb
Host smart-ba8afe02-e331-455d-91f2-424597018fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26998
00424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2699800424
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1246747802
Short name T2476
Test name
Test status
Simulation time 23305976250 ps
CPU time 23.03 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:11:31 PM PDT 24
Peak memory 206876 kb
Host smart-3899916d-c027-49f6-8185-096f740f36ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
47802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1246747802
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1889749296
Short name T1360
Test name
Test status
Simulation time 3262218690 ps
CPU time 3.94 seconds
Started Jul 15 07:10:47 PM PDT 24
Finished Jul 15 07:11:14 PM PDT 24
Peak memory 206712 kb
Host smart-4deb4a30-b673-44f2-93ee-62e37364ade9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18897
49296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1889749296
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3135234174
Short name T2393
Test name
Test status
Simulation time 6291126149 ps
CPU time 58.88 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 207056 kb
Host smart-d44626bb-a307-4e54-8bf0-c8f20c6b55d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31352
34174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3135234174
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2904323291
Short name T586
Test name
Test status
Simulation time 7731532378 ps
CPU time 214.19 seconds
Started Jul 15 07:10:40 PM PDT 24
Finished Jul 15 07:14:43 PM PDT 24
Peak memory 206988 kb
Host smart-fa542ea4-c358-47e9-8878-c61f336e0735
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2904323291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2904323291
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.217944428
Short name T980
Test name
Test status
Simulation time 277861406 ps
CPU time 0.95 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206824 kb
Host smart-a824faa5-92bb-4d33-818d-e660d5d5e356
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=217944428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.217944428
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.4080668322
Short name T302
Test name
Test status
Simulation time 264009010 ps
CPU time 0.92 seconds
Started Jul 15 07:10:39 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206812 kb
Host smart-2d5beef1-c645-46f1-9644-0f6d2dffd488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40806
68322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.4080668322
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.28787442
Short name T1581
Test name
Test status
Simulation time 4806101448 ps
CPU time 132.77 seconds
Started Jul 15 07:10:47 PM PDT 24
Finished Jul 15 07:13:23 PM PDT 24
Peak memory 206892 kb
Host smart-4907dd83-290a-418f-afcc-271182d257ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28787
442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.28787442
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.4147325208
Short name T1436
Test name
Test status
Simulation time 5056681492 ps
CPU time 35.69 seconds
Started Jul 15 07:10:47 PM PDT 24
Finished Jul 15 07:11:46 PM PDT 24
Peak memory 206840 kb
Host smart-798fae4a-ed53-499d-a808-d502f0061c75
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4147325208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.4147325208
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3495316225
Short name T561
Test name
Test status
Simulation time 157672707 ps
CPU time 0.78 seconds
Started Jul 15 07:10:38 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206812 kb
Host smart-190ad6af-e6c7-4951-bd54-f9c32c11abda
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3495316225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3495316225
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3612171847
Short name T785
Test name
Test status
Simulation time 198466726 ps
CPU time 0.88 seconds
Started Jul 15 07:10:39 PM PDT 24
Finished Jul 15 07:11:09 PM PDT 24
Peak memory 206812 kb
Host smart-7e2402c6-889a-4e8e-b196-d03ca0b3f220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36121
71847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3612171847
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.186890183
Short name T109
Test name
Test status
Simulation time 186094360 ps
CPU time 0.82 seconds
Started Jul 15 07:10:45 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206836 kb
Host smart-5ce8aa58-c8f9-4673-842b-629e4e11be03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18689
0183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.186890183
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2054429972
Short name T2668
Test name
Test status
Simulation time 198644984 ps
CPU time 0.83 seconds
Started Jul 15 07:10:42 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206820 kb
Host smart-d670c4d8-bd7f-4a37-8d48-11c7b0a53c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544
29972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2054429972
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.661140310
Short name T1139
Test name
Test status
Simulation time 165996918 ps
CPU time 0.78 seconds
Started Jul 15 07:10:48 PM PDT 24
Finished Jul 15 07:11:11 PM PDT 24
Peak memory 206644 kb
Host smart-284d588c-1fb9-4340-be02-e550843e35e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66114
0310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.661140310
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3104745790
Short name T449
Test name
Test status
Simulation time 192158660 ps
CPU time 0.81 seconds
Started Jul 15 07:10:44 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206768 kb
Host smart-fc142bd0-5f21-4f6e-a65f-ae918d6c7fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31047
45790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3104745790
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3008722744
Short name T2282
Test name
Test status
Simulation time 156808432 ps
CPU time 0.77 seconds
Started Jul 15 07:10:44 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206808 kb
Host smart-8cc9ac92-071d-4da4-8ae7-25d4d2b46596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30087
22744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3008722744
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3700881312
Short name T972
Test name
Test status
Simulation time 242258068 ps
CPU time 0.89 seconds
Started Jul 15 07:10:48 PM PDT 24
Finished Jul 15 07:11:11 PM PDT 24
Peak memory 206648 kb
Host smart-30d89dd7-4b42-4a57-9002-9d85da383a79
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3700881312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3700881312
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2986108752
Short name T985
Test name
Test status
Simulation time 142377771 ps
CPU time 0.76 seconds
Started Jul 15 07:10:44 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206784 kb
Host smart-fca2d00c-5bc1-4e6f-8ea5-960aa8248cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29861
08752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2986108752
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2250671111
Short name T2131
Test name
Test status
Simulation time 94334235 ps
CPU time 0.73 seconds
Started Jul 15 07:10:44 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206756 kb
Host smart-f1138ae3-528e-40d6-a554-25a21d45b70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22506
71111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2250671111
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2942012292
Short name T1565
Test name
Test status
Simulation time 6160934710 ps
CPU time 14.21 seconds
Started Jul 15 07:10:45 PM PDT 24
Finished Jul 15 07:11:24 PM PDT 24
Peak memory 207032 kb
Host smart-a24dd542-1632-4935-8474-b7f72bdd9648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29420
12292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2942012292
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2561109479
Short name T2475
Test name
Test status
Simulation time 210738674 ps
CPU time 0.86 seconds
Started Jul 15 07:10:44 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206704 kb
Host smart-b3d30422-f156-4958-a396-1aa178b8e792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25611
09479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2561109479
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3221143594
Short name T200
Test name
Test status
Simulation time 171505122 ps
CPU time 0.85 seconds
Started Jul 15 07:10:44 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206808 kb
Host smart-7156855b-cddb-4ba0-b6c2-009552bda93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32211
43594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3221143594
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.343846006
Short name T2510
Test name
Test status
Simulation time 232389196 ps
CPU time 0.9 seconds
Started Jul 15 07:10:45 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206972 kb
Host smart-a55775b1-8900-4d90-8132-0ac1cb3d0f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34384
6006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.343846006
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.676519386
Short name T1707
Test name
Test status
Simulation time 199875320 ps
CPU time 0.85 seconds
Started Jul 15 07:10:49 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206748 kb
Host smart-1f71700f-17e4-4b3c-94ff-0547eba77614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67651
9386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.676519386
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.4074848832
Short name T759
Test name
Test status
Simulation time 201309065 ps
CPU time 0.84 seconds
Started Jul 15 07:10:45 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206796 kb
Host smart-4c875da0-eee4-4f06-98cd-0bfafd3f1273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40748
48832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.4074848832
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1720347965
Short name T1741
Test name
Test status
Simulation time 152544175 ps
CPU time 0.74 seconds
Started Jul 15 07:10:45 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206808 kb
Host smart-9b244759-c896-4171-bfcf-022968036e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17203
47965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1720347965
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.894472146
Short name T2737
Test name
Test status
Simulation time 151507086 ps
CPU time 0.76 seconds
Started Jul 15 07:10:43 PM PDT 24
Finished Jul 15 07:11:10 PM PDT 24
Peak memory 206788 kb
Host smart-bb89c463-4849-4fd6-b837-55b9c8a5cd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89447
2146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.894472146
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1509352804
Short name T1730
Test name
Test status
Simulation time 224599226 ps
CPU time 0.96 seconds
Started Jul 15 07:10:45 PM PDT 24
Finished Jul 15 07:11:11 PM PDT 24
Peak memory 206832 kb
Host smart-94f7d372-6262-498f-a087-c36538cdff8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
52804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1509352804
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.4245313305
Short name T731
Test name
Test status
Simulation time 4194873176 ps
CPU time 111.16 seconds
Started Jul 15 07:10:52 PM PDT 24
Finished Jul 15 07:13:02 PM PDT 24
Peak memory 206948 kb
Host smart-15c70772-f45f-482d-aa23-16cb75faf93b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4245313305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.4245313305
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2849607350
Short name T1088
Test name
Test status
Simulation time 185492967 ps
CPU time 0.81 seconds
Started Jul 15 07:10:51 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206816 kb
Host smart-69dab135-3838-4205-bcc7-d0a62b14e3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28496
07350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2849607350
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2902492848
Short name T1416
Test name
Test status
Simulation time 185707578 ps
CPU time 0.81 seconds
Started Jul 15 07:10:50 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206752 kb
Host smart-e1ea27ef-bac2-4a49-977e-a92520288a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29024
92848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2902492848
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.905281897
Short name T1584
Test name
Test status
Simulation time 310279962 ps
CPU time 1.01 seconds
Started Jul 15 07:10:54 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206764 kb
Host smart-429268a6-daf8-46e6-a065-6b331adb0626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90528
1897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.905281897
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.573018202
Short name T2124
Test name
Test status
Simulation time 6665876447 ps
CPU time 64.05 seconds
Started Jul 15 07:10:52 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 206896 kb
Host smart-28bead79-a09b-4b83-bac3-b7f83f3a298c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57301
8202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.573018202
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2903730171
Short name T943
Test name
Test status
Simulation time 56522331 ps
CPU time 0.73 seconds
Started Jul 15 07:11:37 PM PDT 24
Finished Jul 15 07:11:39 PM PDT 24
Peak memory 206844 kb
Host smart-3ff52407-d563-422b-8c6a-acf59c46e158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2903730171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2903730171
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1051173050
Short name T1592
Test name
Test status
Simulation time 4339290139 ps
CPU time 5.13 seconds
Started Jul 15 07:10:51 PM PDT 24
Finished Jul 15 07:11:16 PM PDT 24
Peak memory 206848 kb
Host smart-f727c62a-b0f3-4465-ac10-dc64cb58aa30
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1051173050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1051173050
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3507664644
Short name T504
Test name
Test status
Simulation time 13377563754 ps
CPU time 14.51 seconds
Started Jul 15 07:10:49 PM PDT 24
Finished Jul 15 07:11:25 PM PDT 24
Peak memory 206872 kb
Host smart-47285c2b-08d5-4365-b5b1-a83e3f68a57a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3507664644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3507664644
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.254019622
Short name T742
Test name
Test status
Simulation time 23352165888 ps
CPU time 26.27 seconds
Started Jul 15 07:10:50 PM PDT 24
Finished Jul 15 07:11:37 PM PDT 24
Peak memory 207024 kb
Host smart-e96bd6d1-8203-406a-90ab-05b4cf6eac77
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=254019622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.254019622
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1759717265
Short name T2202
Test name
Test status
Simulation time 149175596 ps
CPU time 0.77 seconds
Started Jul 15 07:10:52 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206760 kb
Host smart-ebaa746d-70a4-408e-8cd7-1ddb31950dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17597
17265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1759717265
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4059380772
Short name T1935
Test name
Test status
Simulation time 198663617 ps
CPU time 0.8 seconds
Started Jul 15 07:10:52 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206776 kb
Host smart-21216c38-3132-4726-8075-9b4242b51103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40593
80772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4059380772
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1014404278
Short name T2373
Test name
Test status
Simulation time 274895247 ps
CPU time 1.08 seconds
Started Jul 15 07:10:54 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206728 kb
Host smart-9dfb545b-9055-49a4-bac4-9cdcb12c7acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
04278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1014404278
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3700431751
Short name T503
Test name
Test status
Simulation time 1375908007 ps
CPU time 3 seconds
Started Jul 15 07:10:49 PM PDT 24
Finished Jul 15 07:11:14 PM PDT 24
Peak memory 207044 kb
Host smart-d35fd87a-1e52-4927-8f24-5eab94718605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37004
31751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3700431751
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.3799958537
Short name T164
Test name
Test status
Simulation time 18803346883 ps
CPU time 32.89 seconds
Started Jul 15 07:10:49 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 207088 kb
Host smart-f886a49c-0a96-4e1c-80b8-d9725e4f3451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37999
58537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3799958537
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.23947390
Short name T682
Test name
Test status
Simulation time 431545385 ps
CPU time 1.31 seconds
Started Jul 15 07:10:52 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206972 kb
Host smart-576c623f-1df8-4253-8053-892725dc81d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23947
390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.23947390
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.2809383994
Short name T35
Test name
Test status
Simulation time 163754440 ps
CPU time 0.79 seconds
Started Jul 15 07:10:51 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206804 kb
Host smart-027e943c-9079-4f9a-a1cc-4283b3e306ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28093
83994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2809383994
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1202239296
Short name T1351
Test name
Test status
Simulation time 38516038 ps
CPU time 0.66 seconds
Started Jul 15 07:10:50 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206808 kb
Host smart-f04eba77-b1c2-4121-b409-8c199f5eec8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12022
39296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1202239296
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3446400317
Short name T1061
Test name
Test status
Simulation time 896552771 ps
CPU time 2.08 seconds
Started Jul 15 07:10:50 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206980 kb
Host smart-1b7380db-d4cb-4d6f-92af-e24b52f3bd6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34464
00317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3446400317
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.4014729447
Short name T1316
Test name
Test status
Simulation time 242229918 ps
CPU time 1.95 seconds
Started Jul 15 07:10:48 PM PDT 24
Finished Jul 15 07:11:12 PM PDT 24
Peak memory 206964 kb
Host smart-478a841e-c141-4cac-85cf-d4058b7f7b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40147
29447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.4014729447
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1474401562
Short name T2380
Test name
Test status
Simulation time 198942415 ps
CPU time 0.9 seconds
Started Jul 15 07:10:58 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206760 kb
Host smart-1d42c5a4-f080-455f-8014-f28400482cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
01562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1474401562
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2505949540
Short name T1157
Test name
Test status
Simulation time 152926642 ps
CPU time 0.77 seconds
Started Jul 15 07:10:57 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206828 kb
Host smart-e0a6750c-a0e9-4887-b6ac-76c9dc10b42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25059
49540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2505949540
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2886240344
Short name T516
Test name
Test status
Simulation time 259172374 ps
CPU time 0.89 seconds
Started Jul 15 07:10:57 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206836 kb
Host smart-6a59bf3b-79d3-4064-b0d0-977ee5cc7ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28862
40344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2886240344
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.965125160
Short name T935
Test name
Test status
Simulation time 6683729743 ps
CPU time 51.19 seconds
Started Jul 15 07:10:57 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 207068 kb
Host smart-9a474fe6-0baf-4331-a255-57249eca1075
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=965125160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.965125160
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.3874538402
Short name T1265
Test name
Test status
Simulation time 6181599574 ps
CPU time 53.99 seconds
Started Jul 15 07:10:58 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 207084 kb
Host smart-7d9397ac-298b-4dc3-905d-9abbedc2538a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38745
38402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.3874538402
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1683539961
Short name T1810
Test name
Test status
Simulation time 209397923 ps
CPU time 0.95 seconds
Started Jul 15 07:10:58 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206784 kb
Host smart-293582c2-86d9-4eb5-9eaf-9636eab95099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16835
39961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1683539961
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2589473545
Short name T2161
Test name
Test status
Simulation time 23401023832 ps
CPU time 23.86 seconds
Started Jul 15 07:10:57 PM PDT 24
Finished Jul 15 07:11:36 PM PDT 24
Peak memory 206872 kb
Host smart-e19db2c0-b939-4577-9503-67d96f72c434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25894
73545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2589473545
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1122815587
Short name T2223
Test name
Test status
Simulation time 3296483057 ps
CPU time 3.99 seconds
Started Jul 15 07:10:57 PM PDT 24
Finished Jul 15 07:11:16 PM PDT 24
Peak memory 206916 kb
Host smart-d11a8c9b-ca12-42a2-a0af-78aa193e7744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11228
15587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1122815587
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2229691530
Short name T398
Test name
Test status
Simulation time 7332321170 ps
CPU time 52.37 seconds
Started Jul 15 07:10:59 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 207032 kb
Host smart-86ee4e8e-38fa-4203-a7c5-13183e7a2aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22296
91530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2229691530
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3427084641
Short name T1479
Test name
Test status
Simulation time 4642098139 ps
CPU time 33.99 seconds
Started Jul 15 07:11:00 PM PDT 24
Finished Jul 15 07:11:47 PM PDT 24
Peak memory 207096 kb
Host smart-ef49c658-d5f6-47f2-9344-ebe8f5cbb8a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3427084641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3427084641
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3855114369
Short name T644
Test name
Test status
Simulation time 293683616 ps
CPU time 0.98 seconds
Started Jul 15 07:10:59 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206812 kb
Host smart-b83c2056-33c0-42e0-be12-ed8340c446e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3855114369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3855114369
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.917407287
Short name T417
Test name
Test status
Simulation time 189601610 ps
CPU time 0.83 seconds
Started Jul 15 07:10:57 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206808 kb
Host smart-f50e9109-5e83-416a-969a-ee7f3aaed7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91740
7287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.917407287
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.848894415
Short name T2359
Test name
Test status
Simulation time 3715863052 ps
CPU time 105.48 seconds
Started Jul 15 07:10:58 PM PDT 24
Finished Jul 15 07:12:58 PM PDT 24
Peak memory 207012 kb
Host smart-f636a33e-eedc-4435-8a12-beb170274b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84889
4415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.848894415
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3087909135
Short name T1380
Test name
Test status
Simulation time 3877223578 ps
CPU time 104.17 seconds
Started Jul 15 07:10:59 PM PDT 24
Finished Jul 15 07:12:56 PM PDT 24
Peak memory 206976 kb
Host smart-cdae023b-f55c-4b58-9543-69685bd5c240
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3087909135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3087909135
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.3851031583
Short name T421
Test name
Test status
Simulation time 166486173 ps
CPU time 0.79 seconds
Started Jul 15 07:10:57 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206828 kb
Host smart-69368e25-4e1b-4fc7-97c5-4e264946367e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3851031583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.3851031583
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2381392657
Short name T1710
Test name
Test status
Simulation time 199187084 ps
CPU time 0.89 seconds
Started Jul 15 07:11:01 PM PDT 24
Finished Jul 15 07:11:14 PM PDT 24
Peak memory 206840 kb
Host smart-1cfd4dc8-b14d-403b-8509-1bae45637646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23813
92657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2381392657
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3031725858
Short name T125
Test name
Test status
Simulation time 208894947 ps
CPU time 0.86 seconds
Started Jul 15 07:10:59 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206784 kb
Host smart-8e578fed-0d59-4202-b97e-077074704a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30317
25858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3031725858
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.4164250153
Short name T1251
Test name
Test status
Simulation time 195965659 ps
CPU time 0.81 seconds
Started Jul 15 07:11:00 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206840 kb
Host smart-c678f46c-9b1d-48b7-b8a9-b9a8857c3f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41642
50153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.4164250153
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3773248963
Short name T756
Test name
Test status
Simulation time 177457141 ps
CPU time 0.78 seconds
Started Jul 15 07:11:00 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206812 kb
Host smart-0d476528-708b-4411-9856-805f9cbca70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37732
48963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3773248963
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2405314416
Short name T1329
Test name
Test status
Simulation time 192593738 ps
CPU time 0.8 seconds
Started Jul 15 07:10:58 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206808 kb
Host smart-e3235038-c405-42d2-865c-be3dbe949c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24053
14416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2405314416
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2112428400
Short name T675
Test name
Test status
Simulation time 157174695 ps
CPU time 0.8 seconds
Started Jul 15 07:10:57 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206832 kb
Host smart-be56544c-58d1-4266-b273-44108fa8ec48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21124
28400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2112428400
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1865523668
Short name T1493
Test name
Test status
Simulation time 263292789 ps
CPU time 0.93 seconds
Started Jul 15 07:10:58 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206820 kb
Host smart-3bb92657-7691-4d2e-a4af-672d477cb2e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1865523668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1865523668
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.676986316
Short name T2263
Test name
Test status
Simulation time 146516304 ps
CPU time 0.78 seconds
Started Jul 15 07:10:59 PM PDT 24
Finished Jul 15 07:11:13 PM PDT 24
Peak memory 206788 kb
Host smart-b66f2113-d874-4f6d-ba3f-303f11d8acbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67698
6316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.676986316
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1541593328
Short name T2605
Test name
Test status
Simulation time 44445216 ps
CPU time 0.7 seconds
Started Jul 15 07:11:33 PM PDT 24
Finished Jul 15 07:11:35 PM PDT 24
Peak memory 206800 kb
Host smart-0b113a7a-b2a2-4be5-980c-8e30a3d59e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15415
93328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1541593328
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2831517516
Short name T1434
Test name
Test status
Simulation time 15126968420 ps
CPU time 32.77 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 207064 kb
Host smart-5c32cb87-fbaa-44e8-a7c9-d17a87200c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28315
17516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2831517516
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1562659944
Short name T2438
Test name
Test status
Simulation time 220527965 ps
CPU time 0.89 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:11:37 PM PDT 24
Peak memory 206812 kb
Host smart-956141f7-d4b6-4be6-a8fd-c9530a78a45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15626
59944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1562659944
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3771403793
Short name T2474
Test name
Test status
Simulation time 204562819 ps
CPU time 0.9 seconds
Started Jul 15 07:11:37 PM PDT 24
Finished Jul 15 07:11:40 PM PDT 24
Peak memory 206844 kb
Host smart-314fb3c5-8487-4b78-b9cc-edbd90231be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37714
03793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3771403793
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2087797783
Short name T999
Test name
Test status
Simulation time 202387655 ps
CPU time 0.88 seconds
Started Jul 15 07:11:37 PM PDT 24
Finished Jul 15 07:11:40 PM PDT 24
Peak memory 206840 kb
Host smart-60ec1b1f-22c4-4f4d-a745-40ec16da9015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877
97783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2087797783
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2153741460
Short name T575
Test name
Test status
Simulation time 162966193 ps
CPU time 0.82 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:11:37 PM PDT 24
Peak memory 206708 kb
Host smart-bff6276f-5306-4bf2-8215-5be587ae3ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21537
41460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2153741460
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.243448374
Short name T751
Test name
Test status
Simulation time 208474593 ps
CPU time 0.88 seconds
Started Jul 15 07:11:36 PM PDT 24
Finished Jul 15 07:11:39 PM PDT 24
Peak memory 206796 kb
Host smart-2e00bab9-3feb-40e3-a77c-310a3995af33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344
8374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.243448374
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2765874084
Short name T993
Test name
Test status
Simulation time 180678649 ps
CPU time 0.78 seconds
Started Jul 15 07:11:36 PM PDT 24
Finished Jul 15 07:11:38 PM PDT 24
Peak memory 206784 kb
Host smart-6d2306d3-1a0b-44ad-8504-46df56d34765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
74084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2765874084
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3534624601
Short name T2323
Test name
Test status
Simulation time 150806604 ps
CPU time 0.79 seconds
Started Jul 15 07:11:35 PM PDT 24
Finished Jul 15 07:11:38 PM PDT 24
Peak memory 206792 kb
Host smart-9fbe716d-309b-4f85-b320-ef6bc45f4462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35346
24601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3534624601
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1237313678
Short name T2464
Test name
Test status
Simulation time 179248897 ps
CPU time 0.85 seconds
Started Jul 15 07:11:32 PM PDT 24
Finished Jul 15 07:11:34 PM PDT 24
Peak memory 206808 kb
Host smart-715e3d47-a387-4680-955b-46897b026fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12373
13678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1237313678
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2996587149
Short name T144
Test name
Test status
Simulation time 5855572814 ps
CPU time 40.92 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 207044 kb
Host smart-c57283c1-712d-46d4-95ca-0797d24762ea
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2996587149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2996587149
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1248662223
Short name T353
Test name
Test status
Simulation time 163931296 ps
CPU time 0.83 seconds
Started Jul 15 07:11:37 PM PDT 24
Finished Jul 15 07:11:40 PM PDT 24
Peak memory 206812 kb
Host smart-cd2a2bf8-48c3-420e-bbbd-d5167bc7d49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12486
62223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1248662223
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.758534301
Short name T1532
Test name
Test status
Simulation time 148963396 ps
CPU time 0.81 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:11:36 PM PDT 24
Peak memory 206788 kb
Host smart-cc356e96-e715-444f-aaf8-0d80767ce480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75853
4301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.758534301
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2758049503
Short name T518
Test name
Test status
Simulation time 495370620 ps
CPU time 1.28 seconds
Started Jul 15 07:11:35 PM PDT 24
Finished Jul 15 07:11:38 PM PDT 24
Peak memory 206812 kb
Host smart-7e389d9c-60b2-497e-a96d-8eae717509c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
49503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2758049503
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3546747253
Short name T1488
Test name
Test status
Simulation time 4143497971 ps
CPU time 29.76 seconds
Started Jul 15 07:11:35 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 207016 kb
Host smart-365ee1ea-11f0-4bc6-b354-3ec820a97f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35467
47253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3546747253
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.574493618
Short name T2660
Test name
Test status
Simulation time 49129982 ps
CPU time 0.7 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 206832 kb
Host smart-265e08f1-b5ad-406c-8286-03003d70a30a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=574493618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.574493618
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3007637889
Short name T475
Test name
Test status
Simulation time 4000090693 ps
CPU time 4.78 seconds
Started Jul 15 07:11:38 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 207088 kb
Host smart-55383f83-61b2-4ec8-8c26-bb5ce0f0f457
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3007637889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3007637889
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2604991513
Short name T1190
Test name
Test status
Simulation time 13326396237 ps
CPU time 13.08 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 206832 kb
Host smart-670389e3-6ae2-4f85-909e-31b8992d722c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2604991513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2604991513
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1437424327
Short name T846
Test name
Test status
Simulation time 23324151135 ps
CPU time 23.44 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:11:59 PM PDT 24
Peak memory 206828 kb
Host smart-9495e453-b856-4720-9690-5efc3ff7baf1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1437424327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1437424327
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.507999983
Short name T453
Test name
Test status
Simulation time 172708403 ps
CPU time 0.81 seconds
Started Jul 15 07:11:37 PM PDT 24
Finished Jul 15 07:11:40 PM PDT 24
Peak memory 206824 kb
Host smart-2eeb9c63-3e27-4609-b5a3-11b97bb5a8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50799
9983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.507999983
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.3820531289
Short name T2266
Test name
Test status
Simulation time 145450620 ps
CPU time 0.79 seconds
Started Jul 15 07:11:35 PM PDT 24
Finished Jul 15 07:11:38 PM PDT 24
Peak memory 206792 kb
Host smart-62a36178-a874-494f-8ceb-815829f646d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38205
31289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3820531289
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1969567630
Short name T1745
Test name
Test status
Simulation time 368125748 ps
CPU time 1.28 seconds
Started Jul 15 07:11:33 PM PDT 24
Finished Jul 15 07:11:35 PM PDT 24
Peak memory 206740 kb
Host smart-300faeba-a3ae-4ea2-9bff-1cca64e834eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19695
67630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1969567630
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3137671431
Short name T1801
Test name
Test status
Simulation time 568053400 ps
CPU time 1.51 seconds
Started Jul 15 07:11:35 PM PDT 24
Finished Jul 15 07:11:38 PM PDT 24
Peak memory 206776 kb
Host smart-13ec434f-2dd8-4252-8182-8014cb8c0fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31376
71431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3137671431
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2386460076
Short name T929
Test name
Test status
Simulation time 10222603186 ps
CPU time 20.54 seconds
Started Jul 15 07:11:37 PM PDT 24
Finished Jul 15 07:11:59 PM PDT 24
Peak memory 207080 kb
Host smart-41b6f69f-2842-4dac-9393-fe01812b8245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23864
60076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2386460076
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.2773475913
Short name T1216
Test name
Test status
Simulation time 420337027 ps
CPU time 1.33 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:11:37 PM PDT 24
Peak memory 206840 kb
Host smart-753c6b0d-32f5-4d8d-bb25-eab1521fa928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27734
75913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.2773475913
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.706168606
Short name T2173
Test name
Test status
Simulation time 135832076 ps
CPU time 0.78 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:11:36 PM PDT 24
Peak memory 206836 kb
Host smart-fda9b152-f41b-4a38-ada7-07de57fc0b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70616
8606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.706168606
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3286673099
Short name T1298
Test name
Test status
Simulation time 47153245 ps
CPU time 0.66 seconds
Started Jul 15 07:11:35 PM PDT 24
Finished Jul 15 07:11:37 PM PDT 24
Peak memory 206772 kb
Host smart-3c377ed6-19af-49bc-9cdc-6ac6bf51cba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32866
73099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3286673099
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2085763820
Short name T767
Test name
Test status
Simulation time 886920992 ps
CPU time 2 seconds
Started Jul 15 07:11:34 PM PDT 24
Finished Jul 15 07:11:37 PM PDT 24
Peak memory 206996 kb
Host smart-cca53e76-be7d-4096-94b0-648774c1adc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20857
63820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2085763820
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.4270350900
Short name T693
Test name
Test status
Simulation time 258302219 ps
CPU time 1.38 seconds
Started Jul 15 07:11:36 PM PDT 24
Finished Jul 15 07:11:39 PM PDT 24
Peak memory 206908 kb
Host smart-c680c969-b1c3-4a10-b685-443b03c40c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42703
50900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4270350900
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2505327895
Short name T784
Test name
Test status
Simulation time 240357788 ps
CPU time 0.91 seconds
Started Jul 15 07:11:33 PM PDT 24
Finished Jul 15 07:11:35 PM PDT 24
Peak memory 206820 kb
Host smart-e4cd4a41-a82f-46ea-a324-3b699b05df2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25053
27895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2505327895
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2752139855
Short name T313
Test name
Test status
Simulation time 201684921 ps
CPU time 0.8 seconds
Started Jul 15 07:11:39 PM PDT 24
Finished Jul 15 07:11:42 PM PDT 24
Peak memory 206760 kb
Host smart-5681a288-fdc9-4e58-908f-6e2c9a9f4e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27521
39855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2752139855
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.928906197
Short name T2001
Test name
Test status
Simulation time 213703011 ps
CPU time 0.95 seconds
Started Jul 15 07:11:39 PM PDT 24
Finished Jul 15 07:11:41 PM PDT 24
Peak memory 206780 kb
Host smart-a58e39e0-2ffc-47b7-be95-9904584830b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92890
6197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.928906197
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.64952467
Short name T2472
Test name
Test status
Simulation time 5364622995 ps
CPU time 41.03 seconds
Started Jul 15 07:11:36 PM PDT 24
Finished Jul 15 07:12:19 PM PDT 24
Peak memory 207036 kb
Host smart-f2c73d8f-c483-4d34-bcb0-d8e8b5b1953f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64952
467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.64952467
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.45689538
Short name T1422
Test name
Test status
Simulation time 180497930 ps
CPU time 0.83 seconds
Started Jul 15 07:11:36 PM PDT 24
Finished Jul 15 07:11:39 PM PDT 24
Peak memory 206792 kb
Host smart-ed8cd45b-7c9b-4322-b5fc-3f4303136169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45689
538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.45689538
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.960252347
Short name T173
Test name
Test status
Simulation time 23267873334 ps
CPU time 26.22 seconds
Started Jul 15 07:11:40 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 206880 kb
Host smart-4110ffe2-68d8-480c-9420-bb220a4e5c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96025
2347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.960252347
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1346689449
Short name T219
Test name
Test status
Simulation time 3342481083 ps
CPU time 4.67 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206868 kb
Host smart-7d78e158-a11f-452d-8425-e3314bc6befd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13466
89449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1346689449
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1691188415
Short name T215
Test name
Test status
Simulation time 12575380458 ps
CPU time 119.63 seconds
Started Jul 15 07:11:40 PM PDT 24
Finished Jul 15 07:13:41 PM PDT 24
Peak memory 207092 kb
Host smart-705eb177-48f5-484b-b3e2-4446665b40f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16911
88415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1691188415
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.4253850769
Short name T1682
Test name
Test status
Simulation time 3788692613 ps
CPU time 105.76 seconds
Started Jul 15 07:11:36 PM PDT 24
Finished Jul 15 07:13:23 PM PDT 24
Peak memory 207012 kb
Host smart-9820c13f-fd97-4759-aebc-a00616704d06
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4253850769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.4253850769
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2062956906
Short name T1435
Test name
Test status
Simulation time 242806281 ps
CPU time 0.92 seconds
Started Jul 15 07:11:40 PM PDT 24
Finished Jul 15 07:11:42 PM PDT 24
Peak memory 206832 kb
Host smart-d51fdde6-af85-4660-9a36-a2e7441c6700
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2062956906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2062956906
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.741112266
Short name T1027
Test name
Test status
Simulation time 200068768 ps
CPU time 0.87 seconds
Started Jul 15 07:11:38 PM PDT 24
Finished Jul 15 07:11:40 PM PDT 24
Peak memory 206824 kb
Host smart-97bff6f1-1aee-43e4-8eee-bcc8ffc1cda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74111
2266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.741112266
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1576184359
Short name T662
Test name
Test status
Simulation time 5077759019 ps
CPU time 35.53 seconds
Started Jul 15 07:11:25 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 207080 kb
Host smart-a861f53d-cf46-49f2-8032-807fa6a79163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15761
84359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1576184359
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3750865887
Short name T933
Test name
Test status
Simulation time 4644893452 ps
CPU time 122.12 seconds
Started Jul 15 07:11:40 PM PDT 24
Finished Jul 15 07:13:44 PM PDT 24
Peak memory 206968 kb
Host smart-af633df5-2f06-4213-a935-f05aa037ed4f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3750865887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3750865887
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1424565980
Short name T1639
Test name
Test status
Simulation time 155574988 ps
CPU time 0.8 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:43 PM PDT 24
Peak memory 206804 kb
Host smart-a6b049d1-0847-4553-ab1c-50264815de41
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1424565980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1424565980
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1707639227
Short name T630
Test name
Test status
Simulation time 141313173 ps
CPU time 0.76 seconds
Started Jul 15 07:11:36 PM PDT 24
Finished Jul 15 07:11:39 PM PDT 24
Peak memory 206796 kb
Host smart-bd315a9d-ddec-4ba7-9647-c32c4a03fd91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17076
39227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1707639227
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2703979901
Short name T127
Test name
Test status
Simulation time 207991666 ps
CPU time 0.82 seconds
Started Jul 15 07:11:39 PM PDT 24
Finished Jul 15 07:11:42 PM PDT 24
Peak memory 206800 kb
Host smart-6fffcd00-4976-4bc9-8b17-9e84a65a8717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27039
79901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2703979901
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.819450813
Short name T92
Test name
Test status
Simulation time 175527800 ps
CPU time 0.82 seconds
Started Jul 15 07:11:38 PM PDT 24
Finished Jul 15 07:11:40 PM PDT 24
Peak memory 206824 kb
Host smart-c98559cf-dfe4-4861-bb83-9733e3e88da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81945
0813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.819450813
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3573575959
Short name T591
Test name
Test status
Simulation time 174804031 ps
CPU time 0.82 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 206812 kb
Host smart-0fe92da5-c410-447d-9191-48283c84e9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35735
75959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3573575959
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.121383924
Short name T808
Test name
Test status
Simulation time 161143069 ps
CPU time 0.81 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 206784 kb
Host smart-242f293d-61f4-47b2-b2f3-c22d3b1da0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12138
3924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.121383924
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1972445842
Short name T789
Test name
Test status
Simulation time 191913398 ps
CPU time 0.79 seconds
Started Jul 15 07:11:39 PM PDT 24
Finished Jul 15 07:11:41 PM PDT 24
Peak memory 206792 kb
Host smart-c6211599-3c1d-48a2-9603-56c7214c2135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19724
45842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1972445842
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.4199429090
Short name T2109
Test name
Test status
Simulation time 208887060 ps
CPU time 0.93 seconds
Started Jul 15 07:11:39 PM PDT 24
Finished Jul 15 07:11:41 PM PDT 24
Peak memory 206836 kb
Host smart-509142b2-c7d0-40ff-afab-71688578705b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4199429090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.4199429090
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3701976789
Short name T1806
Test name
Test status
Simulation time 144870274 ps
CPU time 0.79 seconds
Started Jul 15 07:11:38 PM PDT 24
Finished Jul 15 07:11:41 PM PDT 24
Peak memory 206788 kb
Host smart-69387729-8d3a-4256-af3d-f343004f7535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
76789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3701976789
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3720890609
Short name T1557
Test name
Test status
Simulation time 42940021 ps
CPU time 0.68 seconds
Started Jul 15 07:11:40 PM PDT 24
Finished Jul 15 07:11:42 PM PDT 24
Peak memory 206752 kb
Host smart-cff05cc1-9c56-46f3-9a86-39d9a7f4049e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37208
90609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3720890609
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.235989663
Short name T1001
Test name
Test status
Simulation time 19291862008 ps
CPU time 41.51 seconds
Started Jul 15 07:11:40 PM PDT 24
Finished Jul 15 07:12:23 PM PDT 24
Peak memory 207060 kb
Host smart-17e5d456-0af1-4a11-886e-aa933e9c7e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23598
9663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.235989663
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3730090390
Short name T2713
Test name
Test status
Simulation time 148503333 ps
CPU time 0.76 seconds
Started Jul 15 07:11:42 PM PDT 24
Finished Jul 15 07:11:45 PM PDT 24
Peak memory 206804 kb
Host smart-20fbbb35-dc53-4e5b-923e-74781af93cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37300
90390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3730090390
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1237188357
Short name T799
Test name
Test status
Simulation time 221809736 ps
CPU time 0.85 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:47 PM PDT 24
Peak memory 206824 kb
Host smart-34417c9d-20c4-41d3-a2d3-f06db5fe3fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12371
88357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1237188357
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1634819942
Short name T366
Test name
Test status
Simulation time 228371123 ps
CPU time 0.89 seconds
Started Jul 15 07:11:44 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 206812 kb
Host smart-162f91e4-4024-4cb9-9b47-237723fede2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16348
19942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1634819942
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2864040474
Short name T686
Test name
Test status
Simulation time 160917647 ps
CPU time 0.82 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 206808 kb
Host smart-8ae14886-e4d0-47ff-96ba-b3effc85e73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28640
40474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2864040474
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2354606794
Short name T1761
Test name
Test status
Simulation time 141852465 ps
CPU time 0.73 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:43 PM PDT 24
Peak memory 206800 kb
Host smart-3b32fcd8-4cac-46ea-91ed-957816f4b9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23546
06794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2354606794
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2229111957
Short name T1968
Test name
Test status
Simulation time 172353549 ps
CPU time 0.81 seconds
Started Jul 15 07:11:38 PM PDT 24
Finished Jul 15 07:11:41 PM PDT 24
Peak memory 206820 kb
Host smart-127d0fd6-c0f7-4b00-9311-9b88422a41d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22291
11957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2229111957
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2992310166
Short name T2313
Test name
Test status
Simulation time 161973441 ps
CPU time 0.76 seconds
Started Jul 15 07:11:41 PM PDT 24
Finished Jul 15 07:11:44 PM PDT 24
Peak memory 206788 kb
Host smart-8a687740-f78d-405a-9aae-1209415e1305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29923
10166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2992310166
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1199795001
Short name T2113
Test name
Test status
Simulation time 259008924 ps
CPU time 0.99 seconds
Started Jul 15 07:11:19 PM PDT 24
Finished Jul 15 07:11:20 PM PDT 24
Peak memory 206792 kb
Host smart-6d4d6d54-7858-46d2-8ec8-545e5e92ba1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11997
95001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1199795001
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1411876116
Short name T151
Test name
Test status
Simulation time 3193080047 ps
CPU time 86.75 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:13:13 PM PDT 24
Peak memory 206860 kb
Host smart-2f3e6f30-370a-478e-b691-c675b94a3c84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1411876116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1411876116
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1691828885
Short name T2333
Test name
Test status
Simulation time 244901369 ps
CPU time 0.86 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:48 PM PDT 24
Peak memory 206796 kb
Host smart-d0249989-7a92-4941-8274-092a8782c2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16918
28885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1691828885
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.869063199
Short name T2518
Test name
Test status
Simulation time 179750626 ps
CPU time 0.79 seconds
Started Jul 15 07:11:45 PM PDT 24
Finished Jul 15 07:11:51 PM PDT 24
Peak memory 206792 kb
Host smart-4140992f-7c65-4af5-adb5-3f8f7e2c0a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86906
3199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.869063199
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2576989487
Short name T2444
Test name
Test status
Simulation time 1145741096 ps
CPU time 2.4 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:11:49 PM PDT 24
Peak memory 206872 kb
Host smart-199a1903-6987-48a0-833b-702ce8b1eecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25769
89487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2576989487
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.3002359660
Short name T936
Test name
Test status
Simulation time 5139720995 ps
CPU time 137.09 seconds
Started Jul 15 07:11:43 PM PDT 24
Finished Jul 15 07:14:04 PM PDT 24
Peak memory 207004 kb
Host smart-23dfc6c9-e22f-4d9c-97a8-8908e96ebd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023
59660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.3002359660
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3728071827
Short name T1942
Test name
Test status
Simulation time 50273831 ps
CPU time 0.66 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:03:54 PM PDT 24
Peak memory 206828 kb
Host smart-dd53b1a1-c2b5-4f2d-ba43-4062a8fbf8b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3728071827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3728071827
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1099172414
Short name T1960
Test name
Test status
Simulation time 3526690938 ps
CPU time 3.98 seconds
Started Jul 15 07:03:37 PM PDT 24
Finished Jul 15 07:03:42 PM PDT 24
Peak memory 206896 kb
Host smart-7c91c890-160c-40e3-a04f-155afba7b36c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1099172414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1099172414
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.841394686
Short name T2497
Test name
Test status
Simulation time 13464603590 ps
CPU time 12.89 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:03:52 PM PDT 24
Peak memory 207068 kb
Host smart-2a5164f3-5998-4b9d-8a2f-5156187fec28
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=841394686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.841394686
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2931845588
Short name T897
Test name
Test status
Simulation time 23302235924 ps
CPU time 21.56 seconds
Started Jul 15 07:03:38 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 207068 kb
Host smart-4ab48d30-0177-4c5a-b9d3-615b21478cd1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2931845588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.2931845588
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.57047346
Short name T341
Test name
Test status
Simulation time 183299171 ps
CPU time 0.79 seconds
Started Jul 15 07:03:36 PM PDT 24
Finished Jul 15 07:03:38 PM PDT 24
Peak memory 206796 kb
Host smart-a9b74a1e-3722-4af6-98c4-21bdabe4b5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57047
346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.57047346
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.818114920
Short name T1671
Test name
Test status
Simulation time 152148870 ps
CPU time 0.76 seconds
Started Jul 15 07:03:34 PM PDT 24
Finished Jul 15 07:03:35 PM PDT 24
Peak memory 206808 kb
Host smart-be0bfe24-ccb4-4e7b-9851-b4604d17351b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81811
4920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.818114920
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3014581765
Short name T1698
Test name
Test status
Simulation time 193347239 ps
CPU time 0.85 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206784 kb
Host smart-b0e5e1f0-bbc6-4eff-9b48-c43e9ca90ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30145
81765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3014581765
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3902839914
Short name T1575
Test name
Test status
Simulation time 323002700 ps
CPU time 0.98 seconds
Started Jul 15 07:03:40 PM PDT 24
Finished Jul 15 07:03:43 PM PDT 24
Peak memory 206820 kb
Host smart-b3526f6a-f415-4395-84b9-c5d9f084b246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39028
39914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3902839914
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.2926102423
Short name T2384
Test name
Test status
Simulation time 10581383666 ps
CPU time 22.31 seconds
Started Jul 15 07:03:40 PM PDT 24
Finished Jul 15 07:04:04 PM PDT 24
Peak memory 207016 kb
Host smart-6d73a558-85c6-464e-ac2f-8a4f11b79985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29261
02423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.2926102423
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3134385805
Short name T1770
Test name
Test status
Simulation time 155664003 ps
CPU time 0.8 seconds
Started Jul 15 07:03:40 PM PDT 24
Finished Jul 15 07:03:42 PM PDT 24
Peak memory 206812 kb
Host smart-3a91dd86-7a4d-4c2b-81a6-4702714f1f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31343
85805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3134385805
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3960248823
Short name T986
Test name
Test status
Simulation time 512853128 ps
CPU time 1.45 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:03:43 PM PDT 24
Peak memory 206808 kb
Host smart-eb9e7970-ac96-416f-aa7a-fc7288ad309b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39602
48823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3960248823
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2583222120
Short name T2422
Test name
Test status
Simulation time 148957207 ps
CPU time 0.76 seconds
Started Jul 15 07:03:40 PM PDT 24
Finished Jul 15 07:03:41 PM PDT 24
Peak memory 206792 kb
Host smart-200914a4-4f80-4042-bd28-addb5f480a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25832
22120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2583222120
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2076295713
Short name T2731
Test name
Test status
Simulation time 35063518 ps
CPU time 0.63 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:03:43 PM PDT 24
Peak memory 206820 kb
Host smart-b6c706b9-1cc8-4f54-bcd5-2666760f0276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20762
95713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2076295713
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.424620562
Short name T2183
Test name
Test status
Simulation time 874496068 ps
CPU time 2.19 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:03:46 PM PDT 24
Peak memory 206976 kb
Host smart-a0755918-d421-4d2d-a8bc-5b63ed36aa48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
0562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.424620562
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1383815496
Short name T987
Test name
Test status
Simulation time 367072526 ps
CPU time 2.35 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:03:46 PM PDT 24
Peak memory 206956 kb
Host smart-8e4fc41e-04c3-4f71-8a2f-8dd1c5c04dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13838
15496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1383815496
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3483635538
Short name T1078
Test name
Test status
Simulation time 196874947 ps
CPU time 0.87 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206700 kb
Host smart-dea1131b-9b80-44ab-aa5a-62bf76fd6424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
35538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3483635538
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3839154671
Short name T1848
Test name
Test status
Simulation time 195597102 ps
CPU time 0.81 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:03:44 PM PDT 24
Peak memory 206820 kb
Host smart-911ecf37-74e9-404a-abf4-832c1d9763ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38391
54671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3839154671
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.646794907
Short name T1681
Test name
Test status
Simulation time 152876724 ps
CPU time 0.77 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:03:43 PM PDT 24
Peak memory 206812 kb
Host smart-edc8eeaf-a9d8-45be-9943-af15b1fd5661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64679
4907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.646794907
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.4037403728
Short name T1534
Test name
Test status
Simulation time 10737729129 ps
CPU time 102.6 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:05:27 PM PDT 24
Peak memory 206872 kb
Host smart-cdff0146-fdce-4817-8be8-a8004928f7a4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4037403728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.4037403728
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1663351776
Short name T2521
Test name
Test status
Simulation time 10993654577 ps
CPU time 88.61 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:05:12 PM PDT 24
Peak memory 206992 kb
Host smart-fc1d3dc4-0b87-4a21-8e14-5816e362ec40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16633
51776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1663351776
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3581381297
Short name T2724
Test name
Test status
Simulation time 234011926 ps
CPU time 0.87 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:03:44 PM PDT 24
Peak memory 206836 kb
Host smart-409a92c0-68be-4703-b7af-60f0784a3a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
81297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3581381297
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2552042655
Short name T2701
Test name
Test status
Simulation time 23319578488 ps
CPU time 27.25 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:04:10 PM PDT 24
Peak memory 206828 kb
Host smart-654a9e75-61a6-475d-9960-4fc476f4fa22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
42655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2552042655
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.530574952
Short name T1064
Test name
Test status
Simulation time 3320255767 ps
CPU time 4.44 seconds
Started Jul 15 07:03:40 PM PDT 24
Finished Jul 15 07:03:46 PM PDT 24
Peak memory 206860 kb
Host smart-80ce3d60-ca2b-475e-b597-7808453fe373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53057
4952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.530574952
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3270385030
Short name T766
Test name
Test status
Simulation time 7399953299 ps
CPU time 69.41 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:04:52 PM PDT 24
Peak memory 207096 kb
Host smart-2a651d54-4c85-4d61-a4a9-7d3435f153e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32703
85030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3270385030
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2379257838
Short name T532
Test name
Test status
Simulation time 4592758639 ps
CPU time 34.41 seconds
Started Jul 15 07:03:48 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 207012 kb
Host smart-2dbcd1f8-9cb8-4aeb-ae0e-7be4e0045610
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2379257838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2379257838
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.493185436
Short name T1214
Test name
Test status
Simulation time 240192332 ps
CPU time 0.88 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:03:43 PM PDT 24
Peak memory 206812 kb
Host smart-0faf55ee-ffeb-466f-b4df-a17c33ece083
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=493185436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.493185436
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1008425960
Short name T2122
Test name
Test status
Simulation time 200963129 ps
CPU time 0.87 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206816 kb
Host smart-73aafb5e-b66c-407d-99c2-b8692ec39ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10084
25960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1008425960
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3314941350
Short name T2441
Test name
Test status
Simulation time 3312848782 ps
CPU time 32.86 seconds
Started Jul 15 07:03:48 PM PDT 24
Finished Jul 15 07:04:21 PM PDT 24
Peak memory 207076 kb
Host smart-fd5d39ca-1f7e-4b95-ae6f-287c0ce846fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33149
41350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3314941350
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1956156858
Short name T1601
Test name
Test status
Simulation time 2830375156 ps
CPU time 26.97 seconds
Started Jul 15 07:03:39 PM PDT 24
Finished Jul 15 07:04:07 PM PDT 24
Peak memory 207012 kb
Host smart-b48c59f8-e35e-415c-934f-1c8737e6c47c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1956156858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1956156858
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2577120049
Short name T1871
Test name
Test status
Simulation time 170455237 ps
CPU time 0.81 seconds
Started Jul 15 07:03:47 PM PDT 24
Finished Jul 15 07:03:48 PM PDT 24
Peak memory 206800 kb
Host smart-b881149a-7ff4-4aac-9693-bace5ebcf38f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2577120049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2577120049
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.540222197
Short name T2096
Test name
Test status
Simulation time 212358159 ps
CPU time 0.89 seconds
Started Jul 15 07:03:41 PM PDT 24
Finished Jul 15 07:03:44 PM PDT 24
Peak memory 206828 kb
Host smart-fdba66cb-4c97-4ec5-a514-d7c825804e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54022
2197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.540222197
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2718411475
Short name T2101
Test name
Test status
Simulation time 218985018 ps
CPU time 0.88 seconds
Started Jul 15 07:03:43 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206836 kb
Host smart-55d2cc71-5bff-49bd-81a5-b801469a77f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27184
11475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2718411475
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4285173523
Short name T1947
Test name
Test status
Simulation time 201049908 ps
CPU time 0.83 seconds
Started Jul 15 07:03:43 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206832 kb
Host smart-90708314-85e6-4822-9316-5fb28baab8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851
73523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4285173523
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3706484472
Short name T2676
Test name
Test status
Simulation time 174189596 ps
CPU time 0.78 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206800 kb
Host smart-187698d5-2a54-49e2-9d92-90182017971e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37064
84472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3706484472
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3729379352
Short name T282
Test name
Test status
Simulation time 208481474 ps
CPU time 0.86 seconds
Started Jul 15 07:03:43 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206824 kb
Host smart-5422edab-b11d-4ee2-87fc-d16bc816e41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37293
79352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3729379352
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.672916806
Short name T2357
Test name
Test status
Simulation time 147465062 ps
CPU time 0.79 seconds
Started Jul 15 07:03:47 PM PDT 24
Finished Jul 15 07:03:49 PM PDT 24
Peak memory 206812 kb
Host smart-bd24c504-23b3-44c2-afdd-4b89867df177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67291
6806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.672916806
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2360350953
Short name T2581
Test name
Test status
Simulation time 235735363 ps
CPU time 0.91 seconds
Started Jul 15 07:03:43 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206840 kb
Host smart-c611e0a4-7f42-4c66-8e2b-726508a33d9a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2360350953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2360350953
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.864119630
Short name T1953
Test name
Test status
Simulation time 191636280 ps
CPU time 0.76 seconds
Started Jul 15 07:03:43 PM PDT 24
Finished Jul 15 07:03:45 PM PDT 24
Peak memory 206812 kb
Host smart-0960d803-3f21-476c-87c8-bd5fe4ebfa1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86411
9630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.864119630
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3376693827
Short name T1451
Test name
Test status
Simulation time 28561800 ps
CPU time 0.62 seconds
Started Jul 15 07:03:42 PM PDT 24
Finished Jul 15 07:03:44 PM PDT 24
Peak memory 206776 kb
Host smart-f96a6289-2add-47a9-8fa1-d1fa351845a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
93827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3376693827
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.913200364
Short name T1611
Test name
Test status
Simulation time 17786232262 ps
CPU time 43.21 seconds
Started Jul 15 07:03:46 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 207092 kb
Host smart-2a3987bb-80d5-42c8-a79f-c37520927b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91320
0364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.913200364
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.233716472
Short name T2448
Test name
Test status
Simulation time 188010972 ps
CPU time 0.86 seconds
Started Jul 15 07:03:45 PM PDT 24
Finished Jul 15 07:03:47 PM PDT 24
Peak memory 206808 kb
Host smart-40f0ccbc-405d-44ef-aff4-8a98ab4552a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23371
6472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.233716472
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2905553723
Short name T1637
Test name
Test status
Simulation time 223180838 ps
CPU time 0.86 seconds
Started Jul 15 07:03:49 PM PDT 24
Finished Jul 15 07:03:51 PM PDT 24
Peak memory 206804 kb
Host smart-a8384653-1de2-435b-b289-a7964443087b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
53723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2905553723
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3409539383
Short name T165
Test name
Test status
Simulation time 14565325518 ps
CPU time 107.49 seconds
Started Jul 15 07:03:45 PM PDT 24
Finished Jul 15 07:05:33 PM PDT 24
Peak memory 207040 kb
Host smart-44345db9-f0c0-4c8a-8323-96fedc683b58
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3409539383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3409539383
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3222468493
Short name T1287
Test name
Test status
Simulation time 15932233992 ps
CPU time 85.84 seconds
Started Jul 15 07:03:45 PM PDT 24
Finished Jul 15 07:05:12 PM PDT 24
Peak memory 206988 kb
Host smart-2069c486-f25b-4dab-ac18-192a7f83120a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3222468493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3222468493
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3261476841
Short name T1066
Test name
Test status
Simulation time 240717390 ps
CPU time 0.98 seconds
Started Jul 15 07:03:47 PM PDT 24
Finished Jul 15 07:03:49 PM PDT 24
Peak memory 206840 kb
Host smart-c211a157-227e-4f5f-8a18-3cbf8fa56d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
76841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3261476841
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3177356449
Short name T1311
Test name
Test status
Simulation time 211118821 ps
CPU time 0.85 seconds
Started Jul 15 07:03:49 PM PDT 24
Finished Jul 15 07:03:51 PM PDT 24
Peak memory 206828 kb
Host smart-6c2629f1-483b-4ecf-a308-0f48356a6a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31773
56449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3177356449
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3145409214
Short name T1398
Test name
Test status
Simulation time 139779735 ps
CPU time 0.73 seconds
Started Jul 15 07:03:45 PM PDT 24
Finished Jul 15 07:03:47 PM PDT 24
Peak memory 206788 kb
Host smart-bc937a6e-3f2e-403b-be38-589260dbb63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454
09214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3145409214
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1604761849
Short name T1244
Test name
Test status
Simulation time 162379752 ps
CPU time 0.78 seconds
Started Jul 15 07:03:46 PM PDT 24
Finished Jul 15 07:03:48 PM PDT 24
Peak memory 206792 kb
Host smart-61d489c4-b12c-4fc6-9a65-68fcf94f130b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16047
61849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1604761849
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.2518831361
Short name T594
Test name
Test status
Simulation time 170439700 ps
CPU time 0.84 seconds
Started Jul 15 07:03:46 PM PDT 24
Finished Jul 15 07:03:48 PM PDT 24
Peak memory 206768 kb
Host smart-e20f1e7b-96d0-4f03-b9bb-355f5ce14cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25188
31361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.2518831361
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2479195825
Short name T573
Test name
Test status
Simulation time 203779913 ps
CPU time 0.88 seconds
Started Jul 15 07:03:46 PM PDT 24
Finished Jul 15 07:03:48 PM PDT 24
Peak memory 206808 kb
Host smart-57ce4467-0009-46b7-bb1e-374f807287bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24791
95825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2479195825
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.212590641
Short name T1203
Test name
Test status
Simulation time 5795668519 ps
CPU time 44.4 seconds
Started Jul 15 07:03:44 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 207060 kb
Host smart-47c29454-deca-4c31-9b18-eb791339bb3c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=212590641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.212590641
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2066526653
Short name T2239
Test name
Test status
Simulation time 187875404 ps
CPU time 0.79 seconds
Started Jul 15 07:03:46 PM PDT 24
Finished Jul 15 07:03:48 PM PDT 24
Peak memory 206788 kb
Host smart-a4ab67ec-4f88-46d9-b721-70e96db84049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20665
26653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2066526653
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.119091245
Short name T2665
Test name
Test status
Simulation time 158544752 ps
CPU time 0.77 seconds
Started Jul 15 07:03:47 PM PDT 24
Finished Jul 15 07:03:49 PM PDT 24
Peak memory 206824 kb
Host smart-b192e94a-2dc3-49dd-a559-60357f306d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11909
1245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.119091245
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.3653490052
Short name T746
Test name
Test status
Simulation time 400336872 ps
CPU time 1.27 seconds
Started Jul 15 07:03:46 PM PDT 24
Finished Jul 15 07:03:48 PM PDT 24
Peak memory 206820 kb
Host smart-b8a7eb69-9188-45cb-856f-7a6f8467a99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36534
90052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.3653490052
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.4019780220
Short name T2394
Test name
Test status
Simulation time 4235702975 ps
CPU time 30.17 seconds
Started Jul 15 07:03:47 PM PDT 24
Finished Jul 15 07:04:18 PM PDT 24
Peak memory 207072 kb
Host smart-a33b01ac-a190-4625-b2a4-8c41a77d5f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40197
80220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.4019780220
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1133934468
Short name T2269
Test name
Test status
Simulation time 48143611 ps
CPU time 0.67 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:07 PM PDT 24
Peak memory 206840 kb
Host smart-ccd39ad1-a0fd-4efb-9dd0-c1e31c18a138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1133934468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1133934468
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2597171811
Short name T1292
Test name
Test status
Simulation time 3685149093 ps
CPU time 4.13 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:03:58 PM PDT 24
Peak memory 206988 kb
Host smart-bc812f97-ca1d-403c-bcd3-a707b45240c7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2597171811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.2597171811
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3178442400
Short name T1543
Test name
Test status
Simulation time 13389072111 ps
CPU time 14.55 seconds
Started Jul 15 07:03:54 PM PDT 24
Finished Jul 15 07:04:10 PM PDT 24
Peak memory 206692 kb
Host smart-8fd79d28-df48-49a0-a7be-ef3b7c7e189f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3178442400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3178442400
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3760941481
Short name T1519
Test name
Test status
Simulation time 23361104758 ps
CPU time 22.65 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:04:17 PM PDT 24
Peak memory 206892 kb
Host smart-ea9ea76b-0e2e-4cd1-97cb-762810828f41
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3760941481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3760941481
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2600184077
Short name T371
Test name
Test status
Simulation time 164383808 ps
CPU time 0.79 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 206832 kb
Host smart-e97e8f76-0aaf-4a5e-960d-f80e345a0cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26001
84077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2600184077
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3800020548
Short name T1277
Test name
Test status
Simulation time 194679859 ps
CPU time 0.82 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 206828 kb
Host smart-c5c409fa-60ea-45f9-904a-1e6b97bef0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38000
20548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3800020548
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.877823698
Short name T388
Test name
Test status
Simulation time 166825554 ps
CPU time 0.82 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 206760 kb
Host smart-79a293d6-1c09-4d61-b35b-552da17b1710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87782
3698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.877823698
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1795968606
Short name T2309
Test name
Test status
Simulation time 767865714 ps
CPU time 1.81 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 207020 kb
Host smart-19879d45-2343-4343-add6-79f2b6de7a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17959
68606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1795968606
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3255354323
Short name T832
Test name
Test status
Simulation time 17534348889 ps
CPU time 38.28 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 207020 kb
Host smart-e45cfd5d-e3f1-4922-a939-fd46e6bcf544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32553
54323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3255354323
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.382711204
Short name T2330
Test name
Test status
Simulation time 142448088 ps
CPU time 0.78 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:03:53 PM PDT 24
Peak memory 206828 kb
Host smart-1d17ea40-306c-4a94-80f7-2b7e9aec3050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38271
1204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.382711204
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3978368608
Short name T1976
Test name
Test status
Simulation time 434354890 ps
CPU time 1.28 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 206824 kb
Host smart-eadac019-373a-4e4a-8ad6-41c072587840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39783
68608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3978368608
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.662723433
Short name T2300
Test name
Test status
Simulation time 142364887 ps
CPU time 0.78 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 206820 kb
Host smart-299ec3b0-4a93-42c1-b4db-17a5359b549b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66272
3433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.662723433
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1388870701
Short name T2559
Test name
Test status
Simulation time 89578470 ps
CPU time 0.71 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:03:54 PM PDT 24
Peak memory 206820 kb
Host smart-e2aa8b02-6cbf-42ec-be8c-6428edddfb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13888
70701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1388870701
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1642795553
Short name T1282
Test name
Test status
Simulation time 923867982 ps
CPU time 2.04 seconds
Started Jul 15 07:03:54 PM PDT 24
Finished Jul 15 07:03:57 PM PDT 24
Peak memory 206976 kb
Host smart-bfc4a91a-5e7b-4176-901e-00c1c13c5fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16427
95553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1642795553
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3235365274
Short name T2117
Test name
Test status
Simulation time 424685893 ps
CPU time 2.59 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 206952 kb
Host smart-09e4b4a8-85b0-4ed8-a441-76b6aed1c337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32353
65274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3235365274
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.4110001102
Short name T1792
Test name
Test status
Simulation time 201443148 ps
CPU time 0.86 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:03:54 PM PDT 24
Peak memory 206824 kb
Host smart-4201db80-d184-4766-b5ba-3c43ef7de004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41100
01102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.4110001102
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3875411945
Short name T1673
Test name
Test status
Simulation time 148380476 ps
CPU time 0.81 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:03:55 PM PDT 24
Peak memory 206784 kb
Host smart-dfed7954-b117-4e5d-a623-3a69d9a5d4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38754
11945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3875411945
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.80438634
Short name T1381
Test name
Test status
Simulation time 216394236 ps
CPU time 0.89 seconds
Started Jul 15 07:03:54 PM PDT 24
Finished Jul 15 07:03:56 PM PDT 24
Peak memory 206764 kb
Host smart-836e9d48-971a-4469-b978-ccec2432a356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80438
634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.80438634
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.3948817177
Short name T1254
Test name
Test status
Simulation time 13645230323 ps
CPU time 44.77 seconds
Started Jul 15 07:03:54 PM PDT 24
Finished Jul 15 07:04:40 PM PDT 24
Peak memory 206968 kb
Host smart-97401ee0-399e-4d2e-b6a4-ea7755f14a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39488
17177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.3948817177
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.168750080
Short name T1758
Test name
Test status
Simulation time 264177233 ps
CPU time 0.94 seconds
Started Jul 15 07:03:52 PM PDT 24
Finished Jul 15 07:03:54 PM PDT 24
Peak memory 206844 kb
Host smart-b8a77698-db7f-498d-a11c-bc35d231e9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16875
0080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.168750080
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2555987141
Short name T2041
Test name
Test status
Simulation time 23286946518 ps
CPU time 25.83 seconds
Started Jul 15 07:03:54 PM PDT 24
Finished Jul 15 07:04:21 PM PDT 24
Peak memory 206692 kb
Host smart-677c2d5e-a1ea-478d-a5ea-ab0bec495b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25559
87141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2555987141
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.644352211
Short name T1777
Test name
Test status
Simulation time 3327476369 ps
CPU time 4.02 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:03:57 PM PDT 24
Peak memory 206856 kb
Host smart-91151697-b3b8-4186-9872-e9e6407ce3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64435
2211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.644352211
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1728292178
Short name T1835
Test name
Test status
Simulation time 10000106463 ps
CPU time 74.55 seconds
Started Jul 15 07:03:53 PM PDT 24
Finished Jul 15 07:05:08 PM PDT 24
Peak memory 207088 kb
Host smart-efe2bac0-520c-4a28-8c35-98abce85bb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17282
92178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1728292178
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2453149934
Short name T1977
Test name
Test status
Simulation time 4223951026 ps
CPU time 30.99 seconds
Started Jul 15 07:04:01 PM PDT 24
Finished Jul 15 07:04:33 PM PDT 24
Peak memory 206896 kb
Host smart-5a02691c-7592-4f7c-ac66-c1c8529d01cc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2453149934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2453149934
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2880373987
Short name T472
Test name
Test status
Simulation time 249801017 ps
CPU time 0.92 seconds
Started Jul 15 07:03:51 PM PDT 24
Finished Jul 15 07:03:52 PM PDT 24
Peak memory 206800 kb
Host smart-c8be5816-2b2d-41af-b92b-b3de5cffddc7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2880373987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2880373987
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1889647067
Short name T1588
Test name
Test status
Simulation time 194624003 ps
CPU time 0.86 seconds
Started Jul 15 07:04:00 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 206764 kb
Host smart-b58dfc49-dd9c-4a7a-aa5c-6ce1e9be713f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18896
47067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1889647067
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2646485058
Short name T2520
Test name
Test status
Simulation time 6941945945 ps
CPU time 52.83 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:04:52 PM PDT 24
Peak memory 207076 kb
Host smart-3263755e-b10e-4cb8-b524-92b61095d4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26464
85058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2646485058
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.2682528740
Short name T1554
Test name
Test status
Simulation time 7496952321 ps
CPU time 214 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:07:32 PM PDT 24
Peak memory 207016 kb
Host smart-09617d21-a384-4d5c-806a-e64d12b7577e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2682528740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2682528740
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3037412069
Short name T615
Test name
Test status
Simulation time 193131239 ps
CPU time 0.85 seconds
Started Jul 15 07:04:00 PM PDT 24
Finished Jul 15 07:04:02 PM PDT 24
Peak memory 206832 kb
Host smart-ccc209ba-c02d-4bc8-b551-e314b57ae8d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3037412069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3037412069
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2359135620
Short name T376
Test name
Test status
Simulation time 152467188 ps
CPU time 0.84 seconds
Started Jul 15 07:03:59 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 206844 kb
Host smart-1976b99b-2d30-4c81-af35-ea53637dac64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23591
35620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2359135620
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2806808387
Short name T132
Test name
Test status
Simulation time 248827248 ps
CPU time 0.89 seconds
Started Jul 15 07:03:59 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 206824 kb
Host smart-45c2d063-c9ec-4608-865c-bfda5e3f8cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28068
08387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2806808387
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2466418693
Short name T2273
Test name
Test status
Simulation time 183308288 ps
CPU time 0.9 seconds
Started Jul 15 07:04:00 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 206828 kb
Host smart-e9c203fa-6569-4142-920f-f7b1fbf06404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24664
18693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2466418693
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3121470390
Short name T727
Test name
Test status
Simulation time 169559462 ps
CPU time 0.79 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:04:00 PM PDT 24
Peak memory 206784 kb
Host smart-9e7e4118-1905-4f5f-8bc5-a48602cd5f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31214
70390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3121470390
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3559531111
Short name T958
Test name
Test status
Simulation time 185755543 ps
CPU time 0.84 seconds
Started Jul 15 07:03:57 PM PDT 24
Finished Jul 15 07:03:58 PM PDT 24
Peak memory 206828 kb
Host smart-d8d82fe1-55c9-4afd-9287-04f7af1797f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35595
31111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3559531111
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2660763994
Short name T1875
Test name
Test status
Simulation time 166634735 ps
CPU time 0.8 seconds
Started Jul 15 07:03:57 PM PDT 24
Finished Jul 15 07:03:59 PM PDT 24
Peak memory 206972 kb
Host smart-032e2247-92f3-4e86-af4d-1ba315f3cd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26607
63994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2660763994
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.358130695
Short name T2615
Test name
Test status
Simulation time 196935696 ps
CPU time 0.93 seconds
Started Jul 15 07:03:56 PM PDT 24
Finished Jul 15 07:03:58 PM PDT 24
Peak memory 206772 kb
Host smart-1a9da782-8796-4d8d-a492-6be6e7619c20
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=358130695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.358130695
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3392990598
Short name T1149
Test name
Test status
Simulation time 161528260 ps
CPU time 0.79 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:04:00 PM PDT 24
Peak memory 206824 kb
Host smart-4e187775-5a00-456d-a23f-d2fb271e9e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33929
90598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3392990598
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.252687867
Short name T706
Test name
Test status
Simulation time 43702923 ps
CPU time 0.66 seconds
Started Jul 15 07:04:01 PM PDT 24
Finished Jul 15 07:04:02 PM PDT 24
Peak memory 206732 kb
Host smart-6323b8d4-5fbc-43bd-bda3-21af4d7fb141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25268
7867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.252687867
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1778133707
Short name T2220
Test name
Test status
Simulation time 15001854616 ps
CPU time 34.35 seconds
Started Jul 15 07:04:00 PM PDT 24
Finished Jul 15 07:04:35 PM PDT 24
Peak memory 215188 kb
Host smart-eb4d0d55-66ee-44c6-8a53-733c3dd9eda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17781
33707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1778133707
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3799899264
Short name T833
Test name
Test status
Simulation time 183660251 ps
CPU time 0.88 seconds
Started Jul 15 07:04:01 PM PDT 24
Finished Jul 15 07:04:02 PM PDT 24
Peak memory 206752 kb
Host smart-852db37c-e9d4-404f-a74f-bf8c5102cd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37998
99264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3799899264
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3152754794
Short name T2195
Test name
Test status
Simulation time 226148584 ps
CPU time 0.95 seconds
Started Jul 15 07:04:00 PM PDT 24
Finished Jul 15 07:04:02 PM PDT 24
Peak memory 206832 kb
Host smart-11dd27b4-7c34-4bd4-b431-6fe14f10ce65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31527
54794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3152754794
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2467512637
Short name T1568
Test name
Test status
Simulation time 14488743613 ps
CPU time 394.71 seconds
Started Jul 15 07:03:56 PM PDT 24
Finished Jul 15 07:10:31 PM PDT 24
Peak memory 207072 kb
Host smart-23069537-2138-450d-8cd0-fac0d3853c39
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2467512637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2467512637
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2922987457
Short name T1307
Test name
Test status
Simulation time 4258012744 ps
CPU time 31.39 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 206988 kb
Host smart-2e936bf5-1ec5-45f7-a52f-4a18e8c4bdd2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2922987457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2922987457
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.619977018
Short name T458
Test name
Test status
Simulation time 20197975900 ps
CPU time 448.12 seconds
Started Jul 15 07:04:01 PM PDT 24
Finished Jul 15 07:11:30 PM PDT 24
Peak memory 207052 kb
Host smart-b192ed5b-71bb-4252-a169-e0d9b40bdccb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=619977018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.619977018
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2070892510
Short name T2548
Test name
Test status
Simulation time 179433504 ps
CPU time 0.82 seconds
Started Jul 15 07:04:00 PM PDT 24
Finished Jul 15 07:04:01 PM PDT 24
Peak memory 206824 kb
Host smart-e948825c-718e-461d-a820-696baba2331f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20708
92510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2070892510
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2778452931
Short name T955
Test name
Test status
Simulation time 175754203 ps
CPU time 0.85 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:03:59 PM PDT 24
Peak memory 206808 kb
Host smart-d7a87931-7225-40f5-a930-1c4786fb5dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27784
52931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2778452931
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3453265589
Short name T2098
Test name
Test status
Simulation time 202450146 ps
CPU time 0.87 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:04:00 PM PDT 24
Peak memory 206800 kb
Host smart-1bae8f52-c4bc-456e-9515-0d56a12321ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34532
65589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3453265589
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4161210008
Short name T311
Test name
Test status
Simulation time 150342436 ps
CPU time 0.77 seconds
Started Jul 15 07:03:57 PM PDT 24
Finished Jul 15 07:03:59 PM PDT 24
Peak memory 206804 kb
Host smart-12e89362-8edc-4efe-8f90-98c3ee4bc716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41612
10008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4161210008
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1974496044
Short name T90
Test name
Test status
Simulation time 154194150 ps
CPU time 0.75 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:03:59 PM PDT 24
Peak memory 206792 kb
Host smart-ab656765-9fb3-49b0-899c-5cbbf39ab4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19744
96044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1974496044
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3621152739
Short name T1602
Test name
Test status
Simulation time 255567975 ps
CPU time 0.93 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:04:00 PM PDT 24
Peak memory 206820 kb
Host smart-48a9c28d-ae0b-4ac9-aa65-f2e64293445c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36211
52739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3621152739
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2703044902
Short name T983
Test name
Test status
Simulation time 4054665286 ps
CPU time 43.48 seconds
Started Jul 15 07:03:57 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 207088 kb
Host smart-2849c951-43fd-4d7d-9551-ec2bbc961155
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2703044902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2703044902
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1022201073
Short name T2622
Test name
Test status
Simulation time 206959970 ps
CPU time 0.83 seconds
Started Jul 15 07:04:00 PM PDT 24
Finished Jul 15 07:04:02 PM PDT 24
Peak memory 206836 kb
Host smart-33dac8ce-fb2f-455e-b10a-9e19d82ea218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10222
01073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1022201073
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.218760252
Short name T1391
Test name
Test status
Simulation time 231094402 ps
CPU time 0.86 seconds
Started Jul 15 07:03:58 PM PDT 24
Finished Jul 15 07:04:00 PM PDT 24
Peak memory 206796 kb
Host smart-6c7550b3-5bc8-47a5-a513-5ee2249993ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21876
0252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.218760252
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.3247200677
Short name T1663
Test name
Test status
Simulation time 805012678 ps
CPU time 1.9 seconds
Started Jul 15 07:04:04 PM PDT 24
Finished Jul 15 07:04:06 PM PDT 24
Peak memory 206988 kb
Host smart-e3dbf9d2-f5d6-43d3-9134-6f6562d7fb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472
00677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.3247200677
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3117844312
Short name T1394
Test name
Test status
Simulation time 3260050930 ps
CPU time 26.35 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:33 PM PDT 24
Peak memory 207020 kb
Host smart-dcc4a4d4-279d-4a9c-88f5-d47a8568c8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31178
44312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3117844312
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1073275106
Short name T1407
Test name
Test status
Simulation time 107961363 ps
CPU time 0.79 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:19 PM PDT 24
Peak memory 206820 kb
Host smart-235c9d06-135d-49fe-8070-2b92f1a75818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1073275106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1073275106
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3095038104
Short name T188
Test name
Test status
Simulation time 3550758126 ps
CPU time 4.32 seconds
Started Jul 15 07:04:07 PM PDT 24
Finished Jul 15 07:04:12 PM PDT 24
Peak memory 207100 kb
Host smart-26e6e36c-3850-4a4e-a9a4-f14685a23a14
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3095038104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.3095038104
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2711529302
Short name T505
Test name
Test status
Simulation time 13309517884 ps
CPU time 12.49 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:18 PM PDT 24
Peak memory 207020 kb
Host smart-beaa4d5f-7705-49d2-9144-b2eb0dfb4b4f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2711529302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2711529302
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1114094176
Short name T1382
Test name
Test status
Simulation time 23286459154 ps
CPU time 23.59 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:29 PM PDT 24
Peak memory 207048 kb
Host smart-265a8a58-8a9b-4077-9e50-fc45397637e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1114094176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.1114094176
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3567369524
Short name T390
Test name
Test status
Simulation time 184364303 ps
CPU time 0.87 seconds
Started Jul 15 07:04:04 PM PDT 24
Finished Jul 15 07:04:06 PM PDT 24
Peak memory 206784 kb
Host smart-ea4eb2fb-0009-43c1-8851-d5f8a5722a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35673
69524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3567369524
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2420783214
Short name T1501
Test name
Test status
Simulation time 141152359 ps
CPU time 0.76 seconds
Started Jul 15 07:04:07 PM PDT 24
Finished Jul 15 07:04:08 PM PDT 24
Peak memory 206844 kb
Host smart-ab13047a-7668-4405-ab9c-2ab243ec59f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24207
83214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2420783214
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.616266149
Short name T2741
Test name
Test status
Simulation time 140891347 ps
CPU time 0.78 seconds
Started Jul 15 07:04:04 PM PDT 24
Finished Jul 15 07:04:06 PM PDT 24
Peak memory 206816 kb
Host smart-3c1177bf-452d-4107-bbc2-f3b02874d70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61626
6149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.616266149
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1754277582
Short name T563
Test name
Test status
Simulation time 359437538 ps
CPU time 1.16 seconds
Started Jul 15 07:04:06 PM PDT 24
Finished Jul 15 07:04:08 PM PDT 24
Peak memory 206832 kb
Host smart-eb1c36f7-3227-42fc-958d-b5e04f29f081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17542
77582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1754277582
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.660187339
Short name T1709
Test name
Test status
Simulation time 20291952330 ps
CPU time 36.57 seconds
Started Jul 15 07:04:06 PM PDT 24
Finished Jul 15 07:04:44 PM PDT 24
Peak memory 207032 kb
Host smart-b480d77d-d7c5-4b1b-a4fb-0f7d19c8b18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66018
7339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.660187339
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.610296790
Short name T1106
Test name
Test status
Simulation time 391623855 ps
CPU time 1.2 seconds
Started Jul 15 07:04:07 PM PDT 24
Finished Jul 15 07:04:09 PM PDT 24
Peak memory 206804 kb
Host smart-14c33b10-5f74-4195-859d-ba2b0abf5f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61029
6790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.610296790
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3119474061
Short name T411
Test name
Test status
Simulation time 136994896 ps
CPU time 0.77 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:06 PM PDT 24
Peak memory 206840 kb
Host smart-bfae7870-8ea0-44f9-8f24-6561bc514091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31194
74061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3119474061
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2648439649
Short name T867
Test name
Test status
Simulation time 55722608 ps
CPU time 0.74 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:07 PM PDT 24
Peak memory 206784 kb
Host smart-b1a5c229-aafb-484c-a2dd-26a855f79b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26484
39649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2648439649
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.471293949
Short name T2152
Test name
Test status
Simulation time 995696775 ps
CPU time 2.34 seconds
Started Jul 15 07:04:07 PM PDT 24
Finished Jul 15 07:04:10 PM PDT 24
Peak memory 207008 kb
Host smart-5e500a83-af6f-4b00-ae3c-45857372e381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47129
3949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.471293949
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3686906771
Short name T1689
Test name
Test status
Simulation time 327006446 ps
CPU time 2.03 seconds
Started Jul 15 07:04:04 PM PDT 24
Finished Jul 15 07:04:07 PM PDT 24
Peak memory 207020 kb
Host smart-e82cbce5-d2b1-484c-8e31-5f5f820472e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36869
06771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3686906771
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2480096953
Short name T1732
Test name
Test status
Simulation time 212753099 ps
CPU time 0.94 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:07 PM PDT 24
Peak memory 206764 kb
Host smart-a1641dac-c025-4a57-a08f-19b8ecc53b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24800
96953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2480096953
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3729342714
Short name T104
Test name
Test status
Simulation time 204145032 ps
CPU time 0.85 seconds
Started Jul 15 07:04:04 PM PDT 24
Finished Jul 15 07:04:05 PM PDT 24
Peak memory 206700 kb
Host smart-b2c226be-49d1-4258-8f37-1b70bbb2ba66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37293
42714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3729342714
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3261460244
Short name T444
Test name
Test status
Simulation time 200831755 ps
CPU time 0.86 seconds
Started Jul 15 07:04:06 PM PDT 24
Finished Jul 15 07:04:08 PM PDT 24
Peak memory 206824 kb
Host smart-80178b0e-0b7a-4cfb-868c-05a17f46c57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
60244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3261460244
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.353999152
Short name T2735
Test name
Test status
Simulation time 9257445775 ps
CPU time 262.56 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:08:29 PM PDT 24
Peak memory 207076 kb
Host smart-69b70bd8-593c-468e-8741-2352dbeced37
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=353999152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.353999152
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.2215893491
Short name T1529
Test name
Test status
Simulation time 5032685107 ps
CPU time 44.03 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:50 PM PDT 24
Peak memory 207088 kb
Host smart-6bcd5f31-5456-48df-8dfd-e88c61f4fb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22158
93491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2215893491
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.244895879
Short name T924
Test name
Test status
Simulation time 201350540 ps
CPU time 0.85 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:07 PM PDT 24
Peak memory 206760 kb
Host smart-2340094b-6385-4c71-a759-50cec5641536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24489
5879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.244895879
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3502886698
Short name T1975
Test name
Test status
Simulation time 23332147293 ps
CPU time 22.5 seconds
Started Jul 15 07:04:06 PM PDT 24
Finished Jul 15 07:04:29 PM PDT 24
Peak memory 206836 kb
Host smart-63050d52-e0a8-4e54-b480-abe00efcfdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35028
86698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3502886698
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3694652493
Short name T2400
Test name
Test status
Simulation time 3383768051 ps
CPU time 3.56 seconds
Started Jul 15 07:04:05 PM PDT 24
Finished Jul 15 07:04:10 PM PDT 24
Peak memory 206816 kb
Host smart-60616d74-2016-481d-a3ca-982802af7fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36946
52493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3694652493
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3751521062
Short name T1885
Test name
Test status
Simulation time 10117107837 ps
CPU time 280.36 seconds
Started Jul 15 07:04:11 PM PDT 24
Finished Jul 15 07:08:52 PM PDT 24
Peak memory 207128 kb
Host smart-10bb282a-c18b-472d-90dc-2f55590ed87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37515
21062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3751521062
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.782830884
Short name T1887
Test name
Test status
Simulation time 2930184459 ps
CPU time 20.88 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:35 PM PDT 24
Peak memory 207088 kb
Host smart-28228ce5-df76-47de-b9ad-b7eaf8f7921b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=782830884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.782830884
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.3904884167
Short name T694
Test name
Test status
Simulation time 262467515 ps
CPU time 0.93 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:15 PM PDT 24
Peak memory 206812 kb
Host smart-8b83ce74-3063-4e89-87cc-5d0a81900a35
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3904884167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3904884167
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2103046239
Short name T1367
Test name
Test status
Simulation time 200286592 ps
CPU time 0.94 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206788 kb
Host smart-1a4b625c-f86a-404c-b462-30b26205d8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030
46239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2103046239
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2014975058
Short name T2027
Test name
Test status
Simulation time 5754281767 ps
CPU time 53.56 seconds
Started Jul 15 07:04:11 PM PDT 24
Finished Jul 15 07:05:05 PM PDT 24
Peak memory 207040 kb
Host smart-43f449a5-9587-4328-b175-1bc9350a5df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20149
75058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2014975058
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1323710673
Short name T534
Test name
Test status
Simulation time 5965485305 ps
CPU time 163.34 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:06:57 PM PDT 24
Peak memory 207028 kb
Host smart-7e23ad9a-e281-40f8-9366-74bb5b6a2db3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1323710673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1323710673
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2679479052
Short name T923
Test name
Test status
Simulation time 166451594 ps
CPU time 0.78 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206788 kb
Host smart-f5e6aabb-8c67-4125-b944-46e103e1f31d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2679479052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2679479052
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3972324648
Short name T1813
Test name
Test status
Simulation time 165443943 ps
CPU time 0.84 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:15 PM PDT 24
Peak memory 206828 kb
Host smart-7357a35d-e653-47bb-a2ee-f385abcecb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39723
24648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3972324648
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3745230412
Short name T117
Test name
Test status
Simulation time 214475321 ps
CPU time 1.01 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:04:13 PM PDT 24
Peak memory 206820 kb
Host smart-3eacd48a-8974-4613-a080-06d3bcf56e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37452
30412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3745230412
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2252388113
Short name T580
Test name
Test status
Simulation time 162468580 ps
CPU time 0.78 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206808 kb
Host smart-1b0d4321-95e5-46d2-b960-b21053289eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22523
88113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2252388113
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.317437659
Short name T679
Test name
Test status
Simulation time 165619751 ps
CPU time 0.82 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:04:13 PM PDT 24
Peak memory 206848 kb
Host smart-eacc766c-b107-4872-a15d-08d31f545176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743
7659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.317437659
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1855462818
Short name T78
Test name
Test status
Simulation time 149717200 ps
CPU time 0.75 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:04:13 PM PDT 24
Peak memory 206816 kb
Host smart-430766e4-7000-4d2f-a903-15c5105cc31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
62818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1855462818
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.85898282
Short name T2335
Test name
Test status
Simulation time 242261813 ps
CPU time 0.96 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:15 PM PDT 24
Peak memory 206788 kb
Host smart-d4dab43d-ae23-4750-b1cf-0cf90ec38b01
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=85898282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.85898282
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1864083617
Short name T560
Test name
Test status
Simulation time 145513638 ps
CPU time 0.77 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206816 kb
Host smart-95b37755-22a7-44a8-b75e-7d2d2f7a609d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18640
83617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1864083617
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3604668981
Short name T1513
Test name
Test status
Simulation time 45964506 ps
CPU time 0.69 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206816 kb
Host smart-b7b27d37-2c2c-4c0d-aee6-94f5792e9838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36046
68981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3604668981
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2911758451
Short name T1140
Test name
Test status
Simulation time 21081956567 ps
CPU time 46.25 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:04:58 PM PDT 24
Peak memory 215280 kb
Host smart-1e265073-2f31-46c3-ac55-6c0fa2cc1475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29117
58451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2911758451
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3224675097
Short name T343
Test name
Test status
Simulation time 237904294 ps
CPU time 0.94 seconds
Started Jul 15 07:04:14 PM PDT 24
Finished Jul 15 07:04:16 PM PDT 24
Peak memory 206816 kb
Host smart-fa31ba5e-76e3-4828-8311-d43062bb65fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32246
75097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3224675097
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2054971678
Short name T142
Test name
Test status
Simulation time 270392101 ps
CPU time 0.99 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206836 kb
Host smart-04c35d37-ea74-414b-95eb-1bf21f1a0fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20549
71678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2054971678
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3884904762
Short name T146
Test name
Test status
Simulation time 13461976364 ps
CPU time 94.58 seconds
Started Jul 15 07:04:11 PM PDT 24
Finished Jul 15 07:05:46 PM PDT 24
Peak memory 207028 kb
Host smart-3f325be4-538b-4839-bc9a-c945ad0594bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3884904762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3884904762
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.4197516294
Short name T160
Test name
Test status
Simulation time 10338497781 ps
CPU time 259.68 seconds
Started Jul 15 07:04:10 PM PDT 24
Finished Jul 15 07:08:30 PM PDT 24
Peak memory 207092 kb
Host smart-21f62dc9-eec5-4187-a905-7a5db98ef901
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4197516294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.4197516294
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.956651461
Short name T1762
Test name
Test status
Simulation time 23698882903 ps
CPU time 559.98 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:13:32 PM PDT 24
Peak memory 206972 kb
Host smart-a58f18e6-0fb2-48f4-bce7-efdfd5050e6b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=956651461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.956651461
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.2022996040
Short name T2168
Test name
Test status
Simulation time 177409559 ps
CPU time 0.81 seconds
Started Jul 15 07:04:15 PM PDT 24
Finished Jul 15 07:04:16 PM PDT 24
Peak memory 206812 kb
Host smart-62972d39-1882-4897-ac4d-25859ece5180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20229
96040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2022996040
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2544617664
Short name T2224
Test name
Test status
Simulation time 144625881 ps
CPU time 0.77 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:04:13 PM PDT 24
Peak memory 206840 kb
Host smart-7d0c4236-5114-4ba7-bbbe-a9fd3a577eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
17664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2544617664
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.972320235
Short name T295
Test name
Test status
Simulation time 161978293 ps
CPU time 0.85 seconds
Started Jul 15 07:04:13 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206800 kb
Host smart-cf0cfe23-c82e-4a80-bc15-60690c6f84e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97232
0235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.972320235
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1532426798
Short name T749
Test name
Test status
Simulation time 230585741 ps
CPU time 0.84 seconds
Started Jul 15 07:04:14 PM PDT 24
Finished Jul 15 07:04:16 PM PDT 24
Peak memory 206808 kb
Host smart-b836f492-f326-426c-b2e5-7da75e28c57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15324
26798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1532426798
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2836753116
Short name T609
Test name
Test status
Simulation time 171590751 ps
CPU time 0.88 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206788 kb
Host smart-1f546295-4da3-4cd5-89e1-c7bda86ab7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28367
53116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2836753116
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.574084406
Short name T2322
Test name
Test status
Simulation time 183787595 ps
CPU time 0.84 seconds
Started Jul 15 07:04:12 PM PDT 24
Finished Jul 15 07:04:14 PM PDT 24
Peak memory 206816 kb
Host smart-287dca26-251d-4b6e-ad3f-db54b9fcb08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57408
4406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.574084406
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.577066371
Short name T2427
Test name
Test status
Simulation time 6930412509 ps
CPU time 49.91 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:05:09 PM PDT 24
Peak memory 206956 kb
Host smart-d923cac2-044c-4c0f-a7c5-063bf44aaa47
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=577066371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.577066371
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.696917948
Short name T2430
Test name
Test status
Simulation time 166242613 ps
CPU time 0.78 seconds
Started Jul 15 07:04:19 PM PDT 24
Finished Jul 15 07:04:20 PM PDT 24
Peak memory 206836 kb
Host smart-9d4fcd30-e73b-446e-b941-d17f9cae6c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69691
7948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.696917948
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3002497887
Short name T2689
Test name
Test status
Simulation time 155194665 ps
CPU time 0.84 seconds
Started Jul 15 07:04:16 PM PDT 24
Finished Jul 15 07:04:18 PM PDT 24
Peak memory 206788 kb
Host smart-e0070cf2-6a6d-4a32-990e-b282bcae4c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30024
97887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3002497887
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3568419291
Short name T1093
Test name
Test status
Simulation time 721191270 ps
CPU time 1.61 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:20 PM PDT 24
Peak memory 206808 kb
Host smart-6ecf1f61-0b17-40a8-8301-f6569267f520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35684
19291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3568419291
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.47576170
Short name T1321
Test name
Test status
Simulation time 4575938370 ps
CPU time 43.47 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:05:03 PM PDT 24
Peak memory 207080 kb
Host smart-e1e6c274-3503-416c-8e1c-a51d6d68fd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47576
170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.47576170
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2016561721
Short name T1004
Test name
Test status
Simulation time 44070570 ps
CPU time 0.7 seconds
Started Jul 15 07:04:25 PM PDT 24
Finished Jul 15 07:04:26 PM PDT 24
Peak memory 206864 kb
Host smart-9f97ed74-5103-42e9-a357-761da67f427f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2016561721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2016561721
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3283173702
Short name T1430
Test name
Test status
Simulation time 3735508799 ps
CPU time 4.02 seconds
Started Jul 15 07:04:19 PM PDT 24
Finished Jul 15 07:04:24 PM PDT 24
Peak memory 206960 kb
Host smart-fe0c0286-0a28-4f4c-9994-195c6fe7a53a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3283173702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3283173702
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2062669550
Short name T695
Test name
Test status
Simulation time 13296819295 ps
CPU time 12.16 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 207060 kb
Host smart-ab98479a-8825-4914-a4a3-9743b1c1ea52
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2062669550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2062669550
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2508275027
Short name T1105
Test name
Test status
Simulation time 23321203961 ps
CPU time 29.68 seconds
Started Jul 15 07:04:17 PM PDT 24
Finished Jul 15 07:04:47 PM PDT 24
Peak memory 206884 kb
Host smart-c50f092e-7488-49c2-8ee6-6d0a9737e688
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2508275027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2508275027
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1818401287
Short name T439
Test name
Test status
Simulation time 185855891 ps
CPU time 0.82 seconds
Started Jul 15 07:04:17 PM PDT 24
Finished Jul 15 07:04:19 PM PDT 24
Peak memory 206824 kb
Host smart-59e48792-e393-4328-b13d-7a3a012ee293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18184
01287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1818401287
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.478692782
Short name T1070
Test name
Test status
Simulation time 142016548 ps
CPU time 0.74 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:19 PM PDT 24
Peak memory 206792 kb
Host smart-ff5303c6-b095-4be1-b195-72c6e242be99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47869
2782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.478692782
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2881985908
Short name T809
Test name
Test status
Simulation time 244083637 ps
CPU time 0.96 seconds
Started Jul 15 07:04:24 PM PDT 24
Finished Jul 15 07:04:26 PM PDT 24
Peak memory 206800 kb
Host smart-1e028984-9759-4f96-bbc9-8ab277312a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28819
85908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2881985908
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2160984674
Short name T1544
Test name
Test status
Simulation time 938589623 ps
CPU time 2.27 seconds
Started Jul 15 07:04:17 PM PDT 24
Finished Jul 15 07:04:20 PM PDT 24
Peak memory 207020 kb
Host smart-ae05ac47-147b-487f-a400-21ec4a124965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
84674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2160984674
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.4230719229
Short name T1237
Test name
Test status
Simulation time 11816864400 ps
CPU time 23.68 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:43 PM PDT 24
Peak memory 207060 kb
Host smart-aab0d69d-305e-4c62-8706-42103904aa31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
19229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.4230719229
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.4293659913
Short name T1905
Test name
Test status
Simulation time 315736528 ps
CPU time 1.05 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:20 PM PDT 24
Peak memory 206792 kb
Host smart-17c5ee93-977f-401c-8b2f-1ef658525c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936
59913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.4293659913
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2047893302
Short name T451
Test name
Test status
Simulation time 144653874 ps
CPU time 0.77 seconds
Started Jul 15 07:04:20 PM PDT 24
Finished Jul 15 07:04:22 PM PDT 24
Peak memory 206824 kb
Host smart-b090b287-b006-49a2-b9d7-e1956979f266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20478
93302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2047893302
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.1582238646
Short name T1503
Test name
Test status
Simulation time 59376314 ps
CPU time 0.73 seconds
Started Jul 15 07:04:20 PM PDT 24
Finished Jul 15 07:04:21 PM PDT 24
Peak memory 206804 kb
Host smart-248decb7-4477-473f-a350-d91a1c8a9192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15822
38646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1582238646
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3852494496
Short name T2279
Test name
Test status
Simulation time 866467046 ps
CPU time 2.21 seconds
Started Jul 15 07:04:24 PM PDT 24
Finished Jul 15 07:04:27 PM PDT 24
Peak memory 207012 kb
Host smart-09136f18-d775-42f5-947b-ba7dceba94e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38524
94496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3852494496
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.52085559
Short name T890
Test name
Test status
Simulation time 185284163 ps
CPU time 1.68 seconds
Started Jul 15 07:04:21 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 206984 kb
Host smart-b6219143-08d4-42d6-9d62-7406d792b483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52085
559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.52085559
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.457128789
Short name T1468
Test name
Test status
Simulation time 221104095 ps
CPU time 0.88 seconds
Started Jul 15 07:04:22 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 206824 kb
Host smart-6141878c-5022-49a8-80ef-b9ccc701091a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45712
8789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.457128789
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2512765061
Short name T1171
Test name
Test status
Simulation time 137322734 ps
CPU time 0.75 seconds
Started Jul 15 07:04:20 PM PDT 24
Finished Jul 15 07:04:21 PM PDT 24
Peak memory 206796 kb
Host smart-3a14c52d-6378-4844-b126-0948cb17020b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25127
65061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2512765061
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1376258939
Short name T1485
Test name
Test status
Simulation time 201586179 ps
CPU time 0.89 seconds
Started Jul 15 07:04:21 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 206800 kb
Host smart-7a914af6-9587-4e61-ae4b-e40d7d3afbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13762
58939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1376258939
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.948651236
Short name T1141
Test name
Test status
Simulation time 8589660612 ps
CPU time 247.41 seconds
Started Jul 15 07:04:20 PM PDT 24
Finished Jul 15 07:08:28 PM PDT 24
Peak memory 207032 kb
Host smart-6e4d527e-4261-45f2-aaed-b70cca8dd653
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=948651236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.948651236
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.3852308253
Short name T445
Test name
Test status
Simulation time 12057673977 ps
CPU time 49.74 seconds
Started Jul 15 07:04:17 PM PDT 24
Finished Jul 15 07:05:08 PM PDT 24
Peak memory 207032 kb
Host smart-258367d4-436a-4cc4-a382-9938dcae4e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
08253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.3852308253
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.4038117014
Short name T365
Test name
Test status
Simulation time 173023621 ps
CPU time 0.81 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:19 PM PDT 24
Peak memory 206832 kb
Host smart-8f001066-d267-4083-9640-0f34f6919fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40381
17014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.4038117014
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.1217626063
Short name T1616
Test name
Test status
Simulation time 23330881831 ps
CPU time 24.49 seconds
Started Jul 15 07:04:24 PM PDT 24
Finished Jul 15 07:04:49 PM PDT 24
Peak memory 206864 kb
Host smart-f092d059-7445-4051-84ae-68ebb244f8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12176
26063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.1217626063
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.319125627
Short name T919
Test name
Test status
Simulation time 3262920744 ps
CPU time 4.46 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:24 PM PDT 24
Peak memory 206876 kb
Host smart-6786b37b-9208-4596-bd99-ef0f70207406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31912
5627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.319125627
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2193304628
Short name T722
Test name
Test status
Simulation time 8397802026 ps
CPU time 232.18 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:08:11 PM PDT 24
Peak memory 207084 kb
Host smart-d2ae877b-67e3-4776-a56f-4d0a7ce294dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21933
04628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2193304628
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4236280711
Short name T2378
Test name
Test status
Simulation time 5464536410 ps
CPU time 152.87 seconds
Started Jul 15 07:04:20 PM PDT 24
Finished Jul 15 07:06:54 PM PDT 24
Peak memory 207008 kb
Host smart-aa454b21-6031-42b9-a0a3-d14348fe6ac9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4236280711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4236280711
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1407247084
Short name T328
Test name
Test status
Simulation time 262946682 ps
CPU time 0.93 seconds
Started Jul 15 07:04:18 PM PDT 24
Finished Jul 15 07:04:20 PM PDT 24
Peak memory 206792 kb
Host smart-93e81aec-b929-4915-9794-db8fa22546f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1407247084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1407247084
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3352297222
Short name T2201
Test name
Test status
Simulation time 187489389 ps
CPU time 0.84 seconds
Started Jul 15 07:04:20 PM PDT 24
Finished Jul 15 07:04:22 PM PDT 24
Peak memory 206800 kb
Host smart-c1759211-0ec3-4ff8-b57f-316e6b8a4b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33522
97222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3352297222
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.4009466423
Short name T1115
Test name
Test status
Simulation time 6143656573 ps
CPU time 61.2 seconds
Started Jul 15 07:04:17 PM PDT 24
Finished Jul 15 07:05:19 PM PDT 24
Peak memory 207056 kb
Host smart-6f91e266-4dce-4d0c-9f6e-28a4220892f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40094
66423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.4009466423
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.4253799927
Short name T537
Test name
Test status
Simulation time 3006877898 ps
CPU time 81.76 seconds
Started Jul 15 07:04:22 PM PDT 24
Finished Jul 15 07:05:44 PM PDT 24
Peak memory 206980 kb
Host smart-e85cc51d-1c7f-413c-9477-859d402ae0fb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4253799927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.4253799927
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3745845328
Short name T538
Test name
Test status
Simulation time 161769458 ps
CPU time 0.8 seconds
Started Jul 15 07:04:17 PM PDT 24
Finished Jul 15 07:04:18 PM PDT 24
Peak memory 206744 kb
Host smart-9f9eb487-660d-4e82-9c4b-2e2c23cb131a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3745845328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3745845328
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3932020236
Short name T1870
Test name
Test status
Simulation time 158130640 ps
CPU time 0.75 seconds
Started Jul 15 07:04:17 PM PDT 24
Finished Jul 15 07:04:18 PM PDT 24
Peak memory 206808 kb
Host smart-5141ccc2-9ab8-4da4-b0f9-94fa78b860e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39320
20236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3932020236
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2954027473
Short name T2471
Test name
Test status
Simulation time 221998277 ps
CPU time 0.88 seconds
Started Jul 15 07:04:21 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 206784 kb
Host smart-d8529f03-a371-4c64-a7c2-7db1ff9de3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29540
27473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2954027473
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1339880753
Short name T1415
Test name
Test status
Simulation time 168848715 ps
CPU time 0.83 seconds
Started Jul 15 07:04:20 PM PDT 24
Finished Jul 15 07:04:22 PM PDT 24
Peak memory 206824 kb
Host smart-ffc00624-55b1-47e2-b954-fbfd0366bc7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13398
80753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1339880753
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.4284580302
Short name T1884
Test name
Test status
Simulation time 196878770 ps
CPU time 0.81 seconds
Started Jul 15 07:04:16 PM PDT 24
Finished Jul 15 07:04:17 PM PDT 24
Peak memory 206796 kb
Host smart-948e6441-e045-4bb0-a254-4914d6f57d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42845
80302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.4284580302
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3196164094
Short name T2619
Test name
Test status
Simulation time 157009436 ps
CPU time 0.81 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:04:25 PM PDT 24
Peak memory 206800 kb
Host smart-19786585-8898-4516-aba0-bcd3dc4ce3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31961
64094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3196164094
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.71816303
Short name T648
Test name
Test status
Simulation time 148126017 ps
CPU time 0.83 seconds
Started Jul 15 07:04:21 PM PDT 24
Finished Jul 15 07:04:22 PM PDT 24
Peak memory 206772 kb
Host smart-76acc70d-ee04-4f4d-a1ac-a83d8e3523b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71816
303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.71816303
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.153063444
Short name T2156
Test name
Test status
Simulation time 226895263 ps
CPU time 0.94 seconds
Started Jul 15 07:04:22 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 206820 kb
Host smart-97ed8ad4-0b0f-4c36-a875-9a9bb7bf162b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=153063444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.153063444
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.159314826
Short name T1772
Test name
Test status
Simulation time 223725225 ps
CPU time 0.82 seconds
Started Jul 15 07:04:20 PM PDT 24
Finished Jul 15 07:04:21 PM PDT 24
Peak memory 206844 kb
Host smart-f3d769cb-4c6d-48be-875e-a4c2a203f79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15931
4826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.159314826
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1256812158
Short name T1484
Test name
Test status
Simulation time 43511807 ps
CPU time 0.67 seconds
Started Jul 15 07:04:28 PM PDT 24
Finished Jul 15 07:04:29 PM PDT 24
Peak memory 206812 kb
Host smart-177b84d3-136f-4d77-a299-66360ee10dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12568
12158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1256812158
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.866504054
Short name T1804
Test name
Test status
Simulation time 13516456095 ps
CPU time 29.61 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:04:53 PM PDT 24
Peak memory 207104 kb
Host smart-0d48f377-9847-4e00-b1f2-bc82f2d8a053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86650
4054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.866504054
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1258276915
Short name T27
Test name
Test status
Simulation time 183857378 ps
CPU time 0.87 seconds
Started Jul 15 07:04:25 PM PDT 24
Finished Jul 15 07:04:27 PM PDT 24
Peak memory 206816 kb
Host smart-d61e6048-feff-43e6-b8b8-236a8543292d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
76915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1258276915
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1910859554
Short name T752
Test name
Test status
Simulation time 241209272 ps
CPU time 0.88 seconds
Started Jul 15 07:04:22 PM PDT 24
Finished Jul 15 07:04:24 PM PDT 24
Peak memory 206820 kb
Host smart-86f52f45-2dd1-4a34-96eb-75bf460f4d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108
59554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1910859554
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2099337694
Short name T2463
Test name
Test status
Simulation time 4354311853 ps
CPU time 29.2 seconds
Started Jul 15 07:04:24 PM PDT 24
Finished Jul 15 07:04:54 PM PDT 24
Peak memory 207024 kb
Host smart-24fb54e4-bbe0-4360-8dac-4fedca51aaf4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2099337694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2099337694
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3281862135
Short name T957
Test name
Test status
Simulation time 11528413698 ps
CPU time 228.91 seconds
Started Jul 15 07:04:24 PM PDT 24
Finished Jul 15 07:08:14 PM PDT 24
Peak memory 207028 kb
Host smart-b2816b56-a91c-4218-a792-fa1266f34365
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3281862135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3281862135
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.4146461227
Short name T1240
Test name
Test status
Simulation time 13573542363 ps
CPU time 74.46 seconds
Started Jul 15 07:04:28 PM PDT 24
Finished Jul 15 07:05:42 PM PDT 24
Peak memory 207100 kb
Host smart-5ed5c091-49bc-434d-8f5f-b4037a46c92a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4146461227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.4146461227
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.336359187
Short name T1778
Test name
Test status
Simulation time 245703649 ps
CPU time 0.93 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:04:24 PM PDT 24
Peak memory 206840 kb
Host smart-41d89d8d-b3e0-4116-b260-80a883bcb92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33635
9187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.336359187
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3549970853
Short name T2479
Test name
Test status
Simulation time 181786034 ps
CPU time 0.86 seconds
Started Jul 15 07:04:22 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 206844 kb
Host smart-b01b2e6c-a65a-4ac6-8b26-a07300e04c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35499
70853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3549970853
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2081558963
Short name T1272
Test name
Test status
Simulation time 168201979 ps
CPU time 0.76 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:04:25 PM PDT 24
Peak memory 206792 kb
Host smart-8c7ec894-f8a3-4285-bab0-2cb2ab9f7c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20815
58963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2081558963
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3054544426
Short name T977
Test name
Test status
Simulation time 158359078 ps
CPU time 0.81 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:04:25 PM PDT 24
Peak memory 206808 kb
Host smart-df80b279-6ad9-4e9e-90cb-c04024fac91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30545
44426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3054544426
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2358791518
Short name T361
Test name
Test status
Simulation time 149289010 ps
CPU time 0.83 seconds
Started Jul 15 07:04:22 PM PDT 24
Finished Jul 15 07:04:24 PM PDT 24
Peak memory 206820 kb
Host smart-3a13cda1-1eec-4281-b343-29f34e224389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23587
91518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2358791518
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1816053480
Short name T426
Test name
Test status
Simulation time 229928895 ps
CPU time 0.91 seconds
Started Jul 15 07:04:21 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 206700 kb
Host smart-3484690a-affe-4962-ba5b-b194e56eb2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160
53480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1816053480
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3667797083
Short name T2714
Test name
Test status
Simulation time 3271089785 ps
CPU time 87.52 seconds
Started Jul 15 07:04:24 PM PDT 24
Finished Jul 15 07:05:52 PM PDT 24
Peak memory 207020 kb
Host smart-8f70addd-9cd1-4eff-b64d-73326727b570
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3667797083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3667797083
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3761500002
Short name T647
Test name
Test status
Simulation time 145498810 ps
CPU time 0.82 seconds
Started Jul 15 07:04:26 PM PDT 24
Finished Jul 15 07:04:27 PM PDT 24
Peak memory 206816 kb
Host smart-6ae11e5a-3442-41b1-a0d1-eceb2088e15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
00002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3761500002
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.346617438
Short name T1487
Test name
Test status
Simulation time 182639034 ps
CPU time 0.83 seconds
Started Jul 15 07:04:21 PM PDT 24
Finished Jul 15 07:04:23 PM PDT 24
Peak memory 206780 kb
Host smart-ea54ebb8-ee72-4477-9746-ae3c51470ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34661
7438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.346617438
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.4163476351
Short name T201
Test name
Test status
Simulation time 836830588 ps
CPU time 1.98 seconds
Started Jul 15 07:04:28 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 206992 kb
Host smart-84829328-868b-43f4-b494-99aa5b0425f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41634
76351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.4163476351
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2974175145
Short name T1327
Test name
Test status
Simulation time 4367972780 ps
CPU time 119.83 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:06:24 PM PDT 24
Peak memory 207040 kb
Host smart-7cde7c65-9898-4934-bb44-a293783a33d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29741
75145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2974175145
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.3040996912
Short name T171
Test name
Test status
Simulation time 51535147 ps
CPU time 0.69 seconds
Started Jul 15 07:04:38 PM PDT 24
Finished Jul 15 07:04:39 PM PDT 24
Peak memory 206884 kb
Host smart-b46373ae-fd3e-459a-b508-5878f0dd4dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3040996912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.3040996912
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1966390490
Short name T1325
Test name
Test status
Simulation time 3805725278 ps
CPU time 4.04 seconds
Started Jul 15 07:04:25 PM PDT 24
Finished Jul 15 07:04:30 PM PDT 24
Peak memory 207004 kb
Host smart-a0023467-1abc-4a8d-ac6d-87b427c45e44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1966390490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1966390490
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1813398117
Short name T2111
Test name
Test status
Simulation time 13396927583 ps
CPU time 15.37 seconds
Started Jul 15 07:04:22 PM PDT 24
Finished Jul 15 07:04:38 PM PDT 24
Peak memory 206864 kb
Host smart-1df3ee03-ddf5-4bbf-9f13-0393e500de5c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1813398117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1813398117
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.341334270
Short name T1011
Test name
Test status
Simulation time 23353949683 ps
CPU time 22.91 seconds
Started Jul 15 07:04:24 PM PDT 24
Finished Jul 15 07:04:47 PM PDT 24
Peak memory 207004 kb
Host smart-bde30c58-fad9-458c-a208-ff2e40c55a32
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=341334270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.341334270
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3647965916
Short name T1566
Test name
Test status
Simulation time 232760561 ps
CPU time 0.85 seconds
Started Jul 15 07:04:24 PM PDT 24
Finished Jul 15 07:04:26 PM PDT 24
Peak memory 206792 kb
Host smart-b811642a-d625-4e23-b3de-7175b2e638bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36479
65916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3647965916
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3790403027
Short name T54
Test name
Test status
Simulation time 158467237 ps
CPU time 0.79 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:04:25 PM PDT 24
Peak memory 206788 kb
Host smart-d294d38e-7be4-45ca-a627-8b3478b778fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37904
03027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3790403027
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.1052165300
Short name T1452
Test name
Test status
Simulation time 443155420 ps
CPU time 1.41 seconds
Started Jul 15 07:04:25 PM PDT 24
Finished Jul 15 07:04:27 PM PDT 24
Peak memory 206816 kb
Host smart-29688850-0249-478e-a719-1e5aefbcf43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10521
65300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.1052165300
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1161374707
Short name T1521
Test name
Test status
Simulation time 944060192 ps
CPU time 2.19 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:04:26 PM PDT 24
Peak memory 206980 kb
Host smart-5942f48e-707e-49db-bcca-2b42dd1c34ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11613
74707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1161374707
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3250626655
Short name T950
Test name
Test status
Simulation time 22758770699 ps
CPU time 37.97 seconds
Started Jul 15 07:04:22 PM PDT 24
Finished Jul 15 07:05:00 PM PDT 24
Peak memory 207032 kb
Host smart-1a2873c9-2994-442e-a76a-cbf8657cc777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32506
26655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3250626655
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.454741309
Short name T2192
Test name
Test status
Simulation time 406313344 ps
CPU time 1.26 seconds
Started Jul 15 07:04:23 PM PDT 24
Finished Jul 15 07:04:25 PM PDT 24
Peak memory 206812 kb
Host smart-e3e758f4-2165-4d9d-8096-2fbe368f564d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45474
1309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.454741309
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2670922549
Short name T656
Test name
Test status
Simulation time 151192038 ps
CPU time 0.8 seconds
Started Jul 15 07:04:30 PM PDT 24
Finished Jul 15 07:04:31 PM PDT 24
Peak memory 206832 kb
Host smart-3697cc74-f5e0-46f7-8aee-6db524b0fa89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709
22549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2670922549
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2991468742
Short name T1494
Test name
Test status
Simulation time 37585573 ps
CPU time 0.69 seconds
Started Jul 15 07:04:31 PM PDT 24
Finished Jul 15 07:04:33 PM PDT 24
Peak memory 206804 kb
Host smart-d8943e0d-3c8d-4dd2-9568-0a86e07cf52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29914
68742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2991468742
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1213989300
Short name T2055
Test name
Test status
Simulation time 836093548 ps
CPU time 1.94 seconds
Started Jul 15 07:04:31 PM PDT 24
Finished Jul 15 07:04:33 PM PDT 24
Peak memory 206948 kb
Host smart-7089a167-104e-47fe-b026-02b4c9ff5184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12139
89300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1213989300
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1879858933
Short name T1744
Test name
Test status
Simulation time 307437486 ps
CPU time 1.97 seconds
Started Jul 15 07:04:32 PM PDT 24
Finished Jul 15 07:04:35 PM PDT 24
Peak memory 206848 kb
Host smart-97001b7b-2413-47d2-b043-8feae8ed8bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798
58933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1879858933
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2088877197
Short name T405
Test name
Test status
Simulation time 204234063 ps
CPU time 0.88 seconds
Started Jul 15 07:04:33 PM PDT 24
Finished Jul 15 07:04:34 PM PDT 24
Peak memory 206812 kb
Host smart-9bf656dc-9137-41a4-9981-4779cb5a5b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20888
77197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2088877197
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1309286087
Short name T2048
Test name
Test status
Simulation time 150689256 ps
CPU time 0.77 seconds
Started Jul 15 07:04:29 PM PDT 24
Finished Jul 15 07:04:31 PM PDT 24
Peak memory 206820 kb
Host smart-ca634309-8b15-4bc9-89f2-5f0f34af8990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13092
86087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1309286087
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2350187386
Short name T771
Test name
Test status
Simulation time 195626437 ps
CPU time 0.92 seconds
Started Jul 15 07:04:32 PM PDT 24
Finished Jul 15 07:04:33 PM PDT 24
Peak memory 206824 kb
Host smart-a4942fbd-15d4-4a30-942c-8c9a1bcc20c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23501
87386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2350187386
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.1560222319
Short name T1997
Test name
Test status
Simulation time 4167870769 ps
CPU time 37.31 seconds
Started Jul 15 07:04:31 PM PDT 24
Finished Jul 15 07:05:09 PM PDT 24
Peak memory 206980 kb
Host smart-ff9167d7-d939-409d-a554-bc5132c97d87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1560222319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.1560222319
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.516879049
Short name T2692
Test name
Test status
Simulation time 4072548691 ps
CPU time 31.41 seconds
Started Jul 15 07:04:30 PM PDT 24
Finished Jul 15 07:05:02 PM PDT 24
Peak memory 207080 kb
Host smart-c39018d8-35b8-4098-8983-a4781e2e79c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51687
9049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.516879049
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1512861576
Short name T508
Test name
Test status
Simulation time 188675707 ps
CPU time 0.87 seconds
Started Jul 15 07:04:33 PM PDT 24
Finished Jul 15 07:04:34 PM PDT 24
Peak memory 206808 kb
Host smart-46dfdccc-d1d5-4c61-a184-02a071f9d1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15128
61576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1512861576
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1290253165
Short name T1496
Test name
Test status
Simulation time 23341559030 ps
CPU time 24.47 seconds
Started Jul 15 07:04:30 PM PDT 24
Finished Jul 15 07:04:55 PM PDT 24
Peak memory 206896 kb
Host smart-947ec585-4129-451a-b202-05e516f26016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12902
53165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1290253165
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1522069405
Short name T1050
Test name
Test status
Simulation time 3342787052 ps
CPU time 4.64 seconds
Started Jul 15 07:04:33 PM PDT 24
Finished Jul 15 07:04:38 PM PDT 24
Peak memory 206880 kb
Host smart-f0d92045-8b32-43db-8442-1c03e67df657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15220
69405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1522069405
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2867351542
Short name T805
Test name
Test status
Simulation time 12115010664 ps
CPU time 113.92 seconds
Started Jul 15 07:04:35 PM PDT 24
Finished Jul 15 07:06:29 PM PDT 24
Peak memory 215320 kb
Host smart-74290960-c180-4eb4-a2c1-c0b322e02b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28673
51542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2867351542
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3246981445
Short name T1007
Test name
Test status
Simulation time 7010860690 ps
CPU time 200.23 seconds
Started Jul 15 07:04:30 PM PDT 24
Finished Jul 15 07:07:51 PM PDT 24
Peak memory 207076 kb
Host smart-b9137a19-fb70-448c-ac13-19886dd38c79
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3246981445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3246981445
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.994999458
Short name T1923
Test name
Test status
Simulation time 274470088 ps
CPU time 1.01 seconds
Started Jul 15 07:04:32 PM PDT 24
Finished Jul 15 07:04:34 PM PDT 24
Peak memory 206800 kb
Host smart-d78f59ee-f9e9-4f89-b154-4dda262f45aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=994999458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.994999458
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2781840384
Short name T2436
Test name
Test status
Simulation time 220993419 ps
CPU time 0.93 seconds
Started Jul 15 07:04:32 PM PDT 24
Finished Jul 15 07:04:34 PM PDT 24
Peak memory 206704 kb
Host smart-7e78ce51-3315-49f8-8c33-b587e47efd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27818
40384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2781840384
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2799302954
Short name T1500
Test name
Test status
Simulation time 6296800547 ps
CPU time 171.96 seconds
Started Jul 15 07:04:30 PM PDT 24
Finished Jul 15 07:07:23 PM PDT 24
Peak memory 207024 kb
Host smart-4f07bf90-50b8-4157-a534-8c1b9aa72748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27993
02954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2799302954
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2380972946
Short name T1146
Test name
Test status
Simulation time 3461989508 ps
CPU time 26.91 seconds
Started Jul 15 07:04:31 PM PDT 24
Finished Jul 15 07:04:58 PM PDT 24
Peak memory 207100 kb
Host smart-f5a2640a-dd0f-4679-ad25-0983ee9be607
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2380972946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2380972946
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2830071183
Short name T511
Test name
Test status
Simulation time 182445058 ps
CPU time 0.81 seconds
Started Jul 15 07:04:32 PM PDT 24
Finished Jul 15 07:04:33 PM PDT 24
Peak memory 206824 kb
Host smart-a339806b-89e9-497d-907f-afc3136711a8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2830071183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2830071183
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1073308807
Short name T1740
Test name
Test status
Simulation time 174475813 ps
CPU time 0.81 seconds
Started Jul 15 07:04:30 PM PDT 24
Finished Jul 15 07:04:31 PM PDT 24
Peak memory 206792 kb
Host smart-0e7acae8-c3e7-41ac-9475-0d4f4be7273a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10733
08807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1073308807
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.704936725
Short name T94
Test name
Test status
Simulation time 219130986 ps
CPU time 0.92 seconds
Started Jul 15 07:04:31 PM PDT 24
Finished Jul 15 07:04:33 PM PDT 24
Peak memory 206820 kb
Host smart-56665d0a-fcf4-48d3-9cd3-11ac1b5dbe17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70493
6725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.704936725
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2765197685
Short name T377
Test name
Test status
Simulation time 176862792 ps
CPU time 0.86 seconds
Started Jul 15 07:04:35 PM PDT 24
Finished Jul 15 07:04:36 PM PDT 24
Peak memory 206820 kb
Host smart-728e352f-3e3e-483f-93b0-604b98ac1bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651
97685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2765197685
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1451727823
Short name T1589
Test name
Test status
Simulation time 148897737 ps
CPU time 0.74 seconds
Started Jul 15 07:04:28 PM PDT 24
Finished Jul 15 07:04:29 PM PDT 24
Peak memory 206812 kb
Host smart-3d2ab1d8-e325-4191-995a-d2bd860fa5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14517
27823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1451727823
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3287538900
Short name T2424
Test name
Test status
Simulation time 182884241 ps
CPU time 0.82 seconds
Started Jul 15 07:04:30 PM PDT 24
Finished Jul 15 07:04:32 PM PDT 24
Peak memory 206820 kb
Host smart-db2fb8b2-61bd-45bf-a348-45ca205c73c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32875
38900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3287538900
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2286946226
Short name T1650
Test name
Test status
Simulation time 154993219 ps
CPU time 0.81 seconds
Started Jul 15 07:04:31 PM PDT 24
Finished Jul 15 07:04:33 PM PDT 24
Peak memory 206816 kb
Host smart-4f5b5eba-0ffd-41fc-8c4c-d00eb25c7310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869
46226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2286946226
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3236672259
Short name T2151
Test name
Test status
Simulation time 219158800 ps
CPU time 0.93 seconds
Started Jul 15 07:04:40 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 206824 kb
Host smart-99bfba9f-356c-470b-a809-ecf229609cf4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3236672259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3236672259
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3415651464
Short name T2431
Test name
Test status
Simulation time 154418410 ps
CPU time 0.77 seconds
Started Jul 15 07:04:43 PM PDT 24
Finished Jul 15 07:04:44 PM PDT 24
Peak memory 206824 kb
Host smart-fff348ac-168e-469a-8112-eb1e249f5cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34156
51464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3415651464
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.620652983
Short name T807
Test name
Test status
Simulation time 39815917 ps
CPU time 0.66 seconds
Started Jul 15 07:04:38 PM PDT 24
Finished Jul 15 07:04:40 PM PDT 24
Peak memory 206784 kb
Host smart-f6535475-28e2-4aa2-81d0-52add8b7f319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62065
2983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.620652983
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1124244179
Short name T83
Test name
Test status
Simulation time 22025401164 ps
CPU time 47.73 seconds
Started Jul 15 07:04:43 PM PDT 24
Finished Jul 15 07:05:31 PM PDT 24
Peak memory 207068 kb
Host smart-bb74a538-61a2-43ea-83b1-13e3b1b823de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11242
44179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1124244179
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2238696622
Short name T1268
Test name
Test status
Simulation time 167103468 ps
CPU time 0.8 seconds
Started Jul 15 07:04:39 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 206764 kb
Host smart-ea064e23-c879-4ff8-80fc-1cea531e04a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22386
96622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2238696622
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.751051387
Short name T1264
Test name
Test status
Simulation time 188894022 ps
CPU time 0.87 seconds
Started Jul 15 07:04:43 PM PDT 24
Finished Jul 15 07:04:44 PM PDT 24
Peak memory 206820 kb
Host smart-e79d94ea-70d7-4ffc-837a-28664dc301e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75105
1387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.751051387
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1808550767
Short name T157
Test name
Test status
Simulation time 7294504816 ps
CPU time 180.48 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:07:37 PM PDT 24
Peak memory 207036 kb
Host smart-8401690a-8b3d-4064-afc0-5af12e5a35ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1808550767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1808550767
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.580306334
Short name T1236
Test name
Test status
Simulation time 14050658956 ps
CPU time 92.82 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:06:11 PM PDT 24
Peak memory 207212 kb
Host smart-bd3b867c-61af-4bf1-a61e-bed8d6b757f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=580306334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.580306334
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3495171020
Short name T567
Test name
Test status
Simulation time 13081673253 ps
CPU time 89.18 seconds
Started Jul 15 07:04:38 PM PDT 24
Finished Jul 15 07:06:08 PM PDT 24
Peak memory 207016 kb
Host smart-d1138209-f8b3-475b-816d-16215014524f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3495171020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3495171020
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.4084273959
Short name T2376
Test name
Test status
Simulation time 190010711 ps
CPU time 0.92 seconds
Started Jul 15 07:04:36 PM PDT 24
Finished Jul 15 07:04:38 PM PDT 24
Peak memory 206800 kb
Host smart-1b50a5eb-290f-446c-892c-d04244f72033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40842
73959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.4084273959
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1993701030
Short name T1030
Test name
Test status
Simulation time 240383432 ps
CPU time 0.97 seconds
Started Jul 15 07:04:39 PM PDT 24
Finished Jul 15 07:04:40 PM PDT 24
Peak memory 206804 kb
Host smart-0a0b85cc-2bab-48a0-8bbc-38ab8bbad7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19937
01030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1993701030
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.750113782
Short name T66
Test name
Test status
Simulation time 230263741 ps
CPU time 0.85 seconds
Started Jul 15 07:04:39 PM PDT 24
Finished Jul 15 07:04:41 PM PDT 24
Peak memory 206824 kb
Host smart-53acb1c4-67e3-405b-928d-42526431e6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75011
3782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.750113782
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.292573612
Short name T1176
Test name
Test status
Simulation time 159935712 ps
CPU time 0.76 seconds
Started Jul 15 07:04:38 PM PDT 24
Finished Jul 15 07:04:39 PM PDT 24
Peak memory 206768 kb
Host smart-10cb5e43-32c4-453a-b5aa-e9c6349126bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29257
3612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.292573612
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.650737593
Short name T1476
Test name
Test status
Simulation time 217227979 ps
CPU time 0.82 seconds
Started Jul 15 07:04:36 PM PDT 24
Finished Jul 15 07:04:37 PM PDT 24
Peak memory 206816 kb
Host smart-27024366-ff5e-467a-9df2-23fae6c60159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65073
7593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.650737593
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1467101110
Short name T2493
Test name
Test status
Simulation time 207737394 ps
CPU time 0.92 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:04:39 PM PDT 24
Peak memory 206824 kb
Host smart-c169502b-5f18-4271-b975-62fb26dc3a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14671
01110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1467101110
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.149903798
Short name T2406
Test name
Test status
Simulation time 3584894526 ps
CPU time 33.88 seconds
Started Jul 15 07:04:39 PM PDT 24
Finished Jul 15 07:05:13 PM PDT 24
Peak memory 207000 kb
Host smart-6aeab7b4-a324-462a-899d-d2ccf711346f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=149903798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.149903798
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1736584803
Short name T1507
Test name
Test status
Simulation time 185856745 ps
CPU time 0.83 seconds
Started Jul 15 07:04:38 PM PDT 24
Finished Jul 15 07:04:39 PM PDT 24
Peak memory 206828 kb
Host smart-2fdbf228-ebd8-4cb7-a3b0-403792454028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17365
84803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1736584803
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2405133976
Short name T775
Test name
Test status
Simulation time 209207001 ps
CPU time 0.84 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:04:38 PM PDT 24
Peak memory 206824 kb
Host smart-cabe1dbe-745d-4c1e-a652-6ac0f366842a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24051
33976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2405133976
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.1957519125
Short name T696
Test name
Test status
Simulation time 206083285 ps
CPU time 0.9 seconds
Started Jul 15 07:04:36 PM PDT 24
Finished Jul 15 07:04:37 PM PDT 24
Peak memory 206760 kb
Host smart-23d4b18d-4bef-492b-bf20-d5dbed724135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19575
19125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.1957519125
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3856158017
Short name T1579
Test name
Test status
Simulation time 5259984763 ps
CPU time 36.49 seconds
Started Jul 15 07:04:37 PM PDT 24
Finished Jul 15 07:05:14 PM PDT 24
Peak memory 207020 kb
Host smart-c1f34e3a-4e1a-483a-b6f4-ce2b618bfb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38561
58017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3856158017
Directory /workspace/9.usbdev_streaming_out/latest
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