Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	81446	1		T1	2		T2	3		T3	2
all_values[1]	81446	1		T1	2		T2	3		T3	2
all_values[2]	81446	1		T1	2		T2	3		T3	2
all_values[3]	81446	1		T1	2		T2	3		T3	2
all_values[4]	81446	1		T1	2		T2	3		T3	2
all_values[5]	81446	1		T1	2		T2	3		T3	2
all_values[6]	81446	1		T1	2		T2	3		T3	2
all_values[7]	81446	1		T1	2		T2	3		T3	2
all_values[8]	81446	1		T1	2		T2	3		T3	2
all_values[9]	81446	1		T1	2		T2	3		T3	2
all_values[10]	81446	1		T1	2		T2	3		T3	2
all_values[11]	81446	1		T1	2		T2	3		T3	2
all_values[12]	81446	1		T1	2		T2	3		T3	2
all_values[13]	81446	1		T1	2		T2	3		T3	2
all_values[14]	81446	1		T1	2		T2	3		T3	2
all_values[15]	81446	1		T1	2		T2	3		T3	2
all_values[16]	81446	1		T1	2		T2	3		T3	2
all_values[17]	81446	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1459534	1		T1	36		T2	51		T3	36
auto[1]	6494	1		T2	3		T7	2		T17	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1461472	1		T1	36		T2	54		T3	36
auto[1]	4556	1		T198	66		T195	126		T200	74

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80495	1		T1	2		T3	2		T7	4
all_values[0]	auto[0]	auto[1]	136	1		T198	5		T195	5		T200	1
all_values[0]	auto[1]	auto[0]	692	1		T2	3		T19	3		T24	3
all_values[0]	auto[1]	auto[1]	123	1		T195	3		T200	4		T197	3
all_values[1]	auto[0]	auto[0]	79663	1		T1	2		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	130	1		T195	4		T200	1		T196	1
all_values[1]	auto[1]	auto[0]	1512	1		T7	2		T17	14		T22	14
all_values[1]	auto[1]	auto[1]	141	1		T198	5		T195	4		T200	4
all_values[2]	auto[0]	auto[0]	81072	1		T1	2		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	129	1		T198	4		T195	3		T196	1
all_values[2]	auto[1]	auto[0]	121	1		T42	2		T43	2		T44	2
all_values[2]	auto[1]	auto[1]	124	1		T198	1		T195	4		T200	5
all_values[3]	auto[0]	auto[0]	79755	1		T1	2		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	129	1		T195	6		T200	4		T196	4
all_values[3]	auto[1]	auto[0]	1436	1		T64	1407		T198	1		T268	3
all_values[3]	auto[1]	auto[1]	126	1		T198	4		T195	1		T200	1
all_values[4]	auto[0]	auto[0]	81171	1		T1	2		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	120	1		T196	2		T199	3		T197	5
all_values[4]	auto[1]	auto[0]	32	1		T65	2		T198	4		T195	1
all_values[4]	auto[1]	auto[1]	123	1		T195	6		T196	3		T199	1
all_values[5]	auto[0]	auto[0]	81174	1		T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	110	1		T198	1		T195	4		T196	3
all_values[5]	auto[1]	auto[0]	38	1		T195	1		T200	1		T196	1
all_values[5]	auto[1]	auto[1]	124	1		T198	3		T195	3		T196	1
all_values[6]	auto[0]	auto[0]	81159	1		T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	146	1		T198	2		T195	6		T200	1
all_values[6]	auto[1]	auto[0]	18	1		T197	1		T269	1		T270	1
all_values[6]	auto[1]	auto[1]	123	1		T198	3		T195	2		T200	4
all_values[7]	auto[0]	auto[0]	81153	1		T1	2		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	133	1		T198	4		T195	1		T200	2
all_values[7]	auto[1]	auto[0]	37	1		T49	2		T50	2		T51	2
all_values[7]	auto[1]	auto[1]	123	1		T195	4		T200	3		T196	4
all_values[8]	auto[0]	auto[0]	81167	1		T1	2		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	152	1		T198	3		T195	2		T199	4
all_values[8]	auto[1]	auto[0]	36	1		T53	11		T195	1		T196	1
all_values[8]	auto[1]	auto[1]	91	1		T195	4		T200	3		T196	3
all_values[9]	auto[0]	auto[0]	81151	1		T1	2		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	116	1		T198	2		T195	3		T200	3
all_values[9]	auto[1]	auto[0]	59	1		T61	5		T62	5		T63	5
all_values[9]	auto[1]	auto[1]	120	1		T198	3		T195	4		T200	1
all_values[10]	auto[0]	auto[0]	81154	1		T1	2		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	133	1		T198	4		T195	3		T200	1
all_values[10]	auto[1]	auto[0]	21	1		T195	2		T197	1		T271	5
all_values[10]	auto[1]	auto[1]	138	1		T200	4		T196	5		T197	4
all_values[11]	auto[0]	auto[0]	81070	1		T1	2		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	128	1		T198	1		T195	6		T196	4
all_values[11]	auto[1]	auto[0]	113	1		T47	2		T69	2		T70	2
all_values[11]	auto[1]	auto[1]	135	1		T198	4		T195	2		T200	5
all_values[12]	auto[0]	auto[0]	81165	1		T1	2		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	124	1		T195	4		T200	5		T196	1
all_values[12]	auto[1]	auto[0]	44	1		T74	3		T75	3		T76	3
all_values[12]	auto[1]	auto[1]	113	1		T195	4		T196	3		T199	4
all_values[13]	auto[0]	auto[0]	81183	1		T1	2		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	136	1		T198	4		T195	5		T196	4
all_values[13]	auto[1]	auto[0]	33	1		T198	1		T199	2		T268	1
all_values[13]	auto[1]	auto[1]	94	1		T195	3		T200	3		T197	6
all_values[14]	auto[0]	auto[0]	81166	1		T1	2		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	140	1		T198	2		T195	2		T200	2
all_values[14]	auto[1]	auto[0]	22	1		T196	1		T197	1		T272	1
all_values[14]	auto[1]	auto[1]	118	1		T198	3		T195	6		T200	3
all_values[15]	auto[0]	auto[0]	81168	1		T1	2		T2	3		T3	2
all_values[15]	auto[0]	auto[1]	142	1		T198	4		T195	5		T200	4
all_values[15]	auto[1]	auto[0]	18	1		T198	1		T200	1		T199	1
all_values[15]	auto[1]	auto[1]	118	1		T195	2		T196	1		T197	2
all_values[16]	auto[0]	auto[0]	81133	1		T1	2		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	140	1		T198	4		T195	2		T200	1
all_values[16]	auto[1]	auto[0]	41	1		T66	8		T67	8		T68	8
all_values[16]	auto[1]	auto[1]	132	1		T195	6		T200	4		T196	3
all_values[17]	auto[0]	auto[0]	81172	1		T1	2		T2	3		T3	2
all_values[17]	auto[0]	auto[1]	119	1		T195	6		T200	1		T197	5
all_values[17]	auto[1]	auto[0]	28	1		T198	3		T199	1		T273	1
all_values[17]	auto[1]	auto[1]	127	1		T195	1		T200	4		T196	3