Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	81446	1		T1	2		T2	3		T3	2
all_pins[1]	81446	1		T1	2		T2	3		T3	2
all_pins[2]	81446	1		T1	2		T2	3		T3	2
all_pins[3]	81446	1		T1	2		T2	3		T3	2
all_pins[4]	81446	1		T1	2		T2	3		T3	2
all_pins[5]	81446	1		T1	2		T2	3		T3	2
all_pins[6]	81446	1		T1	2		T2	3		T3	2
all_pins[7]	81446	1		T1	2		T2	3		T3	2
all_pins[8]	81446	1		T1	2		T2	3		T3	2
all_pins[9]	81446	1		T1	2		T2	3		T3	2
all_pins[10]	81446	1		T1	2		T2	3		T3	2
all_pins[11]	81446	1		T1	2		T2	3		T3	2
all_pins[12]	81446	1		T1	2		T2	3		T3	2
all_pins[13]	81446	1		T1	2		T2	3		T3	2
all_pins[14]	81446	1		T1	2		T2	3		T3	2
all_pins[15]	81446	1		T1	2		T2	3		T3	2
all_pins[16]	81446	1		T1	2		T2	3		T3	2
all_pins[17]	81446	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1463877	1		T1	36		T2	54		T3	36
values[0x1]	2151	1		T7	1		T17	12		T22	12
transitions[0x0=>0x1]	1926	1		T7	1		T17	12		T22	12
transitions[0x1=>0x0]	1937	1		T7	1		T17	12		T22	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	81348	1		T1	2		T2	3		T3	2
all_pins[0]	values[0x1]	98	1		T274	1		T275	1		T276	1
all_pins[0]	transitions[0x0=>0x1]	83	1		T274	1		T275	1		T276	1
all_pins[0]	transitions[0x1=>0x0]	1002	1		T7	1		T17	12		T22	12
all_pins[1]	values[0x0]	80429	1		T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	1017	1		T7	1		T17	12		T22	12
all_pins[1]	transitions[0x0=>0x1]	1003	1		T7	1		T17	12		T22	12
all_pins[1]	transitions[0x1=>0x0]	92	1		T42	1		T43	1		T44	1
all_pins[2]	values[0x0]	81340	1		T1	2		T2	3		T3	2
all_pins[2]	values[0x1]	106	1		T42	1		T43	1		T44	1
all_pins[2]	transitions[0x0=>0x1]	91	1		T42	1		T43	1		T44	1
all_pins[2]	transitions[0x1=>0x0]	50	1		T64	1		T198	3		T199	3
all_pins[3]	values[0x0]	81381	1		T1	2		T2	3		T3	2
all_pins[3]	values[0x1]	65	1		T64	1		T198	3		T199	4
all_pins[3]	transitions[0x0=>0x1]	52	1		T64	1		T198	3		T199	3
all_pins[3]	transitions[0x1=>0x0]	51	1		T65	1		T195	4		T197	3
all_pins[4]	values[0x0]	81382	1		T1	2		T2	3		T3	2
all_pins[4]	values[0x1]	64	1		T65	1		T195	4		T199	1
all_pins[4]	transitions[0x0=>0x1]	55	1		T65	1		T195	3		T199	1
all_pins[4]	transitions[0x1=>0x0]	50	1		T195	1		T196	1		T199	3
all_pins[5]	values[0x0]	81387	1		T1	2		T2	3		T3	2
all_pins[5]	values[0x1]	59	1		T195	2		T196	1		T199	3
all_pins[5]	transitions[0x0=>0x1]	47	1		T196	1		T199	2		T197	1
all_pins[5]	transitions[0x1=>0x0]	39	1		T198	2		T200	1		T199	1
all_pins[6]	values[0x0]	81395	1		T1	2		T2	3		T3	2
all_pins[6]	values[0x1]	51	1		T198	2		T195	2		T200	1
all_pins[6]	transitions[0x0=>0x1]	36	1		T198	2		T195	2		T200	1
all_pins[6]	transitions[0x1=>0x0]	39	1		T49	1		T50	1		T51	1
all_pins[7]	values[0x0]	81392	1		T1	2		T2	3		T3	2
all_pins[7]	values[0x1]	54	1		T49	1		T50	1		T51	1
all_pins[7]	transitions[0x0=>0x1]	45	1		T49	1		T50	1		T51	1
all_pins[7]	transitions[0x1=>0x0]	28	1		T53	1		T199	1		T197	2
all_pins[8]	values[0x0]	81409	1		T1	2		T2	3		T3	2
all_pins[8]	values[0x1]	37	1		T53	1		T200	1		T196	1
all_pins[8]	transitions[0x0=>0x1]	29	1		T53	1		T200	1		T199	1
all_pins[8]	transitions[0x1=>0x0]	62	1		T61	2		T62	2		T63	2
all_pins[9]	values[0x0]	81376	1		T1	2		T2	3		T3	2
all_pins[9]	values[0x1]	70	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x0=>0x1]	55	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x1=>0x0]	42	1		T200	2		T196	2		T197	1
all_pins[10]	values[0x0]	81389	1		T1	2		T2	3		T3	2
all_pins[10]	values[0x1]	57	1		T200	3		T196	2		T197	1
all_pins[10]	transitions[0x0=>0x1]	42	1		T196	1		T197	1		T268	1
all_pins[10]	transitions[0x1=>0x0]	92	1		T47	1		T69	1		T70	1
all_pins[11]	values[0x0]	81339	1		T1	2		T2	3		T3	2
all_pins[11]	values[0x1]	107	1		T47	1		T69	1		T70	1
all_pins[11]	transitions[0x0=>0x1]	93	1		T47	1		T69	1		T70	1
all_pins[11]	transitions[0x1=>0x0]	57	1		T74	1		T75	1		T76	1
all_pins[12]	values[0x0]	81375	1		T1	2		T2	3		T3	2
all_pins[12]	values[0x1]	71	1		T74	1		T75	1		T76	1
all_pins[12]	transitions[0x0=>0x1]	61	1		T74	1		T75	1		T76	1
all_pins[12]	transitions[0x1=>0x0]	44	1		T197	1		T277	1		T273	1
all_pins[13]	values[0x0]	81392	1		T1	2		T2	3		T3	2
all_pins[13]	values[0x1]	54	1		T197	2		T277	1		T273	1
all_pins[13]	transitions[0x0=>0x1]	42	1		T197	2		T273	1		T269	4
all_pins[13]	transitions[0x1=>0x0]	45	1		T195	5		T197	1		T268	3
all_pins[14]	values[0x0]	81389	1		T1	2		T2	3		T3	2
all_pins[14]	values[0x1]	57	1		T195	5		T197	1		T268	3
all_pins[14]	transitions[0x0=>0x1]	44	1		T195	4		T197	1		T268	1
all_pins[14]	transitions[0x1=>0x0]	50	1		T195	1		T196	1		T197	2
all_pins[15]	values[0x0]	81383	1		T1	2		T2	3		T3	2
all_pins[15]	values[0x1]	63	1		T195	2		T196	1		T197	2
all_pins[15]	transitions[0x0=>0x1]	52	1		T195	1		T196	1		T197	2
all_pins[15]	transitions[0x1=>0x0]	59	1		T66	4		T67	4		T68	4
all_pins[16]	values[0x0]	81376	1		T1	2		T2	3		T3	2
all_pins[16]	values[0x1]	70	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x0=>0x1]	63	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x1=>0x0]	44	1		T195	1		T196	1		T199	1
all_pins[17]	values[0x0]	81395	1		T1	2		T2	3		T3	2
all_pins[17]	values[0x1]	51	1		T195	1		T196	1		T199	1
all_pins[17]	transitions[0x0=>0x1]	33	1		T196	1		T199	1		T273	1
all_pins[17]	transitions[0x1=>0x0]	91	1		T274	1		T275	1		T276	1