Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.58 97.84 93.74 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2855
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T279 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3056636708 Jul 16 06:58:51 PM PDT 24 Jul 16 06:58:52 PM PDT 24 82830999 ps
T2773 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2001541428 Jul 16 06:57:59 PM PDT 24 Jul 16 06:58:02 PM PDT 24 149182687 ps
T246 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1919023783 Jul 16 06:58:12 PM PDT 24 Jul 16 06:58:16 PM PDT 24 164497630 ps
T286 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2451101983 Jul 16 06:58:39 PM PDT 24 Jul 16 06:58:42 PM PDT 24 37927243 ps
T283 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.611287801 Jul 16 06:58:13 PM PDT 24 Jul 16 06:58:16 PM PDT 24 43811670 ps
T247 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3113455019 Jul 16 06:58:13 PM PDT 24 Jul 16 06:58:16 PM PDT 24 95756369 ps
T2774 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3610330378 Jul 16 06:58:41 PM PDT 24 Jul 16 06:58:45 PM PDT 24 220130943 ps
T289 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3718558176 Jul 16 06:58:39 PM PDT 24 Jul 16 06:58:42 PM PDT 24 47564148 ps
T293 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3751030525 Jul 16 06:58:30 PM PDT 24 Jul 16 06:58:37 PM PDT 24 943587142 ps
T299 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2711888666 Jul 16 06:57:58 PM PDT 24 Jul 16 06:58:03 PM PDT 24 445103465 ps
T280 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1907143754 Jul 16 06:58:48 PM PDT 24 Jul 16 06:58:49 PM PDT 24 64690267 ps
T248 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4249511386 Jul 16 06:58:14 PM PDT 24 Jul 16 06:58:19 PM PDT 24 84910086 ps
T2775 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.145069916 Jul 16 06:58:42 PM PDT 24 Jul 16 06:58:44 PM PDT 24 55663748 ps
T2776 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1316501527 Jul 16 06:58:14 PM PDT 24 Jul 16 06:58:18 PM PDT 24 114051862 ps
T2777 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2866613513 Jul 16 06:58:13 PM PDT 24 Jul 16 06:58:17 PM PDT 24 188844346 ps
T2778 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3217766942 Jul 16 06:58:45 PM PDT 24 Jul 16 06:58:51 PM PDT 24 1108394907 ps
T249 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1807995442 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:31 PM PDT 24 133230702 ps
T2779 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.92160120 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:32 PM PDT 24 88213857 ps
T250 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1057754940 Jul 16 06:58:12 PM PDT 24 Jul 16 06:58:15 PM PDT 24 64336106 ps
T2780 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2604974908 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:30 PM PDT 24 60654832 ps
T284 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3616750488 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:28 PM PDT 24 43848616 ps
T2781 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.167896076 Jul 16 06:58:25 PM PDT 24 Jul 16 06:58:28 PM PDT 24 41689803 ps
T251 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3700381256 Jul 16 06:58:12 PM PDT 24 Jul 16 06:58:16 PM PDT 24 118003867 ps
T2782 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.752607044 Jul 16 06:58:12 PM PDT 24 Jul 16 06:58:16 PM PDT 24 260834367 ps
T2783 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2646768673 Jul 16 06:58:25 PM PDT 24 Jul 16 06:58:30 PM PDT 24 926389688 ps
T297 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1041476760 Jul 16 06:58:23 PM PDT 24 Jul 16 06:58:29 PM PDT 24 1058963458 ps
T2784 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3751835113 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:30 PM PDT 24 67254415 ps
T2785 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.766637461 Jul 16 06:58:14 PM PDT 24 Jul 16 06:58:17 PM PDT 24 184161359 ps
T2786 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2531861312 Jul 16 06:58:24 PM PDT 24 Jul 16 06:58:26 PM PDT 24 40385248 ps
T252 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3436421266 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:31 PM PDT 24 72919526 ps
T2787 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3445024761 Jul 16 06:58:14 PM PDT 24 Jul 16 06:58:17 PM PDT 24 44134205 ps
T253 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1122461769 Jul 16 06:57:59 PM PDT 24 Jul 16 06:58:03 PM PDT 24 124151340 ps
T2788 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1717031862 Jul 16 06:58:24 PM PDT 24 Jul 16 06:58:25 PM PDT 24 95661759 ps
T2789 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.112393363 Jul 16 06:58:38 PM PDT 24 Jul 16 06:58:41 PM PDT 24 64011862 ps
T2790 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3017505502 Jul 16 06:58:41 PM PDT 24 Jul 16 06:58:43 PM PDT 24 47715859 ps
T294 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2368545835 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:33 PM PDT 24 299964325 ps
T290 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1988500531 Jul 16 06:58:39 PM PDT 24 Jul 16 06:58:42 PM PDT 24 35238048 ps
T2791 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2941715303 Jul 16 06:58:24 PM PDT 24 Jul 16 06:58:26 PM PDT 24 151803012 ps
T2792 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.336464682 Jul 16 06:58:38 PM PDT 24 Jul 16 06:58:40 PM PDT 24 40018811 ps
T2793 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1345513371 Jul 16 06:58:25 PM PDT 24 Jul 16 06:58:29 PM PDT 24 149715660 ps
T2794 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3838393440 Jul 16 06:58:36 PM PDT 24 Jul 16 06:58:39 PM PDT 24 193281618 ps
T2795 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3235676759 Jul 16 06:57:58 PM PDT 24 Jul 16 06:58:01 PM PDT 24 85449024 ps
T2796 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2592766509 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:31 PM PDT 24 54589989 ps
T2797 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3480882229 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:31 PM PDT 24 401756497 ps
T2798 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.720615520 Jul 16 06:58:39 PM PDT 24 Jul 16 06:58:43 PM PDT 24 203400165 ps
T2799 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1006341278 Jul 16 06:58:40 PM PDT 24 Jul 16 06:58:42 PM PDT 24 100558398 ps
T2800 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2956252399 Jul 16 06:58:54 PM PDT 24 Jul 16 06:58:55 PM PDT 24 89688102 ps
T2801 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3945513417 Jul 16 06:58:36 PM PDT 24 Jul 16 06:58:38 PM PDT 24 34548024 ps
T2802 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.770557115 Jul 16 06:58:25 PM PDT 24 Jul 16 06:58:27 PM PDT 24 71787123 ps
T2803 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3917989328 Jul 16 06:58:49 PM PDT 24 Jul 16 06:58:50 PM PDT 24 43715531 ps
T2804 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3596753373 Jul 16 06:58:25 PM PDT 24 Jul 16 06:58:28 PM PDT 24 225665589 ps
T2805 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3656030931 Jul 16 06:58:37 PM PDT 24 Jul 16 06:58:39 PM PDT 24 35270879 ps
T2806 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1444859580 Jul 16 06:58:24 PM PDT 24 Jul 16 06:58:26 PM PDT 24 105850303 ps
T2807 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4288109784 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:32 PM PDT 24 205757674 ps
T295 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3384252010 Jul 16 06:58:15 PM PDT 24 Jul 16 06:58:23 PM PDT 24 881216822 ps
T2808 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4146801295 Jul 16 06:58:39 PM PDT 24 Jul 16 06:58:42 PM PDT 24 63832492 ps
T2809 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1754384833 Jul 16 06:58:37 PM PDT 24 Jul 16 06:58:40 PM PDT 24 96263305 ps
T2810 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2933479625 Jul 16 06:58:11 PM PDT 24 Jul 16 06:58:13 PM PDT 24 110970625 ps
T2811 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3733954895 Jul 16 06:58:12 PM PDT 24 Jul 16 06:58:15 PM PDT 24 184224507 ps
T2812 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3678865219 Jul 16 06:57:57 PM PDT 24 Jul 16 06:58:04 PM PDT 24 991395764 ps
T2813 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2219640475 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:28 PM PDT 24 39923018 ps
T2814 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2756389147 Jul 16 06:58:14 PM PDT 24 Jul 16 06:58:18 PM PDT 24 184893224 ps
T2815 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1947845478 Jul 16 06:57:58 PM PDT 24 Jul 16 06:58:02 PM PDT 24 168701456 ps
T2816 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3430444597 Jul 16 06:58:38 PM PDT 24 Jul 16 06:58:40 PM PDT 24 80645686 ps
T2817 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2392497708 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:28 PM PDT 24 68532250 ps
T2818 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1007872074 Jul 16 06:58:23 PM PDT 24 Jul 16 06:58:26 PM PDT 24 174058793 ps
T2819 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1301957754 Jul 16 06:58:13 PM PDT 24 Jul 16 06:58:19 PM PDT 24 370022391 ps
T2820 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1567212228 Jul 16 06:58:38 PM PDT 24 Jul 16 06:58:40 PM PDT 24 66550636 ps
T2821 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.186112371 Jul 16 06:58:38 PM PDT 24 Jul 16 06:58:41 PM PDT 24 90337937 ps
T2822 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3924239216 Jul 16 06:58:12 PM PDT 24 Jul 16 06:58:17 PM PDT 24 208054581 ps
T2823 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3017431121 Jul 16 06:58:51 PM PDT 24 Jul 16 06:58:52 PM PDT 24 37804194 ps
T2824 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.397382118 Jul 16 06:57:57 PM PDT 24 Jul 16 06:58:02 PM PDT 24 299066731 ps
T2825 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4129776891 Jul 16 06:58:02 PM PDT 24 Jul 16 06:58:05 PM PDT 24 227489265 ps
T287 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.407470070 Jul 16 06:58:40 PM PDT 24 Jul 16 06:58:42 PM PDT 24 29153835 ps
T2826 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3310401145 Jul 16 06:58:37 PM PDT 24 Jul 16 06:58:40 PM PDT 24 336186178 ps
T2827 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.287393047 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:32 PM PDT 24 69715101 ps
T2828 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3261828468 Jul 16 06:58:13 PM PDT 24 Jul 16 06:58:18 PM PDT 24 218040375 ps
T2829 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2210155029 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:31 PM PDT 24 67168436 ps
T2830 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1144577263 Jul 16 06:58:12 PM PDT 24 Jul 16 06:58:15 PM PDT 24 32613587 ps
T2831 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1038235714 Jul 16 06:58:28 PM PDT 24 Jul 16 06:58:34 PM PDT 24 399499119 ps
T2832 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.526440843 Jul 16 06:58:37 PM PDT 24 Jul 16 06:58:39 PM PDT 24 40491382 ps
T2833 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3933881394 Jul 16 06:58:13 PM PDT 24 Jul 16 06:58:17 PM PDT 24 149529679 ps
T2834 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1778804782 Jul 16 06:58:12 PM PDT 24 Jul 16 06:58:15 PM PDT 24 186277342 ps
T2835 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3584723618 Jul 16 06:57:57 PM PDT 24 Jul 16 06:58:01 PM PDT 24 71761273 ps
T2836 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1912324246 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:35 PM PDT 24 1652481739 ps
T2837 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2050708662 Jul 16 06:57:59 PM PDT 24 Jul 16 06:58:06 PM PDT 24 822990564 ps
T2838 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2168605769 Jul 16 06:58:11 PM PDT 24 Jul 16 06:58:14 PM PDT 24 84452262 ps
T2839 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4244035883 Jul 16 06:58:36 PM PDT 24 Jul 16 06:58:38 PM PDT 24 46730418 ps
T2840 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2331248737 Jul 16 06:58:36 PM PDT 24 Jul 16 06:58:37 PM PDT 24 42263602 ps
T2841 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1229420386 Jul 16 06:58:14 PM PDT 24 Jul 16 06:58:24 PM PDT 24 1568535199 ps
T2842 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1863730553 Jul 16 06:58:27 PM PDT 24 Jul 16 06:58:32 PM PDT 24 163026486 ps
T2843 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1631975850 Jul 16 06:58:39 PM PDT 24 Jul 16 06:58:42 PM PDT 24 50147574 ps
T2844 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1419453164 Jul 16 06:58:52 PM PDT 24 Jul 16 06:58:53 PM PDT 24 91665280 ps
T2845 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2397854317 Jul 16 06:58:10 PM PDT 24 Jul 16 06:58:11 PM PDT 24 86381610 ps
T296 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4172941354 Jul 16 06:58:25 PM PDT 24 Jul 16 06:58:32 PM PDT 24 943943327 ps
T2846 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2900262735 Jul 16 06:58:35 PM PDT 24 Jul 16 06:58:38 PM PDT 24 93912915 ps
T2847 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3112576057 Jul 16 06:58:36 PM PDT 24 Jul 16 06:58:38 PM PDT 24 55326844 ps
T2848 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1919021690 Jul 16 06:58:37 PM PDT 24 Jul 16 06:58:39 PM PDT 24 83870474 ps
T2849 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1515220811 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:30 PM PDT 24 105451706 ps
T2850 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3515288476 Jul 16 06:58:11 PM PDT 24 Jul 16 06:58:12 PM PDT 24 107561799 ps
T2851 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.95199373 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:29 PM PDT 24 117202386 ps
T2852 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1960205045 Jul 16 06:58:38 PM PDT 24 Jul 16 06:58:42 PM PDT 24 144791698 ps
T2853 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1592180349 Jul 16 06:58:00 PM PDT 24 Jul 16 06:58:05 PM PDT 24 262733695 ps
T2854 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3312452423 Jul 16 06:57:58 PM PDT 24 Jul 16 06:58:01 PM PDT 24 69284888 ps
T2855 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1376721920 Jul 16 06:58:26 PM PDT 24 Jul 16 06:58:31 PM PDT 24 256954739 ps

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.943579757
Short name T19
Test name
Test status
Simulation time 227514612 ps
CPU time 0.85 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:46:52 PM PDT 24
Peak memory 206836 kb
Host smart-9dfd3887-ac62-4edc-93cb-468fb4db2902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94357
9757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.943579757
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/38.usbdev_device_address.2123427591
Short name T41
Test name
Test status
Simulation time 18113276260 ps
CPU time 36.33 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:46 PM PDT 24
Peak memory 207040 kb
Host smart-e680c59f-aa2a-40d8-90dd-fcdef204ea3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21234
27591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.2123427591
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1183533387
Short name T197
Test name
Test status
Simulation time 45581231 ps
CPU time 0.69 seconds
Started Jul 16 06:58:50 PM PDT 24
Finished Jul 16 06:58:52 PM PDT 24
Peak memory 206364 kb
Host smart-a1ceba4e-bc05-4034-86fb-ec165dde35d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1183533387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1183533387
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.314664573
Short name T7
Test name
Test status
Simulation time 4400046541 ps
CPU time 4.74 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206856 kb
Host smart-91222a39-1f93-4947-a2ec-4139c9f1d400
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=314664573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.314664573
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.536443582
Short name T184
Test name
Test status
Simulation time 715686571 ps
CPU time 4.56 seconds
Started Jul 16 06:58:17 PM PDT 24
Finished Jul 16 06:58:23 PM PDT 24
Peak memory 206632 kb
Host smart-724875f7-1bcd-44d8-bd5a-49ae41fdc3e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=536443582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.536443582
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.4259417435
Short name T37
Test name
Test status
Simulation time 118144746528 ps
CPU time 141.88 seconds
Started Jul 16 06:47:03 PM PDT 24
Finished Jul 16 06:49:26 PM PDT 24
Peak memory 207116 kb
Host smart-9e12c6fc-0730-4cb0-94e2-c2c3d29b8551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259417435 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.4259417435
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1025778065
Short name T78
Test name
Test status
Simulation time 165166464 ps
CPU time 0.84 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:31 PM PDT 24
Peak memory 206888 kb
Host smart-4e6338e6-e115-441e-b0b7-29a6914a019d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10257
78065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1025778065
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4215484879
Short name T273
Test name
Test status
Simulation time 30450199 ps
CPU time 0.69 seconds
Started Jul 16 06:58:41 PM PDT 24
Finished Jul 16 06:58:43 PM PDT 24
Peak memory 206352 kb
Host smart-fd55a7f3-8c8e-49b3-93d8-89bc9fd268d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4215484879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4215484879
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1848028341
Short name T14
Test name
Test status
Simulation time 23329007505 ps
CPU time 21.12 seconds
Started Jul 16 06:52:29 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 207164 kb
Host smart-8a0ec9dc-caf6-432e-9059-c6bbf717d6ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1848028341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1848028341
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.891057436
Short name T82
Test name
Test status
Simulation time 5299993447 ps
CPU time 48.69 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:52:08 PM PDT 24
Peak memory 207052 kb
Host smart-c0879d83-bd13-456d-9d33-c95507a26be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89105
7436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.891057436
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1874825741
Short name T29
Test name
Test status
Simulation time 192449618 ps
CPU time 0.81 seconds
Started Jul 16 06:47:13 PM PDT 24
Finished Jul 16 06:47:15 PM PDT 24
Peak memory 206816 kb
Host smart-2b782e2d-38e4-43de-8c2d-28f3b250b0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18748
25741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1874825741
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1827248365
Short name T21
Test name
Test status
Simulation time 1206082788 ps
CPU time 2.72 seconds
Started Jul 16 06:55:05 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 207004 kb
Host smart-abac9df3-846d-423d-a7ed-a63cb6cf4732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18272
48365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1827248365
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.63765000
Short name T230
Test name
Test status
Simulation time 184505345 ps
CPU time 2.05 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:43 PM PDT 24
Peak memory 223040 kb
Host smart-75139b1a-7d43-4627-9449-e4a59c863ed6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63765000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev
_csr_mem_rw_with_rand_reset.63765000
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.4050600088
Short name T88
Test name
Test status
Simulation time 5926464775 ps
CPU time 150.64 seconds
Started Jul 16 06:47:44 PM PDT 24
Finished Jul 16 06:50:16 PM PDT 24
Peak memory 207164 kb
Host smart-30ddf953-ec24-4bdf-bfb6-e5882618c5d8
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4050600088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.4050600088
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1146217908
Short name T27
Test name
Test status
Simulation time 60823443 ps
CPU time 0.74 seconds
Started Jul 16 06:51:27 PM PDT 24
Finished Jul 16 06:51:28 PM PDT 24
Peak memory 206872 kb
Host smart-78941148-6b24-4280-bb19-2244fd5b03dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11462
17908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1146217908
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1209022902
Short name T43
Test name
Test status
Simulation time 150979983 ps
CPU time 0.76 seconds
Started Jul 16 06:49:45 PM PDT 24
Finished Jul 16 06:49:46 PM PDT 24
Peak memory 206896 kb
Host smart-551758e3-6e69-46e7-b083-32225fdf1c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12090
22902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1209022902
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.249028978
Short name T199
Test name
Test status
Simulation time 41060478 ps
CPU time 0.67 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:41 PM PDT 24
Peak memory 206352 kb
Host smart-a9840c84-1105-43a2-8691-f2e5889ca3cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=249028978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.249028978
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2316113687
Short name T183
Test name
Test status
Simulation time 629802449 ps
CPU time 1.39 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:46:51 PM PDT 24
Peak memory 225596 kb
Host smart-94d37877-cc42-48f0-8e45-aa53bf1683e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2316113687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2316113687
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.975921302
Short name T176
Test name
Test status
Simulation time 51683175 ps
CPU time 0.77 seconds
Started Jul 16 06:50:17 PM PDT 24
Finished Jul 16 06:50:22 PM PDT 24
Peak memory 206880 kb
Host smart-62a70279-d416-4350-9c8c-e46369402f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=975921302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.975921302
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.6934363
Short name T77
Test name
Test status
Simulation time 301315602 ps
CPU time 0.94 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:53 PM PDT 24
Peak memory 206828 kb
Host smart-922a8e13-f027-4462-9db1-b36e572afb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69343
63 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.6934363
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2888819106
Short name T102
Test name
Test status
Simulation time 392578338 ps
CPU time 1.37 seconds
Started Jul 16 06:54:20 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206876 kb
Host smart-06b4dbe6-2690-41cb-bbd8-c0af9f24ee59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28888
19106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2888819106
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3014786301
Short name T46
Test name
Test status
Simulation time 20165422916 ps
CPU time 22.06 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:47:10 PM PDT 24
Peak memory 206912 kb
Host smart-dcaf8dfd-7f09-4c00-b540-26ded0fd84c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30147
86301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3014786301
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1864759533
Short name T45
Test name
Test status
Simulation time 14609497298 ps
CPU time 76.24 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:48:07 PM PDT 24
Peak memory 207088 kb
Host smart-42331944-d182-4570-b1ef-dcc5a8b87be4
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1864759533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.1864759533
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1907143754
Short name T280
Test name
Test status
Simulation time 64690267 ps
CPU time 0.7 seconds
Started Jul 16 06:58:48 PM PDT 24
Finished Jul 16 06:58:49 PM PDT 24
Peak memory 206328 kb
Host smart-2cbb312c-e26c-4e5b-ad2b-b5e9b92e3ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1907143754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1907143754
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3356885227
Short name T243
Test name
Test status
Simulation time 216169697 ps
CPU time 2.29 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:16 PM PDT 24
Peak memory 215928 kb
Host smart-14f4b274-16e3-4f2f-8feb-6223223fc15f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3356885227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3356885227
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.454059796
Short name T70
Test name
Test status
Simulation time 183929008 ps
CPU time 0.8 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206752 kb
Host smart-cca7b0a8-8527-4ecc-b716-006571225e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45405
9796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.454059796
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1268448076
Short name T223
Test name
Test status
Simulation time 219556375 ps
CPU time 2.93 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:44 PM PDT 24
Peak memory 214824 kb
Host smart-dfd43f42-36b4-43fb-953a-9fbeed33c51c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1268448076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1268448076
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.409775595
Short name T6
Test name
Test status
Simulation time 10975517930 ps
CPU time 105.54 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:53:06 PM PDT 24
Peak memory 207160 kb
Host smart-691c754c-f3ae-4784-a424-623b56ea6926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40977
5595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.409775595
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.407470070
Short name T287
Test name
Test status
Simulation time 29153835 ps
CPU time 0.66 seconds
Started Jul 16 06:58:40 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206360 kb
Host smart-aece4ca5-cff7-49fc-8a83-eb4d8b594f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=407470070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.407470070
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.433660157
Short name T272
Test name
Test status
Simulation time 54472170 ps
CPU time 0.7 seconds
Started Jul 16 06:57:59 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 206324 kb
Host smart-55f1edfd-c64a-48af-a5c6-9954c7a5c3d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=433660157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.433660157
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3751030525
Short name T293
Test name
Test status
Simulation time 943587142 ps
CPU time 5.18 seconds
Started Jul 16 06:58:30 PM PDT 24
Finished Jul 16 06:58:37 PM PDT 24
Peak memory 206620 kb
Host smart-ec7b541d-3353-4e34-9f5d-a4aec72bf6fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3751030525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3751030525
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1364142985
Short name T414
Test name
Test status
Simulation time 154572122 ps
CPU time 0.8 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:49:54 PM PDT 24
Peak memory 206788 kb
Host smart-929e2199-97d0-4f18-895a-28457922042c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13641
42985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1364142985
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3876275572
Short name T165
Test name
Test status
Simulation time 13062140249 ps
CPU time 257.78 seconds
Started Jul 16 06:48:01 PM PDT 24
Finished Jul 16 06:52:20 PM PDT 24
Peak memory 207012 kb
Host smart-b84091be-7963-4199-a108-48e81093756a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3876275572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3876275572
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3725229862
Short name T66
Test name
Test status
Simulation time 440577016 ps
CPU time 1.23 seconds
Started Jul 16 06:46:42 PM PDT 24
Finished Jul 16 06:46:44 PM PDT 24
Peak memory 206880 kb
Host smart-97821d1c-2bf9-40e6-8d08-694fa5c3465b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37252
29862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3725229862
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.1567830079
Short name T193
Test name
Test status
Simulation time 13375997830 ps
CPU time 13.89 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:52:02 PM PDT 24
Peak memory 206924 kb
Host smart-6a44d679-082b-41b3-98a1-30c2f066df59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1567830079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.1567830079
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.516936160
Short name T52
Test name
Test status
Simulation time 413743683 ps
CPU time 1.26 seconds
Started Jul 16 06:47:34 PM PDT 24
Finished Jul 16 06:47:38 PM PDT 24
Peak memory 206876 kb
Host smart-2b77489e-b662-4c0d-a4b0-c424fc18a8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51693
6160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.516936160
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.893549683
Short name T22
Test name
Test status
Simulation time 922759035 ps
CPU time 2.22 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 207036 kb
Host smart-d654a0cc-9d6b-427c-b52f-371c50f18378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89354
9683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.893549683
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.553339126
Short name T148
Test name
Test status
Simulation time 14110956122 ps
CPU time 297.68 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:53:51 PM PDT 24
Peak memory 207120 kb
Host smart-d090bcda-080e-4bb4-bb99-40321f112deb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=553339126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.553339126
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.97689331
Short name T61
Test name
Test status
Simulation time 160329291 ps
CPU time 0.79 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:46:39 PM PDT 24
Peak memory 206824 kb
Host smart-ed41a7ef-8d54-49bb-8bab-8e81ab469a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97689
331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.97689331
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3751835113
Short name T2784
Test name
Test status
Simulation time 67254415 ps
CPU time 0.73 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 206352 kb
Host smart-5fbe37f6-4a6d-4e75-8d64-c85fc6a2b094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3751835113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3751835113
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2368545835
Short name T294
Test name
Test status
Simulation time 299964325 ps
CPU time 2.48 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:33 PM PDT 24
Peak memory 206588 kb
Host smart-f2b7bf69-b596-416f-97a2-5f79756bcfa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2368545835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2368545835
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.795846038
Short name T291
Test name
Test status
Simulation time 283222417 ps
CPU time 2.57 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 206564 kb
Host smart-1cc62f00-546f-45ac-b842-14b2068d6183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=795846038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.795846038
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1587300460
Short name T213
Test name
Test status
Simulation time 121466849 ps
CPU time 1.38 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 206540 kb
Host smart-21b41854-da7b-47e6-8344-89b39d573d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1587300460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1587300460
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_device_address.3596222708
Short name T87
Test name
Test status
Simulation time 6831886821 ps
CPU time 12.35 seconds
Started Jul 16 06:47:01 PM PDT 24
Finished Jul 16 06:47:15 PM PDT 24
Peak memory 207064 kb
Host smart-73978ce6-c76a-4da3-884f-8ab3ca98c981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35962
22708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.3596222708
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3931180000
Short name T745
Test name
Test status
Simulation time 53486131 ps
CPU time 0.69 seconds
Started Jul 16 06:47:18 PM PDT 24
Finished Jul 16 06:47:19 PM PDT 24
Peak memory 206800 kb
Host smart-0cb6bc35-f232-480b-9a6a-2e942a4e294f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39311
80000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3931180000
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2474873061
Short name T39
Test name
Test status
Simulation time 171451565 ps
CPU time 0.75 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 206900 kb
Host smart-668182ce-3731-4b73-9c4e-33bb2d7d0a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24748
73061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2474873061
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.3510154411
Short name T62
Test name
Test status
Simulation time 133159347 ps
CPU time 0.75 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:02 PM PDT 24
Peak memory 206752 kb
Host smart-c604019b-d6f1-401c-8784-0126127ffb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35101
54411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3510154411
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3925988351
Short name T174
Test name
Test status
Simulation time 221953039 ps
CPU time 1.44 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:18 PM PDT 24
Peak memory 207016 kb
Host smart-51b63805-2cfd-409f-9661-cab2c3868cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39259
88351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3925988351
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3274219865
Short name T49
Test name
Test status
Simulation time 195550750 ps
CPU time 0.87 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:46:39 PM PDT 24
Peak memory 207028 kb
Host smart-6d3d3d85-6d55-4faa-a2f0-ca4036e1d589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32742
19865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3274219865
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.2667730493
Short name T64
Test name
Test status
Simulation time 4185767549 ps
CPU time 8.96 seconds
Started Jul 16 06:46:39 PM PDT 24
Finished Jul 16 06:46:49 PM PDT 24
Peak memory 207032 kb
Host smart-ff87e6b8-c602-4f82-99ff-e4554ed4d7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26677
30493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.2667730493
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.490126417
Short name T65
Test name
Test status
Simulation time 186121978 ps
CPU time 0.77 seconds
Started Jul 16 06:46:42 PM PDT 24
Finished Jul 16 06:46:44 PM PDT 24
Peak memory 206744 kb
Host smart-df5848af-d489-480b-a62b-a34120c54ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49012
6417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.490126417
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.4012633106
Short name T53
Test name
Test status
Simulation time 257906491 ps
CPU time 0.99 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:46:52 PM PDT 24
Peak memory 206840 kb
Host smart-72254fb5-2097-44ae-b900-16b85a428b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40126
33106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.4012633106
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1858878597
Short name T75
Test name
Test status
Simulation time 187070200 ps
CPU time 0.84 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 207032 kb
Host smart-e03c0d65-2f10-4001-a08e-cfd54a8fb2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18588
78597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1858878597
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.3238760056
Short name T399
Test name
Test status
Simulation time 6803681565 ps
CPU time 46.7 seconds
Started Jul 16 06:50:36 PM PDT 24
Finished Jul 16 06:51:26 PM PDT 24
Peak memory 206936 kb
Host smart-e65241e0-b3b5-4456-9fbb-67dbd0fa37e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
60056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.3238760056
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3418465052
Short name T128
Test name
Test status
Simulation time 204090882 ps
CPU time 0.89 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206852 kb
Host smart-e0f1463a-f892-4202-8793-dbe6a5b29146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
65052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3418465052
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3697757017
Short name T2411
Test name
Test status
Simulation time 201374113 ps
CPU time 0.85 seconds
Started Jul 16 06:49:37 PM PDT 24
Finished Jul 16 06:49:40 PM PDT 24
Peak memory 206816 kb
Host smart-bb8041e6-fc29-4e6c-9037-b8d1dbf0f442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36977
57017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3697757017
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2067247148
Short name T130
Test name
Test status
Simulation time 177122328 ps
CPU time 0.85 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:49:54 PM PDT 24
Peak memory 206888 kb
Host smart-0592b0e7-72f2-4cb7-b4f6-aa40acb12b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672
47148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2067247148
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1011228581
Short name T1975
Test name
Test status
Simulation time 193075266 ps
CPU time 0.87 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206880 kb
Host smart-ed572714-49a1-47de-bfe5-3c37919d92e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10112
28581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1011228581
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1514550011
Short name T111
Test name
Test status
Simulation time 244161745 ps
CPU time 0.95 seconds
Started Jul 16 06:50:31 PM PDT 24
Finished Jul 16 06:50:33 PM PDT 24
Peak memory 206800 kb
Host smart-a8c3c6aa-2a6e-4cb1-8496-ead9a5152977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15145
50011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1514550011
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3483393125
Short name T122
Test name
Test status
Simulation time 206431594 ps
CPU time 0.86 seconds
Started Jul 16 06:51:10 PM PDT 24
Finished Jul 16 06:51:12 PM PDT 24
Peak memory 206872 kb
Host smart-020290bb-7c53-41fc-9475-f96997b561e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34833
93125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3483393125
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.276682915
Short name T116
Test name
Test status
Simulation time 213415725 ps
CPU time 0.9 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206736 kb
Host smart-9a4fa7b9-cc31-4fe8-9269-d9387809bbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27668
2915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.276682915
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2331301432
Short name T121
Test name
Test status
Simulation time 161480832 ps
CPU time 0.85 seconds
Started Jul 16 06:51:52 PM PDT 24
Finished Jul 16 06:51:54 PM PDT 24
Peak memory 206880 kb
Host smart-ca5fea4f-f5d3-4dd0-b331-ce6c2f68eaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
01432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2331301432
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1621507767
Short name T109
Test name
Test status
Simulation time 215320723 ps
CPU time 0.87 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:52:13 PM PDT 24
Peak memory 206692 kb
Host smart-40ed34f5-6871-4d5f-8db8-5dd7dc2e8e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16215
07767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1621507767
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.941197521
Short name T136
Test name
Test status
Simulation time 171216925 ps
CPU time 0.83 seconds
Started Jul 16 06:53:17 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 206852 kb
Host smart-fbd51dfd-c9c0-49fe-a3cb-0c3e4b3e7caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94119
7521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.941197521
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.529851151
Short name T125
Test name
Test status
Simulation time 225383385 ps
CPU time 0.88 seconds
Started Jul 16 06:54:58 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206884 kb
Host smart-192e7526-3b70-404f-90cb-64c69b4e9dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52985
1151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.529851151
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.397382118
Short name T2824
Test name
Test status
Simulation time 299066731 ps
CPU time 3.7 seconds
Started Jul 16 06:57:57 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 206504 kb
Host smart-5a05b191-6823-42bc-a47b-8778a83b80bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=397382118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.397382118
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3678865219
Short name T2812
Test name
Test status
Simulation time 991395764 ps
CPU time 5.36 seconds
Started Jul 16 06:57:57 PM PDT 24
Finished Jul 16 06:58:04 PM PDT 24
Peak memory 206440 kb
Host smart-957387d2-c399-46cb-baf3-7b08350c3cea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3678865219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3678865219
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1947845478
Short name T2815
Test name
Test status
Simulation time 168701456 ps
CPU time 0.9 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 206388 kb
Host smart-ed9f84bb-a5e1-4034-97a2-94285cc2c5c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1947845478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1947845478
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3235676759
Short name T2795
Test name
Test status
Simulation time 85449024 ps
CPU time 1.22 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:01 PM PDT 24
Peak memory 214880 kb
Host smart-cc1da420-0ccd-4366-aec1-5a46a8d89abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235676759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3235676759
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3312452423
Short name T2854
Test name
Test status
Simulation time 69284888 ps
CPU time 0.86 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:01 PM PDT 24
Peak memory 206404 kb
Host smart-44477fc9-7a4a-4be7-8d95-aa66476b14c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3312452423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3312452423
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3365651040
Short name T271
Test name
Test status
Simulation time 96348108 ps
CPU time 0.71 seconds
Started Jul 16 06:58:01 PM PDT 24
Finished Jul 16 06:58:03 PM PDT 24
Peak memory 206340 kb
Host smart-2dda867c-9ac0-4ac7-951e-6f2fe83dadab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3365651040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3365651040
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1122461769
Short name T253
Test name
Test status
Simulation time 124151340 ps
CPU time 1.53 seconds
Started Jul 16 06:57:59 PM PDT 24
Finished Jul 16 06:58:03 PM PDT 24
Peak memory 215964 kb
Host smart-6c7d87d7-aae0-4a6f-bf31-e9a6a5456364
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1122461769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1122461769
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1592180349
Short name T2853
Test name
Test status
Simulation time 262733695 ps
CPU time 2.78 seconds
Started Jul 16 06:58:00 PM PDT 24
Finished Jul 16 06:58:05 PM PDT 24
Peak memory 206452 kb
Host smart-55755cb6-8f04-4b04-b0ee-ceb1b67d1ed7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1592180349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1592180349
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2001541428
Short name T2773
Test name
Test status
Simulation time 149182687 ps
CPU time 1.53 seconds
Started Jul 16 06:57:59 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 206532 kb
Host smart-40163d94-3714-45c2-ba35-898a6c6bd51e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2001541428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2001541428
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3584723618
Short name T2835
Test name
Test status
Simulation time 71761273 ps
CPU time 1.4 seconds
Started Jul 16 06:57:57 PM PDT 24
Finished Jul 16 06:58:01 PM PDT 24
Peak memory 206656 kb
Host smart-bd2caf96-0326-4820-92b3-db393a16188b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3584723618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3584723618
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2050708662
Short name T2837
Test name
Test status
Simulation time 822990564 ps
CPU time 4.99 seconds
Started Jul 16 06:57:59 PM PDT 24
Finished Jul 16 06:58:06 PM PDT 24
Peak memory 206552 kb
Host smart-ee5e17cc-1fe1-4e73-96bf-3d452f0cd749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2050708662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2050708662
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3959958250
Short name T191
Test name
Test status
Simulation time 302196253 ps
CPU time 3.69 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:20 PM PDT 24
Peak memory 206548 kb
Host smart-80e8f58b-ba13-406c-8a82-1c29f7b72748
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3959958250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3959958250
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4212840414
Short name T189
Test name
Test status
Simulation time 474455862 ps
CPU time 4.49 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:21 PM PDT 24
Peak memory 206500 kb
Host smart-5a22e591-55f0-41c9-8b30-3fb69bdce703
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4212840414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.4212840414
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1807998331
Short name T245
Test name
Test status
Simulation time 103007584 ps
CPU time 0.89 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 206408 kb
Host smart-4649945b-0b5f-4695-b10e-ef4f82505820
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1807998331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1807998331
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2168605769
Short name T2838
Test name
Test status
Simulation time 84452262 ps
CPU time 2.05 seconds
Started Jul 16 06:58:11 PM PDT 24
Finished Jul 16 06:58:14 PM PDT 24
Peak memory 214792 kb
Host smart-9766e779-ade8-43e3-95c0-a61820f0e6b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168605769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2168605769
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2397854317
Short name T2845
Test name
Test status
Simulation time 86381610 ps
CPU time 0.88 seconds
Started Jul 16 06:58:10 PM PDT 24
Finished Jul 16 06:58:11 PM PDT 24
Peak memory 206292 kb
Host smart-a468364f-f83d-4355-bd70-5e170cef7cf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2397854317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2397854317
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1057754940
Short name T250
Test name
Test status
Simulation time 64336106 ps
CPU time 1.42 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 214864 kb
Host smart-b0149d03-a52e-46fe-8789-3d70881668eb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1057754940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1057754940
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.385649591
Short name T2758
Test name
Test status
Simulation time 384298662 ps
CPU time 2.9 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:20 PM PDT 24
Peak memory 206460 kb
Host smart-6a6b3f9a-9b33-48a8-8a3f-f9a815452732
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=385649591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.385649591
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.766637461
Short name T2785
Test name
Test status
Simulation time 184161359 ps
CPU time 1.31 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:17 PM PDT 24
Peak memory 206584 kb
Host smart-b84892a3-461d-468c-b6ed-f32ee0f3b258
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=766637461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.766637461
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4129776891
Short name T2825
Test name
Test status
Simulation time 227489265 ps
CPU time 2.11 seconds
Started Jul 16 06:58:02 PM PDT 24
Finished Jul 16 06:58:05 PM PDT 24
Peak memory 206624 kb
Host smart-a1b11c06-e403-40ab-a6c4-3aa9119ba636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4129776891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4129776891
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2711888666
Short name T299
Test name
Test status
Simulation time 445103465 ps
CPU time 2.72 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:03 PM PDT 24
Peak memory 206540 kb
Host smart-2a06e398-e258-44c9-804f-a1486ef3aeb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2711888666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2711888666
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2627346925
Short name T233
Test name
Test status
Simulation time 151230678 ps
CPU time 1.45 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 214840 kb
Host smart-f6538c17-66f4-41cf-903a-9f87e7450302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627346925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2627346925
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2210155029
Short name T2829
Test name
Test status
Simulation time 67168436 ps
CPU time 1 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206516 kb
Host smart-39460cb0-6455-4f55-a566-1439cfd9763b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2210155029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2210155029
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2821826013
Short name T269
Test name
Test status
Simulation time 41060897 ps
CPU time 0.65 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:26 PM PDT 24
Peak memory 206408 kb
Host smart-6e72e00e-ba13-4d41-a7ab-09f3e221c050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2821826013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2821826013
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2077873637
Short name T259
Test name
Test status
Simulation time 287659147 ps
CPU time 1.9 seconds
Started Jul 16 06:58:28 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 206612 kb
Host smart-7f60a18d-001f-4766-8b56-492d7f14b178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2077873637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2077873637
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1038235714
Short name T2831
Test name
Test status
Simulation time 399499119 ps
CPU time 3.06 seconds
Started Jul 16 06:58:28 PM PDT 24
Finished Jul 16 06:58:34 PM PDT 24
Peak memory 206668 kb
Host smart-e9685125-1ca1-4b60-b9b1-007527befaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1038235714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1038235714
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2128983532
Short name T227
Test name
Test status
Simulation time 84291694 ps
CPU time 2.13 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 214808 kb
Host smart-4b8973ce-07c4-4f18-ab90-a72aa4c2f466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128983532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2128983532
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1057850275
Short name T260
Test name
Test status
Simulation time 61892991 ps
CPU time 0.98 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:27 PM PDT 24
Peak memory 206452 kb
Host smart-f2a64cd8-99df-4170-9ce5-2e8b24ff7088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1057850275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1057850275
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2604974908
Short name T2780
Test name
Test status
Simulation time 60654832 ps
CPU time 0.69 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 206352 kb
Host smart-d7bce694-9b44-47b3-852c-f6a2577ec61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2604974908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2604974908
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1891228262
Short name T258
Test name
Test status
Simulation time 215791361 ps
CPU time 1.79 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 206544 kb
Host smart-99f96da7-1aa4-4a72-906b-0dbc7c87306f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1891228262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1891228262
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1377733736
Short name T226
Test name
Test status
Simulation time 81408321 ps
CPU time 2.37 seconds
Started Jul 16 06:58:23 PM PDT 24
Finished Jul 16 06:58:26 PM PDT 24
Peak memory 222456 kb
Host smart-6493710b-ad69-4803-bafc-15eed32be185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1377733736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1377733736
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2646768673
Short name T2783
Test name
Test status
Simulation time 926389688 ps
CPU time 3.06 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 206280 kb
Host smart-d58f7d4e-232e-4307-a328-da7e54d40e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2646768673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2646768673
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2805396418
Short name T2760
Test name
Test status
Simulation time 71939457 ps
CPU time 1.75 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 214808 kb
Host smart-1b2b12f7-7d12-439c-a812-72aff9ca2d3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805396418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2805396418
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.167896076
Short name T2781
Test name
Test status
Simulation time 41689803 ps
CPU time 0.79 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 206388 kb
Host smart-8afffaf5-1e16-4ba9-a885-9961af13445b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=167896076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.167896076
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2392497708
Short name T2817
Test name
Test status
Simulation time 68532250 ps
CPU time 0.67 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 206396 kb
Host smart-369dcc42-7438-486e-a5f5-d5d577fdbda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2392497708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2392497708
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3596753373
Short name T2804
Test name
Test status
Simulation time 225665589 ps
CPU time 1.7 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 206468 kb
Host smart-90389374-8c76-46a3-8d1d-e4eb8fbf1cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3596753373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3596753373
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.364837812
Short name T229
Test name
Test status
Simulation time 319651045 ps
CPU time 3.19 seconds
Started Jul 16 06:58:28 PM PDT 24
Finished Jul 16 06:58:34 PM PDT 24
Peak memory 214948 kb
Host smart-bc03ca32-6ed9-489a-acfc-b68f7f180fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=364837812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.364837812
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3480882229
Short name T2797
Test name
Test status
Simulation time 401756497 ps
CPU time 2.44 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206584 kb
Host smart-09c6a270-55d9-478f-b7e5-d022b2f9df5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3480882229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3480882229
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.92160120
Short name T2779
Test name
Test status
Simulation time 88213857 ps
CPU time 1.9 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 214808 kb
Host smart-aeceb2ef-61c3-404d-8451-3a1da2d97723
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92160120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev
_csr_mem_rw_with_rand_reset.92160120
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1807995442
Short name T249
Test name
Test status
Simulation time 133230702 ps
CPU time 1.11 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206412 kb
Host smart-7956d198-9b7b-4411-aec7-9d48165dd225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1807995442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1807995442
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1012738147
Short name T2761
Test name
Test status
Simulation time 207498349 ps
CPU time 1.4 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 206636 kb
Host smart-270aca67-0046-443e-9391-73ca2791433a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1012738147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1012738147
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1376721920
Short name T2855
Test name
Test status
Simulation time 256954739 ps
CPU time 2.36 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206580 kb
Host smart-38bfb498-da79-4631-85eb-4efa852d595c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1376721920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1376721920
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.95199373
Short name T2851
Test name
Test status
Simulation time 117202386 ps
CPU time 1.31 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 214832 kb
Host smart-b079a372-f904-4f5c-abe2-b0cb5ac3c5e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95199373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev
_csr_mem_rw_with_rand_reset.95199373
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1460963224
Short name T2762
Test name
Test status
Simulation time 71089720 ps
CPU time 0.85 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 206416 kb
Host smart-bf43f509-7c54-4d56-bc45-c4614fbd403c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1460963224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1460963224
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1026156970
Short name T288
Test name
Test status
Simulation time 44432960 ps
CPU time 0.69 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206256 kb
Host smart-7c87282e-7e5b-4f11-b608-aecf99bc5641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1026156970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1026156970
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.883502876
Short name T266
Test name
Test status
Simulation time 228465980 ps
CPU time 1.2 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206588 kb
Host smart-4d889721-69e9-4188-9c43-57a2c53201c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=883502876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.883502876
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4288109784
Short name T2807
Test name
Test status
Simulation time 205757674 ps
CPU time 2.19 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 214760 kb
Host smart-7ff67b2e-2516-41b6-9ba9-32395cc7e308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4288109784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4288109784
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4146801295
Short name T2808
Test name
Test status
Simulation time 63832492 ps
CPU time 0.81 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206388 kb
Host smart-a2f39ae6-1f52-4fc1-bddc-ad3d1fa60b91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4146801295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4146801295
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1732222004
Short name T2772
Test name
Test status
Simulation time 49782998 ps
CPU time 0.66 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 206368 kb
Host smart-5ed6ac42-fa1f-417f-95a0-987c7303d41d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1732222004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1732222004
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.720615520
Short name T2798
Test name
Test status
Simulation time 203400165 ps
CPU time 1.74 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:43 PM PDT 24
Peak memory 206548 kb
Host smart-31659871-c84b-4412-b1d7-65d29beed9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=720615520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.720615520
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3954089611
Short name T2768
Test name
Test status
Simulation time 189788796 ps
CPU time 2.11 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206680 kb
Host smart-1317571b-1645-4552-8e25-09665da6e62c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3954089611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3954089611
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1912324246
Short name T2836
Test name
Test status
Simulation time 1652481739 ps
CPU time 5.85 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:35 PM PDT 24
Peak memory 206572 kb
Host smart-1a9b7159-6997-48a0-b493-d954c4954e41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1912324246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1912324246
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.112393363
Short name T2789
Test name
Test status
Simulation time 64011862 ps
CPU time 1.09 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:41 PM PDT 24
Peak memory 216636 kb
Host smart-bd8e9c90-b6bc-4baf-a7ec-cb5f468a1d2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112393363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.112393363
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.336464682
Short name T2792
Test name
Test status
Simulation time 40018811 ps
CPU time 0.77 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:40 PM PDT 24
Peak memory 206364 kb
Host smart-c9ca95b6-d9fa-46ef-9a96-8674647a30c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=336464682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.336464682
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3017505502
Short name T2790
Test name
Test status
Simulation time 47715859 ps
CPU time 0.71 seconds
Started Jul 16 06:58:41 PM PDT 24
Finished Jul 16 06:58:43 PM PDT 24
Peak memory 206356 kb
Host smart-20458ff8-160d-48ff-b2ac-12ed1c0c91e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3017505502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3017505502
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.459723612
Short name T254
Test name
Test status
Simulation time 221124564 ps
CPU time 1.62 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:41 PM PDT 24
Peak memory 206580 kb
Host smart-b5457fce-a3ef-4d02-be70-5557aca367e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=459723612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.459723612
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3310401145
Short name T2826
Test name
Test status
Simulation time 336186178 ps
CPU time 2.54 seconds
Started Jul 16 06:58:37 PM PDT 24
Finished Jul 16 06:58:40 PM PDT 24
Peak memory 206544 kb
Host smart-da32dca5-f624-40b5-903f-6556eb3e0fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3310401145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3310401145
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1960205045
Short name T2852
Test name
Test status
Simulation time 144791698 ps
CPU time 1.73 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 214860 kb
Host smart-b7489e13-549e-4f79-8845-2af0754ef9e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960205045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1960205045
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1919021690
Short name T2848
Test name
Test status
Simulation time 83870474 ps
CPU time 0.98 seconds
Started Jul 16 06:58:37 PM PDT 24
Finished Jul 16 06:58:39 PM PDT 24
Peak memory 206456 kb
Host smart-d802c878-3038-47ed-a46a-b899b0da51a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1919021690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1919021690
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1006341278
Short name T2799
Test name
Test status
Simulation time 100558398 ps
CPU time 0.75 seconds
Started Jul 16 06:58:40 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206364 kb
Host smart-209f9b05-23e8-4a78-b171-fc61dec10f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1006341278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1006341278
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1043500426
Short name T2767
Test name
Test status
Simulation time 94304619 ps
CPU time 1.39 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206472 kb
Host smart-0f226bef-034a-476a-90a6-bf4558ae9140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1043500426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1043500426
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2900262735
Short name T2846
Test name
Test status
Simulation time 93912915 ps
CPU time 1.8 seconds
Started Jul 16 06:58:35 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 214792 kb
Host smart-9c0d4efd-4c4a-4b2b-ad8e-af9b40edd493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2900262735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2900262735
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3217766942
Short name T2778
Test name
Test status
Simulation time 1108394907 ps
CPU time 5.06 seconds
Started Jul 16 06:58:45 PM PDT 24
Finished Jul 16 06:58:51 PM PDT 24
Peak memory 206608 kb
Host smart-961815f8-b7fe-4be8-b042-36607913682c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3217766942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3217766942
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3838393440
Short name T2794
Test name
Test status
Simulation time 193281618 ps
CPU time 1.57 seconds
Started Jul 16 06:58:36 PM PDT 24
Finished Jul 16 06:58:39 PM PDT 24
Peak memory 214768 kb
Host smart-7c6521a9-2b74-4f01-b6e7-4df4985a3f0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838393440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3838393440
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.145069916
Short name T2775
Test name
Test status
Simulation time 55663748 ps
CPU time 0.8 seconds
Started Jul 16 06:58:42 PM PDT 24
Finished Jul 16 06:58:44 PM PDT 24
Peak memory 206352 kb
Host smart-a7cfb854-c274-4362-9453-da1979180d26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=145069916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.145069916
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.807546950
Short name T2763
Test name
Test status
Simulation time 170444678 ps
CPU time 1.42 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206584 kb
Host smart-8128e71e-9243-4af7-a439-2a90bb40d6af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=807546950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.807546950
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3610330378
Short name T2774
Test name
Test status
Simulation time 220130943 ps
CPU time 2.89 seconds
Started Jul 16 06:58:41 PM PDT 24
Finished Jul 16 06:58:45 PM PDT 24
Peak memory 214824 kb
Host smart-efbbb63a-1e06-48ef-865b-05b05921fca5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3610330378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3610330378
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2182912285
Short name T292
Test name
Test status
Simulation time 623873496 ps
CPU time 4.27 seconds
Started Jul 16 06:58:40 PM PDT 24
Finished Jul 16 06:58:46 PM PDT 24
Peak memory 206604 kb
Host smart-3167c545-3106-419a-a9fe-3692590e07ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2182912285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2182912285
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1754384833
Short name T2809
Test name
Test status
Simulation time 96263305 ps
CPU time 1.32 seconds
Started Jul 16 06:58:37 PM PDT 24
Finished Jul 16 06:58:40 PM PDT 24
Peak memory 214800 kb
Host smart-a869a867-4216-423d-b6bf-69593859b619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754384833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1754384833
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.186112371
Short name T2821
Test name
Test status
Simulation time 90337937 ps
CPU time 0.99 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:41 PM PDT 24
Peak memory 206464 kb
Host smart-bde40aff-0c60-4172-8845-b6f936fff189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=186112371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.186112371
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.41851558
Short name T2770
Test name
Test status
Simulation time 52388225 ps
CPU time 0.66 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:41 PM PDT 24
Peak memory 206276 kb
Host smart-f09a5ed9-af86-4af7-99bc-eb80589c800f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=41851558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.41851558
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1990198065
Short name T190
Test name
Test status
Simulation time 259112016 ps
CPU time 1.6 seconds
Started Jul 16 06:58:37 PM PDT 24
Finished Jul 16 06:58:40 PM PDT 24
Peak memory 206644 kb
Host smart-f076f0d0-5915-45f1-a590-596702ea1343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1990198065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1990198065
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.748002423
Short name T185
Test name
Test status
Simulation time 335539091 ps
CPU time 3.5 seconds
Started Jul 16 06:58:37 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 214784 kb
Host smart-7950de84-9189-4acf-bac9-4f77c3aa56a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=748002423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.748002423
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2890743396
Short name T267
Test name
Test status
Simulation time 1006332824 ps
CPU time 3.34 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:44 PM PDT 24
Peak memory 206540 kb
Host smart-61ce62c7-93d2-438e-93e0-1394f3f3b095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2890743396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2890743396
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.238747782
Short name T2764
Test name
Test status
Simulation time 98835925 ps
CPU time 1.86 seconds
Started Jul 16 06:58:07 PM PDT 24
Finished Jul 16 06:58:09 PM PDT 24
Peak memory 206508 kb
Host smart-4b6e65d2-3586-4986-a878-d86f9618ba34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=238747782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.238747782
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4245637117
Short name T2771
Test name
Test status
Simulation time 973633216 ps
CPU time 5.65 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:20 PM PDT 24
Peak memory 206504 kb
Host smart-24fb0be2-1b7d-4019-95e6-61f3b4faff16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4245637117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4245637117
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1778804782
Short name T2834
Test name
Test status
Simulation time 186277342 ps
CPU time 1.03 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 206208 kb
Host smart-e4ce928f-28ff-49de-b6af-594bd1225c5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1778804782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1778804782
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2756389147
Short name T2814
Test name
Test status
Simulation time 184893224 ps
CPU time 1.3 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:18 PM PDT 24
Peak memory 214800 kb
Host smart-212fcc34-8185-4559-9fbd-688016806be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756389147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2756389147
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3933881394
Short name T2833
Test name
Test status
Simulation time 149529679 ps
CPU time 1.09 seconds
Started Jul 16 06:58:13 PM PDT 24
Finished Jul 16 06:58:17 PM PDT 24
Peak memory 206472 kb
Host smart-e3bf88dd-ee33-473e-91b3-bb128985e7bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3933881394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3933881394
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1144577263
Short name T2830
Test name
Test status
Simulation time 32613587 ps
CPU time 0.66 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 206336 kb
Host smart-ae4614e5-4a10-409d-8928-6f9d350d1f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1144577263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1144577263
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4249511386
Short name T248
Test name
Test status
Simulation time 84910086 ps
CPU time 2.16 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:19 PM PDT 24
Peak memory 214808 kb
Host smart-cfbb33ae-b886-4d7b-b7de-161d80de13ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4249511386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4249511386
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3246935972
Short name T2757
Test name
Test status
Simulation time 482192146 ps
CPU time 4.29 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:19 PM PDT 24
Peak memory 206396 kb
Host smart-5d05c39b-4e42-4395-ae95-c08901c531e0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3246935972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3246935972
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3733954895
Short name T2811
Test name
Test status
Simulation time 184224507 ps
CPU time 1.78 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 206564 kb
Host smart-0141a6b8-1bec-4fe7-a8e2-5c3d43543afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3733954895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3733954895
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2866613513
Short name T2777
Test name
Test status
Simulation time 188844346 ps
CPU time 2.62 seconds
Started Jul 16 06:58:13 PM PDT 24
Finished Jul 16 06:58:17 PM PDT 24
Peak memory 214836 kb
Host smart-72e5d0b3-ce80-474a-8c2d-1c0bed5cc27c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2866613513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2866613513
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.966235362
Short name T219
Test name
Test status
Simulation time 1000260335 ps
CPU time 5.18 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:19 PM PDT 24
Peak memory 206468 kb
Host smart-e020d2d0-dddb-4b1e-8aea-ddd179bfaf12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=966235362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.966235362
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3939904388
Short name T278
Test name
Test status
Simulation time 90968844 ps
CPU time 0.76 seconds
Started Jul 16 06:58:40 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206352 kb
Host smart-bd61fa9a-75b1-47b1-86a8-bc203edb4db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3939904388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3939904388
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4244035883
Short name T2839
Test name
Test status
Simulation time 46730418 ps
CPU time 0.69 seconds
Started Jul 16 06:58:36 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 206368 kb
Host smart-3dc2de95-7c7e-4902-942a-b37db0841ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4244035883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4244035883
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1153512341
Short name T281
Test name
Test status
Simulation time 31541262 ps
CPU time 0.68 seconds
Started Jul 16 06:58:37 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 206364 kb
Host smart-4c59cfdb-62df-4396-9054-e0c177ad7257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1153512341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1153512341
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3112576057
Short name T2847
Test name
Test status
Simulation time 55326844 ps
CPU time 0.72 seconds
Started Jul 16 06:58:36 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 206364 kb
Host smart-bf675ba8-32c8-4e5e-8daa-6aa30610fbe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3112576057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3112576057
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2271755539
Short name T200
Test name
Test status
Simulation time 71188814 ps
CPU time 0.69 seconds
Started Jul 16 06:58:36 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 206340 kb
Host smart-a926b2a4-54ac-49c8-9474-ff10cb98008d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2271755539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2271755539
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2331248737
Short name T2840
Test name
Test status
Simulation time 42263602 ps
CPU time 0.68 seconds
Started Jul 16 06:58:36 PM PDT 24
Finished Jul 16 06:58:37 PM PDT 24
Peak memory 206288 kb
Host smart-c1af731c-6314-4339-809d-5246347bd8b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2331248737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2331248737
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2451101983
Short name T286
Test name
Test status
Simulation time 37927243 ps
CPU time 0.67 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206368 kb
Host smart-ef4f285f-bb03-48a6-bec4-310db0de4c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2451101983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2451101983
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3656030931
Short name T2805
Test name
Test status
Simulation time 35270879 ps
CPU time 0.67 seconds
Started Jul 16 06:58:37 PM PDT 24
Finished Jul 16 06:58:39 PM PDT 24
Peak memory 206356 kb
Host smart-3521fcdf-f9b9-422c-918d-7719e5df1165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3656030931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3656030931
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1988500531
Short name T290
Test name
Test status
Simulation time 35238048 ps
CPU time 0.65 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206356 kb
Host smart-d0e4258b-c9e7-4d0a-8fc5-131bdd2146ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1988500531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1988500531
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3700381256
Short name T251
Test name
Test status
Simulation time 118003867 ps
CPU time 3.39 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:16 PM PDT 24
Peak memory 206452 kb
Host smart-605bd7a4-e775-4bd0-b7ae-7ffa2894bea2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3700381256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3700381256
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3794295801
Short name T244
Test name
Test status
Simulation time 1614788511 ps
CPU time 6.69 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:20 PM PDT 24
Peak memory 206516 kb
Host smart-887c685e-1964-42db-86e5-cadd4be429df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3794295801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3794295801
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1503473201
Short name T2769
Test name
Test status
Simulation time 62508995 ps
CPU time 0.8 seconds
Started Jul 16 06:58:13 PM PDT 24
Finished Jul 16 06:58:16 PM PDT 24
Peak memory 206320 kb
Host smart-1b4e8381-0764-4043-ab07-4268c1667cdc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1503473201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1503473201
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2729629460
Short name T232
Test name
Test status
Simulation time 169462892 ps
CPU time 1.88 seconds
Started Jul 16 06:58:15 PM PDT 24
Finished Jul 16 06:58:19 PM PDT 24
Peak memory 214824 kb
Host smart-4504e042-efeb-4760-99b9-5c23e0e0ffaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729629460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2729629460
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2933479625
Short name T2810
Test name
Test status
Simulation time 110970625 ps
CPU time 0.95 seconds
Started Jul 16 06:58:11 PM PDT 24
Finished Jul 16 06:58:13 PM PDT 24
Peak memory 206364 kb
Host smart-6edd54e1-c5f1-4da8-ad19-9fad9bb20cc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2933479625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2933479625
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3445024761
Short name T2787
Test name
Test status
Simulation time 44134205 ps
CPU time 0.69 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:17 PM PDT 24
Peak memory 206336 kb
Host smart-f1ebb6d8-1cea-47ed-a34f-262d19df96fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3445024761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3445024761
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1288516516
Short name T2765
Test name
Test status
Simulation time 383316729 ps
CPU time 2.68 seconds
Started Jul 16 06:58:13 PM PDT 24
Finished Jul 16 06:58:17 PM PDT 24
Peak memory 206440 kb
Host smart-94e42f88-f876-47c1-9378-7beb340c46e6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1288516516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1288516516
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1316501527
Short name T2776
Test name
Test status
Simulation time 114051862 ps
CPU time 1.16 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:18 PM PDT 24
Peak memory 206592 kb
Host smart-5d911f46-8c8f-4868-b9b0-54dfc3cd4ff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1316501527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1316501527
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3924239216
Short name T2822
Test name
Test status
Simulation time 208054581 ps
CPU time 2.84 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:17 PM PDT 24
Peak memory 214848 kb
Host smart-e5627141-5a1c-47ad-b17b-154c456478cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3924239216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3924239216
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3384252010
Short name T295
Test name
Test status
Simulation time 881216822 ps
CPU time 5.26 seconds
Started Jul 16 06:58:15 PM PDT 24
Finished Jul 16 06:58:23 PM PDT 24
Peak memory 206584 kb
Host smart-f373f8f5-c6ad-40c3-a33b-6e643361f0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3384252010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3384252010
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.526440843
Short name T2832
Test name
Test status
Simulation time 40491382 ps
CPU time 0.67 seconds
Started Jul 16 06:58:37 PM PDT 24
Finished Jul 16 06:58:39 PM PDT 24
Peak memory 206228 kb
Host smart-0aa5cde2-e89b-4735-ae34-7d981f4eba71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=526440843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.526440843
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1631975850
Short name T2843
Test name
Test status
Simulation time 50147574 ps
CPU time 0.69 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206312 kb
Host smart-cf8389ef-7ca1-4493-9534-23b19568774e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1631975850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1631975850
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1567212228
Short name T2820
Test name
Test status
Simulation time 66550636 ps
CPU time 0.72 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:40 PM PDT 24
Peak memory 206352 kb
Host smart-1490a603-b344-473a-812a-e0fb671359d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1567212228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1567212228
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3430444597
Short name T2816
Test name
Test status
Simulation time 80645686 ps
CPU time 0.74 seconds
Started Jul 16 06:58:38 PM PDT 24
Finished Jul 16 06:58:40 PM PDT 24
Peak memory 206364 kb
Host smart-bb0307b8-40d7-4ec8-94fe-81f151ec3a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3430444597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3430444597
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3718558176
Short name T289
Test name
Test status
Simulation time 47564148 ps
CPU time 0.67 seconds
Started Jul 16 06:58:39 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 206308 kb
Host smart-f7fff4e8-34f9-4cbe-8ba6-e5a65497bb1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3718558176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3718558176
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3945513417
Short name T2801
Test name
Test status
Simulation time 34548024 ps
CPU time 0.7 seconds
Started Jul 16 06:58:36 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 206372 kb
Host smart-1b7e33fb-0417-4479-ada1-344133229f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3945513417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3945513417
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2956252399
Short name T2800
Test name
Test status
Simulation time 89688102 ps
CPU time 0.8 seconds
Started Jul 16 06:58:54 PM PDT 24
Finished Jul 16 06:58:55 PM PDT 24
Peak memory 206436 kb
Host smart-c54440f5-e481-451c-a2df-de8054d6330e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2956252399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2956252399
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3559511744
Short name T196
Test name
Test status
Simulation time 63749681 ps
CPU time 0.69 seconds
Started Jul 16 06:58:54 PM PDT 24
Finished Jul 16 06:58:55 PM PDT 24
Peak memory 206428 kb
Host smart-757dea87-63f8-42f8-9426-2872c459a33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3559511744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3559511744
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1301957754
Short name T2819
Test name
Test status
Simulation time 370022391 ps
CPU time 3.51 seconds
Started Jul 16 06:58:13 PM PDT 24
Finished Jul 16 06:58:19 PM PDT 24
Peak memory 206544 kb
Host smart-633bba17-68ed-4492-acf9-06da05e3212e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1301957754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1301957754
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1229420386
Short name T2841
Test name
Test status
Simulation time 1568535199 ps
CPU time 8.57 seconds
Started Jul 16 06:58:14 PM PDT 24
Finished Jul 16 06:58:24 PM PDT 24
Peak memory 206456 kb
Host smart-fb3029ba-db28-486c-8e69-c2a486f4d157
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1229420386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1229420386
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3515288476
Short name T2850
Test name
Test status
Simulation time 107561799 ps
CPU time 1.04 seconds
Started Jul 16 06:58:11 PM PDT 24
Finished Jul 16 06:58:12 PM PDT 24
Peak memory 206364 kb
Host smart-c827e6e7-c0a3-4eff-b19c-2a506a7dcadc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3515288476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3515288476
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2472895059
Short name T2759
Test name
Test status
Simulation time 79911630 ps
CPU time 1.73 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 214796 kb
Host smart-466a7dd9-6fdc-45c0-8d88-309afcd53ed2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472895059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2472895059
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3113455019
Short name T247
Test name
Test status
Simulation time 95756369 ps
CPU time 1.07 seconds
Started Jul 16 06:58:13 PM PDT 24
Finished Jul 16 06:58:16 PM PDT 24
Peak memory 206476 kb
Host smart-462779ba-302f-44eb-a844-b081566b4520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3113455019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3113455019
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.611287801
Short name T283
Test name
Test status
Simulation time 43811670 ps
CPU time 0.71 seconds
Started Jul 16 06:58:13 PM PDT 24
Finished Jul 16 06:58:16 PM PDT 24
Peak memory 206300 kb
Host smart-47158cf6-bc82-4d32-8ee6-dffcec925a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=611287801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.611287801
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1919023783
Short name T246
Test name
Test status
Simulation time 164497630 ps
CPU time 2.58 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:16 PM PDT 24
Peak memory 214784 kb
Host smart-8ef8955a-ac18-41b1-8199-de9b53945000
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1919023783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1919023783
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.752607044
Short name T2782
Test name
Test status
Simulation time 260834367 ps
CPU time 2.62 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:16 PM PDT 24
Peak memory 206432 kb
Host smart-df111769-0dbd-4560-b478-4ea2dbc4f2a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=752607044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.752607044
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1407360594
Short name T256
Test name
Test status
Simulation time 129063820 ps
CPU time 1.59 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 206540 kb
Host smart-0f5ddffc-d4a7-4291-b10a-ba5c7134f715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1407360594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1407360594
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3261828468
Short name T2828
Test name
Test status
Simulation time 218040375 ps
CPU time 2.61 seconds
Started Jul 16 06:58:13 PM PDT 24
Finished Jul 16 06:58:18 PM PDT 24
Peak memory 222160 kb
Host smart-02304af8-6a48-40f1-b440-408ca87c97f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3261828468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3261828468
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3017431121
Short name T2823
Test name
Test status
Simulation time 37804194 ps
CPU time 0.77 seconds
Started Jul 16 06:58:51 PM PDT 24
Finished Jul 16 06:58:52 PM PDT 24
Peak memory 206396 kb
Host smart-2e63a993-fdc5-4a3f-ad16-4ff58d84f6d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3017431121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3017431121
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2251467985
Short name T268
Test name
Test status
Simulation time 54978737 ps
CPU time 0.72 seconds
Started Jul 16 06:58:48 PM PDT 24
Finished Jul 16 06:58:49 PM PDT 24
Peak memory 206336 kb
Host smart-919893ca-3636-453d-9719-2645d3aa70ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2251467985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2251467985
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3917989328
Short name T2803
Test name
Test status
Simulation time 43715531 ps
CPU time 0.64 seconds
Started Jul 16 06:58:49 PM PDT 24
Finished Jul 16 06:58:50 PM PDT 24
Peak memory 206404 kb
Host smart-af9d1ee0-4d6c-467b-be69-2ca0ed160ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3917989328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3917989328
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3056636708
Short name T279
Test name
Test status
Simulation time 82830999 ps
CPU time 0.71 seconds
Started Jul 16 06:58:51 PM PDT 24
Finished Jul 16 06:58:52 PM PDT 24
Peak memory 206368 kb
Host smart-cb909825-34cb-45a3-9ee9-d1de78707e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3056636708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3056636708
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1105212410
Short name T195
Test name
Test status
Simulation time 63697780 ps
CPU time 0.72 seconds
Started Jul 16 06:58:50 PM PDT 24
Finished Jul 16 06:58:51 PM PDT 24
Peak memory 206304 kb
Host smart-f8cd3a43-23c8-4cdd-bcd2-e6c9fd1618f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1105212410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1105212410
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2746135463
Short name T285
Test name
Test status
Simulation time 38247530 ps
CPU time 0.66 seconds
Started Jul 16 06:58:49 PM PDT 24
Finished Jul 16 06:58:51 PM PDT 24
Peak memory 206268 kb
Host smart-9b1eb62a-c8d8-4080-be08-59d189632d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2746135463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2746135463
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3412100246
Short name T198
Test name
Test status
Simulation time 117867785 ps
CPU time 0.73 seconds
Started Jul 16 06:58:49 PM PDT 24
Finished Jul 16 06:58:51 PM PDT 24
Peak memory 206372 kb
Host smart-badffe78-e9f0-4927-82f6-a3b3bd89c743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412100246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3412100246
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1419453164
Short name T2844
Test name
Test status
Simulation time 91665280 ps
CPU time 0.72 seconds
Started Jul 16 06:58:52 PM PDT 24
Finished Jul 16 06:58:53 PM PDT 24
Peak memory 206372 kb
Host smart-237f7fb7-5071-4cae-bb5c-9e9615b1d8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1419453164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1419453164
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1907437420
Short name T270
Test name
Test status
Simulation time 84218095 ps
CPU time 0.71 seconds
Started Jul 16 06:58:52 PM PDT 24
Finished Jul 16 06:58:53 PM PDT 24
Peak memory 206396 kb
Host smart-3e2d41c4-4585-450d-a2fd-89039ff50dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1907437420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1907437420
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4105654991
Short name T265
Test name
Test status
Simulation time 251728873 ps
CPU time 2.07 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 218200 kb
Host smart-a81f877a-8fa6-4274-8e21-a73865c20cb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105654991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.4105654991
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.770557115
Short name T2802
Test name
Test status
Simulation time 71787123 ps
CPU time 1.1 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:27 PM PDT 24
Peak memory 206428 kb
Host smart-669ee5f2-1a19-4141-93cd-bff241e49d21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=770557115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.770557115
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1883888103
Short name T282
Test name
Test status
Simulation time 47277029 ps
CPU time 0.72 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 206328 kb
Host smart-9cbf6cd7-52da-4e2f-9793-f1d879978f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1883888103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1883888103
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1863730553
Short name T2842
Test name
Test status
Simulation time 163026486 ps
CPU time 1.77 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 206612 kb
Host smart-648b555b-10ee-436b-8516-365d2744d1da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1863730553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1863730553
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3547650819
Short name T225
Test name
Test status
Simulation time 152405352 ps
CPU time 1.97 seconds
Started Jul 16 06:58:12 PM PDT 24
Finished Jul 16 06:58:16 PM PDT 24
Peak memory 214612 kb
Host smart-a1283e93-9d4e-4615-b65a-8379d043d2a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3547650819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3547650819
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1041476760
Short name T297
Test name
Test status
Simulation time 1058963458 ps
CPU time 5.77 seconds
Started Jul 16 06:58:23 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 206636 kb
Host smart-0353073d-3783-48ea-9fe8-e9046208a1b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1041476760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1041476760
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4237587329
Short name T228
Test name
Test status
Simulation time 157986526 ps
CPU time 1.79 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 214836 kb
Host smart-c4f43f57-b298-4f66-8a56-caa824894a94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237587329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.4237587329
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3436421266
Short name T252
Test name
Test status
Simulation time 72919526 ps
CPU time 0.85 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206376 kb
Host smart-c0ce9ffa-c411-4817-96f1-41ec88f1c865
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3436421266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3436421266
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.43870117
Short name T277
Test name
Test status
Simulation time 41885630 ps
CPU time 0.68 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206292 kb
Host smart-a5e872aa-8288-4be9-912f-2d99c0b84344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=43870117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.43870117
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4097940695
Short name T257
Test name
Test status
Simulation time 236495155 ps
CPU time 1.93 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 206512 kb
Host smart-8889e72d-eabf-40da-aff8-cb7f34a7ef3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4097940695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4097940695
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1345513371
Short name T2793
Test name
Test status
Simulation time 149715660 ps
CPU time 1.73 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 206616 kb
Host smart-f7bb7e91-9166-4032-9a10-510cdc4d1740
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1345513371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1345513371
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3834530379
Short name T218
Test name
Test status
Simulation time 278093035 ps
CPU time 2.49 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206568 kb
Host smart-ab32b2e5-936f-488a-acd0-a174ea395488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3834530379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3834530379
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1007872074
Short name T2818
Test name
Test status
Simulation time 174058793 ps
CPU time 2.14 seconds
Started Jul 16 06:58:23 PM PDT 24
Finished Jul 16 06:58:26 PM PDT 24
Peak memory 214860 kb
Host smart-ecfb5a76-5a0b-40d7-a6e8-adabd6e50d64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007872074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1007872074
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1717031862
Short name T2788
Test name
Test status
Simulation time 95661759 ps
CPU time 0.89 seconds
Started Jul 16 06:58:24 PM PDT 24
Finished Jul 16 06:58:25 PM PDT 24
Peak memory 206388 kb
Host smart-4c69b6d2-f654-4460-b817-45e8cfb1a8ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1717031862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1717031862
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2219640475
Short name T2813
Test name
Test status
Simulation time 39923018 ps
CPU time 0.68 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 206332 kb
Host smart-2ef790ae-ab9b-4e02-a371-5cae441e2adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2219640475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2219640475
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.751242729
Short name T214
Test name
Test status
Simulation time 81660249 ps
CPU time 0.96 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 206460 kb
Host smart-9be7ab82-742e-414c-8ef1-20ee65ee668d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=751242729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.751242729
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1687183922
Short name T224
Test name
Test status
Simulation time 276177697 ps
CPU time 2.81 seconds
Started Jul 16 06:58:24 PM PDT 24
Finished Jul 16 06:58:27 PM PDT 24
Peak memory 222612 kb
Host smart-5c289b52-9ba3-4a7b-b3a2-6ccd880f2812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1687183922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1687183922
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.287393047
Short name T2827
Test name
Test status
Simulation time 69715101 ps
CPU time 1.83 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 214820 kb
Host smart-98580c16-9a32-40aa-8768-ba675b0d130e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287393047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.287393047
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2592766509
Short name T2796
Test name
Test status
Simulation time 54589989 ps
CPU time 0.86 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 206320 kb
Host smart-d9962734-6031-4d6b-bcd8-fb796c073f6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2592766509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2592766509
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3616750488
Short name T284
Test name
Test status
Simulation time 43848616 ps
CPU time 0.67 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 206368 kb
Host smart-23bae57d-a067-4db2-8bfa-479abebf9735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3616750488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3616750488
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1444859580
Short name T2806
Test name
Test status
Simulation time 105850303 ps
CPU time 1.16 seconds
Started Jul 16 06:58:24 PM PDT 24
Finished Jul 16 06:58:26 PM PDT 24
Peak memory 206500 kb
Host smart-95cfc514-4467-454c-b15d-3390af3ee7c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1444859580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1444859580
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3473292804
Short name T2766
Test name
Test status
Simulation time 239423403 ps
CPU time 3 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 214828 kb
Host smart-091859f8-6e34-4bc4-b735-28db9da855f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3473292804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3473292804
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.516701040
Short name T298
Test name
Test status
Simulation time 498965052 ps
CPU time 2.63 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 206516 kb
Host smart-0958caae-add9-4d4b-ab24-37a95da9c6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=516701040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.516701040
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2941715303
Short name T2791
Test name
Test status
Simulation time 151803012 ps
CPU time 1.35 seconds
Started Jul 16 06:58:24 PM PDT 24
Finished Jul 16 06:58:26 PM PDT 24
Peak memory 214820 kb
Host smart-5b29416d-f521-44c8-89f4-571a5a3bec4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941715303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2941715303
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2531861312
Short name T2786
Test name
Test status
Simulation time 40385248 ps
CPU time 0.83 seconds
Started Jul 16 06:58:24 PM PDT 24
Finished Jul 16 06:58:26 PM PDT 24
Peak memory 206416 kb
Host smart-08a262cc-f1e8-4e4d-859a-d67d7bd27d1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2531861312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2531861312
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1515220811
Short name T2849
Test name
Test status
Simulation time 105451706 ps
CPU time 0.77 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 206340 kb
Host smart-b7a8c564-d00a-49f6-a8f4-6c01d94b80d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1515220811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1515220811
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2846334772
Short name T255
Test name
Test status
Simulation time 203221491 ps
CPU time 1.23 seconds
Started Jul 16 06:58:26 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 206592 kb
Host smart-6eeaba38-c7af-4f0a-a936-98a8adb5f59b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2846334772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2846334772
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2227234368
Short name T186
Test name
Test status
Simulation time 56550826 ps
CPU time 1.5 seconds
Started Jul 16 06:58:27 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 206652 kb
Host smart-e624fdb2-822e-4f72-b382-01144ed20604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2227234368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2227234368
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4172941354
Short name T296
Test name
Test status
Simulation time 943943327 ps
CPU time 5.16 seconds
Started Jul 16 06:58:25 PM PDT 24
Finished Jul 16 06:58:32 PM PDT 24
Peak memory 206284 kb
Host smart-7a24a2d7-6b4d-430b-9a3e-2f46d8693953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4172941354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.4172941354
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2988993438
Short name T842
Test name
Test status
Simulation time 52768540 ps
CPU time 0.68 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:46:52 PM PDT 24
Peak memory 206880 kb
Host smart-1a216ee2-4b75-400f-97be-9a4f7ee52a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2988993438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2988993438
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2810877923
Short name T2629
Test name
Test status
Simulation time 4337390051 ps
CPU time 5.26 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:46:42 PM PDT 24
Peak memory 206896 kb
Host smart-3a0f5902-8ab1-4715-8be5-454c6c6ee445
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2810877923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2810877923
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.73232365
Short name T2165
Test name
Test status
Simulation time 13397051825 ps
CPU time 12.27 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 206876 kb
Host smart-b224a0d3-3572-4b2e-9bdf-9f0d8d2d9696
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=73232365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.73232365
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3937081574
Short name T2072
Test name
Test status
Simulation time 23365054802 ps
CPU time 24.67 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:47:01 PM PDT 24
Peak memory 206928 kb
Host smart-cf2c9412-c9b6-411b-963d-bec084dda833
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3937081574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3937081574
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1742847882
Short name T2580
Test name
Test status
Simulation time 153469194 ps
CPU time 0.78 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:46:37 PM PDT 24
Peak memory 206872 kb
Host smart-5bac546d-2a93-4b09-8edd-55b072dffb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17428
47882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1742847882
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.181019448
Short name T722
Test name
Test status
Simulation time 214195171 ps
CPU time 0.89 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:46:38 PM PDT 24
Peak memory 206884 kb
Host smart-5230dc34-2a79-4067-ab9f-4367594c9ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18101
9448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.181019448
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.2736270030
Short name T1000
Test name
Test status
Simulation time 317881934 ps
CPU time 1.12 seconds
Started Jul 16 06:46:37 PM PDT 24
Finished Jul 16 06:46:40 PM PDT 24
Peak memory 207028 kb
Host smart-cac6d30b-0d02-421f-aa53-f7158a52ac5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27362
70030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.2736270030
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3039621669
Short name T2162
Test name
Test status
Simulation time 621662424 ps
CPU time 1.53 seconds
Started Jul 16 06:46:38 PM PDT 24
Finished Jul 16 06:46:41 PM PDT 24
Peak memory 206772 kb
Host smart-a93551a3-4551-4e85-b558-dccf0391ff47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30396
21669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3039621669
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1981096516
Short name T1359
Test name
Test status
Simulation time 8051152654 ps
CPU time 14.61 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:46:53 PM PDT 24
Peak memory 207072 kb
Host smart-56436347-e305-4649-84e1-7badc87dc34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19810
96516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1981096516
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3655260733
Short name T714
Test name
Test status
Simulation time 444953553 ps
CPU time 1.23 seconds
Started Jul 16 06:46:40 PM PDT 24
Finished Jul 16 06:46:42 PM PDT 24
Peak memory 206776 kb
Host smart-e46680bf-33fc-41d5-b4aa-2560cc3c8e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36552
60733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3655260733
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.4086970723
Short name T1378
Test name
Test status
Simulation time 158266195 ps
CPU time 0.77 seconds
Started Jul 16 06:46:38 PM PDT 24
Finished Jul 16 06:46:40 PM PDT 24
Peak memory 206860 kb
Host smart-80bdf76d-fd6a-49bc-ad9a-e3f4aa2d29de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40869
70723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.4086970723
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1179424767
Short name T2145
Test name
Test status
Simulation time 5109190892 ps
CPU time 36.65 seconds
Started Jul 16 06:46:38 PM PDT 24
Finished Jul 16 06:47:16 PM PDT 24
Peak memory 206992 kb
Host smart-1a623d89-ab58-4e9d-a2be-e3b0d68b7922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11794
24767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1179424767
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1574409742
Short name T2262
Test name
Test status
Simulation time 49336159 ps
CPU time 0.66 seconds
Started Jul 16 06:46:40 PM PDT 24
Finished Jul 16 06:46:41 PM PDT 24
Peak memory 206852 kb
Host smart-4962cca5-3105-4e45-b310-27896ed77711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15744
09742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1574409742
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1813015028
Short name T373
Test name
Test status
Simulation time 912328707 ps
CPU time 2.13 seconds
Started Jul 16 06:46:36 PM PDT 24
Finished Jul 16 06:46:39 PM PDT 24
Peak memory 207088 kb
Host smart-29ddcc64-5c7b-4de5-9c67-f722c2c6e855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130
15028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1813015028
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1862547189
Short name T1266
Test name
Test status
Simulation time 329968917 ps
CPU time 2.03 seconds
Started Jul 16 06:46:40 PM PDT 24
Finished Jul 16 06:46:43 PM PDT 24
Peak memory 206968 kb
Host smart-0acfb2f5-a0da-4510-b17e-6f440832c907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18625
47189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1862547189
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3654269562
Short name T1488
Test name
Test status
Simulation time 108229363951 ps
CPU time 147.62 seconds
Started Jul 16 06:46:39 PM PDT 24
Finished Jul 16 06:49:08 PM PDT 24
Peak memory 207052 kb
Host smart-e8c8d993-1b90-4e5f-913f-e39a42824db2
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3654269562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3654269562
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.399822712
Short name T1713
Test name
Test status
Simulation time 111053839648 ps
CPU time 144.27 seconds
Started Jul 16 06:46:40 PM PDT 24
Finished Jul 16 06:49:05 PM PDT 24
Peak memory 207112 kb
Host smart-7d75246f-3d4f-4ac8-af2b-d95e9ad74977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399822712 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.399822712
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.132505528
Short name T473
Test name
Test status
Simulation time 106097095436 ps
CPU time 162.32 seconds
Started Jul 16 06:46:38 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 207072 kb
Host smart-456a028a-7072-4a02-ade0-2009d5aa4301
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=132505528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.132505528
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.666249908
Short name T204
Test name
Test status
Simulation time 119157120807 ps
CPU time 161.46 seconds
Started Jul 16 06:46:39 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 207072 kb
Host smart-ceb12de8-b533-4747-acbf-07b87a3d0ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666249908 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.666249908
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.4258191842
Short name T1059
Test name
Test status
Simulation time 111226208657 ps
CPU time 158.88 seconds
Started Jul 16 06:46:38 PM PDT 24
Finished Jul 16 06:49:18 PM PDT 24
Peak memory 207092 kb
Host smart-28655e5b-2194-4a05-8ae1-1e055fe2638f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42581
91842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.4258191842
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3717987572
Short name T1790
Test name
Test status
Simulation time 230786376 ps
CPU time 0.92 seconds
Started Jul 16 06:46:38 PM PDT 24
Finished Jul 16 06:46:40 PM PDT 24
Peak memory 206884 kb
Host smart-688f28d1-92e7-48af-b3a6-498406edbbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37179
87572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3717987572
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2984346670
Short name T1419
Test name
Test status
Simulation time 151911313 ps
CPU time 0.73 seconds
Started Jul 16 06:46:39 PM PDT 24
Finished Jul 16 06:46:41 PM PDT 24
Peak memory 206852 kb
Host smart-f284bd14-40f7-41ff-b131-deb06cf3bdfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29843
46670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2984346670
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.788992246
Short name T2472
Test name
Test status
Simulation time 229226771 ps
CPU time 0.99 seconds
Started Jul 16 06:46:38 PM PDT 24
Finished Jul 16 06:46:41 PM PDT 24
Peak memory 206872 kb
Host smart-8787f131-7875-4d0a-a575-20e1dd40317e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78899
2246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.788992246
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.3347845981
Short name T2208
Test name
Test status
Simulation time 12200475805 ps
CPU time 36.93 seconds
Started Jul 16 06:46:42 PM PDT 24
Finished Jul 16 06:47:19 PM PDT 24
Peak memory 207128 kb
Host smart-505add70-09b4-4712-b60d-bda667190baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33478
45981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.3347845981
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3723939021
Short name T1404
Test name
Test status
Simulation time 208947373 ps
CPU time 0.86 seconds
Started Jul 16 06:46:42 PM PDT 24
Finished Jul 16 06:46:44 PM PDT 24
Peak memory 206860 kb
Host smart-142896f7-4f84-4f4b-bb08-4f5898c2c9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37239
39021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3723939021
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1582681939
Short name T68
Test name
Test status
Simulation time 433937117 ps
CPU time 1.23 seconds
Started Jul 16 06:46:39 PM PDT 24
Finished Jul 16 06:46:41 PM PDT 24
Peak memory 206892 kb
Host smart-f0d8fb90-9cda-4fbf-a720-c5ac180244d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826
81939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1582681939
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.136342771
Short name T1066
Test name
Test status
Simulation time 23372260395 ps
CPU time 24.74 seconds
Started Jul 16 06:46:42 PM PDT 24
Finished Jul 16 06:47:07 PM PDT 24
Peak memory 206928 kb
Host smart-27ffaa5c-e5d8-402f-b000-b3e563972b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13634
2771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.136342771
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.602367392
Short name T794
Test name
Test status
Simulation time 3362122339 ps
CPU time 4.14 seconds
Started Jul 16 06:46:42 PM PDT 24
Finished Jul 16 06:46:47 PM PDT 24
Peak memory 206836 kb
Host smart-a668c661-0bcb-4a19-9591-b989c865852e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60236
7392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.602367392
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.1824159561
Short name T1261
Test name
Test status
Simulation time 9205529016 ps
CPU time 88.65 seconds
Started Jul 16 06:46:50 PM PDT 24
Finished Jul 16 06:48:20 PM PDT 24
Peak memory 207124 kb
Host smart-5b6a80d4-6a08-4a4d-89d3-c9994d022583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18241
59561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.1824159561
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2942735667
Short name T1874
Test name
Test status
Simulation time 6439639175 ps
CPU time 49.67 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206980 kb
Host smart-62ab39a5-2039-48f7-a7ea-a91cbe462184
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2942735667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2942735667
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2569819163
Short name T811
Test name
Test status
Simulation time 244718172 ps
CPU time 0.93 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206848 kb
Host smart-f776fc9d-0d89-4718-8c4b-5606c499a964
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2569819163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2569819163
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.108425282
Short name T1842
Test name
Test status
Simulation time 191854171 ps
CPU time 0.85 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 206804 kb
Host smart-a2974129-745b-43e1-aa01-7319439318c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10842
5282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.108425282
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2644284912
Short name T1186
Test name
Test status
Simulation time 5158345216 ps
CPU time 133.39 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:49:07 PM PDT 24
Peak memory 207104 kb
Host smart-4246b553-54ca-4457-a7bb-4ac235f474f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26442
84912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2644284912
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1378729910
Short name T2229
Test name
Test status
Simulation time 4968116859 ps
CPU time 36.68 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:47:27 PM PDT 24
Peak memory 207000 kb
Host smart-842d1d5b-716d-4237-9c11-3da1c9ac77dd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1378729910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1378729910
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.2985856003
Short name T1688
Test name
Test status
Simulation time 211692414 ps
CPU time 0.89 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206808 kb
Host smart-695f86f7-2f5a-4d2c-8c25-c6cae14d7dde
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2985856003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.2985856003
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1647443714
Short name T1088
Test name
Test status
Simulation time 141020769 ps
CPU time 0.85 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 206868 kb
Host smart-cbc7f949-fe57-4630-8c13-bf8e410079af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16474
43714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1647443714
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2359953332
Short name T67
Test name
Test status
Simulation time 538563630 ps
CPU time 1.48 seconds
Started Jul 16 06:46:50 PM PDT 24
Finished Jul 16 06:46:53 PM PDT 24
Peak memory 206860 kb
Host smart-5b892fe2-0b2a-4daa-90f3-9d46b7fa6949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23599
53332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2359953332
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3530196292
Short name T2705
Test name
Test status
Simulation time 180161062 ps
CPU time 0.86 seconds
Started Jul 16 06:46:50 PM PDT 24
Finished Jul 16 06:46:53 PM PDT 24
Peak memory 206876 kb
Host smart-77d50f53-318e-43ca-9474-c67d7442a004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35301
96292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3530196292
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1538845142
Short name T847
Test name
Test status
Simulation time 180036397 ps
CPU time 0.85 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 206860 kb
Host smart-2dd34398-20f5-4394-9619-03058362489e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15388
45142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1538845142
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2611864701
Short name T629
Test name
Test status
Simulation time 145177424 ps
CPU time 0.76 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:46:49 PM PDT 24
Peak memory 206816 kb
Host smart-771b82fe-0f5a-4a25-b1f8-cf8af1856568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
64701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2611864701
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2535713422
Short name T1801
Test name
Test status
Simulation time 192770553 ps
CPU time 0.89 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 206848 kb
Host smart-2d6c6fbc-58fe-4866-b880-59c359af2c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25357
13422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2535713422
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.514712403
Short name T484
Test name
Test status
Simulation time 183411820 ps
CPU time 0.98 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206860 kb
Host smart-d56d5b79-10b1-4a6a-b476-319b84fa1731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51471
2403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.514712403
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2025106896
Short name T2754
Test name
Test status
Simulation time 252141007 ps
CPU time 0.99 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 206820 kb
Host smart-c60b4a6e-b556-4296-9289-16b3119a1287
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2025106896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2025106896
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1393968667
Short name T1256
Test name
Test status
Simulation time 185170075 ps
CPU time 0.88 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:46:52 PM PDT 24
Peak memory 206780 kb
Host smart-2801ce28-3dfc-487a-b18c-e22dc6206ca9
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1393968667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1393968667
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.4181289208
Short name T192
Test name
Test status
Simulation time 197660412 ps
CPU time 0.91 seconds
Started Jul 16 06:46:50 PM PDT 24
Finished Jul 16 06:46:53 PM PDT 24
Peak memory 206856 kb
Host smart-90d94f29-45f7-4986-b254-e6b49a034485
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4181289208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.4181289208
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.811331381
Short name T2269
Test name
Test status
Simulation time 34472954 ps
CPU time 0.65 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206808 kb
Host smart-8670a9ee-dbf0-4448-8cc2-2ae7866ed4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81133
1381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.811331381
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2657956785
Short name T2690
Test name
Test status
Simulation time 10754825408 ps
CPU time 23.17 seconds
Started Jul 16 06:46:50 PM PDT 24
Finished Jul 16 06:47:15 PM PDT 24
Peak memory 207120 kb
Host smart-f113dea8-6d04-4e28-b1e9-82d9f8dafdde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
56785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2657956785
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1408007220
Short name T1270
Test name
Test status
Simulation time 145908850 ps
CPU time 0.79 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:46:49 PM PDT 24
Peak memory 206868 kb
Host smart-6154148d-9efc-4a05-ab99-c25c1650d6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14080
07220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1408007220
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1578723399
Short name T1762
Test name
Test status
Simulation time 162173560 ps
CPU time 0.8 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:46:52 PM PDT 24
Peak memory 206744 kb
Host smart-6b0164a0-cc97-4fd1-8906-096a6dd005fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
23399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1578723399
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.3187422128
Short name T166
Test name
Test status
Simulation time 13817082170 ps
CPU time 94.95 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:48:26 PM PDT 24
Peak memory 207068 kb
Host smart-df56d8cb-371e-47fd-a721-2f4bbee6c587
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3187422128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.3187422128
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.4935454
Short name T149
Test name
Test status
Simulation time 7488417990 ps
CPU time 204.35 seconds
Started Jul 16 06:46:50 PM PDT 24
Finished Jul 16 06:50:17 PM PDT 24
Peak memory 207152 kb
Host smart-7c3a6840-3a70-4872-99d8-377aed561850
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4935454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.4935454
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.527500096
Short name T690
Test name
Test status
Simulation time 16154778336 ps
CPU time 325.47 seconds
Started Jul 16 06:46:52 PM PDT 24
Finished Jul 16 06:52:19 PM PDT 24
Peak memory 207096 kb
Host smart-ba59e181-1250-4827-b31b-b74beb8e9386
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=527500096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.527500096
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.2115566646
Short name T2537
Test name
Test status
Simulation time 221775944 ps
CPU time 0.85 seconds
Started Jul 16 06:46:52 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206864 kb
Host smart-dc694632-5e18-4233-84db-dc63204b1858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21155
66646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.2115566646
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.245005966
Short name T1940
Test name
Test status
Simulation time 182615705 ps
CPU time 0.82 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:46:52 PM PDT 24
Peak memory 206776 kb
Host smart-d261dd73-c451-4fd8-abc0-f0c8f1a3ba26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24500
5966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.245005966
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2644692076
Short name T366
Test name
Test status
Simulation time 184579175 ps
CPU time 0.89 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:46:52 PM PDT 24
Peak memory 206800 kb
Host smart-53eb2c78-44a8-4d26-bc47-150de4342b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
92076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2644692076
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3188877461
Short name T2452
Test name
Test status
Simulation time 371206057 ps
CPU time 1.22 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:46:49 PM PDT 24
Peak memory 206852 kb
Host smart-a7747d3b-55d7-4f79-83f2-cc3a848a3891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31888
77461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3188877461
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2471351539
Short name T1885
Test name
Test status
Simulation time 192734447 ps
CPU time 0.87 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:46:50 PM PDT 24
Peak memory 206864 kb
Host smart-092e38c6-2535-492e-8a04-d1c9e0ef30e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24713
51539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2471351539
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.386988134
Short name T875
Test name
Test status
Simulation time 215148190 ps
CPU time 0.83 seconds
Started Jul 16 06:46:50 PM PDT 24
Finished Jul 16 06:46:53 PM PDT 24
Peak memory 206852 kb
Host smart-026c1a0a-3f81-4825-a600-330bfcd35dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38698
8134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.386988134
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.841258827
Short name T1498
Test name
Test status
Simulation time 189749613 ps
CPU time 0.84 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:46:51 PM PDT 24
Peak memory 206852 kb
Host smart-b6882443-9cab-454a-b203-ba988fca8fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84125
8827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.841258827
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1000977504
Short name T1924
Test name
Test status
Simulation time 198228589 ps
CPU time 0.86 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206808 kb
Host smart-436619b3-72d0-447a-a07f-b7cdf13f611a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10009
77504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1000977504
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3180068003
Short name T1635
Test name
Test status
Simulation time 2856962896 ps
CPU time 74.79 seconds
Started Jul 16 06:46:47 PM PDT 24
Finished Jul 16 06:48:04 PM PDT 24
Peak memory 207088 kb
Host smart-6166a561-a86b-45ab-8f4b-cd52c5b28021
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3180068003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3180068003
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2052730619
Short name T1776
Test name
Test status
Simulation time 147794390 ps
CPU time 0.78 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206756 kb
Host smart-7e034bf8-8edb-4924-9aa2-b551e413e163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20527
30619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2052730619
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3817212109
Short name T556
Test name
Test status
Simulation time 177183721 ps
CPU time 0.87 seconds
Started Jul 16 06:46:51 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206732 kb
Host smart-59b8b3e9-bf8e-4348-86b0-bd1402d7ca98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38172
12109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3817212109
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.3646387850
Short name T2177
Test name
Test status
Simulation time 631370257 ps
CPU time 1.63 seconds
Started Jul 16 06:46:50 PM PDT 24
Finished Jul 16 06:46:54 PM PDT 24
Peak memory 206736 kb
Host smart-95a249fd-e5d3-4d9d-95bb-87470dabbfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36463
87850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.3646387850
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1670205086
Short name T1518
Test name
Test status
Simulation time 5128190078 ps
CPU time 36.34 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:47:26 PM PDT 24
Peak memory 207120 kb
Host smart-8ceb86af-a7fe-4b45-8c04-506762d43065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16702
05086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1670205086
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3204407352
Short name T715
Test name
Test status
Simulation time 32988098 ps
CPU time 0.72 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206844 kb
Host smart-9d4d6239-19f5-497c-b873-6acba579813b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3204407352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3204407352
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.257710866
Short name T215
Test name
Test status
Simulation time 3535195407 ps
CPU time 4.39 seconds
Started Jul 16 06:46:48 PM PDT 24
Finished Jul 16 06:46:55 PM PDT 24
Peak memory 207104 kb
Host smart-f4cd7ed9-62d2-45eb-a6cd-d20861a79825
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=257710866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.257710866
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2060256480
Short name T947
Test name
Test status
Simulation time 13367951772 ps
CPU time 12.63 seconds
Started Jul 16 06:46:49 PM PDT 24
Finished Jul 16 06:47:04 PM PDT 24
Peak memory 206988 kb
Host smart-1b1e8683-77fd-436f-8a17-b62d45b56707
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2060256480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2060256480
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2613396861
Short name T1661
Test name
Test status
Simulation time 23365726367 ps
CPU time 23.53 seconds
Started Jul 16 06:47:04 PM PDT 24
Finished Jul 16 06:47:28 PM PDT 24
Peak memory 206944 kb
Host smart-88fb7487-f729-4d24-9d52-52852b27ca44
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2613396861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.2613396861
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1176870604
Short name T2200
Test name
Test status
Simulation time 153722440 ps
CPU time 0.77 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:02 PM PDT 24
Peak memory 206880 kb
Host smart-1aa0eda3-60f7-4f26-b8d5-df92b390bc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11768
70604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1176870604
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1505507498
Short name T51
Test name
Test status
Simulation time 239322121 ps
CPU time 0.89 seconds
Started Jul 16 06:47:04 PM PDT 24
Finished Jul 16 06:47:05 PM PDT 24
Peak memory 206876 kb
Host smart-2ddfd0c6-e590-4d96-898a-96abff296736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15055
07498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1505507498
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.4283774463
Short name T1543
Test name
Test status
Simulation time 159083298 ps
CPU time 0.79 seconds
Started Jul 16 06:47:01 PM PDT 24
Finished Jul 16 06:47:03 PM PDT 24
Peak memory 206804 kb
Host smart-72899326-e9e6-4f26-8ea8-92acdc4a39b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42837
74463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.4283774463
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2062238004
Short name T2582
Test name
Test status
Simulation time 567287764 ps
CPU time 1.49 seconds
Started Jul 16 06:46:57 PM PDT 24
Finished Jul 16 06:46:59 PM PDT 24
Peak memory 207092 kb
Host smart-7475e942-44a9-460c-8dd2-17c5d1eb93c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
38004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2062238004
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1935183104
Short name T1264
Test name
Test status
Simulation time 1425027378 ps
CPU time 3.29 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:05 PM PDT 24
Peak memory 207084 kb
Host smart-d637c30c-2992-44f7-b9db-c62388f65358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
83104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1935183104
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1496207351
Short name T1379
Test name
Test status
Simulation time 363986506 ps
CPU time 1.18 seconds
Started Jul 16 06:46:58 PM PDT 24
Finished Jul 16 06:46:59 PM PDT 24
Peak memory 206888 kb
Host smart-9af9c7c8-8c35-49e7-aa0f-a31c571c00d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14962
07351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1496207351
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3597414576
Short name T2444
Test name
Test status
Simulation time 144215731 ps
CPU time 0.81 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:03 PM PDT 24
Peak memory 206848 kb
Host smart-1bd84885-252c-4091-aad5-7fef1fb6d1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35974
14576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3597414576
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2789731099
Short name T2521
Test name
Test status
Simulation time 110508278 ps
CPU time 0.73 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:02 PM PDT 24
Peak memory 206844 kb
Host smart-f433f0a1-b288-4930-8fea-12864c5ba683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27897
31099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2789731099
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.4206212598
Short name T1028
Test name
Test status
Simulation time 871196509 ps
CPU time 2.13 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:03 PM PDT 24
Peak memory 207040 kb
Host smart-754b0a81-bd41-4247-9077-cb58ee04d82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42062
12598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.4206212598
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1070790090
Short name T2532
Test name
Test status
Simulation time 255412870 ps
CPU time 1.7 seconds
Started Jul 16 06:46:59 PM PDT 24
Finished Jul 16 06:47:01 PM PDT 24
Peak memory 207024 kb
Host smart-92f6d4b8-404a-4f9c-ba0e-d60918443886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10707
90090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1070790090
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2943579503
Short name T900
Test name
Test status
Simulation time 103204073644 ps
CPU time 143.56 seconds
Started Jul 16 06:47:02 PM PDT 24
Finished Jul 16 06:49:26 PM PDT 24
Peak memory 207040 kb
Host smart-77983490-76b3-48e7-a20b-1b731cea506d
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2943579503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2943579503
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1432549137
Short name T1435
Test name
Test status
Simulation time 110123892620 ps
CPU time 160.36 seconds
Started Jul 16 06:47:05 PM PDT 24
Finished Jul 16 06:49:46 PM PDT 24
Peak memory 207080 kb
Host smart-c962d459-b46d-4fa3-a8ec-f50aac31f665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432549137 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1432549137
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.4229783504
Short name T1143
Test name
Test status
Simulation time 85110369928 ps
CPU time 115.14 seconds
Started Jul 16 06:47:02 PM PDT 24
Finished Jul 16 06:48:58 PM PDT 24
Peak memory 207084 kb
Host smart-08b94614-caf7-4845-b005-63daa5effa26
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4229783504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.4229783504
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.2629960443
Short name T758
Test name
Test status
Simulation time 102185988186 ps
CPU time 129.18 seconds
Started Jul 16 06:46:59 PM PDT 24
Finished Jul 16 06:49:09 PM PDT 24
Peak memory 207084 kb
Host smart-e69dc6e0-e3a8-4528-86e7-795865c2936d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26299
60443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.2629960443
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3746023970
Short name T642
Test name
Test status
Simulation time 187124697 ps
CPU time 0.96 seconds
Started Jul 16 06:47:02 PM PDT 24
Finished Jul 16 06:47:04 PM PDT 24
Peak memory 206820 kb
Host smart-3f718ac5-a623-44c5-92ca-c9c9e9419d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460
23970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3746023970
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.416609524
Short name T1479
Test name
Test status
Simulation time 181013150 ps
CPU time 0.74 seconds
Started Jul 16 06:47:03 PM PDT 24
Finished Jul 16 06:47:04 PM PDT 24
Peak memory 206784 kb
Host smart-17889cc7-0b86-42b8-919d-9855cbbd1517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41660
9524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.416609524
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.552164288
Short name T1908
Test name
Test status
Simulation time 172394216 ps
CPU time 0.82 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:02 PM PDT 24
Peak memory 206748 kb
Host smart-84e76504-f50f-4db5-91a6-7b131911a4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55216
4288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.552164288
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.1190089767
Short name T1741
Test name
Test status
Simulation time 6499859850 ps
CPU time 61.12 seconds
Started Jul 16 06:47:01 PM PDT 24
Finished Jul 16 06:48:04 PM PDT 24
Peak memory 207048 kb
Host smart-ff6abc78-a8ad-48ac-a4ac-d24837893e0a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1190089767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.1190089767
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3919994164
Short name T682
Test name
Test status
Simulation time 216684840 ps
CPU time 0.92 seconds
Started Jul 16 06:47:01 PM PDT 24
Finished Jul 16 06:47:04 PM PDT 24
Peak memory 206756 kb
Host smart-85fc5399-ee19-42f0-940c-f25ae34e4790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39199
94164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3919994164
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3614958001
Short name T554
Test name
Test status
Simulation time 23366878640 ps
CPU time 26.67 seconds
Started Jul 16 06:47:05 PM PDT 24
Finished Jul 16 06:47:32 PM PDT 24
Peak memory 206936 kb
Host smart-49ebb3be-12b6-4ebf-893f-bddaa0fd038d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
58001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3614958001
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.230549104
Short name T848
Test name
Test status
Simulation time 3392336375 ps
CPU time 3.89 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:05 PM PDT 24
Peak memory 206924 kb
Host smart-dff118b6-8bbc-4f5a-8475-58da32b8e410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23054
9104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.230549104
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2095077439
Short name T2003
Test name
Test status
Simulation time 8300572551 ps
CPU time 78.76 seconds
Started Jul 16 06:46:59 PM PDT 24
Finished Jul 16 06:48:19 PM PDT 24
Peak memory 207140 kb
Host smart-ca4c329a-ac02-4333-9c80-c280ad7fb830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
77439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2095077439
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2329095554
Short name T1073
Test name
Test status
Simulation time 7049595714 ps
CPU time 194.75 seconds
Started Jul 16 06:47:01 PM PDT 24
Finished Jul 16 06:50:17 PM PDT 24
Peak memory 207008 kb
Host smart-124289a3-dbc6-434e-9ebd-0807aa0b70b4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2329095554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2329095554
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1476325698
Short name T2455
Test name
Test status
Simulation time 233683694 ps
CPU time 0.99 seconds
Started Jul 16 06:47:01 PM PDT 24
Finished Jul 16 06:47:03 PM PDT 24
Peak memory 206752 kb
Host smart-7e1a36a1-4376-44af-85cf-bb5a128d74ae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1476325698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1476325698
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3062129563
Short name T1286
Test name
Test status
Simulation time 189947452 ps
CPU time 0.86 seconds
Started Jul 16 06:47:01 PM PDT 24
Finished Jul 16 06:47:03 PM PDT 24
Peak memory 206880 kb
Host smart-5f6f9f25-f888-4044-96cd-ecc28f7c5e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30621
29563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3062129563
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3450728308
Short name T2497
Test name
Test status
Simulation time 5211979406 ps
CPU time 45.33 seconds
Started Jul 16 06:46:59 PM PDT 24
Finished Jul 16 06:47:45 PM PDT 24
Peak memory 207032 kb
Host smart-144b72e9-e988-46f3-a10b-7036d3606ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34507
28308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3450728308
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3255842670
Short name T2117
Test name
Test status
Simulation time 4738856640 ps
CPU time 47.31 seconds
Started Jul 16 06:47:00 PM PDT 24
Finished Jul 16 06:47:49 PM PDT 24
Peak memory 207092 kb
Host smart-8e469280-d911-4a44-87ec-320b2f9a0cdb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3255842670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3255842670
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3640418317
Short name T1994
Test name
Test status
Simulation time 156047152 ps
CPU time 0.83 seconds
Started Jul 16 06:46:59 PM PDT 24
Finished Jul 16 06:47:00 PM PDT 24
Peak memory 206884 kb
Host smart-7417022e-55f8-4242-aed4-fba14b58391f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3640418317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3640418317
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3492274047
Short name T1503
Test name
Test status
Simulation time 147379859 ps
CPU time 0.8 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206868 kb
Host smart-bedd7fa7-6509-4352-a54f-fde83c8170d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34922
74047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3492274047
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1106890936
Short name T2135
Test name
Test status
Simulation time 176910616 ps
CPU time 0.83 seconds
Started Jul 16 06:47:12 PM PDT 24
Finished Jul 16 06:47:14 PM PDT 24
Peak memory 206664 kb
Host smart-86eae27c-b8fc-4f01-95f0-5d3dba3e093a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068
90936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1106890936
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2271753168
Short name T1156
Test name
Test status
Simulation time 177180186 ps
CPU time 0.81 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206896 kb
Host smart-a449380d-fde0-4140-ac01-7254c3b837a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22717
53168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2271753168
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3894349758
Short name T445
Test name
Test status
Simulation time 173467608 ps
CPU time 0.77 seconds
Started Jul 16 06:47:12 PM PDT 24
Finished Jul 16 06:47:14 PM PDT 24
Peak memory 206816 kb
Host smart-b698031f-9b51-4ceb-b15e-e91bca1d33e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38943
49758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3894349758
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.4017389280
Short name T428
Test name
Test status
Simulation time 158643070 ps
CPU time 0.76 seconds
Started Jul 16 06:47:14 PM PDT 24
Finished Jul 16 06:47:16 PM PDT 24
Peak memory 206820 kb
Host smart-590b6fd6-930f-4d34-9e48-d6c6d0ef6191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40173
89280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.4017389280
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2931836578
Short name T1192
Test name
Test status
Simulation time 238317350 ps
CPU time 0.94 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206780 kb
Host smart-55ef8a7f-b517-4417-a5bb-04efb7905d72
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2931836578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2931836578
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3994062027
Short name T760
Test name
Test status
Simulation time 273203725 ps
CPU time 0.98 seconds
Started Jul 16 06:47:13 PM PDT 24
Finished Jul 16 06:47:15 PM PDT 24
Peak memory 206736 kb
Host smart-aebf8d90-08e7-4a90-b06e-bdd4c245ba5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39940
62027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3994062027
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.922162836
Short name T829
Test name
Test status
Simulation time 158390223 ps
CPU time 0.8 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206804 kb
Host smart-986f74d0-6819-451d-a4af-02783e1b8f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92216
2836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.922162836
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2397143344
Short name T1484
Test name
Test status
Simulation time 22772283587 ps
CPU time 47.12 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:48:04 PM PDT 24
Peak memory 207128 kb
Host smart-1407544c-9ae2-4e99-bce9-a0328c8a96b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23971
43344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2397143344
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.4028998215
Short name T2156
Test name
Test status
Simulation time 215773540 ps
CPU time 0.84 seconds
Started Jul 16 06:47:13 PM PDT 24
Finished Jul 16 06:47:16 PM PDT 24
Peak memory 206884 kb
Host smart-e4f9c30b-24b4-481d-bcb1-08bb0371799f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40289
98215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.4028998215
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3927384615
Short name T374
Test name
Test status
Simulation time 195498181 ps
CPU time 0.79 seconds
Started Jul 16 06:47:12 PM PDT 24
Finished Jul 16 06:47:13 PM PDT 24
Peak memory 206880 kb
Host smart-1d58c6a9-a05b-40e7-829b-af22e14f0e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39273
84615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3927384615
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2978666702
Short name T153
Test name
Test status
Simulation time 9992975000 ps
CPU time 61.55 seconds
Started Jul 16 06:47:16 PM PDT 24
Finished Jul 16 06:48:19 PM PDT 24
Peak memory 207128 kb
Host smart-fb9b2a38-04a4-4025-9f41-3a407e358faf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2978666702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2978666702
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2407039283
Short name T2427
Test name
Test status
Simulation time 4859797019 ps
CPU time 32.11 seconds
Started Jul 16 06:47:14 PM PDT 24
Finished Jul 16 06:47:48 PM PDT 24
Peak memory 207140 kb
Host smart-32d5c90a-44ea-4e32-8f71-04a69f4cfc9d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2407039283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2407039283
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.2821380700
Short name T1995
Test name
Test status
Simulation time 11951239616 ps
CPU time 57.28 seconds
Started Jul 16 06:47:14 PM PDT 24
Finished Jul 16 06:48:13 PM PDT 24
Peak memory 207108 kb
Host smart-8d16c47f-9ba0-42a5-9fa6-26511ddd5f59
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2821380700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2821380700
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3445849646
Short name T1176
Test name
Test status
Simulation time 167392232 ps
CPU time 0.79 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206872 kb
Host smart-d23a6045-db12-4b4c-9942-cc21ddd9b84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34458
49646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3445849646
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.818628574
Short name T763
Test name
Test status
Simulation time 161602260 ps
CPU time 0.81 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206848 kb
Host smart-92838a23-3450-4eac-8316-891000e42007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81862
8574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.818628574
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3671813644
Short name T380
Test name
Test status
Simulation time 184510783 ps
CPU time 0.85 seconds
Started Jul 16 06:47:13 PM PDT 24
Finished Jul 16 06:47:16 PM PDT 24
Peak memory 206864 kb
Host smart-d70f0c95-b5c8-4b3d-86a3-996111604d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36718
13644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3671813644
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2670712409
Short name T1626
Test name
Test status
Simulation time 197104911 ps
CPU time 0.82 seconds
Started Jul 16 06:47:18 PM PDT 24
Finished Jul 16 06:47:20 PM PDT 24
Peak memory 206876 kb
Host smart-a3a74089-afe9-40b3-87bb-b7e633413727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26707
12409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2670712409
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.892052642
Short name T181
Test name
Test status
Simulation time 409565631 ps
CPU time 1.36 seconds
Started Jul 16 06:47:14 PM PDT 24
Finished Jul 16 06:47:17 PM PDT 24
Peak memory 224508 kb
Host smart-43b88aaf-d6ab-451f-833a-c77edccee189
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=892052642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.892052642
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1535652995
Short name T55
Test name
Test status
Simulation time 540493632 ps
CPU time 1.67 seconds
Started Jul 16 06:47:18 PM PDT 24
Finished Jul 16 06:47:21 PM PDT 24
Peak memory 206808 kb
Host smart-a91ecf19-b9ae-48f5-a6b3-c34acc73a71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15356
52995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1535652995
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3557741722
Short name T164
Test name
Test status
Simulation time 326568573 ps
CPU time 0.94 seconds
Started Jul 16 06:47:14 PM PDT 24
Finished Jul 16 06:47:17 PM PDT 24
Peak memory 206892 kb
Host smart-3c916a1a-87ea-424f-b47b-57010a1b37ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35577
41722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3557741722
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1013223937
Short name T392
Test name
Test status
Simulation time 157101178 ps
CPU time 0.79 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206748 kb
Host smart-0272dc3a-b941-4dc2-8587-e880eef6d1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10132
23937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1013223937
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3481394207
Short name T898
Test name
Test status
Simulation time 154394206 ps
CPU time 0.78 seconds
Started Jul 16 06:47:12 PM PDT 24
Finished Jul 16 06:47:14 PM PDT 24
Peak memory 206864 kb
Host smart-15a9c2c8-8650-4726-8e44-9100daf4c571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34813
94207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3481394207
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.636867050
Short name T691
Test name
Test status
Simulation time 262940383 ps
CPU time 1.03 seconds
Started Jul 16 06:47:14 PM PDT 24
Finished Jul 16 06:47:17 PM PDT 24
Peak memory 206888 kb
Host smart-b78036a6-8b74-4495-b132-7dadac1b4f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63686
7050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.636867050
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2345979043
Short name T483
Test name
Test status
Simulation time 5014743864 ps
CPU time 36.7 seconds
Started Jul 16 06:47:13 PM PDT 24
Finished Jul 16 06:47:51 PM PDT 24
Peak memory 207116 kb
Host smart-dfdef8c3-2ed4-4230-a030-55209cfe6c4a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2345979043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2345979043
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.591679236
Short name T2749
Test name
Test status
Simulation time 173791600 ps
CPU time 0.84 seconds
Started Jul 16 06:47:19 PM PDT 24
Finished Jul 16 06:47:21 PM PDT 24
Peak memory 206872 kb
Host smart-7e5e70ff-c9e2-47d4-95fa-6571ad082888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59167
9236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.591679236
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1524869959
Short name T1587
Test name
Test status
Simulation time 169707829 ps
CPU time 0.79 seconds
Started Jul 16 06:47:15 PM PDT 24
Finished Jul 16 06:47:18 PM PDT 24
Peak memory 206816 kb
Host smart-10f3533c-6a0d-4a99-88e6-d7939bc6e0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15248
69959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1524869959
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.2159482235
Short name T2726
Test name
Test status
Simulation time 421874740 ps
CPU time 1.12 seconds
Started Jul 16 06:47:12 PM PDT 24
Finished Jul 16 06:47:15 PM PDT 24
Peak memory 206732 kb
Host smart-e1c27851-aae1-47cf-af7a-1270730c54e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21594
82235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2159482235
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2070291980
Short name T1984
Test name
Test status
Simulation time 4325995424 ps
CPU time 41.88 seconds
Started Jul 16 06:47:13 PM PDT 24
Finished Jul 16 06:47:56 PM PDT 24
Peak memory 207136 kb
Host smart-734010c0-9c30-4689-9a29-53f09224a2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20702
91980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2070291980
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3159820388
Short name T156
Test name
Test status
Simulation time 13893628940 ps
CPU time 88.55 seconds
Started Jul 16 06:47:14 PM PDT 24
Finished Jul 16 06:48:44 PM PDT 24
Peak memory 207036 kb
Host smart-886bba45-e5d4-46ca-9135-3a88bd221cfa
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3159820388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3159820388
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3935941677
Short name T2474
Test name
Test status
Simulation time 84167550 ps
CPU time 0.73 seconds
Started Jul 16 06:49:31 PM PDT 24
Finished Jul 16 06:49:33 PM PDT 24
Peak memory 206908 kb
Host smart-6d798051-cede-4968-8b89-aeacfe26e39a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3935941677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3935941677
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1751396620
Short name T1453
Test name
Test status
Simulation time 3439108839 ps
CPU time 3.83 seconds
Started Jul 16 06:49:34 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 207084 kb
Host smart-801a0726-1515-498f-8585-68be899afaf6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1751396620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1751396620
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2916126029
Short name T1112
Test name
Test status
Simulation time 13359622432 ps
CPU time 12.88 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:48 PM PDT 24
Peak memory 206940 kb
Host smart-8009269b-4cb1-411e-994a-db3d0a305b30
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2916126029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2916126029
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.4129730695
Short name T13
Test name
Test status
Simulation time 23415651251 ps
CPU time 23.04 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:57 PM PDT 24
Peak memory 206816 kb
Host smart-87d106e6-f42b-45b3-8880-c6300f122c85
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4129730695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.4129730695
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3756385544
Short name T2398
Test name
Test status
Simulation time 213759846 ps
CPU time 0.88 seconds
Started Jul 16 06:49:31 PM PDT 24
Finished Jul 16 06:49:33 PM PDT 24
Peak memory 206804 kb
Host smart-7c016f03-afcc-4ea9-87cc-e1d3ae5843d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37563
85544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3756385544
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1334331258
Short name T1060
Test name
Test status
Simulation time 148343158 ps
CPU time 0.82 seconds
Started Jul 16 06:49:29 PM PDT 24
Finished Jul 16 06:49:31 PM PDT 24
Peak memory 206732 kb
Host smart-9f63d8c4-4200-4dc3-9380-81179c377f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343
31258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1334331258
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3857722470
Short name T1628
Test name
Test status
Simulation time 268085362 ps
CPU time 1.06 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:35 PM PDT 24
Peak memory 206780 kb
Host smart-53f8c044-9c84-4817-8f7d-35f556e4efae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38577
22470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3857722470
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.446278406
Short name T431
Test name
Test status
Simulation time 558211270 ps
CPU time 1.42 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 206852 kb
Host smart-07bcb1c3-b682-41a4-b7c5-94e7ec8ac955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44627
8406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.446278406
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1403259201
Short name T2573
Test name
Test status
Simulation time 7349664459 ps
CPU time 12.87 seconds
Started Jul 16 06:49:37 PM PDT 24
Finished Jul 16 06:49:52 PM PDT 24
Peak memory 207076 kb
Host smart-b88cb1f9-369e-4ed2-944f-0b0eef79cbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14032
59201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1403259201
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1067569370
Short name T2090
Test name
Test status
Simulation time 441542430 ps
CPU time 1.35 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:38 PM PDT 24
Peak memory 206816 kb
Host smart-84ad447f-5763-44d1-8b1d-4cebf5c6b291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10675
69370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1067569370
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.146080914
Short name T2544
Test name
Test status
Simulation time 138549329 ps
CPU time 0.8 seconds
Started Jul 16 06:49:35 PM PDT 24
Finished Jul 16 06:49:39 PM PDT 24
Peak memory 206880 kb
Host smart-e2526608-4bd0-41d4-96a0-6561584cd4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
0914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.146080914
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3314656328
Short name T620
Test name
Test status
Simulation time 35190072 ps
CPU time 0.65 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 206876 kb
Host smart-13d77ecf-facb-43e4-919f-8d2e24b8e80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
56328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3314656328
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.4184848206
Short name T836
Test name
Test status
Simulation time 959183213 ps
CPU time 2.22 seconds
Started Jul 16 06:49:36 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 207012 kb
Host smart-a5cb42f5-7204-4e8c-ba97-9d2f3ea687af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41848
48206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.4184848206
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1096246585
Short name T788
Test name
Test status
Simulation time 337632306 ps
CPU time 2.2 seconds
Started Jul 16 06:49:35 PM PDT 24
Finished Jul 16 06:49:40 PM PDT 24
Peak memory 207020 kb
Host smart-dc465e2d-551c-4554-94ed-e7dbc3260815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10962
46585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1096246585
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.98152454
Short name T1742
Test name
Test status
Simulation time 196959091 ps
CPU time 0.83 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 206888 kb
Host smart-e784b9c6-d909-424d-ad54-73ed64ea7f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98152
454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.98152454
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1534934295
Short name T1542
Test name
Test status
Simulation time 138727042 ps
CPU time 0.76 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 206884 kb
Host smart-56afa51c-36c6-4dfc-9078-3dd0d3e5c36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15349
34295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1534934295
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.4085138685
Short name T2330
Test name
Test status
Simulation time 212861021 ps
CPU time 0.87 seconds
Started Jul 16 06:49:36 PM PDT 24
Finished Jul 16 06:49:40 PM PDT 24
Peak memory 206860 kb
Host smart-5b34f5f6-d16c-4526-9e90-1d9d05677eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40851
38685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.4085138685
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.2944187109
Short name T839
Test name
Test status
Simulation time 210115405 ps
CPU time 0.86 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:36 PM PDT 24
Peak memory 206800 kb
Host smart-fd38eda8-dccd-474a-87cd-d6f37603658b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
87109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2944187109
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1382956595
Short name T2498
Test name
Test status
Simulation time 23327728636 ps
CPU time 21.09 seconds
Started Jul 16 06:49:38 PM PDT 24
Finished Jul 16 06:50:01 PM PDT 24
Peak memory 206880 kb
Host smart-b1369e01-1401-4bec-bdde-cd947afb226c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
56595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1382956595
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.474053458
Short name T1817
Test name
Test status
Simulation time 3287161637 ps
CPU time 3.65 seconds
Started Jul 16 06:49:38 PM PDT 24
Finished Jul 16 06:49:43 PM PDT 24
Peak memory 206816 kb
Host smart-5cf84b57-057f-4a27-8db2-80934f80a6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47405
3458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.474053458
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3334648494
Short name T2151
Test name
Test status
Simulation time 8826671113 ps
CPU time 63.23 seconds
Started Jul 16 06:49:35 PM PDT 24
Finished Jul 16 06:50:41 PM PDT 24
Peak memory 207156 kb
Host smart-59ddf3f7-0de2-48f2-83a6-47e7cc42abb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33346
48494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3334648494
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.4076487172
Short name T1463
Test name
Test status
Simulation time 5837902560 ps
CPU time 44.74 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 207012 kb
Host smart-96be8529-b3a5-4134-85c6-d490efb577bb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4076487172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.4076487172
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2911786224
Short name T2001
Test name
Test status
Simulation time 312156007 ps
CPU time 0.93 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:36 PM PDT 24
Peak memory 206892 kb
Host smart-3b901e42-87a7-4189-abda-7c3e6a926795
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2911786224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2911786224
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3155520819
Short name T1391
Test name
Test status
Simulation time 197922889 ps
CPU time 0.86 seconds
Started Jul 16 06:49:39 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 206752 kb
Host smart-ce7b4032-4e04-474c-92cf-d9cd50701ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31555
20819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3155520819
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.4277750113
Short name T1235
Test name
Test status
Simulation time 5465951119 ps
CPU time 149.68 seconds
Started Jul 16 06:49:34 PM PDT 24
Finished Jul 16 06:52:08 PM PDT 24
Peak memory 207000 kb
Host smart-a110eec9-420e-402b-8b84-e6192979eada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42777
50113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.4277750113
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.435489999
Short name T1161
Test name
Test status
Simulation time 4849745653 ps
CPU time 46.56 seconds
Started Jul 16 06:49:39 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206968 kb
Host smart-0a525bc3-3acd-4932-8786-7bd63f6f1786
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=435489999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.435489999
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3525697885
Short name T1440
Test name
Test status
Simulation time 225861688 ps
CPU time 0.86 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 206888 kb
Host smart-884d9284-c99b-42c1-afbc-831086f8296c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3525697885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3525697885
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.660811018
Short name T1656
Test name
Test status
Simulation time 143810102 ps
CPU time 0.76 seconds
Started Jul 16 06:49:31 PM PDT 24
Finished Jul 16 06:49:35 PM PDT 24
Peak memory 206880 kb
Host smart-528b27cd-3ca3-428a-8d6b-114e54ca7461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66081
1018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.660811018
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1125240681
Short name T1305
Test name
Test status
Simulation time 157368946 ps
CPU time 0.8 seconds
Started Jul 16 06:49:38 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 206816 kb
Host smart-646d23c3-e3db-4285-8ddb-a68ad66998c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11252
40681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1125240681
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2955362176
Short name T96
Test name
Test status
Simulation time 156133894 ps
CPU time 0.82 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:35 PM PDT 24
Peak memory 206856 kb
Host smart-7674bcbc-caf3-4ab9-a5dc-9c1198b9dbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29553
62176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2955362176
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3092394004
Short name T210
Test name
Test status
Simulation time 183025394 ps
CPU time 0.85 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:35 PM PDT 24
Peak memory 206648 kb
Host smart-1ac782d0-1e17-443e-8a7f-05cca4af56a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30923
94004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3092394004
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1748279234
Short name T915
Test name
Test status
Simulation time 242790781 ps
CPU time 0.92 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:35 PM PDT 24
Peak memory 206896 kb
Host smart-d80d2c68-7eab-4bd3-8858-33aa90e22609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17482
79234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1748279234
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.2863716869
Short name T2477
Test name
Test status
Simulation time 206014236 ps
CPU time 0.88 seconds
Started Jul 16 06:49:35 PM PDT 24
Finished Jul 16 06:49:39 PM PDT 24
Peak memory 206880 kb
Host smart-cd084bf3-76af-4d8f-941c-a2f2b33d4448
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2863716869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.2863716869
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.555740902
Short name T1970
Test name
Test status
Simulation time 166817049 ps
CPU time 0.8 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:36 PM PDT 24
Peak memory 206844 kb
Host smart-0c95cd19-131e-49d5-ad6f-cc3bc971da67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55574
0902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.555740902
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1882064258
Short name T2530
Test name
Test status
Simulation time 40469721 ps
CPU time 0.69 seconds
Started Jul 16 06:49:34 PM PDT 24
Finished Jul 16 06:49:38 PM PDT 24
Peak memory 206804 kb
Host smart-019957c4-52e9-4339-9baa-c1823ad12a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18820
64258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1882064258
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.123299684
Short name T235
Test name
Test status
Simulation time 9179599581 ps
CPU time 20.32 seconds
Started Jul 16 06:49:36 PM PDT 24
Finished Jul 16 06:49:59 PM PDT 24
Peak memory 207100 kb
Host smart-98ba4953-dabd-4891-91f6-697ea766dee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12329
9684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.123299684
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1540401970
Short name T1324
Test name
Test status
Simulation time 183388522 ps
CPU time 0.8 seconds
Started Jul 16 06:49:39 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 206752 kb
Host smart-704dd560-48dd-4c22-b9a9-e6bda9f6491e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
01970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1540401970
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.51329171
Short name T1655
Test name
Test status
Simulation time 173762011 ps
CPU time 0.81 seconds
Started Jul 16 06:49:35 PM PDT 24
Finished Jul 16 06:49:39 PM PDT 24
Peak memory 206860 kb
Host smart-e80d419d-f815-4987-841f-dddc6fd5a36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51329
171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.51329171
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3012755151
Short name T2707
Test name
Test status
Simulation time 212443624 ps
CPU time 0.87 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 206860 kb
Host smart-8ef979d4-3242-4805-ae07-4cb2ba539225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30127
55151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3012755151
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.4294965458
Short name T2053
Test name
Test status
Simulation time 187374535 ps
CPU time 0.82 seconds
Started Jul 16 06:49:30 PM PDT 24
Finished Jul 16 06:49:31 PM PDT 24
Peak memory 206728 kb
Host smart-da3aa64d-e312-4c1e-b05d-9c434f05c3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42949
65458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.4294965458
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3008947825
Short name T1622
Test name
Test status
Simulation time 137867423 ps
CPU time 0.81 seconds
Started Jul 16 06:49:36 PM PDT 24
Finished Jul 16 06:49:40 PM PDT 24
Peak memory 206864 kb
Host smart-e4734eeb-daed-4784-9d92-449d3b79b02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30089
47825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3008947825
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2435031275
Short name T1858
Test name
Test status
Simulation time 143904468 ps
CPU time 0.75 seconds
Started Jul 16 06:49:35 PM PDT 24
Finished Jul 16 06:49:39 PM PDT 24
Peak memory 206856 kb
Host smart-0c200d0a-e435-4e1e-ae6c-5d9665967cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
31275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2435031275
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1286948629
Short name T673
Test name
Test status
Simulation time 172452460 ps
CPU time 0.8 seconds
Started Jul 16 06:49:36 PM PDT 24
Finished Jul 16 06:49:40 PM PDT 24
Peak memory 206860 kb
Host smart-0c4491c1-8fec-49c5-b189-3757d81746a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
48629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1286948629
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3485065261
Short name T1348
Test name
Test status
Simulation time 218821951 ps
CPU time 0.96 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 206868 kb
Host smart-f55201ef-0581-44d5-82a2-5cab2e0e6939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34850
65261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3485065261
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.4231826234
Short name T2641
Test name
Test status
Simulation time 4843222221 ps
CPU time 129.93 seconds
Started Jul 16 06:49:35 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 207084 kb
Host smart-559f37e2-4ea1-439e-9ed8-87567bd4b60d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4231826234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.4231826234
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1667786429
Short name T2224
Test name
Test status
Simulation time 173381035 ps
CPU time 0.81 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:36 PM PDT 24
Peak memory 206852 kb
Host smart-02dd1fd2-6a1c-445e-8213-798b235755d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16677
86429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1667786429
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2456304045
Short name T2310
Test name
Test status
Simulation time 222827867 ps
CPU time 0.86 seconds
Started Jul 16 06:49:39 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 206748 kb
Host smart-686445a8-c52d-4923-aa04-97943af7046a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24563
04045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2456304045
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1323925040
Short name T2407
Test name
Test status
Simulation time 1299167529 ps
CPU time 2.63 seconds
Started Jul 16 06:49:35 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 207040 kb
Host smart-66b60367-e7f8-4887-a79e-e780c083b4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13239
25040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1323925040
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3923001400
Short name T2404
Test name
Test status
Simulation time 4178920922 ps
CPU time 37.69 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:50:12 PM PDT 24
Peak memory 207176 kb
Host smart-06103090-1ef9-463d-9359-b53e207955c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39230
01400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3923001400
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3254049641
Short name T1759
Test name
Test status
Simulation time 57827183 ps
CPU time 0.69 seconds
Started Jul 16 06:49:50 PM PDT 24
Finished Jul 16 06:49:53 PM PDT 24
Peak memory 206872 kb
Host smart-b65b64e1-19f0-4ce4-80f6-93dad7e688fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3254049641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3254049641
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1903713300
Short name T2664
Test name
Test status
Simulation time 4055504106 ps
CPU time 4.64 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 206956 kb
Host smart-e0373213-1c42-4b54-a8da-dc9348957ec4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1903713300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.1903713300
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1865951911
Short name T2233
Test name
Test status
Simulation time 13424163722 ps
CPU time 11.79 seconds
Started Jul 16 06:49:34 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 207132 kb
Host smart-9ef3b53d-fded-4ed1-a01e-4c407d4eed1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1865951911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1865951911
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1765218858
Short name T1218
Test name
Test status
Simulation time 23380998764 ps
CPU time 22.23 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:57 PM PDT 24
Peak memory 207056 kb
Host smart-783c9639-0369-4ccc-bc77-0190fc2c71af
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1765218858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1765218858
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.4257174607
Short name T1393
Test name
Test status
Simulation time 145814254 ps
CPU time 0.77 seconds
Started Jul 16 06:49:36 PM PDT 24
Finished Jul 16 06:49:40 PM PDT 24
Peak memory 206860 kb
Host smart-1bb77349-365c-4092-a665-fa0f818e7158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42571
74607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.4257174607
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.958337209
Short name T59
Test name
Test status
Simulation time 228531889 ps
CPU time 0.85 seconds
Started Jul 16 06:49:37 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 206820 kb
Host smart-bfc78486-e9b1-477d-9494-54b3fd75bb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95833
7209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.958337209
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1784852406
Short name T464
Test name
Test status
Simulation time 607018698 ps
CPU time 1.73 seconds
Started Jul 16 06:49:36 PM PDT 24
Finished Jul 16 06:49:41 PM PDT 24
Peak memory 207060 kb
Host smart-c5086f69-f12a-4781-bf7d-3273d15afb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17848
52406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1784852406
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.674317117
Short name T2074
Test name
Test status
Simulation time 664450823 ps
CPU time 1.79 seconds
Started Jul 16 06:49:33 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 206956 kb
Host smart-3dfdcff9-c8fc-4cfa-8c2d-ebb2839b1731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67431
7117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.674317117
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2101235780
Short name T1229
Test name
Test status
Simulation time 10453984872 ps
CPU time 21.48 seconds
Started Jul 16 06:49:34 PM PDT 24
Finished Jul 16 06:49:59 PM PDT 24
Peak memory 207060 kb
Host smart-8c5aea09-593c-4672-8536-cef50310bb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21012
35780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2101235780
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1812404858
Short name T2409
Test name
Test status
Simulation time 356452014 ps
CPU time 1.16 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:49:54 PM PDT 24
Peak memory 206888 kb
Host smart-eee30560-a2f3-4fff-a0c2-e6daf9580f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18124
04858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1812404858
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_enable.802541855
Short name T1439
Test name
Test status
Simulation time 49965935 ps
CPU time 0.69 seconds
Started Jul 16 06:49:45 PM PDT 24
Finished Jul 16 06:49:46 PM PDT 24
Peak memory 206868 kb
Host smart-f794e04f-ee85-4504-b6c3-465677f0d459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80254
1855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.802541855
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1490490847
Short name T787
Test name
Test status
Simulation time 849844995 ps
CPU time 2.06 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:51 PM PDT 24
Peak memory 206964 kb
Host smart-3a9847c6-b2f7-44d7-83a5-9be507c15ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904
90847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1490490847
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.338744247
Short name T809
Test name
Test status
Simulation time 268734049 ps
CPU time 1.85 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:49:55 PM PDT 24
Peak memory 207012 kb
Host smart-85ad6a7e-8889-408c-854e-7bb32c28fa27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33874
4247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.338744247
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1202870355
Short name T753
Test name
Test status
Simulation time 217871821 ps
CPU time 0.89 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206668 kb
Host smart-15b9ab9b-9558-4ed0-8994-5f47c8add0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12028
70355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1202870355
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3651844981
Short name T2226
Test name
Test status
Simulation time 195563289 ps
CPU time 0.77 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:51 PM PDT 24
Peak memory 206876 kb
Host smart-de2dc30c-bcaf-461c-ae5b-51ecae743e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36518
44981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3651844981
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.45839693
Short name T1035
Test name
Test status
Simulation time 165262279 ps
CPU time 0.83 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206908 kb
Host smart-008b7283-9bdc-4770-aea2-89bc7ba52d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45839
693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.45839693
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3631338310
Short name T2342
Test name
Test status
Simulation time 9556582513 ps
CPU time 278.23 seconds
Started Jul 16 06:49:50 PM PDT 24
Finished Jul 16 06:54:30 PM PDT 24
Peak memory 207032 kb
Host smart-f2006063-2367-4fcf-98e2-bbf52771b026
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3631338310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3631338310
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.2992640876
Short name T1356
Test name
Test status
Simulation time 256019228 ps
CPU time 0.93 seconds
Started Jul 16 06:49:46 PM PDT 24
Finished Jul 16 06:49:48 PM PDT 24
Peak memory 206888 kb
Host smart-947d24f4-758f-4d53-bae5-9a83c7a8614c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29926
40876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.2992640876
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1572081432
Short name T2080
Test name
Test status
Simulation time 23353585669 ps
CPU time 22.15 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:50:13 PM PDT 24
Peak memory 206912 kb
Host smart-261cc8d4-1c6c-434a-bae2-9f3c0fc2afdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15720
81432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1572081432
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1354437981
Short name T660
Test name
Test status
Simulation time 3343286985 ps
CPU time 4.74 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:53 PM PDT 24
Peak memory 206940 kb
Host smart-ad5b2d86-5970-43df-8800-8c607f792ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
37981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1354437981
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2960104541
Short name T1897
Test name
Test status
Simulation time 11119228863 ps
CPU time 313.41 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:55:06 PM PDT 24
Peak memory 207136 kb
Host smart-ebcb5213-9694-4fc7-88b9-d5f55925d858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29601
04541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2960104541
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3755447361
Short name T1079
Test name
Test status
Simulation time 6977471080 ps
CPU time 207.16 seconds
Started Jul 16 06:49:46 PM PDT 24
Finished Jul 16 06:53:14 PM PDT 24
Peak memory 207072 kb
Host smart-439fe9cb-b639-495c-8fa6-c127a7af56ab
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3755447361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3755447361
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1854728354
Short name T1284
Test name
Test status
Simulation time 252538007 ps
CPU time 0.91 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:49:53 PM PDT 24
Peak memory 206864 kb
Host smart-b3d6d8c6-0f90-4a10-a105-76ab8208d40c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1854728354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1854728354
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.221957416
Short name T1528
Test name
Test status
Simulation time 191755841 ps
CPU time 0.87 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:49 PM PDT 24
Peak memory 206808 kb
Host smart-3d39b0ff-980a-4bfe-92f1-85c60f19f808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22195
7416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.221957416
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1895409212
Short name T1919
Test name
Test status
Simulation time 4782643995 ps
CPU time 34.3 seconds
Started Jul 16 06:49:49 PM PDT 24
Finished Jul 16 06:50:25 PM PDT 24
Peak memory 207144 kb
Host smart-7d839020-1b52-4a11-9c72-3590d77ee779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18954
09212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1895409212
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3838852755
Short name T2069
Test name
Test status
Simulation time 5587529003 ps
CPU time 157.23 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 207060 kb
Host smart-8b650c04-ff12-408c-b802-120cc34ec4e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3838852755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3838852755
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2065377199
Short name T2714
Test name
Test status
Simulation time 154240256 ps
CPU time 0.84 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206860 kb
Host smart-eeb96d18-09d7-4874-9850-a3e7beef3f35
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2065377199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2065377199
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1116238976
Short name T1949
Test name
Test status
Simulation time 203443125 ps
CPU time 0.84 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:49 PM PDT 24
Peak memory 206852 kb
Host smart-50e4a169-32ab-4862-8530-5b81f52ba32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11162
38976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1116238976
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3948092494
Short name T2362
Test name
Test status
Simulation time 185582714 ps
CPU time 0.82 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206880 kb
Host smart-2f87bb32-0552-4342-a7a6-55e52a7b4e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39480
92494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3948092494
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.561909113
Short name T948
Test name
Test status
Simulation time 169349499 ps
CPU time 0.78 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206660 kb
Host smart-10f70061-c2d5-4105-9565-0a56d0328cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56190
9113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.561909113
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4055491989
Short name T2570
Test name
Test status
Simulation time 155633336 ps
CPU time 0.75 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:49 PM PDT 24
Peak memory 206884 kb
Host smart-c3dce9b3-9321-4c8c-ad41-53ccf5b23ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40554
91989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4055491989
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2479630715
Short name T1509
Test name
Test status
Simulation time 165917827 ps
CPU time 0.77 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206668 kb
Host smart-a4ea11e7-b6cd-4dd8-bede-96c73a7eb07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24796
30715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2479630715
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.228128771
Short name T140
Test name
Test status
Simulation time 238344156 ps
CPU time 1.06 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206860 kb
Host smart-115f81a0-668e-4231-aec9-ddf2945990b1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=228128771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.228128771
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3676814865
Short name T1761
Test name
Test status
Simulation time 140698334 ps
CPU time 0.77 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:49 PM PDT 24
Peak memory 206868 kb
Host smart-993da7ff-d97a-4b5a-b629-45cf651216c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36768
14865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3676814865
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1162220059
Short name T2321
Test name
Test status
Simulation time 39500070 ps
CPU time 0.63 seconds
Started Jul 16 06:49:45 PM PDT 24
Finished Jul 16 06:49:46 PM PDT 24
Peak memory 206896 kb
Host smart-09f076ec-5583-48ca-bf91-3c61f5a41eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11622
20059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1162220059
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4150974004
Short name T1131
Test name
Test status
Simulation time 13318292992 ps
CPU time 31.97 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:50:25 PM PDT 24
Peak memory 207156 kb
Host smart-2e94ab0b-2f58-49dd-b5fd-d359552794c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
74004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4150974004
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.4281917901
Short name T1767
Test name
Test status
Simulation time 180703372 ps
CPU time 0.83 seconds
Started Jul 16 06:49:52 PM PDT 24
Finished Jul 16 06:49:54 PM PDT 24
Peak memory 206888 kb
Host smart-3ab2cddb-c40c-4017-ad4b-8d8afa9e111b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42819
17901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.4281917901
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.456112013
Short name T2275
Test name
Test status
Simulation time 172638640 ps
CPU time 0.84 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:51 PM PDT 24
Peak memory 206884 kb
Host smart-7f66e3ea-e726-4f2f-ac5c-7748fde15603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45611
2013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.456112013
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.626958439
Short name T985
Test name
Test status
Simulation time 160135477 ps
CPU time 0.84 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:51 PM PDT 24
Peak memory 207032 kb
Host smart-2d120ba2-39c1-4b62-959c-604b4cd6794f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62695
8439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.626958439
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1495295366
Short name T778
Test name
Test status
Simulation time 233490283 ps
CPU time 0.88 seconds
Started Jul 16 06:49:49 PM PDT 24
Finished Jul 16 06:49:52 PM PDT 24
Peak memory 206860 kb
Host smart-da891cbc-107e-49f7-9777-4d48029e2ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14952
95366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1495295366
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.4234571714
Short name T808
Test name
Test status
Simulation time 152847545 ps
CPU time 0.87 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:51 PM PDT 24
Peak memory 207024 kb
Host smart-15df2c68-2eab-4c43-9308-53cff8d57f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345
71714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.4234571714
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2223185349
Short name T463
Test name
Test status
Simulation time 144939186 ps
CPU time 0.81 seconds
Started Jul 16 06:49:49 PM PDT 24
Finished Jul 16 06:49:52 PM PDT 24
Peak memory 206856 kb
Host smart-b295bbc8-c87c-4a1a-bdbb-0e05d9346c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22231
85349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2223185349
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3504543126
Short name T312
Test name
Test status
Simulation time 226396823 ps
CPU time 0.94 seconds
Started Jul 16 06:49:49 PM PDT 24
Finished Jul 16 06:49:52 PM PDT 24
Peak memory 206872 kb
Host smart-9ab9f561-8f26-4ab4-ada3-8650628fe842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35045
43126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3504543126
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.657999829
Short name T1095
Test name
Test status
Simulation time 4559325325 ps
CPU time 131.5 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:52:04 PM PDT 24
Peak memory 207084 kb
Host smart-ef18becb-c55c-4b61-bd95-45068f33a31a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=657999829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.657999829
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1668903895
Short name T2013
Test name
Test status
Simulation time 169903166 ps
CPU time 0.83 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:51 PM PDT 24
Peak memory 206864 kb
Host smart-aa026c25-35b5-48c1-b150-343b497340c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16689
03895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1668903895
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1211357962
Short name T1354
Test name
Test status
Simulation time 168164561 ps
CPU time 0.81 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206880 kb
Host smart-7f7f2ff7-b77c-4b6a-9dfa-4dad56b7ab8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12113
57962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1211357962
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.201368338
Short name T2561
Test name
Test status
Simulation time 571764687 ps
CPU time 1.47 seconds
Started Jul 16 06:49:49 PM PDT 24
Finished Jul 16 06:49:52 PM PDT 24
Peak memory 206868 kb
Host smart-a18261d2-f8bb-49ef-b7ee-45328cf092fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20136
8338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.201368338
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2698937371
Short name T1020
Test name
Test status
Simulation time 5705273217 ps
CPU time 156.52 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:52:25 PM PDT 24
Peak memory 206956 kb
Host smart-05da5a70-49b9-4ac0-b364-b7f93b32a3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26989
37371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2698937371
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.4048608180
Short name T1520
Test name
Test status
Simulation time 55443690 ps
CPU time 0.72 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:05 PM PDT 24
Peak memory 206844 kb
Host smart-aa51954e-9849-45fd-87e3-10f0338b3888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4048608180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.4048608180
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.520634787
Short name T1899
Test name
Test status
Simulation time 3761479145 ps
CPU time 4.54 seconds
Started Jul 16 06:49:49 PM PDT 24
Finished Jul 16 06:49:55 PM PDT 24
Peak memory 206892 kb
Host smart-c6d4d5f1-a096-43e2-99c5-d215b9408694
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=520634787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.520634787
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.948594364
Short name T2663
Test name
Test status
Simulation time 13466405942 ps
CPU time 15.11 seconds
Started Jul 16 06:49:49 PM PDT 24
Finished Jul 16 06:50:06 PM PDT 24
Peak memory 207052 kb
Host smart-d12a9efd-52df-43c2-8036-78a7c2d3517b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=948594364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.948594364
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2360105861
Short name T1729
Test name
Test status
Simulation time 23371693749 ps
CPU time 22.74 seconds
Started Jul 16 06:49:52 PM PDT 24
Finished Jul 16 06:50:16 PM PDT 24
Peak memory 207056 kb
Host smart-1b3a76a1-64c2-49b0-a0a6-a1bacd65a201
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2360105861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2360105861
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3013701865
Short name T615
Test name
Test status
Simulation time 145621377 ps
CPU time 0.77 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:49:53 PM PDT 24
Peak memory 206880 kb
Host smart-23d1f55f-92e1-4294-9b0d-aca296fc4d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30137
01865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3013701865
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1943474306
Short name T415
Test name
Test status
Simulation time 152509441 ps
CPU time 0.79 seconds
Started Jul 16 06:49:49 PM PDT 24
Finished Jul 16 06:49:52 PM PDT 24
Peak memory 206876 kb
Host smart-f4ae3d6e-9eba-4ccb-8120-68e253c83fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19434
74306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1943474306
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.567424719
Short name T2441
Test name
Test status
Simulation time 317508605 ps
CPU time 1.1 seconds
Started Jul 16 06:49:47 PM PDT 24
Finished Jul 16 06:49:50 PM PDT 24
Peak memory 206876 kb
Host smart-5441dd15-4d75-42d6-b444-48fda7d65f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56742
4719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.567424719
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1881543435
Short name T2115
Test name
Test status
Simulation time 1556525244 ps
CPU time 2.97 seconds
Started Jul 16 06:49:48 PM PDT 24
Finished Jul 16 06:49:53 PM PDT 24
Peak memory 207028 kb
Host smart-ea959cb9-78a5-4552-a715-1c3cbd4a96ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
43435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1881543435
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1615927512
Short name T1944
Test name
Test status
Simulation time 18110334321 ps
CPU time 34.32 seconds
Started Jul 16 06:49:51 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 207084 kb
Host smart-02b0f993-7e48-4be8-8ed0-7fca32d408ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16159
27512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1615927512
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3001182774
Short name T1136
Test name
Test status
Simulation time 403274086 ps
CPU time 1.34 seconds
Started Jul 16 06:50:00 PM PDT 24
Finished Jul 16 06:50:03 PM PDT 24
Peak memory 206896 kb
Host smart-f4a845a4-8e0c-4e25-8c6b-c2ea327e64fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30011
82774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3001182774
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.1294159886
Short name T454
Test name
Test status
Simulation time 137908526 ps
CPU time 0.77 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:04 PM PDT 24
Peak memory 206668 kb
Host smart-44cb642c-ab13-4723-9a74-d2a9fafca4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12941
59886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.1294159886
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3189611746
Short name T586
Test name
Test status
Simulation time 34215278 ps
CPU time 0.65 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:04 PM PDT 24
Peak memory 206784 kb
Host smart-a7bb7ae8-5986-4746-9469-13445a9631f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
11746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3189611746
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2633639034
Short name T2040
Test name
Test status
Simulation time 1074524805 ps
CPU time 2.16 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206792 kb
Host smart-a8e2bd2f-b812-497e-b9ee-692bbba6c022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26336
39034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2633639034
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2232648787
Short name T1327
Test name
Test status
Simulation time 257658468 ps
CPU time 1.46 seconds
Started Jul 16 06:49:59 PM PDT 24
Finished Jul 16 06:50:02 PM PDT 24
Peak memory 207056 kb
Host smart-b54f6020-8745-43de-aa5b-56eb2f2184de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
48787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2232648787
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3526573745
Short name T1733
Test name
Test status
Simulation time 231596824 ps
CPU time 0.89 seconds
Started Jul 16 06:50:00 PM PDT 24
Finished Jul 16 06:50:03 PM PDT 24
Peak memory 206732 kb
Host smart-555e6ceb-21c5-4526-945e-bfbdc2118576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35265
73745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3526573745
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.670963645
Short name T1840
Test name
Test status
Simulation time 145881652 ps
CPU time 0.74 seconds
Started Jul 16 06:50:05 PM PDT 24
Finished Jul 16 06:50:08 PM PDT 24
Peak memory 206844 kb
Host smart-c799918c-ec84-4fd0-8898-91bff437dae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67096
3645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.670963645
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2917990692
Short name T1623
Test name
Test status
Simulation time 198439848 ps
CPU time 0.88 seconds
Started Jul 16 06:50:00 PM PDT 24
Finished Jul 16 06:50:02 PM PDT 24
Peak memory 206804 kb
Host smart-8e8d301b-72ae-4a99-a4d4-5c2e84c9879d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29179
90692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2917990692
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1978658756
Short name T212
Test name
Test status
Simulation time 9213454141 ps
CPU time 83.58 seconds
Started Jul 16 06:50:00 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 207096 kb
Host smart-2f5c40b4-77f2-40f7-9147-1ac2e67e67d1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1978658756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1978658756
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1328732595
Short name T2141
Test name
Test status
Simulation time 8209600702 ps
CPU time 75.26 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:51:21 PM PDT 24
Peak memory 207124 kb
Host smart-f62ed147-129e-40ec-9892-77199378764b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13287
32595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1328732595
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1019502059
Short name T1115
Test name
Test status
Simulation time 234530312 ps
CPU time 0.94 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:06 PM PDT 24
Peak memory 206800 kb
Host smart-38b1bd03-27ec-43e0-8600-71f92d98e74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10195
02059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1019502059
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2359506943
Short name T1200
Test name
Test status
Simulation time 23341015789 ps
CPU time 25.28 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:28 PM PDT 24
Peak memory 206972 kb
Host smart-acb9a9e7-e657-4746-a8ad-1f2693313f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23595
06943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2359506943
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2199833100
Short name T2278
Test name
Test status
Simulation time 3320888755 ps
CPU time 3.67 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:50:11 PM PDT 24
Peak memory 206880 kb
Host smart-352a402a-57ea-4329-9f69-39dd9f5efb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21998
33100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2199833100
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2738998919
Short name T734
Test name
Test status
Simulation time 6794499379 ps
CPU time 181.01 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:53:09 PM PDT 24
Peak memory 207108 kb
Host smart-1203da7e-e95c-48a0-bfac-da6014e15173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27389
98919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2738998919
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.228966679
Short name T1852
Test name
Test status
Simulation time 3904587820 ps
CPU time 106.82 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:51:53 PM PDT 24
Peak memory 207084 kb
Host smart-7fe69409-ce31-4e0a-9db4-9ac0218d0883
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=228966679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.228966679
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2949807286
Short name T2699
Test name
Test status
Simulation time 234526509 ps
CPU time 0.95 seconds
Started Jul 16 06:49:59 PM PDT 24
Finished Jul 16 06:50:01 PM PDT 24
Peak memory 206732 kb
Host smart-f358ed18-10fa-4a80-aaac-4e6a0a685bb8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2949807286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2949807286
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1206070602
Short name T1139
Test name
Test status
Simulation time 192566609 ps
CPU time 0.96 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:04 PM PDT 24
Peak memory 206816 kb
Host smart-8f46f347-2c1f-4b71-affa-012ee7ed3e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060
70602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1206070602
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2931847559
Short name T858
Test name
Test status
Simulation time 5134561021 ps
CPU time 36.64 seconds
Started Jul 16 06:50:00 PM PDT 24
Finished Jul 16 06:50:38 PM PDT 24
Peak memory 207128 kb
Host smart-ab7b3cf2-a093-4f43-9374-b3f04e142419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
47559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2931847559
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1164621816
Short name T1455
Test name
Test status
Simulation time 6911035264 ps
CPU time 63.97 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:51:07 PM PDT 24
Peak memory 207064 kb
Host smart-e958d327-0322-4150-a8c0-848afdfcb588
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1164621816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1164621816
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3002730194
Short name T1328
Test name
Test status
Simulation time 225235283 ps
CPU time 0.89 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:03 PM PDT 24
Peak memory 206888 kb
Host smart-ee02f8f0-8987-4884-9c6d-26ac26c759a8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3002730194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3002730194
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1100715281
Short name T2250
Test name
Test status
Simulation time 154566996 ps
CPU time 0.82 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:03 PM PDT 24
Peak memory 206884 kb
Host smart-271b2e47-c5c4-46ae-9fdf-252d9def8e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11007
15281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1100715281
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.541118954
Short name T376
Test name
Test status
Simulation time 194213069 ps
CPU time 0.87 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:08 PM PDT 24
Peak memory 206852 kb
Host smart-cff0888e-4138-4e2e-a296-22708ea03a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54111
8954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.541118954
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2592837607
Short name T2068
Test name
Test status
Simulation time 152142346 ps
CPU time 0.76 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:06 PM PDT 24
Peak memory 207028 kb
Host smart-6c3929d3-8ad4-4c53-9b1a-ee53462416a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
37607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2592837607
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3402560486
Short name T1364
Test name
Test status
Simulation time 199619625 ps
CPU time 0.83 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206840 kb
Host smart-23960a6f-5b6f-4583-87a7-90bc6ed02953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
60486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3402560486
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2986178296
Short name T1135
Test name
Test status
Simulation time 163887147 ps
CPU time 0.83 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206836 kb
Host smart-b756eb6d-29af-4276-a667-4cd5b466b2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29861
78296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2986178296
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2029180589
Short name T1144
Test name
Test status
Simulation time 193468785 ps
CPU time 0.89 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:03 PM PDT 24
Peak memory 206856 kb
Host smart-54a25b54-902c-48f2-b1b2-3136497970bc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2029180589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2029180589
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2370861685
Short name T2414
Test name
Test status
Simulation time 185799320 ps
CPU time 0.78 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206876 kb
Host smart-1672ecb8-e998-4991-89b6-a8b2560861c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
61685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2370861685
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2450681840
Short name T2293
Test name
Test status
Simulation time 69570720 ps
CPU time 0.71 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:04 PM PDT 24
Peak memory 206772 kb
Host smart-10f3006e-e945-415d-8fa3-438fa54ed71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24506
81840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2450681840
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.613187196
Short name T1694
Test name
Test status
Simulation time 23566354903 ps
CPU time 51.86 seconds
Started Jul 16 06:50:00 PM PDT 24
Finished Jul 16 06:50:53 PM PDT 24
Peak memory 207176 kb
Host smart-9a704da9-c4ba-4da9-9a80-8395fc94bd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61318
7196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.613187196
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1491852111
Short name T2434
Test name
Test status
Simulation time 210050920 ps
CPU time 0.91 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:04 PM PDT 24
Peak memory 206844 kb
Host smart-17047960-9741-4782-bbc4-f6213837b6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14918
52111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1491852111
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2270835687
Short name T1188
Test name
Test status
Simulation time 265588268 ps
CPU time 0.93 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:04 PM PDT 24
Peak memory 206892 kb
Host smart-e5b431f1-02c6-4ead-a97d-3182f534a2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22708
35687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2270835687
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1126583152
Short name T2605
Test name
Test status
Simulation time 188722589 ps
CPU time 0.84 seconds
Started Jul 16 06:50:00 PM PDT 24
Finished Jul 16 06:50:02 PM PDT 24
Peak memory 206792 kb
Host smart-5b03c2a4-12a3-42fa-ae9e-10525f5de650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11265
83152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1126583152
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2863882934
Short name T2481
Test name
Test status
Simulation time 215154981 ps
CPU time 0.94 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:06 PM PDT 24
Peak memory 206856 kb
Host smart-40bc59c3-cf54-4240-b12e-387a1a4fa9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28638
82934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2863882934
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3559210249
Short name T1865
Test name
Test status
Simulation time 187334641 ps
CPU time 0.84 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 207028 kb
Host smart-f0f20a9f-e9fd-4e6f-80b2-5a9ba1b54cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35592
10249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3559210249
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.1065258440
Short name T1178
Test name
Test status
Simulation time 155434171 ps
CPU time 0.81 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:05 PM PDT 24
Peak memory 206868 kb
Host smart-18041a9a-4576-41a9-9aea-b096ac747b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10652
58440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1065258440
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.288563708
Short name T24
Test name
Test status
Simulation time 160571781 ps
CPU time 0.78 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:04 PM PDT 24
Peak memory 206808 kb
Host smart-035fa1fb-a117-4f0d-a59e-eb346c10dd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28856
3708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.288563708
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.364791502
Short name T2552
Test name
Test status
Simulation time 244688017 ps
CPU time 0.93 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:50:09 PM PDT 24
Peak memory 206812 kb
Host smart-6a2b2e43-21eb-4763-adaa-7d09758a8c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36479
1502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.364791502
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2986831289
Short name T1436
Test name
Test status
Simulation time 5340145020 ps
CPU time 38.34 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:43 PM PDT 24
Peak memory 207124 kb
Host smart-eb3790b0-349e-47b1-9d67-af7f01c5d7b6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2986831289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2986831289
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.929317712
Short name T539
Test name
Test status
Simulation time 237036168 ps
CPU time 0.9 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:06 PM PDT 24
Peak memory 206752 kb
Host smart-342030cf-bd9e-4bfe-8ea8-c220c58762ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92931
7712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.929317712
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1475501855
Short name T1329
Test name
Test status
Simulation time 194612678 ps
CPU time 0.82 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:50:08 PM PDT 24
Peak memory 206804 kb
Host smart-e2dde526-1fc4-44dd-b4b4-d209ed781a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14755
01855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1475501855
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.2396541622
Short name T2240
Test name
Test status
Simulation time 253290152 ps
CPU time 0.93 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206864 kb
Host smart-1acb2944-27af-45eb-a469-0bd93f6d3833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965
41622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.2396541622
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3707161658
Short name T654
Test name
Test status
Simulation time 5681608876 ps
CPU time 44.66 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:51 PM PDT 24
Peak memory 207076 kb
Host smart-c4703855-bc30-4b40-b5ce-6580992f8b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37071
61658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3707161658
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3337531076
Short name T742
Test name
Test status
Simulation time 4351095510 ps
CPU time 4.58 seconds
Started Jul 16 06:50:02 PM PDT 24
Finished Jul 16 06:50:10 PM PDT 24
Peak memory 207024 kb
Host smart-53457d19-279e-4eca-9edb-6c6a0c50e2c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3337531076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3337531076
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2997641141
Short name T2643
Test name
Test status
Simulation time 13377255839 ps
CPU time 11.54 seconds
Started Jul 16 06:50:01 PM PDT 24
Finished Jul 16 06:50:15 PM PDT 24
Peak memory 207080 kb
Host smart-4e9aa4f9-1b67-4b99-9a7d-c691409f0189
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2997641141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2997641141
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2476445286
Short name T1326
Test name
Test status
Simulation time 23366493791 ps
CPU time 25.82 seconds
Started Jul 16 06:49:59 PM PDT 24
Finished Jul 16 06:50:26 PM PDT 24
Peak memory 206932 kb
Host smart-2df6ce01-4e94-4ffe-8961-32e00329263c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2476445286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.2476445286
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.4265868117
Short name T1833
Test name
Test status
Simulation time 156465616 ps
CPU time 0.78 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206752 kb
Host smart-561af81d-9dc3-4953-a51d-4170e09f7c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42658
68117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.4265868117
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.440068462
Short name T2391
Test name
Test status
Simulation time 172794087 ps
CPU time 0.82 seconds
Started Jul 16 06:49:59 PM PDT 24
Finished Jul 16 06:50:01 PM PDT 24
Peak memory 206848 kb
Host smart-2b2c086a-bcad-46ae-8d57-99b71e7e5593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44006
8462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.440068462
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.1632974074
Short name T1640
Test name
Test status
Simulation time 402897567 ps
CPU time 1.26 seconds
Started Jul 16 06:50:05 PM PDT 24
Finished Jul 16 06:50:10 PM PDT 24
Peak memory 206808 kb
Host smart-f231da25-090d-4c6d-9023-e7dbdfa575c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16329
74074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1632974074
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3482817513
Short name T832
Test name
Test status
Simulation time 359960856 ps
CPU time 1.1 seconds
Started Jul 16 06:50:05 PM PDT 24
Finished Jul 16 06:50:09 PM PDT 24
Peak memory 206824 kb
Host smart-c4fd876e-d1f7-46e1-951b-d5dd6cfea610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34828
17513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3482817513
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.956406629
Short name T158
Test name
Test status
Simulation time 6648380894 ps
CPU time 11.75 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:50:19 PM PDT 24
Peak memory 207144 kb
Host smart-90cc6bc5-aeca-478e-9cdd-91a5a281a245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95640
6629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.956406629
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.2286851035
Short name T2504
Test name
Test status
Simulation time 155740535 ps
CPU time 0.8 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:50:09 PM PDT 24
Peak memory 206880 kb
Host smart-c203b109-7b2b-41c6-a31a-8aaaf11c5798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22868
51035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.2286851035
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2241238396
Short name T2133
Test name
Test status
Simulation time 469780811 ps
CPU time 1.36 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:50:09 PM PDT 24
Peak memory 206824 kb
Host smart-0b838654-9880-4e21-82f7-c931fcecda1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22412
38396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2241238396
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.388911171
Short name T560
Test name
Test status
Simulation time 147908660 ps
CPU time 0.79 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206888 kb
Host smart-50958cec-e4a1-4007-ac44-48f80e449221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38891
1171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.388911171
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2121842308
Short name T443
Test name
Test status
Simulation time 42110979 ps
CPU time 0.67 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:50:08 PM PDT 24
Peak memory 206876 kb
Host smart-8ad6602e-eb32-4553-9383-d5e8caef0114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21218
42308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2121842308
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.4121186640
Short name T1516
Test name
Test status
Simulation time 917631416 ps
CPU time 2.11 seconds
Started Jul 16 06:50:04 PM PDT 24
Finished Jul 16 06:50:10 PM PDT 24
Peak memory 207004 kb
Host smart-129b155f-862c-48ff-986e-bfa7253e1383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41211
86640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.4121186640
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1697594047
Short name T2341
Test name
Test status
Simulation time 182917742 ps
CPU time 2.02 seconds
Started Jul 16 06:50:06 PM PDT 24
Finished Jul 16 06:50:10 PM PDT 24
Peak memory 207076 kb
Host smart-b693fbd1-61cd-46ba-9a8b-66a36b4faacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
94047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1697594047
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1637171115
Short name T2588
Test name
Test status
Simulation time 198289922 ps
CPU time 0.83 seconds
Started Jul 16 06:50:03 PM PDT 24
Finished Jul 16 06:50:07 PM PDT 24
Peak memory 206884 kb
Host smart-91759051-9707-40fe-8aed-eb17850b679e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
71115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1637171115
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.119290789
Short name T1544
Test name
Test status
Simulation time 194150704 ps
CPU time 0.82 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:20 PM PDT 24
Peak memory 206796 kb
Host smart-c1ce4e62-e76c-45ac-bf8f-d2983c725ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11929
0789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.119290789
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1037000362
Short name T1602
Test name
Test status
Simulation time 215684579 ps
CPU time 0.89 seconds
Started Jul 16 06:50:19 PM PDT 24
Finished Jul 16 06:50:24 PM PDT 24
Peak memory 206760 kb
Host smart-d75d8724-4934-4175-9c45-786ff8e160e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
00362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1037000362
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.2081161190
Short name T1702
Test name
Test status
Simulation time 11657104824 ps
CPU time 95.94 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:51:54 PM PDT 24
Peak memory 207080 kb
Host smart-22aec7db-65f6-456e-addf-e394e82fdc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20811
61190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.2081161190
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.670146707
Short name T1809
Test name
Test status
Simulation time 158526705 ps
CPU time 0.83 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:17 PM PDT 24
Peak memory 206848 kb
Host smart-1dd60bc2-1c52-476d-8d7d-42f3d038b266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67014
6707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.670146707
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.812799323
Short name T2567
Test name
Test status
Simulation time 23290275973 ps
CPU time 25.41 seconds
Started Jul 16 06:50:19 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206792 kb
Host smart-33f7eef3-cc37-4761-ad55-a4dd75bd1a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81279
9323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.812799323
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.578890300
Short name T669
Test name
Test status
Simulation time 3326440511 ps
CPU time 3.46 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:19 PM PDT 24
Peak memory 206936 kb
Host smart-326df683-a2cb-4dfd-8e31-c31909543b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57889
0300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.578890300
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.304200322
Short name T1643
Test name
Test status
Simulation time 12666165722 ps
CPU time 88.94 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 207132 kb
Host smart-876fe2da-4b20-44bc-8963-26f4e0cea41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30420
0322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.304200322
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2243391732
Short name T805
Test name
Test status
Simulation time 7355271832 ps
CPU time 52.44 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:51:11 PM PDT 24
Peak memory 207144 kb
Host smart-f06044be-d771-45b4-9c6b-5780dc2eaa86
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2243391732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2243391732
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.922874642
Short name T1928
Test name
Test status
Simulation time 236759909 ps
CPU time 0.91 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206864 kb
Host smart-d89fa66b-89a6-46fe-a000-11eb31dbfbd6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=922874642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.922874642
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1931243703
Short name T2189
Test name
Test status
Simulation time 202083005 ps
CPU time 0.88 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206860 kb
Host smart-fd7caf6d-0ba6-4ac3-b174-5d5581a306d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19312
43703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1931243703
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.4205859884
Short name T1882
Test name
Test status
Simulation time 3623220122 ps
CPU time 99.86 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 206940 kb
Host smart-2e8ea495-c322-46c9-b0c4-1ebde5e7b27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42058
59884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.4205859884
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.720230475
Short name T2621
Test name
Test status
Simulation time 5658019792 ps
CPU time 40.8 seconds
Started Jul 16 06:50:17 PM PDT 24
Finished Jul 16 06:51:02 PM PDT 24
Peak memory 207100 kb
Host smart-8a55b04e-f5aa-405c-9a66-99909f57b3b8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=720230475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.720230475
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2604349711
Short name T1454
Test name
Test status
Simulation time 170698092 ps
CPU time 0.8 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206848 kb
Host smart-234f6c57-9622-4b23-90a9-37bf1e505b57
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2604349711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2604349711
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2512396551
Short name T372
Test name
Test status
Simulation time 145536471 ps
CPU time 0.74 seconds
Started Jul 16 06:50:17 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206880 kb
Host smart-8d317a0f-f191-46ce-9d40-8a50dc081a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25123
96551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2512396551
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1522537271
Short name T2348
Test name
Test status
Simulation time 194688051 ps
CPU time 0.91 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:19 PM PDT 24
Peak memory 206816 kb
Host smart-857d41f1-3eaf-4d1c-a5d9-605818520192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15225
37271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1522537271
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.712976470
Short name T997
Test name
Test status
Simulation time 222882645 ps
CPU time 0.96 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:19 PM PDT 24
Peak memory 206844 kb
Host smart-bbeb0fc9-10e1-43ed-9233-c311b90a641a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71297
6470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.712976470
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1845222594
Short name T1684
Test name
Test status
Simulation time 217276633 ps
CPU time 0.88 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206868 kb
Host smart-dc54978a-d2bc-4e32-880f-510564b53e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18452
22594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1845222594
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3082471865
Short name T2454
Test name
Test status
Simulation time 167455048 ps
CPU time 0.83 seconds
Started Jul 16 06:50:19 PM PDT 24
Finished Jul 16 06:50:25 PM PDT 24
Peak memory 206884 kb
Host smart-2ab1a444-3cfa-4f2a-9c85-b4ee92d04c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30824
71865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3082471865
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2376262516
Short name T934
Test name
Test status
Simulation time 180106170 ps
CPU time 0.88 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206836 kb
Host smart-b24427da-5689-40f8-894a-3f6c25a60fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23762
62516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2376262516
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2890657127
Short name T627
Test name
Test status
Simulation time 223294648 ps
CPU time 0.96 seconds
Started Jul 16 06:50:21 PM PDT 24
Finished Jul 16 06:50:26 PM PDT 24
Peak memory 206880 kb
Host smart-8421b1c9-b142-4d27-a9cb-55da16d31d87
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2890657127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2890657127
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1699990816
Short name T733
Test name
Test status
Simulation time 150469106 ps
CPU time 0.75 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206828 kb
Host smart-d22905c1-7336-4411-9b2e-80f5030fd6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16999
90816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1699990816
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.7201463
Short name T33
Test name
Test status
Simulation time 65653735 ps
CPU time 0.7 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206828 kb
Host smart-6ead78a8-3b7a-4da1-9f70-7ab10674a8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72014
63 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.7201463
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1386911746
Short name T236
Test name
Test status
Simulation time 15854371806 ps
CPU time 35.9 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:51 PM PDT 24
Peak memory 207180 kb
Host smart-567220a9-0601-4679-9bc7-4bb255c4305a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13869
11746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1386911746
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2499551114
Short name T2148
Test name
Test status
Simulation time 156713177 ps
CPU time 0.83 seconds
Started Jul 16 06:50:18 PM PDT 24
Finished Jul 16 06:50:23 PM PDT 24
Peak memory 206832 kb
Host smart-13b72534-371a-49e3-af57-34f3c3953e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24995
51114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2499551114
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1879973995
Short name T2701
Test name
Test status
Simulation time 257828562 ps
CPU time 0.9 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:19 PM PDT 24
Peak memory 206668 kb
Host smart-c8bedf05-642c-4e83-a3c1-5cd9aef3f7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18799
73995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1879973995
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2398974258
Short name T624
Test name
Test status
Simulation time 183681771 ps
CPU time 0.86 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:19 PM PDT 24
Peak memory 206872 kb
Host smart-d70b2e01-e3d2-4a0a-9470-04a997855df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23989
74258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2398974258
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1006085597
Short name T2467
Test name
Test status
Simulation time 222236858 ps
CPU time 0.92 seconds
Started Jul 16 06:50:19 PM PDT 24
Finished Jul 16 06:50:24 PM PDT 24
Peak memory 206860 kb
Host smart-7a1bd62b-091f-4276-8b6e-c314e9b2afd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10060
85597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1006085597
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2862744437
Short name T2745
Test name
Test status
Simulation time 177072356 ps
CPU time 0.8 seconds
Started Jul 16 06:50:19 PM PDT 24
Finished Jul 16 06:50:24 PM PDT 24
Peak memory 206800 kb
Host smart-e5409df0-2b4c-4f1a-8270-989397bd55ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28627
44437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2862744437
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3412463871
Short name T1307
Test name
Test status
Simulation time 189891796 ps
CPU time 0.8 seconds
Started Jul 16 06:50:17 PM PDT 24
Finished Jul 16 06:50:22 PM PDT 24
Peak memory 206872 kb
Host smart-eb2ef2e6-474f-4ce5-be75-1d1d5755c8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34124
63871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3412463871
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1930228014
Short name T2241
Test name
Test status
Simulation time 154500776 ps
CPU time 0.77 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206884 kb
Host smart-625f43f4-291b-4237-acea-27f0097972e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19302
28014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1930228014
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.325626963
Short name T1158
Test name
Test status
Simulation time 195606286 ps
CPU time 0.86 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206888 kb
Host smart-948b6363-3f08-40a0-906f-006a365f6f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32562
6963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.325626963
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.401400396
Short name T2155
Test name
Test status
Simulation time 3998459184 ps
CPU time 37.25 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:55 PM PDT 24
Peak memory 207120 kb
Host smart-5182a01d-67cc-4436-9942-c8dee20bde31
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=401400396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.401400396
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.4038725564
Short name T1104
Test name
Test status
Simulation time 186431045 ps
CPU time 0.81 seconds
Started Jul 16 06:50:20 PM PDT 24
Finished Jul 16 06:50:25 PM PDT 24
Peak memory 206808 kb
Host smart-09d874fe-25e0-4e53-9348-a29552162b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387
25564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.4038725564
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2589280566
Short name T1666
Test name
Test status
Simulation time 149202132 ps
CPU time 0.81 seconds
Started Jul 16 06:50:18 PM PDT 24
Finished Jul 16 06:50:23 PM PDT 24
Peak memory 206748 kb
Host smart-755d9272-1d63-48cd-bc3c-f9df89a01fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25892
80566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2589280566
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1611883967
Short name T2181
Test name
Test status
Simulation time 1328694765 ps
CPU time 2.86 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:22 PM PDT 24
Peak memory 207052 kb
Host smart-91b4c7db-ae73-460d-8d5c-e48e85ca6e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16118
83967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1611883967
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.857798076
Short name T1179
Test name
Test status
Simulation time 4685170225 ps
CPU time 32.99 seconds
Started Jul 16 06:50:19 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206996 kb
Host smart-dffa96f0-bf17-4a51-b805-36e05e9cd7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85779
8076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.857798076
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.4165878954
Short name T2744
Test name
Test status
Simulation time 38931675 ps
CPU time 0.65 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206880 kb
Host smart-15c68bc8-7862-4ae9-ae8f-1dff51bd0fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4165878954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.4165878954
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2854722910
Short name T1239
Test name
Test status
Simulation time 3669935155 ps
CPU time 4.48 seconds
Started Jul 16 06:50:18 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206672 kb
Host smart-ec19a72c-be35-42ff-9c22-ca37982ea1ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2854722910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.2854722910
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3809187345
Short name T2129
Test name
Test status
Simulation time 13318041052 ps
CPU time 12.36 seconds
Started Jul 16 06:50:20 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206872 kb
Host smart-95b9cabc-6c2c-41f1-9892-d1040107e7ac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3809187345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3809187345
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3795470711
Short name T1659
Test name
Test status
Simulation time 23391457308 ps
CPU time 24 seconds
Started Jul 16 06:50:17 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 207064 kb
Host smart-09b13781-cfea-460a-8341-4ba2eb5f0ef5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3795470711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.3795470711
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2257186438
Short name T1055
Test name
Test status
Simulation time 146721813 ps
CPU time 0.8 seconds
Started Jul 16 06:50:17 PM PDT 24
Finished Jul 16 06:50:22 PM PDT 24
Peak memory 206824 kb
Host smart-a775a447-7ed6-4064-afc1-06cf4b93f733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22571
86438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2257186438
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3670344901
Short name T825
Test name
Test status
Simulation time 151543213 ps
CPU time 0.81 seconds
Started Jul 16 06:50:18 PM PDT 24
Finished Jul 16 06:50:23 PM PDT 24
Peak memory 206648 kb
Host smart-2786c09a-422c-4688-8f99-e8722d1ab60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36703
44901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3670344901
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1121326219
Short name T619
Test name
Test status
Simulation time 243876153 ps
CPU time 1.02 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:50:16 PM PDT 24
Peak memory 206788 kb
Host smart-4d7f0a34-eacc-48ae-ba3c-d4bd2eb3c43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11213
26219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1121326219
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.397541407
Short name T1108
Test name
Test status
Simulation time 950569606 ps
CPU time 2.21 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 207040 kb
Host smart-747cd2b2-2076-4064-85ec-740807159284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
1407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.397541407
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3264225602
Short name T2683
Test name
Test status
Simulation time 18293148897 ps
CPU time 35.24 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:54 PM PDT 24
Peak memory 206940 kb
Host smart-79e00763-c12f-4047-824b-86c459341f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32642
25602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3264225602
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1720810496
Short name T2688
Test name
Test status
Simulation time 410902453 ps
CPU time 1.14 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206888 kb
Host smart-beba9362-56ee-4f9a-9ba4-3723a31a6a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17208
10496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1720810496
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2848000720
Short name T1581
Test name
Test status
Simulation time 182396376 ps
CPU time 0.82 seconds
Started Jul 16 06:50:18 PM PDT 24
Finished Jul 16 06:50:23 PM PDT 24
Peak memory 206884 kb
Host smart-1e8b0b72-2822-4cd3-9862-ee40d8c8266b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
00720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2848000720
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2828203981
Short name T1961
Test name
Test status
Simulation time 38702135 ps
CPU time 0.64 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206740 kb
Host smart-7abb6c81-1dde-481c-ba52-309ad35a977f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28282
03981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2828203981
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1922071585
Short name T960
Test name
Test status
Simulation time 882416876 ps
CPU time 2.31 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:29 PM PDT 24
Peak memory 207060 kb
Host smart-ff02668a-d812-4829-b564-09f90a6603df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19220
71585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1922071585
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1584221060
Short name T2339
Test name
Test status
Simulation time 175702252 ps
CPU time 0.76 seconds
Started Jul 16 06:50:21 PM PDT 24
Finished Jul 16 06:50:26 PM PDT 24
Peak memory 206864 kb
Host smart-1270745d-2469-41c9-8ffb-b03d9e5eef7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15842
21060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1584221060
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.731058025
Short name T2424
Test name
Test status
Simulation time 148439151 ps
CPU time 0.77 seconds
Started Jul 16 06:50:21 PM PDT 24
Finished Jul 16 06:50:26 PM PDT 24
Peak memory 206580 kb
Host smart-25b9e148-34b9-441a-9e72-648bbc18c622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73105
8025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.731058025
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3466282460
Short name T440
Test name
Test status
Simulation time 219027062 ps
CPU time 0.91 seconds
Started Jul 16 06:50:18 PM PDT 24
Finished Jul 16 06:50:22 PM PDT 24
Peak memory 206852 kb
Host smart-a0fc1452-1323-4f21-8f69-ef7fcf41d939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34662
82460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3466282460
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.3933813606
Short name T2028
Test name
Test status
Simulation time 5175663606 ps
CPU time 47.32 seconds
Started Jul 16 06:50:15 PM PDT 24
Finished Jul 16 06:51:04 PM PDT 24
Peak memory 207080 kb
Host smart-e2f1b41b-72fe-4627-acb3-d538515e6133
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3933813606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3933813606
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.3192339956
Short name T927
Test name
Test status
Simulation time 12348516772 ps
CPU time 112 seconds
Started Jul 16 06:50:21 PM PDT 24
Finished Jul 16 06:52:17 PM PDT 24
Peak memory 206868 kb
Host smart-53d2fe5f-28a5-419f-8ed6-5f9f78069f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31923
39956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3192339956
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.121001187
Short name T2284
Test name
Test status
Simulation time 203797117 ps
CPU time 0.87 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 206840 kb
Host smart-250f1cba-fce8-4bd1-ac51-22f43b416491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12100
1187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.121001187
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.193412287
Short name T1042
Test name
Test status
Simulation time 23274314602 ps
CPU time 22.88 seconds
Started Jul 16 06:50:20 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206932 kb
Host smart-798f6cb1-917e-420b-b8c1-a2cb9c09324b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19341
2287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.193412287
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2317405286
Short name T1206
Test name
Test status
Simulation time 3327339733 ps
CPU time 3.72 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:30 PM PDT 24
Peak memory 206928 kb
Host smart-7d803f78-8147-4d54-afb7-fbfa29219820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23174
05286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2317405286
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.207035936
Short name T85
Test name
Test status
Simulation time 11319546816 ps
CPU time 78.22 seconds
Started Jul 16 06:50:16 PM PDT 24
Finished Jul 16 06:51:37 PM PDT 24
Peak memory 207160 kb
Host smart-aac5f05d-f3d7-4c56-af79-fcb53a34d28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20703
5936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.207035936
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1948668035
Short name T1165
Test name
Test status
Simulation time 4381673214 ps
CPU time 43.38 seconds
Started Jul 16 06:50:20 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 207052 kb
Host smart-b12ede00-62a4-4ed9-866d-5a7e78ab39d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1948668035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1948668035
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.164132389
Short name T963
Test name
Test status
Simulation time 271597941 ps
CPU time 0.95 seconds
Started Jul 16 06:50:18 PM PDT 24
Finished Jul 16 06:50:24 PM PDT 24
Peak memory 206880 kb
Host smart-69eaf9c5-62b5-4000-a099-fd562e729466
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=164132389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.164132389
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1811909749
Short name T2661
Test name
Test status
Simulation time 197117968 ps
CPU time 0.84 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206812 kb
Host smart-d9c98f9c-bc02-47cf-a91c-a2046c6340cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18119
09749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1811909749
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2091350424
Short name T2549
Test name
Test status
Simulation time 3815445574 ps
CPU time 36.97 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:51:03 PM PDT 24
Peak memory 207080 kb
Host smart-f205128f-5791-4611-9553-5f8bae2738c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20913
50424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2091350424
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.839816388
Short name T2535
Test name
Test status
Simulation time 5638562018 ps
CPU time 40.02 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:51:06 PM PDT 24
Peak memory 207072 kb
Host smart-66388999-161d-4ff4-8009-705b1030cb03
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=839816388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.839816388
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3355448963
Short name T1330
Test name
Test status
Simulation time 159888870 ps
CPU time 0.8 seconds
Started Jul 16 06:50:21 PM PDT 24
Finished Jul 16 06:50:26 PM PDT 24
Peak memory 206888 kb
Host smart-ddbfbeff-d9b5-412f-be92-5d22540556ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3355448963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3355448963
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1451662133
Short name T518
Test name
Test status
Simulation time 156306664 ps
CPU time 0.78 seconds
Started Jul 16 06:50:20 PM PDT 24
Finished Jul 16 06:50:25 PM PDT 24
Peak memory 206792 kb
Host smart-b63cdcb2-e53a-49b4-924d-174fe54b8853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14516
62133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1451662133
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3062440849
Short name T107
Test name
Test status
Simulation time 199321708 ps
CPU time 0.86 seconds
Started Jul 16 06:50:21 PM PDT 24
Finished Jul 16 06:50:26 PM PDT 24
Peak memory 206860 kb
Host smart-568461f4-6e4b-4291-97c9-4cb50a9f5488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30624
40849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3062440849
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2056783716
Short name T1559
Test name
Test status
Simulation time 194906568 ps
CPU time 0.81 seconds
Started Jul 16 06:50:19 PM PDT 24
Finished Jul 16 06:50:24 PM PDT 24
Peak memory 206892 kb
Host smart-ffa106ab-d16d-46e8-9fc2-7f0e50ca3030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20567
83716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2056783716
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2944290066
Short name T547
Test name
Test status
Simulation time 175909784 ps
CPU time 0.83 seconds
Started Jul 16 06:50:20 PM PDT 24
Finished Jul 16 06:50:25 PM PDT 24
Peak memory 206796 kb
Host smart-42cf7ba2-fd1a-46b7-9472-7b7e8fb5da6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
90066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2944290066
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.376743669
Short name T1925
Test name
Test status
Simulation time 198761461 ps
CPU time 0.82 seconds
Started Jul 16 06:50:20 PM PDT 24
Finished Jul 16 06:50:25 PM PDT 24
Peak memory 206872 kb
Host smart-de90e1dc-ef87-4ff6-bd81-cff492ebda7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37674
3669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.376743669
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3648213538
Short name T513
Test name
Test status
Simulation time 192202944 ps
CPU time 0.84 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206816 kb
Host smart-b4efbb60-4d5f-4eb1-a612-77b5e7fa7d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36482
13538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3648213538
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3702372546
Short name T2614
Test name
Test status
Simulation time 227329162 ps
CPU time 0.99 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206884 kb
Host smart-2ce46c44-a9f7-4343-908b-a22c6930909c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3702372546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3702372546
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.958632220
Short name T1675
Test name
Test status
Simulation time 179287156 ps
CPU time 0.8 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206844 kb
Host smart-2ecce745-89ab-4ade-bd04-c46101d4d2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95863
2220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.958632220
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1731680739
Short name T1747
Test name
Test status
Simulation time 34617356 ps
CPU time 0.64 seconds
Started Jul 16 06:50:22 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206860 kb
Host smart-e77c07d9-ac28-4adb-96ee-1d1451e19f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17316
80739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1731680739
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.4072791133
Short name T263
Test name
Test status
Simulation time 19218960417 ps
CPU time 42.98 seconds
Started Jul 16 06:50:23 PM PDT 24
Finished Jul 16 06:51:11 PM PDT 24
Peak memory 207076 kb
Host smart-4f105324-fd64-4ad2-afbf-cdc522c4c757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40727
91133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.4072791133
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.756821604
Short name T2630
Test name
Test status
Simulation time 167843298 ps
CPU time 0.81 seconds
Started Jul 16 06:50:23 PM PDT 24
Finished Jul 16 06:50:28 PM PDT 24
Peak memory 206864 kb
Host smart-ead4d8b2-5d2a-4114-ba88-1b4742f3d196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75682
1604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.756821604
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.828607518
Short name T1712
Test name
Test status
Simulation time 189644659 ps
CPU time 0.82 seconds
Started Jul 16 06:50:29 PM PDT 24
Finished Jul 16 06:50:32 PM PDT 24
Peak memory 206892 kb
Host smart-81330a97-aef9-4028-b5a1-0e7c360401df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82860
7518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.828607518
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2001519393
Short name T1374
Test name
Test status
Simulation time 243106965 ps
CPU time 0.92 seconds
Started Jul 16 06:50:26 PM PDT 24
Finished Jul 16 06:50:30 PM PDT 24
Peak memory 206884 kb
Host smart-6cc94b67-1237-4ae4-af66-be94e3535dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20015
19393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2001519393
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2067278124
Short name T1344
Test name
Test status
Simulation time 176294748 ps
CPU time 0.84 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206756 kb
Host smart-81480aec-31ff-4438-829a-7aca1760b5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672
78124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2067278124
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3800061824
Short name T2410
Test name
Test status
Simulation time 155288311 ps
CPU time 0.77 seconds
Started Jul 16 06:50:29 PM PDT 24
Finished Jul 16 06:50:31 PM PDT 24
Peak memory 206908 kb
Host smart-e1c009bb-d5af-4709-a6ac-f59f5e9e8506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38000
61824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3800061824
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1298082337
Short name T667
Test name
Test status
Simulation time 202231827 ps
CPU time 0.83 seconds
Started Jul 16 06:50:27 PM PDT 24
Finished Jul 16 06:50:30 PM PDT 24
Peak memory 206852 kb
Host smart-1d9b5801-263c-4266-be81-ad4396f689c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12980
82337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1298082337
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1939527931
Short name T1403
Test name
Test status
Simulation time 256970136 ps
CPU time 0.98 seconds
Started Jul 16 06:50:29 PM PDT 24
Finished Jul 16 06:50:31 PM PDT 24
Peak memory 206848 kb
Host smart-794c1e16-bda8-41ff-b2c8-342fb974971f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19395
27931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1939527931
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2520923122
Short name T1253
Test name
Test status
Simulation time 5356609742 ps
CPU time 147.06 seconds
Started Jul 16 06:50:30 PM PDT 24
Finished Jul 16 06:52:58 PM PDT 24
Peak memory 207132 kb
Host smart-9499bcc6-cc87-4da9-a2c0-b0e52db4ed6a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2520923122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2520923122
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3210654522
Short name T2300
Test name
Test status
Simulation time 176326905 ps
CPU time 0.87 seconds
Started Jul 16 06:50:26 PM PDT 24
Finished Jul 16 06:50:30 PM PDT 24
Peak memory 206736 kb
Host smart-939579a6-cf01-4721-8f5d-ad81d79569ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32106
54522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3210654522
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.391692206
Short name T2622
Test name
Test status
Simulation time 158178963 ps
CPU time 0.77 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206812 kb
Host smart-165023fa-5d9d-49b7-91e5-32e0854dbecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39169
2206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.391692206
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1220461570
Short name T932
Test name
Test status
Simulation time 1048366551 ps
CPU time 2.32 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:39 PM PDT 24
Peak memory 207036 kb
Host smart-25be087f-af47-449b-ab5b-c4c09dbf3d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12204
61570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1220461570
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3071970596
Short name T2650
Test name
Test status
Simulation time 5596267692 ps
CPU time 37.9 seconds
Started Jul 16 06:50:34 PM PDT 24
Finished Jul 16 06:51:15 PM PDT 24
Peak memory 207036 kb
Host smart-49abd0af-571d-4100-a3b7-63fabf49a874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30719
70596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3071970596
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2404350415
Short name T1547
Test name
Test status
Simulation time 56723483 ps
CPU time 0.69 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:43 PM PDT 24
Peak memory 206896 kb
Host smart-f7491b42-2a51-4a24-bea3-51c931c5d560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2404350415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2404350415
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.4249423886
Short name T1021
Test name
Test status
Simulation time 3405894034 ps
CPU time 3.99 seconds
Started Jul 16 06:50:27 PM PDT 24
Finished Jul 16 06:50:33 PM PDT 24
Peak memory 207128 kb
Host smart-bc083e03-24d4-4be3-85fb-8e4e796a75da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4249423886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.4249423886
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.4263652513
Short name T550
Test name
Test status
Simulation time 13409546225 ps
CPU time 12.43 seconds
Started Jul 16 06:50:36 PM PDT 24
Finished Jul 16 06:50:53 PM PDT 24
Peak memory 206668 kb
Host smart-0a00ed54-abdf-4bb9-9912-6ca703f268e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4263652513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.4263652513
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2398976663
Short name T2442
Test name
Test status
Simulation time 23392766039 ps
CPU time 22.88 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:51:00 PM PDT 24
Peak memory 206964 kb
Host smart-481082b9-c949-45fe-a437-d175699de6c6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2398976663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.2398976663
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2506305669
Short name T1474
Test name
Test status
Simulation time 164429149 ps
CPU time 0.77 seconds
Started Jul 16 06:50:25 PM PDT 24
Finished Jul 16 06:50:29 PM PDT 24
Peak memory 206888 kb
Host smart-e725f552-0ce1-4612-a246-3590fcbec3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
05669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2506305669
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.551903836
Short name T638
Test name
Test status
Simulation time 197335108 ps
CPU time 0.82 seconds
Started Jul 16 06:50:25 PM PDT 24
Finished Jul 16 06:50:29 PM PDT 24
Peak memory 206876 kb
Host smart-dee582c5-1950-4879-88e1-7d0e2f8f8746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55190
3836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.551903836
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1159097284
Short name T686
Test name
Test status
Simulation time 392026000 ps
CPU time 1.31 seconds
Started Jul 16 06:50:25 PM PDT 24
Finished Jul 16 06:50:30 PM PDT 24
Peak memory 206880 kb
Host smart-bbf9cffe-ae3f-4f14-a75b-1d1ca77441ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11590
97284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1159097284
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3740894007
Short name T1500
Test name
Test status
Simulation time 419687321 ps
CPU time 1.19 seconds
Started Jul 16 06:50:29 PM PDT 24
Finished Jul 16 06:50:32 PM PDT 24
Peak memory 206896 kb
Host smart-5f6a1d00-a167-4d11-bc0b-116c6acee97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37408
94007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3740894007
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.1165021025
Short name T161
Test name
Test status
Simulation time 13421075694 ps
CPU time 24.94 seconds
Started Jul 16 06:50:31 PM PDT 24
Finished Jul 16 06:50:57 PM PDT 24
Peak memory 206768 kb
Host smart-bd5a67da-8aa8-4bd3-9ddc-0f39f42d6863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11650
21025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1165021025
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3628180560
Short name T1224
Test name
Test status
Simulation time 400481603 ps
CPU time 1.29 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:38 PM PDT 24
Peak memory 206756 kb
Host smart-a21f0d82-10dd-4655-adef-98df18660f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36281
80560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3628180560
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1481485202
Short name T1891
Test name
Test status
Simulation time 169485160 ps
CPU time 0.75 seconds
Started Jul 16 06:50:29 PM PDT 24
Finished Jul 16 06:50:31 PM PDT 24
Peak memory 206852 kb
Host smart-e9f394c8-b720-4349-985c-c4786e4f5f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
85202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1481485202
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2200397812
Short name T2506
Test name
Test status
Simulation time 43570896 ps
CPU time 0.67 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206856 kb
Host smart-f068bf7b-2646-475a-b7d6-d569627d5f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
97812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2200397812
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.4102443080
Short name T956
Test name
Test status
Simulation time 991179308 ps
CPU time 2.25 seconds
Started Jul 16 06:50:28 PM PDT 24
Finished Jul 16 06:50:33 PM PDT 24
Peak memory 206976 kb
Host smart-33ff5479-2958-4dba-a309-d82fc7471e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41024
43080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.4102443080
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.413184003
Short name T2000
Test name
Test status
Simulation time 161055043 ps
CPU time 1.63 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:50:44 PM PDT 24
Peak memory 207080 kb
Host smart-4e420724-5290-441b-b901-b8d5c09c1c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41318
4003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.413184003
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.594422367
Short name T846
Test name
Test status
Simulation time 247519296 ps
CPU time 1 seconds
Started Jul 16 06:50:31 PM PDT 24
Finished Jul 16 06:50:33 PM PDT 24
Peak memory 206816 kb
Host smart-37024d97-f92a-49ce-b6b5-3ddc86074cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59442
2367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.594422367
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2725563693
Short name T912
Test name
Test status
Simulation time 191617417 ps
CPU time 0.83 seconds
Started Jul 16 06:50:31 PM PDT 24
Finished Jul 16 06:50:33 PM PDT 24
Peak memory 206556 kb
Host smart-8234c113-3cc8-4ee1-a2aa-93f475ca4833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27255
63693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2725563693
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2388437136
Short name T904
Test name
Test status
Simulation time 211044062 ps
CPU time 0.89 seconds
Started Jul 16 06:50:26 PM PDT 24
Finished Jul 16 06:50:30 PM PDT 24
Peak memory 206892 kb
Host smart-9547d0d0-7c19-4739-ba8a-10f80b84bd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23884
37136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2388437136
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3472736095
Short name T2282
Test name
Test status
Simulation time 7665672197 ps
CPU time 206.33 seconds
Started Jul 16 06:50:32 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 207068 kb
Host smart-f3e33cb0-93c6-433b-90cd-38a729838371
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3472736095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3472736095
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.4049986019
Short name T367
Test name
Test status
Simulation time 5336536779 ps
CPU time 20.75 seconds
Started Jul 16 06:50:36 PM PDT 24
Finished Jul 16 06:51:01 PM PDT 24
Peak memory 206944 kb
Host smart-d9cffa94-5ba6-4bed-82d5-27c4cf673457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40499
86019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.4049986019
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3737016428
Short name T784
Test name
Test status
Simulation time 179357367 ps
CPU time 0.82 seconds
Started Jul 16 06:50:36 PM PDT 24
Finished Jul 16 06:50:41 PM PDT 24
Peak memory 206752 kb
Host smart-d40f05fa-7eff-4e27-900a-3d73aafcf604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37370
16428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3737016428
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.20107107
Short name T2045
Test name
Test status
Simulation time 23322412551 ps
CPU time 24.38 seconds
Started Jul 16 06:50:26 PM PDT 24
Finished Jul 16 06:50:53 PM PDT 24
Peak memory 206900 kb
Host smart-d21f7d4d-e31f-4030-8e6e-451214f8a1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20107
107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.20107107
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1308845796
Short name T1578
Test name
Test status
Simulation time 3327563714 ps
CPU time 4.02 seconds
Started Jul 16 06:50:24 PM PDT 24
Finished Jul 16 06:50:32 PM PDT 24
Peak memory 206940 kb
Host smart-cd142d39-ab67-4b0d-a1e5-a70831c3b5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13088
45796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1308845796
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1243376644
Short name T670
Test name
Test status
Simulation time 12091833297 ps
CPU time 89.46 seconds
Started Jul 16 06:50:36 PM PDT 24
Finished Jul 16 06:52:10 PM PDT 24
Peak memory 207012 kb
Host smart-fb0d4ca3-2146-442f-90d1-a82c7d15cb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12433
76644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1243376644
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.683549749
Short name T1527
Test name
Test status
Simulation time 4944588808 ps
CPU time 36.09 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:51:13 PM PDT 24
Peak memory 207112 kb
Host smart-ba44add0-f58a-4e94-8f40-ece005f8d1d0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=683549749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.683549749
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3678231385
Short name T2024
Test name
Test status
Simulation time 250577382 ps
CPU time 0.94 seconds
Started Jul 16 06:50:31 PM PDT 24
Finished Jul 16 06:50:33 PM PDT 24
Peak memory 206860 kb
Host smart-da5d3485-d4fa-44dd-9107-dce3971c4694
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3678231385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3678231385
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.674897075
Short name T817
Test name
Test status
Simulation time 194224273 ps
CPU time 0.87 seconds
Started Jul 16 06:50:36 PM PDT 24
Finished Jul 16 06:50:42 PM PDT 24
Peak memory 206752 kb
Host smart-172c9ab9-c214-4389-94df-7cb453fee284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67489
7075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.674897075
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3383451190
Short name T1788
Test name
Test status
Simulation time 4395813213 ps
CPU time 32.07 seconds
Started Jul 16 06:50:29 PM PDT 24
Finished Jul 16 06:51:03 PM PDT 24
Peak memory 207104 kb
Host smart-22c4c7f8-74f6-48f6-bb47-cae97335eb46
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3383451190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3383451190
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2194098584
Short name T2593
Test name
Test status
Simulation time 180406147 ps
CPU time 0.82 seconds
Started Jul 16 06:50:30 PM PDT 24
Finished Jul 16 06:50:32 PM PDT 24
Peak memory 206896 kb
Host smart-2e11346c-82ce-401b-afeb-cf77920a4c18
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2194098584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2194098584
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.165735236
Short name T684
Test name
Test status
Simulation time 158392318 ps
CPU time 0.77 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206756 kb
Host smart-e70697ac-d163-4dcf-a92e-cbe4ece3bc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16573
5236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.165735236
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2147113064
Short name T1936
Test name
Test status
Simulation time 237935743 ps
CPU time 0.86 seconds
Started Jul 16 06:50:32 PM PDT 24
Finished Jul 16 06:50:36 PM PDT 24
Peak memory 206828 kb
Host smart-62d69bba-2c92-4fcd-a2ae-1cda1a7b50d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21471
13064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2147113064
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.705502705
Short name T925
Test name
Test status
Simulation time 191526880 ps
CPU time 0.79 seconds
Started Jul 16 06:50:30 PM PDT 24
Finished Jul 16 06:50:32 PM PDT 24
Peak memory 206896 kb
Host smart-bce641f0-bd29-467f-967a-613d2c66431a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70550
2705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.705502705
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.801935333
Short name T1033
Test name
Test status
Simulation time 184256788 ps
CPU time 0.91 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 206584 kb
Host smart-0d829078-7e12-4b99-9f3b-2c80fc9466f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80193
5333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.801935333
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3687252831
Short name T386
Test name
Test status
Simulation time 160483365 ps
CPU time 0.76 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:50:42 PM PDT 24
Peak memory 206888 kb
Host smart-d8fe4aac-8ae9-419c-87b3-97a843413ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872
52831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3687252831
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2386393239
Short name T2173
Test name
Test status
Simulation time 200317780 ps
CPU time 0.88 seconds
Started Jul 16 06:50:34 PM PDT 24
Finished Jul 16 06:50:38 PM PDT 24
Peak memory 206824 kb
Host smart-e3955394-69e0-4fce-998b-c66ba39ee60b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2386393239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2386393239
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.867955160
Short name T38
Test name
Test status
Simulation time 141272279 ps
CPU time 0.78 seconds
Started Jul 16 06:50:25 PM PDT 24
Finished Jul 16 06:50:29 PM PDT 24
Peak memory 206884 kb
Host smart-37ccac1a-92c5-497e-90fc-4962e4da83f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86795
5160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.867955160
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.149222039
Short name T36
Test name
Test status
Simulation time 94070949 ps
CPU time 0.68 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206808 kb
Host smart-7ee4d6cf-ed9f-42bf-a423-fc3f57ddf884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14922
2039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.149222039
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3793610354
Short name T2301
Test name
Test status
Simulation time 12257491996 ps
CPU time 24.59 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 206752 kb
Host smart-acec1d51-a522-41eb-bc25-c3c7417cca5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37936
10354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3793610354
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.833385612
Short name T1943
Test name
Test status
Simulation time 176337359 ps
CPU time 0.82 seconds
Started Jul 16 06:50:33 PM PDT 24
Finished Jul 16 06:50:37 PM PDT 24
Peak memory 206860 kb
Host smart-75fdd3a8-a76c-48d4-9da1-2f2bbfe2eeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83338
5612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.833385612
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1766568638
Short name T1268
Test name
Test status
Simulation time 256165990 ps
CPU time 0.92 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:44 PM PDT 24
Peak memory 206880 kb
Host smart-e651a290-21a8-40fe-ac09-635d07b0072b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17665
68638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1766568638
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1360329170
Short name T1834
Test name
Test status
Simulation time 199632883 ps
CPU time 0.84 seconds
Started Jul 16 06:50:31 PM PDT 24
Finished Jul 16 06:50:33 PM PDT 24
Peak memory 206860 kb
Host smart-ea39ca9d-9563-4596-95a3-ddafc8727ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13603
29170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1360329170
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1965243465
Short name T2204
Test name
Test status
Simulation time 189599060 ps
CPU time 0.84 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:43 PM PDT 24
Peak memory 206888 kb
Host smart-fd87ac40-a02d-428e-a513-4e2416fb7027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19652
43465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1965243465
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3151644790
Short name T1726
Test name
Test status
Simulation time 149010147 ps
CPU time 0.77 seconds
Started Jul 16 06:50:32 PM PDT 24
Finished Jul 16 06:50:35 PM PDT 24
Peak memory 206556 kb
Host smart-e2e74c1a-efa6-4825-a176-c44f72b144d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31516
44790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3151644790
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.555429967
Short name T1399
Test name
Test status
Simulation time 148539167 ps
CPU time 0.75 seconds
Started Jul 16 06:50:32 PM PDT 24
Finished Jul 16 06:50:35 PM PDT 24
Peak memory 206496 kb
Host smart-4820c879-68da-4cd0-a91f-c37c6300f297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55542
9967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.555429967
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2688066282
Short name T2685
Test name
Test status
Simulation time 147992922 ps
CPU time 0.73 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 206884 kb
Host smart-37a0eba0-12c3-421a-8de9-2111addaedd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26880
66282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2688066282
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2400434776
Short name T1954
Test name
Test status
Simulation time 239269260 ps
CPU time 0.91 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:50:43 PM PDT 24
Peak memory 206880 kb
Host smart-0f6d7786-8f19-40ad-b49b-a4f60534a582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24004
34776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2400434776
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.4257448633
Short name T1923
Test name
Test status
Simulation time 4059993561 ps
CPU time 109.83 seconds
Started Jul 16 06:50:24 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 207056 kb
Host smart-554ea59c-f544-463b-9706-d916da100ef2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4257448633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.4257448633
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2252832735
Short name T2543
Test name
Test status
Simulation time 165194788 ps
CPU time 0.8 seconds
Started Jul 16 06:50:32 PM PDT 24
Finished Jul 16 06:50:35 PM PDT 24
Peak memory 206844 kb
Host smart-8201671b-a4b7-47f3-89d1-32d80cb64369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22528
32735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2252832735
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.4048040021
Short name T365
Test name
Test status
Simulation time 225604008 ps
CPU time 0.79 seconds
Started Jul 16 06:50:32 PM PDT 24
Finished Jul 16 06:50:33 PM PDT 24
Peak memory 206856 kb
Host smart-05e24cef-d96b-43bd-a737-0f09ac5448df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40480
40021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.4048040021
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2363649244
Short name T2631
Test name
Test status
Simulation time 850968133 ps
CPU time 1.96 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:50:50 PM PDT 24
Peak memory 207056 kb
Host smart-4c45e8fe-fdbe-41c4-b4fa-984ae5668a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23636
49244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2363649244
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.864244178
Short name T1513
Test name
Test status
Simulation time 3811322947 ps
CPU time 27.79 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:51:16 PM PDT 24
Peak memory 207112 kb
Host smart-ea5ee4ee-9cd5-45c4-a732-b997938256a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86424
4178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.864244178
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.882047274
Short name T895
Test name
Test status
Simulation time 67130943 ps
CPU time 0.74 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206840 kb
Host smart-af0aca20-466f-4b08-b31f-10de0b06cf76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=882047274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.882047274
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3700385669
Short name T9
Test name
Test status
Simulation time 3834460168 ps
CPU time 5.19 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:53 PM PDT 24
Peak memory 207084 kb
Host smart-59b09b9f-9903-452d-92a5-2a51ee437df6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3700385669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3700385669
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2109501075
Short name T807
Test name
Test status
Simulation time 13366362203 ps
CPU time 15.42 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:51:00 PM PDT 24
Peak memory 206956 kb
Host smart-fbdfdda5-668f-47e4-a2de-eaa13af36a45
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2109501075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2109501075
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2576720041
Short name T622
Test name
Test status
Simulation time 23385382631 ps
CPU time 23.4 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206952 kb
Host smart-fad1d96a-d87d-4a2d-b82d-3e2ab8959c5a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2576720041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2576720041
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2915823655
Short name T1957
Test name
Test status
Simulation time 149646188 ps
CPU time 0.78 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 206848 kb
Host smart-fe7162f6-8df9-40a2-b475-f74b6fffd1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29158
23655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2915823655
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3061641357
Short name T1052
Test name
Test status
Simulation time 147951395 ps
CPU time 0.78 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 206752 kb
Host smart-9a4c480d-1744-427c-b617-96690761a68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30616
41357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3061641357
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1522239863
Short name T2320
Test name
Test status
Simulation time 536212266 ps
CPU time 1.53 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:50:44 PM PDT 24
Peak memory 206920 kb
Host smart-fe224484-39bc-4725-850b-0e8c7b873bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15222
39863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1522239863
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3842892541
Short name T2666
Test name
Test status
Simulation time 484984590 ps
CPU time 1.27 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206860 kb
Host smart-18b43f98-6fe9-48ec-a8a8-7a731cf8dcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38428
92541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3842892541
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.1644746029
Short name T2381
Test name
Test status
Simulation time 6757531201 ps
CPU time 12.32 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:55 PM PDT 24
Peak memory 207132 kb
Host smart-f9214103-fbe8-4880-9df7-8d3b800c7f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16447
46029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1644746029
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3673548018
Short name T769
Test name
Test status
Simulation time 433909387 ps
CPU time 1.35 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206864 kb
Host smart-adca3f4b-aeb1-4929-9c13-12650d17ca8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36735
48018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3673548018
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1428700270
Short name T2682
Test name
Test status
Simulation time 173309919 ps
CPU time 0.8 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:46 PM PDT 24
Peak memory 206864 kb
Host smart-ff9fbb1b-e3d3-4dd6-a7e4-95ff5e38e6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14287
00270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1428700270
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2668420547
Short name T1293
Test name
Test status
Simulation time 33430104 ps
CPU time 0.62 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:44 PM PDT 24
Peak memory 206880 kb
Host smart-e9b0046c-f9af-4c95-8a42-34e5020717cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26684
20547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2668420547
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2875299861
Short name T2026
Test name
Test status
Simulation time 975273404 ps
CPU time 2.28 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:50 PM PDT 24
Peak memory 207072 kb
Host smart-0f2b5511-4b3a-48e7-bffa-f499d1246e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28752
99861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2875299861
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.551569059
Short name T680
Test name
Test status
Simulation time 191972592 ps
CPU time 2.15 seconds
Started Jul 16 06:50:43 PM PDT 24
Finished Jul 16 06:50:51 PM PDT 24
Peak memory 207024 kb
Host smart-016a3745-8c21-41e0-b11f-8d12ec5a80f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55156
9059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.551569059
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.75856731
Short name T1103
Test name
Test status
Simulation time 199687458 ps
CPU time 0.86 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:44 PM PDT 24
Peak memory 206844 kb
Host smart-4f15c971-63fb-47ee-b133-a56c85e653e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75856
731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.75856731
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1843751872
Short name T362
Test name
Test status
Simulation time 139552213 ps
CPU time 0.74 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 206908 kb
Host smart-969cbda6-901d-46c9-8fa9-c2422a1c13df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18437
51872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1843751872
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1603108152
Short name T2555
Test name
Test status
Simulation time 276418726 ps
CPU time 0.99 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206876 kb
Host smart-57ac78d3-4d44-46cc-838e-55720b21a094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
08152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1603108152
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.3050603555
Short name T94
Test name
Test status
Simulation time 8291956578 ps
CPU time 77.5 seconds
Started Jul 16 06:50:45 PM PDT 24
Finished Jul 16 06:52:07 PM PDT 24
Peak memory 206980 kb
Host smart-94dbe446-4bc6-48f0-a160-7e69b1cc1681
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3050603555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.3050603555
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.3289956876
Short name T83
Test name
Test status
Simulation time 9223237947 ps
CPU time 31.12 seconds
Started Jul 16 06:50:43 PM PDT 24
Finished Jul 16 06:51:20 PM PDT 24
Peak memory 206856 kb
Host smart-a0d48473-6ea7-47d0-b68d-1f8b00b2fcff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32899
56876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3289956876
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.4244716159
Short name T1567
Test name
Test status
Simulation time 210586487 ps
CPU time 0.93 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:44 PM PDT 24
Peak memory 206864 kb
Host smart-1b0c9421-c405-41d0-a661-8fb757992036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42447
16159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.4244716159
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1732581805
Short name T1343
Test name
Test status
Simulation time 23348724522 ps
CPU time 27.38 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206884 kb
Host smart-5096eeb9-d1f2-4832-b720-181d8fe3c1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325
81805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1732581805
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1372004705
Short name T1548
Test name
Test status
Simulation time 3298836207 ps
CPU time 3.96 seconds
Started Jul 16 06:50:38 PM PDT 24
Finished Jul 16 06:50:46 PM PDT 24
Peak memory 206952 kb
Host smart-a650064d-3441-4fe1-b05d-9132f266c296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13720
04705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1372004705
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.445290574
Short name T551
Test name
Test status
Simulation time 10341017082 ps
CPU time 101.67 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 206680 kb
Host smart-2df0db7f-8e44-444e-a7b6-3a9cada78451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44529
0574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.445290574
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.2405368594
Short name T735
Test name
Test status
Simulation time 5633058505 ps
CPU time 158.18 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 207056 kb
Host smart-0a4dd017-ec41-4a92-bbc9-12762a2c48be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2405368594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.2405368594
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1527163434
Short name T1152
Test name
Test status
Simulation time 242991421 ps
CPU time 0.92 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206752 kb
Host smart-1aebc560-9e1b-4763-b046-1f3d830322e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1527163434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1527163434
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1330618641
Short name T806
Test name
Test status
Simulation time 210112424 ps
CPU time 0.85 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206872 kb
Host smart-3c59050d-0209-4ec0-8710-5ae7df0035ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13306
18641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1330618641
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1204658358
Short name T2102
Test name
Test status
Simulation time 6847948551 ps
CPU time 190.72 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:53:55 PM PDT 24
Peak memory 207000 kb
Host smart-6e1ab6a7-eccc-4707-a8e1-67dce38e3d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12046
58358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1204658358
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1654483563
Short name T1915
Test name
Test status
Simulation time 3524698476 ps
CPU time 96 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:52:19 PM PDT 24
Peak memory 207080 kb
Host smart-90f4e7dd-ca0d-4035-9033-0a5105f4dd43
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1654483563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1654483563
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1173541952
Short name T2219
Test name
Test status
Simulation time 199997207 ps
CPU time 0.82 seconds
Started Jul 16 06:50:43 PM PDT 24
Finished Jul 16 06:50:50 PM PDT 24
Peak memory 206888 kb
Host smart-b655872a-b88f-4f87-bf31-843e15692b83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1173541952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1173541952
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.399468182
Short name T1517
Test name
Test status
Simulation time 159211481 ps
CPU time 0.79 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:50:43 PM PDT 24
Peak memory 206888 kb
Host smart-f8bd31c5-4473-4924-bdc6-c8b4fe535b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39946
8182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.399468182
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3801228382
Short name T2316
Test name
Test status
Simulation time 273096305 ps
CPU time 0.95 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 206816 kb
Host smart-d3caa533-7cd3-41d9-9fcb-e88bddd1edcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38012
28382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3801228382
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.599119408
Short name T322
Test name
Test status
Simulation time 224127497 ps
CPU time 0.86 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:50:50 PM PDT 24
Peak memory 206884 kb
Host smart-bd6010c2-a85f-4f4e-b56f-52d8c38d0b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59911
9408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.599119408
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2441227668
Short name T885
Test name
Test status
Simulation time 212092007 ps
CPU time 0.84 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:48 PM PDT 24
Peak memory 206812 kb
Host smart-7fe54d51-9215-4970-b85f-ae3dd751a607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24412
27668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2441227668
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3842919575
Short name T2120
Test name
Test status
Simulation time 189542518 ps
CPU time 0.87 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206860 kb
Host smart-3d85c7c6-cf02-4f15-9234-8dd7c2edee9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38429
19575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3842919575
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.397076355
Short name T1668
Test name
Test status
Simulation time 163370781 ps
CPU time 0.81 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206856 kb
Host smart-618c0f15-d6dd-4214-8d12-cd0a048d7db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39707
6355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.397076355
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.47737188
Short name T646
Test name
Test status
Simulation time 206911261 ps
CPU time 0.92 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:46 PM PDT 24
Peak memory 206860 kb
Host smart-cf60cce1-3cbf-4344-8a3f-3cfe6b4cd790
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=47737188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.47737188
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2438133970
Short name T1242
Test name
Test status
Simulation time 142386280 ps
CPU time 0.74 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:50:43 PM PDT 24
Peak memory 206880 kb
Host smart-1a2c9f83-7bfc-43d6-9ffd-ccc9146edbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24381
33970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2438133970
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1771319364
Short name T888
Test name
Test status
Simulation time 66162241 ps
CPU time 0.71 seconds
Started Jul 16 06:50:37 PM PDT 24
Finished Jul 16 06:50:43 PM PDT 24
Peak memory 206828 kb
Host smart-e2eed1d8-fe51-48b8-8fe2-e422cc255c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17713
19364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1771319364
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.934869615
Short name T241
Test name
Test status
Simulation time 13603155828 ps
CPU time 33.67 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 207104 kb
Host smart-f4edfa24-b9d7-4b0a-9d09-d5a4e9390b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93486
9615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.934869615
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2901032576
Short name T1490
Test name
Test status
Simulation time 226813625 ps
CPU time 0.87 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:46 PM PDT 24
Peak memory 206884 kb
Host smart-fbfd00a8-93ea-43b8-86aa-7fb4d140a96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29010
32576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2901032576
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2848065821
Short name T937
Test name
Test status
Simulation time 237547184 ps
CPU time 0.98 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206764 kb
Host smart-263b4f13-623d-4079-b902-4de81f129199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
65821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2848065821
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1912127156
Short name T879
Test name
Test status
Simulation time 187844115 ps
CPU time 0.84 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206880 kb
Host smart-53181b9c-fb2c-4843-9325-fe7c199e770d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19121
27156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1912127156
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.4135004077
Short name T1204
Test name
Test status
Simulation time 174889206 ps
CPU time 0.81 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206808 kb
Host smart-89864e9b-eb6a-4b70-9ccc-6dd9e799efec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41350
04077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.4135004077
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.91962103
Short name T1460
Test name
Test status
Simulation time 142771425 ps
CPU time 0.78 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206812 kb
Host smart-8fd78da9-1b0b-4ce2-aba5-74c7056d68f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91962
103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.91962103
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.19640984
Short name T2572
Test name
Test status
Simulation time 156481925 ps
CPU time 0.77 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206756 kb
Host smart-b1bf21cd-4da2-4104-9301-04f4792f2fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19640
984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.19640984
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2664871688
Short name T1734
Test name
Test status
Simulation time 152774217 ps
CPU time 0.77 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206384 kb
Host smart-73be7984-53ba-40a6-a454-91fc2f1df08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26648
71688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2664871688
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2120212703
Short name T589
Test name
Test status
Simulation time 243938404 ps
CPU time 0.94 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206764 kb
Host smart-c70e73db-16c2-4954-8025-bcb50c4cee76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21202
12703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2120212703
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1910055117
Short name T1850
Test name
Test status
Simulation time 3942036605 ps
CPU time 40.45 seconds
Started Jul 16 06:50:44 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 207000 kb
Host smart-c2c6d7f5-b60f-4156-9804-37910d6596cb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1910055117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1910055117
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1085254655
Short name T1004
Test name
Test status
Simulation time 164753898 ps
CPU time 0.8 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:48 PM PDT 24
Peak memory 206716 kb
Host smart-8aa91849-26f7-4152-8cbe-5e4bd8690e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10852
54655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1085254655
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3396374331
Short name T1721
Test name
Test status
Simulation time 203882525 ps
CPU time 0.81 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206852 kb
Host smart-fc4dac0b-acf6-4eaf-9c77-bfc379f815c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
74331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3396374331
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.1689487853
Short name T1870
Test name
Test status
Simulation time 639082329 ps
CPU time 1.57 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206840 kb
Host smart-53d88139-dbdd-4ad4-b04e-063c680172c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16894
87853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1689487853
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2027136255
Short name T1201
Test name
Test status
Simulation time 3613104960 ps
CPU time 96.94 seconds
Started Jul 16 06:50:43 PM PDT 24
Finished Jul 16 06:52:26 PM PDT 24
Peak memory 206252 kb
Host smart-f7ddcad3-a1a2-4717-8534-6eccb195b0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20271
36255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2027136255
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1323643781
Short name T1335
Test name
Test status
Simulation time 101356600 ps
CPU time 0.72 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206800 kb
Host smart-aceca0d0-2bb4-4a43-a769-fc09eef0c0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1323643781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1323643781
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3880221791
Short name T10
Test name
Test status
Simulation time 3829551769 ps
CPU time 4.71 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:50:53 PM PDT 24
Peak memory 206948 kb
Host smart-442e258c-a98f-4eed-a532-5cf55e0546c1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3880221791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3880221791
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.415144677
Short name T717
Test name
Test status
Simulation time 13289447989 ps
CPU time 12.75 seconds
Started Jul 16 06:50:40 PM PDT 24
Finished Jul 16 06:50:59 PM PDT 24
Peak memory 207004 kb
Host smart-8080c3b9-2988-4ecc-b416-7031bf5d0438
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=415144677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.415144677
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.4211254886
Short name T1238
Test name
Test status
Simulation time 23302878122 ps
CPU time 24.05 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:51:12 PM PDT 24
Peak memory 206920 kb
Host smart-44de329f-874e-49e4-8604-2e5c14dc115c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4211254886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.4211254886
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1634469817
Short name T1972
Test name
Test status
Simulation time 169150577 ps
CPU time 0.83 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206860 kb
Host smart-cfe6e73c-e466-4197-8ee3-f53d96eef021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16344
69817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1634469817
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.345574336
Short name T2704
Test name
Test status
Simulation time 143372256 ps
CPU time 0.76 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 206736 kb
Host smart-76f913fb-edbf-48e3-b63b-6b9eb24a06a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34557
4336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.345574336
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1557103777
Short name T2499
Test name
Test status
Simulation time 438798981 ps
CPU time 1.49 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:50:50 PM PDT 24
Peak memory 206852 kb
Host smart-669ee9d5-6952-484c-bf60-8d037f00ae7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15571
03777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1557103777
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2399721935
Short name T1540
Test name
Test status
Simulation time 1508828525 ps
CPU time 3.37 seconds
Started Jul 16 06:54:20 PM PDT 24
Finished Jul 16 06:54:25 PM PDT 24
Peak memory 207008 kb
Host smart-98581694-b47f-4b47-8405-326b36f744ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23997
21935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2399721935
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.4258193609
Short name T1969
Test name
Test status
Simulation time 15210076056 ps
CPU time 27.41 seconds
Started Jul 16 06:50:43 PM PDT 24
Finished Jul 16 06:51:16 PM PDT 24
Peak memory 206244 kb
Host smart-3ef19072-bde0-4afb-8913-af94dd3bdf04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42581
93609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.4258193609
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2469330182
Short name T2684
Test name
Test status
Simulation time 332318896 ps
CPU time 1.15 seconds
Started Jul 16 06:50:39 PM PDT 24
Finished Jul 16 06:50:47 PM PDT 24
Peak memory 206908 kb
Host smart-749ad361-0d04-46ce-94bc-a7c47b480af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24693
30182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2469330182
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.291624330
Short name T2436
Test name
Test status
Simulation time 156494839 ps
CPU time 0.78 seconds
Started Jul 16 06:50:41 PM PDT 24
Finished Jul 16 06:50:48 PM PDT 24
Peak memory 206852 kb
Host smart-fb8a50dd-74bb-4521-9f3e-068ce7d4e552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29162
4330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.291624330
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2035755654
Short name T1164
Test name
Test status
Simulation time 48786139 ps
CPU time 0.65 seconds
Started Jul 16 06:50:42 PM PDT 24
Finished Jul 16 06:50:49 PM PDT 24
Peak memory 206880 kb
Host smart-5df8eba2-f587-4915-a918-b6120abbde41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20357
55654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2035755654
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1891186533
Short name T1258
Test name
Test status
Simulation time 808025052 ps
CPU time 1.98 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:50:54 PM PDT 24
Peak memory 207076 kb
Host smart-bce38791-7c24-44b5-902e-e2771af3f030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18911
86533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1891186533
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.761462351
Short name T1081
Test name
Test status
Simulation time 239747177 ps
CPU time 1.47 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:50:53 PM PDT 24
Peak memory 207020 kb
Host smart-c61b4222-b246-4047-b3c9-62b720008dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76146
2351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.761462351
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.739665072
Short name T103
Test name
Test status
Simulation time 197561897 ps
CPU time 0.87 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206808 kb
Host smart-bae12671-5209-4ee1-a1de-cc72405fdb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73966
5072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.739665072
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3674579100
Short name T1352
Test name
Test status
Simulation time 135896069 ps
CPU time 0.74 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206852 kb
Host smart-87781f14-baf6-486a-91fa-a6e064a73697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36745
79100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3674579100
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2833578349
Short name T2403
Test name
Test status
Simulation time 241670215 ps
CPU time 0.9 seconds
Started Jul 16 06:50:55 PM PDT 24
Finished Jul 16 06:51:00 PM PDT 24
Peak memory 206752 kb
Host smart-128cea6c-1af4-47fe-806f-e0a176b03445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28335
78349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2833578349
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.2533358758
Short name T2508
Test name
Test status
Simulation time 7023877961 ps
CPU time 188.66 seconds
Started Jul 16 06:50:54 PM PDT 24
Finished Jul 16 06:54:06 PM PDT 24
Peak memory 206872 kb
Host smart-6818ee9b-3faa-41bb-8652-1ebef94870af
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2533358758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.2533358758
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.770162001
Short name T1633
Test name
Test status
Simulation time 7834796899 ps
CPU time 28.49 seconds
Started Jul 16 06:50:53 PM PDT 24
Finished Jul 16 06:51:26 PM PDT 24
Peak memory 207028 kb
Host smart-70547111-2ada-41d7-a158-3e8e838d8898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77016
2001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.770162001
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.728769456
Short name T2268
Test name
Test status
Simulation time 206804929 ps
CPU time 0.85 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:51:04 PM PDT 24
Peak memory 206832 kb
Host smart-ed7b02b0-cc31-4751-bb0c-f73ae131f1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72876
9456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.728769456
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.448969724
Short name T1774
Test name
Test status
Simulation time 23344947500 ps
CPU time 24.88 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:51:18 PM PDT 24
Peak memory 206904 kb
Host smart-1a4b4e4d-dd78-479a-b008-886c7c54da11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44896
9724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.448969724
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1534750318
Short name T804
Test name
Test status
Simulation time 3284982120 ps
CPU time 3.88 seconds
Started Jul 16 06:50:54 PM PDT 24
Finished Jul 16 06:51:02 PM PDT 24
Peak memory 207088 kb
Host smart-24d22630-08f1-412c-9195-46cdf9f5e8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
50318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1534750318
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.4023000694
Short name T359
Test name
Test status
Simulation time 9457845753 ps
CPU time 66.79 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:52:03 PM PDT 24
Peak memory 207008 kb
Host smart-1973bd7e-00b2-4d9a-ad8e-8518120ee41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
00694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.4023000694
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2894793365
Short name T2170
Test name
Test status
Simulation time 4796244420 ps
CPU time 46.32 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:51:42 PM PDT 24
Peak memory 207012 kb
Host smart-30ad0a29-3e0d-496e-96d9-ef57adc44ca1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2894793365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2894793365
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2509991655
Short name T1922
Test name
Test status
Simulation time 281192918 ps
CPU time 0.94 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206856 kb
Host smart-d5daf92d-c644-4c8c-8472-7ea3cee1467f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2509991655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2509991655
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.338430700
Short name T2073
Test name
Test status
Simulation time 227648141 ps
CPU time 0.87 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:57 PM PDT 24
Peak memory 206748 kb
Host smart-4627c2bb-201e-43d6-b785-41ff48a3a7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33843
0700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.338430700
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.859304942
Short name T1369
Test name
Test status
Simulation time 3903059478 ps
CPU time 31.33 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:51:26 PM PDT 24
Peak memory 207124 kb
Host smart-5c029275-1901-4536-b283-0c1e69ff3746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85930
4942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.859304942
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2953261777
Short name T988
Test name
Test status
Simulation time 3086495529 ps
CPU time 85.2 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:52:22 PM PDT 24
Peak memory 207100 kb
Host smart-86e5e192-8252-448b-9ae0-03ea912d6aaf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2953261777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2953261777
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1889277591
Short name T1829
Test name
Test status
Simulation time 170911417 ps
CPU time 0.84 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:55 PM PDT 24
Peak memory 206776 kb
Host smart-a43ba3d0-9e31-42f4-9338-71f3866c886b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1889277591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1889277591
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3317629916
Short name T451
Test name
Test status
Simulation time 177045587 ps
CPU time 0.81 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:50:53 PM PDT 24
Peak memory 206832 kb
Host smart-785fbc05-d443-43cf-8205-3c91c9a19268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33176
29916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3317629916
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1600282901
Short name T127
Test name
Test status
Simulation time 270353169 ps
CPU time 0.96 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206868 kb
Host smart-fe840e0e-aff0-4c9e-9caa-dcdc276b2e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16002
82901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1600282901
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2665898374
Short name T2492
Test name
Test status
Simulation time 164378755 ps
CPU time 0.85 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:55 PM PDT 24
Peak memory 206908 kb
Host smart-35d78bc4-aac3-4132-b140-6371278c413a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658
98374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2665898374
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.711690301
Short name T2254
Test name
Test status
Simulation time 160044358 ps
CPU time 0.78 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:50:53 PM PDT 24
Peak memory 206848 kb
Host smart-20546632-754c-4f35-864f-2901bc694889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71169
0301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.711690301
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1137736338
Short name T1368
Test name
Test status
Simulation time 157088050 ps
CPU time 0.79 seconds
Started Jul 16 06:50:54 PM PDT 24
Finished Jul 16 06:50:59 PM PDT 24
Peak memory 206648 kb
Host smart-020e58d5-3648-4190-afc9-72176198b346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11377
36338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1137736338
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.508952438
Short name T2721
Test name
Test status
Simulation time 159412537 ps
CPU time 0.74 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206796 kb
Host smart-5d727c79-b174-48eb-ab83-9b2240379133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50895
2438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.508952438
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3163037852
Short name T1074
Test name
Test status
Simulation time 243334376 ps
CPU time 0.93 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 207008 kb
Host smart-d0c7551d-0080-43c1-b909-320d3fee9f94
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3163037852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3163037852
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.972281238
Short name T391
Test name
Test status
Simulation time 149239686 ps
CPU time 0.77 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:58 PM PDT 24
Peak memory 206820 kb
Host smart-b34047fe-acfc-493b-84b6-5a45d8d5fb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97228
1238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.972281238
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3793976692
Short name T555
Test name
Test status
Simulation time 65178623 ps
CPU time 0.68 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:51:04 PM PDT 24
Peak memory 206836 kb
Host smart-473d65d1-1a1a-447e-82bc-8447d652a4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939
76692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3793976692
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2726895025
Short name T2014
Test name
Test status
Simulation time 16601259837 ps
CPU time 39.07 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 207164 kb
Host smart-c5d419b3-2192-4875-ab68-2169c41060a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268
95025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2726895025
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.71548279
Short name T2248
Test name
Test status
Simulation time 226712504 ps
CPU time 0.88 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:58 PM PDT 24
Peak memory 206824 kb
Host smart-a62b711f-96e4-40c4-b27b-176caab2cc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71548
279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.71548279
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.390342987
Short name T1697
Test name
Test status
Simulation time 192904433 ps
CPU time 0.86 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:57 PM PDT 24
Peak memory 206812 kb
Host smart-352ba1cb-abe8-40bd-b037-301915f26c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39034
2987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.390342987
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1455798646
Short name T2654
Test name
Test status
Simulation time 250649932 ps
CPU time 0.94 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:50:54 PM PDT 24
Peak memory 206884 kb
Host smart-6c72c9dd-c882-4c7e-973f-2035fe1a75ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14557
98646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1455798646
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.196077950
Short name T777
Test name
Test status
Simulation time 154524870 ps
CPU time 0.89 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:55 PM PDT 24
Peak memory 206868 kb
Host smart-b2be1f53-69b8-4a28-a0c5-9ab405d67bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19607
7950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.196077950
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1546628077
Short name T47
Test name
Test status
Simulation time 157541258 ps
CPU time 0.85 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:50:54 PM PDT 24
Peak memory 206796 kb
Host smart-5fd03309-d851-4aa1-9cc0-5f7015db60c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15466
28077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1546628077
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2716753067
Short name T1272
Test name
Test status
Simulation time 172181261 ps
CPU time 0.79 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:55 PM PDT 24
Peak memory 206844 kb
Host smart-e76028fa-492e-464b-b6af-e5afbb4480e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
53067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2716753067
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3552781233
Short name T1449
Test name
Test status
Simulation time 159265516 ps
CPU time 0.78 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:58 PM PDT 24
Peak memory 206816 kb
Host smart-1e9cc083-ff45-4d7d-8ea4-e2a89156e5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35527
81233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3552781233
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3581547578
Short name T2755
Test name
Test status
Simulation time 249825853 ps
CPU time 0.98 seconds
Started Jul 16 06:50:49 PM PDT 24
Finished Jul 16 06:50:52 PM PDT 24
Peak memory 206888 kb
Host smart-63a8a893-af82-4483-bb40-4f7b6dbf580f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35815
47578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3581547578
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2220893822
Short name T1552
Test name
Test status
Simulation time 6373721277 ps
CPU time 55.96 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:51:51 PM PDT 24
Peak memory 207144 kb
Host smart-41797767-26bc-4e65-9cd7-325388708685
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2220893822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2220893822
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2154598648
Short name T207
Test name
Test status
Simulation time 148876189 ps
CPU time 0.78 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:54 PM PDT 24
Peak memory 206804 kb
Host smart-a4a71b89-43a6-4b49-a0a9-5ef1483c4d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21545
98648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2154598648
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3601337248
Short name T1538
Test name
Test status
Simulation time 246551280 ps
CPU time 0.95 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:55 PM PDT 24
Peak memory 206808 kb
Host smart-02089044-1d89-4849-b3a2-49c373e81e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36013
37248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3601337248
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.4105530492
Short name T2076
Test name
Test status
Simulation time 316929203 ps
CPU time 1.1 seconds
Started Jul 16 06:50:53 PM PDT 24
Finished Jul 16 06:50:58 PM PDT 24
Peak memory 206880 kb
Host smart-0b27ae72-1439-49d2-87a9-01fb074e9555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41055
30492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.4105530492
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3439212905
Short name T2479
Test name
Test status
Simulation time 7555860600 ps
CPU time 69.23 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:52:06 PM PDT 24
Peak memory 207112 kb
Host smart-c5f1b0c3-fe45-4553-8e07-39b8ef3527ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
12905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3439212905
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3499330663
Short name T675
Test name
Test status
Simulation time 68087979 ps
CPU time 0.68 seconds
Started Jul 16 06:51:06 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206908 kb
Host smart-1912a0c3-1c83-43c5-9edc-07fb64cdc8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3499330663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3499330663
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3509221067
Short name T12
Test name
Test status
Simulation time 4160169648 ps
CPU time 4.79 seconds
Started Jul 16 06:50:53 PM PDT 24
Finished Jul 16 06:51:02 PM PDT 24
Peak memory 206860 kb
Host smart-803ee243-0218-41f1-a2ee-c84e339d6af0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3509221067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3509221067
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4074515600
Short name T1317
Test name
Test status
Simulation time 13337090523 ps
CPU time 14.19 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:51:10 PM PDT 24
Peak memory 206916 kb
Host smart-05f9ae13-dff3-47f9-91b3-dd37d1ed0e11
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4074515600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4074515600
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3753229126
Short name T437
Test name
Test status
Simulation time 23337700761 ps
CPU time 22.14 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:51:18 PM PDT 24
Peak memory 207152 kb
Host smart-784f1e15-bf55-4d79-92e8-2c1f8f2f7fb7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3753229126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3753229126
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1859850529
Short name T1592
Test name
Test status
Simulation time 185912949 ps
CPU time 0.86 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206888 kb
Host smart-bce17c10-0cb7-4bc2-8e4a-eb4a99dd99d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18598
50529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1859850529
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.416363703
Short name T1306
Test name
Test status
Simulation time 167348913 ps
CPU time 0.8 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:50:57 PM PDT 24
Peak memory 206852 kb
Host smart-af3f5d30-5d89-406f-aebb-8538a43be111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41636
3703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.416363703
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.2564440375
Short name T2213
Test name
Test status
Simulation time 346307490 ps
CPU time 1.2 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:55 PM PDT 24
Peak memory 206800 kb
Host smart-c1066ab6-76f5-4430-880b-8f7aeaa7219b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
40375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.2564440375
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2404179011
Short name T97
Test name
Test status
Simulation time 697532724 ps
CPU time 1.63 seconds
Started Jul 16 06:50:53 PM PDT 24
Finished Jul 16 06:50:59 PM PDT 24
Peak memory 207016 kb
Host smart-7b88b3ca-3004-4fd6-a6ad-14ccc9d1479b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
79011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2404179011
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.3837797569
Short name T2202
Test name
Test status
Simulation time 8763805030 ps
CPU time 16.68 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 207076 kb
Host smart-c4387842-ddd8-4a8b-966f-b7a169db335a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38377
97569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.3837797569
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.616675806
Short name T591
Test name
Test status
Simulation time 318199434 ps
CPU time 1.14 seconds
Started Jul 16 06:50:53 PM PDT 24
Finished Jul 16 06:50:58 PM PDT 24
Peak memory 206880 kb
Host smart-de215fe1-6228-49c3-a770-cacc449c0f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61667
5806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.616675806
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2816417750
Short name T1758
Test name
Test status
Simulation time 143340834 ps
CPU time 0.74 seconds
Started Jul 16 06:50:55 PM PDT 24
Finished Jul 16 06:50:59 PM PDT 24
Peak memory 206772 kb
Host smart-7b07887a-c1f0-424e-9b8a-ec3866a01920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28164
17750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2816417750
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1309220606
Short name T683
Test name
Test status
Simulation time 73610063 ps
CPU time 0.7 seconds
Started Jul 16 06:50:50 PM PDT 24
Finished Jul 16 06:50:54 PM PDT 24
Peak memory 206860 kb
Host smart-2dc22d1e-289c-4bb1-bf2e-cf7733f0c36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13092
20606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1309220606
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.415836088
Short name T477
Test name
Test status
Simulation time 926617044 ps
CPU time 2.46 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:57 PM PDT 24
Peak memory 207060 kb
Host smart-71d09b9d-3bdc-4c35-b338-58eb7cc2dccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41583
6088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.415836088
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.396142385
Short name T1947
Test name
Test status
Simulation time 365126587 ps
CPU time 2.19 seconds
Started Jul 16 06:50:51 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 206944 kb
Host smart-0a229097-50f7-4255-947a-7133c375fff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39614
2385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.396142385
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1931917142
Short name T2070
Test name
Test status
Simulation time 265438607 ps
CPU time 0.97 seconds
Started Jul 16 06:50:53 PM PDT 24
Finished Jul 16 06:50:58 PM PDT 24
Peak memory 206880 kb
Host smart-36297bba-e168-45d2-9189-93973298bab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19319
17142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1931917142
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3151718382
Short name T1067
Test name
Test status
Simulation time 137693778 ps
CPU time 0.77 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 206832 kb
Host smart-48e9c73b-436a-449a-bdb9-cf528823d4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31517
18382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3151718382
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.963256143
Short name T2136
Test name
Test status
Simulation time 177723113 ps
CPU time 0.88 seconds
Started Jul 16 06:50:53 PM PDT 24
Finished Jul 16 06:50:58 PM PDT 24
Peak memory 206876 kb
Host smart-4111b719-4b85-4844-add3-e8e1716a86a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96325
6143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.963256143
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.1929502477
Short name T2180
Test name
Test status
Simulation time 5691344615 ps
CPU time 39.3 seconds
Started Jul 16 06:50:52 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 207056 kb
Host smart-c3f25319-e2ad-4c7e-b308-575fb35ad554
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1929502477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.1929502477
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.2970789467
Short name T448
Test name
Test status
Simulation time 3429469089 ps
CPU time 12.92 seconds
Started Jul 16 06:50:53 PM PDT 24
Finished Jul 16 06:51:10 PM PDT 24
Peak memory 207124 kb
Host smart-9fe95d42-bbb6-43cc-9d7c-0debd1f66e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29707
89467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.2970789467
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2061493247
Short name T1557
Test name
Test status
Simulation time 212102925 ps
CPU time 0.98 seconds
Started Jul 16 06:51:03 PM PDT 24
Finished Jul 16 06:51:06 PM PDT 24
Peak memory 206844 kb
Host smart-e70f6609-34ff-41be-aa65-683a29729dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
93247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2061493247
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1800319710
Short name T385
Test name
Test status
Simulation time 23291089379 ps
CPU time 21.03 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:51:24 PM PDT 24
Peak memory 206920 kb
Host smart-aa7a66b5-be60-4836-ba56-6d27b09cb8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18003
19710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1800319710
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2437972686
Short name T2021
Test name
Test status
Simulation time 3272201744 ps
CPU time 3.58 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:12 PM PDT 24
Peak memory 206852 kb
Host smart-d2da270e-88b7-402a-803b-e115ac4f3cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24379
72686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2437972686
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3584375867
Short name T1172
Test name
Test status
Simulation time 8150989194 ps
CPU time 71.99 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:52:15 PM PDT 24
Peak memory 207024 kb
Host smart-1c5e76ee-6960-4e11-acc8-606b281b3f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35843
75867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3584375867
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3793064322
Short name T958
Test name
Test status
Simulation time 7238953074 ps
CPU time 199.59 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:54:24 PM PDT 24
Peak memory 207076 kb
Host smart-408ed00d-0f9e-4d26-8077-2823897a0586
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3793064322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3793064322
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2130193693
Short name T765
Test name
Test status
Simulation time 263976306 ps
CPU time 0.95 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:51:05 PM PDT 24
Peak memory 206872 kb
Host smart-6bcaf5a3-1380-40a9-bd46-172bc8496459
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2130193693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2130193693
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3492160614
Short name T1025
Test name
Test status
Simulation time 202615949 ps
CPU time 0.84 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206820 kb
Host smart-2611fe6b-f3b0-4331-8255-d91bde50a2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34921
60614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3492160614
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3543562305
Short name T2128
Test name
Test status
Simulation time 4852689785 ps
CPU time 130.05 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:53:17 PM PDT 24
Peak memory 207076 kb
Host smart-faaf53a6-1ca5-4c01-b690-267939969be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35435
62305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3543562305
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.61429935
Short name T1357
Test name
Test status
Simulation time 3013543216 ps
CPU time 23.95 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:31 PM PDT 24
Peak memory 207124 kb
Host smart-fb91868b-6162-4edd-ac37-746da517baf7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=61429935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.61429935
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2764274981
Short name T1593
Test name
Test status
Simulation time 157632192 ps
CPU time 0.88 seconds
Started Jul 16 06:51:03 PM PDT 24
Finished Jul 16 06:51:06 PM PDT 24
Peak memory 206736 kb
Host smart-a939e0e9-0311-415f-9cd2-7f68a1b56f85
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2764274981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2764274981
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3235272894
Short name T1685
Test name
Test status
Simulation time 142461748 ps
CPU time 0.79 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:07 PM PDT 24
Peak memory 206812 kb
Host smart-e2da8eda-7bd1-4155-895c-96e49184ee22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32352
72894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3235272894
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2566451384
Short name T2606
Test name
Test status
Simulation time 178031089 ps
CPU time 0.84 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 206856 kb
Host smart-638d0bf5-f262-4526-9ca6-b6dff628f1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25664
51384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2566451384
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.473399137
Short name T1755
Test name
Test status
Simulation time 202310261 ps
CPU time 0.81 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:07 PM PDT 24
Peak memory 206884 kb
Host smart-23d1a28c-85e5-4be4-a223-0e4770e8ee72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47339
9137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.473399137
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1838928187
Short name T2724
Test name
Test status
Simulation time 242039710 ps
CPU time 0.9 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206852 kb
Host smart-2fbed20a-80ef-4a9b-887a-159c1935170c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18389
28187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1838928187
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.923560766
Short name T694
Test name
Test status
Simulation time 159746521 ps
CPU time 0.76 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 206796 kb
Host smart-ba6c7284-5145-482c-afb5-0aa62fa6c475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92356
0766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.923560766
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2314017684
Short name T1271
Test name
Test status
Simulation time 278188272 ps
CPU time 1.03 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206856 kb
Host smart-bec18f3d-0ba4-41b7-b489-203a8180ebae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2314017684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2314017684
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2650856212
Short name T994
Test name
Test status
Simulation time 188912328 ps
CPU time 0.85 seconds
Started Jul 16 06:51:03 PM PDT 24
Finished Jul 16 06:51:05 PM PDT 24
Peak memory 206884 kb
Host smart-3948fcbe-2df3-47f6-9fa9-83dbddf17105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26508
56212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2650856212
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2898284971
Short name T1260
Test name
Test status
Simulation time 70961911 ps
CPU time 0.66 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 206796 kb
Host smart-2f2db175-0106-4b5a-a11c-d837bf43f17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28982
84971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2898284971
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2560422066
Short name T1673
Test name
Test status
Simulation time 22529005361 ps
CPU time 52.31 seconds
Started Jul 16 06:51:06 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 207184 kb
Host smart-27cc22dd-84c0-41c3-a142-4762787170b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25604
22066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2560422066
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.4131835584
Short name T872
Test name
Test status
Simulation time 188991408 ps
CPU time 0.85 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:51:05 PM PDT 24
Peak memory 206756 kb
Host smart-648590df-319c-4eeb-b1ca-74bad1e97fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41318
35584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.4131835584
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2375338018
Short name T1473
Test name
Test status
Simulation time 230627552 ps
CPU time 0.86 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 206796 kb
Host smart-2a86054a-996a-404c-a3c2-0311e3e33602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23753
38018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2375338018
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1538434304
Short name T1311
Test name
Test status
Simulation time 206177007 ps
CPU time 0.91 seconds
Started Jul 16 06:51:03 PM PDT 24
Finished Jul 16 06:51:06 PM PDT 24
Peak memory 206880 kb
Host smart-9d3f584f-8d1f-450b-bddc-db621c067514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384
34304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1538434304
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.237476013
Short name T587
Test name
Test status
Simulation time 195590510 ps
CPU time 0.85 seconds
Started Jul 16 06:51:03 PM PDT 24
Finished Jul 16 06:51:06 PM PDT 24
Peak memory 206868 kb
Host smart-1e001787-32af-4035-a220-be05cbe8dd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23747
6013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.237476013
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.991010396
Short name T1276
Test name
Test status
Simulation time 169029804 ps
CPU time 0.81 seconds
Started Jul 16 06:51:03 PM PDT 24
Finished Jul 16 06:51:05 PM PDT 24
Peak memory 206832 kb
Host smart-e41a474d-a914-44df-ad1f-bb332ed4f81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99101
0396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.991010396
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3389501733
Short name T1722
Test name
Test status
Simulation time 222152114 ps
CPU time 0.84 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 206872 kb
Host smart-df9c770c-b014-4026-9e28-6462478bb129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
01733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3389501733
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1632417851
Short name T827
Test name
Test status
Simulation time 150047155 ps
CPU time 0.78 seconds
Started Jul 16 06:51:07 PM PDT 24
Finished Jul 16 06:51:10 PM PDT 24
Peak memory 206888 kb
Host smart-56c71042-b2b1-48f7-8534-a7bfb5b6fadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16324
17851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1632417851
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3288376925
Short name T1629
Test name
Test status
Simulation time 198513877 ps
CPU time 0.92 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:51:05 PM PDT 24
Peak memory 206852 kb
Host smart-425c283c-a889-40d4-abda-c1c12099891c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32883
76925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3288376925
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3292805224
Short name T941
Test name
Test status
Simulation time 5457803899 ps
CPU time 52.91 seconds
Started Jul 16 06:51:06 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 207084 kb
Host smart-c594a801-f54d-4cb6-af58-fd7f5495c003
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3292805224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3292805224
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2142095643
Short name T2023
Test name
Test status
Simulation time 149716812 ps
CPU time 0.75 seconds
Started Jul 16 06:51:07 PM PDT 24
Finished Jul 16 06:51:11 PM PDT 24
Peak memory 206756 kb
Host smart-bf792413-1d40-4e72-b4a8-e13f42fe4e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21420
95643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2142095643
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1022151308
Short name T2611
Test name
Test status
Simulation time 207222957 ps
CPU time 0.86 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206872 kb
Host smart-e1146270-c9c3-437a-aa74-93205e15866c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10221
51308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1022151308
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.4137003861
Short name T2276
Test name
Test status
Simulation time 369679938 ps
CPU time 1.08 seconds
Started Jul 16 06:51:09 PM PDT 24
Finished Jul 16 06:51:11 PM PDT 24
Peak memory 206820 kb
Host smart-7a066996-c392-44ae-9669-fe981a3b1377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41370
03861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.4137003861
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2165582446
Short name T1571
Test name
Test status
Simulation time 4924158203 ps
CPU time 135.46 seconds
Started Jul 16 06:51:03 PM PDT 24
Finished Jul 16 06:53:21 PM PDT 24
Peak memory 207136 kb
Host smart-fe58ff6f-5db6-4ab2-a212-a4634814c4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
82446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2165582446
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.429310755
Short name T1189
Test name
Test status
Simulation time 74606673 ps
CPU time 0.71 seconds
Started Jul 16 06:51:16 PM PDT 24
Finished Jul 16 06:51:18 PM PDT 24
Peak memory 206944 kb
Host smart-75fa846b-1e6c-4d5d-b385-5dac39f56484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=429310755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.429310755
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2980239430
Short name T2050
Test name
Test status
Simulation time 4239294748 ps
CPU time 5.06 seconds
Started Jul 16 06:51:09 PM PDT 24
Finished Jul 16 06:51:15 PM PDT 24
Peak memory 206796 kb
Host smart-bb485e15-3e08-4c00-abb1-14d5c9f84e4d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2980239430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2980239430
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3674205062
Short name T16
Test name
Test status
Simulation time 13425147242 ps
CPU time 16.44 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206916 kb
Host smart-168ee690-20e6-4bfd-8c72-c9e2ba9e68ce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3674205062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3674205062
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1885640822
Short name T2680
Test name
Test status
Simulation time 23365263945 ps
CPU time 22.22 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:28 PM PDT 24
Peak memory 207072 kb
Host smart-4bb82ea7-4cd7-4887-a5e0-256ff776e2b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1885640822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1885640822
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3548299377
Short name T2647
Test name
Test status
Simulation time 157269758 ps
CPU time 0.78 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:07 PM PDT 24
Peak memory 206880 kb
Host smart-5be05e33-b68b-4397-8dca-57d851da2aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35482
99377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3548299377
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2956131855
Short name T494
Test name
Test status
Simulation time 155948454 ps
CPU time 0.8 seconds
Started Jul 16 06:51:03 PM PDT 24
Finished Jul 16 06:51:06 PM PDT 24
Peak memory 206832 kb
Host smart-31f1acf6-15a4-4de1-931a-10c41f503661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29561
31855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2956131855
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.4112469908
Short name T1056
Test name
Test status
Simulation time 556866858 ps
CPU time 1.6 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 207024 kb
Host smart-5f5ea142-3f48-4b34-ab19-34c003a1c249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41124
69908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.4112469908
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2470280861
Short name T726
Test name
Test status
Simulation time 380840719 ps
CPU time 1.04 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:51:04 PM PDT 24
Peak memory 206804 kb
Host smart-bb3a3504-72f2-4fc8-9f75-8457e9e45b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24702
80861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2470280861
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.280030013
Short name T520
Test name
Test status
Simulation time 9592385361 ps
CPU time 17.35 seconds
Started Jul 16 06:51:07 PM PDT 24
Finished Jul 16 06:51:27 PM PDT 24
Peak memory 207092 kb
Host smart-9f140a28-9a41-4dac-9b1b-39a1187e4612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28003
0013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.280030013
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1683962521
Short name T907
Test name
Test status
Simulation time 488145956 ps
CPU time 1.57 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:10 PM PDT 24
Peak memory 206860 kb
Host smart-266e53bc-27a1-4653-86ab-a6d77fb1edc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16839
62521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1683962521
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1652907827
Short name T576
Test name
Test status
Simulation time 147104023 ps
CPU time 0.74 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206816 kb
Host smart-765f8b0c-3ede-412f-a8bb-60e8d0784428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16529
07827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1652907827
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.4039149174
Short name T2374
Test name
Test status
Simulation time 108950690 ps
CPU time 0.73 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:51:06 PM PDT 24
Peak memory 206856 kb
Host smart-bd805e8f-cc02-4b7f-bbfd-6b1d8a9ade95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40391
49174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.4039149174
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3336443323
Short name T2717
Test name
Test status
Simulation time 813342530 ps
CPU time 2.02 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:10 PM PDT 24
Peak memory 206936 kb
Host smart-6c569abc-6cd1-4dde-8c64-b40c30c50cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
43323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3336443323
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1315134272
Short name T2287
Test name
Test status
Simulation time 210119432 ps
CPU time 1.64 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:10 PM PDT 24
Peak memory 207068 kb
Host smart-2718106d-550d-45a8-a238-444699edec68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13151
34272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1315134272
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3722751915
Short name T1395
Test name
Test status
Simulation time 165755704 ps
CPU time 0.78 seconds
Started Jul 16 06:51:09 PM PDT 24
Finished Jul 16 06:51:11 PM PDT 24
Peak memory 206820 kb
Host smart-8fe85ac7-7076-417e-a3ec-159e3810d7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37227
51915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3722751915
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.620602999
Short name T525
Test name
Test status
Simulation time 164053667 ps
CPU time 0.8 seconds
Started Jul 16 06:51:05 PM PDT 24
Finished Jul 16 06:51:09 PM PDT 24
Peak memory 206808 kb
Host smart-c91d445c-6b19-4340-8b2e-aca18d6ad981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62060
2999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.620602999
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.77742937
Short name T1231
Test name
Test status
Simulation time 226291357 ps
CPU time 0.94 seconds
Started Jul 16 06:51:02 PM PDT 24
Finished Jul 16 06:51:04 PM PDT 24
Peak memory 206892 kb
Host smart-4ad4c33c-7959-4eb4-9ca6-da1c451c5e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77742
937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.77742937
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.105763138
Short name T2612
Test name
Test status
Simulation time 10215330840 ps
CPU time 104.43 seconds
Started Jul 16 06:51:04 PM PDT 24
Finished Jul 16 06:52:51 PM PDT 24
Peak memory 207000 kb
Host smart-61286688-34b9-413d-82d2-b40fe177eea9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=105763138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.105763138
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.3162640839
Short name T485
Test name
Test status
Simulation time 11298811426 ps
CPU time 91.42 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:52:50 PM PDT 24
Peak memory 207092 kb
Host smart-67b83879-434a-459c-8045-3a56b81c47eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31626
40839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3162640839
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1772273606
Short name T1363
Test name
Test status
Simulation time 160313510 ps
CPU time 0.8 seconds
Started Jul 16 06:51:22 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 206836 kb
Host smart-f177d65e-b4a8-4d5a-a3b7-ee07162f52b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17722
73606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1772273606
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.4092375027
Short name T1849
Test name
Test status
Simulation time 23348199501 ps
CPU time 26.79 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 206884 kb
Host smart-23984836-bfd7-4da1-8c03-91b0a3ecb9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40923
75027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.4092375027
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1658569702
Short name T837
Test name
Test status
Simulation time 3331216795 ps
CPU time 3.64 seconds
Started Jul 16 06:51:16 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206896 kb
Host smart-66d3e3e1-0c24-4b73-a4b7-34eaf3e96e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16585
69702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1658569702
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1742042173
Short name T1472
Test name
Test status
Simulation time 9586112089 ps
CPU time 93.51 seconds
Started Jul 16 06:51:16 PM PDT 24
Finished Jul 16 06:52:51 PM PDT 24
Peak memory 207148 kb
Host smart-fc61a634-2446-4be7-9b2f-1e5a23def4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17420
42173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1742042173
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2200235531
Short name T1876
Test name
Test status
Simulation time 3195483928 ps
CPU time 22.13 seconds
Started Jul 16 06:51:15 PM PDT 24
Finished Jul 16 06:51:38 PM PDT 24
Peak memory 207056 kb
Host smart-e25d0558-1640-4b36-9ed4-3b5f752ea562
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2200235531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2200235531
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.271549913
Short name T1415
Test name
Test status
Simulation time 246420093 ps
CPU time 0.92 seconds
Started Jul 16 06:51:15 PM PDT 24
Finished Jul 16 06:51:17 PM PDT 24
Peak memory 206872 kb
Host smart-8d370fc0-5035-44c3-bf2a-1c79d2179f2a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=271549913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.271549913
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3983290503
Short name T490
Test name
Test status
Simulation time 221511603 ps
CPU time 0.88 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:20 PM PDT 24
Peak memory 206812 kb
Host smart-6001adff-d717-4d59-a484-d9a2b1829700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39832
90503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3983290503
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2094234552
Short name T2089
Test name
Test status
Simulation time 4728779651 ps
CPU time 43.24 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:52:05 PM PDT 24
Peak memory 207124 kb
Host smart-1390385e-d5e0-4e66-958d-3f7e7c89c42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20942
34552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2094234552
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.298410819
Short name T2027
Test name
Test status
Simulation time 4516778162 ps
CPU time 121.1 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:53:21 PM PDT 24
Peak memory 207104 kb
Host smart-f5996273-0d46-4ae6-8024-d44ee62a63ea
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=298410819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.298410819
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1487351975
Short name T1916
Test name
Test status
Simulation time 210273567 ps
CPU time 0.85 seconds
Started Jul 16 06:51:21 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 206820 kb
Host smart-c68c87ef-1a1f-4f71-adb8-5ae7cd068ced
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1487351975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1487351975
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2796840397
Short name T1050
Test name
Test status
Simulation time 173352125 ps
CPU time 0.77 seconds
Started Jul 16 06:51:26 PM PDT 24
Finished Jul 16 06:51:28 PM PDT 24
Peak memory 206376 kb
Host smart-fa0ed53e-5474-451b-b578-a3d28d6f1f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968
40397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2796840397
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.979956560
Short name T129
Test name
Test status
Simulation time 226638591 ps
CPU time 0.89 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206888 kb
Host smart-d7dd362f-7e24-4f72-82e6-da78f0c825af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97995
6560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.979956560
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.4200313377
Short name T1799
Test name
Test status
Simulation time 157725649 ps
CPU time 0.79 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:23 PM PDT 24
Peak memory 206892 kb
Host smart-dd33f2c8-1887-4578-85ba-b890394f8d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42003
13377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.4200313377
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2434500665
Short name T2737
Test name
Test status
Simulation time 151252169 ps
CPU time 0.82 seconds
Started Jul 16 06:51:16 PM PDT 24
Finished Jul 16 06:51:18 PM PDT 24
Peak memory 206876 kb
Host smart-7f05d711-7982-4e65-82b4-24a9ce1ab618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24345
00665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2434500665
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2981700357
Short name T1141
Test name
Test status
Simulation time 164060031 ps
CPU time 0.88 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:20 PM PDT 24
Peak memory 206796 kb
Host smart-54aed788-0c49-4d7a-b43c-a69a982a29ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29817
00357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2981700357
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1623262308
Short name T2004
Test name
Test status
Simulation time 167761255 ps
CPU time 0.82 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:23 PM PDT 24
Peak memory 206824 kb
Host smart-816117a2-7b5c-476f-94d3-8a8febc6a36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
62308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1623262308
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3982295583
Short name T2616
Test name
Test status
Simulation time 205838043 ps
CPU time 0.89 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:20 PM PDT 24
Peak memory 206852 kb
Host smart-f65628f8-a3d2-4347-9ef6-c134781c7caa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3982295583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3982295583
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3941460382
Short name T1223
Test name
Test status
Simulation time 206013225 ps
CPU time 0.82 seconds
Started Jul 16 06:51:16 PM PDT 24
Finished Jul 16 06:51:18 PM PDT 24
Peak memory 206856 kb
Host smart-b660bd5d-92f6-4526-a38e-8d0bf48c98a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39414
60382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3941460382
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2769769726
Short name T1138
Test name
Test status
Simulation time 83620725 ps
CPU time 0.68 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:24 PM PDT 24
Peak memory 206856 kb
Host smart-7f5a9267-1b9e-42bf-83f9-f5a8b9e368c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27697
69726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2769769726
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1263770681
Short name T1177
Test name
Test status
Simulation time 18083312789 ps
CPU time 40.87 seconds
Started Jul 16 06:51:16 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 207084 kb
Host smart-c74e590d-7d4e-4737-b71f-80f3ea89545a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12637
70681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1263770681
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3152986145
Short name T1674
Test name
Test status
Simulation time 156496314 ps
CPU time 0.83 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:20 PM PDT 24
Peak memory 206848 kb
Host smart-51d2f94a-2a24-4279-ab7c-06027c8d7680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31529
86145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3152986145
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1391774100
Short name T1955
Test name
Test status
Simulation time 225712466 ps
CPU time 0.86 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:23 PM PDT 24
Peak memory 206860 kb
Host smart-a4d20a6b-8d8d-4e33-bcf1-c43940fbd310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13917
74100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1391774100
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3433911678
Short name T1933
Test name
Test status
Simulation time 196498887 ps
CPU time 0.85 seconds
Started Jul 16 06:51:15 PM PDT 24
Finished Jul 16 06:51:17 PM PDT 24
Peak memory 206908 kb
Host smart-e1f38cd4-4ad8-4f4a-98d9-a90e150680a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34339
11678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3433911678
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2459885387
Short name T672
Test name
Test status
Simulation time 193680675 ps
CPU time 0.86 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:51:21 PM PDT 24
Peak memory 206888 kb
Host smart-1d2208b9-5b5c-47fc-9ae1-a9778e32e820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24598
85387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2459885387
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1962281153
Short name T2739
Test name
Test status
Simulation time 205137643 ps
CPU time 0.89 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:21 PM PDT 24
Peak memory 206868 kb
Host smart-2b334ff5-edba-406e-a335-42b1ecda4356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19622
81153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1962281153
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3583715273
Short name T332
Test name
Test status
Simulation time 142251591 ps
CPU time 0.79 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:19 PM PDT 24
Peak memory 206880 kb
Host smart-ec4016d7-b416-43d7-a5db-fa8128588e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35837
15273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3583715273
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1196224120
Short name T2294
Test name
Test status
Simulation time 149429960 ps
CPU time 0.76 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206880 kb
Host smart-3a796530-ac64-4f08-b9f0-185a3275dd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11962
24120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1196224120
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1591149717
Short name T1405
Test name
Test status
Simulation time 249260712 ps
CPU time 0.99 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:20 PM PDT 24
Peak memory 206880 kb
Host smart-4ef0f4f1-5d8a-4108-bf0f-5a683935b688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15911
49717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1591149717
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2582845247
Short name T921
Test name
Test status
Simulation time 5679421618 ps
CPU time 42.51 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 207056 kb
Host smart-a4ac8398-7e62-417e-ae2f-2e9e9cce9197
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2582845247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2582845247
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.26330312
Short name T1297
Test name
Test status
Simulation time 192861430 ps
CPU time 0.8 seconds
Started Jul 16 06:51:21 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 206816 kb
Host smart-61cb775f-46b1-4fd0-a0d5-b96929a7cc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26330
312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.26330312
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2482584940
Short name T1719
Test name
Test status
Simulation time 209501791 ps
CPU time 0.83 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:24 PM PDT 24
Peak memory 206840 kb
Host smart-88549a47-9794-41b1-a2c0-738fde37e8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24825
84940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2482584940
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.3203939081
Short name T1199
Test name
Test status
Simulation time 561027593 ps
CPU time 1.57 seconds
Started Jul 16 06:51:16 PM PDT 24
Finished Jul 16 06:51:20 PM PDT 24
Peak memory 206872 kb
Host smart-82fc10ac-5353-44a0-93ea-d6d7c30694c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32039
39081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3203939081
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2837892364
Short name T1091
Test name
Test status
Simulation time 4581140407 ps
CPU time 42.93 seconds
Started Jul 16 06:51:21 PM PDT 24
Finished Jul 16 06:52:07 PM PDT 24
Peak memory 207124 kb
Host smart-eefd1ba0-cbef-4f1a-86a2-4cc8c9ace80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28378
92364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2837892364
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.4071387493
Short name T2395
Test name
Test status
Simulation time 52131539 ps
CPU time 0.68 seconds
Started Jul 16 06:47:45 PM PDT 24
Finished Jul 16 06:47:48 PM PDT 24
Peak memory 206924 kb
Host smart-a76e7641-4607-405b-b8c7-9e29ea8f22f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4071387493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.4071387493
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.923610836
Short name T491
Test name
Test status
Simulation time 4119319044 ps
CPU time 4.58 seconds
Started Jul 16 06:47:13 PM PDT 24
Finished Jul 16 06:47:19 PM PDT 24
Peak memory 206956 kb
Host smart-9eaeaf8d-298e-4979-b3d6-4d6fb30555f3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=923610836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.923610836
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.891981506
Short name T2365
Test name
Test status
Simulation time 13366228350 ps
CPU time 12.47 seconds
Started Jul 16 06:47:29 PM PDT 24
Finished Jul 16 06:47:42 PM PDT 24
Peak memory 207140 kb
Host smart-9079ac52-5dc2-4fe5-8807-065a15219fce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=891981506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.891981506
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1200310574
Short name T867
Test name
Test status
Simulation time 23393701162 ps
CPU time 26.24 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:48:01 PM PDT 24
Peak memory 207136 kb
Host smart-38242e49-1b8d-467e-b6b8-e606471a350f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1200310574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1200310574
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2690063169
Short name T533
Test name
Test status
Simulation time 147053701 ps
CPU time 0.79 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:34 PM PDT 24
Peak memory 206816 kb
Host smart-72a2ae46-4160-4c49-abac-0619b71cb62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26900
63169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2690063169
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.4268644467
Short name T50
Test name
Test status
Simulation time 185344194 ps
CPU time 0.83 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206744 kb
Host smart-98ad1bcb-d714-4869-a594-7b4ef7b7a120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42686
44467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.4268644467
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1399010361
Short name T80
Test name
Test status
Simulation time 155162977 ps
CPU time 0.76 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206872 kb
Host smart-454bc7ae-be6f-4f92-9410-11d52344bc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
10361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1399010361
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2432928255
Short name T1412
Test name
Test status
Simulation time 144720804 ps
CPU time 0.77 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:35 PM PDT 24
Peak memory 206836 kb
Host smart-2e5ed0ae-fa56-481d-80ea-03187f8e1f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24329
28255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2432928255
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.804711694
Short name T2222
Test name
Test status
Simulation time 377339363 ps
CPU time 1.26 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:32 PM PDT 24
Peak memory 206876 kb
Host smart-c80cd6a5-12dc-49a9-9ab5-1692e62a9710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80471
1694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.804711694
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.199638381
Short name T390
Test name
Test status
Simulation time 525032384 ps
CPU time 1.57 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206828 kb
Host smart-3dd0d86d-272d-42dd-8572-f21ab30a18f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19963
8381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.199638381
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.50767226
Short name T163
Test name
Test status
Simulation time 12262214275 ps
CPU time 22.34 seconds
Started Jul 16 06:47:34 PM PDT 24
Finished Jul 16 06:47:59 PM PDT 24
Peak memory 206940 kb
Host smart-9d7be2ba-662c-4c8c-83bc-e596c4c4b4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50767
226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.50767226
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2611851335
Short name T1385
Test name
Test status
Simulation time 447584647 ps
CPU time 1.35 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 206860 kb
Host smart-2e08d942-c9fc-4c40-ad5e-b8b37510afd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
51335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2611851335
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3628328124
Short name T1170
Test name
Test status
Simulation time 145533079 ps
CPU time 0.74 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:31 PM PDT 24
Peak memory 206860 kb
Host smart-bedda881-0cec-4ba3-988b-ea3430350ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36283
28124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3628328124
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2993134648
Short name T1963
Test name
Test status
Simulation time 35656675 ps
CPU time 0.68 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206796 kb
Host smart-8ef1d9fd-8aa4-4dee-9eaf-b49cb4d10174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29931
34648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2993134648
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1414056241
Short name T2534
Test name
Test status
Simulation time 856305047 ps
CPU time 1.98 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:34 PM PDT 24
Peak memory 207024 kb
Host smart-38beeeaa-70f8-4218-ae01-16da8169e0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14140
56241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1414056241
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1253341095
Short name T522
Test name
Test status
Simulation time 180954172 ps
CPU time 1.9 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206960 kb
Host smart-8e581d6c-8308-44bd-ac16-93e095c4a27c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12533
41095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1253341095
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.4059888957
Short name T2188
Test name
Test status
Simulation time 89192412167 ps
CPU time 120.29 seconds
Started Jul 16 06:47:29 PM PDT 24
Finished Jul 16 06:49:31 PM PDT 24
Peak memory 207000 kb
Host smart-492b776f-8701-4ad3-b091-b356d6d75852
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4059888957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.4059888957
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.3975355847
Short name T2097
Test name
Test status
Simulation time 105087243877 ps
CPU time 159.19 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:50:11 PM PDT 24
Peak memory 207080 kb
Host smart-d4b3d5c7-62f3-4801-a552-f5b0e2d3bb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975355847 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3975355847
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1128135668
Short name T2679
Test name
Test status
Simulation time 119116366354 ps
CPU time 163.59 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:50:20 PM PDT 24
Peak memory 206860 kb
Host smart-c5a7a017-58f3-4fc2-afc9-ecdbfa393162
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1128135668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1128135668
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1046265504
Short name T1796
Test name
Test status
Simulation time 121181797875 ps
CPU time 159.97 seconds
Started Jul 16 06:47:29 PM PDT 24
Finished Jul 16 06:50:10 PM PDT 24
Peak memory 207096 kb
Host smart-ab886dfb-f49b-4bbd-a4c5-c91b22965e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046265504 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1046265504
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.2131757456
Short name T2740
Test name
Test status
Simulation time 83180313891 ps
CPU time 132.74 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:49:46 PM PDT 24
Peak memory 207064 kb
Host smart-fb5ffc6f-0ef6-49cd-a94b-47eb2aab942f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21317
57456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.2131757456
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3722965112
Short name T1147
Test name
Test status
Simulation time 228202056 ps
CPU time 0.92 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:35 PM PDT 24
Peak memory 206860 kb
Host smart-d142e051-e7b7-468c-817b-1349e251f894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37229
65112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3722965112
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2110616862
Short name T537
Test name
Test status
Simulation time 154300385 ps
CPU time 0.81 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206840 kb
Host smart-90156f2a-b5f5-42cb-8733-3403866ef492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21106
16862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2110616862
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3815702839
Short name T2600
Test name
Test status
Simulation time 169532057 ps
CPU time 0.9 seconds
Started Jul 16 06:47:29 PM PDT 24
Finished Jul 16 06:47:31 PM PDT 24
Peak memory 206776 kb
Host smart-1c47bb1c-7a29-47da-9fd5-3ac6652d84df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38157
02839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3815702839
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.3334702601
Short name T2553
Test name
Test status
Simulation time 6336831211 ps
CPU time 188.3 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:50:44 PM PDT 24
Peak memory 206984 kb
Host smart-605c3a17-7e2b-4e81-83b8-1a665301f8d9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3334702601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.3334702601
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.405388960
Short name T1658
Test name
Test status
Simulation time 156137526 ps
CPU time 0.82 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:33 PM PDT 24
Peak memory 206776 kb
Host smart-6a76fe53-af88-4fc8-b6f7-c1b33f3fe71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40538
8960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.405388960
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.2577206112
Short name T1015
Test name
Test status
Simulation time 23334369750 ps
CPU time 21.97 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:47:57 PM PDT 24
Peak memory 206868 kb
Host smart-524f693c-89c7-46f0-9dc2-e2472a597f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25772
06112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.2577206112
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3205081642
Short name T767
Test name
Test status
Simulation time 3375041455 ps
CPU time 3.55 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206948 kb
Host smart-873472d5-4502-43a1-a1e0-b515f4209469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32050
81642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3205081642
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2703056922
Short name T1417
Test name
Test status
Simulation time 12744734439 ps
CPU time 87.42 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:49:02 PM PDT 24
Peak memory 207132 kb
Host smart-6f4f6d9a-8642-4f54-ab15-a0d55013c175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27030
56922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2703056922
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2675206358
Short name T2747
Test name
Test status
Simulation time 5089117363 ps
CPU time 35.31 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:48:11 PM PDT 24
Peak memory 207012 kb
Host smart-6436f6e7-d552-44b0-bbe9-fb0a785fcc89
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2675206358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2675206358
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.4162703880
Short name T2354
Test name
Test status
Simulation time 240839158 ps
CPU time 0.92 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:33 PM PDT 24
Peak memory 206892 kb
Host smart-0123f894-b452-403c-9c02-f61fcb67744a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4162703880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.4162703880
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1189381361
Short name T644
Test name
Test status
Simulation time 220844205 ps
CPU time 0.91 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 206872 kb
Host smart-dfffa668-43e5-4206-9a01-1b41116a59eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11893
81361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1189381361
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.931107306
Short name T1588
Test name
Test status
Simulation time 5808224448 ps
CPU time 39.94 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:48:16 PM PDT 24
Peak memory 207084 kb
Host smart-8ac86fde-cf2f-409b-af3d-cfe0fe0a65a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93110
7306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.931107306
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3841992608
Short name T1504
Test name
Test status
Simulation time 7492308041 ps
CPU time 213.72 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:51:07 PM PDT 24
Peak memory 207068 kb
Host smart-d413b42c-fce8-48e4-9682-1e75b3be1a5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3841992608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3841992608
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3562810420
Short name T843
Test name
Test status
Simulation time 147452394 ps
CPU time 0.77 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:34 PM PDT 24
Peak memory 206868 kb
Host smart-a8ad312a-a420-486b-b105-65199908c370
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3562810420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3562810420
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1724183628
Short name T2113
Test name
Test status
Simulation time 140831504 ps
CPU time 0.76 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:32 PM PDT 24
Peak memory 206660 kb
Host smart-584dd184-79c2-4692-a201-e354a9864767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
83628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1724183628
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1006068089
Short name T1926
Test name
Test status
Simulation time 187647034 ps
CPU time 0.81 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:35 PM PDT 24
Peak memory 206884 kb
Host smart-8151e757-7a5a-434f-976b-ff268663badd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10060
68089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1006068089
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.4166934149
Short name T1590
Test name
Test status
Simulation time 167792038 ps
CPU time 0.8 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 206856 kb
Host smart-402040e3-f5bd-4f27-85ca-a550541e1971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41669
34149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.4166934149
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.85098014
Short name T1
Test name
Test status
Simulation time 154399987 ps
CPU time 0.73 seconds
Started Jul 16 06:47:30 PM PDT 24
Finished Jul 16 06:47:34 PM PDT 24
Peak memory 206868 kb
Host smart-9035a9d9-fd98-42ba-9f3e-29f26a6b9723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85098
014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.85098014
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.985126227
Short name T1714
Test name
Test status
Simulation time 286948983 ps
CPU time 0.95 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:35 PM PDT 24
Peak memory 206888 kb
Host smart-3ea91932-7d98-4c2f-a4a1-594e7a4fc456
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=985126227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.985126227
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1376053951
Short name T1167
Test name
Test status
Simulation time 245907763 ps
CPU time 0.92 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:34 PM PDT 24
Peak memory 206864 kb
Host smart-93aad701-48fd-44b2-9f50-cd14badcc242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
53951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1376053951
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.600654282
Short name T1831
Test name
Test status
Simulation time 215368775 ps
CPU time 0.82 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 206864 kb
Host smart-10d7f65e-b8fc-4564-aa5e-28b34b338f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60065
4282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.600654282
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2116639069
Short name T950
Test name
Test status
Simulation time 47688733 ps
CPU time 0.67 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 206800 kb
Host smart-5aeb8ce9-42c1-4d6e-ac13-e1ddc0f97e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21166
39069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2116639069
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1948463798
Short name T238
Test name
Test status
Simulation time 14880806094 ps
CPU time 33.33 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:48:09 PM PDT 24
Peak memory 206976 kb
Host smart-15b3f04a-ed57-4c16-9ab4-dd6cd7323f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19484
63798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1948463798
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.814545278
Short name T1950
Test name
Test status
Simulation time 185622583 ps
CPU time 0.87 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 206880 kb
Host smart-01069648-f46b-44de-a4ca-6365955b57f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81454
5278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.814545278
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3037514941
Short name T1313
Test name
Test status
Simulation time 201358748 ps
CPU time 0.89 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 206868 kb
Host smart-cce1e897-68d2-4c22-8157-7bf544eaef5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30375
14941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3037514941
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.866455283
Short name T980
Test name
Test status
Simulation time 11080391973 ps
CPU time 73.11 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:48:49 PM PDT 24
Peak memory 207060 kb
Host smart-6d0c8097-0c22-423d-ab89-927527983184
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=866455283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.866455283
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1037682526
Short name T2292
Test name
Test status
Simulation time 12460352533 ps
CPU time 258.6 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:51:53 PM PDT 24
Peak memory 207180 kb
Host smart-ca002991-4f96-4ce5-ae93-35b772a0e401
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1037682526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1037682526
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.974171494
Short name T562
Test name
Test status
Simulation time 7787871158 ps
CPU time 40.19 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:48:16 PM PDT 24
Peak memory 206848 kb
Host smart-0442ff27-217f-4689-a198-20b25b59cc5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=974171494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.974171494
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.528140312
Short name T1735
Test name
Test status
Simulation time 207837120 ps
CPU time 0.86 seconds
Started Jul 16 06:47:34 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206736 kb
Host smart-57c817e2-c477-42e0-8d55-738f16f44b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52814
0312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.528140312
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2849997249
Short name T1998
Test name
Test status
Simulation time 179788623 ps
CPU time 0.84 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206876 kb
Host smart-0de084a9-a567-4876-8b2b-6231e3848614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28499
97249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2849997249
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3600456435
Short name T2295
Test name
Test status
Simulation time 182332766 ps
CPU time 0.94 seconds
Started Jul 16 06:47:32 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 206864 kb
Host smart-10065e0a-e36d-4520-a80f-c028cb007cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36004
56435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3600456435
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3333057103
Short name T74
Test name
Test status
Simulation time 194540275 ps
CPU time 0.96 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:47:37 PM PDT 24
Peak memory 206864 kb
Host smart-aa74dc3a-d2e8-465f-9853-0e08dfb39526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33330
57103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3333057103
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.730973027
Short name T201
Test name
Test status
Simulation time 613616135 ps
CPU time 1.47 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:50 PM PDT 24
Peak memory 225596 kb
Host smart-22141311-fdc0-4dd4-b522-cdbe454efe39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=730973027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.730973027
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.418945255
Short name T2733
Test name
Test status
Simulation time 311604674 ps
CPU time 1 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:34 PM PDT 24
Peak memory 206860 kb
Host smart-ed8f500e-fa72-4110-bf8c-f3893a4616d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41894
5255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.418945255
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2836173179
Short name T2628
Test name
Test status
Simulation time 149361620 ps
CPU time 0.77 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:34 PM PDT 24
Peak memory 206828 kb
Host smart-3f62f6c6-9461-4f1d-afc4-52f489e05e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
73179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2836173179
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2074201879
Short name T2671
Test name
Test status
Simulation time 198431611 ps
CPU time 0.84 seconds
Started Jul 16 06:47:31 PM PDT 24
Finished Jul 16 06:47:35 PM PDT 24
Peak memory 206872 kb
Host smart-e7a2cd5a-8fd4-45dc-88e7-9408d11dfd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20742
01879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2074201879
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1578897407
Short name T1638
Test name
Test status
Simulation time 266609120 ps
CPU time 0.99 seconds
Started Jul 16 06:47:29 PM PDT 24
Finished Jul 16 06:47:31 PM PDT 24
Peak memory 206800 kb
Host smart-fc75b4a9-0ee5-49cd-8227-b0c7fdfd090e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15788
97407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1578897407
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1463135297
Short name T593
Test name
Test status
Simulation time 5984344530 ps
CPU time 170.84 seconds
Started Jul 16 06:47:33 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 207096 kb
Host smart-dcaacc48-01d4-4023-af34-f8fd7023ee2c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1463135297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1463135297
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.401583838
Short name T2604
Test name
Test status
Simulation time 197962101 ps
CPU time 0.83 seconds
Started Jul 16 06:47:45 PM PDT 24
Finished Jul 16 06:47:47 PM PDT 24
Peak memory 206896 kb
Host smart-594e8d17-0c2c-4410-a342-6b82e2ec0043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40158
3838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.401583838
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3601612863
Short name T908
Test name
Test status
Simulation time 213540465 ps
CPU time 0.84 seconds
Started Jul 16 06:47:45 PM PDT 24
Finished Jul 16 06:47:48 PM PDT 24
Peak memory 206864 kb
Host smart-b81f6161-eaf0-4844-843a-1a4a4d46335c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36016
12863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3601612863
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.867772802
Short name T18
Test name
Test status
Simulation time 335935469 ps
CPU time 1.18 seconds
Started Jul 16 06:47:44 PM PDT 24
Finished Jul 16 06:47:46 PM PDT 24
Peak memory 206868 kb
Host smart-3e5e7226-c419-44c0-9ffe-c7caf36da90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86777
2802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.867772802
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1425496387
Short name T573
Test name
Test status
Simulation time 7061470174 ps
CPU time 184.27 seconds
Started Jul 16 06:47:45 PM PDT 24
Finished Jul 16 06:50:50 PM PDT 24
Peak memory 207012 kb
Host smart-c093a628-53b7-4939-b201-26a30b19e272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
96387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1425496387
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.906616820
Short name T663
Test name
Test status
Simulation time 40302508 ps
CPU time 0.69 seconds
Started Jul 16 06:51:32 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206924 kb
Host smart-f00a1cd7-0e2c-45f3-a779-fb810affcd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=906616820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.906616820
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1643843797
Short name T1670
Test name
Test status
Simulation time 3839624622 ps
CPU time 4.3 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:28 PM PDT 24
Peak memory 206960 kb
Host smart-4fbe3d76-c5af-4928-9c49-b17f9b3c4316
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1643843797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1643843797
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1830214763
Short name T188
Test name
Test status
Simulation time 13398805270 ps
CPU time 12.27 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206936 kb
Host smart-fc0bce28-237f-4e53-8794-782fc569e41a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1830214763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1830214763
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1872309289
Short name T187
Test name
Test status
Simulation time 23374110129 ps
CPU time 23.83 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206888 kb
Host smart-c4a26acf-f179-4b34-a9c4-876bdfdcb678
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1872309289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1872309289
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1353255594
Short name T953
Test name
Test status
Simulation time 171044011 ps
CPU time 0.81 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206748 kb
Host smart-6f6a6975-f690-47db-94a3-766c34a98440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13532
55594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1353255594
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.479257236
Short name T884
Test name
Test status
Simulation time 181843549 ps
CPU time 0.83 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:23 PM PDT 24
Peak memory 206864 kb
Host smart-36872ceb-6cab-4339-87fe-a0543cb2c840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47925
7236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.479257236
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.288131583
Short name T1471
Test name
Test status
Simulation time 433161754 ps
CPU time 1.48 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206888 kb
Host smart-a8b11909-5874-41ea-950f-7320911205d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28813
1583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.288131583
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2286485976
Short name T353
Test name
Test status
Simulation time 408995030 ps
CPU time 1.22 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206748 kb
Host smart-c657b2e6-f76e-4753-b01d-21545166ecc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22864
85976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2286485976
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2999127001
Short name T1803
Test name
Test status
Simulation time 17371063597 ps
CPU time 32.51 seconds
Started Jul 16 06:51:22 PM PDT 24
Finished Jul 16 06:51:57 PM PDT 24
Peak memory 207048 kb
Host smart-cfcd1eb5-ee89-4419-ac50-ff2630c24016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29991
27001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2999127001
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3321941792
Short name T2610
Test name
Test status
Simulation time 496165717 ps
CPU time 1.44 seconds
Started Jul 16 06:51:21 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 206864 kb
Host smart-55fec770-308d-44c4-bf93-6d824813a47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33219
41792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3321941792
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3209232074
Short name T1046
Test name
Test status
Simulation time 141402124 ps
CPU time 0.74 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:23 PM PDT 24
Peak memory 206868 kb
Host smart-b8be03e5-ef4e-433f-accc-922ade6c2a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32092
32074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3209232074
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.2713310633
Short name T2445
Test name
Test status
Simulation time 69158911 ps
CPU time 0.69 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:24 PM PDT 24
Peak memory 206844 kb
Host smart-2221759f-c201-4a30-bff7-5a59b47bd775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27133
10633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2713310633
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1479357375
Short name T515
Test name
Test status
Simulation time 855993971 ps
CPU time 1.97 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 207016 kb
Host smart-022e9581-8b32-4433-8f06-6f897453fcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14793
57375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1479357375
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.892281476
Short name T172
Test name
Test status
Simulation time 293605484 ps
CPU time 1.95 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:24 PM PDT 24
Peak memory 207020 kb
Host smart-27ccf9e8-fe89-4450-890c-98787823006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89228
1476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.892281476
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3916406008
Short name T1589
Test name
Test status
Simulation time 232633673 ps
CPU time 0.9 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206880 kb
Host smart-6cefa93f-f333-4e93-ae91-6db2aca68c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39164
06008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3916406008
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3517185786
Short name T727
Test name
Test status
Simulation time 163411108 ps
CPU time 0.76 seconds
Started Jul 16 06:51:22 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 206784 kb
Host smart-60cb8fb3-2dfe-4240-a5ac-2bc13a74d580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35171
85786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3517185786
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3782784634
Short name T536
Test name
Test status
Simulation time 264972281 ps
CPU time 0.96 seconds
Started Jul 16 06:51:16 PM PDT 24
Finished Jul 16 06:51:19 PM PDT 24
Peak memory 206888 kb
Host smart-537a9e09-604b-4a50-8cc1-147f426de15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37827
84634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3782784634
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.4122997109
Short name T2741
Test name
Test status
Simulation time 5767589108 ps
CPU time 38.46 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 207120 kb
Host smart-fa9c98fc-60f8-4f7b-a44d-72fda866e4c8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4122997109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.4122997109
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.295415434
Short name T1720
Test name
Test status
Simulation time 234876054 ps
CPU time 0.87 seconds
Started Jul 16 06:51:22 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 206780 kb
Host smart-e32d9f37-4723-4e07-84d0-870f69192a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29541
5434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.295415434
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1785319987
Short name T1029
Test name
Test status
Simulation time 23284372757 ps
CPU time 26.12 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 206924 kb
Host smart-48a68d6f-1457-4d6c-8fe3-cc619c95b3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
19987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1785319987
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.675873475
Short name T1863
Test name
Test status
Simulation time 3322036586 ps
CPU time 3.7 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:26 PM PDT 24
Peak memory 206928 kb
Host smart-1a22cba8-b56a-42b6-b4f7-82c1b90de7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67587
3475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.675873475
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.1134029477
Short name T419
Test name
Test status
Simulation time 3920456096 ps
CPU time 101.95 seconds
Started Jul 16 06:51:21 PM PDT 24
Finished Jul 16 06:53:06 PM PDT 24
Peak memory 207020 kb
Host smart-f7c85b62-000a-42ca-9366-962acf0b133f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1134029477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1134029477
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2579587106
Short name T1492
Test name
Test status
Simulation time 258249298 ps
CPU time 0.92 seconds
Started Jul 16 06:51:24 PM PDT 24
Finished Jul 16 06:51:26 PM PDT 24
Peak memory 206832 kb
Host smart-e321b1eb-b55f-40d4-824a-69387eaa2c91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2579587106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2579587106
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1653665591
Short name T326
Test name
Test status
Simulation time 229287525 ps
CPU time 0.92 seconds
Started Jul 16 06:51:17 PM PDT 24
Finished Jul 16 06:51:20 PM PDT 24
Peak memory 206752 kb
Host smart-e3113bf1-7eda-4e57-b412-5a2385b651f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16536
65591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1653665591
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.1895593181
Short name T662
Test name
Test status
Simulation time 4288979863 ps
CPU time 117.34 seconds
Started Jul 16 06:51:23 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 206996 kb
Host smart-9c781fa2-d12a-4f8c-8192-a452491dff0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18955
93181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.1895593181
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1378962230
Short name T920
Test name
Test status
Simulation time 7134549495 ps
CPU time 48.56 seconds
Started Jul 16 06:51:26 PM PDT 24
Finished Jul 16 06:52:16 PM PDT 24
Peak memory 206748 kb
Host smart-3b38c9d5-7760-4c5d-963f-9e53da2d8f85
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1378962230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1378962230
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3526377504
Short name T1775
Test name
Test status
Simulation time 151683354 ps
CPU time 0.77 seconds
Started Jul 16 06:51:21 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 206896 kb
Host smart-07c07119-ba4e-4ccd-8a4e-1068c8a24d3f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3526377504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3526377504
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.247774079
Short name T861
Test name
Test status
Simulation time 152359274 ps
CPU time 0.76 seconds
Started Jul 16 06:51:23 PM PDT 24
Finished Jul 16 06:51:26 PM PDT 24
Peak memory 206796 kb
Host smart-9fc2c3b3-8c16-4706-bf3d-a531569b75e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24777
4079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.247774079
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1486022147
Short name T2713
Test name
Test status
Simulation time 248852608 ps
CPU time 0.94 seconds
Started Jul 16 06:51:19 PM PDT 24
Finished Jul 16 06:51:23 PM PDT 24
Peak memory 206888 kb
Host smart-8d9a9526-c6a6-475c-8c9c-9bcfa6f7c447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14860
22147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1486022147
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4146604301
Short name T2227
Test name
Test status
Simulation time 167903922 ps
CPU time 0.85 seconds
Started Jul 16 06:51:24 PM PDT 24
Finished Jul 16 06:51:26 PM PDT 24
Peak memory 206828 kb
Host smart-44219f0a-e193-48b0-86b7-14b699bc63f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41466
04301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4146604301
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2328084494
Short name T1502
Test name
Test status
Simulation time 159420459 ps
CPU time 0.79 seconds
Started Jul 16 06:51:26 PM PDT 24
Finished Jul 16 06:51:28 PM PDT 24
Peak memory 206848 kb
Host smart-f4de8ee8-75d7-48ea-9dac-c6c293ce83db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23280
84494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2328084494
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1950376624
Short name T418
Test name
Test status
Simulation time 165114572 ps
CPU time 0.8 seconds
Started Jul 16 06:51:26 PM PDT 24
Finished Jul 16 06:51:28 PM PDT 24
Peak memory 206796 kb
Host smart-80ffe1a3-41a4-4134-b695-2d46262a8faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503
76624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1950376624
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.4281756461
Short name T944
Test name
Test status
Simulation time 164212867 ps
CPU time 0.77 seconds
Started Jul 16 06:51:20 PM PDT 24
Finished Jul 16 06:51:24 PM PDT 24
Peak memory 206896 kb
Host smart-60fd3a22-ab22-47a1-af8e-ac8a1a91cb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42817
56461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.4281756461
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.133357451
Short name T1934
Test name
Test status
Simulation time 197975726 ps
CPU time 0.85 seconds
Started Jul 16 06:51:21 PM PDT 24
Finished Jul 16 06:51:25 PM PDT 24
Peak memory 206900 kb
Host smart-33b79afb-1164-44dc-97c6-507d004e0a81
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=133357451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.133357451
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3447561147
Short name T1332
Test name
Test status
Simulation time 209162348 ps
CPU time 0.81 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:31 PM PDT 24
Peak memory 206860 kb
Host smart-4ac3c4b5-daa5-449d-9aa5-1304d9fc9602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34475
61147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3447561147
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3541430370
Short name T1225
Test name
Test status
Simulation time 60371206 ps
CPU time 0.69 seconds
Started Jul 16 06:51:24 PM PDT 24
Finished Jul 16 06:51:26 PM PDT 24
Peak memory 206776 kb
Host smart-8b3cf2f9-9813-4c54-bbe2-8b2b8f9cc16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35414
30370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3541430370
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.4131206444
Short name T720
Test name
Test status
Simulation time 6910205671 ps
CPU time 15.43 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:51:36 PM PDT 24
Peak memory 207140 kb
Host smart-c6cdeb98-a38b-4af3-a9d9-2d09e9485e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41312
06444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.4131206444
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1224722927
Short name T824
Test name
Test status
Simulation time 164411309 ps
CPU time 0.82 seconds
Started Jul 16 06:51:18 PM PDT 24
Finished Jul 16 06:51:22 PM PDT 24
Peak memory 206892 kb
Host smart-2c999a0d-f17f-4d7c-89e7-d9b410f22d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12247
22927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1224722927
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.90912014
Short name T2160
Test name
Test status
Simulation time 176623545 ps
CPU time 0.82 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 206880 kb
Host smart-0f53d8ed-100f-421a-9251-84158e213e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90912
014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.90912014
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.1696431893
Short name T1948
Test name
Test status
Simulation time 243862898 ps
CPU time 0.86 seconds
Started Jul 16 06:51:28 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 206820 kb
Host smart-f30571a9-bb9e-44f1-9f53-095fd8eb571c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16964
31893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.1696431893
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.127743735
Short name T2743
Test name
Test status
Simulation time 156743718 ps
CPU time 0.8 seconds
Started Jul 16 06:51:28 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 206868 kb
Host smart-2bb31233-4b9f-459b-a4cd-bd129d33d858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12774
3735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.127743735
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.4264564738
Short name T1243
Test name
Test status
Simulation time 178708818 ps
CPU time 0.81 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206148 kb
Host smart-efd9a5da-f802-46a4-9460-3a4cc8e239c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42645
64738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.4264564738
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1401453693
Short name T2575
Test name
Test status
Simulation time 153584034 ps
CPU time 0.77 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:31 PM PDT 24
Peak memory 206728 kb
Host smart-14269078-32d9-47d0-ba7b-531ec0144776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14014
53693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1401453693
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3647651700
Short name T526
Test name
Test status
Simulation time 149498748 ps
CPU time 0.77 seconds
Started Jul 16 06:51:28 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 206908 kb
Host smart-f03bfbb7-bde4-4e1c-b18d-7dbdb00640a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
51700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3647651700
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.667135154
Short name T1333
Test name
Test status
Simulation time 264211648 ps
CPU time 0.95 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:32 PM PDT 24
Peak memory 206876 kb
Host smart-f629bd03-9cc6-4c6b-a17e-a18f6ccad620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66713
5154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.667135154
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.4199006516
Short name T558
Test name
Test status
Simulation time 4654834727 ps
CPU time 129.95 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:53:42 PM PDT 24
Peak memory 206952 kb
Host smart-4b68ada1-4d50-4650-9f63-44e128bc6f77
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4199006516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.4199006516
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2092161061
Short name T1743
Test name
Test status
Simulation time 161871544 ps
CPU time 0.78 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 206836 kb
Host smart-14945557-243d-492c-94dc-f7de234180b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20921
61061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2092161061
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1608287263
Short name T658
Test name
Test status
Simulation time 206914489 ps
CPU time 0.82 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206884 kb
Host smart-b3e28234-6e73-4a59-a61c-0c2891db13b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16082
87263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1608287263
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.1328928795
Short name T1489
Test name
Test status
Simulation time 981842290 ps
CPU time 2.23 seconds
Started Jul 16 06:51:27 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 207020 kb
Host smart-166cea8c-97e1-472a-8618-18312436c4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13289
28795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.1328928795
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.77414207
Short name T2164
Test name
Test status
Simulation time 5142488488 ps
CPU time 46.36 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 207120 kb
Host smart-8da420e4-b68a-4fe4-a60f-22835602a5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77414
207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.77414207
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.3903477873
Short name T616
Test name
Test status
Simulation time 130981200 ps
CPU time 0.76 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:45 PM PDT 24
Peak memory 206924 kb
Host smart-e16029e1-8b2d-455a-a5e2-31a35050095b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3903477873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.3903477873
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3171835587
Short name T1409
Test name
Test status
Simulation time 4413945816 ps
CPU time 4.87 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:36 PM PDT 24
Peak memory 206944 kb
Host smart-78c08a93-b5b6-4449-ac54-12293b6bb093
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3171835587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3171835587
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3135292278
Short name T1860
Test name
Test status
Simulation time 13325652314 ps
CPU time 12.66 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:44 PM PDT 24
Peak memory 206944 kb
Host smart-08b2fcd1-2836-4fbe-b650-57afd415de31
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3135292278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3135292278
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2964907993
Short name T1302
Test name
Test status
Simulation time 23329166796 ps
CPU time 27.84 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:52:00 PM PDT 24
Peak memory 206816 kb
Host smart-7adb17b3-f18b-4ecf-ba25-5c0f77f48877
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2964907993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2964907993
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.868893574
Short name T504
Test name
Test status
Simulation time 202179003 ps
CPU time 0.83 seconds
Started Jul 16 06:51:35 PM PDT 24
Finished Jul 16 06:51:37 PM PDT 24
Peak memory 206888 kb
Host smart-1cce8b1f-de22-4138-945a-f636f53a9186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86889
3574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.868893574
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2645272708
Short name T2378
Test name
Test status
Simulation time 234299225 ps
CPU time 0.83 seconds
Started Jul 16 06:51:32 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206864 kb
Host smart-d4ccc55f-35a7-4bb3-8d91-91747d850a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26452
72708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2645272708
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.374265980
Short name T945
Test name
Test status
Simulation time 497677847 ps
CPU time 1.37 seconds
Started Jul 16 06:51:35 PM PDT 24
Finished Jul 16 06:51:37 PM PDT 24
Peak memory 206888 kb
Host smart-a6aa9f8b-1709-4aa2-9c00-b62766a92238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37426
5980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.374265980
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2960162878
Short name T1080
Test name
Test status
Simulation time 1188834593 ps
CPU time 2.77 seconds
Started Jul 16 06:51:35 PM PDT 24
Finished Jul 16 06:51:39 PM PDT 24
Peak memory 207064 kb
Host smart-fa76228a-48c3-453c-aece-c73cdcb12cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29601
62878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2960162878
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3768525707
Short name T1927
Test name
Test status
Simulation time 9645365214 ps
CPU time 18.99 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:52 PM PDT 24
Peak memory 207072 kb
Host smart-62b8d676-d6b4-4b1e-a21b-d281b79d6968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37685
25707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3768525707
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3881696766
Short name T1818
Test name
Test status
Simulation time 498029772 ps
CPU time 1.56 seconds
Started Jul 16 06:51:28 PM PDT 24
Finished Jul 16 06:51:31 PM PDT 24
Peak memory 206860 kb
Host smart-938a2fce-737f-40b1-a093-ec98276152ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38816
96766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3881696766
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2225347954
Short name T746
Test name
Test status
Simulation time 144734816 ps
CPU time 0.76 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206876 kb
Host smart-eb223d32-dec3-4e09-abd4-c2766600b59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22253
47954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2225347954
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1430848988
Short name T606
Test name
Test status
Simulation time 35828280 ps
CPU time 0.7 seconds
Started Jul 16 06:51:27 PM PDT 24
Finished Jul 16 06:51:29 PM PDT 24
Peak memory 207024 kb
Host smart-908b3fae-47be-4c41-a181-d481a8e7565e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308
48988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1430848988
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3343875825
Short name T408
Test name
Test status
Simulation time 803404648 ps
CPU time 2.03 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 206860 kb
Host smart-5a653901-0093-4ea0-88f6-beb9cdd8061d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33438
75825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3343875825
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2102060808
Short name T1162
Test name
Test status
Simulation time 395036222 ps
CPU time 2.43 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 207084 kb
Host smart-7e45c4cc-c8d5-4924-9f8a-a830349c858e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21020
60808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2102060808
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1552714257
Short name T706
Test name
Test status
Simulation time 191712430 ps
CPU time 0.84 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206880 kb
Host smart-722de234-d5df-4dfe-9c9e-9115779e5e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15527
14257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1552714257
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3297295013
Short name T2112
Test name
Test status
Simulation time 146123731 ps
CPU time 0.8 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 206840 kb
Host smart-ae1cf8b3-4f4e-411d-a7bf-7614376147e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32972
95013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3297295013
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3880293328
Short name T316
Test name
Test status
Simulation time 249290821 ps
CPU time 0.92 seconds
Started Jul 16 06:51:32 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206860 kb
Host smart-ab23cb9e-1dec-45ea-88a7-f56ad81d1461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802
93328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3880293328
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.364214773
Short name T2178
Test name
Test status
Simulation time 206063337 ps
CPU time 0.91 seconds
Started Jul 16 06:51:32 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206888 kb
Host smart-f5b467d2-745f-447a-8c2d-6d93dc55244e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36421
4773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.364214773
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3383065099
Short name T1545
Test name
Test status
Simulation time 23291244307 ps
CPU time 28.6 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:52:02 PM PDT 24
Peak memory 206816 kb
Host smart-040f36e8-2c18-4698-a04b-1fc6315168fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33830
65099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3383065099
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3144002683
Short name T803
Test name
Test status
Simulation time 3317407267 ps
CPU time 3.95 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206796 kb
Host smart-03e3a46b-bfd9-48b9-9f34-c2542e8a3652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
02683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3144002683
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.62801763
Short name T1600
Test name
Test status
Simulation time 12524138060 ps
CPU time 338.61 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:57:10 PM PDT 24
Peak memory 207084 kb
Host smart-37a7ab9d-8910-4f14-ad31-96e322cbc161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62801
763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.62801763
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.4274340941
Short name T2495
Test name
Test status
Simulation time 3986058702 ps
CPU time 30.37 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:52:02 PM PDT 24
Peak memory 206932 kb
Host smart-3ec436f9-7ddf-4f54-9c1a-3adfd2c8d69b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4274340941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.4274340941
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2483605139
Short name T220
Test name
Test status
Simulation time 285326155 ps
CPU time 0.96 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:34 PM PDT 24
Peak memory 206864 kb
Host smart-509e94ad-e966-47e9-9bfe-f48bb8bf2a21
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2483605139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2483605139
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1094410394
Short name T744
Test name
Test status
Simulation time 195451250 ps
CPU time 0.88 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 206736 kb
Host smart-37848d44-4978-466e-9e17-6a0b386c9575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944
10394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1094410394
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.728485054
Short name T1213
Test name
Test status
Simulation time 5344661495 ps
CPU time 152.19 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:54:06 PM PDT 24
Peak memory 207084 kb
Host smart-20ababd2-3b6c-4bf6-b61d-d9ed1bf58efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72848
5054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.728485054
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3275654841
Short name T5
Test name
Test status
Simulation time 4768376457 ps
CPU time 44.36 seconds
Started Jul 16 06:51:29 PM PDT 24
Finished Jul 16 06:52:16 PM PDT 24
Peak memory 207136 kb
Host smart-c431ecde-38df-43cb-a75e-bb97f6870065
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3275654841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3275654841
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1497278288
Short name T1325
Test name
Test status
Simulation time 162801633 ps
CPU time 0.82 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 206860 kb
Host smart-0735e0c8-e0de-4582-a157-ce8434e32b98
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1497278288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1497278288
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.4280834144
Short name T2370
Test name
Test status
Simulation time 218571680 ps
CPU time 0.81 seconds
Started Jul 16 06:51:35 PM PDT 24
Finished Jul 16 06:51:37 PM PDT 24
Peak memory 206884 kb
Host smart-b68e6a4d-1a0b-4855-815c-9a9382b5b1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42808
34144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.4280834144
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1391848947
Short name T114
Test name
Test status
Simulation time 229302282 ps
CPU time 0.88 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 206872 kb
Host smart-ff481588-bcba-44f7-9406-94224a46831c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13918
48947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1391848947
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.325291874
Short name T433
Test name
Test status
Simulation time 184637345 ps
CPU time 0.86 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:34 PM PDT 24
Peak memory 206836 kb
Host smart-5869f9ba-9d3c-4e05-8074-a5a94f75702d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32529
1874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.325291874
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1668231807
Short name T2255
Test name
Test status
Simulation time 202124508 ps
CPU time 0.83 seconds
Started Jul 16 06:51:35 PM PDT 24
Finished Jul 16 06:51:37 PM PDT 24
Peak memory 206884 kb
Host smart-84c2dd3e-a154-4893-9a31-61873daf175a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16682
31807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1668231807
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1408794516
Short name T1953
Test name
Test status
Simulation time 184276353 ps
CPU time 0.86 seconds
Started Jul 16 06:51:28 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 206884 kb
Host smart-f4d9a896-e865-483b-8092-6f1abaf90601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
94516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1408794516
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.4242739272
Short name T1744
Test name
Test status
Simulation time 160712353 ps
CPU time 0.82 seconds
Started Jul 16 06:51:28 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 206860 kb
Host smart-653a3b28-a334-4031-a412-894b08ffd29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
39272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.4242739272
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.555349545
Short name T739
Test name
Test status
Simulation time 200309161 ps
CPU time 0.85 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206888 kb
Host smart-98b933d5-9e1b-44c6-ac8d-f5340110fadf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=555349545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.555349545
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1281206603
Short name T2480
Test name
Test status
Simulation time 151133298 ps
CPU time 0.77 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206132 kb
Host smart-a944e73c-4f26-41ce-82c3-c890adcbd0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12812
06603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1281206603
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3045187161
Short name T2551
Test name
Test status
Simulation time 18812933825 ps
CPU time 41.11 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 207164 kb
Host smart-d0c1356e-1351-45e7-9da6-642248da1156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451
87161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3045187161
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1969040968
Short name T1410
Test name
Test status
Simulation time 217430655 ps
CPU time 0.86 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:34 PM PDT 24
Peak memory 206884 kb
Host smart-cddb971f-5bc9-4341-96c4-0d5e43279b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19690
40968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1969040968
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3168475230
Short name T470
Test name
Test status
Simulation time 197899240 ps
CPU time 0.89 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:34 PM PDT 24
Peak memory 206848 kb
Host smart-e2db059e-5611-4f9d-a947-72246cd2a482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
75230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3168475230
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.501491114
Short name T301
Test name
Test status
Simulation time 229504805 ps
CPU time 0.94 seconds
Started Jul 16 06:51:30 PM PDT 24
Finished Jul 16 06:51:33 PM PDT 24
Peak memory 206852 kb
Host smart-5e1f610a-c17d-4fd0-a96b-2ada4d574067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50149
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.501491114
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2014179715
Short name T2314
Test name
Test status
Simulation time 148809917 ps
CPU time 0.78 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206844 kb
Host smart-64deb279-1a48-49d4-ac28-56ed9bd55752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20141
79715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2014179715
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1638958053
Short name T2272
Test name
Test status
Simulation time 156997890 ps
CPU time 0.83 seconds
Started Jul 16 06:51:28 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 206868 kb
Host smart-a008dd28-7037-474b-9cf5-f51f7ac4f506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389
58053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1638958053
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2412439649
Short name T568
Test name
Test status
Simulation time 204806042 ps
CPU time 0.85 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 206908 kb
Host smart-920437a6-0bd5-4c6d-b5d3-76f82b16abdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24124
39649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2412439649
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1656802310
Short name T2265
Test name
Test status
Simulation time 163625243 ps
CPU time 0.82 seconds
Started Jul 16 06:51:28 PM PDT 24
Finished Jul 16 06:51:30 PM PDT 24
Peak memory 206872 kb
Host smart-bcc13e40-6d2e-4227-a0da-f41de748c3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16568
02310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1656802310
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1528074146
Short name T2137
Test name
Test status
Simulation time 251610710 ps
CPU time 0.92 seconds
Started Jul 16 06:51:31 PM PDT 24
Finished Jul 16 06:51:34 PM PDT 24
Peak memory 206908 kb
Host smart-0cf57fd5-f349-45d1-b21b-4b5a20e7335c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15280
74146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1528074146
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2326781486
Short name T2668
Test name
Test status
Simulation time 3984138527 ps
CPU time 118.72 seconds
Started Jul 16 06:51:39 PM PDT 24
Finished Jul 16 06:53:39 PM PDT 24
Peak memory 207136 kb
Host smart-9e4a4b40-7a4f-4c19-a09e-22b62e35f0ce
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2326781486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2326781486
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1337700075
Short name T1613
Test name
Test status
Simulation time 180672863 ps
CPU time 0.82 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206752 kb
Host smart-6255ca60-e104-4217-bc3c-88263b11d6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13377
00075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1337700075
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1614784034
Short name T458
Test name
Test status
Simulation time 185053435 ps
CPU time 0.81 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206752 kb
Host smart-0bf2088d-b1c3-4dcc-8619-e529c856318d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16147
84034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1614784034
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.4044760868
Short name T2507
Test name
Test status
Simulation time 1265934964 ps
CPU time 2.6 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 207200 kb
Host smart-552a0c14-cdd4-406e-83bb-7d413e6aef74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40447
60868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.4044760868
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.756562023
Short name T2247
Test name
Test status
Simulation time 4984486958 ps
CPU time 35.33 seconds
Started Jul 16 06:51:39 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 207040 kb
Host smart-3891e19c-5b66-4f90-b60e-da60934f3b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75656
2023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.756562023
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2816044976
Short name T2422
Test name
Test status
Simulation time 37740897 ps
CPU time 0.66 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:49 PM PDT 24
Peak memory 206896 kb
Host smart-e3f3e3cd-2b85-4f21-a1fe-6d1ef29272af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2816044976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2816044976
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1729099559
Short name T412
Test name
Test status
Simulation time 3999070043 ps
CPU time 4.66 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 207060 kb
Host smart-6cadb091-f2de-44d1-bef1-e606d5d6263f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1729099559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1729099559
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.539335398
Short name T651
Test name
Test status
Simulation time 13363875379 ps
CPU time 13.09 seconds
Started Jul 16 06:51:39 PM PDT 24
Finished Jul 16 06:51:53 PM PDT 24
Peak memory 207152 kb
Host smart-93fab9c5-9e71-4c6e-9b48-bca62797d114
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=539335398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.539335398
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1594505728
Short name T216
Test name
Test status
Simulation time 23456560433 ps
CPU time 21.99 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:52:09 PM PDT 24
Peak memory 207024 kb
Host smart-de508c2a-f80b-42f9-afda-2a92083e4df1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1594505728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1594505728
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3570660756
Short name T2209
Test name
Test status
Simulation time 167418503 ps
CPU time 0.83 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:45 PM PDT 24
Peak memory 206884 kb
Host smart-ef115f17-7457-43c9-becb-49a9a717cb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35706
60756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3570660756
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2496791108
Short name T2305
Test name
Test status
Simulation time 167405012 ps
CPU time 0.76 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:43 PM PDT 24
Peak memory 206800 kb
Host smart-15164549-5f87-41e1-896c-d7d2f9149bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24967
91108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2496791108
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2080372818
Short name T56
Test name
Test status
Simulation time 315524983 ps
CPU time 1.15 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:49 PM PDT 24
Peak memory 206840 kb
Host smart-d6c8b0c5-c92a-4ead-af3b-b01649de6bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20803
72818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2080372818
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3607790565
Short name T57
Test name
Test status
Simulation time 1200653042 ps
CPU time 2.68 seconds
Started Jul 16 06:51:39 PM PDT 24
Finished Jul 16 06:51:42 PM PDT 24
Peak memory 207088 kb
Host smart-9a28a3d7-99c5-4802-81c8-566ee5eb0e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36077
90565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3607790565
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3465214171
Short name T863
Test name
Test status
Simulation time 10613049170 ps
CPU time 19.63 seconds
Started Jul 16 06:51:51 PM PDT 24
Finished Jul 16 06:52:11 PM PDT 24
Peak memory 206752 kb
Host smart-3bd8871c-1eae-4ca8-b12c-ae130439c8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34652
14171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3465214171
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2515229066
Short name T1030
Test name
Test status
Simulation time 352062369 ps
CPU time 1.2 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:49 PM PDT 24
Peak memory 206816 kb
Host smart-c526e860-b385-4f82-8d91-a43c21d02096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25152
29066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2515229066
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.324632386
Short name T2239
Test name
Test status
Simulation time 193772849 ps
CPU time 0.77 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 206840 kb
Host smart-be5b11b0-44a1-427f-ae17-a36a3638ca3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463
2386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.324632386
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.707771387
Short name T598
Test name
Test status
Simulation time 37436683 ps
CPU time 0.64 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:44 PM PDT 24
Peak memory 206812 kb
Host smart-8c246997-59bd-4320-9cc9-3b803b485fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70777
1387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.707771387
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.584697864
Short name T648
Test name
Test status
Simulation time 750725099 ps
CPU time 1.87 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:42 PM PDT 24
Peak memory 207016 kb
Host smart-40760572-8045-48a3-9927-0e4fc1474994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58469
7864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.584697864
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1677360676
Short name T2140
Test name
Test status
Simulation time 324098804 ps
CPU time 2.35 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 206936 kb
Host smart-cf96feb3-c31f-4bf5-8d24-dd0dd87571f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16773
60676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1677360676
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1480279372
Short name T104
Test name
Test status
Simulation time 173915841 ps
CPU time 0.8 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206752 kb
Host smart-f78c51be-5590-44e8-9c91-60cdd1568cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14802
79372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1480279372
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.344223680
Short name T577
Test name
Test status
Simulation time 209961740 ps
CPU time 0.86 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:45 PM PDT 24
Peak memory 207020 kb
Host smart-9297c199-fc8c-494c-b77b-23e809c8001d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34422
3680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.344223680
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3135752538
Short name T1397
Test name
Test status
Simulation time 215528141 ps
CPU time 0.88 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:41 PM PDT 24
Peak memory 206888 kb
Host smart-67417bcb-a4a6-41bf-bd95-d15ddd2702a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
52538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3135752538
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.413988143
Short name T750
Test name
Test status
Simulation time 9418025036 ps
CPU time 264.88 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:56:09 PM PDT 24
Peak memory 207064 kb
Host smart-11dcf550-25a8-405d-bab7-cec153c53d18
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=413988143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.413988143
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3456023236
Short name T2725
Test name
Test status
Simulation time 175803929 ps
CPU time 0.85 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206836 kb
Host smart-3bcfc8e5-29a9-44d2-906b-d35cce2358ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560
23236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3456023236
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1199572497
Short name T969
Test name
Test status
Simulation time 23331065279 ps
CPU time 20.79 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:52:07 PM PDT 24
Peak memory 206916 kb
Host smart-c3cb0918-92c5-46fe-8165-a7c9363ed7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11995
72497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1199572497
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1340542610
Short name T973
Test name
Test status
Simulation time 3327294405 ps
CPU time 4.28 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:53 PM PDT 24
Peak memory 206920 kb
Host smart-82e25473-bae6-4b8c-a966-d09dbd3a94b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13405
42610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1340542610
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.4107866272
Short name T1085
Test name
Test status
Simulation time 11432620851 ps
CPU time 78.69 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:53:01 PM PDT 24
Peak memory 207148 kb
Host smart-e212592a-1fa2-48ff-98f4-a2c39b6c6bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41078
66272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.4107866272
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.2554000232
Short name T2460
Test name
Test status
Simulation time 6189823319 ps
CPU time 43.1 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 206948 kb
Host smart-bf2ff959-079b-4f04-9946-cd7ee27f39dd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2554000232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.2554000232
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1595820947
Short name T363
Test name
Test status
Simulation time 268432236 ps
CPU time 0.98 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:45 PM PDT 24
Peak memory 206872 kb
Host smart-5b862218-1f16-4910-ab08-0f3161f376c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1595820947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1595820947
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3571523647
Short name T2473
Test name
Test status
Simulation time 192088450 ps
CPU time 0.86 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:43 PM PDT 24
Peak memory 206732 kb
Host smart-fa792f50-870f-49e5-ac13-4aa9fa30afb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35715
23647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3571523647
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.118738858
Short name T2526
Test name
Test status
Simulation time 5222519748 ps
CPU time 35.97 seconds
Started Jul 16 06:51:39 PM PDT 24
Finished Jul 16 06:52:16 PM PDT 24
Peak memory 206856 kb
Host smart-72042c13-f269-4a18-b8ba-f0ed2dcb304b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11873
8858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.118738858
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3281687130
Short name T628
Test name
Test status
Simulation time 4583965399 ps
CPU time 45 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:52:26 PM PDT 24
Peak memory 207088 kb
Host smart-ae827108-2e6a-4086-9bf4-3926c14100c4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3281687130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3281687130
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.242428400
Short name T529
Test name
Test status
Simulation time 148606127 ps
CPU time 0.78 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:42 PM PDT 24
Peak memory 206888 kb
Host smart-d3f9ab3a-a179-43fe-b185-68d3d7a0ea05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=242428400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.242428400
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.523591343
Short name T2198
Test name
Test status
Simulation time 157820775 ps
CPU time 0.76 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 206748 kb
Host smart-61a312c2-ba1c-4211-8d8f-2e6011896c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52359
1343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.523591343
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1470526230
Short name T113
Test name
Test status
Simulation time 202778564 ps
CPU time 0.87 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:43 PM PDT 24
Peak memory 206732 kb
Host smart-860896ae-ab22-46ab-9545-5c9396eb4948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14705
26230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1470526230
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2890567969
Short name T1939
Test name
Test status
Simulation time 233855252 ps
CPU time 0.88 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:44 PM PDT 24
Peak memory 206884 kb
Host smart-1f180df7-0f4c-489f-b668-d4912dd24bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28905
67969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2890567969
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1861517037
Short name T2176
Test name
Test status
Simulation time 146864019 ps
CPU time 0.78 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:44 PM PDT 24
Peak memory 206864 kb
Host smart-7023c3b2-f655-44f4-864c-25db8757d08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18615
17037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1861517037
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.205483134
Short name T1083
Test name
Test status
Simulation time 184418074 ps
CPU time 0.82 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 206844 kb
Host smart-71496263-b74f-4779-b5c6-b7edb483227e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20548
3134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.205483134
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3293399324
Short name T2332
Test name
Test status
Simulation time 165644697 ps
CPU time 0.82 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206864 kb
Host smart-5f6ff6ad-51dc-4abc-a22a-0b94a9226095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32933
99324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3293399324
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3648006916
Short name T1037
Test name
Test status
Simulation time 217963933 ps
CPU time 0.96 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206792 kb
Host smart-7943c21b-8bd9-49b7-bd77-60bffa4d24a7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3648006916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3648006916
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1233010562
Short name T2433
Test name
Test status
Simulation time 141588388 ps
CPU time 0.78 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 206888 kb
Host smart-8482ee92-4e5b-4ac4-bab0-e998b5be1c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12330
10562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1233010562
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2211243691
Short name T2098
Test name
Test status
Simulation time 37429205 ps
CPU time 0.68 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 206796 kb
Host smart-aeb9e07d-eb56-4df2-a9aa-963370c54264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22112
43691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2211243691
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1567923996
Short name T1707
Test name
Test status
Simulation time 22037130674 ps
CPU time 44.15 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:52:31 PM PDT 24
Peak memory 206992 kb
Host smart-2c46be4c-8f73-405f-bf7a-2261f3fcf366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15679
23996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1567923996
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2848659218
Short name T1465
Test name
Test status
Simulation time 167464076 ps
CPU time 0.81 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 206816 kb
Host smart-60057d04-e075-4073-a891-61e60705a05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
59218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2848659218
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.601769423
Short name T1708
Test name
Test status
Simulation time 239553850 ps
CPU time 0.84 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:45 PM PDT 24
Peak memory 206816 kb
Host smart-a99777cf-4571-4ca0-a88e-dde94d680f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60176
9423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.601769423
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1313552747
Short name T1493
Test name
Test status
Simulation time 166232660 ps
CPU time 0.84 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:44 PM PDT 24
Peak memory 206836 kb
Host smart-5a0dd2da-a68c-4063-b637-4466dfd5103f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13135
52747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1313552747
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3178195836
Short name T1651
Test name
Test status
Simulation time 165130284 ps
CPU time 0.83 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 206896 kb
Host smart-9597e660-f558-4447-a821-63ebc11b1382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31781
95836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3178195836
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.4194861876
Short name T2317
Test name
Test status
Simulation time 169776057 ps
CPU time 0.76 seconds
Started Jul 16 06:51:41 PM PDT 24
Finished Jul 16 06:51:45 PM PDT 24
Peak memory 206872 kb
Host smart-7240aff8-6e30-432d-be3f-e37013ef15f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41948
61876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.4194861876
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2987643030
Short name T2030
Test name
Test status
Simulation time 146924175 ps
CPU time 0.78 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206816 kb
Host smart-d0fca589-ec57-4021-a67b-520265c869a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29876
43030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2987643030
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1519852055
Short name T1101
Test name
Test status
Simulation time 157707586 ps
CPU time 0.8 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206856 kb
Host smart-0b87f0e0-9f0a-4627-9d2f-4d477820d2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15198
52055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1519852055
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.406789713
Short name T2352
Test name
Test status
Simulation time 234439324 ps
CPU time 0.92 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:49 PM PDT 24
Peak memory 206820 kb
Host smart-f14c7bfe-95fc-400a-a4d2-2cbf749e0d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40678
9713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.406789713
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3427452701
Short name T1644
Test name
Test status
Simulation time 4499487908 ps
CPU time 41.41 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:52:26 PM PDT 24
Peak memory 207056 kb
Host smart-ba493b9e-3971-436e-bd8a-7ebf39ee1289
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3427452701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3427452701
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.382069809
Short name T871
Test name
Test status
Simulation time 200574853 ps
CPU time 0.8 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206836 kb
Host smart-1cc82f8e-9d66-41dc-8792-b06a80ed7ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38206
9809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.382069809
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2195900687
Short name T1732
Test name
Test status
Simulation time 182399317 ps
CPU time 0.8 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206844 kb
Host smart-423125c0-4e09-416d-89cd-533a45821092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21959
00687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2195900687
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1668034645
Short name T2470
Test name
Test status
Simulation time 664120851 ps
CPU time 1.63 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206808 kb
Host smart-28c831d7-4644-498b-87b8-34c7cf924712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16680
34645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1668034645
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3637607209
Short name T1711
Test name
Test status
Simulation time 5814348905 ps
CPU time 40.43 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:52:21 PM PDT 24
Peak memory 207132 kb
Host smart-8333470d-b50d-42f3-85b4-5bee8a26a36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36376
07209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3637607209
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1171461366
Short name T711
Test name
Test status
Simulation time 56305419 ps
CPU time 0.7 seconds
Started Jul 16 06:51:59 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 206928 kb
Host smart-8b071f19-9301-46e7-b274-e37bbc13c9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1171461366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1171461366
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3012528310
Short name T2419
Test name
Test status
Simulation time 3752525382 ps
CPU time 4.45 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:52 PM PDT 24
Peak memory 206860 kb
Host smart-df8c1bfe-5d86-450c-9270-6ed6a90b2d46
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3012528310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3012528310
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3811647022
Short name T482
Test name
Test status
Simulation time 23355731499 ps
CPU time 30.18 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 206924 kb
Host smart-b04e6e7c-736c-4315-93c0-539cc20c93f4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3811647022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3811647022
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1241519196
Short name T710
Test name
Test status
Simulation time 222176547 ps
CPU time 0.91 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:42 PM PDT 24
Peak memory 206888 kb
Host smart-07548a56-7c57-420c-999b-818a6dcc9b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12415
19196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1241519196
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.514767261
Short name T2236
Test name
Test status
Simulation time 228302925 ps
CPU time 0.9 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206884 kb
Host smart-e33361e7-7e95-4c3f-b82e-9c2c14f2c293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51476
7261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.514767261
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.708609235
Short name T1738
Test name
Test status
Simulation time 377748429 ps
CPU time 1.29 seconds
Started Jul 16 06:51:40 PM PDT 24
Finished Jul 16 06:51:42 PM PDT 24
Peak memory 206856 kb
Host smart-03db1abd-438b-4ec6-8bce-93bc03b2f57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70860
9235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.708609235
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.4186437156
Short name T781
Test name
Test status
Simulation time 1374318084 ps
CPU time 2.86 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 207024 kb
Host smart-34f3c334-31ef-4073-8a31-9fa4c2ac7f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41864
37156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.4186437156
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2752527198
Short name T2396
Test name
Test status
Simulation time 7930096466 ps
CPU time 15.56 seconds
Started Jul 16 06:51:39 PM PDT 24
Finished Jul 16 06:51:55 PM PDT 24
Peak memory 207048 kb
Host smart-7c21db8b-1c60-495e-aa41-ccf27bac708e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
27198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2752527198
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.669025943
Short name T2625
Test name
Test status
Simulation time 504067643 ps
CPU time 1.45 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 206704 kb
Host smart-077da45d-d5f2-4f6b-a408-105a49cd24a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66902
5943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.669025943
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.950233774
Short name T2329
Test name
Test status
Simulation time 187091499 ps
CPU time 0.84 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206760 kb
Host smart-e4fd428c-51ee-4055-9651-a75d6f95f9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95023
3774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.950233774
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3678186883
Short name T2086
Test name
Test status
Simulation time 61341200 ps
CPU time 0.67 seconds
Started Jul 16 06:51:50 PM PDT 24
Finished Jul 16 06:51:52 PM PDT 24
Peak memory 206668 kb
Host smart-17f4bcd5-36a7-4ec3-9aa2-50615cfb815b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36781
86883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3678186883
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3523924768
Short name T425
Test name
Test status
Simulation time 201559604 ps
CPU time 1.26 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:49 PM PDT 24
Peak memory 206796 kb
Host smart-da334e63-7382-441c-b2d4-1d8c8ec9af65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35239
24768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3523924768
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.585337485
Short name T1441
Test name
Test status
Simulation time 277865800 ps
CPU time 0.89 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206852 kb
Host smart-029ceb2b-7660-4d42-b73b-4c7588858ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58533
7485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.585337485
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1030662516
Short name T1187
Test name
Test status
Simulation time 154476118 ps
CPU time 0.77 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:47 PM PDT 24
Peak memory 206892 kb
Host smart-4655da05-0488-4c4c-9def-eb472c523353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10306
62516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1030662516
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.575808483
Short name T1558
Test name
Test status
Simulation time 221117169 ps
CPU time 0.89 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 206560 kb
Host smart-ebf4f912-d200-4384-891f-3cff15db1898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57580
8483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.575808483
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3181747934
Short name T2186
Test name
Test status
Simulation time 6074558556 ps
CPU time 44.02 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 207100 kb
Host smart-56897904-c9d6-4172-bdda-86910d5c858a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3181747934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3181747934
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.2581812756
Short name T2457
Test name
Test status
Simulation time 4374616074 ps
CPU time 15.19 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:52:02 PM PDT 24
Peak memory 206984 kb
Host smart-6afdb5a0-9f14-479f-80cf-fd4e3ad1833a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25818
12756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.2581812756
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.242951699
Short name T426
Test name
Test status
Simulation time 254265200 ps
CPU time 0.9 seconds
Started Jul 16 06:51:50 PM PDT 24
Finished Jul 16 06:51:52 PM PDT 24
Peak memory 206680 kb
Host smart-996462f1-24ba-4ee7-8f04-1726863fbf9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24295
1699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.242951699
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3447102427
Short name T2324
Test name
Test status
Simulation time 23305930819 ps
CPU time 23.91 seconds
Started Jul 16 06:51:51 PM PDT 24
Finished Jul 16 06:52:16 PM PDT 24
Peak memory 206564 kb
Host smart-9df0abc4-4dbf-42a9-b20f-6da6956b82c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34471
02427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3447102427
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1376849497
Short name T743
Test name
Test status
Simulation time 3288644187 ps
CPU time 3.65 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:52 PM PDT 24
Peak memory 206916 kb
Host smart-28032048-a8eb-4118-a87c-657c2e04e62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13768
49497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1376849497
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1702206378
Short name T1477
Test name
Test status
Simulation time 11948399097 ps
CPU time 86.52 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 207128 kb
Host smart-9233ee44-8c0a-47d2-9933-98fdbece553d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17022
06378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1702206378
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.4098851996
Short name T1550
Test name
Test status
Simulation time 3719492629 ps
CPU time 101.63 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:53:31 PM PDT 24
Peak memory 207044 kb
Host smart-b5c48440-cfc5-457a-af51-ba4a201fee71
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4098851996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.4098851996
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2125795794
Short name T924
Test name
Test status
Simulation time 253499995 ps
CPU time 0.91 seconds
Started Jul 16 06:51:50 PM PDT 24
Finished Jul 16 06:51:52 PM PDT 24
Peak memory 206872 kb
Host smart-e0fa24bf-825f-4d32-af53-8ecb8d517e2b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2125795794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2125795794
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3007152154
Short name T2517
Test name
Test status
Simulation time 187686631 ps
CPU time 0.84 seconds
Started Jul 16 06:51:45 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206852 kb
Host smart-d3634b42-6bb6-4248-a62c-b3db7fbae1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30071
52154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3007152154
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.9033803
Short name T1207
Test name
Test status
Simulation time 5990337098 ps
CPU time 41.82 seconds
Started Jul 16 06:51:50 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 207120 kb
Host smart-66a2bbf3-e29f-4b47-9dc4-a6cf6d615956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90338
03 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.9033803
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3969336790
Short name T671
Test name
Test status
Simulation time 4677519975 ps
CPU time 127.24 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:53:55 PM PDT 24
Peak memory 206952 kb
Host smart-9158b035-acb4-4151-8944-9734fcdd22ef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3969336790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3969336790
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1644466916
Short name T1907
Test name
Test status
Simulation time 160790280 ps
CPU time 0.79 seconds
Started Jul 16 06:51:50 PM PDT 24
Finished Jul 16 06:51:52 PM PDT 24
Peak memory 206872 kb
Host smart-0905014b-60aa-4dc4-af8b-01576653bb12
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1644466916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1644466916
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3856074861
Short name T2486
Test name
Test status
Simulation time 184878837 ps
CPU time 0.87 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:49 PM PDT 24
Peak memory 206840 kb
Host smart-00c1ef75-2576-48a3-8b1e-17a531ca793d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38560
74861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3856074861
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4221584809
Short name T2656
Test name
Test status
Simulation time 206991704 ps
CPU time 0.92 seconds
Started Jul 16 06:51:46 PM PDT 24
Finished Jul 16 06:51:51 PM PDT 24
Peak memory 206776 kb
Host smart-04b8a8d5-4358-408f-bb41-2f79c13528ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42215
84809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4221584809
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3297476525
Short name T2464
Test name
Test status
Simulation time 190964535 ps
CPU time 0.87 seconds
Started Jul 16 06:51:46 PM PDT 24
Finished Jul 16 06:51:50 PM PDT 24
Peak memory 206772 kb
Host smart-c2f53b6d-c24f-4dfc-9ca6-59b1514c8c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32974
76525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3297476525
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3993180093
Short name T2564
Test name
Test status
Simulation time 154311033 ps
CPU time 0.76 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:45 PM PDT 24
Peak memory 206864 kb
Host smart-bf84a954-3279-482c-8b6f-32a616ecf0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39931
80093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3993180093
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.341976144
Short name T40
Test name
Test status
Simulation time 168774486 ps
CPU time 0.79 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:49 PM PDT 24
Peak memory 206888 kb
Host smart-5bd4a19e-7353-42e5-ac45-fc336f2a73a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197
6144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.341976144
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.911273019
Short name T168
Test name
Test status
Simulation time 147038052 ps
CPU time 0.76 seconds
Started Jul 16 06:51:44 PM PDT 24
Finished Jul 16 06:51:49 PM PDT 24
Peak memory 206876 kb
Host smart-f9c8e8aa-81a9-4fdc-ac2a-06b505342434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91127
3019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.911273019
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1446917016
Short name T1316
Test name
Test status
Simulation time 251993514 ps
CPU time 0.95 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 206832 kb
Host smart-ab59d5e2-1816-4958-bb38-876f5218def6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1446917016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1446917016
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1687633307
Short name T2727
Test name
Test status
Simulation time 145467736 ps
CPU time 0.77 seconds
Started Jul 16 06:51:42 PM PDT 24
Finished Jul 16 06:51:46 PM PDT 24
Peak memory 206832 kb
Host smart-64a58a36-2bda-4ad5-9580-d949499f9d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16876
33307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1687633307
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1033878170
Short name T1717
Test name
Test status
Simulation time 40647742 ps
CPU time 0.66 seconds
Started Jul 16 06:51:43 PM PDT 24
Finished Jul 16 06:51:48 PM PDT 24
Peak memory 206860 kb
Host smart-6d830f78-347b-4330-959a-ea05990bf1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338
78170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1033878170
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1149668234
Short name T2168
Test name
Test status
Simulation time 7876556263 ps
CPU time 17.77 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:52:16 PM PDT 24
Peak memory 207048 kb
Host smart-b589e6fd-1b16-4c2e-a57d-81ca5b1fb46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11496
68234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1149668234
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3989378322
Short name T2138
Test name
Test status
Simulation time 176049857 ps
CPU time 0.84 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:58 PM PDT 24
Peak memory 206892 kb
Host smart-90d7e134-c350-4602-bb18-28cc4531345c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39893
78322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3989378322
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3830500296
Short name T612
Test name
Test status
Simulation time 253322706 ps
CPU time 0.92 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:56 PM PDT 24
Peak memory 206888 kb
Host smart-40f3465a-1bb4-4fac-9038-4cb4180c09e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38305
00296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3830500296
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3664774571
Short name T1773
Test name
Test status
Simulation time 219952766 ps
CPU time 0.81 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:55 PM PDT 24
Peak memory 206868 kb
Host smart-0462b511-3c27-4750-8be5-27e0072cf5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36647
74571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3664774571
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2479617235
Short name T2697
Test name
Test status
Simulation time 179439262 ps
CPU time 0.91 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 206840 kb
Host smart-e869c0ac-19e9-43d1-9c1a-3934f9ac9e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24796
17235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2479617235
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2858128507
Short name T2694
Test name
Test status
Simulation time 227999426 ps
CPU time 0.84 seconds
Started Jul 16 06:51:58 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 206852 kb
Host smart-cf8e4f42-ef6c-4a27-a6d9-ba65363535d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28581
28507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2858128507
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2501125981
Short name T461
Test name
Test status
Simulation time 150392835 ps
CPU time 0.76 seconds
Started Jul 16 06:51:52 PM PDT 24
Finished Jul 16 06:51:54 PM PDT 24
Peak memory 206816 kb
Host smart-8bf774e9-6c38-43c3-8838-fb91d29730fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25011
25981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2501125981
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.390756171
Short name T2286
Test name
Test status
Simulation time 145593645 ps
CPU time 0.79 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:57 PM PDT 24
Peak memory 206856 kb
Host smart-a23a5661-3a69-4daa-b8cf-e3830ee6ff59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39075
6171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.390756171
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.388705458
Short name T774
Test name
Test status
Simulation time 262753104 ps
CPU time 0.95 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:56 PM PDT 24
Peak memory 206880 kb
Host smart-271865ba-80a4-430f-bf6d-2079848dfe46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38870
5458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.388705458
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.645390235
Short name T561
Test name
Test status
Simulation time 4079028149 ps
CPU time 29.48 seconds
Started Jul 16 06:51:57 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 207116 kb
Host smart-824b17ec-249e-4f29-8b17-570788e1b6a1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=645390235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.645390235
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2006049108
Short name T698
Test name
Test status
Simulation time 180523577 ps
CPU time 0.83 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:56 PM PDT 24
Peak memory 206736 kb
Host smart-8ada927b-5cb5-4238-8547-51340aee22a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20060
49108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2006049108
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1017114015
Short name T1973
Test name
Test status
Simulation time 194245684 ps
CPU time 0.85 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:57 PM PDT 24
Peak memory 206908 kb
Host smart-9536b027-a08c-44aa-8f1f-8296ea375958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10171
14015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1017114015
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2005595336
Short name T721
Test name
Test status
Simulation time 661317559 ps
CPU time 1.53 seconds
Started Jul 16 06:51:52 PM PDT 24
Finished Jul 16 06:51:55 PM PDT 24
Peak memory 206864 kb
Host smart-53b460fb-1dec-4544-ae99-392036cb34ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20055
95336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2005595336
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2763629363
Short name T2267
Test name
Test status
Simulation time 7986453229 ps
CPU time 79.11 seconds
Started Jul 16 06:51:58 PM PDT 24
Finished Jul 16 06:53:19 PM PDT 24
Peak memory 207120 kb
Host smart-0c671725-e5eb-43cc-b7b3-3abbdbc69271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
29363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2763629363
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2179103161
Short name T2234
Test name
Test status
Simulation time 42624221 ps
CPU time 0.63 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:57 PM PDT 24
Peak memory 207036 kb
Host smart-56a72bea-ceed-47ac-916d-cee241cd3021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2179103161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2179103161
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.4128513754
Short name T179
Test name
Test status
Simulation time 3669062818 ps
CPU time 5.31 seconds
Started Jul 16 06:51:55 PM PDT 24
Finished Jul 16 06:52:03 PM PDT 24
Peak memory 207088 kb
Host smart-5fdf4b4b-6a9c-4e3e-83e9-05ca5273543a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4128513754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.4128513754
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1524343728
Short name T2364
Test name
Test status
Simulation time 13370236812 ps
CPU time 14 seconds
Started Jul 16 06:51:55 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 207152 kb
Host smart-c37a632e-f6b3-4e3c-8fa5-b0f7bf3bb322
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1524343728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1524343728
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3977048330
Short name T1577
Test name
Test status
Simulation time 23328216046 ps
CPU time 23.62 seconds
Started Jul 16 06:52:04 PM PDT 24
Finished Jul 16 06:52:29 PM PDT 24
Peak memory 206884 kb
Host smart-0141671b-2f30-46f4-b823-4aeb3360af73
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3977048330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.3977048330
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2967182259
Short name T1076
Test name
Test status
Simulation time 151154946 ps
CPU time 0.8 seconds
Started Jul 16 06:51:52 PM PDT 24
Finished Jul 16 06:51:54 PM PDT 24
Peak memory 206872 kb
Host smart-368a558f-6bf1-4f3a-9026-6e8a1f6fed73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29671
82259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2967182259
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3149453765
Short name T1607
Test name
Test status
Simulation time 184946811 ps
CPU time 0.8 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:57 PM PDT 24
Peak memory 206868 kb
Host smart-ba551377-1d07-4594-9771-1e87020f9374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31494
53765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3149453765
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.401216890
Short name T460
Test name
Test status
Simulation time 453163356 ps
CPU time 1.33 seconds
Started Jul 16 06:51:52 PM PDT 24
Finished Jul 16 06:51:54 PM PDT 24
Peak memory 206824 kb
Host smart-1f865a1e-988f-4015-aebc-b5736e56844f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
6890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.401216890
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.65254691
Short name T100
Test name
Test status
Simulation time 1139219298 ps
CPU time 2.4 seconds
Started Jul 16 06:51:51 PM PDT 24
Finished Jul 16 06:51:54 PM PDT 24
Peak memory 207016 kb
Host smart-71c35b7b-fb5a-4462-a0e4-96c7b59f386b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65254
691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.65254691
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.1451412694
Short name T1351
Test name
Test status
Simulation time 12061047413 ps
CPU time 21.87 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 207084 kb
Host smart-68fe149d-c756-42c5-a0dd-3cb884d74457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14514
12694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.1451412694
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3988417218
Short name T2613
Test name
Test status
Simulation time 405247241 ps
CPU time 1.46 seconds
Started Jul 16 06:51:58 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 206844 kb
Host smart-9519a7a1-0de0-4073-9b88-52abd8f8ba12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39884
17218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3988417218
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2296637066
Short name T1430
Test name
Test status
Simulation time 190410939 ps
CPU time 0.82 seconds
Started Jul 16 06:51:59 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 206840 kb
Host smart-482397b2-18be-4298-8756-8e496bbcb0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22966
37066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2296637066
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.3594847531
Short name T2583
Test name
Test status
Simulation time 56442760 ps
CPU time 0.66 seconds
Started Jul 16 06:51:57 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 206848 kb
Host smart-cbe6e811-2779-4379-889c-9e6f1584373c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35948
47531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3594847531
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.304445917
Short name T2122
Test name
Test status
Simulation time 928183974 ps
CPU time 2.22 seconds
Started Jul 16 06:52:04 PM PDT 24
Finished Jul 16 06:52:07 PM PDT 24
Peak memory 206900 kb
Host smart-aaefe7eb-b0aa-4c36-96b5-22c237b94df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30444
5917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.304445917
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.489799228
Short name T704
Test name
Test status
Simulation time 355659023 ps
CPU time 2.15 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:57 PM PDT 24
Peak memory 207220 kb
Host smart-28ae4240-5a69-4721-95d3-346da75922b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48979
9228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.489799228
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3736027954
Short name T1227
Test name
Test status
Simulation time 174773591 ps
CPU time 0.81 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:57 PM PDT 24
Peak memory 206860 kb
Host smart-b51caace-f2e9-4137-99a1-f5d86ba7022a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37360
27954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3736027954
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.7778418
Short name T2678
Test name
Test status
Simulation time 148539578 ps
CPU time 0.78 seconds
Started Jul 16 06:52:04 PM PDT 24
Finished Jul 16 06:52:06 PM PDT 24
Peak memory 206768 kb
Host smart-cd8c7ccd-2767-43df-b3cc-ed21f8b2659a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77784
18 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.7778418
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.901773204
Short name T1425
Test name
Test status
Simulation time 214899237 ps
CPU time 0.91 seconds
Started Jul 16 06:52:04 PM PDT 24
Finished Jul 16 06:52:05 PM PDT 24
Peak memory 206772 kb
Host smart-4b77f64c-d642-4046-8a9f-152b2e4c0bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90177
3204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.901773204
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.364806013
Short name T2172
Test name
Test status
Simulation time 5556567987 ps
CPU time 52.06 seconds
Started Jul 16 06:51:59 PM PDT 24
Finished Jul 16 06:52:52 PM PDT 24
Peak memory 207032 kb
Host smart-1bed9720-1c10-4c12-a07f-a9f39597c4b7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=364806013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.364806013
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.372235889
Short name T2646
Test name
Test status
Simulation time 3504846114 ps
CPU time 30.69 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:52:27 PM PDT 24
Peak memory 207108 kb
Host smart-d4b7f69a-81bf-4d0c-8ab0-f6471f2e8c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37223
5889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.372235889
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.490941083
Short name T2735
Test name
Test status
Simulation time 217072477 ps
CPU time 0.89 seconds
Started Jul 16 06:51:55 PM PDT 24
Finished Jul 16 06:51:58 PM PDT 24
Peak memory 206816 kb
Host smart-7a494613-cffe-4a73-ab36-a0dc26af5fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49094
1083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.490941083
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.2350639482
Short name T516
Test name
Test status
Simulation time 23324718841 ps
CPU time 21.56 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:52:20 PM PDT 24
Peak memory 206940 kb
Host smart-0db781db-a62f-4897-8eb0-ecd8c2cfe833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23506
39482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.2350639482
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2191415806
Short name T866
Test name
Test status
Simulation time 3325325303 ps
CPU time 3.67 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 206948 kb
Host smart-640144c7-ab36-4884-adb8-983a3f44f7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21914
15806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2191415806
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2186775984
Short name T139
Test name
Test status
Simulation time 9782304285 ps
CPU time 274.74 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:56:31 PM PDT 24
Peak memory 207116 kb
Host smart-c167cb88-7233-49e1-9d19-4b253ccf7392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
75984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2186775984
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.774339109
Short name T2146
Test name
Test status
Simulation time 6480461879 ps
CPU time 186.01 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:55:04 PM PDT 24
Peak memory 206996 kb
Host smart-c3746374-de48-491c-a60c-77af4e8eb748
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=774339109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.774339109
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1134819451
Short name T1822
Test name
Test status
Simulation time 280575177 ps
CPU time 0.93 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 206876 kb
Host smart-4d74706e-fce0-441f-8b06-0d2cf1e0e7e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1134819451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1134819451
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.450033064
Short name T1285
Test name
Test status
Simulation time 215734607 ps
CPU time 0.91 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:56 PM PDT 24
Peak memory 206732 kb
Host smart-692774d3-62fa-4a83-8515-4e516ee58e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45003
3064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.450033064
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.123591064
Short name T1098
Test name
Test status
Simulation time 5518617219 ps
CPU time 148.95 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:54:27 PM PDT 24
Peak memory 206984 kb
Host smart-63af58e0-b57d-4cc5-8aa3-4d04d347db3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12359
1064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.123591064
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1706334435
Short name T1323
Test name
Test status
Simulation time 6143863498 ps
CPU time 45.32 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 207128 kb
Host smart-1cd29121-af3a-4034-8c5e-98335fa20bcc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1706334435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1706334435
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3017715825
Short name T1783
Test name
Test status
Simulation time 159767176 ps
CPU time 0.78 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:56 PM PDT 24
Peak memory 206888 kb
Host smart-fede0d0e-d5b2-4131-9b51-8c7e47b172e0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3017715825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3017715825
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2456793109
Short name T2082
Test name
Test status
Simulation time 185841150 ps
CPU time 0.78 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:58 PM PDT 24
Peak memory 206664 kb
Host smart-d48b7e0f-6336-4681-9a86-d79dd3acf3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24567
93109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2456793109
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2722162782
Short name T889
Test name
Test status
Simulation time 169798958 ps
CPU time 0.82 seconds
Started Jul 16 06:51:55 PM PDT 24
Finished Jul 16 06:51:58 PM PDT 24
Peak memory 206884 kb
Host smart-8d66a96c-36e7-4b62-9aaa-a6c9fe46f019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27221
62782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2722162782
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1445550916
Short name T315
Test name
Test status
Simulation time 225205286 ps
CPU time 0.79 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:55 PM PDT 24
Peak memory 206856 kb
Host smart-f60cb849-cc9a-4d2a-ae2c-1900d35d9d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14455
50916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1445550916
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1453547218
Short name T441
Test name
Test status
Simulation time 151802706 ps
CPU time 0.8 seconds
Started Jul 16 06:51:55 PM PDT 24
Finished Jul 16 06:51:58 PM PDT 24
Peak memory 206860 kb
Host smart-54cc91e4-c9fc-4a2d-935e-704483ef751f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14535
47218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1453547218
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1412867915
Short name T782
Test name
Test status
Simulation time 152833915 ps
CPU time 0.79 seconds
Started Jul 16 06:51:59 PM PDT 24
Finished Jul 16 06:52:01 PM PDT 24
Peak memory 206880 kb
Host smart-2b5a4bac-b5b4-477c-b21d-7ca59c661f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14128
67915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1412867915
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.2523128010
Short name T1145
Test name
Test status
Simulation time 183934622 ps
CPU time 0.99 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 206876 kb
Host smart-b6405492-8908-4955-8eee-33935df7d13d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2523128010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.2523128010
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3186006647
Short name T2101
Test name
Test status
Simulation time 172188739 ps
CPU time 0.76 seconds
Started Jul 16 06:51:58 PM PDT 24
Finished Jul 16 06:52:00 PM PDT 24
Peak memory 206808 kb
Host smart-4c2f2991-6c25-4db6-8190-ac2271d8aa4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31860
06647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3186006647
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2072611406
Short name T1920
Test name
Test status
Simulation time 35536850 ps
CPU time 0.65 seconds
Started Jul 16 06:51:58 PM PDT 24
Finished Jul 16 06:52:00 PM PDT 24
Peak memory 206792 kb
Host smart-d47ef62c-de03-48b3-90cb-4448925bb53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20726
11406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2072611406
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3321535779
Short name T1917
Test name
Test status
Simulation time 21732925648 ps
CPU time 47.42 seconds
Started Jul 16 06:52:04 PM PDT 24
Finished Jul 16 06:52:53 PM PDT 24
Peak memory 207060 kb
Host smart-bc4639a3-e22d-404f-b4bf-76d8ea467b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33215
35779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3321535779
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2926269016
Short name T2238
Test name
Test status
Simulation time 188499952 ps
CPU time 0.8 seconds
Started Jul 16 06:51:54 PM PDT 24
Finished Jul 16 06:51:58 PM PDT 24
Peak memory 206668 kb
Host smart-e1950581-33ba-476a-a9a9-501210d22225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29262
69016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2926269016
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.585168426
Short name T1124
Test name
Test status
Simulation time 250351777 ps
CPU time 0.94 seconds
Started Jul 16 06:51:56 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 206844 kb
Host smart-91db154d-b156-40c8-acac-e41e8958012f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58516
8426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.585168426
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.685531171
Short name T2529
Test name
Test status
Simulation time 175028622 ps
CPU time 0.8 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:55 PM PDT 24
Peak memory 206872 kb
Host smart-60ba4a8f-1d4d-401b-ab2a-52c9a18b1d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68553
1171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.685531171
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3169315961
Short name T1698
Test name
Test status
Simulation time 164116942 ps
CPU time 0.81 seconds
Started Jul 16 06:51:57 PM PDT 24
Finished Jul 16 06:51:59 PM PDT 24
Peak memory 206788 kb
Host smart-da5796dc-c842-4d05-a803-f36af1c1642b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31693
15961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3169315961
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.122853728
Short name T1878
Test name
Test status
Simulation time 151965138 ps
CPU time 0.81 seconds
Started Jul 16 06:52:00 PM PDT 24
Finished Jul 16 06:52:02 PM PDT 24
Peak memory 206856 kb
Host smart-3bf27ee4-42be-4da9-8ccc-4377c0ee0b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12285
3728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.122853728
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1580680373
Short name T1900
Test name
Test status
Simulation time 146177903 ps
CPU time 0.76 seconds
Started Jul 16 06:52:05 PM PDT 24
Finished Jul 16 06:52:06 PM PDT 24
Peak memory 206504 kb
Host smart-e087a9cc-c672-4be0-9cf9-4785229d7e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
80373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1580680373
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.859256395
Short name T530
Test name
Test status
Simulation time 210596273 ps
CPU time 0.86 seconds
Started Jul 16 06:52:03 PM PDT 24
Finished Jul 16 06:52:05 PM PDT 24
Peak memory 206776 kb
Host smart-e56965b8-254f-4b21-9a79-54cedf7510f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85925
6395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.859256395
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.837282255
Short name T609
Test name
Test status
Simulation time 212451193 ps
CPU time 0.86 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:55 PM PDT 24
Peak memory 206984 kb
Host smart-11e8d8d9-b283-4497-b03b-be5935a51c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83728
2255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.837282255
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.858216888
Short name T995
Test name
Test status
Simulation time 5851489851 ps
CPU time 164.71 seconds
Started Jul 16 06:52:05 PM PDT 24
Finished Jul 16 06:54:50 PM PDT 24
Peak memory 206892 kb
Host smart-0550a036-d6f7-46ca-b07d-aac0479f23f1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=858216888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.858216888
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.356332487
Short name T1468
Test name
Test status
Simulation time 163339340 ps
CPU time 0.77 seconds
Started Jul 16 06:52:05 PM PDT 24
Finished Jul 16 06:52:06 PM PDT 24
Peak memory 206752 kb
Host smart-c46722d0-8bd4-4372-96b0-136f96eb1e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
2487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.356332487
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2293615157
Short name T2010
Test name
Test status
Simulation time 193821879 ps
CPU time 0.81 seconds
Started Jul 16 06:52:05 PM PDT 24
Finished Jul 16 06:52:07 PM PDT 24
Peak memory 206808 kb
Host smart-a04604ab-ccff-459f-9136-551539e5486c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
15157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2293615157
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1625648765
Short name T564
Test name
Test status
Simulation time 830102957 ps
CPU time 1.92 seconds
Started Jul 16 06:51:53 PM PDT 24
Finished Jul 16 06:51:56 PM PDT 24
Peak memory 206980 kb
Host smart-49c6106f-8973-4968-9abd-8113a19c41e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
48765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1625648765
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3021953456
Short name T810
Test name
Test status
Simulation time 7249379412 ps
CPU time 67.1 seconds
Started Jul 16 06:52:05 PM PDT 24
Finished Jul 16 06:53:13 PM PDT 24
Peak memory 206892 kb
Host smart-af3f81fe-603b-48de-b571-2a8472fd062a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30219
53456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3021953456
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2109694704
Short name T2639
Test name
Test status
Simulation time 77885924 ps
CPU time 0.69 seconds
Started Jul 16 06:52:13 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 206908 kb
Host smart-cbb10d49-6180-42b8-bc09-419a553985ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2109694704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2109694704
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.4159397945
Short name T712
Test name
Test status
Simulation time 3769742698 ps
CPU time 5.4 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 206896 kb
Host smart-8a2f8f95-8bd2-4f58-bf0d-42bcd75cc37a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4159397945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.4159397945
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2546697057
Short name T2039
Test name
Test status
Simulation time 13340506365 ps
CPU time 14.55 seconds
Started Jul 16 06:52:13 PM PDT 24
Finished Jul 16 06:52:31 PM PDT 24
Peak memory 207124 kb
Host smart-b1bde2aa-ee6c-4ccc-bc83-99fe1892bcce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2546697057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2546697057
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.4153266188
Short name T2091
Test name
Test status
Simulation time 23415848991 ps
CPU time 22.48 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:52:34 PM PDT 24
Peak memory 207140 kb
Host smart-b3778e23-7cc9-4894-8d1d-c4fc91c4088d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4153266188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.4153266188
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1920782876
Short name T2483
Test name
Test status
Simulation time 168426970 ps
CPU time 0.84 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:10 PM PDT 24
Peak memory 206888 kb
Host smart-8321308a-f324-4209-8f1f-038716ec1238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19207
82876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1920782876
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2706250670
Short name T1657
Test name
Test status
Simulation time 182422935 ps
CPU time 0.89 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206860 kb
Host smart-8c3be6f4-786c-466d-87a3-15d1aa81fd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27062
50670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2706250670
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1613319855
Short name T1763
Test name
Test status
Simulation time 279868718 ps
CPU time 1.04 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206872 kb
Host smart-a9c57fe1-9801-48c8-90d7-72022489b555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16133
19855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1613319855
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.792354563
Short name T2399
Test name
Test status
Simulation time 715889405 ps
CPU time 1.76 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 206960 kb
Host smart-a2ad6885-15f3-4c98-8d43-bd788cbe9da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79235
4563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.792354563
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3536005164
Short name T1365
Test name
Test status
Simulation time 14129656539 ps
CPU time 24.61 seconds
Started Jul 16 06:52:12 PM PDT 24
Finished Jul 16 06:52:40 PM PDT 24
Peak memory 207040 kb
Host smart-60111d7f-c66a-42ed-96d5-98475b11871e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35360
05164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3536005164
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2068498523
Short name T1812
Test name
Test status
Simulation time 341877500 ps
CPU time 1.26 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 206816 kb
Host smart-1150cd04-98da-4fd7-92cd-ac4a1bedd534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20684
98523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2068498523
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.905613019
Short name T474
Test name
Test status
Simulation time 140464695 ps
CPU time 0.76 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:09 PM PDT 24
Peak memory 206668 kb
Host smart-204d7190-192e-4ce7-b4a8-ebae57d43096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90561
3019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.905613019
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2543875790
Short name T1142
Test name
Test status
Simulation time 36854555 ps
CPU time 0.7 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 206876 kb
Host smart-d4b4fb6a-ba37-4238-b6d6-350846cf5df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
75790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2543875790
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1295649662
Short name T1610
Test name
Test status
Simulation time 821933181 ps
CPU time 2.14 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:15 PM PDT 24
Peak memory 206988 kb
Host smart-8edd9a83-0d1f-4439-b024-ed2b7429108b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12956
49662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1295649662
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1551033265
Short name T728
Test name
Test status
Simulation time 364967608 ps
CPU time 1.79 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:10 PM PDT 24
Peak memory 207016 kb
Host smart-077a810a-863c-426f-8369-ebafcf08f400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15510
33265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1551033265
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3287695205
Short name T1816
Test name
Test status
Simulation time 229617698 ps
CPU time 0.93 seconds
Started Jul 16 06:52:14 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 206892 kb
Host smart-6be359f7-2964-4f1a-8707-f359dbf0d576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32876
95205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3287695205
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1413349071
Short name T645
Test name
Test status
Simulation time 172734393 ps
CPU time 0.84 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 206880 kb
Host smart-5b3ed8bb-12e5-4a43-83e8-f1f2341d81b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14133
49071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1413349071
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.4076747528
Short name T2390
Test name
Test status
Simulation time 225430588 ps
CPU time 0.9 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 206884 kb
Host smart-cfe1d139-ad63-49ab-b77b-e62643a2817f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40767
47528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.4076747528
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.4148039135
Short name T73
Test name
Test status
Simulation time 6020906211 ps
CPU time 171.67 seconds
Started Jul 16 06:52:12 PM PDT 24
Finished Jul 16 06:55:07 PM PDT 24
Peak memory 207088 kb
Host smart-20b503bd-4ce5-4c79-953b-f00f57947a21
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4148039135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.4148039135
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.1520818216
Short name T1370
Test name
Test status
Simulation time 7012291913 ps
CPU time 25.11 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:38 PM PDT 24
Peak memory 207120 kb
Host smart-bb1c9a16-afdb-4fdf-a695-90c78bbc3eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15208
18216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1520818216
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2399560720
Short name T1946
Test name
Test status
Simulation time 245696558 ps
CPU time 0.93 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:10 PM PDT 24
Peak memory 206748 kb
Host smart-9ba5ebfe-37c1-42c8-96b0-51a1007b34ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23995
60720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2399560720
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.4098418380
Short name T2159
Test name
Test status
Simulation time 23315735689 ps
CPU time 26.86 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:52:39 PM PDT 24
Peak memory 206716 kb
Host smart-387e60d0-a2a9-40d6-abc4-cad89b17b9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40984
18380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.4098418380
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3985927861
Short name T752
Test name
Test status
Simulation time 3339499715 ps
CPU time 3.85 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206972 kb
Host smart-618caa8b-bdd0-4262-b34a-684c69b81d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39859
27861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3985927861
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2634861835
Short name T2081
Test name
Test status
Simulation time 9272860694 ps
CPU time 91.65 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:53:41 PM PDT 24
Peak memory 207300 kb
Host smart-3664b1de-7b52-4ef4-8304-2a178f7628a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26348
61835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2634861835
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1326183259
Short name T2703
Test name
Test status
Simulation time 6129925638 ps
CPU time 167.19 seconds
Started Jul 16 06:52:05 PM PDT 24
Finished Jul 16 06:54:54 PM PDT 24
Peak memory 207020 kb
Host smart-e3572811-e4e3-49db-b7f2-85fbc672e273
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1326183259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1326183259
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2669574370
Short name T2371
Test name
Test status
Simulation time 269574040 ps
CPU time 0.98 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:52:11 PM PDT 24
Peak memory 206880 kb
Host smart-b24cc7d3-dfb9-4909-91a6-5a3c5bf2279d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2669574370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2669574370
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1568309171
Short name T1212
Test name
Test status
Simulation time 241844500 ps
CPU time 0.93 seconds
Started Jul 16 06:52:12 PM PDT 24
Finished Jul 16 06:52:17 PM PDT 24
Peak memory 206580 kb
Host smart-62c4ed86-1978-4716-94f7-f2a596dc851a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15683
09171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1568309171
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2001865049
Short name T1699
Test name
Test status
Simulation time 6341234090 ps
CPU time 162.18 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:54:52 PM PDT 24
Peak memory 207080 kb
Host smart-2fc2bd99-80e4-484e-9e0d-dd33277b4ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20018
65049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2001865049
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2863467352
Short name T1429
Test name
Test status
Simulation time 7470667435 ps
CPU time 216.99 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:55:48 PM PDT 24
Peak memory 207084 kb
Host smart-56b4b919-b71e-46ef-bae0-a60cbda423b9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2863467352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2863467352
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2659278025
Short name T2382
Test name
Test status
Simulation time 175356699 ps
CPU time 0.82 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:09 PM PDT 24
Peak memory 206832 kb
Host smart-53c7edbb-ab21-4bd7-8f98-d99d387299fe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2659278025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2659278025
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3486686771
Short name T2152
Test name
Test status
Simulation time 150857657 ps
CPU time 0.81 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206868 kb
Host smart-6b643dd9-acea-4832-8897-9be4756936b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34866
86771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3486686771
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1134014571
Short name T313
Test name
Test status
Simulation time 172272328 ps
CPU time 0.87 seconds
Started Jul 16 06:52:13 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 206624 kb
Host smart-a4da7149-44f8-439c-aace-06cd51558ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11340
14571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1134014571
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.4282359483
Short name T421
Test name
Test status
Simulation time 251340117 ps
CPU time 0.94 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:52:11 PM PDT 24
Peak memory 206884 kb
Host smart-210499e1-c915-40cb-9409-c3690dc4eb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42823
59483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.4282359483
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.4198311805
Short name T1338
Test name
Test status
Simulation time 191788099 ps
CPU time 0.87 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:52:13 PM PDT 24
Peak memory 206860 kb
Host smart-ddc5c09d-4e72-47b3-b061-8b6a3c33692f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41983
11805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.4198311805
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.491220515
Short name T154
Test name
Test status
Simulation time 151805171 ps
CPU time 0.87 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206892 kb
Host smart-fff0e112-9e69-4840-9c0c-084b9e9824d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49122
0515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.491220515
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.716877504
Short name T1486
Test name
Test status
Simulation time 222182646 ps
CPU time 0.94 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206856 kb
Host smart-93147a70-33c1-4c77-b4b0-a8e4c57e8c3d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=716877504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.716877504
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1108350517
Short name T618
Test name
Test status
Simulation time 173823317 ps
CPU time 0.79 seconds
Started Jul 16 06:52:12 PM PDT 24
Finished Jul 16 06:52:16 PM PDT 24
Peak memory 206844 kb
Host smart-691cc4bf-37fe-4c5f-b271-74b2cff937cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11083
50517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1108350517
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.261933164
Short name T666
Test name
Test status
Simulation time 27604395 ps
CPU time 0.67 seconds
Started Jul 16 06:52:06 PM PDT 24
Finished Jul 16 06:52:09 PM PDT 24
Peak memory 206848 kb
Host smart-ed1865cf-2075-4d1c-ac15-fd6e608da793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26193
3164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.261933164
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2139937099
Short name T264
Test name
Test status
Simulation time 6374564078 ps
CPU time 14.77 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 207104 kb
Host smart-83a737fc-3d95-472a-86d8-d0ff5cac77c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21399
37099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2139937099
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.51114433
Short name T1057
Test name
Test status
Simulation time 177696555 ps
CPU time 0.79 seconds
Started Jul 16 06:52:06 PM PDT 24
Finished Jul 16 06:52:09 PM PDT 24
Peak memory 206884 kb
Host smart-34b1d471-c715-4cfe-b926-443129fd570e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51114
433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.51114433
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.345215460
Short name T860
Test name
Test status
Simulation time 200003658 ps
CPU time 0.89 seconds
Started Jul 16 06:52:06 PM PDT 24
Finished Jul 16 06:52:09 PM PDT 24
Peak memory 206908 kb
Host smart-9f1b63a1-7ff7-41ca-8c55-d588562b5163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34521
5460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.345215460
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3606469775
Short name T1061
Test name
Test status
Simulation time 245752557 ps
CPU time 0.93 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206860 kb
Host smart-050350ea-a5a9-41ce-856b-a2f8c1675bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36064
69775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3606469775
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3722713332
Short name T935
Test name
Test status
Simulation time 178557723 ps
CPU time 0.88 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:10 PM PDT 24
Peak memory 206888 kb
Host smart-ce8d7c87-f1b5-4dad-9020-4ff31df658ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37227
13332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3722713332
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.2427787313
Short name T1976
Test name
Test status
Simulation time 159524503 ps
CPU time 0.79 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:09 PM PDT 24
Peak memory 206812 kb
Host smart-94951fd8-2614-45a9-a109-6a6c5feca241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24277
87313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.2427787313
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2161170632
Short name T488
Test name
Test status
Simulation time 205391801 ps
CPU time 0.82 seconds
Started Jul 16 06:52:14 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 206856 kb
Host smart-3ebf86be-6a26-4c12-82a1-5e92aec5453c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21611
70632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2161170632
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3824556525
Short name T1873
Test name
Test status
Simulation time 177640849 ps
CPU time 0.77 seconds
Started Jul 16 06:52:07 PM PDT 24
Finished Jul 16 06:52:10 PM PDT 24
Peak memory 206896 kb
Host smart-74bf9cd7-acf8-4ffc-b9d9-9c1196a60416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38245
56525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3824556525
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1574811692
Short name T723
Test name
Test status
Simulation time 232617005 ps
CPU time 0.93 seconds
Started Jul 16 06:52:12 PM PDT 24
Finished Jul 16 06:52:17 PM PDT 24
Peak memory 206660 kb
Host smart-6f49b0fb-30ad-4184-9b3b-5c5495a30275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
11692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1574811692
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1886321560
Short name T2375
Test name
Test status
Simulation time 5372523417 ps
CPU time 150.07 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:54:42 PM PDT 24
Peak memory 207040 kb
Host smart-379d9bcf-bbb6-4151-9ed1-d3205efc30ac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1886321560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1886321560
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2549194041
Short name T2462
Test name
Test status
Simulation time 238508353 ps
CPU time 0.88 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:14 PM PDT 24
Peak memory 206736 kb
Host smart-f518e19d-d7e8-4538-9f99-d32aa9115c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25491
94041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2549194041
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1832278421
Short name T821
Test name
Test status
Simulation time 187283001 ps
CPU time 0.82 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206860 kb
Host smart-96ed40a4-627c-478f-b568-f8f5c16574fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18322
78421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1832278421
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.743910084
Short name T2349
Test name
Test status
Simulation time 741763418 ps
CPU time 1.75 seconds
Started Jul 16 06:52:11 PM PDT 24
Finished Jul 16 06:52:17 PM PDT 24
Peak memory 207060 kb
Host smart-d6dd6d04-0851-4335-b011-2a7df9cb3ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74391
0084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.743910084
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.492860856
Short name T1819
Test name
Test status
Simulation time 6287298900 ps
CPU time 45.97 seconds
Started Jul 16 06:52:09 PM PDT 24
Finished Jul 16 06:52:58 PM PDT 24
Peak memory 207076 kb
Host smart-7f8cbef2-cb81-4ca0-8407-e14ce70b93f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49286
0856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.492860856
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.4181579371
Short name T773
Test name
Test status
Simulation time 33134979 ps
CPU time 0.69 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206832 kb
Host smart-d457b8f3-075c-45c5-b5b4-0b84cb4e2931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4181579371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.4181579371
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3035853834
Short name T2596
Test name
Test status
Simulation time 3795998680 ps
CPU time 4.54 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:17 PM PDT 24
Peak memory 206944 kb
Host smart-51bdd7ba-c53a-44c1-9cc2-72066eac590d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3035853834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.3035853834
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.294200575
Short name T1011
Test name
Test status
Simulation time 13451832311 ps
CPU time 12.14 seconds
Started Jul 16 06:52:10 PM PDT 24
Finished Jul 16 06:52:26 PM PDT 24
Peak memory 206964 kb
Host smart-e6bc00bf-d9ae-4a9d-91d0-23cc9bb498a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=294200575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.294200575
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.49760483
Short name T1751
Test name
Test status
Simulation time 23327845967 ps
CPU time 22.64 seconds
Started Jul 16 06:52:11 PM PDT 24
Finished Jul 16 06:52:38 PM PDT 24
Peak memory 207156 kb
Host smart-0b7675a4-a06d-42d3-be0f-6f9ed000a63a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=49760483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.49760483
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.270528188
Short name T2312
Test name
Test status
Simulation time 149128448 ps
CPU time 0.8 seconds
Started Jul 16 06:52:08 PM PDT 24
Finished Jul 16 06:52:12 PM PDT 24
Peak memory 206728 kb
Host smart-a4228c59-a9e6-4075-bff4-0ff152111e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27052
8188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.270528188
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1332496477
Short name T2327
Test name
Test status
Simulation time 169200976 ps
CPU time 0.82 seconds
Started Jul 16 06:52:11 PM PDT 24
Finished Jul 16 06:52:16 PM PDT 24
Peak memory 206896 kb
Host smart-c846b2fe-3b6d-4793-b6f7-9f0cb6e39097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13324
96477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1332496477
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.453709439
Short name T1233
Test name
Test status
Simulation time 236504577 ps
CPU time 0.97 seconds
Started Jul 16 06:52:12 PM PDT 24
Finished Jul 16 06:52:17 PM PDT 24
Peak memory 206600 kb
Host smart-f6953b17-513e-48bc-972f-e7bc75e704f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45370
9439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.453709439
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.4005842314
Short name T2085
Test name
Test status
Simulation time 469068288 ps
CPU time 1.28 seconds
Started Jul 16 06:52:11 PM PDT 24
Finished Jul 16 06:52:16 PM PDT 24
Peak memory 206896 kb
Host smart-589d6ae8-f534-423d-a8a9-e0399ffb0bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40058
42314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.4005842314
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3634472178
Short name T2355
Test name
Test status
Simulation time 9708531078 ps
CPU time 17.23 seconds
Started Jul 16 06:52:11 PM PDT 24
Finished Jul 16 06:52:32 PM PDT 24
Peak memory 207112 kb
Host smart-8d19ccc5-e12c-4e4f-b760-8c8ecd7eb5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36344
72178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3634472178
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1776831760
Short name T2563
Test name
Test status
Simulation time 430611306 ps
CPU time 1.28 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 206888 kb
Host smart-09308d52-a9cb-489a-8227-7d6554abfb43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17768
31760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1776831760
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.628077714
Short name T1997
Test name
Test status
Simulation time 214048343 ps
CPU time 0.83 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:32 PM PDT 24
Peak memory 206756 kb
Host smart-0bf93cde-33f8-43bf-8e3c-64d2f54ea244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62807
7714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.628077714
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.575235487
Short name T1263
Test name
Test status
Simulation time 55975306 ps
CPU time 0.68 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:29 PM PDT 24
Peak memory 206888 kb
Host smart-5e307297-ce71-45b7-8e30-73970e647eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57523
5487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.575235487
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3118972478
Short name T1312
Test name
Test status
Simulation time 931583290 ps
CPU time 2.45 seconds
Started Jul 16 06:53:13 PM PDT 24
Finished Jul 16 06:53:18 PM PDT 24
Peak memory 207068 kb
Host smart-1a23e153-0fb6-49a4-9cf6-0be51bbd2d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
72478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3118972478
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.4178366358
Short name T1367
Test name
Test status
Simulation time 168018780 ps
CPU time 1.74 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:29 PM PDT 24
Peak memory 207044 kb
Host smart-5f58c06e-d844-451f-8b5e-649c71170eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41783
66358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.4178366358
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.829535044
Short name T2088
Test name
Test status
Simulation time 196941860 ps
CPU time 0.87 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:52:26 PM PDT 24
Peak memory 206864 kb
Host smart-b5fbc06a-4d08-43eb-921c-539a5267d7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82953
5044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.829535044
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2009939827
Short name T772
Test name
Test status
Simulation time 131837967 ps
CPU time 0.73 seconds
Started Jul 16 06:52:22 PM PDT 24
Finished Jul 16 06:52:23 PM PDT 24
Peak memory 206852 kb
Host smart-95deadd0-63f5-44a3-8b6d-c92238b6d82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099
39827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2009939827
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.770018065
Short name T1163
Test name
Test status
Simulation time 212686362 ps
CPU time 0.88 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:30 PM PDT 24
Peak memory 206880 kb
Host smart-1c04d441-5f94-461a-8376-ef725522858a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77001
8065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.770018065
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.4263883969
Short name T211
Test name
Test status
Simulation time 10788024551 ps
CPU time 314.85 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:57:46 PM PDT 24
Peak memory 207132 kb
Host smart-ff827fc8-f599-4caf-a245-b1635ef3018a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4263883969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.4263883969
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.4043341755
Short name T2756
Test name
Test status
Simulation time 4475248068 ps
CPU time 31.38 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:53:04 PM PDT 24
Peak memory 207092 kb
Host smart-2b3c14ad-7658-4e79-ae46-56ef0d88422a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40433
41755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.4043341755
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1792980911
Short name T1447
Test name
Test status
Simulation time 216018842 ps
CPU time 0.88 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206844 kb
Host smart-8cad96d9-c906-4f34-a076-a518af238971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17929
80911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1792980911
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.807072126
Short name T1981
Test name
Test status
Simulation time 23287390423 ps
CPU time 24.79 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:52 PM PDT 24
Peak memory 206916 kb
Host smart-ee195708-4f1e-48ce-aa9c-047e0b1e4917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80707
2126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.807072126
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.3995861885
Short name T307
Test name
Test status
Simulation time 3310269844 ps
CPU time 3.72 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206800 kb
Host smart-96b9a6b3-3c01-4218-a24d-4fc32f5b29e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39958
61885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.3995861885
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2364251519
Short name T856
Test name
Test status
Simulation time 9156434391 ps
CPU time 65.02 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:53:30 PM PDT 24
Peak memory 207148 kb
Host smart-7d82a023-3ccd-4434-8573-c521c84ed66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23642
51519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2364251519
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1062198185
Short name T693
Test name
Test status
Simulation time 5810888092 ps
CPU time 155.54 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:54:59 PM PDT 24
Peak memory 207076 kb
Host smart-6c57ce79-4f91-43bf-ab8e-1d9738467da3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1062198185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1062198185
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3156591321
Short name T2466
Test name
Test status
Simulation time 241207083 ps
CPU time 0.95 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:30 PM PDT 24
Peak memory 206732 kb
Host smart-7b6a384d-ded6-4d48-b0f8-3874ed602ab9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3156591321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3156591321
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1163538373
Short name T2599
Test name
Test status
Simulation time 242014611 ps
CPU time 0.9 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:30 PM PDT 24
Peak memory 206884 kb
Host smart-20a52fba-5843-40ae-8025-8d41a473840f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11635
38373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1163538373
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1175945941
Short name T1265
Test name
Test status
Simulation time 5430761760 ps
CPU time 38.1 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:53:02 PM PDT 24
Peak memory 207240 kb
Host smart-030ae382-e6f2-4606-b563-8cf149404503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11759
45941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1175945941
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.620137321
Short name T1959
Test name
Test status
Simulation time 6363097800 ps
CPU time 185.43 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:55:29 PM PDT 24
Peak memory 206984 kb
Host smart-d841130d-6407-4127-9e34-764568761930
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=620137321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.620137321
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.1420915453
Short name T1982
Test name
Test status
Simulation time 243764916 ps
CPU time 0.92 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 206876 kb
Host smart-e1a5036f-11ee-4b38-b1ff-6fbca24dd1d4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1420915453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.1420915453
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1388294532
Short name T613
Test name
Test status
Simulation time 145021024 ps
CPU time 0.76 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206860 kb
Host smart-4e159722-ff17-4673-a8b4-f5754a77d49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13882
94532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1388294532
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3574362493
Short name T1476
Test name
Test status
Simulation time 171835844 ps
CPU time 0.8 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:52:25 PM PDT 24
Peak memory 206892 kb
Host smart-044ac23f-b5ce-4b04-a22c-f41b82c8d2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35743
62493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3574362493
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2732378012
Short name T2273
Test name
Test status
Simulation time 182846678 ps
CPU time 0.88 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:31 PM PDT 24
Peak memory 206884 kb
Host smart-0c2de0ac-17e6-4f47-9055-6202483b682f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27323
78012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2732378012
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.465906038
Short name T2319
Test name
Test status
Simulation time 158480827 ps
CPU time 0.79 seconds
Started Jul 16 06:52:22 PM PDT 24
Finished Jul 16 06:52:24 PM PDT 24
Peak memory 206872 kb
Host smart-d7f48357-4bb3-41e9-a4d8-61d5ac74e2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46590
6038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.465906038
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2362559585
Short name T396
Test name
Test status
Simulation time 183594959 ps
CPU time 0.86 seconds
Started Jul 16 06:52:22 PM PDT 24
Finished Jul 16 06:52:24 PM PDT 24
Peak memory 206848 kb
Host smart-16af24bb-c061-4221-b294-bb3d91536584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23625
59585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2362559585
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1605768952
Short name T1768
Test name
Test status
Simulation time 147934214 ps
CPU time 0.75 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206524 kb
Host smart-1cb3f076-6457-41bb-be0a-abb3b42dda6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16057
68952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1605768952
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2613857334
Short name T2484
Test name
Test status
Simulation time 206096178 ps
CPU time 0.86 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:31 PM PDT 24
Peak memory 206744 kb
Host smart-6ce94233-1ca6-42d9-bc00-cd053c3e0f63
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2613857334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2613857334
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.735406973
Short name T939
Test name
Test status
Simulation time 146878600 ps
CPU time 0.77 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206836 kb
Host smart-92367309-4a2e-4cb0-adbd-23908731c62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73540
6973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.735406973
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.4294413258
Short name T1779
Test name
Test status
Simulation time 37566431 ps
CPU time 0.65 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 207016 kb
Host smart-a3b5d716-6d3b-4d50-a9d8-1563e0acb443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42944
13258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.4294413258
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1187857380
Short name T1521
Test name
Test status
Simulation time 13241292306 ps
CPU time 30.04 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:53:00 PM PDT 24
Peak memory 207052 kb
Host smart-a7deebb5-e6c2-46e2-9271-66bab8081ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11878
57380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1187857380
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1020126905
Short name T730
Test name
Test status
Simulation time 155394507 ps
CPU time 0.76 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:52:26 PM PDT 24
Peak memory 206888 kb
Host smart-fad68a23-6936-4097-8cca-05425a8d2e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10201
26905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1020126905
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3051940291
Short name T897
Test name
Test status
Simulation time 245358073 ps
CPU time 0.93 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 206812 kb
Host smart-57829ba7-a2e5-4754-9a57-8ab9aab07e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30519
40291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3051940291
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3826376262
Short name T334
Test name
Test status
Simulation time 216745822 ps
CPU time 0.92 seconds
Started Jul 16 06:52:22 PM PDT 24
Finished Jul 16 06:52:24 PM PDT 24
Peak memory 206860 kb
Host smart-21737c66-702a-4c78-85ee-06ea69d82dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38263
76262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3826376262
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2297052309
Short name T1384
Test name
Test status
Simulation time 173730985 ps
CPU time 0.82 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206844 kb
Host smart-ca59a738-bad6-42b9-ad65-959a6885f994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22970
52309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2297052309
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3102940596
Short name T1380
Test name
Test status
Simulation time 176760615 ps
CPU time 0.8 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206860 kb
Host smart-64923df6-6512-4e5c-bcb6-b8c920258807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31029
40596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3102940596
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.184894191
Short name T2077
Test name
Test status
Simulation time 219547109 ps
CPU time 0.91 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:34 PM PDT 24
Peak memory 206824 kb
Host smart-ec4794bd-094e-4542-8a8f-896fb615c1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18489
4191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.184894191
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3108820906
Short name T2734
Test name
Test status
Simulation time 160717337 ps
CPU time 0.77 seconds
Started Jul 16 06:52:30 PM PDT 24
Finished Jul 16 06:52:35 PM PDT 24
Peak memory 206892 kb
Host smart-3ba4501c-c8cd-4d11-8512-aaa7a0e20184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31088
20906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3108820906
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1937843800
Short name T968
Test name
Test status
Simulation time 218839618 ps
CPU time 0.91 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:52:27 PM PDT 24
Peak memory 206864 kb
Host smart-dc827f62-3573-478b-8217-1e255c9f7aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19378
43800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1937843800
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.524251719
Short name T146
Test name
Test status
Simulation time 4034081853 ps
CPU time 39.96 seconds
Started Jul 16 06:52:22 PM PDT 24
Finished Jul 16 06:53:02 PM PDT 24
Peak memory 207056 kb
Host smart-3be2d239-1d09-473a-a3e6-a6c90299013c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=524251719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.524251719
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.274736319
Short name T1269
Test name
Test status
Simulation time 186360399 ps
CPU time 0.8 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:31 PM PDT 24
Peak memory 206888 kb
Host smart-f2bb1a75-02ad-4648-b6ca-51afc5299986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27473
6319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.274736319
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1687725532
Short name T2542
Test name
Test status
Simulation time 191825655 ps
CPU time 0.85 seconds
Started Jul 16 06:52:22 PM PDT 24
Finished Jul 16 06:52:24 PM PDT 24
Peak memory 206884 kb
Host smart-ebceabd0-8338-4072-a496-722a4642dd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16877
25532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1687725532
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.1920535400
Short name T557
Test name
Test status
Simulation time 484144112 ps
CPU time 1.29 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:32 PM PDT 24
Peak memory 206860 kb
Host smart-cbea48fd-eca4-4863-89c5-c622d4420d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19205
35400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1920535400
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.4270089761
Short name T1226
Test name
Test status
Simulation time 4965750547 ps
CPU time 136.79 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:54:41 PM PDT 24
Peak memory 207084 kb
Host smart-a2f85e68-c452-4fd4-a68a-1dc507d464e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
89761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.4270089761
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.4258236092
Short name T2413
Test name
Test status
Simulation time 56027974 ps
CPU time 0.67 seconds
Started Jul 16 06:52:34 PM PDT 24
Finished Jul 16 06:52:36 PM PDT 24
Peak memory 206844 kb
Host smart-7e4c2663-7ad9-4a42-8233-69d4633816ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4258236092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.4258236092
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.286294046
Short name T1906
Test name
Test status
Simulation time 3632202510 ps
CPU time 4.04 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:36 PM PDT 24
Peak memory 206880 kb
Host smart-a36b23e8-bf1e-4645-a763-70380bc26af2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=286294046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.286294046
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1674022167
Short name T946
Test name
Test status
Simulation time 13350039886 ps
CPU time 12.46 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206336 kb
Host smart-6cc94e2a-ba20-4beb-9a73-cf0a087134ad
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1674022167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1674022167
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1474106594
Short name T567
Test name
Test status
Simulation time 162366794 ps
CPU time 0.87 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:31 PM PDT 24
Peak memory 206728 kb
Host smart-1f3be879-67dc-4c8f-97ef-6f663398aa48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14741
06594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1474106594
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2335572528
Short name T983
Test name
Test status
Simulation time 144588248 ps
CPU time 0.77 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:32 PM PDT 24
Peak memory 206856 kb
Host smart-30e6f65c-5ba6-4724-9720-4392a3014744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23355
72528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2335572528
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1838807720
Short name T552
Test name
Test status
Simulation time 472379300 ps
CPU time 1.53 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:34 PM PDT 24
Peak memory 206848 kb
Host smart-16f825b8-9a4b-4ba5-8ba9-af3812676e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18388
07720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1838807720
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.639906129
Short name T1193
Test name
Test status
Simulation time 1206961294 ps
CPU time 2.61 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206876 kb
Host smart-d74f51dd-d664-48cc-9b2c-46f5bdfc0a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63990
6129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.639906129
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.809697556
Short name T405
Test name
Test status
Simulation time 6150010573 ps
CPU time 10.69 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 207072 kb
Host smart-341a5c99-d1df-4c5f-b546-2dd416def2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80969
7556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.809697556
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.2804512336
Short name T2578
Test name
Test status
Simulation time 507370753 ps
CPU time 1.47 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:29 PM PDT 24
Peak memory 206860 kb
Host smart-035f8b86-d2e8-4062-a62f-ad1d406ff2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28045
12336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.2804512336
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.4218585816
Short name T1960
Test name
Test status
Simulation time 142210335 ps
CPU time 0.75 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:32 PM PDT 24
Peak memory 206756 kb
Host smart-445940c6-9387-49bd-a33f-c77d30d219f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42185
85816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.4218585816
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.4056447861
Short name T25
Test name
Test status
Simulation time 31725455 ps
CPU time 0.65 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:32 PM PDT 24
Peak memory 206876 kb
Host smart-73f5d1f4-990d-4e4b-8690-3ea61612ef0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40564
47861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.4056447861
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2678324960
Short name T844
Test name
Test status
Simulation time 980344387 ps
CPU time 2 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:34 PM PDT 24
Peak memory 207008 kb
Host smart-0651b979-313a-4e81-ad46-f15a92215861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26783
24960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2678324960
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3585622759
Short name T1663
Test name
Test status
Simulation time 355564622 ps
CPU time 2.33 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206376 kb
Host smart-47859c24-82e4-43a1-90f1-a04bfb7f6d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856
22759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3585622759
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2342259709
Short name T321
Test name
Test status
Simulation time 235831122 ps
CPU time 0.88 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:31 PM PDT 24
Peak memory 206864 kb
Host smart-ffed6dda-c08b-4fa2-ae09-9ce20d5b2042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23422
59709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2342259709
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2131775135
Short name T1396
Test name
Test status
Simulation time 143731291 ps
CPU time 0.75 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:31 PM PDT 24
Peak memory 206752 kb
Host smart-c5011391-9830-4c60-b8c5-2c47352636be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21317
75135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2131775135
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1553272876
Short name T1880
Test name
Test status
Simulation time 283336945 ps
CPU time 0.94 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:52:32 PM PDT 24
Peak memory 206856 kb
Host smart-4d1836b7-594e-4dd6-b320-794281259c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15532
72876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1553272876
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.4073537460
Short name T2750
Test name
Test status
Simulation time 4734973015 ps
CPU time 137.5 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:54:48 PM PDT 24
Peak memory 207100 kb
Host smart-37ab38d4-50fb-4cf6-8804-0e6ec53f5f70
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4073537460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.4073537460
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.3542576316
Short name T2509
Test name
Test status
Simulation time 5261175070 ps
CPU time 47.16 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:53:19 PM PDT 24
Peak memory 207128 kb
Host smart-652c82b9-383d-4274-9c29-922d5350cf1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35425
76316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.3542576316
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2016314180
Short name T1536
Test name
Test status
Simulation time 219425868 ps
CPU time 0.86 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206892 kb
Host smart-e5c43b26-8866-4b69-8225-306db61addaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20163
14180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2016314180
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3642002153
Short name T1968
Test name
Test status
Simulation time 23358954878 ps
CPU time 24.95 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206944 kb
Host smart-dcf4967c-ab9c-4025-8153-db7f3b2340d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36420
02153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3642002153
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2325823273
Short name T1301
Test name
Test status
Simulation time 3338119929 ps
CPU time 4.7 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:37 PM PDT 24
Peak memory 206960 kb
Host smart-b840774f-4dc5-4392-82f2-604954b5f2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23258
23273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2325823273
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2918264250
Short name T1432
Test name
Test status
Simulation time 8482124229 ps
CPU time 83.09 seconds
Started Jul 16 06:52:25 PM PDT 24
Finished Jul 16 06:53:53 PM PDT 24
Peak memory 207132 kb
Host smart-4ca53ed5-bb03-455a-867b-e6654e221d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
64250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2918264250
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2773405043
Short name T783
Test name
Test status
Simulation time 4031284833 ps
CPU time 105.72 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:54:18 PM PDT 24
Peak memory 207064 kb
Host smart-7e264cc6-1062-4590-ab10-b1a628cc4246
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2773405043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2773405043
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.538340723
Short name T1716
Test name
Test status
Simulation time 241102088 ps
CPU time 0.98 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206864 kb
Host smart-7de9d765-ae6d-4bfd-aa2f-688241a01c1e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=538340723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.538340723
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2689519097
Short name T2075
Test name
Test status
Simulation time 219389992 ps
CPU time 0.88 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 206744 kb
Host smart-f4b32f3a-0ae6-46a7-a39e-e16655caeba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26895
19097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2689519097
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.23373361
Short name T1709
Test name
Test status
Simulation time 5385323739 ps
CPU time 48.24 seconds
Started Jul 16 06:52:23 PM PDT 24
Finished Jul 16 06:53:14 PM PDT 24
Peak memory 206988 kb
Host smart-c4f06768-77d6-4d71-90f0-cf3ef0c37bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23373
361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.23373361
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2135809166
Short name T695
Test name
Test status
Simulation time 2921547919 ps
CPU time 26.46 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:59 PM PDT 24
Peak memory 207012 kb
Host smart-5a8a7e07-510d-49df-ba4f-658a4f4d4d84
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2135809166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2135809166
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3493995235
Short name T2260
Test name
Test status
Simulation time 180936340 ps
CPU time 0.8 seconds
Started Jul 16 06:52:29 PM PDT 24
Finished Jul 16 06:52:35 PM PDT 24
Peak memory 206892 kb
Host smart-93b03326-4d79-4f7b-8862-392fc92cd21c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3493995235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3493995235
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1398485904
Short name T594
Test name
Test status
Simulation time 138464451 ps
CPU time 0.86 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206908 kb
Host smart-ca113bfe-ffda-4e1d-ae91-ad6263c89eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13984
85904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1398485904
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1236066234
Short name T2309
Test name
Test status
Simulation time 206512669 ps
CPU time 0.88 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206880 kb
Host smart-83091e5d-aa29-4cd2-b255-0f789657604f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
66234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1236066234
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3030119043
Short name T1106
Test name
Test status
Simulation time 158813089 ps
CPU time 0.8 seconds
Started Jul 16 06:52:29 PM PDT 24
Finished Jul 16 06:52:35 PM PDT 24
Peak memory 206888 kb
Host smart-33811281-ba62-4ded-8e00-8e5fd1fd16a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30301
19043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3030119043
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2619717507
Short name T964
Test name
Test status
Simulation time 197886791 ps
CPU time 0.81 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206752 kb
Host smart-7abc5aba-7c19-4700-971d-e5064cb0a253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26197
17507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2619717507
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2802782281
Short name T2716
Test name
Test status
Simulation time 192887818 ps
CPU time 0.86 seconds
Started Jul 16 06:52:26 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206508 kb
Host smart-7ea112ee-b2c1-4f3e-8389-d5d294cf0449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28027
82281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2802782281
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3093937200
Short name T524
Test name
Test status
Simulation time 182676796 ps
CPU time 0.79 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206888 kb
Host smart-1d82951d-a835-4a60-b1d5-7273385230ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30939
37200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3093937200
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3563805945
Short name T2232
Test name
Test status
Simulation time 243850269 ps
CPU time 0.96 seconds
Started Jul 16 06:52:27 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206776 kb
Host smart-a9a1055c-be13-461b-8a74-7df4739582fd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3563805945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3563805945
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1815617029
Short name T2366
Test name
Test status
Simulation time 177659109 ps
CPU time 0.78 seconds
Started Jul 16 06:52:24 PM PDT 24
Finished Jul 16 06:52:30 PM PDT 24
Peak memory 206808 kb
Host smart-f89e21ca-6b1a-4dec-99cb-3fbaa989ae65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18156
17029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1815617029
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.4237213436
Short name T1390
Test name
Test status
Simulation time 94722182 ps
CPU time 0.71 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:52:39 PM PDT 24
Peak memory 207020 kb
Host smart-369c63ed-f954-4053-a695-7eb364cfe063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372
13436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.4237213436
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2290927903
Short name T1857
Test name
Test status
Simulation time 13784829183 ps
CPU time 29.68 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:53:11 PM PDT 24
Peak memory 207148 kb
Host smart-55183623-c24c-4d15-ae68-e1d5a062a07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22909
27903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2290927903
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3814446985
Short name T1686
Test name
Test status
Simulation time 154144950 ps
CPU time 0.81 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:39 PM PDT 24
Peak memory 206896 kb
Host smart-7beb0187-03ad-4124-ba2b-eca883172644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
46985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3814446985
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.907385349
Short name T548
Test name
Test status
Simulation time 245614995 ps
CPU time 0.94 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:52:46 PM PDT 24
Peak memory 206876 kb
Host smart-cb5d5711-23db-4be3-9e00-88d94fbf62cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90738
5349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.907385349
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3596787611
Short name T893
Test name
Test status
Simulation time 219811829 ps
CPU time 0.85 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:41 PM PDT 24
Peak memory 206820 kb
Host smart-3e716dc5-e6c4-451a-a9d9-98d9e852c69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35967
87611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3596787611
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.466820687
Short name T442
Test name
Test status
Simulation time 155221940 ps
CPU time 0.78 seconds
Started Jul 16 06:52:34 PM PDT 24
Finished Jul 16 06:52:36 PM PDT 24
Peak memory 206872 kb
Host smart-a993022b-148e-404f-95f5-c977db3e416f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46682
0687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.466820687
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1605493295
Short name T2110
Test name
Test status
Simulation time 160309478 ps
CPU time 0.8 seconds
Started Jul 16 06:52:35 PM PDT 24
Finished Jul 16 06:52:37 PM PDT 24
Peak memory 206868 kb
Host smart-c0e66e30-f24b-4e05-bcf6-0cfafe5d5e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16054
93295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1605493295
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3761149333
Short name T471
Test name
Test status
Simulation time 161395213 ps
CPU time 0.78 seconds
Started Jul 16 06:52:34 PM PDT 24
Finished Jul 16 06:52:36 PM PDT 24
Peak memory 206856 kb
Host smart-a8dc2fdf-633b-47d0-bad6-53873e8af933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37611
49333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3761149333
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1030565824
Short name T1837
Test name
Test status
Simulation time 150348916 ps
CPU time 0.84 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:52:37 PM PDT 24
Peak memory 206668 kb
Host smart-b158c7fa-c614-4e34-9ff3-1b46bc620442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10305
65824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1030565824
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.247633514
Short name T2041
Test name
Test status
Simulation time 217831984 ps
CPU time 0.95 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:52:38 PM PDT 24
Peak memory 206664 kb
Host smart-ae742def-e8af-4778-b687-2c2348d00b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24763
3514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.247633514
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.3531412373
Short name T1525
Test name
Test status
Simulation time 5667335134 ps
CPU time 41.65 seconds
Started Jul 16 06:53:06 PM PDT 24
Finished Jul 16 06:53:50 PM PDT 24
Peak memory 207088 kb
Host smart-5d99cc59-6f3b-493f-8e83-561fcad05668
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3531412373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.3531412373
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.373410866
Short name T1089
Test name
Test status
Simulation time 190211012 ps
CPU time 0.85 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:52:39 PM PDT 24
Peak memory 206844 kb
Host smart-ced9bbd3-c6d2-45f4-9834-2d01a9489b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37341
0866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.373410866
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3511067344
Short name T756
Test name
Test status
Simulation time 172856857 ps
CPU time 0.82 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:52:37 PM PDT 24
Peak memory 206860 kb
Host smart-8cb0534a-6f70-4f3f-8902-148575748393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35110
67344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3511067344
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2304453648
Short name T1246
Test name
Test status
Simulation time 583590779 ps
CPU time 1.46 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:44 PM PDT 24
Peak memory 206860 kb
Host smart-7e33bafd-3be9-4b5c-8125-1ac4c49bf3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23044
53648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2304453648
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1321247867
Short name T1945
Test name
Test status
Simulation time 3371524603 ps
CPU time 25.37 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 207024 kb
Host smart-f83b0b9d-43ef-4886-a5a1-5783efa62ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13212
47867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1321247867
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.1750154950
Short name T1524
Test name
Test status
Simulation time 35891431 ps
CPU time 0.68 seconds
Started Jul 16 06:52:39 PM PDT 24
Finished Jul 16 06:52:44 PM PDT 24
Peak memory 206928 kb
Host smart-4bf5a9ca-efec-4ea7-9c0b-cd4b067cee87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1750154950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1750154950
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1764986671
Short name T2009
Test name
Test status
Simulation time 4350977324 ps
CPU time 4.74 seconds
Started Jul 16 06:52:39 PM PDT 24
Finished Jul 16 06:52:48 PM PDT 24
Peak memory 206916 kb
Host smart-fb35533e-085c-46d9-8a0d-403fdf03631b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1764986671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1764986671
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2756253025
Short name T1382
Test name
Test status
Simulation time 13353861417 ps
CPU time 14.57 seconds
Started Jul 16 06:52:34 PM PDT 24
Finished Jul 16 06:52:50 PM PDT 24
Peak memory 207044 kb
Host smart-e3d59b54-eabf-420e-810a-a49c72770401
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2756253025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2756253025
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.1782319266
Short name T749
Test name
Test status
Simulation time 23413353345 ps
CPU time 26.34 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:53:06 PM PDT 24
Peak memory 206884 kb
Host smart-a9de2a7d-ca4e-44bd-95e5-77a8515859a5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1782319266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.1782319266
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3994818770
Short name T2105
Test name
Test status
Simulation time 161481651 ps
CPU time 0.82 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:41 PM PDT 24
Peak memory 206880 kb
Host smart-949fab16-e53e-4c8f-853e-9a40c2c06d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
18770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3994818770
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3565056681
Short name T2514
Test name
Test status
Simulation time 172308782 ps
CPU time 0.8 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:40 PM PDT 24
Peak memory 206732 kb
Host smart-16893a28-de59-438e-aa70-633d5ae6abed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35650
56681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3565056681
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1291992919
Short name T2022
Test name
Test status
Simulation time 278459953 ps
CPU time 1.07 seconds
Started Jul 16 06:52:39 PM PDT 24
Finished Jul 16 06:52:44 PM PDT 24
Peak memory 206684 kb
Host smart-212fd9f3-3b2f-47c2-b842-6a19674a5fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12919
92919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1291992919
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2693159509
Short name T949
Test name
Test status
Simulation time 1007672539 ps
CPU time 2.18 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:52:47 PM PDT 24
Peak memory 207084 kb
Host smart-1e973885-2c9b-4b62-9b90-8b92f85c9d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931
59509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2693159509
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3872251544
Short name T155
Test name
Test status
Simulation time 20694763291 ps
CPU time 40.61 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 207152 kb
Host smart-af799e1a-a054-45a3-8c51-f564fa3ec353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38722
51544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3872251544
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3022796933
Short name T883
Test name
Test status
Simulation time 374518291 ps
CPU time 1.19 seconds
Started Jul 16 06:52:35 PM PDT 24
Finished Jul 16 06:52:37 PM PDT 24
Peak memory 206884 kb
Host smart-f5e496f9-2a05-45c2-8e56-6b3d5e4485f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30227
96933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3022796933
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.251124099
Short name T1689
Test name
Test status
Simulation time 177982337 ps
CPU time 0.79 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206832 kb
Host smart-51aa0d69-a1a8-4464-8eca-571b59fc40b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25112
4099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.251124099
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.582344723
Short name T1427
Test name
Test status
Simulation time 36960820 ps
CPU time 0.66 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206788 kb
Host smart-3b37963a-7033-41ed-8599-fcb83b2b10d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58234
4723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.582344723
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1382355939
Short name T1532
Test name
Test status
Simulation time 1000291761 ps
CPU time 2.31 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206988 kb
Host smart-adb807dd-ef58-41f4-af07-b56151402675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13823
55939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1382355939
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1105786663
Short name T955
Test name
Test status
Simulation time 267299907 ps
CPU time 2.03 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:44 PM PDT 24
Peak memory 207028 kb
Host smart-bc965ed0-5869-4b58-a423-698c32bcc2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11057
86663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1105786663
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.461839186
Short name T1464
Test name
Test status
Simulation time 190806450 ps
CPU time 0.87 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:40 PM PDT 24
Peak memory 206884 kb
Host smart-123ba0d0-f9f8-4606-8a37-4861c3579711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46183
9186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.461839186
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2494562660
Short name T1497
Test name
Test status
Simulation time 154599095 ps
CPU time 0.79 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:41 PM PDT 24
Peak memory 206812 kb
Host smart-24319fe5-05a7-49db-8325-2f61d309b523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24945
62660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2494562660
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.118094212
Short name T2210
Test name
Test status
Simulation time 206712634 ps
CPU time 0.94 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:52:39 PM PDT 24
Peak memory 206852 kb
Host smart-1ec69fab-a8c9-4edb-ad8d-8b4d9ec761e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
4212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.118094212
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.43650353
Short name T1221
Test name
Test status
Simulation time 173631392 ps
CPU time 0.82 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206880 kb
Host smart-653ed846-ae18-4585-ac65-36bdfb766439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43650
353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.43650353
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.636469181
Short name T1377
Test name
Test status
Simulation time 23356429946 ps
CPU time 23.4 seconds
Started Jul 16 06:52:43 PM PDT 24
Finished Jul 16 06:53:09 PM PDT 24
Peak memory 206892 kb
Host smart-45962e47-a979-4bb6-a9d2-70e88249e62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63646
9181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.636469181
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2657746552
Short name T1442
Test name
Test status
Simulation time 3279122948 ps
CPU time 3.84 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:52:49 PM PDT 24
Peak memory 206944 kb
Host smart-e725b474-9d58-480c-8a76-2586e1f35b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26577
46552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2657746552
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1311123010
Short name T1856
Test name
Test status
Simulation time 5989901392 ps
CPU time 45.25 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 207144 kb
Host smart-5bf62999-e6e8-447b-9321-a5200a7f68df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13111
23010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1311123010
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3668530466
Short name T2558
Test name
Test status
Simulation time 5997491484 ps
CPU time 165.29 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:55:23 PM PDT 24
Peak memory 207000 kb
Host smart-a6d5c87c-ddcb-4d3c-bb69-c5ee7742ffdd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3668530466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3668530466
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2063098410
Short name T1618
Test name
Test status
Simulation time 298526214 ps
CPU time 0.99 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206808 kb
Host smart-bc3f8191-0db3-4f14-afd0-831eaa9178ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2063098410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2063098410
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3381312758
Short name T1974
Test name
Test status
Simulation time 191321001 ps
CPU time 0.86 seconds
Started Jul 16 06:52:42 PM PDT 24
Finished Jul 16 06:52:46 PM PDT 24
Peak memory 206880 kb
Host smart-e47c8b17-8727-476d-821b-694830925edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813
12758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3381312758
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2700975970
Short name T1983
Test name
Test status
Simulation time 4389969517 ps
CPU time 123.86 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:54:42 PM PDT 24
Peak memory 207084 kb
Host smart-766e7769-38dc-4380-8860-b0882984df78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27009
75970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2700975970
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1824275735
Short name T2217
Test name
Test status
Simulation time 2779433782 ps
CPU time 76.08 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:54:00 PM PDT 24
Peak memory 206844 kb
Host smart-f8d7a670-a49a-498e-94d2-bdca7ec3d38a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1824275735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1824275735
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2540779703
Short name T234
Test name
Test status
Simulation time 174271094 ps
CPU time 0.79 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:41 PM PDT 24
Peak memory 206736 kb
Host smart-73cc4624-f35d-4c85-b319-73012f1cd54a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2540779703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2540779703
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1255300531
Short name T1349
Test name
Test status
Simulation time 199822256 ps
CPU time 0.82 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:42 PM PDT 24
Peak memory 206856 kb
Host smart-b9e6faf6-bebb-40f7-97c4-2457932a1974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
00531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1255300531
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.4153923265
Short name T2335
Test name
Test status
Simulation time 273396955 ps
CPU time 0.92 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206880 kb
Host smart-7535ec26-a490-42a8-a356-2cf69448b67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41539
23265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.4153923265
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1852203252
Short name T2249
Test name
Test status
Simulation time 174040873 ps
CPU time 0.82 seconds
Started Jul 16 06:52:42 PM PDT 24
Finished Jul 16 06:52:46 PM PDT 24
Peak memory 206908 kb
Host smart-1ce22664-2863-44c1-9f76-290ce069851e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18522
03252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1852203252
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1680848677
Short name T2277
Test name
Test status
Simulation time 234744300 ps
CPU time 0.85 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206888 kb
Host smart-337d9406-eda4-44da-8c83-6679c2632556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16808
48677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1680848677
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.902216995
Short name T2510
Test name
Test status
Simulation time 207357050 ps
CPU time 0.83 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:42 PM PDT 24
Peak memory 206852 kb
Host smart-d29a865b-f494-4384-8059-217dbd1a6853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90221
6995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.902216995
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.581455006
Short name T2119
Test name
Test status
Simulation time 162153755 ps
CPU time 0.81 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:41 PM PDT 24
Peak memory 206768 kb
Host smart-3b911353-a15c-4417-81bb-4f2184e12cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58145
5006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.581455006
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1844391056
Short name T2336
Test name
Test status
Simulation time 239570760 ps
CPU time 0.93 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206864 kb
Host smart-ffd908ce-5ede-4ecb-8b30-7d0220b79fa6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1844391056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1844391056
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3975309034
Short name T1216
Test name
Test status
Simulation time 145750217 ps
CPU time 0.79 seconds
Started Jul 16 06:52:36 PM PDT 24
Finished Jul 16 06:52:39 PM PDT 24
Peak memory 206864 kb
Host smart-74464ee1-3920-4574-850d-754c1497ccde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39753
09034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3975309034
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3166470786
Short name T1667
Test name
Test status
Simulation time 52314203 ps
CPU time 0.68 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206604 kb
Host smart-e0b44b12-12e5-4e56-b75d-9679f60a8017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31664
70786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3166470786
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2695168503
Short name T1244
Test name
Test status
Simulation time 6580238640 ps
CPU time 15.32 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:56 PM PDT 24
Peak memory 207088 kb
Host smart-e984ce58-c208-4d41-b4e3-c8e7666a72f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26951
68503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2695168503
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1423390414
Short name T914
Test name
Test status
Simulation time 160070057 ps
CPU time 0.82 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206832 kb
Host smart-6d718d69-78b4-4527-9eb9-a7d6974cbdb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14233
90414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1423390414
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2348095501
Short name T813
Test name
Test status
Simulation time 242652630 ps
CPU time 0.9 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:41 PM PDT 24
Peak memory 206772 kb
Host smart-b0d09244-40da-4965-8379-80941eda2451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23480
95501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2348095501
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.618757591
Short name T2361
Test name
Test status
Simulation time 164042132 ps
CPU time 0.84 seconds
Started Jul 16 06:52:35 PM PDT 24
Finished Jul 16 06:52:37 PM PDT 24
Peak memory 206908 kb
Host smart-905fbdc3-e022-4780-a070-c0bd35c36efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61875
7591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.618757591
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.613306432
Short name T478
Test name
Test status
Simulation time 192662775 ps
CPU time 0.84 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:40 PM PDT 24
Peak memory 206860 kb
Host smart-abce832c-5608-4183-a702-13e814cbb3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61330
6432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.613306432
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2421999877
Short name T2002
Test name
Test status
Simulation time 201716602 ps
CPU time 0.81 seconds
Started Jul 16 06:52:43 PM PDT 24
Finished Jul 16 06:52:47 PM PDT 24
Peak memory 206828 kb
Host smart-b7b7a59b-6aab-405d-b494-f28f431e8c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24219
99877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2421999877
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.969253665
Short name T535
Test name
Test status
Simulation time 150479910 ps
CPU time 0.85 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:52:46 PM PDT 24
Peak memory 206812 kb
Host smart-6ac5c455-beb4-4cc0-9d9c-c51c6691aaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96925
3665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.969253665
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1168958790
Short name T532
Test name
Test status
Simulation time 152481266 ps
CPU time 0.85 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:39 PM PDT 24
Peak memory 206856 kb
Host smart-57ffc087-703c-4917-a32e-2b55d64d4619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11689
58790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1168958790
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3931741643
Short name T2405
Test name
Test status
Simulation time 199733885 ps
CPU time 0.87 seconds
Started Jul 16 06:52:39 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206848 kb
Host smart-e7a36df5-f8cd-446f-83fd-42dbc15f4c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39317
41643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3931741643
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.777782270
Short name T1798
Test name
Test status
Simulation time 3720702834 ps
CPU time 26.45 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:53:11 PM PDT 24
Peak memory 207104 kb
Host smart-23ced214-f43a-472b-a82a-cfdc4734fa8d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=777782270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.777782270
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2939686339
Short name T633
Test name
Test status
Simulation time 187884420 ps
CPU time 0.9 seconds
Started Jul 16 06:52:31 PM PDT 24
Finished Jul 16 06:52:36 PM PDT 24
Peak memory 206864 kb
Host smart-f3075653-c7b7-42ae-b0ca-29c54c910366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29396
86339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2939686339
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3608823642
Short name T346
Test name
Test status
Simulation time 155162445 ps
CPU time 0.79 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206908 kb
Host smart-1354e2e9-2ff0-479a-91bd-622a1098c116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36088
23642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3608823642
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.546647000
Short name T345
Test name
Test status
Simulation time 204257581 ps
CPU time 0.83 seconds
Started Jul 16 06:52:39 PM PDT 24
Finished Jul 16 06:52:44 PM PDT 24
Peak memory 206852 kb
Host smart-96f90430-e843-47dd-8215-7c4fedb113c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54664
7000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.546647000
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1406876978
Short name T881
Test name
Test status
Simulation time 3391460222 ps
CPU time 23.04 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:53:08 PM PDT 24
Peak memory 207104 kb
Host smart-bc3cf0f7-3b9e-485e-a929-12a4ff39e156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14068
76978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1406876978
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.4275467839
Short name T175
Test name
Test status
Simulation time 50667615 ps
CPU time 0.72 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:53 PM PDT 24
Peak memory 206900 kb
Host smart-cefe22f7-eacb-4340-8d60-b3bffd0b3b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4275467839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.4275467839
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.3970677105
Short name T2539
Test name
Test status
Simulation time 3833488729 ps
CPU time 4.53 seconds
Started Jul 16 06:52:42 PM PDT 24
Finished Jul 16 06:52:50 PM PDT 24
Peak memory 207152 kb
Host smart-fcae4059-aa35-48af-86e7-8e40cf272702
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3970677105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.3970677105
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2251263636
Short name T2531
Test name
Test status
Simulation time 13333857834 ps
CPU time 15.31 seconds
Started Jul 16 06:52:42 PM PDT 24
Finished Jul 16 06:53:01 PM PDT 24
Peak memory 206944 kb
Host smart-13c0c846-d3d4-40e4-a43b-6eaa11be29b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2251263636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2251263636
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2211377572
Short name T869
Test name
Test status
Simulation time 23451252147 ps
CPU time 22.97 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 207068 kb
Host smart-ab556f62-63cc-40a4-81bd-0d7829a080fa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2211377572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2211377572
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1602722278
Short name T641
Test name
Test status
Simulation time 147833477 ps
CPU time 0.8 seconds
Started Jul 16 06:52:39 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206816 kb
Host smart-a1b01a1d-5c92-4f28-8279-ceb78a20e074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16027
22278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1602722278
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1286799130
Short name T1671
Test name
Test status
Simulation time 185579375 ps
CPU time 0.88 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:41 PM PDT 24
Peak memory 206732 kb
Host smart-9bc90aeb-14d9-4849-9f8a-92aae65478f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12867
99130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1286799130
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.592974514
Short name T595
Test name
Test status
Simulation time 306800887 ps
CPU time 1.24 seconds
Started Jul 16 06:52:39 PM PDT 24
Finished Jul 16 06:52:44 PM PDT 24
Peak memory 206816 kb
Host smart-6d4f4c96-1def-4ec4-b392-bd5adce8aef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59297
4514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.592974514
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.541631454
Short name T505
Test name
Test status
Simulation time 1419635607 ps
CPU time 3.08 seconds
Started Jul 16 06:52:42 PM PDT 24
Finished Jul 16 06:52:48 PM PDT 24
Peak memory 207072 kb
Host smart-befa0bbd-4cf7-4688-93a7-89061971a9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54163
1454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.541631454
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3076064446
Short name T86
Test name
Test status
Simulation time 10012052207 ps
CPU time 17.47 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:53:01 PM PDT 24
Peak memory 207040 kb
Host smart-938d5e14-8f2a-429b-8135-d28e186c370d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760
64446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3076064446
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.351561992
Short name T324
Test name
Test status
Simulation time 496519792 ps
CPU time 1.42 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206880 kb
Host smart-47ac1c69-d881-4918-b112-9bbeec506f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35156
1992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.351561992
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2952311563
Short name T2619
Test name
Test status
Simulation time 140202279 ps
CPU time 0.74 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:41 PM PDT 24
Peak memory 206876 kb
Host smart-e5cfc9ee-0968-4383-9347-205d49979aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
11563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2952311563
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2008753759
Short name T2093
Test name
Test status
Simulation time 39686204 ps
CPU time 0.65 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206864 kb
Host smart-26637a31-00e2-4c67-898e-cc8d982f714a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20087
53759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2008753759
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3175850473
Short name T2206
Test name
Test status
Simulation time 1029220923 ps
CPU time 2.34 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:52:47 PM PDT 24
Peak memory 206996 kb
Host smart-f2d25c25-69ce-4f4b-9287-4c40801b7fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31758
50473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3175850473
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.98669067
Short name T910
Test name
Test status
Simulation time 307904834 ps
CPU time 1.94 seconds
Started Jul 16 06:52:41 PM PDT 24
Finished Jul 16 06:52:47 PM PDT 24
Peak memory 207008 kb
Host smart-898764d9-d064-4a73-91be-f51c3f77ffae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98669
067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.98669067
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2771032337
Short name T1913
Test name
Test status
Simulation time 187795551 ps
CPU time 0.83 seconds
Started Jul 16 06:52:42 PM PDT 24
Finished Jul 16 06:52:46 PM PDT 24
Peak memory 206868 kb
Host smart-b843ea2d-33d7-4c90-b4bb-20cae98081f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
32337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2771032337
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3567528927
Short name T1048
Test name
Test status
Simulation time 150700906 ps
CPU time 0.73 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206864 kb
Host smart-b8a6bc5e-a4c8-4bd9-87ee-093914916517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
28927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3567528927
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.4262720111
Short name T780
Test name
Test status
Simulation time 230269976 ps
CPU time 0.94 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206888 kb
Host smart-8906eee3-576e-43cb-af66-e3f0b9f525f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42627
20111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4262720111
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.2442638360
Short name T2059
Test name
Test status
Simulation time 7909728659 ps
CPU time 24.05 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:53:06 PM PDT 24
Peak memory 206984 kb
Host smart-62f71046-47c5-4cfa-8ef7-e419008a4b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24426
38360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.2442638360
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2437231960
Short name T523
Test name
Test status
Simulation time 203070412 ps
CPU time 0.84 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:52:45 PM PDT 24
Peak memory 206868 kb
Host smart-95352f99-9235-4edd-bbdc-f0fc717a507f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24372
31960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2437231960
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1719329070
Short name T2130
Test name
Test status
Simulation time 23335431406 ps
CPU time 24.05 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:53:08 PM PDT 24
Peak memory 206932 kb
Host smart-dafdd670-284d-477b-99b9-45ced6fd56c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17193
29070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1719329070
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3803183675
Short name T1310
Test name
Test status
Simulation time 3302266523 ps
CPU time 3.84 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:52:47 PM PDT 24
Peak memory 206948 kb
Host smart-a865d4b2-585c-4006-8c01-6cd112b48a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38031
83675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3803183675
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1326117272
Short name T1044
Test name
Test status
Simulation time 8484422959 ps
CPU time 83.42 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 207008 kb
Host smart-9e91a114-0fe5-4f5d-a54b-b2867f7af06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13261
17272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1326117272
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.255803714
Short name T916
Test name
Test status
Simulation time 5354803985 ps
CPU time 143.98 seconds
Started Jul 16 06:52:40 PM PDT 24
Finished Jul 16 06:55:08 PM PDT 24
Peak memory 207064 kb
Host smart-780091fd-f5da-43cd-8044-537424fb6323
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=255803714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.255803714
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1121157634
Short name T2560
Test name
Test status
Simulation time 240450347 ps
CPU time 0.95 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:52:40 PM PDT 24
Peak memory 206752 kb
Host smart-06787bc7-f0b0-4437-90bb-06bb91e11b65
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1121157634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1121157634
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2385883117
Short name T785
Test name
Test status
Simulation time 229815381 ps
CPU time 0.88 seconds
Started Jul 16 06:52:38 PM PDT 24
Finished Jul 16 06:52:43 PM PDT 24
Peak memory 206868 kb
Host smart-56186404-979d-4b0a-87fa-d11aa9069078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23858
83117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2385883117
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.1687240159
Short name T2331
Test name
Test status
Simulation time 7071994290 ps
CPU time 186.54 seconds
Started Jul 16 06:52:37 PM PDT 24
Finished Jul 16 06:55:45 PM PDT 24
Peak memory 206964 kb
Host smart-db04408a-02c4-4d63-9651-37cea0337123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16872
40159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.1687240159
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3209654329
Short name T1728
Test name
Test status
Simulation time 5975185544 ps
CPU time 164.46 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:55:36 PM PDT 24
Peak memory 206948 kb
Host smart-e8d36ef3-31a5-4aa2-8d53-8ccad63a97f9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3209654329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3209654329
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.152484994
Short name T1169
Test name
Test status
Simulation time 153874691 ps
CPU time 0.84 seconds
Started Jul 16 06:52:48 PM PDT 24
Finished Jul 16 06:52:50 PM PDT 24
Peak memory 206892 kb
Host smart-9ba0cdee-e635-428e-929e-658801989ba2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=152484994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.152484994
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1437290131
Short name T1572
Test name
Test status
Simulation time 147121032 ps
CPU time 0.77 seconds
Started Jul 16 06:52:53 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206816 kb
Host smart-625ca6f2-85b4-48ec-8fb2-9f131816c100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
90131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1437290131
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3166069845
Short name T112
Test name
Test status
Simulation time 193810441 ps
CPU time 0.79 seconds
Started Jul 16 06:52:55 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206776 kb
Host smart-5c00371b-c6d9-48b0-aebb-c9acb131e991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660
69845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3166069845
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3056491056
Short name T1653
Test name
Test status
Simulation time 146540767 ps
CPU time 0.81 seconds
Started Jul 16 06:52:55 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206836 kb
Host smart-024e95fa-26bc-44d8-9569-fff253a97703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
91056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3056491056
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.662247697
Short name T2061
Test name
Test status
Simulation time 183850720 ps
CPU time 0.84 seconds
Started Jul 16 06:52:52 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206860 kb
Host smart-1a14315b-3579-4b1b-810f-30fd23f7577e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66224
7697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.662247697
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3182722526
Short name T755
Test name
Test status
Simulation time 221195410 ps
CPU time 0.85 seconds
Started Jul 16 06:52:51 PM PDT 24
Finished Jul 16 06:52:54 PM PDT 24
Peak memory 206836 kb
Host smart-ac38a229-a166-4131-a1bd-57b4b12f01b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31827
22526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3182722526
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.382502728
Short name T581
Test name
Test status
Simulation time 160610895 ps
CPU time 0.75 seconds
Started Jul 16 06:52:51 PM PDT 24
Finished Jul 16 06:52:54 PM PDT 24
Peak memory 206860 kb
Host smart-382481f2-ebc2-4c6a-bb6b-559e3971921e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38250
2728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.382502728
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.914969864
Short name T2
Test name
Test status
Simulation time 186804863 ps
CPU time 0.85 seconds
Started Jul 16 06:52:49 PM PDT 24
Finished Jul 16 06:52:51 PM PDT 24
Peak memory 206888 kb
Host smart-e27bf52b-764b-4597-8a59-7f89393afd55
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=914969864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.914969864
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2928477928
Short name T180
Test name
Test status
Simulation time 193619261 ps
CPU time 0.83 seconds
Started Jul 16 06:52:56 PM PDT 24
Finished Jul 16 06:52:58 PM PDT 24
Peak memory 206904 kb
Host smart-ba96a434-1c13-469f-9d1e-561ed0e3bdf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29284
77928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2928477928
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3392662975
Short name T833
Test name
Test status
Simulation time 54881738 ps
CPU time 0.67 seconds
Started Jul 16 06:53:00 PM PDT 24
Finished Jul 16 06:53:01 PM PDT 24
Peak memory 206808 kb
Host smart-31de1d7d-a774-4641-9fe8-eaf2ec976a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33926
62975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3392662975
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1939253939
Short name T242
Test name
Test status
Simulation time 18611320865 ps
CPU time 39.96 seconds
Started Jul 16 06:52:53 PM PDT 24
Finished Jul 16 06:53:35 PM PDT 24
Peak memory 207152 kb
Host smart-22176b87-7601-4ed2-b921-6df890667aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19392
53939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1939253939
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1456565878
Short name T905
Test name
Test status
Simulation time 160914323 ps
CPU time 0.8 seconds
Started Jul 16 06:52:52 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206880 kb
Host smart-3028a9bc-b0cd-421b-a7b7-1fdbf1835160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14565
65878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1456565878
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.532138402
Short name T2337
Test name
Test status
Simulation time 237298428 ps
CPU time 0.94 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:53 PM PDT 24
Peak memory 206748 kb
Host smart-78ee2aac-054a-4314-b14e-3e978d198f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53213
8402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.532138402
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.738489664
Short name T2386
Test name
Test status
Simulation time 236281498 ps
CPU time 0.88 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:53 PM PDT 24
Peak memory 206884 kb
Host smart-f5c3e552-c66a-4ec9-b2c6-ee8187801118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73848
9664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.738489664
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1348953300
Short name T1826
Test name
Test status
Simulation time 214212187 ps
CPU time 0.88 seconds
Started Jul 16 06:52:51 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206780 kb
Host smart-30e9d674-056b-4f5e-8297-c8f088bc4e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489
53300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1348953300
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.498605279
Short name T1485
Test name
Test status
Simulation time 185182120 ps
CPU time 0.78 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:53 PM PDT 24
Peak memory 206648 kb
Host smart-031e7718-6bc6-4d23-b194-6b49d401383c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49860
5279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.498605279
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2885469592
Short name T1012
Test name
Test status
Simulation time 152573991 ps
CPU time 0.77 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:54 PM PDT 24
Peak memory 206724 kb
Host smart-70a61374-5929-461d-ab66-440732d76591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28854
69592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2885469592
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2589990394
Short name T1555
Test name
Test status
Simulation time 148099045 ps
CPU time 0.78 seconds
Started Jul 16 06:52:49 PM PDT 24
Finished Jul 16 06:52:51 PM PDT 24
Peak memory 206872 kb
Host smart-ec2d5b07-11f5-4329-bbff-e8c7eaffaa22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25899
90394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2589990394
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1795183860
Short name T1752
Test name
Test status
Simulation time 237902818 ps
CPU time 0.97 seconds
Started Jul 16 06:53:00 PM PDT 24
Finished Jul 16 06:53:02 PM PDT 24
Peak memory 206828 kb
Host smart-3be07598-baac-44d7-958a-a1fad1179ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17951
83860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1795183860
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3401160447
Short name T2124
Test name
Test status
Simulation time 6303609668 ps
CPU time 63.4 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:53:56 PM PDT 24
Peak memory 207092 kb
Host smart-4281509b-dc32-4eb5-a84d-7e7f388ff362
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3401160447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3401160447
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.889117766
Short name T435
Test name
Test status
Simulation time 186384597 ps
CPU time 0.82 seconds
Started Jul 16 06:52:53 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206856 kb
Host smart-9a060f1b-6562-4144-92a0-e47faa885bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88911
7766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.889117766
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1750084706
Short name T1595
Test name
Test status
Simulation time 187920960 ps
CPU time 0.76 seconds
Started Jul 16 06:52:56 PM PDT 24
Finished Jul 16 06:52:59 PM PDT 24
Peak memory 206772 kb
Host smart-e5f42482-e7d6-44ad-a6f8-0968329172b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17500
84706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1750084706
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1010987411
Short name T1102
Test name
Test status
Simulation time 336138538 ps
CPU time 1.14 seconds
Started Jul 16 06:52:53 PM PDT 24
Finished Jul 16 06:52:56 PM PDT 24
Peak memory 206816 kb
Host smart-649cbb88-3ebf-443b-8ae4-ac0b8fd77af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10109
87411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1010987411
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.46597539
Short name T1614
Test name
Test status
Simulation time 3945193273 ps
CPU time 106.71 seconds
Started Jul 16 06:52:56 PM PDT 24
Finished Jul 16 06:54:44 PM PDT 24
Peak memory 206964 kb
Host smart-3b83cb44-42fe-4daf-bc3c-5cec23b7be75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46597
539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.46597539
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2539796979
Short name T1160
Test name
Test status
Simulation time 47933679 ps
CPU time 0.64 seconds
Started Jul 16 06:47:59 PM PDT 24
Finished Jul 16 06:48:01 PM PDT 24
Peak memory 206900 kb
Host smart-15706267-62fc-4c5d-b497-45e66e3fc70b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2539796979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2539796979
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3820152989
Short name T696
Test name
Test status
Simulation time 3878416533 ps
CPU time 4.62 seconds
Started Jul 16 06:47:44 PM PDT 24
Finished Jul 16 06:47:50 PM PDT 24
Peak memory 206960 kb
Host smart-24f7abdd-ceb9-42a1-8ffc-c05107e3f0a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3820152989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3820152989
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3347483220
Short name T1210
Test name
Test status
Simulation time 13336898453 ps
CPU time 12.74 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:48:01 PM PDT 24
Peak memory 207272 kb
Host smart-122eba32-f91d-4e2d-9b3f-c1bd121687ad
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3347483220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3347483220
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.267934558
Short name T605
Test name
Test status
Simulation time 23460545356 ps
CPU time 22.34 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:48:13 PM PDT 24
Peak memory 206820 kb
Host smart-deeb511f-6118-4003-b536-a377673764b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=267934558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.267934558
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.398180835
Short name T2279
Test name
Test status
Simulation time 188135088 ps
CPU time 0.81 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:51 PM PDT 24
Peak memory 206804 kb
Host smart-49435dcb-f243-4c58-9ee1-6ac3661fb524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
0835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.398180835
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3458140792
Short name T2195
Test name
Test status
Simulation time 166248030 ps
CPU time 0.83 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206588 kb
Host smart-28a3473e-9ac7-406b-8a41-133d7e3c0325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34581
40792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3458140792
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2359960056
Short name T81
Test name
Test status
Simulation time 197625383 ps
CPU time 0.85 seconds
Started Jul 16 06:47:43 PM PDT 24
Finished Jul 16 06:47:45 PM PDT 24
Peak memory 206868 kb
Host smart-83bd381e-f352-41e2-9c64-10d6cf01fc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23599
60056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2359960056
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.954013580
Short name T1971
Test name
Test status
Simulation time 163838748 ps
CPU time 0.76 seconds
Started Jul 16 06:47:44 PM PDT 24
Finished Jul 16 06:47:45 PM PDT 24
Peak memory 206828 kb
Host smart-e75e657b-8bcf-406a-9a3e-8a54bd7ab3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95401
3580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.954013580
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2558193430
Short name T1766
Test name
Test status
Simulation time 326414626 ps
CPU time 1.17 seconds
Started Jul 16 06:47:44 PM PDT 24
Finished Jul 16 06:47:47 PM PDT 24
Peak memory 206884 kb
Host smart-877c4a23-cb48-4fc1-9764-51b376d34e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25581
93430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2558193430
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2472819997
Short name T351
Test name
Test status
Simulation time 1290757497 ps
CPU time 3.09 seconds
Started Jul 16 06:47:43 PM PDT 24
Finished Jul 16 06:47:47 PM PDT 24
Peak memory 206940 kb
Host smart-77c19959-7366-4ccc-af54-58ce9e4b2df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24728
19997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2472819997
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.687495647
Short name T160
Test name
Test status
Simulation time 5871420845 ps
CPU time 10.14 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:48:01 PM PDT 24
Peak memory 207072 kb
Host smart-b6d37546-fed6-43e3-84e4-555b59f20633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68749
5647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.687495647
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.1797513646
Short name T2015
Test name
Test status
Simulation time 364587717 ps
CPU time 1.12 seconds
Started Jul 16 06:47:45 PM PDT 24
Finished Jul 16 06:47:48 PM PDT 24
Peak memory 206856 kb
Host smart-7a94a239-95aa-4cd5-81d6-844038602f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17975
13646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.1797513646
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1946921561
Short name T446
Test name
Test status
Simulation time 148334871 ps
CPU time 0.78 seconds
Started Jul 16 06:47:47 PM PDT 24
Finished Jul 16 06:47:50 PM PDT 24
Peak memory 206876 kb
Host smart-a4bb94f1-cf8b-424c-be02-e43ea173fcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19469
21561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1946921561
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3457004889
Short name T1815
Test name
Test status
Simulation time 81026473 ps
CPU time 0.7 seconds
Started Jul 16 06:47:49 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206768 kb
Host smart-70eb4836-8405-4303-a5c7-a5cb6459f1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
04889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3457004889
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2611887842
Short name T999
Test name
Test status
Simulation time 861719180 ps
CPU time 2.09 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:53 PM PDT 24
Peak memory 206956 kb
Host smart-70ca40e2-c2d1-4ae7-90db-c01fd94515b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
87842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2611887842
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1600669785
Short name T1038
Test name
Test status
Simulation time 198974727 ps
CPU time 1.82 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:50 PM PDT 24
Peak memory 206944 kb
Host smart-f9d4707e-a39c-453d-894f-21ac9ea35100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16006
69785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1600669785
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3738289351
Short name T1825
Test name
Test status
Simulation time 117197191086 ps
CPU time 186.22 seconds
Started Jul 16 06:47:47 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 207092 kb
Host smart-bb34c6f5-5a53-41fa-8f17-15f5897357df
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3738289351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3738289351
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.1998929803
Short name T487
Test name
Test status
Simulation time 100297563229 ps
CPU time 139.94 seconds
Started Jul 16 06:47:45 PM PDT 24
Finished Jul 16 06:50:06 PM PDT 24
Peak memory 207144 kb
Host smart-1e399e80-ab67-4137-b3cc-48163dbb205b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998929803 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.1998929803
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.4018478411
Short name T996
Test name
Test status
Simulation time 82119864639 ps
CPU time 105.48 seconds
Started Jul 16 06:47:44 PM PDT 24
Finished Jul 16 06:49:30 PM PDT 24
Peak memory 207044 kb
Host smart-0478e816-1359-46f3-b0f3-fcf0e9205a70
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4018478411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.4018478411
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2827100024
Short name T496
Test name
Test status
Simulation time 86149258806 ps
CPU time 116.94 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:49:48 PM PDT 24
Peak memory 206836 kb
Host smart-4c4c2dc5-e77a-450d-bf86-74f73ca3cb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827100024 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2827100024
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.1552370322
Short name T2591
Test name
Test status
Simulation time 92161902249 ps
CPU time 127.52 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:49:58 PM PDT 24
Peak memory 207068 kb
Host smart-cfeb70e5-e294-42f4-bffb-178c96fb7508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15523
70322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.1552370322
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.867700875
Short name T1956
Test name
Test status
Simulation time 231587316 ps
CPU time 0.92 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:51 PM PDT 24
Peak memory 206744 kb
Host smart-afa2cda4-9246-4322-9f06-6fa844d4a8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86770
0875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.867700875
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1798219712
Short name T369
Test name
Test status
Simulation time 151743266 ps
CPU time 0.77 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:49 PM PDT 24
Peak memory 206740 kb
Host smart-7a33247a-e703-4f72-bd44-715693efb97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17982
19712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1798219712
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2532740387
Short name T1935
Test name
Test status
Simulation time 175713711 ps
CPU time 0.84 seconds
Started Jul 16 06:47:49 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206772 kb
Host smart-08de2c40-7ab9-47ed-a39e-e4cec0de1ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25327
40387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2532740387
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3392585154
Short name T1241
Test name
Test status
Simulation time 6708569380 ps
CPU time 186.16 seconds
Started Jul 16 06:47:44 PM PDT 24
Finished Jul 16 06:50:52 PM PDT 24
Peak memory 207120 kb
Host smart-4276efd5-fcec-4894-a82e-4ffe71739cc3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3392585154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3392585154
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.138293109
Short name T1727
Test name
Test status
Simulation time 11343928469 ps
CPU time 104.32 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:49:35 PM PDT 24
Peak memory 207100 kb
Host smart-2429f75d-0720-4215-9ae0-bd640fcb0183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
3109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.138293109
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3758340357
Short name T566
Test name
Test status
Simulation time 163866126 ps
CPU time 0.78 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:51 PM PDT 24
Peak memory 206736 kb
Host smart-65a32f09-9313-4b25-abdd-7c5f90e974dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37583
40357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3758340357
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1246325605
Short name T1360
Test name
Test status
Simulation time 23282130562 ps
CPU time 23.34 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:48:14 PM PDT 24
Peak memory 206940 kb
Host smart-cb775519-d905-42b6-b68c-cac1bd413364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463
25605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1246325605
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3227420369
Short name T1422
Test name
Test status
Simulation time 3307413101 ps
CPU time 3.74 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:51 PM PDT 24
Peak memory 206920 kb
Host smart-2a346d5c-7b08-40e8-a86a-8c376bc3244e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32274
20369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3227420369
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.4229130944
Short name T1585
Test name
Test status
Simulation time 4722175615 ps
CPU time 125.47 seconds
Started Jul 16 06:47:47 PM PDT 24
Finished Jul 16 06:49:55 PM PDT 24
Peak memory 207008 kb
Host smart-2b3a4a23-5d57-4160-af87-81e0adf03a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42291
30944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.4229130944
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2581393077
Short name T688
Test name
Test status
Simulation time 5008495318 ps
CPU time 36.75 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:48:25 PM PDT 24
Peak memory 207120 kb
Host smart-e887a387-0215-4e05-8c8e-9175a8aa5ff3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2581393077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2581393077
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1182126907
Short name T1072
Test name
Test status
Simulation time 259960306 ps
CPU time 0.94 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:49 PM PDT 24
Peak memory 206856 kb
Host smart-cc5cbdd9-607c-4c18-84f5-f7ab458dc281
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1182126907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1182126907
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3674222769
Short name T901
Test name
Test status
Simulation time 202777871 ps
CPU time 0.91 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:50 PM PDT 24
Peak memory 206864 kb
Host smart-5267f300-76fc-4b7c-8bf5-d1b3451d86ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36742
22769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3674222769
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1271629561
Short name T1537
Test name
Test status
Simulation time 5659806421 ps
CPU time 52.69 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:48:40 PM PDT 24
Peak memory 207068 kb
Host smart-aa8bb60b-2068-43bf-8f1d-abfcc1ba7c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12716
29561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1271629561
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.222272805
Short name T1315
Test name
Test status
Simulation time 6748377218 ps
CPU time 47.92 seconds
Started Jul 16 06:47:44 PM PDT 24
Finished Jul 16 06:48:34 PM PDT 24
Peak memory 207072 kb
Host smart-896f0c58-ce5b-4e25-b2c4-cd91af4a5d8d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=222272805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.222272805
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.4163368833
Short name T1294
Test name
Test status
Simulation time 161708864 ps
CPU time 0.82 seconds
Started Jul 16 06:47:43 PM PDT 24
Finished Jul 16 06:47:44 PM PDT 24
Peak memory 206884 kb
Host smart-10eaadbe-1336-4815-abcd-30ccc6f3d7a5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4163368833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.4163368833
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4034663382
Short name T585
Test name
Test status
Simulation time 144175128 ps
CPU time 0.76 seconds
Started Jul 16 06:47:45 PM PDT 24
Finished Jul 16 06:47:48 PM PDT 24
Peak memory 206856 kb
Host smart-1408bdac-7785-47ac-ae85-6398676030cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40346
63382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4034663382
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.615742967
Short name T120
Test name
Test status
Simulation time 213263546 ps
CPU time 0.94 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:51 PM PDT 24
Peak memory 206880 kb
Host smart-e1916a15-9ba7-412f-85b9-cd6ba0380184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61574
2967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.615742967
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3350601273
Short name T92
Test name
Test status
Simulation time 147462519 ps
CPU time 0.8 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:51 PM PDT 24
Peak memory 206752 kb
Host smart-11b7fa43-8373-4caf-8f49-22cad301bf86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33506
01273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3350601273
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.322148296
Short name T355
Test name
Test status
Simulation time 187482739 ps
CPU time 0.81 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206852 kb
Host smart-3a42c9ab-678a-4b84-b348-e0f35aefbe27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32214
8296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.322148296
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.294491556
Short name T1386
Test name
Test status
Simulation time 145334471 ps
CPU time 0.79 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:50 PM PDT 24
Peak memory 206856 kb
Host smart-db0edc0d-5ed9-4160-a1dc-145bbedecc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29449
1556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.294491556
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.4248666141
Short name T1642
Test name
Test status
Simulation time 223458788 ps
CPU time 0.84 seconds
Started Jul 16 06:47:47 PM PDT 24
Finished Jul 16 06:47:50 PM PDT 24
Peak memory 206860 kb
Host smart-71e65b89-4e27-4e9d-ba59-d02fd48be90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42486
66141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.4248666141
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3247108302
Short name T1196
Test name
Test status
Simulation time 176848797 ps
CPU time 0.84 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:49 PM PDT 24
Peak memory 207004 kb
Host smart-c64316bf-c521-4642-b80f-c4c472f10cd9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3247108302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3247108302
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.4158131138
Short name T444
Test name
Test status
Simulation time 193377064 ps
CPU time 0.86 seconds
Started Jul 16 06:47:45 PM PDT 24
Finished Jul 16 06:47:47 PM PDT 24
Peak memory 207032 kb
Host smart-c4f89591-8196-48e4-a8b2-fb3de10de790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41581
31138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.4158131138
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.50500754
Short name T1881
Test name
Test status
Simulation time 140143111 ps
CPU time 0.81 seconds
Started Jul 16 06:47:49 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206808 kb
Host smart-4d793373-09f2-4325-8495-2d316fccf895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50500
754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.50500754
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.782724908
Short name T792
Test name
Test status
Simulation time 61089978 ps
CPU time 0.72 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:49 PM PDT 24
Peak memory 206856 kb
Host smart-298b8a4d-e520-4f22-98fe-0b1f2ffd7240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78272
4908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.782724908
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1258751720
Short name T1529
Test name
Test status
Simulation time 11323477031 ps
CPU time 27.56 seconds
Started Jul 16 06:47:49 PM PDT 24
Finished Jul 16 06:48:19 PM PDT 24
Peak memory 215252 kb
Host smart-450b834d-4862-4175-93ce-eccb56ee7793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12587
51720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1258751720
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.212955834
Short name T1487
Test name
Test status
Simulation time 223769530 ps
CPU time 0.9 seconds
Started Jul 16 06:47:49 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206828 kb
Host smart-08cf3a78-b058-42cb-becd-82bcc365ea6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21295
5834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.212955834
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.682830864
Short name T845
Test name
Test status
Simulation time 185106169 ps
CPU time 0.88 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:51 PM PDT 24
Peak memory 206856 kb
Host smart-00f42f0a-f828-4e71-85fe-73fbe932bc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68283
0864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.682830864
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.401666761
Short name T159
Test name
Test status
Simulation time 15391853065 ps
CPU time 108.57 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:49:37 PM PDT 24
Peak memory 207064 kb
Host smart-569a9481-7c1f-428e-b9c9-499b0e2705a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=401666761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.401666761
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.905147675
Short name T2693
Test name
Test status
Simulation time 12447746482 ps
CPU time 232.54 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:51:43 PM PDT 24
Peak memory 207176 kb
Host smart-25545c07-38ea-4ead-92ba-f9dbe4348a59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=905147675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.905147675
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2561148060
Short name T1691
Test name
Test status
Simulation time 6663996355 ps
CPU time 30.87 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 207052 kb
Host smart-7af6a9a0-51ad-4e70-b652-75bdf9d173ab
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2561148060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2561148060
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2381850323
Short name T434
Test name
Test status
Simulation time 170890295 ps
CPU time 0.83 seconds
Started Jul 16 06:47:46 PM PDT 24
Finished Jul 16 06:47:49 PM PDT 24
Peak memory 206856 kb
Host smart-54d04b0f-4411-4785-bbc7-747b693b7034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23818
50323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2381850323
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1130804837
Short name T2435
Test name
Test status
Simulation time 206545291 ps
CPU time 0.83 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206840 kb
Host smart-7f518888-1c35-4378-8896-8214b667d5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308
04837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1130804837
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2436848899
Short name T2627
Test name
Test status
Simulation time 204655084 ps
CPU time 0.77 seconds
Started Jul 16 06:47:47 PM PDT 24
Finished Jul 16 06:47:50 PM PDT 24
Peak memory 206876 kb
Host smart-ef83cf5c-73aa-4203-900d-813421216c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24368
48899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2436848899
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.61727061
Short name T1481
Test name
Test status
Simulation time 174603817 ps
CPU time 0.89 seconds
Started Jul 16 06:47:49 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206852 kb
Host smart-705a2e4b-ceaf-4e6b-9954-f0e487c67ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61727
061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.61727061
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2207708974
Short name T202
Test name
Test status
Simulation time 285860922 ps
CPU time 1.11 seconds
Started Jul 16 06:47:59 PM PDT 24
Finished Jul 16 06:48:02 PM PDT 24
Peak memory 224480 kb
Host smart-5a12d110-c287-4e8d-a4d3-8abd2c979a06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2207708974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2207708974
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.796669507
Short name T54
Test name
Test status
Simulation time 510683526 ps
CPU time 1.51 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206832 kb
Host smart-8a7849d8-ecba-4be3-9085-92e9e212f646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79666
9507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.796669507
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.4134495050
Short name T1884
Test name
Test status
Simulation time 217262843 ps
CPU time 0.91 seconds
Started Jul 16 06:47:48 PM PDT 24
Finished Jul 16 06:47:52 PM PDT 24
Peak memory 206832 kb
Host smart-5cc66a4c-5fae-4250-8a31-9850b9ba3e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41344
95050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.4134495050
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.164282141
Short name T2519
Test name
Test status
Simulation time 189679931 ps
CPU time 0.9 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:48:01 PM PDT 24
Peak memory 206656 kb
Host smart-4cc66709-f463-45ce-b1f5-4d9b31faf048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16428
2141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.164282141
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.591195353
Short name T330
Test name
Test status
Simulation time 160495307 ps
CPU time 0.92 seconds
Started Jul 16 06:48:03 PM PDT 24
Finished Jul 16 06:48:04 PM PDT 24
Peak memory 206848 kb
Host smart-2b48fd11-49d9-48b7-8dad-3fffb5934f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59119
5353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.591195353
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2341012772
Short name T823
Test name
Test status
Simulation time 184700055 ps
CPU time 0.86 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:47:59 PM PDT 24
Peak memory 206860 kb
Host smart-5876ef44-37a4-4ef4-a6e4-8502a0b37ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23410
12772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2341012772
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2289428797
Short name T1049
Test name
Test status
Simulation time 5501515813 ps
CPU time 152.69 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:50:31 PM PDT 24
Peak memory 207012 kb
Host smart-82882a32-c9d5-46b2-9a33-d61be5bf6ee5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2289428797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2289428797
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.150316445
Short name T1054
Test name
Test status
Simulation time 162266906 ps
CPU time 0.79 seconds
Started Jul 16 06:48:04 PM PDT 24
Finished Jul 16 06:48:06 PM PDT 24
Peak memory 206752 kb
Host smart-403dcfae-554a-48f1-9080-448be7e9b725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15031
6445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.150316445
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2212175415
Short name T2029
Test name
Test status
Simulation time 174823466 ps
CPU time 0.83 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:47:58 PM PDT 24
Peak memory 206812 kb
Host smart-92ede380-fddd-4c7c-aa51-7a3230fed6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22121
75415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2212175415
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3274073497
Short name T2132
Test name
Test status
Simulation time 208964174 ps
CPU time 0.86 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:47:59 PM PDT 24
Peak memory 206828 kb
Host smart-6798fb79-c94e-4b2f-a1da-236b999ed946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32740
73497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3274073497
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.596803883
Short name T849
Test name
Test status
Simulation time 5986208875 ps
CPU time 172.56 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:50:51 PM PDT 24
Peak memory 207088 kb
Host smart-9d92cbf6-ca5b-4cde-81d7-81dab0f80f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59680
3883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.596803883
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.1098693391
Short name T2528
Test name
Test status
Simulation time 38221815 ps
CPU time 0.68 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:06 PM PDT 24
Peak memory 206908 kb
Host smart-14bf6b0a-5dd1-43fa-b0ed-92644a13c507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1098693391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.1098693391
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.188280002
Short name T8
Test name
Test status
Simulation time 3957372756 ps
CPU time 4.93 seconds
Started Jul 16 06:52:52 PM PDT 24
Finished Jul 16 06:52:59 PM PDT 24
Peak memory 206872 kb
Host smart-5fd4ba9d-cd79-4a48-be4d-a16268224f27
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=188280002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.188280002
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1852362746
Short name T447
Test name
Test status
Simulation time 13328655369 ps
CPU time 15.05 seconds
Started Jul 16 06:52:56 PM PDT 24
Finished Jul 16 06:53:13 PM PDT 24
Peak memory 207044 kb
Host smart-3450549b-ca82-4c1e-857f-7a10666d71e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1852362746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1852362746
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1710934122
Short name T1353
Test name
Test status
Simulation time 23356233563 ps
CPU time 23.94 seconds
Started Jul 16 06:52:58 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 207112 kb
Host smart-4f12e703-75a6-49f5-b925-038871b436f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1710934122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1710934122
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1765695747
Short name T2351
Test name
Test status
Simulation time 192236448 ps
CPU time 0.84 seconds
Started Jul 16 06:53:00 PM PDT 24
Finished Jul 16 06:53:01 PM PDT 24
Peak memory 206832 kb
Host smart-a80c8f6a-f18c-4b46-a960-246563f60380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17656
95747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1765695747
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3176079085
Short name T2166
Test name
Test status
Simulation time 159070291 ps
CPU time 0.78 seconds
Started Jul 16 06:52:49 PM PDT 24
Finished Jul 16 06:52:52 PM PDT 24
Peak memory 206852 kb
Host smart-ac490a10-7d8f-4715-9aa3-307713f3d428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
79085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3176079085
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3150521227
Short name T2712
Test name
Test status
Simulation time 238775060 ps
CPU time 0.92 seconds
Started Jul 16 06:52:56 PM PDT 24
Finished Jul 16 06:52:58 PM PDT 24
Peak memory 206856 kb
Host smart-efeb1964-841f-46bf-ac34-6557cedae86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31505
21227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3150521227
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1695201776
Short name T632
Test name
Test status
Simulation time 685900959 ps
CPU time 1.79 seconds
Started Jul 16 06:52:51 PM PDT 24
Finished Jul 16 06:52:59 PM PDT 24
Peak memory 207004 kb
Host smart-451d8e24-a790-4e91-aca3-caf187c64757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16952
01776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1695201776
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3811757013
Short name T1448
Test name
Test status
Simulation time 22416190429 ps
CPU time 42.29 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:53:34 PM PDT 24
Peak memory 207080 kb
Host smart-f6e3b0ca-a0a2-4142-b579-681b69563efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38117
57013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3811757013
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2367288439
Short name T3
Test name
Test status
Simulation time 448618010 ps
CPU time 1.42 seconds
Started Jul 16 06:52:52 PM PDT 24
Finished Jul 16 06:52:56 PM PDT 24
Peak memory 206880 kb
Host smart-12a93b97-83dd-4fe9-9b36-73abfde283ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23672
88439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2367288439
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2449431843
Short name T2406
Test name
Test status
Simulation time 142865729 ps
CPU time 0.85 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:52 PM PDT 24
Peak memory 206820 kb
Host smart-e262021a-ae78-4617-b5cb-11816a6623a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24494
31843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2449431843
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2840280026
Short name T976
Test name
Test status
Simulation time 40921728 ps
CPU time 0.65 seconds
Started Jul 16 06:52:52 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206872 kb
Host smart-ce9e477d-4de0-4970-b80c-67e029a96e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28402
80026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2840280026
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3713123752
Short name T400
Test name
Test status
Simulation time 840241449 ps
CPU time 1.98 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:54 PM PDT 24
Peak memory 207068 kb
Host smart-a2264aba-9406-4282-a82f-09a8e437ffdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37131
23752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3713123752
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3802169819
Short name T1888
Test name
Test status
Simulation time 245603097 ps
CPU time 2.06 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206948 kb
Host smart-96b69ec2-6c29-4029-bf13-b6f813519f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38021
69819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3802169819
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1910556892
Short name T2083
Test name
Test status
Simulation time 283296994 ps
CPU time 0.97 seconds
Started Jul 16 06:52:51 PM PDT 24
Finished Jul 16 06:52:54 PM PDT 24
Peak memory 206752 kb
Host smart-0eaf44be-3057-42ab-8f9c-a98a9c90340d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
56892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1910556892
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3217488989
Short name T2154
Test name
Test status
Simulation time 145848330 ps
CPU time 0.76 seconds
Started Jul 16 06:52:53 PM PDT 24
Finished Jul 16 06:52:56 PM PDT 24
Peak memory 206860 kb
Host smart-7aea7d80-0a6a-4a59-b7c5-70f6e4fcf3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32174
88989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3217488989
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2780957068
Short name T222
Test name
Test status
Simulation time 290656072 ps
CPU time 0.9 seconds
Started Jul 16 06:52:55 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206888 kb
Host smart-dbb5a0a1-2a57-4991-86ee-99cdbddaf9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27809
57068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2780957068
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.1397049389
Short name T2167
Test name
Test status
Simulation time 6653309985 ps
CPU time 49.11 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:53:42 PM PDT 24
Peak memory 207076 kb
Host smart-6738e51b-4a98-432a-8726-60bcb68deda8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1397049389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.1397049389
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.543002313
Short name T1322
Test name
Test status
Simulation time 7470023374 ps
CPU time 23.63 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:28 PM PDT 24
Peak memory 207016 kb
Host smart-bccc46d6-a5ee-4ab3-affa-272d284c87f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54300
2313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.543002313
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2204436683
Short name T2304
Test name
Test status
Simulation time 199404920 ps
CPU time 0.93 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:52 PM PDT 24
Peak memory 206876 kb
Host smart-47821b00-64e3-4f81-9a78-484b08a4a46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044
36683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2204436683
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2990046987
Short name T851
Test name
Test status
Simulation time 23343326681 ps
CPU time 26.86 seconds
Started Jul 16 06:52:51 PM PDT 24
Finished Jul 16 06:53:21 PM PDT 24
Peak memory 206924 kb
Host smart-2b5b0670-8427-40c4-bf26-dc9c347dcbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29900
46987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2990046987
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2256970983
Short name T2615
Test name
Test status
Simulation time 3311071796 ps
CPU time 4.28 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206916 kb
Host smart-2976d578-95a5-42d2-9d67-e8b68bf4eccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
70983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2256970983
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1040429934
Short name T465
Test name
Test status
Simulation time 12689114157 ps
CPU time 94.03 seconds
Started Jul 16 06:52:52 PM PDT 24
Finished Jul 16 06:54:29 PM PDT 24
Peak memory 207060 kb
Host smart-dffed57f-f409-4756-b42d-e4b394b5cc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10404
29934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1040429934
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.827597748
Short name T1105
Test name
Test status
Simulation time 5344487753 ps
CPU time 38.46 seconds
Started Jul 16 06:52:49 PM PDT 24
Finished Jul 16 06:53:29 PM PDT 24
Peak memory 207112 kb
Host smart-16a30b7c-2513-4446-b29c-b399cd63962d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=827597748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.827597748
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2606494607
Short name T2078
Test name
Test status
Simulation time 243452710 ps
CPU time 0.92 seconds
Started Jul 16 06:52:51 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206752 kb
Host smart-48edd3aa-7776-4b3a-8187-bb98d2790709
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2606494607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2606494607
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3263159164
Short name T2659
Test name
Test status
Simulation time 196220980 ps
CPU time 0.86 seconds
Started Jul 16 06:52:55 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206884 kb
Host smart-03233ace-b4bf-458e-b4c8-8b81459323e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32631
59164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3263159164
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.288026273
Short name T1153
Test name
Test status
Simulation time 3188223200 ps
CPU time 88.93 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:54:21 PM PDT 24
Peak memory 207076 kb
Host smart-37df97df-4acb-40b1-b943-5c8ea6c7927b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28802
6273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.288026273
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3389832810
Short name T328
Test name
Test status
Simulation time 6687611424 ps
CPU time 183.1 seconds
Started Jul 16 06:52:51 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 207052 kb
Host smart-243901dd-1ba4-4fb0-8cf4-9129dfb0a53b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3389832810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3389832810
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3303005577
Short name T2667
Test name
Test status
Simulation time 210376188 ps
CPU time 0.81 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:52:54 PM PDT 24
Peak memory 206888 kb
Host smart-82aa943f-b92c-4b07-a3f4-599f803d572c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3303005577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3303005577
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1832081511
Short name T2595
Test name
Test status
Simulation time 143826293 ps
CPU time 0.82 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:05 PM PDT 24
Peak memory 206828 kb
Host smart-30fc0986-d449-4cb5-872e-a897005a4d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320
81511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1832081511
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3606221970
Short name T1562
Test name
Test status
Simulation time 205018226 ps
CPU time 0.83 seconds
Started Jul 16 06:52:55 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206888 kb
Host smart-48a4024d-0f81-41cb-ae29-bb09e68fa787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36062
21970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3606221970
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3688397640
Short name T1987
Test name
Test status
Simulation time 155266421 ps
CPU time 0.78 seconds
Started Jul 16 06:52:54 PM PDT 24
Finished Jul 16 06:52:56 PM PDT 24
Peak memory 206812 kb
Host smart-4a56bf08-a268-4202-864d-6f67554f45e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36883
97640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3688397640
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.439825670
Short name T1731
Test name
Test status
Simulation time 166976587 ps
CPU time 0.76 seconds
Started Jul 16 06:52:55 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206776 kb
Host smart-bd342390-58dc-4b95-9016-6d6743a5789c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43982
5670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.439825670
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3289559171
Short name T1580
Test name
Test status
Simulation time 221135454 ps
CPU time 0.84 seconds
Started Jul 16 06:52:53 PM PDT 24
Finished Jul 16 06:52:56 PM PDT 24
Peak memory 206840 kb
Host smart-2865bc9a-17a6-4a0d-82ac-57d085d6b4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32895
59171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3289559171
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.230754942
Short name T1014
Test name
Test status
Simulation time 159202251 ps
CPU time 0.8 seconds
Started Jul 16 06:52:56 PM PDT 24
Finished Jul 16 06:52:58 PM PDT 24
Peak memory 206880 kb
Host smart-f2a2b48e-c779-4eb1-afb5-0dc4c711a8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23075
4942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.230754942
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1368520415
Short name T1836
Test name
Test status
Simulation time 240651648 ps
CPU time 0.96 seconds
Started Jul 16 06:53:00 PM PDT 24
Finished Jul 16 06:53:01 PM PDT 24
Peak memory 206828 kb
Host smart-3fa76308-d9b3-4685-95de-155354364572
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1368520415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1368520415
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3654116396
Short name T1339
Test name
Test status
Simulation time 143497317 ps
CPU time 0.77 seconds
Started Jul 16 06:52:53 PM PDT 24
Finished Jul 16 06:52:55 PM PDT 24
Peak memory 206812 kb
Host smart-261efca8-5fb4-42ab-b8f1-fb51d52a445b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36541
16396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3654116396
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.569273746
Short name T1549
Test name
Test status
Simulation time 33519120 ps
CPU time 0.65 seconds
Started Jul 16 06:52:56 PM PDT 24
Finished Jul 16 06:52:58 PM PDT 24
Peak memory 206856 kb
Host smart-e56c4ebd-f80f-4a53-a56f-3445120da111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56927
3746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.569273746
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.704573235
Short name T676
Test name
Test status
Simulation time 9707180399 ps
CPU time 20.6 seconds
Started Jul 16 06:52:50 PM PDT 24
Finished Jul 16 06:53:13 PM PDT 24
Peak memory 207088 kb
Host smart-c6d190e7-6867-4027-bbed-49799b3f7746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70457
3235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.704573235
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2089453778
Short name T1551
Test name
Test status
Simulation time 144928477 ps
CPU time 0.74 seconds
Started Jul 16 06:52:55 PM PDT 24
Finished Jul 16 06:52:57 PM PDT 24
Peak memory 206840 kb
Host smart-29acabd0-d90c-4857-8852-95c58caf08bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20894
53778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2089453778
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2149858358
Short name T492
Test name
Test status
Simulation time 212486134 ps
CPU time 0.89 seconds
Started Jul 16 06:53:07 PM PDT 24
Finished Jul 16 06:53:10 PM PDT 24
Peak memory 206860 kb
Host smart-d067a900-51a4-4991-b51f-0248eb19a962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21498
58358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2149858358
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3024912694
Short name T1736
Test name
Test status
Simulation time 201621875 ps
CPU time 0.83 seconds
Started Jul 16 06:53:12 PM PDT 24
Finished Jul 16 06:53:14 PM PDT 24
Peak memory 206880 kb
Host smart-bf2e0146-3038-4dd6-9d6d-f844dd957ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30249
12694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3024912694
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.554946188
Short name T1456
Test name
Test status
Simulation time 180303057 ps
CPU time 0.82 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:04 PM PDT 24
Peak memory 206884 kb
Host smart-df4105e6-46c5-456d-ba9e-923838353928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55494
6188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.554946188
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1191686558
Short name T457
Test name
Test status
Simulation time 162190511 ps
CPU time 0.8 seconds
Started Jul 16 06:53:09 PM PDT 24
Finished Jul 16 06:53:12 PM PDT 24
Peak memory 206888 kb
Host smart-412a2848-1dca-48b8-b569-d209758ce252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916
86558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1191686558
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3380103976
Short name T1770
Test name
Test status
Simulation time 154639315 ps
CPU time 0.77 seconds
Started Jul 16 06:53:07 PM PDT 24
Finished Jul 16 06:53:15 PM PDT 24
Peak memory 206744 kb
Host smart-df60320c-00d4-456a-925d-c2c55365f938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33801
03976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3380103976
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2251121976
Short name T2153
Test name
Test status
Simulation time 149966718 ps
CPU time 0.84 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 206860 kb
Host smart-edae17ab-7f2d-4093-a7b9-973247b80ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22511
21976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2251121976
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1407332938
Short name T1914
Test name
Test status
Simulation time 189498095 ps
CPU time 0.86 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 206748 kb
Host smart-74c9c4b0-1416-4ace-87c1-c48beb801784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
32938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1407332938
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.923125751
Short name T2127
Test name
Test status
Simulation time 3371455145 ps
CPU time 23.83 seconds
Started Jul 16 06:53:01 PM PDT 24
Finished Jul 16 06:53:26 PM PDT 24
Peak memory 207116 kb
Host smart-7ddf9d66-6224-4abf-a29f-54754a34f463
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=923125751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.923125751
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3337096086
Short name T678
Test name
Test status
Simulation time 174253231 ps
CPU time 0.8 seconds
Started Jul 16 06:53:09 PM PDT 24
Finished Jul 16 06:53:12 PM PDT 24
Peak memory 206896 kb
Host smart-74e58323-63a3-4a43-bee8-1d09c67afe38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33370
96086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3337096086
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.152847595
Short name T1168
Test name
Test status
Simulation time 163955000 ps
CPU time 0.81 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:06 PM PDT 24
Peak memory 206872 kb
Host smart-d827021d-20bf-4696-bf35-6533bee6a638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15284
7595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.152847595
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2839000591
Short name T630
Test name
Test status
Simulation time 436075330 ps
CPU time 1.23 seconds
Started Jul 16 06:53:13 PM PDT 24
Finished Jul 16 06:53:16 PM PDT 24
Peak memory 206752 kb
Host smart-c7313fbf-5c82-402c-b3ce-480e50ba6399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390
00591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2839000591
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.4102090962
Short name T2420
Test name
Test status
Simulation time 6452865817 ps
CPU time 58.99 seconds
Started Jul 16 06:53:11 PM PDT 24
Finished Jul 16 06:54:11 PM PDT 24
Peak memory 207132 kb
Host smart-b05c71f2-b2c2-4cf6-9e49-6ae43d94ff2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41020
90962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.4102090962
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2846282944
Short name T2099
Test name
Test status
Simulation time 33919598 ps
CPU time 0.65 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:18 PM PDT 24
Peak memory 206844 kb
Host smart-0a495526-ff6f-401b-8d03-e9be3cc26915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2846282944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2846282944
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1077234412
Short name T481
Test name
Test status
Simulation time 3867809397 ps
CPU time 4.96 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:09 PM PDT 24
Peak memory 206936 kb
Host smart-1613b5f6-12d0-4b2c-8384-d63b706b27a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1077234412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.1077234412
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1101500231
Short name T890
Test name
Test status
Simulation time 13361844344 ps
CPU time 14.63 seconds
Started Jul 16 06:53:07 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 206924 kb
Host smart-fc611ae7-a850-4b0a-a6d7-67b600dae12f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1101500231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1101500231
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.455057058
Short name T2475
Test name
Test status
Simulation time 23364874209 ps
CPU time 29.58 seconds
Started Jul 16 06:53:06 PM PDT 24
Finished Jul 16 06:53:38 PM PDT 24
Peak memory 206816 kb
Host smart-a606e5ec-2508-4393-afcd-0eb8debe1308
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=455057058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.455057058
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1008487276
Short name T1362
Test name
Test status
Simulation time 159119969 ps
CPU time 0.82 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:05 PM PDT 24
Peak memory 206856 kb
Host smart-41c48c57-a4e5-40d4-8558-7c07c7b8b99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10084
87276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1008487276
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2802605628
Short name T2431
Test name
Test status
Simulation time 158850605 ps
CPU time 0.78 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:04 PM PDT 24
Peak memory 206864 kb
Host smart-c6f8ccb6-5011-49a4-bdfb-95957f680ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28026
05628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2802605628
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3789569913
Short name T1259
Test name
Test status
Simulation time 479080264 ps
CPU time 1.44 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 207016 kb
Host smart-235ca679-163f-41ca-989a-608420f1d8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37895
69913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3789569913
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3186071151
Short name T1371
Test name
Test status
Simulation time 1308433829 ps
CPU time 2.83 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:11 PM PDT 24
Peak memory 206936 kb
Host smart-1b10601b-ea84-4697-8877-74c5a63f8425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31860
71151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3186071151
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.4257851098
Short name T151
Test name
Test status
Simulation time 19337474167 ps
CPU time 40.15 seconds
Started Jul 16 06:53:01 PM PDT 24
Finished Jul 16 06:53:42 PM PDT 24
Peak memory 207116 kb
Host smart-d1466fb7-fa76-46ac-a0a9-c6e4e66271ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578
51098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.4257851098
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3572501035
Short name T1250
Test name
Test status
Simulation time 409089501 ps
CPU time 1.37 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:12 PM PDT 24
Peak memory 206668 kb
Host smart-d93053b0-ef92-4f0e-b126-56a320f747cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35725
01035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3572501035
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.467983747
Short name T2252
Test name
Test status
Simulation time 154933342 ps
CPU time 0.79 seconds
Started Jul 16 06:53:08 PM PDT 24
Finished Jul 16 06:53:11 PM PDT 24
Peak memory 206888 kb
Host smart-7b3cf091-d11f-4c3e-aa77-005c7cd33352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46798
3747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.467983747
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.4118094575
Short name T943
Test name
Test status
Simulation time 59492500 ps
CPU time 0.71 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:05 PM PDT 24
Peak memory 206844 kb
Host smart-d7c4a097-c22d-42cf-9e89-f94588f5c5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
94575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.4118094575
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3483663034
Short name T2689
Test name
Test status
Simulation time 760052323 ps
CPU time 1.81 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 206960 kb
Host smart-1ba67e96-37ca-424a-a032-7eafee73b1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
63034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3483663034
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1744437387
Short name T2706
Test name
Test status
Simulation time 259917910 ps
CPU time 1.33 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:08 PM PDT 24
Peak memory 207016 kb
Host smart-a31af898-97fa-4ef9-857d-c15eb1dffb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17444
37387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1744437387
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3682078743
Short name T677
Test name
Test status
Simulation time 177503691 ps
CPU time 0.83 seconds
Started Jul 16 06:53:06 PM PDT 24
Finished Jul 16 06:53:09 PM PDT 24
Peak memory 206876 kb
Host smart-5b849260-6f51-49c1-82df-fcfaa795e2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36820
78743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3682078743
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.773270469
Short name T2692
Test name
Test status
Simulation time 154700250 ps
CPU time 0.84 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:05 PM PDT 24
Peak memory 206848 kb
Host smart-21aa3ab1-12c5-4ce4-966b-f5691463ad02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77327
0469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.773270469
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2195702994
Short name T2566
Test name
Test status
Simulation time 189558931 ps
CPU time 0.87 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 206668 kb
Host smart-c65ff72f-a5b5-4c02-851c-ab2d491d3ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21957
02994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2195702994
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.43179340
Short name T71
Test name
Test status
Simulation time 5902147512 ps
CPU time 52.68 seconds
Started Jul 16 06:53:08 PM PDT 24
Finished Jul 16 06:54:02 PM PDT 24
Peak memory 207148 kb
Host smart-36cc197e-8dc5-4674-a5e7-dd2fa31c9423
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=43179340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.43179340
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.2878139054
Short name T2256
Test name
Test status
Simulation time 5386637500 ps
CPU time 47.65 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:53 PM PDT 24
Peak memory 207100 kb
Host smart-f913ed29-67f3-4f1d-aa97-5cf5f9da1b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28781
39054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.2878139054
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.766499153
Short name T402
Test name
Test status
Simulation time 221180403 ps
CPU time 0.87 seconds
Started Jul 16 06:53:07 PM PDT 24
Finished Jul 16 06:53:10 PM PDT 24
Peak memory 206728 kb
Host smart-737dda82-d111-4ff8-9ad3-347dbc46b7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76649
9153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.766499153
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3220049042
Short name T2496
Test name
Test status
Simulation time 23340365549 ps
CPU time 25.12 seconds
Started Jul 16 06:53:10 PM PDT 24
Finished Jul 16 06:53:37 PM PDT 24
Peak memory 206880 kb
Host smart-51419dcf-c81e-4624-963d-b5c658add09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32200
49042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3220049042
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1403821066
Short name T306
Test name
Test status
Simulation time 3316731043 ps
CPU time 4.12 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:09 PM PDT 24
Peak memory 206928 kb
Host smart-44c15c83-e1a1-470f-a33f-1358024b3f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14038
21066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1403821066
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2031211385
Short name T2426
Test name
Test status
Simulation time 9234801582 ps
CPU time 67.78 seconds
Started Jul 16 06:53:01 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 207140 kb
Host smart-e6e81ea0-64c4-4a4f-b816-aa861f705587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20312
11385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2031211385
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1729322946
Short name T1389
Test name
Test status
Simulation time 4204146122 ps
CPU time 28.47 seconds
Started Jul 16 06:53:12 PM PDT 24
Finished Jul 16 06:53:42 PM PDT 24
Peak memory 207080 kb
Host smart-8c9e8d1f-bf50-4953-aae8-f29d83ec882d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1729322946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1729322946
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1849002096
Short name T2468
Test name
Test status
Simulation time 299760645 ps
CPU time 0.92 seconds
Started Jul 16 06:53:08 PM PDT 24
Finished Jul 16 06:53:10 PM PDT 24
Peak memory 206884 kb
Host smart-6cc0cf7c-09db-469f-93aa-200acfab0f3a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1849002096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1849002096
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2075146458
Short name T1965
Test name
Test status
Simulation time 191330777 ps
CPU time 0.84 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:04 PM PDT 24
Peak memory 206884 kb
Host smart-7bd8798f-f8bb-4316-a14a-d68e87ef7ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20751
46458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2075146458
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1351487295
Short name T2720
Test name
Test status
Simulation time 4354306212 ps
CPU time 43.68 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:47 PM PDT 24
Peak memory 207116 kb
Host smart-22b80bd9-4966-407a-ad36-2118021bbe35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13514
87295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1351487295
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.1371962229
Short name T1128
Test name
Test status
Simulation time 5493655410 ps
CPU time 143.15 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:55:28 PM PDT 24
Peak memory 207052 kb
Host smart-f200a96a-9483-4700-bc3b-f78afe516ebe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1371962229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.1371962229
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.797878503
Short name T1077
Test name
Test status
Simulation time 212961537 ps
CPU time 0.86 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:06 PM PDT 24
Peak memory 206892 kb
Host smart-55424f33-514e-4f6e-893c-61eea5d8f29f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=797878503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.797878503
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2323862141
Short name T1631
Test name
Test status
Simulation time 195028237 ps
CPU time 0.85 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:05 PM PDT 24
Peak memory 206856 kb
Host smart-c161fc80-9c10-4d29-923d-de66b766a458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23238
62141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2323862141
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.501529001
Short name T133
Test name
Test status
Simulation time 223417443 ps
CPU time 0.9 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:05 PM PDT 24
Peak memory 206880 kb
Host smart-0425167c-7180-42d4-940c-981b7449ace3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50152
9001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.501529001
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.636106727
Short name T2025
Test name
Test status
Simulation time 156909181 ps
CPU time 0.8 seconds
Started Jul 16 06:53:13 PM PDT 24
Finished Jul 16 06:53:16 PM PDT 24
Peak memory 206744 kb
Host smart-6cafc31a-019a-4d72-8c88-7070f5314ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63610
6727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.636106727
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4222417925
Short name T625
Test name
Test status
Simulation time 162704115 ps
CPU time 0.83 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:05 PM PDT 24
Peak memory 206828 kb
Host smart-5f90197f-075e-4f40-8784-d52b1bb15c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42224
17925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4222417925
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2196360832
Short name T404
Test name
Test status
Simulation time 169533655 ps
CPU time 0.84 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 206880 kb
Host smart-5cfaf4f9-b29d-484d-885a-f16d38f03375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21963
60832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2196360832
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3303063634
Short name T2139
Test name
Test status
Simulation time 153440542 ps
CPU time 0.77 seconds
Started Jul 16 06:53:08 PM PDT 24
Finished Jul 16 06:53:11 PM PDT 24
Peak memory 206888 kb
Host smart-96a0821a-ff93-4da3-8dea-7df61c5df848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030
63634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3303063634
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3549979647
Short name T835
Test name
Test status
Simulation time 185417163 ps
CPU time 0.9 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:08 PM PDT 24
Peak memory 206852 kb
Host smart-7aa2958b-b9b8-4a02-8539-5dd714180b45
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3549979647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3549979647
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.382089027
Short name T685
Test name
Test status
Simulation time 158563591 ps
CPU time 0.77 seconds
Started Jul 16 06:53:06 PM PDT 24
Finished Jul 16 06:53:09 PM PDT 24
Peak memory 206752 kb
Host smart-c1c1096f-d20a-4cac-b712-23b2602dc98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38208
9027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.382089027
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3049527611
Short name T1828
Test name
Test status
Simulation time 108169394 ps
CPU time 0.75 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 206828 kb
Host smart-514ef112-ade5-4f44-8f9f-48ba187ff256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30495
27611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3049527611
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.487479268
Short name T992
Test name
Test status
Simulation time 9517817402 ps
CPU time 21.6 seconds
Started Jul 16 06:53:07 PM PDT 24
Finished Jul 16 06:53:31 PM PDT 24
Peak memory 207080 kb
Host smart-dfad898e-3c2a-44d1-8e89-d06d5f081a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48747
9268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.487479268
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4140425761
Short name T274
Test name
Test status
Simulation time 155521214 ps
CPU time 0.8 seconds
Started Jul 16 06:53:06 PM PDT 24
Finished Jul 16 06:53:09 PM PDT 24
Peak memory 206752 kb
Host smart-f72e6d50-ea3e-480e-972a-09ee84d8396b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404
25761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4140425761
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.548683206
Short name T2550
Test name
Test status
Simulation time 267492082 ps
CPU time 0.97 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 206816 kb
Host smart-80f381da-f505-42d1-a816-f4ab05847474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54868
3206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.548683206
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2716309553
Short name T1791
Test name
Test status
Simulation time 185757987 ps
CPU time 0.85 seconds
Started Jul 16 06:53:10 PM PDT 24
Finished Jul 16 06:53:12 PM PDT 24
Peak memory 206856 kb
Host smart-6e527aa9-c197-479a-add0-3dfe52c16fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27163
09553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2716309553
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.222592407
Short name T775
Test name
Test status
Simulation time 156353106 ps
CPU time 0.8 seconds
Started Jul 16 06:53:10 PM PDT 24
Finished Jul 16 06:53:12 PM PDT 24
Peak memory 206892 kb
Host smart-15a1172c-431d-46c8-8141-e37607d39bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22259
2407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.222592407
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.1499522362
Short name T868
Test name
Test status
Simulation time 178707696 ps
CPU time 0.85 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 206876 kb
Host smart-a65f8c7e-6efa-4b64-ba4a-f03413fd29fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14995
22362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.1499522362
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1181420093
Short name T2298
Test name
Test status
Simulation time 176867329 ps
CPU time 0.8 seconds
Started Jul 16 06:53:07 PM PDT 24
Finished Jul 16 06:53:10 PM PDT 24
Peak memory 206876 kb
Host smart-a43f1f71-10cc-446a-939d-deeb4379bd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
20093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1181420093
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3947778554
Short name T357
Test name
Test status
Simulation time 149650502 ps
CPU time 0.81 seconds
Started Jul 16 06:53:10 PM PDT 24
Finished Jul 16 06:53:12 PM PDT 24
Peak memory 206852 kb
Host smart-7fe187bf-3bb6-401a-8176-272fd2970fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39477
78554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3947778554
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3877962477
Short name T1166
Test name
Test status
Simulation time 230674503 ps
CPU time 1 seconds
Started Jul 16 06:53:02 PM PDT 24
Finished Jul 16 06:53:05 PM PDT 24
Peak memory 206848 kb
Host smart-e27c3a5d-2d7e-4356-9377-bde374fb6cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38779
62477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3877962477
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.114420032
Short name T2394
Test name
Test status
Simulation time 3849547338 ps
CPU time 106.96 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:55:08 PM PDT 24
Peak memory 206960 kb
Host smart-bdfd5cb4-67e1-4a42-9df0-dd8f9c09fccb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=114420032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.114420032
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2289563233
Short name T1938
Test name
Test status
Simulation time 174838324 ps
CPU time 0.79 seconds
Started Jul 16 06:53:07 PM PDT 24
Finished Jul 16 06:53:10 PM PDT 24
Peak memory 206724 kb
Host smart-a43ae191-e4b7-4f90-a25d-56a0ed62f9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22895
63233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2289563233
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3685343443
Short name T1725
Test name
Test status
Simulation time 177113945 ps
CPU time 0.84 seconds
Started Jul 16 06:53:13 PM PDT 24
Finished Jul 16 06:53:16 PM PDT 24
Peak memory 206748 kb
Host smart-e02ee51b-1add-4d19-80cb-18b3e7dae1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36853
43443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3685343443
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2489581052
Short name T938
Test name
Test status
Simulation time 211779390 ps
CPU time 0.84 seconds
Started Jul 16 06:53:11 PM PDT 24
Finished Jul 16 06:53:14 PM PDT 24
Peak memory 206856 kb
Host smart-47017e8e-3195-4427-9431-dc3bd3d48270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24895
81052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2489581052
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3018526323
Short name T1122
Test name
Test status
Simulation time 4522727036 ps
CPU time 31.95 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:49 PM PDT 24
Peak memory 206940 kb
Host smart-fa8548e8-841a-4346-bd41-e963cede35aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30185
26323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3018526323
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.708813778
Short name T2400
Test name
Test status
Simulation time 71497920 ps
CPU time 0.74 seconds
Started Jul 16 06:53:13 PM PDT 24
Finished Jul 16 06:53:17 PM PDT 24
Peak memory 206992 kb
Host smart-50e48bb7-5fcb-47cf-976d-59b4a1db27ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=708813778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.708813778
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.1375055349
Short name T1387
Test name
Test status
Simulation time 3632893573 ps
CPU time 4.37 seconds
Started Jul 16 06:53:13 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 207012 kb
Host smart-8fafa9b9-04dc-47cf-9094-d0585df8f366
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1375055349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.1375055349
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3710088500
Short name T2376
Test name
Test status
Simulation time 13392447705 ps
CPU time 16.71 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:34 PM PDT 24
Peak memory 206808 kb
Host smart-132fb496-e834-413c-b3c3-93a07f42e524
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3710088500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3710088500
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.264176100
Short name T1043
Test name
Test status
Simulation time 23302396281 ps
CPU time 21.2 seconds
Started Jul 16 06:53:12 PM PDT 24
Finished Jul 16 06:53:35 PM PDT 24
Peak memory 207088 kb
Host smart-f56bf25b-c90f-4345-8495-103c1dffe367
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=264176100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.264176100
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.165240310
Short name T459
Test name
Test status
Simulation time 153415114 ps
CPU time 0.79 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206748 kb
Host smart-10a11234-3892-4d00-9d99-0dc2179a71fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16524
0310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.165240310
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2380308691
Short name T891
Test name
Test status
Simulation time 166165074 ps
CPU time 0.79 seconds
Started Jul 16 06:53:12 PM PDT 24
Finished Jul 16 06:53:14 PM PDT 24
Peak memory 206884 kb
Host smart-2035fced-5026-4114-a4e4-0703612f305a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23803
08691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2380308691
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1207648910
Short name T604
Test name
Test status
Simulation time 360232011 ps
CPU time 1.26 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206800 kb
Host smart-d0cdadc9-64e0-4431-b2b1-903312ce0793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12076
48910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1207648910
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1307069123
Short name T1171
Test name
Test status
Simulation time 452257266 ps
CPU time 1.2 seconds
Started Jul 16 06:53:03 PM PDT 24
Finished Jul 16 06:53:06 PM PDT 24
Peak memory 206888 kb
Host smart-fe34fd55-c8df-4e28-ae3b-b3d4365bd5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13070
69123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1307069123
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2074996250
Short name T1443
Test name
Test status
Simulation time 16115617006 ps
CPU time 30.45 seconds
Started Jul 16 06:53:10 PM PDT 24
Finished Jul 16 06:53:42 PM PDT 24
Peak memory 207064 kb
Host smart-1398bbff-98ae-4cb6-9be3-0f3a627c131f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20749
96250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2074996250
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3697576550
Short name T1470
Test name
Test status
Simulation time 465132933 ps
CPU time 1.35 seconds
Started Jul 16 06:53:05 PM PDT 24
Finished Jul 16 06:53:08 PM PDT 24
Peak memory 206892 kb
Host smart-466f26ba-9274-496c-9515-fb1ca620aaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36975
76550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3697576550
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1501643464
Short name T1515
Test name
Test status
Simulation time 166941221 ps
CPU time 0.75 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206804 kb
Host smart-48d61af3-f8f2-4dbf-97e9-a4d3006447d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15016
43464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1501643464
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3299693988
Short name T1533
Test name
Test status
Simulation time 64538385 ps
CPU time 0.69 seconds
Started Jul 16 06:53:11 PM PDT 24
Finished Jul 16 06:53:13 PM PDT 24
Peak memory 206864 kb
Host smart-7656409a-1013-422b-96da-8f156b05c744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32996
93988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3299693988
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.820172374
Short name T570
Test name
Test status
Simulation time 897449195 ps
CPU time 2.14 seconds
Started Jul 16 06:53:11 PM PDT 24
Finished Jul 16 06:53:15 PM PDT 24
Peak memory 207056 kb
Host smart-3c1997d3-1a96-450e-b06f-c1788c6a0fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82017
2374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.820172374
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3357950138
Short name T1596
Test name
Test status
Simulation time 261215697 ps
CPU time 1.37 seconds
Started Jul 16 06:53:07 PM PDT 24
Finished Jul 16 06:53:10 PM PDT 24
Peak memory 206916 kb
Host smart-6df403f3-2921-4850-848d-5ecdd3b83c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33579
50138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3357950138
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2502540251
Short name T1617
Test name
Test status
Simulation time 181544212 ps
CPU time 0.8 seconds
Started Jul 16 06:53:11 PM PDT 24
Finished Jul 16 06:53:14 PM PDT 24
Peak memory 206868 kb
Host smart-808df507-33bc-415d-a2f2-fe238ef93ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
40251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2502540251
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.762726436
Short name T2369
Test name
Test status
Simulation time 144893108 ps
CPU time 0.75 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:07 PM PDT 24
Peak memory 206852 kb
Host smart-6888f8db-dc93-45d9-93c7-a161038299d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76272
6436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.762726436
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1420209384
Short name T1444
Test name
Test status
Simulation time 200009964 ps
CPU time 0.85 seconds
Started Jul 16 06:53:13 PM PDT 24
Finished Jul 16 06:53:17 PM PDT 24
Peak memory 206864 kb
Host smart-92028a1d-fae6-4a0c-b086-230495e28df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14202
09384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1420209384
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1658599584
Short name T2367
Test name
Test status
Simulation time 6053164984 ps
CPU time 57.42 seconds
Started Jul 16 06:53:11 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 207080 kb
Host smart-cc797486-1a1e-4508-9697-d8d226f05297
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1658599584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1658599584
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.474603430
Short name T1036
Test name
Test status
Simulation time 12920542262 ps
CPU time 39.04 seconds
Started Jul 16 06:53:04 PM PDT 24
Finished Jul 16 06:53:46 PM PDT 24
Peak memory 207084 kb
Host smart-323879f7-ce4c-4b0b-9dd0-f8f369c4ba3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47460
3430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.474603430
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2574270816
Short name T2308
Test name
Test status
Simulation time 190061023 ps
CPU time 0.8 seconds
Started Jul 16 06:53:09 PM PDT 24
Finished Jul 16 06:53:11 PM PDT 24
Peak memory 206812 kb
Host smart-a2af9c95-36bf-46fa-880d-81f8e877c1b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25742
70816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2574270816
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2272780093
Short name T936
Test name
Test status
Simulation time 23290987515 ps
CPU time 24.73 seconds
Started Jul 16 06:53:11 PM PDT 24
Finished Jul 16 06:53:38 PM PDT 24
Peak memory 206936 kb
Host smart-b73ae18c-159a-4d69-bad4-fdadc2a22a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22727
80093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2272780093
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3871415796
Short name T2728
Test name
Test status
Simulation time 3322709701 ps
CPU time 4.64 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 206916 kb
Host smart-f647ca27-a5cf-4a22-b6d1-0b2b09ca883c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38714
15796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3871415796
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3064801425
Short name T1180
Test name
Test status
Simulation time 13403925057 ps
CPU time 385.88 seconds
Started Jul 16 06:53:17 PM PDT 24
Finished Jul 16 06:59:47 PM PDT 24
Peak memory 207144 kb
Host smart-03062461-efc7-41b7-8b18-fab826bb0673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30648
01425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3064801425
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3418298631
Short name T1018
Test name
Test status
Simulation time 7225520047 ps
CPU time 195.25 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:56:32 PM PDT 24
Peak memory 207008 kb
Host smart-be7d2de2-9d79-49cf-bebc-917461d3f4a2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3418298631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3418298631
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1924937831
Short name T99
Test name
Test status
Simulation time 286061534 ps
CPU time 0.9 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:19 PM PDT 24
Peak memory 206808 kb
Host smart-7f4a4642-1df7-4780-9466-a14f15563150
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1924937831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1924937831
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2197659040
Short name T320
Test name
Test status
Simulation time 184035752 ps
CPU time 0.87 seconds
Started Jul 16 06:53:20 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 206856 kb
Host smart-c4464348-6745-4401-b7e0-7d072c316f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21976
59040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2197659040
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2158822222
Short name T1608
Test name
Test status
Simulation time 3886328719 ps
CPU time 37.51 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:53:58 PM PDT 24
Peak memory 207052 kb
Host smart-327d951e-9b95-443f-b76c-348539aa1bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21588
22222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2158822222
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1422008739
Short name T2440
Test name
Test status
Simulation time 6409829909 ps
CPU time 56.98 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 207012 kb
Host smart-ef0a6894-b534-404f-82f8-b954560f8d3f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1422008739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1422008739
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.4014055179
Short name T977
Test name
Test status
Simulation time 182657668 ps
CPU time 0.82 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:17 PM PDT 24
Peak memory 206816 kb
Host smart-f67b189c-567f-45f0-a955-6298e089b2af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4014055179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.4014055179
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2613267697
Short name T1560
Test name
Test status
Simulation time 146134281 ps
CPU time 0.76 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:18 PM PDT 24
Peak memory 206852 kb
Host smart-ac74d9f9-b02b-4967-a914-790bb4d76f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26132
67697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2613267697
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3955332256
Short name T1802
Test name
Test status
Simulation time 171071602 ps
CPU time 0.78 seconds
Started Jul 16 06:53:23 PM PDT 24
Finished Jul 16 06:53:26 PM PDT 24
Peak memory 206872 kb
Host smart-ec597c11-ea6b-461a-b6a8-9e732153c0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
32256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3955332256
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.841233863
Short name T664
Test name
Test status
Simulation time 163188185 ps
CPU time 0.79 seconds
Started Jul 16 06:53:19 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 206884 kb
Host smart-2c76e681-3291-466a-83e6-b667f9d94cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84123
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.841233863
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.4062886403
Short name T814
Test name
Test status
Simulation time 191032442 ps
CPU time 0.88 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 206884 kb
Host smart-2474623c-0e5b-4e79-9957-8cff98a021e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
86403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.4062886403
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3721475966
Short name T1092
Test name
Test status
Simulation time 165513017 ps
CPU time 0.8 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206884 kb
Host smart-1ce0239e-c2d2-42aa-8304-7d1223cbf762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37214
75966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3721475966
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.500227807
Short name T2562
Test name
Test status
Simulation time 245879692 ps
CPU time 1 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 206884 kb
Host smart-91f36cee-756c-4bd0-8155-1ea996a94313
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=500227807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.500227807
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.260248619
Short name T2511
Test name
Test status
Simulation time 155825353 ps
CPU time 0.75 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206852 kb
Host smart-b7402264-700a-4045-8dce-591935c8b149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26024
8619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.260248619
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2470479402
Short name T28
Test name
Test status
Simulation time 39477647 ps
CPU time 0.67 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:19 PM PDT 24
Peak memory 206860 kb
Host smart-f22d0687-65cc-4e74-b13c-82ca7b527898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24704
79402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2470479402
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1942875487
Short name T984
Test name
Test status
Simulation time 9976607716 ps
CPU time 23.06 seconds
Started Jul 16 06:53:20 PM PDT 24
Finished Jul 16 06:53:46 PM PDT 24
Peak memory 207132 kb
Host smart-e13e9f50-01b9-491d-8963-1f42b99676b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19428
75487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1942875487
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.4198160669
Short name T1495
Test name
Test status
Simulation time 183134748 ps
CPU time 0.9 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 206732 kb
Host smart-410b9f20-01b0-4f70-978e-39f639178ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41981
60669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.4198160669
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.908544623
Short name T1120
Test name
Test status
Simulation time 270992670 ps
CPU time 0.93 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:19 PM PDT 24
Peak memory 206860 kb
Host smart-e68ffe2f-490a-4164-89ec-cad00ea7dbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90854
4623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.908544623
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1666896684
Short name T719
Test name
Test status
Simulation time 194718380 ps
CPU time 0.85 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:18 PM PDT 24
Peak memory 206844 kb
Host smart-e7c20b58-483a-4719-b4f0-d164ede63527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16668
96684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1666896684
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.3015717825
Short name T2245
Test name
Test status
Simulation time 188863911 ps
CPU time 0.84 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 206904 kb
Host smart-f38867eb-ea98-4457-b461-daefd7b3e62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30157
17825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.3015717825
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2078665294
Short name T1866
Test name
Test status
Simulation time 142408912 ps
CPU time 0.81 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:21 PM PDT 24
Peak memory 206876 kb
Host smart-0799d1af-7581-423a-80d5-7f7ab721d391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20786
65294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2078665294
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1730228129
Short name T2633
Test name
Test status
Simulation time 182680895 ps
CPU time 0.86 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206868 kb
Host smart-9464e1d3-575a-47d8-b42b-ecdd32261512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17302
28129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1730228129
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1222712246
Short name T2108
Test name
Test status
Simulation time 154805291 ps
CPU time 0.79 seconds
Started Jul 16 06:53:17 PM PDT 24
Finished Jul 16 06:53:22 PM PDT 24
Peak memory 206884 kb
Host smart-93fdafb3-68ec-4a41-bdc2-05edbeefdd55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12227
12246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1222712246
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.175263798
Short name T2738
Test name
Test status
Simulation time 222033713 ps
CPU time 0.89 seconds
Started Jul 16 06:53:19 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 206892 kb
Host smart-c71f590a-7bc0-4785-b643-65d886336439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17526
3798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.175263798
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3242701895
Short name T466
Test name
Test status
Simulation time 3567175928 ps
CPU time 95.68 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 207064 kb
Host smart-402b5e0c-49c5-458c-a757-7ba1a2831a07
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3242701895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3242701895
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1695675758
Short name T553
Test name
Test status
Simulation time 194792152 ps
CPU time 0.83 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:19 PM PDT 24
Peak memory 206864 kb
Host smart-76f7da9d-c55a-4955-a01a-dcf46c025ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16956
75758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1695675758
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.11704020
Short name T1746
Test name
Test status
Simulation time 172645782 ps
CPU time 0.8 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 206860 kb
Host smart-15319f04-df0f-412d-9766-1f32222f1b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11704
020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.11704020
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.4032346972
Short name T1952
Test name
Test status
Simulation time 1116830285 ps
CPU time 2.3 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 207028 kb
Host smart-1a9072f3-48c2-4572-96f2-74c77a7cecac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40323
46972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.4032346972
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.1510805545
Short name T531
Test name
Test status
Simulation time 4803071483 ps
CPU time 48.47 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:54:09 PM PDT 24
Peak memory 206632 kb
Host smart-918a1aa4-4299-4dc6-90ec-3d362f151a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15108
05545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1510805545
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.667903565
Short name T1669
Test name
Test status
Simulation time 42385456 ps
CPU time 0.75 seconds
Started Jul 16 06:53:29 PM PDT 24
Finished Jul 16 06:53:32 PM PDT 24
Peak memory 206820 kb
Host smart-d498dbe6-ec4e-4d0f-a402-89049d221354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=667903565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.667903565
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2599388994
Short name T2617
Test name
Test status
Simulation time 3694285289 ps
CPU time 5.03 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:53:26 PM PDT 24
Peak memory 206996 kb
Host smart-47843665-4b2c-40bf-a071-85c9b8b1da3f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2599388994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2599388994
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3965169083
Short name T597
Test name
Test status
Simulation time 13544716708 ps
CPU time 14.35 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:35 PM PDT 24
Peak memory 206660 kb
Host smart-c8d052b1-d315-4e94-a504-8d69eb778f40
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3965169083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3965169083
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.94841950
Short name T420
Test name
Test status
Simulation time 23374454670 ps
CPU time 21.92 seconds
Started Jul 16 06:53:17 PM PDT 24
Finished Jul 16 06:53:43 PM PDT 24
Peak memory 207160 kb
Host smart-b45a1a14-0ed5-41f2-9e61-e65c0c1e1357
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=94841950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.94841950
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.874961172
Short name T2389
Test name
Test status
Simulation time 185097458 ps
CPU time 0.84 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206816 kb
Host smart-82e1c4b8-9a7a-4b70-99c5-a9b35b4075c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87496
1172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.874961172
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.33662419
Short name T1094
Test name
Test status
Simulation time 172875756 ps
CPU time 0.81 seconds
Started Jul 16 06:53:21 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 206744 kb
Host smart-ae813102-c714-4ecd-8bbf-a905fb67e599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33662
419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.33662419
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.874976100
Short name T1126
Test name
Test status
Simulation time 326724121 ps
CPU time 1.17 seconds
Started Jul 16 06:53:19 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 206892 kb
Host smart-178dfa34-7b73-42fe-b16f-0070a4f5331c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87497
6100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.874976100
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.353406707
Short name T2328
Test name
Test status
Simulation time 892635935 ps
CPU time 1.9 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 207012 kb
Host smart-60a9d3f6-2b23-483f-87e7-13db577b4888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35340
6707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.353406707
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.306350656
Short name T2261
Test name
Test status
Simulation time 23633724610 ps
CPU time 49.48 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 207084 kb
Host smart-33e2ed8b-aac1-40c9-a048-39fca165b769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30635
0656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.306350656
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.820394183
Short name T2092
Test name
Test status
Simulation time 359082015 ps
CPU time 1.23 seconds
Started Jul 16 06:53:16 PM PDT 24
Finished Jul 16 06:53:21 PM PDT 24
Peak memory 206872 kb
Host smart-30edf9b0-6a73-4bda-a1a7-8b7c921c6a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82039
4183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.820394183
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.520636651
Short name T2751
Test name
Test status
Simulation time 148450439 ps
CPU time 0.77 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 206888 kb
Host smart-c4b27767-44bc-4d43-8f7f-8c397e317345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52063
6651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.520636651
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2467576306
Short name T637
Test name
Test status
Simulation time 41759069 ps
CPU time 0.67 seconds
Started Jul 16 06:53:12 PM PDT 24
Finished Jul 16 06:53:15 PM PDT 24
Peak memory 206788 kb
Host smart-f6d28c91-88ce-44f8-9cff-0deed1ef338d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24675
76306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2467576306
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.740431860
Short name T2670
Test name
Test status
Simulation time 933982793 ps
CPU time 2.23 seconds
Started Jul 16 06:53:21 PM PDT 24
Finished Jul 16 06:53:26 PM PDT 24
Peak memory 207020 kb
Host smart-415139c3-41af-4d5e-9a38-bbfee88a64c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74043
1860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.740431860
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1137977714
Short name T1789
Test name
Test status
Simulation time 231746062 ps
CPU time 1.43 seconds
Started Jul 16 06:53:20 PM PDT 24
Finished Jul 16 06:53:25 PM PDT 24
Peak memory 207084 kb
Host smart-1398324a-6b87-48a3-9060-3a7f7bd84d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11379
77714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1137977714
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.810646864
Short name T1652
Test name
Test status
Simulation time 223600596 ps
CPU time 0.93 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206852 kb
Host smart-1264760c-0911-4636-bab3-235914588b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81064
6864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.810646864
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1161483714
Short name T1373
Test name
Test status
Simulation time 152627393 ps
CPU time 0.81 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:21 PM PDT 24
Peak memory 206864 kb
Host smart-4125ff04-10d2-49dc-86f0-fe8f6a427d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11614
83714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1161483714
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1137309894
Short name T2363
Test name
Test status
Simulation time 225728893 ps
CPU time 0.85 seconds
Started Jul 16 06:53:20 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 206828 kb
Host smart-e74a671c-36b0-4327-a8ec-136e937580f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11373
09894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1137309894
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2400045084
Short name T1413
Test name
Test status
Simulation time 6671043000 ps
CPU time 26.56 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:45 PM PDT 24
Peak memory 207092 kb
Host smart-ab01323c-592f-40af-8939-5b7cb17f2465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24000
45084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2400045084
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2699916764
Short name T2066
Test name
Test status
Simulation time 186133150 ps
CPU time 0.83 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 207028 kb
Host smart-1e5b5619-acfc-4b19-b194-2251df6ea2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26999
16764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2699916764
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2197326581
Short name T2289
Test name
Test status
Simulation time 23336090143 ps
CPU time 24.53 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:43 PM PDT 24
Peak memory 206944 kb
Host smart-9b8ef8b2-9bb5-4a13-8be2-e1e3edf2d6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21973
26581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2197326581
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2973001962
Short name T802
Test name
Test status
Simulation time 3268350258 ps
CPU time 3.56 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:21 PM PDT 24
Peak memory 206952 kb
Host smart-306e605a-d227-47be-a14c-aa66d24773c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29730
01962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2973001962
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1381051804
Short name T1584
Test name
Test status
Simulation time 8732313737 ps
CPU time 60.1 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:54:19 PM PDT 24
Peak memory 207300 kb
Host smart-4ba7cc46-4c75-4c14-913e-044ce0d28aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13810
51804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1381051804
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.3505402489
Short name T1561
Test name
Test status
Simulation time 5197924112 ps
CPU time 145.76 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:55:54 PM PDT 24
Peak memory 206980 kb
Host smart-7ecd1a06-3beb-4aa0-ab28-384dfcac765b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3505402489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.3505402489
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.3912686180
Short name T1505
Test name
Test status
Simulation time 240636916 ps
CPU time 0.93 seconds
Started Jul 16 06:53:22 PM PDT 24
Finished Jul 16 06:53:25 PM PDT 24
Peak memory 206848 kb
Host smart-6011407c-d0c8-44bb-8adf-f69b7e693bc8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3912686180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3912686180
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3791876346
Short name T2708
Test name
Test status
Simulation time 209793851 ps
CPU time 0.87 seconds
Started Jul 16 06:53:25 PM PDT 24
Finished Jul 16 06:53:28 PM PDT 24
Peak memory 206844 kb
Host smart-3fd39b2e-75c8-4f9d-a8fe-dc72d2d932b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37918
76346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3791876346
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.4061256442
Short name T1846
Test name
Test status
Simulation time 3659934043 ps
CPU time 100.87 seconds
Started Jul 16 06:53:23 PM PDT 24
Finished Jul 16 06:55:06 PM PDT 24
Peak memory 207036 kb
Host smart-28fc0680-6c2c-4657-b9dc-0de96dd89f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40612
56442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.4061256442
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1972066970
Short name T2185
Test name
Test status
Simulation time 3952058238 ps
CPU time 108.14 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:55:10 PM PDT 24
Peak memory 207092 kb
Host smart-32913643-d3dd-4f02-9069-c93c4f5f1a23
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1972066970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1972066970
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2187058280
Short name T1361
Test name
Test status
Simulation time 169579523 ps
CPU time 0.82 seconds
Started Jul 16 06:53:25 PM PDT 24
Finished Jul 16 06:53:27 PM PDT 24
Peak memory 206756 kb
Host smart-808919e3-7d72-451b-b015-7e2aa2e3d02d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2187058280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2187058280
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.450873706
Short name T649
Test name
Test status
Simulation time 152050017 ps
CPU time 0.8 seconds
Started Jul 16 06:53:15 PM PDT 24
Finished Jul 16 06:53:20 PM PDT 24
Peak memory 206888 kb
Host smart-b91e9cd0-e7eb-4630-8ebc-1fc7b118b34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45087
3706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.450873706
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2154975980
Short name T106
Test name
Test status
Simulation time 238051717 ps
CPU time 0.92 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 206856 kb
Host smart-594dc564-f8ba-4291-b4d3-16d56eedb337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21549
75980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2154975980
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3631829491
Short name T610
Test name
Test status
Simulation time 152024745 ps
CPU time 0.78 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 206856 kb
Host smart-52dc0613-552a-41df-a157-254f661a7d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318
29491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3631829491
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1906216228
Short name T559
Test name
Test status
Simulation time 205349080 ps
CPU time 0.85 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:28 PM PDT 24
Peak memory 206756 kb
Host smart-1ef35794-1211-417f-b774-ecc5d992de3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19062
16228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1906216228
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1870551285
Short name T1024
Test name
Test status
Simulation time 186179272 ps
CPU time 0.84 seconds
Started Jul 16 06:53:28 PM PDT 24
Finished Jul 16 06:53:31 PM PDT 24
Peak memory 206736 kb
Host smart-359636ab-71e9-49ad-afe3-261648501959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18705
51285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1870551285
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2030439329
Short name T1806
Test name
Test status
Simulation time 195778994 ps
CPU time 0.83 seconds
Started Jul 16 06:53:19 PM PDT 24
Finished Jul 16 06:53:24 PM PDT 24
Peak memory 206888 kb
Host smart-c6057f9e-9cda-4ba1-977b-50fa50efea80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20304
39329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2030439329
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.4005631156
Short name T2149
Test name
Test status
Simulation time 249801230 ps
CPU time 1 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 206820 kb
Host smart-b6b4baf4-1cc8-4f3f-81a8-c8bc0812c1f0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4005631156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.4005631156
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.535951975
Short name T731
Test name
Test status
Simulation time 142835136 ps
CPU time 0.76 seconds
Started Jul 16 06:53:24 PM PDT 24
Finished Jul 16 06:53:26 PM PDT 24
Peak memory 206848 kb
Host smart-569094f6-1886-4228-9084-a0e5cc9ce8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53595
1975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.535951975
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1239017684
Short name T2191
Test name
Test status
Simulation time 36563272 ps
CPU time 0.67 seconds
Started Jul 16 06:53:24 PM PDT 24
Finished Jul 16 06:53:26 PM PDT 24
Peak memory 206828 kb
Host smart-05d02f49-19dd-4245-a927-63219870753f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12390
17684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1239017684
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1264307325
Short name T240
Test name
Test status
Simulation time 10263617982 ps
CPU time 24.33 seconds
Started Jul 16 06:53:23 PM PDT 24
Finished Jul 16 06:53:49 PM PDT 24
Peak memory 207084 kb
Host smart-3c55a1c9-718c-4374-b624-e4732cec4932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12643
07325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1264307325
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.105486279
Short name T1594
Test name
Test status
Simulation time 164128216 ps
CPU time 0.93 seconds
Started Jul 16 06:53:14 PM PDT 24
Finished Jul 16 06:53:19 PM PDT 24
Peak memory 206736 kb
Host smart-a60f0668-deb6-4528-98cc-e8e3adee9ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548
6279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.105486279
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.690708889
Short name T1563
Test name
Test status
Simulation time 187695790 ps
CPU time 0.8 seconds
Started Jul 16 06:53:23 PM PDT 24
Finished Jul 16 06:53:26 PM PDT 24
Peak memory 206860 kb
Host smart-3bc98b1c-0550-467f-aa46-63a83d7bc31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69070
8889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.690708889
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.630365358
Short name T429
Test name
Test status
Simulation time 218113595 ps
CPU time 0.86 seconds
Started Jul 16 06:53:24 PM PDT 24
Finished Jul 16 06:53:26 PM PDT 24
Peak memory 206864 kb
Host smart-ad3f4248-e721-4b27-99c2-ae4c89d8a6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63036
5358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.630365358
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3304362201
Short name T655
Test name
Test status
Simulation time 180702838 ps
CPU time 0.87 seconds
Started Jul 16 06:53:24 PM PDT 24
Finished Jul 16 06:53:27 PM PDT 24
Peak memory 206832 kb
Host smart-de4f7c81-2e4c-4665-b3cf-5d5e7144e481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33043
62201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3304362201
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.3369643818
Short name T2602
Test name
Test status
Simulation time 176574666 ps
CPU time 0.75 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 206816 kb
Host smart-232db1a4-8cce-4259-80c6-2a29d90962ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33696
43818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3369643818
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1062658115
Short name T582
Test name
Test status
Simulation time 157064839 ps
CPU time 0.72 seconds
Started Jul 16 06:53:18 PM PDT 24
Finished Jul 16 06:53:23 PM PDT 24
Peak memory 206812 kb
Host smart-54135723-34fd-4709-b028-6b651f943b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10626
58115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1062658115
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3637358182
Short name T1598
Test name
Test status
Simulation time 194306496 ps
CPU time 0.85 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:29 PM PDT 24
Peak memory 206852 kb
Host smart-7609dada-af45-4c93-92a0-fedbcc9ec80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36373
58182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3637358182
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3360147847
Short name T1827
Test name
Test status
Simulation time 254163391 ps
CPU time 1.07 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:29 PM PDT 24
Peak memory 206880 kb
Host smart-cdb5c256-dc3a-4eef-a99f-addfbff51383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33601
47847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3360147847
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2555499565
Short name T840
Test name
Test status
Simulation time 5084362941 ps
CPU time 133.14 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:55:42 PM PDT 24
Peak memory 206872 kb
Host smart-23d60de3-40f0-4590-901f-b8a9380924e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2555499565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2555499565
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.664230998
Short name T2586
Test name
Test status
Simulation time 153882176 ps
CPU time 0.76 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:53:30 PM PDT 24
Peak memory 206812 kb
Host smart-512ce10f-b25d-48a6-ad37-2b310e01c8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66423
0998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.664230998
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.4015474840
Short name T602
Test name
Test status
Simulation time 163769180 ps
CPU time 0.8 seconds
Started Jul 16 06:53:29 PM PDT 24
Finished Jul 16 06:53:31 PM PDT 24
Peak memory 206844 kb
Host smart-adaacb14-03fe-4f7f-8e60-29bc77fb1173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
74840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.4015474840
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.514255426
Short name T2109
Test name
Test status
Simulation time 955321538 ps
CPU time 2.34 seconds
Started Jul 16 06:53:30 PM PDT 24
Finished Jul 16 06:53:34 PM PDT 24
Peak memory 207008 kb
Host smart-12be5b5c-7fc6-42d8-b91c-afa9fae0db8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51425
5426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.514255426
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.4235891642
Short name T375
Test name
Test status
Simulation time 4124330747 ps
CPU time 37.17 seconds
Started Jul 16 06:53:40 PM PDT 24
Finished Jul 16 06:54:18 PM PDT 24
Peak memory 207076 kb
Host smart-436250d9-a8cf-404c-8e40-b24c6dbd307a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42358
91642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.4235891642
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.167215025
Short name T702
Test name
Test status
Simulation time 51383503 ps
CPU time 0.75 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:53:30 PM PDT 24
Peak memory 206900 kb
Host smart-231ba716-3f5f-4810-afc6-de13e9241f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=167215025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.167215025
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1081432669
Short name T397
Test name
Test status
Simulation time 4236749553 ps
CPU time 4.82 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:33 PM PDT 24
Peak memory 207100 kb
Host smart-8a340a19-eee5-43b6-b8ac-0986ec09db0b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1081432669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1081432669
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3665432693
Short name T918
Test name
Test status
Simulation time 13405440948 ps
CPU time 11.92 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:53:40 PM PDT 24
Peak memory 207080 kb
Host smart-62c7bf9e-c8ae-4d76-a882-2167860152f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3665432693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3665432693
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1902456372
Short name T1051
Test name
Test status
Simulation time 23343695868 ps
CPU time 24.29 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:53:59 PM PDT 24
Peak memory 207068 kb
Host smart-99aeb980-45e7-4693-b37c-d7ca3207c3f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1902456372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.1902456372
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2083689511
Short name T2657
Test name
Test status
Simulation time 162040883 ps
CPU time 0.81 seconds
Started Jul 16 06:53:32 PM PDT 24
Finished Jul 16 06:53:35 PM PDT 24
Peak memory 207028 kb
Host smart-206b12bc-1c58-4a19-86bb-8be72b9d9f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20836
89511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2083689511
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1380549370
Short name T614
Test name
Test status
Simulation time 157744896 ps
CPU time 0.81 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:53:36 PM PDT 24
Peak memory 206852 kb
Host smart-97ba4fcd-b084-43af-b03e-23aa7aacac3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13805
49370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1380549370
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3179545936
Short name T679
Test name
Test status
Simulation time 337999900 ps
CPU time 1.09 seconds
Started Jul 16 06:53:28 PM PDT 24
Finished Jul 16 06:53:31 PM PDT 24
Peak memory 206860 kb
Host smart-47630a27-709b-489a-afed-11e56a3d5489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31795
45936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3179545936
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3245237768
Short name T406
Test name
Test status
Simulation time 341856329 ps
CPU time 1.06 seconds
Started Jul 16 06:53:32 PM PDT 24
Finished Jul 16 06:53:35 PM PDT 24
Peak memory 206872 kb
Host smart-9c11c14e-2f1f-4768-a152-7660453d6298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
37768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3245237768
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1912883292
Short name T2340
Test name
Test status
Simulation time 13600375705 ps
CPU time 25.95 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:53:55 PM PDT 24
Peak memory 206856 kb
Host smart-1bad4ed9-63e7-4b73-b27e-564facc76895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19128
83292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1912883292
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1617902232
Short name T584
Test name
Test status
Simulation time 427903267 ps
CPU time 1.27 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:53:35 PM PDT 24
Peak memory 206868 kb
Host smart-6f0cfc94-200c-43dc-861d-26ffdbba0937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16179
02232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1617902232
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.79106463
Short name T2557
Test name
Test status
Simulation time 141484937 ps
CPU time 0.74 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:53:29 PM PDT 24
Peak memory 206880 kb
Host smart-9cf14f99-7867-49da-9858-c69f18df0917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79106
463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.79106463
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.794643351
Short name T1615
Test name
Test status
Simulation time 41749738 ps
CPU time 0.65 seconds
Started Jul 16 06:53:30 PM PDT 24
Finished Jul 16 06:53:32 PM PDT 24
Peak memory 206876 kb
Host smart-47b7b8f1-256c-43ee-9833-10a3a0e02c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79464
3351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.794643351
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1863354151
Short name T1281
Test name
Test status
Simulation time 901882133 ps
CPU time 2.38 seconds
Started Jul 16 06:53:38 PM PDT 24
Finished Jul 16 06:53:41 PM PDT 24
Peak memory 207072 kb
Host smart-1eea58b2-1019-4296-b896-aa592bbad14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18633
54151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1863354151
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3995725559
Short name T1255
Test name
Test status
Simulation time 163139649 ps
CPU time 1.61 seconds
Started Jul 16 06:53:29 PM PDT 24
Finished Jul 16 06:53:33 PM PDT 24
Peak memory 206864 kb
Host smart-de7ff626-d774-4302-aad2-a9f14972ea37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39957
25559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3995725559
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3194274290
Short name T1252
Test name
Test status
Simulation time 165913326 ps
CPU time 0.86 seconds
Started Jul 16 06:53:30 PM PDT 24
Finished Jul 16 06:53:33 PM PDT 24
Peak memory 206876 kb
Host smart-df04b226-ca5f-49e5-9770-3ea193975954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31942
74290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3194274290
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2359121033
Short name T2649
Test name
Test status
Simulation time 162754745 ps
CPU time 0.79 seconds
Started Jul 16 06:53:30 PM PDT 24
Finished Jul 16 06:53:33 PM PDT 24
Peak memory 206824 kb
Host smart-1fba6b4b-a076-4b51-bafd-02cd898a177e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23591
21033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2359121033
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2504530327
Short name T2095
Test name
Test status
Simulation time 226955182 ps
CPU time 0.93 seconds
Started Jul 16 06:53:39 PM PDT 24
Finished Jul 16 06:53:40 PM PDT 24
Peak memory 206852 kb
Host smart-84a7fd9f-a0d4-4e3e-96ca-20d286174e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25045
30327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2504530327
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2483300920
Short name T95
Test name
Test status
Simulation time 8108598179 ps
CPU time 59.62 seconds
Started Jul 16 06:53:31 PM PDT 24
Finished Jul 16 06:54:32 PM PDT 24
Peak memory 207068 kb
Host smart-f38203fe-b83d-4b0b-8c62-9a57e863cf88
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2483300920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2483300920
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.3803531839
Short name T1901
Test name
Test status
Simulation time 8407951579 ps
CPU time 31.1 seconds
Started Jul 16 06:53:25 PM PDT 24
Finished Jul 16 06:53:58 PM PDT 24
Peak memory 207016 kb
Host smart-53f0432b-6a86-4bfe-81a2-0b97a311aa27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38035
31839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3803531839
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.890072351
Short name T798
Test name
Test status
Simulation time 230113392 ps
CPU time 0.89 seconds
Started Jul 16 06:53:32 PM PDT 24
Finished Jul 16 06:53:35 PM PDT 24
Peak memory 206716 kb
Host smart-89135a5f-870c-42da-bc43-f75454c352b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89007
2351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.890072351
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.903372020
Short name T603
Test name
Test status
Simulation time 23318519978 ps
CPU time 26.45 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:54 PM PDT 24
Peak memory 206940 kb
Host smart-fbe9b17b-2cb5-4a8b-b594-ca3eb275117a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90337
2020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.903372020
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3419204068
Short name T578
Test name
Test status
Simulation time 3341744249 ps
CPU time 3.77 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:53:38 PM PDT 24
Peak memory 206916 kb
Host smart-5c9546b8-70ef-4fb5-802b-50f7c74c5606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34192
04068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3419204068
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3733403255
Short name T931
Test name
Test status
Simulation time 8953259952 ps
CPU time 65.52 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:54:35 PM PDT 24
Peak memory 207056 kb
Host smart-1339428e-caa0-4537-9716-69938a22c5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37334
03255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3733403255
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.419058112
Short name T2171
Test name
Test status
Simulation time 7405750576 ps
CPU time 194.71 seconds
Started Jul 16 06:53:28 PM PDT 24
Finished Jul 16 06:56:44 PM PDT 24
Peak memory 207036 kb
Host smart-28681093-d9bb-4a75-8da3-709f74fd9032
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=419058112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.419058112
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.447699969
Short name T2624
Test name
Test status
Simulation time 237051228 ps
CPU time 0.95 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:29 PM PDT 24
Peak memory 206860 kb
Host smart-b9b4311f-f39c-45a5-a62b-28398a772a6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=447699969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.447699969
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.369544570
Short name T789
Test name
Test status
Simulation time 194608689 ps
CPU time 0.85 seconds
Started Jul 16 06:53:30 PM PDT 24
Finished Jul 16 06:53:33 PM PDT 24
Peak memory 206884 kb
Host smart-e9b0113e-ac49-46b7-9d97-53e48db003f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954
4570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.369544570
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3860257840
Short name T521
Test name
Test status
Simulation time 4109887970 ps
CPU time 29.03 seconds
Started Jul 16 06:53:36 PM PDT 24
Finished Jul 16 06:54:06 PM PDT 24
Peak memory 207120 kb
Host smart-8f1c04d2-0a04-4516-9b7e-52cebf1fbea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
57840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3860257840
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1458304450
Short name T2651
Test name
Test status
Simulation time 3059312857 ps
CPU time 22.46 seconds
Started Jul 16 06:53:28 PM PDT 24
Finished Jul 16 06:53:52 PM PDT 24
Peak memory 207120 kb
Host smart-f22505fb-459e-46cf-8a48-ec8fd3fc7d98
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1458304450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1458304450
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2620340212
Short name T2686
Test name
Test status
Simulation time 164116376 ps
CPU time 0.81 seconds
Started Jul 16 06:53:34 PM PDT 24
Finished Jul 16 06:53:36 PM PDT 24
Peak memory 206880 kb
Host smart-3d94b150-c828-4a9c-b204-110a8b48ec9c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2620340212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2620340212
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3336530113
Short name T1942
Test name
Test status
Simulation time 146350508 ps
CPU time 0.77 seconds
Started Jul 16 06:53:35 PM PDT 24
Finished Jul 16 06:53:37 PM PDT 24
Peak memory 206884 kb
Host smart-f5fa8ae1-d1dd-46fb-acd2-21e4c4bc3609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33365
30113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3336530113
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2770004056
Short name T2423
Test name
Test status
Simulation time 185864896 ps
CPU time 0.86 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:29 PM PDT 24
Peak memory 206856 kb
Host smart-751c791e-5067-40d8-a543-389e981fc8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27700
04056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2770004056
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.428526249
Short name T1554
Test name
Test status
Simulation time 151741947 ps
CPU time 0.78 seconds
Started Jul 16 06:53:39 PM PDT 24
Finished Jul 16 06:53:41 PM PDT 24
Peak memory 206848 kb
Host smart-65f94a06-f172-44c7-8e24-65560e26163c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42852
6249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.428526249
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1892350725
Short name T1855
Test name
Test status
Simulation time 215606724 ps
CPU time 0.84 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:53:36 PM PDT 24
Peak memory 206868 kb
Host smart-d2ee4bfa-982f-407a-a12d-2290f7173bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18923
50725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1892350725
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1450282234
Short name T2753
Test name
Test status
Simulation time 163270990 ps
CPU time 0.78 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:28 PM PDT 24
Peak memory 206856 kb
Host smart-f9e8ee2a-d93d-4a31-b9b9-f6d9fb6229e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14502
82234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1450282234
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2127186295
Short name T314
Test name
Test status
Simulation time 244759786 ps
CPU time 0.89 seconds
Started Jul 16 06:53:31 PM PDT 24
Finished Jul 16 06:53:33 PM PDT 24
Peak memory 206888 kb
Host smart-b7600b81-9725-4aef-aef8-7e4948690dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21271
86295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2127186295
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.4129117922
Short name T928
Test name
Test status
Simulation time 241617724 ps
CPU time 0.97 seconds
Started Jul 16 06:53:35 PM PDT 24
Finished Jul 16 06:53:37 PM PDT 24
Peak memory 206808 kb
Host smart-5921b382-e078-4330-8674-53e6621336a2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4129117922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.4129117922
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1654534358
Short name T972
Test name
Test status
Simulation time 141808685 ps
CPU time 0.78 seconds
Started Jul 16 06:53:36 PM PDT 24
Finished Jul 16 06:53:39 PM PDT 24
Peak memory 206752 kb
Host smart-cc8e6c28-b0bf-433f-8573-ea324000e31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16545
34358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1654534358
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3756492880
Short name T697
Test name
Test status
Simulation time 36975598 ps
CPU time 0.68 seconds
Started Jul 16 06:53:29 PM PDT 24
Finished Jul 16 06:53:31 PM PDT 24
Peak memory 206728 kb
Host smart-74c171f2-bed9-461e-82e2-1de1fe2cc2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37564
92880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3756492880
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3417673239
Short name T2035
Test name
Test status
Simulation time 18982178507 ps
CPU time 42.3 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:54:09 PM PDT 24
Peak memory 207128 kb
Host smart-a962cb19-b379-450b-995f-66e4e67dfea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34176
73239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3417673239
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.986673435
Short name T797
Test name
Test status
Simulation time 188214742 ps
CPU time 0.88 seconds
Started Jul 16 06:53:35 PM PDT 24
Finished Jul 16 06:53:37 PM PDT 24
Peak memory 206800 kb
Host smart-c2115ad0-38f7-4ad6-8a4f-7e933390120f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98667
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.986673435
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2064434254
Short name T1110
Test name
Test status
Simulation time 205787103 ps
CPU time 0.91 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:53:30 PM PDT 24
Peak memory 206868 kb
Host smart-febc81a7-4c4e-41e1-8b21-2f34aaad93a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20644
34254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2064434254
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2920790335
Short name T1989
Test name
Test status
Simulation time 308642727 ps
CPU time 0.96 seconds
Started Jul 16 06:53:34 PM PDT 24
Finished Jul 16 06:53:37 PM PDT 24
Peak memory 206892 kb
Host smart-86d73f7e-9cc9-424d-a704-075ed84e13dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207
90335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2920790335
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.4140393408
Short name T1931
Test name
Test status
Simulation time 214702939 ps
CPU time 0.89 seconds
Started Jul 16 06:53:26 PM PDT 24
Finished Jul 16 06:53:29 PM PDT 24
Peak memory 206896 kb
Host smart-ad9b5469-d953-4074-b0f4-1a390202eb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41403
93408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.4140393408
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.218463997
Short name T2482
Test name
Test status
Simulation time 152892373 ps
CPU time 0.77 seconds
Started Jul 16 06:53:37 PM PDT 24
Finished Jul 16 06:53:39 PM PDT 24
Peak memory 206884 kb
Host smart-572607a4-6fcb-47ed-9356-50365ca0470d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
3997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.218463997
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.432770411
Short name T480
Test name
Test status
Simulation time 151365148 ps
CPU time 0.75 seconds
Started Jul 16 06:53:29 PM PDT 24
Finished Jul 16 06:53:32 PM PDT 24
Peak memory 206624 kb
Host smart-98c20184-370c-4bd4-be2b-a27acc701218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43277
0411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.432770411
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.847046517
Short name T1478
Test name
Test status
Simulation time 154079749 ps
CPU time 0.76 seconds
Started Jul 16 06:53:32 PM PDT 24
Finished Jul 16 06:53:34 PM PDT 24
Peak memory 206888 kb
Host smart-2b5ffeb6-0c73-453d-a854-258d39c6c864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84704
6517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.847046517
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3197336290
Short name T1794
Test name
Test status
Simulation time 176290808 ps
CPU time 0.79 seconds
Started Jul 16 06:53:28 PM PDT 24
Finished Jul 16 06:53:31 PM PDT 24
Peak memory 206876 kb
Host smart-bd131d47-0010-4101-b5cb-cad8b7e4d7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31973
36290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3197336290
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3748905549
Short name T1068
Test name
Test status
Simulation time 6185382600 ps
CPU time 169.22 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:56:24 PM PDT 24
Peak memory 206912 kb
Host smart-36aaf2d2-a954-455c-93a7-250cc2b854c7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3748905549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3748905549
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1564777569
Short name T356
Test name
Test status
Simulation time 148156018 ps
CPU time 0.78 seconds
Started Jul 16 06:53:37 PM PDT 24
Finished Jul 16 06:53:39 PM PDT 24
Peak memory 206880 kb
Host smart-c26073b9-ac3b-44ca-827a-582c4d745487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15647
77569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1564777569
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2844600530
Short name T1303
Test name
Test status
Simulation time 148088915 ps
CPU time 0.78 seconds
Started Jul 16 06:53:29 PM PDT 24
Finished Jul 16 06:53:32 PM PDT 24
Peak memory 206732 kb
Host smart-c58cfa2b-a67f-4a8d-8249-874e151598d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28446
00530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2844600530
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.3281395290
Short name T718
Test name
Test status
Simulation time 508289051 ps
CPU time 1.37 seconds
Started Jul 16 06:53:29 PM PDT 24
Finished Jul 16 06:53:32 PM PDT 24
Peak memory 206864 kb
Host smart-b67cf921-81f7-4f62-8cd8-76c36c2b37f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32813
95290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.3281395290
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.458840802
Short name T343
Test name
Test status
Simulation time 3394228072 ps
CPU time 93.09 seconds
Started Jul 16 06:53:32 PM PDT 24
Finished Jul 16 06:55:07 PM PDT 24
Peak memory 207076 kb
Host smart-4a9f8e26-3d75-4058-9eea-2fada47efea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45884
0802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.458840802
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2791194801
Short name T2577
Test name
Test status
Simulation time 45859814 ps
CPU time 0.65 seconds
Started Jul 16 06:53:39 PM PDT 24
Finished Jul 16 06:53:41 PM PDT 24
Peak memory 206876 kb
Host smart-1ead945b-a6c3-448d-ba97-30847d44886a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2791194801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2791194801
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2911842435
Short name T371
Test name
Test status
Simulation time 4135641986 ps
CPU time 5.3 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:53:41 PM PDT 24
Peak memory 207136 kb
Host smart-223c79c6-48f8-488a-8e8e-9a405cf9d1b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2911842435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2911842435
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1354294455
Short name T2387
Test name
Test status
Simulation time 13412773105 ps
CPU time 12.68 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:53:48 PM PDT 24
Peak memory 206944 kb
Host smart-d690d259-baca-4ad0-9190-50271245e829
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1354294455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1354294455
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1185117286
Short name T178
Test name
Test status
Simulation time 23335084210 ps
CPU time 23.3 seconds
Started Jul 16 06:53:36 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206928 kb
Host smart-6743cd17-872f-46ff-9ee1-1afa05e2ebb0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1185117286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.1185117286
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.919514345
Short name T1461
Test name
Test status
Simulation time 158193272 ps
CPU time 0.89 seconds
Started Jul 16 06:53:32 PM PDT 24
Finished Jul 16 06:53:34 PM PDT 24
Peak memory 206856 kb
Host smart-6f62d0ee-6ba8-4dde-8183-a403cc291e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91951
4345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.919514345
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1999560048
Short name T1797
Test name
Test status
Simulation time 139733356 ps
CPU time 0.79 seconds
Started Jul 16 06:53:38 PM PDT 24
Finished Jul 16 06:53:40 PM PDT 24
Peak memory 206876 kb
Host smart-a9d790df-42c1-4222-a152-3d3f0e4625c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19995
60048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1999560048
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.332330248
Short name T1646
Test name
Test status
Simulation time 343042817 ps
CPU time 1.24 seconds
Started Jul 16 06:53:33 PM PDT 24
Finished Jul 16 06:53:36 PM PDT 24
Peak memory 206884 kb
Host smart-3da483b4-7ddf-477a-85a6-91155e2d756e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33233
0248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.332330248
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2766137976
Short name T1452
Test name
Test status
Simulation time 663194575 ps
CPU time 1.72 seconds
Started Jul 16 06:53:34 PM PDT 24
Finished Jul 16 06:53:37 PM PDT 24
Peak memory 207056 kb
Host smart-254e54a0-d905-4e53-b85f-c1fbb70088fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27661
37976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2766137976
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3282901382
Short name T636
Test name
Test status
Simulation time 19962997762 ps
CPU time 40.04 seconds
Started Jul 16 06:53:34 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 207072 kb
Host smart-fa17243c-6df8-434e-894d-315ac99555c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32829
01382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3282901382
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.209507355
Short name T635
Test name
Test status
Simulation time 430378906 ps
CPU time 1.37 seconds
Started Jul 16 06:53:27 PM PDT 24
Finished Jul 16 06:53:30 PM PDT 24
Peak memory 206884 kb
Host smart-42fd9a1a-21ac-438f-bdd1-4138190c2923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
7355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.209507355
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.72775007
Short name T1639
Test name
Test status
Simulation time 158907143 ps
CPU time 0.79 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:53:50 PM PDT 24
Peak memory 207032 kb
Host smart-cde4d673-c6e4-4716-a005-bb79cb0999e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72775
007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.72775007
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.882610337
Short name T2681
Test name
Test status
Simulation time 31828572 ps
CPU time 0.64 seconds
Started Jul 16 06:53:40 PM PDT 24
Finished Jul 16 06:53:42 PM PDT 24
Peak memory 206852 kb
Host smart-8423f268-911d-43a4-8b62-dd27ca2db842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88261
0337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.882610337
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2729858532
Short name T2449
Test name
Test status
Simulation time 967648350 ps
CPU time 2.37 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:54 PM PDT 24
Peak memory 207028 kb
Host smart-d64c025f-14b7-4034-b38d-0de98f7f1441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27298
58532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2729858532
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2048178384
Short name T2652
Test name
Test status
Simulation time 261064222 ps
CPU time 2.11 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:53:55 PM PDT 24
Peak memory 207032 kb
Host smart-524e387f-c4e0-4572-ae21-68c1f07f3525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20481
78384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2048178384
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.4176005303
Short name T1649
Test name
Test status
Simulation time 219541405 ps
CPU time 0.94 seconds
Started Jul 16 06:53:40 PM PDT 24
Finished Jul 16 06:53:43 PM PDT 24
Peak memory 206868 kb
Host smart-8b808845-2ea6-4eba-b428-96b61dfe22c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41760
05303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.4176005303
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1593102099
Short name T2150
Test name
Test status
Simulation time 145747196 ps
CPU time 0.8 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:52 PM PDT 24
Peak memory 206724 kb
Host smart-3a1a6960-fe3a-4565-a9da-a5a21f36f90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15931
02099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1593102099
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1500944294
Short name T998
Test name
Test status
Simulation time 240774234 ps
CPU time 0.94 seconds
Started Jul 16 06:53:50 PM PDT 24
Finished Jul 16 06:53:57 PM PDT 24
Peak memory 206808 kb
Host smart-2d9158e8-7282-4e92-9700-2af39ef494d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15009
44294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1500944294
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.3438885358
Short name T2228
Test name
Test status
Simulation time 7658368725 ps
CPU time 21.77 seconds
Started Jul 16 06:53:49 PM PDT 24
Finished Jul 16 06:54:17 PM PDT 24
Peak memory 207060 kb
Host smart-3280c463-6a26-4163-9943-6d7122e200de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34388
85358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.3438885358
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1082004497
Short name T2372
Test name
Test status
Simulation time 245692425 ps
CPU time 0.95 seconds
Started Jul 16 06:53:44 PM PDT 24
Finished Jul 16 06:53:49 PM PDT 24
Peak memory 206876 kb
Host smart-4fed96ff-b5ad-406e-a917-aa358de41ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
04497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1082004497
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.4132296005
Short name T1433
Test name
Test status
Simulation time 23272825068 ps
CPU time 29.52 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206924 kb
Host smart-d5ae0ed7-273c-496d-a91a-5c2bd8ee7886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41322
96005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.4132296005
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1899604936
Short name T2357
Test name
Test status
Simulation time 3330554898 ps
CPU time 3.73 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:53:48 PM PDT 24
Peak memory 206916 kb
Host smart-ead131ae-05a3-4a7d-8a26-bf4ed17d9c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18996
04936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1899604936
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2467181753
Short name T394
Test name
Test status
Simulation time 6351665236 ps
CPU time 57.7 seconds
Started Jul 16 06:53:39 PM PDT 24
Finished Jul 16 06:54:38 PM PDT 24
Peak memory 207068 kb
Host smart-bf123d95-e672-4e4e-9cfa-501bd9e2d5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24671
81753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2467181753
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.4283675601
Short name T342
Test name
Test status
Simulation time 5801528594 ps
CPU time 55.39 seconds
Started Jul 16 06:53:43 PM PDT 24
Finished Jul 16 06:54:41 PM PDT 24
Peak memory 206952 kb
Host smart-875e5d07-2475-401c-a545-cbc8cdab9f04
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4283675601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.4283675601
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2210808202
Short name T2503
Test name
Test status
Simulation time 256646430 ps
CPU time 0.95 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:53:44 PM PDT 24
Peak memory 206844 kb
Host smart-ea910774-73ec-4ed4-9e2c-65b66777752c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2210808202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2210808202
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.733171601
Short name T1530
Test name
Test status
Simulation time 196389762 ps
CPU time 0.86 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:53:45 PM PDT 24
Peak memory 206880 kb
Host smart-1b8639bc-7f5d-488d-9ff8-de416cf59636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73317
1601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.733171601
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.274223180
Short name T1745
Test name
Test status
Simulation time 5433124927 ps
CPU time 49.94 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 207048 kb
Host smart-1fae9d89-6c14-4fc2-a50a-d3b03fc84d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
3180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.274223180
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.221524295
Short name T1844
Test name
Test status
Simulation time 7819754721 ps
CPU time 216.64 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:57:20 PM PDT 24
Peak memory 206996 kb
Host smart-5b359daa-346b-4487-b0fe-e4b460171fd8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=221524295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.221524295
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.987907108
Short name T1494
Test name
Test status
Simulation time 164522484 ps
CPU time 0.82 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:53:44 PM PDT 24
Peak memory 206880 kb
Host smart-cac90027-f6c6-4bd2-a332-1318edf9e6f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=987907108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.987907108
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.4033697280
Short name T1140
Test name
Test status
Simulation time 144102098 ps
CPU time 0.82 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:53:45 PM PDT 24
Peak memory 206860 kb
Host smart-169f2fd7-0ec1-4d27-94f1-98d185bd7ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40336
97280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.4033697280
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1944557487
Short name T110
Test name
Test status
Simulation time 215701595 ps
CPU time 0.92 seconds
Started Jul 16 06:53:40 PM PDT 24
Finished Jul 16 06:53:43 PM PDT 24
Peak memory 206888 kb
Host smart-07733eb2-17f3-490f-a52f-af73301e3f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19445
57487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1944557487
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.4268334011
Short name T747
Test name
Test status
Simulation time 235903337 ps
CPU time 0.93 seconds
Started Jul 16 06:53:42 PM PDT 24
Finished Jul 16 06:53:46 PM PDT 24
Peak memory 206852 kb
Host smart-4b8c0d0e-8a53-4197-861a-5a77c3758553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42683
34011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.4268334011
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1543663651
Short name T1764
Test name
Test status
Simulation time 196973707 ps
CPU time 0.82 seconds
Started Jul 16 06:53:40 PM PDT 24
Finished Jul 16 06:53:42 PM PDT 24
Peak memory 206752 kb
Host smart-20f479bc-7058-4e61-80e8-23139a79c80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
63651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1543663651
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2149807537
Short name T565
Test name
Test status
Simulation time 186568975 ps
CPU time 0.8 seconds
Started Jul 16 06:53:42 PM PDT 24
Finished Jul 16 06:53:46 PM PDT 24
Peak memory 206736 kb
Host smart-5048f485-62f1-4b1d-9480-64e604b7490a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21498
07537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2149807537
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.866112376
Short name T1677
Test name
Test status
Simulation time 143957783 ps
CPU time 0.77 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:53:50 PM PDT 24
Peak memory 206704 kb
Host smart-129516b4-65a9-49ef-b254-c97ac690d3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86611
2376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.866112376
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.153406843
Short name T580
Test name
Test status
Simulation time 199113575 ps
CPU time 0.87 seconds
Started Jul 16 06:53:40 PM PDT 24
Finished Jul 16 06:53:42 PM PDT 24
Peak memory 206892 kb
Host smart-241b66b6-458a-4fc8-89f9-e6cf6ba6fd01
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=153406843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.153406843
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2568466208
Short name T707
Test name
Test status
Simulation time 144560883 ps
CPU time 0.75 seconds
Started Jul 16 06:53:42 PM PDT 24
Finished Jul 16 06:53:46 PM PDT 24
Peak memory 206884 kb
Host smart-aa3c75f4-ff93-43d0-a741-2b5f4b0cf341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25684
66208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2568466208
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3939515468
Short name T757
Test name
Test status
Simulation time 56282993 ps
CPU time 0.68 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:51 PM PDT 24
Peak memory 206828 kb
Host smart-adac5d1b-b6e7-408f-9aa7-7326b2554fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39395
15468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3939515468
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.553091787
Short name T1993
Test name
Test status
Simulation time 16661419754 ps
CPU time 37.94 seconds
Started Jul 16 06:53:47 PM PDT 24
Finished Jul 16 06:54:31 PM PDT 24
Peak memory 207124 kb
Host smart-98341562-6758-44d5-864a-4e3539fb698d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55309
1787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.553091787
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3224983712
Short name T1181
Test name
Test status
Simulation time 184002659 ps
CPU time 0.85 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:53:55 PM PDT 24
Peak memory 206852 kb
Host smart-f5dfffb4-fb3c-4e20-a59d-812087200499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32249
83712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3224983712
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1305780797
Short name T2658
Test name
Test status
Simulation time 268114235 ps
CPU time 0.88 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:53:45 PM PDT 24
Peak memory 206664 kb
Host smart-e3981f33-7ec6-4563-9754-553cfbce2f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13057
80797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1305780797
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.4204806073
Short name T1706
Test name
Test status
Simulation time 246552817 ps
CPU time 0.91 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:52 PM PDT 24
Peak memory 206860 kb
Host smart-b285f109-88db-4abd-8630-f27bdce9dd5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42048
06073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.4204806073
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.706518051
Short name T439
Test name
Test status
Simulation time 194954764 ps
CPU time 0.9 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:53:44 PM PDT 24
Peak memory 206876 kb
Host smart-293f4a0b-fe09-43c6-9d8f-eab017d0e468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70651
8051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.706518051
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3330812593
Short name T69
Test name
Test status
Simulation time 156500928 ps
CPU time 0.86 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:53:54 PM PDT 24
Peak memory 206852 kb
Host smart-a88ea2c5-9f13-4982-bd9d-c20107e3d85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33308
12593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3330812593
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3253663029
Short name T1407
Test name
Test status
Simulation time 175981223 ps
CPU time 0.82 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:53:44 PM PDT 24
Peak memory 206828 kb
Host smart-e94f681e-11d7-465e-b085-ba30d5283f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32536
63029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3253663029
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1103126924
Short name T590
Test name
Test status
Simulation time 164528624 ps
CPU time 0.86 seconds
Started Jul 16 06:53:51 PM PDT 24
Finished Jul 16 06:53:58 PM PDT 24
Peak memory 206820 kb
Host smart-d2350f8d-f9f3-4dc7-9a6b-cd0c2faadcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11031
26924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1103126924
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2867714851
Short name T1462
Test name
Test status
Simulation time 200479167 ps
CPU time 0.88 seconds
Started Jul 16 06:53:47 PM PDT 24
Finished Jul 16 06:53:54 PM PDT 24
Peak memory 206876 kb
Host smart-7fba47e8-1f98-47b8-8b3d-af0ee054d2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28677
14851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2867714851
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.665159558
Short name T1784
Test name
Test status
Simulation time 5681913257 ps
CPU time 159.87 seconds
Started Jul 16 06:53:42 PM PDT 24
Finished Jul 16 06:56:25 PM PDT 24
Peak memory 207084 kb
Host smart-a65acf1a-2378-4e3b-93c1-781ff6b7ed2b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=665159558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.665159558
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.96894485
Short name T1304
Test name
Test status
Simulation time 197697719 ps
CPU time 0.88 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:51 PM PDT 24
Peak memory 206772 kb
Host smart-6b956e18-bd65-43df-8d8e-d582f2d06059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96894
485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.96894485
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2672019702
Short name T2175
Test name
Test status
Simulation time 174359829 ps
CPU time 0.82 seconds
Started Jul 16 06:53:49 PM PDT 24
Finished Jul 16 06:53:56 PM PDT 24
Peak memory 206816 kb
Host smart-6e5e8d07-d381-4be9-b18a-cd4e279061df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26720
19702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2672019702
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.1201695721
Short name T395
Test name
Test status
Simulation time 1018223345 ps
CPU time 2.2 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:53:56 PM PDT 24
Peak memory 207052 kb
Host smart-ddf70ef4-243d-4379-9706-d9c1ac6a7dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
95721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1201695721
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3679513443
Short name T534
Test name
Test status
Simulation time 5530197038 ps
CPU time 39.3 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:54:28 PM PDT 24
Peak memory 206920 kb
Host smart-fa51c38a-2309-4572-b0ac-e7e7dfdfd425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36795
13443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3679513443
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2671728769
Short name T1510
Test name
Test status
Simulation time 38347338 ps
CPU time 0.67 seconds
Started Jul 16 06:54:03 PM PDT 24
Finished Jul 16 06:54:06 PM PDT 24
Peak memory 206896 kb
Host smart-4da8eaaf-8608-4172-8a08-5c87b093c9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2671728769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2671728769
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1964597891
Short name T815
Test name
Test status
Simulation time 4198881073 ps
CPU time 5.71 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:53:59 PM PDT 24
Peak memory 206916 kb
Host smart-d0822d04-8bc4-49ed-9eca-c350bd59d713
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1964597891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.1964597891
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.229795166
Short name T194
Test name
Test status
Simulation time 13331732314 ps
CPU time 13.99 seconds
Started Jul 16 06:53:44 PM PDT 24
Finished Jul 16 06:54:02 PM PDT 24
Peak memory 207116 kb
Host smart-13411530-bd7a-4943-9879-4db3996c21a2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=229795166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.229795166
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1690197945
Short name T1499
Test name
Test status
Simulation time 23402146397 ps
CPU time 21.62 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:54:06 PM PDT 24
Peak memory 207132 kb
Host smart-965d4edd-2c4c-4aae-9bbb-743ba8347c1f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1690197945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.1690197945
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.308524397
Short name T2418
Test name
Test status
Simulation time 214109042 ps
CPU time 0.9 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:53:50 PM PDT 24
Peak memory 206692 kb
Host smart-c588bb10-15f8-4977-8e10-62ccb8fbf77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
4397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.308524397
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2095216307
Short name T1185
Test name
Test status
Simulation time 140984116 ps
CPU time 0.8 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:53:50 PM PDT 24
Peak memory 206888 kb
Host smart-30e8e040-ee7e-4d12-895d-047f8f03b49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20952
16307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2095216307
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3060599426
Short name T1739
Test name
Test status
Simulation time 493395142 ps
CPU time 1.49 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:53:51 PM PDT 24
Peak memory 207076 kb
Host smart-840ae58c-e9d2-4933-aeaa-9577bc618164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30605
99426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3060599426
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1215949049
Short name T1451
Test name
Test status
Simulation time 515860489 ps
CPU time 1.38 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:52 PM PDT 24
Peak memory 206832 kb
Host smart-3abdc1c0-e0ee-455b-b0fa-9bd005367e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12159
49049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1215949049
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1195541242
Short name T170
Test name
Test status
Simulation time 11250469867 ps
CPU time 20.26 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 207124 kb
Host smart-659c4189-ab5a-4ea3-9b8e-9d0bad7a90f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11955
41242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1195541242
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2571547783
Short name T903
Test name
Test status
Simulation time 490942864 ps
CPU time 1.42 seconds
Started Jul 16 06:53:44 PM PDT 24
Finished Jul 16 06:53:49 PM PDT 24
Peak memory 206880 kb
Host smart-8708e5b4-87e8-4e86-96b5-a8e1f96f9fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25715
47783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2571547783
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3585384091
Short name T754
Test name
Test status
Simulation time 188593499 ps
CPU time 0.8 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:53:51 PM PDT 24
Peak memory 206884 kb
Host smart-a121dafe-cdea-401e-b972-022eca7f845f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35853
84091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3585384091
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.4074703265
Short name T906
Test name
Test status
Simulation time 51041220 ps
CPU time 0.65 seconds
Started Jul 16 06:53:42 PM PDT 24
Finished Jul 16 06:53:46 PM PDT 24
Peak memory 206864 kb
Host smart-179865a4-9c6d-4138-ad42-a46967825554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40747
03265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.4074703265
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2869923049
Short name T1336
Test name
Test status
Simulation time 1044623801 ps
CPU time 2.26 seconds
Started Jul 16 06:53:44 PM PDT 24
Finished Jul 16 06:53:50 PM PDT 24
Peak memory 207060 kb
Host smart-10bd7939-057b-461a-9c90-403dff1f5343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
23049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2869923049
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.130174162
Short name T1355
Test name
Test status
Simulation time 367150695 ps
CPU time 2.18 seconds
Started Jul 16 06:53:45 PM PDT 24
Finished Jul 16 06:53:52 PM PDT 24
Peak memory 206968 kb
Host smart-e6345bf2-8a4a-4006-9ca3-88cc94a5ecae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13017
4162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.130174162
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1026741302
Short name T2730
Test name
Test status
Simulation time 202541666 ps
CPU time 0.9 seconds
Started Jul 16 06:53:47 PM PDT 24
Finished Jul 16 06:53:53 PM PDT 24
Peak memory 206808 kb
Host smart-56be259e-9bc2-463d-8cbd-f86342bf5ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10267
41302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1026741302
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3227485538
Short name T631
Test name
Test status
Simulation time 181719309 ps
CPU time 0.8 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:53:55 PM PDT 24
Peak memory 206888 kb
Host smart-db922d9a-d7da-45e8-b1bb-a09faafe6603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32274
85538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3227485538
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2358145519
Short name T1137
Test name
Test status
Simulation time 214741420 ps
CPU time 0.96 seconds
Started Jul 16 06:53:47 PM PDT 24
Finished Jul 16 06:53:53 PM PDT 24
Peak memory 206864 kb
Host smart-d223a4e3-18ca-4bea-862e-94b6b2250cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23581
45519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2358145519
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.1510816281
Short name T2253
Test name
Test status
Simulation time 9415341580 ps
CPU time 38 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:54:31 PM PDT 24
Peak memory 207140 kb
Host smart-2a96cf3b-398b-43da-b3c4-40cb082607fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15108
16281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.1510816281
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.4045669287
Short name T1700
Test name
Test status
Simulation time 238557493 ps
CPU time 0.94 seconds
Started Jul 16 06:53:47 PM PDT 24
Finished Jul 16 06:53:53 PM PDT 24
Peak memory 206876 kb
Host smart-a7c4075c-24bc-4a52-99cf-4d5a966272fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
69287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.4045669287
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3644536390
Short name T2271
Test name
Test status
Simulation time 23309426299 ps
CPU time 21.69 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 206836 kb
Host smart-1d1a8ff9-88e4-48df-a361-94e0441aed5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
36390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3644536390
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1039842011
Short name T2471
Test name
Test status
Simulation time 3345895788 ps
CPU time 3.71 seconds
Started Jul 16 06:53:47 PM PDT 24
Finished Jul 16 06:53:56 PM PDT 24
Peak memory 206840 kb
Host smart-9e70de01-aef0-47fe-a3ef-b6bc0946dfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
42011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1039842011
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.488660746
Short name T1566
Test name
Test status
Simulation time 9013935775 ps
CPU time 263.97 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:58:18 PM PDT 24
Peak memory 207176 kb
Host smart-72acb42d-5698-4c79-b37f-32ac694b8736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48866
0746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.488660746
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3061153143
Short name T450
Test name
Test status
Simulation time 5143182729 ps
CPU time 140.87 seconds
Started Jul 16 06:53:41 PM PDT 24
Finished Jul 16 06:56:05 PM PDT 24
Peak memory 207088 kb
Host smart-6cd8551b-3de8-4bb0-b798-60722812b8ea
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3061153143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3061153143
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1205130112
Short name T2568
Test name
Test status
Simulation time 272216726 ps
CPU time 0.96 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:53 PM PDT 24
Peak memory 206772 kb
Host smart-6da93418-2e6f-4387-afb4-32ef9fe06da2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1205130112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1205130112
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.49408372
Short name T1203
Test name
Test status
Simulation time 197831111 ps
CPU time 0.88 seconds
Started Jul 16 06:53:47 PM PDT 24
Finished Jul 16 06:53:53 PM PDT 24
Peak memory 206868 kb
Host smart-cac26866-6c62-4e57-8e5c-2c31e7bbe13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49408
372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.49408372
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1993781743
Short name T2223
Test name
Test status
Simulation time 5409402682 ps
CPU time 151.99 seconds
Started Jul 16 06:53:43 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 207096 kb
Host smart-2feae8e1-4f86-4913-8752-4075dd669440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19937
81743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1993781743
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.486282692
Short name T2018
Test name
Test status
Simulation time 4950646540 ps
CPU time 46.32 seconds
Started Jul 16 06:53:48 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 207132 kb
Host smart-761eac1c-6e58-4fd0-a2cd-53aee181b02f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=486282692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.486282692
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.770226094
Short name T304
Test name
Test status
Simulation time 150979542 ps
CPU time 0.77 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:52 PM PDT 24
Peak memory 206816 kb
Host smart-e58e97a9-c6f1-43ca-b83c-118dc954fe57
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=770226094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.770226094
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.421230723
Short name T751
Test name
Test status
Simulation time 170811779 ps
CPU time 0.79 seconds
Started Jul 16 06:53:46 PM PDT 24
Finished Jul 16 06:53:51 PM PDT 24
Peak memory 206772 kb
Host smart-305ebba7-a006-441a-9765-f3742ef9dd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42123
0723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.421230723
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3029102886
Short name T108
Test name
Test status
Simulation time 209481543 ps
CPU time 0.81 seconds
Started Jul 16 06:53:40 PM PDT 24
Finished Jul 16 06:53:43 PM PDT 24
Peak memory 206824 kb
Host smart-7f5c14de-5c5e-4e08-93f0-7e87afd6e1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30291
02886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3029102886
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.2320556027
Short name T1100
Test name
Test status
Simulation time 151428277 ps
CPU time 0.76 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206664 kb
Host smart-520e2118-eaea-4fa8-9480-8f47d64e5c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
56027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.2320556027
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2612754334
Short name T1195
Test name
Test status
Simulation time 167324221 ps
CPU time 0.85 seconds
Started Jul 16 06:53:52 PM PDT 24
Finished Jul 16 06:53:59 PM PDT 24
Peak memory 206748 kb
Host smart-476bef8d-1308-49ff-a244-0c3b93d98a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26127
54334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2612754334
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.4023567709
Short name T2131
Test name
Test status
Simulation time 156910787 ps
CPU time 0.78 seconds
Started Jul 16 06:53:56 PM PDT 24
Finished Jul 16 06:54:02 PM PDT 24
Peak memory 206884 kb
Host smart-aea70dfe-d4f4-4d61-8592-b873c5adeffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40235
67709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.4023567709
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3951820755
Short name T2100
Test name
Test status
Simulation time 145323535 ps
CPU time 0.75 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206824 kb
Host smart-c755b58d-484f-4a0b-ba14-4f68b5c30e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39518
20755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3951820755
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2642695231
Short name T401
Test name
Test status
Simulation time 263387822 ps
CPU time 0.94 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 206852 kb
Host smart-77bb78c3-5f4e-4d2e-9a3b-4e9dd446a054
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2642695231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2642695231
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3398147552
Short name T2425
Test name
Test status
Simulation time 142692159 ps
CPU time 0.76 seconds
Started Jul 16 06:54:00 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 206888 kb
Host smart-ed6eb63c-3af2-403f-a086-db5ee843e631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33981
47552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3398147552
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1957871126
Short name T2207
Test name
Test status
Simulation time 37120276 ps
CPU time 0.64 seconds
Started Jul 16 06:54:09 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 206812 kb
Host smart-815a7b85-252a-4468-a69b-4fbd4769fb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19578
71126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1957871126
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1662929123
Short name T1295
Test name
Test status
Simulation time 16005112828 ps
CPU time 33.82 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:54:33 PM PDT 24
Peak memory 207088 kb
Host smart-87dd2a83-005a-4320-aa46-65575bae3cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16629
29123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1662929123
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.4079022586
Short name T1778
Test name
Test status
Simulation time 202099999 ps
CPU time 0.87 seconds
Started Jul 16 06:53:53 PM PDT 24
Finished Jul 16 06:53:59 PM PDT 24
Peak memory 206872 kb
Host smart-82c512b1-b110-492c-ac93-588fe70308b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40790
22586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.4079022586
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3272894848
Short name T1821
Test name
Test status
Simulation time 194663672 ps
CPU time 0.88 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206848 kb
Host smart-fca505ff-0d53-45c1-9208-a331106f111c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728
94848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3272894848
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3721304206
Short name T1692
Test name
Test status
Simulation time 217775188 ps
CPU time 0.93 seconds
Started Jul 16 06:54:03 PM PDT 24
Finished Jul 16 06:54:06 PM PDT 24
Peak memory 206820 kb
Host smart-b2b744a1-52e9-4e94-9734-e30664600052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37213
04206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3721304206
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2493545657
Short name T1211
Test name
Test status
Simulation time 172506051 ps
CPU time 0.86 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:54:00 PM PDT 24
Peak memory 206868 kb
Host smart-fc2e5f00-2bb9-47f9-abaf-ee163e3ccf90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24935
45657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2493545657
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.1473609931
Short name T2325
Test name
Test status
Simulation time 192117648 ps
CPU time 0.86 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206732 kb
Host smart-e89f985b-6f5a-4a5a-bbc3-12e498ca5885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
09931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1473609931
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.183464636
Short name T512
Test name
Test status
Simulation time 147922790 ps
CPU time 0.78 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:07 PM PDT 24
Peak memory 206804 kb
Host smart-3a2a695d-5a35-41c8-aa71-dbac8916a1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18346
4636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.183464636
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1175912705
Short name T852
Test name
Test status
Simulation time 159928925 ps
CPU time 0.83 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206868 kb
Host smart-f23a94e6-4ec3-4e01-b45c-c0c0883b785a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11759
12705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1175912705
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.537143409
Short name T1017
Test name
Test status
Simulation time 271823409 ps
CPU time 0.96 seconds
Started Jul 16 06:54:11 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 206836 kb
Host smart-d746d4d5-f3f7-45fa-8098-70a3c6f82c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53714
3409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.537143409
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3062304351
Short name T542
Test name
Test status
Simulation time 7322780651 ps
CPU time 54.81 seconds
Started Jul 16 06:54:02 PM PDT 24
Finished Jul 16 06:54:59 PM PDT 24
Peak memory 207108 kb
Host smart-2fa3bc82-7347-4381-a701-e150b2de9446
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3062304351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3062304351
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3664249853
Short name T919
Test name
Test status
Simulation time 147803111 ps
CPU time 0.82 seconds
Started Jul 16 06:53:52 PM PDT 24
Finished Jul 16 06:53:58 PM PDT 24
Peak memory 206872 kb
Host smart-518260f3-33fc-4a7c-809d-e4d5308f8721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36642
49853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3664249853
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.581973179
Short name T389
Test name
Test status
Simulation time 180988320 ps
CPU time 0.81 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206776 kb
Host smart-a61daa9d-e10d-4512-889a-65ffee79facd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58197
3179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.581973179
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2701807515
Short name T874
Test name
Test status
Simulation time 1278703994 ps
CPU time 2.46 seconds
Started Jul 16 06:54:02 PM PDT 24
Finished Jul 16 06:54:07 PM PDT 24
Peak memory 206992 kb
Host smart-feead449-ab6c-45bc-af6d-9f8bd10ea444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27018
07515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2701807515
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1989661930
Short name T203
Test name
Test status
Simulation time 5015511547 ps
CPU time 44.67 seconds
Started Jul 16 06:54:00 PM PDT 24
Finished Jul 16 06:54:48 PM PDT 24
Peak memory 207120 kb
Host smart-984a49f6-ec5f-460d-b16d-44a090a003df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19896
61930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1989661930
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3075776890
Short name T476
Test name
Test status
Simulation time 57647055 ps
CPU time 0.7 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 206896 kb
Host smart-4a635885-63f7-459a-8347-b248eb6b256a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3075776890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3075776890
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.11054365
Short name T217
Test name
Test status
Simulation time 3900517533 ps
CPU time 4.78 seconds
Started Jul 16 06:53:52 PM PDT 24
Finished Jul 16 06:54:02 PM PDT 24
Peak memory 207128 kb
Host smart-7e2020f7-760d-4bb1-bb56-e7bc59e3c6d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=11054365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.11054365
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3734980569
Short name T1962
Test name
Test status
Simulation time 13400947705 ps
CPU time 12.79 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:13 PM PDT 24
Peak memory 206820 kb
Host smart-62762ccb-ce6a-4be0-a3c0-1a09471cba1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3734980569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3734980569
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2390891429
Short name T975
Test name
Test status
Simulation time 23360441668 ps
CPU time 21.15 seconds
Started Jul 16 06:54:02 PM PDT 24
Finished Jul 16 06:54:26 PM PDT 24
Peak memory 206964 kb
Host smart-c3c586ba-e78d-45ac-866d-2c6fad8d7f75
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2390891429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.2390891429
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3632397253
Short name T870
Test name
Test status
Simulation time 169191968 ps
CPU time 0.8 seconds
Started Jul 16 06:54:03 PM PDT 24
Finished Jul 16 06:54:06 PM PDT 24
Peak memory 206764 kb
Host smart-cb39cb7a-d48e-4536-9755-4005f347314e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36323
97253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3632397253
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.858578013
Short name T1701
Test name
Test status
Simulation time 165265537 ps
CPU time 0.83 seconds
Started Jul 16 06:54:05 PM PDT 24
Finished Jul 16 06:54:09 PM PDT 24
Peak memory 206804 kb
Host smart-5f73c462-98f6-4e6b-a950-952a2a00b52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85857
8013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.858578013
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.575484735
Short name T1069
Test name
Test status
Simulation time 228874959 ps
CPU time 0.94 seconds
Started Jul 16 06:54:00 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 206792 kb
Host smart-0e09c018-bf30-4ae4-8c04-ecf61a5531c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57548
4735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.575484735
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.263449062
Short name T791
Test name
Test status
Simulation time 1296837000 ps
CPU time 2.78 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:03 PM PDT 24
Peak memory 207056 kb
Host smart-c7170575-31d0-4c8e-bf9c-6ab162af7b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26344
9062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.263449062
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.4230793899
Short name T79
Test name
Test status
Simulation time 9046654408 ps
CPU time 17.27 seconds
Started Jul 16 06:53:59 PM PDT 24
Finished Jul 16 06:54:21 PM PDT 24
Peak memory 207148 kb
Host smart-372da7b2-4a71-448b-81e1-34f6110aa034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
93899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.4230793899
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2514878653
Short name T333
Test name
Test status
Simulation time 361895790 ps
CPU time 1.25 seconds
Started Jul 16 06:54:05 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 206852 kb
Host smart-8dd6716c-c9f1-4088-a870-1c3b2ef5e0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25148
78653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2514878653
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2901575888
Short name T44
Test name
Test status
Simulation time 138337098 ps
CPU time 0.74 seconds
Started Jul 16 06:54:14 PM PDT 24
Finished Jul 16 06:54:17 PM PDT 24
Peak memory 206840 kb
Host smart-a605d430-82ea-4dd1-ae79-728c534c9071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29015
75888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2901575888
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2797046868
Short name T2516
Test name
Test status
Simulation time 75984981 ps
CPU time 0.72 seconds
Started Jul 16 06:54:01 PM PDT 24
Finished Jul 16 06:54:05 PM PDT 24
Peak memory 206856 kb
Host smart-26465a18-a202-4c17-9412-cc2d793c4106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27970
46868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2797046868
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1524714797
Short name T17
Test name
Test status
Simulation time 958529640 ps
CPU time 2.11 seconds
Started Jul 16 06:54:03 PM PDT 24
Finished Jul 16 06:54:07 PM PDT 24
Peak memory 207024 kb
Host smart-a201b2f0-098c-490b-9158-a5c8b3958716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15247
14797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1524714797
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2343171816
Short name T173
Test name
Test status
Simulation time 180033671 ps
CPU time 1.43 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 206776 kb
Host smart-cba9b2ed-ad8a-460d-9c47-0ae72dc4a31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23431
71816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2343171816
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3558240329
Short name T1526
Test name
Test status
Simulation time 277194470 ps
CPU time 1.04 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206732 kb
Host smart-4a6aec75-8888-45ce-94bf-b0ec848586f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35582
40329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3558240329
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.325726155
Short name T398
Test name
Test status
Simulation time 151379917 ps
CPU time 0.78 seconds
Started Jul 16 06:54:00 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 206884 kb
Host smart-3f32062b-9859-458e-ae96-31846a433090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32572
6155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.325726155
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3872830250
Short name T1483
Test name
Test status
Simulation time 175907590 ps
CPU time 0.83 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:11 PM PDT 24
Peak memory 206848 kb
Host smart-8cf83847-e0fc-4ef6-b8d3-c4407d2fead8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38728
30250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3872830250
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.306311522
Short name T1340
Test name
Test status
Simulation time 6832783964 ps
CPU time 182.18 seconds
Started Jul 16 06:53:56 PM PDT 24
Finished Jul 16 06:57:04 PM PDT 24
Peak memory 206972 kb
Host smart-4c7b40d1-7a34-46ca-a773-48a6c3a10458
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=306311522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.306311522
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.868228461
Short name T569
Test name
Test status
Simulation time 6378828921 ps
CPU time 54.55 seconds
Started Jul 16 06:54:00 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 207100 kb
Host smart-cadafda9-a9b3-4e09-8b3b-523673b35f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86822
8461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.868228461
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.328837144
Short name T2695
Test name
Test status
Simulation time 213940774 ps
CPU time 0.88 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:07 PM PDT 24
Peak memory 206848 kb
Host smart-fb1f39e0-fac5-4d8d-ab8e-e1c6ffebcdd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32883
7144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.328837144
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1543252908
Short name T509
Test name
Test status
Simulation time 23366944291 ps
CPU time 22.87 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206932 kb
Host smart-c27fc8bb-ade8-4f8b-b77b-b7f0660b2b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15432
52908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1543252908
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1588439822
Short name T308
Test name
Test status
Simulation time 3307836360 ps
CPU time 3.66 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 206732 kb
Host smart-7b3ee42a-2f59-48c1-99e8-69bd509920ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15884
39822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1588439822
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.4232679011
Short name T1620
Test name
Test status
Simulation time 11646334617 ps
CPU time 311.98 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:59:11 PM PDT 24
Peak memory 207108 kb
Host smart-8f77d8ca-2fb8-44d9-b9bc-d7b9b577c0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42326
79011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.4232679011
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.4179933243
Short name T1236
Test name
Test status
Simulation time 7185325520 ps
CPU time 68.72 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:55:08 PM PDT 24
Peak memory 207084 kb
Host smart-ea2ddfa3-f6c6-4f35-a2ae-a27a30a6952e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4179933243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.4179933243
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.23327038
Short name T705
Test name
Test status
Simulation time 245508494 ps
CPU time 0.94 seconds
Started Jul 16 06:53:56 PM PDT 24
Finished Jul 16 06:54:02 PM PDT 24
Peak memory 206864 kb
Host smart-561b285c-599e-4a0c-a178-21f24aaaeed1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=23327038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.23327038
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3481770482
Short name T2158
Test name
Test status
Simulation time 229518295 ps
CPU time 0.88 seconds
Started Jul 16 06:54:03 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 206748 kb
Host smart-2a65f54d-79af-470d-8d59-22536c8f9105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34817
70482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3481770482
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3311993629
Short name T607
Test name
Test status
Simulation time 4746024116 ps
CPU time 44.32 seconds
Started Jul 16 06:53:57 PM PDT 24
Finished Jul 16 06:54:46 PM PDT 24
Peak memory 207044 kb
Host smart-2b13d97a-422f-426e-a545-329a43f5b318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33119
93629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3311993629
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1710455157
Short name T1291
Test name
Test status
Simulation time 5888698070 ps
CPU time 162.09 seconds
Started Jul 16 06:53:53 PM PDT 24
Finished Jul 16 06:56:41 PM PDT 24
Peak memory 207124 kb
Host smart-ef8f6d64-e830-4033-88b2-a19462f1346c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1710455157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1710455157
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.373447655
Short name T1458
Test name
Test status
Simulation time 176122851 ps
CPU time 0.8 seconds
Started Jul 16 06:53:52 PM PDT 24
Finished Jul 16 06:53:59 PM PDT 24
Peak memory 206884 kb
Host smart-5284f640-57ad-4bf8-86ff-48f1a441a647
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=373447655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.373447655
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.124856990
Short name T959
Test name
Test status
Simulation time 203970748 ps
CPU time 0.81 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:11 PM PDT 24
Peak memory 206800 kb
Host smart-b2107594-9c76-481e-8709-03a6b7ce9acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12485
6990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.124856990
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2950047132
Short name T119
Test name
Test status
Simulation time 230048109 ps
CPU time 0.99 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:02 PM PDT 24
Peak memory 206848 kb
Host smart-a1c55673-14bf-4b59-827a-fe6039008ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29500
47132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2950047132
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.4257726491
Short name T2533
Test name
Test status
Simulation time 228702797 ps
CPU time 0.91 seconds
Started Jul 16 06:53:58 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 206816 kb
Host smart-c492c715-9056-476e-b9e7-67acd0941cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42577
26491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.4257726491
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1588767016
Short name T364
Test name
Test status
Simulation time 222095577 ps
CPU time 0.83 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:07 PM PDT 24
Peak memory 206852 kb
Host smart-5393ad96-d397-48fe-afcd-00789dd70c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15887
67016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1588767016
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2672373040
Short name T819
Test name
Test status
Simulation time 166515239 ps
CPU time 0.88 seconds
Started Jul 16 06:53:53 PM PDT 24
Finished Jul 16 06:53:59 PM PDT 24
Peak memory 206908 kb
Host smart-6f679705-3dce-4819-9d02-797e51ace6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26723
73040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2672373040
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3767807111
Short name T1991
Test name
Test status
Simulation time 155432934 ps
CPU time 0.78 seconds
Started Jul 16 06:54:02 PM PDT 24
Finished Jul 16 06:54:05 PM PDT 24
Peak memory 206820 kb
Host smart-4e91b0ee-05a8-4b63-a200-d6dcd3509169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
07111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3767807111
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.157589540
Short name T1978
Test name
Test status
Simulation time 206245111 ps
CPU time 0.87 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:08 PM PDT 24
Peak memory 206820 kb
Host smart-2273d51d-d4b3-4278-81f7-95f1e41cd318
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=157589540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.157589540
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3064718815
Short name T2274
Test name
Test status
Simulation time 143559173 ps
CPU time 0.79 seconds
Started Jul 16 06:53:55 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206788 kb
Host smart-09ddf2f0-4e08-45ca-9326-192c52fad8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30647
18815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3064718815
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2191287123
Short name T2397
Test name
Test status
Simulation time 42861768 ps
CPU time 0.66 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:11 PM PDT 24
Peak memory 206812 kb
Host smart-38f516e2-b48f-403b-9b8e-fb116c233b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21912
87123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2191287123
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2179989680
Short name T1813
Test name
Test status
Simulation time 6813700352 ps
CPU time 15.74 seconds
Started Jul 16 06:54:19 PM PDT 24
Finished Jul 16 06:54:37 PM PDT 24
Peak memory 207108 kb
Host smart-ba1517eb-fc1d-4cb0-a029-eebc3af753b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21799
89680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2179989680
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1435290338
Short name T1830
Test name
Test status
Simulation time 202892502 ps
CPU time 0.88 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:54:01 PM PDT 24
Peak memory 206860 kb
Host smart-7772261d-d633-4e8b-b2a5-b5ebd8d869ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14352
90338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1435290338
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.853862371
Short name T1871
Test name
Test status
Simulation time 224025974 ps
CPU time 0.89 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:11 PM PDT 24
Peak memory 206832 kb
Host smart-31efaa76-e6d7-4d78-a72b-30936e315cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85386
2371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.853862371
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2036439998
Short name T1392
Test name
Test status
Simulation time 156124530 ps
CPU time 0.79 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:13 PM PDT 24
Peak memory 206808 kb
Host smart-298f17f6-c604-40a8-8369-09a5857c43db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20364
39998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2036439998
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2012865389
Short name T1045
Test name
Test status
Simulation time 154559122 ps
CPU time 0.77 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:11 PM PDT 24
Peak memory 206840 kb
Host smart-3fab8484-e453-4a6e-85d4-ba15acacbbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20128
65389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2012865389
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.842424109
Short name T453
Test name
Test status
Simulation time 142466306 ps
CPU time 0.72 seconds
Started Jul 16 06:54:09 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 206836 kb
Host smart-530f7e3f-bc6e-49f5-b340-42ccc42c144a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84242
4109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.842424109
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2599810200
Short name T1113
Test name
Test status
Simulation time 151075575 ps
CPU time 0.82 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:54:00 PM PDT 24
Peak memory 206856 kb
Host smart-98833e4c-2028-4515-a48f-89a95fd75ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25998
10200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2599810200
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.188722938
Short name T91
Test name
Test status
Simulation time 170123340 ps
CPU time 0.76 seconds
Started Jul 16 06:53:54 PM PDT 24
Finished Jul 16 06:54:00 PM PDT 24
Peak memory 206896 kb
Host smart-7db1c9e2-d6a7-4338-92af-67aef81ab2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18872
2938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.188722938
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1025073247
Short name T608
Test name
Test status
Simulation time 245729584 ps
CPU time 0.95 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206808 kb
Host smart-4ea8a96c-4a16-46f5-ac38-5e16895e47d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10250
73247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1025073247
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.455364686
Short name T2065
Test name
Test status
Simulation time 3280347118 ps
CPU time 91.09 seconds
Started Jul 16 06:54:08 PM PDT 24
Finished Jul 16 06:55:44 PM PDT 24
Peak memory 206992 kb
Host smart-1f9a0112-fdfa-4632-a2cb-fa63434b87c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=455364686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.455364686
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1493081447
Short name T452
Test name
Test status
Simulation time 185590207 ps
CPU time 0.88 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206816 kb
Host smart-70adba80-9fa9-4269-a891-740e0d5d7f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14930
81447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1493081447
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4283435496
Short name T335
Test name
Test status
Simulation time 172555673 ps
CPU time 0.78 seconds
Started Jul 16 06:53:59 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 206756 kb
Host smart-2dcf0b89-ecc2-4ef0-be93-91d5b5ea2f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42834
35496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4283435496
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2824704225
Short name T2071
Test name
Test status
Simulation time 769834924 ps
CPU time 1.72 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 206988 kb
Host smart-3c2230d8-c096-45ec-ac97-c9e0a3c78c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28247
04225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2824704225
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1363181389
Short name T2632
Test name
Test status
Simulation time 7289555641 ps
CPU time 206.75 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:57:39 PM PDT 24
Peak memory 207016 kb
Host smart-bd7b478a-8faf-426b-8ba5-fa619bd3f423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13631
81389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1363181389
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1706033667
Short name T1446
Test name
Test status
Simulation time 102283602 ps
CPU time 0.75 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206896 kb
Host smart-f9a74c45-3f39-4c40-9a75-b5a2ed04fbb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1706033667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1706033667
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1718070817
Short name T15
Test name
Test status
Simulation time 3899025122 ps
CPU time 5.94 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:18 PM PDT 24
Peak memory 207072 kb
Host smart-076a27f1-313e-4309-af7f-cfe6712f2059
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1718070817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1718070817
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2188888210
Short name T2333
Test name
Test status
Simulation time 13350377135 ps
CPU time 11.78 seconds
Started Jul 16 06:54:01 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 206984 kb
Host smart-e294a9b9-48d6-420e-ad5e-a5c3bdeedd36
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2188888210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2188888210
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1132558032
Short name T687
Test name
Test status
Simulation time 23350978281 ps
CPU time 22.99 seconds
Started Jul 16 06:53:59 PM PDT 24
Finished Jul 16 06:54:26 PM PDT 24
Peak memory 206952 kb
Host smart-7069fc88-9f4d-4262-9859-d0a6bd3991e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1132558032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.1132558032
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.839032828
Short name T2584
Test name
Test status
Simulation time 170567527 ps
CPU time 0.81 seconds
Started Jul 16 06:53:59 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 206888 kb
Host smart-6502d695-4869-409b-baa5-6491e88b9d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83903
2828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.839032828
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1088502489
Short name T2401
Test name
Test status
Simulation time 143354678 ps
CPU time 0.74 seconds
Started Jul 16 06:53:59 PM PDT 24
Finished Jul 16 06:54:04 PM PDT 24
Peak memory 206888 kb
Host smart-10a39892-b3e1-4d8d-954d-c589c3496a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10885
02489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1088502489
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2289108168
Short name T1421
Test name
Test status
Simulation time 317288259 ps
CPU time 1.16 seconds
Started Jul 16 06:54:22 PM PDT 24
Finished Jul 16 06:54:24 PM PDT 24
Peak memory 206812 kb
Host smart-2eff51f7-b5f0-4df1-a6fb-4340d9cc4a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22891
08168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2289108168
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.462483495
Short name T617
Test name
Test status
Simulation time 1469465010 ps
CPU time 2.91 seconds
Started Jul 16 06:54:08 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 207008 kb
Host smart-be3b16eb-f734-4f90-b188-d0655f4d2ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46248
3495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.462483495
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.517095383
Short name T468
Test name
Test status
Simulation time 328030656 ps
CPU time 1.25 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 206868 kb
Host smart-1cfb652a-26b1-4272-b760-7b3539806b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51709
5383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.517095383
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.45489241
Short name T42
Test name
Test status
Simulation time 176450240 ps
CPU time 0.86 seconds
Started Jul 16 06:54:11 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 206876 kb
Host smart-2ce2f7ff-55e3-4ca0-b110-d4d7e371720d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45489
241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.45489241
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3546365019
Short name T2116
Test name
Test status
Simulation time 44851854 ps
CPU time 0.66 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206888 kb
Host smart-02c63be9-4121-42bd-b32c-48ca961094f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35463
65019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3546365019
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2565689074
Short name T761
Test name
Test status
Simulation time 886843886 ps
CPU time 2.05 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 206900 kb
Host smart-2b92b77c-6650-4c3c-a538-abdc10b7f2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25656
89074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2565689074
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3783048709
Short name T1146
Test name
Test status
Simulation time 179161262 ps
CPU time 1.21 seconds
Started Jul 16 06:54:15 PM PDT 24
Finished Jul 16 06:54:18 PM PDT 24
Peak memory 207020 kb
Host smart-4e54f486-6b44-4586-b432-1a6e5cbcd45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37830
48709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3783048709
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3228301563
Short name T1886
Test name
Test status
Simulation time 220192631 ps
CPU time 0.89 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206884 kb
Host smart-ebfb4a62-8d44-429b-8c45-24b90646430d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32283
01563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3228301563
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2413364294
Short name T1664
Test name
Test status
Simulation time 148083933 ps
CPU time 0.78 seconds
Started Jul 16 06:54:05 PM PDT 24
Finished Jul 16 06:54:09 PM PDT 24
Peak memory 206876 kb
Host smart-90d01931-4b55-42ba-a4aa-077dd94d5ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24133
64294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2413364294
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.344934217
Short name T424
Test name
Test status
Simulation time 222665955 ps
CPU time 0.91 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 206884 kb
Host smart-93b4ecef-c8a2-486c-9b77-5bc87662d4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34493
4217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.344934217
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.3598256115
Short name T2648
Test name
Test status
Simulation time 8793894282 ps
CPU time 251.82 seconds
Started Jul 16 06:54:15 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 207000 kb
Host smart-cc18a94b-c603-421c-97cc-f1c0814ddf2b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3598256115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.3598256115
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1276796997
Short name T800
Test name
Test status
Simulation time 253015631 ps
CPU time 0.89 seconds
Started Jul 16 06:54:09 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 207028 kb
Host smart-1087dc46-c156-48da-afb2-fb1e02e408f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12767
96997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1276796997
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1424691945
Short name T1134
Test name
Test status
Simulation time 23305561976 ps
CPU time 26.17 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:37 PM PDT 24
Peak memory 206924 kb
Host smart-271dad00-024e-4b3a-b978-2c6134e1e5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14246
91945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1424691945
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3535640589
Short name T1564
Test name
Test status
Simulation time 3265310067 ps
CPU time 3.87 seconds
Started Jul 16 06:54:09 PM PDT 24
Finished Jul 16 06:54:18 PM PDT 24
Peak memory 206884 kb
Host smart-a2376671-5e24-40b2-9ec1-e973dfc976b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35356
40589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3535640589
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2657948298
Short name T1859
Test name
Test status
Simulation time 8374002571 ps
CPU time 74.74 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:55:22 PM PDT 24
Peak memory 207148 kb
Host smart-e6306845-8a1e-495c-9b4c-4b7906a82761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
48298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2657948298
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.1331817385
Short name T2318
Test name
Test status
Simulation time 4132522130 ps
CPU time 111.26 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:56:05 PM PDT 24
Peak memory 207004 kb
Host smart-82f98737-78b0-46d5-8a45-cb093f979159
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1331817385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.1331817385
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3858986694
Short name T1482
Test name
Test status
Simulation time 256504882 ps
CPU time 0.89 seconds
Started Jul 16 06:54:23 PM PDT 24
Finished Jul 16 06:54:30 PM PDT 24
Peak memory 206852 kb
Host smart-20c22cd9-8d65-448e-a2b7-a576194f9cac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3858986694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3858986694
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2510282852
Short name T2512
Test name
Test status
Simulation time 183148312 ps
CPU time 0.82 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:07 PM PDT 24
Peak memory 206884 kb
Host smart-e8cb9d31-54bd-4ff4-9c30-120c6662d057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25102
82852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2510282852
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.746125605
Short name T2574
Test name
Test status
Simulation time 6131391711 ps
CPU time 42.88 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:53 PM PDT 24
Peak memory 207124 kb
Host smart-296df237-b408-4195-9cea-199efdfc4b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74612
5605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.746125605
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.997439164
Short name T2565
Test name
Test status
Simulation time 7595909922 ps
CPU time 204.42 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:57:36 PM PDT 24
Peak memory 207048 kb
Host smart-1991d642-afbc-4530-abe5-241c679d9cc6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=997439164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.997439164
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1498932496
Short name T2037
Test name
Test status
Simulation time 167274261 ps
CPU time 0.82 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:08 PM PDT 24
Peak memory 206896 kb
Host smart-3389b3dc-4937-4dd9-abcd-ff277086d014
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1498932496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1498932496
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2887922186
Short name T1480
Test name
Test status
Simulation time 183833203 ps
CPU time 0.82 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:11 PM PDT 24
Peak memory 206884 kb
Host smart-20930b1d-0040-4459-8fb5-78a7ef22cad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28879
22186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2887922186
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.4257249604
Short name T2297
Test name
Test status
Simulation time 228023978 ps
CPU time 0.89 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206872 kb
Host smart-d365b17c-6c90-4dd1-a13c-7686428005a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42572
49604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.4257249604
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2573718987
Short name T93
Test name
Test status
Simulation time 157053688 ps
CPU time 0.84 seconds
Started Jul 16 06:54:16 PM PDT 24
Finished Jul 16 06:54:19 PM PDT 24
Peak memory 206860 kb
Host smart-b8cbc540-a5ca-486a-953e-369de0c42a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25737
18987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2573718987
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3860290159
Short name T1262
Test name
Test status
Simulation time 144045849 ps
CPU time 0.75 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 206728 kb
Host smart-397563ee-50fb-42df-b428-1a16b38f8cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
90159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3860290159
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.601254857
Short name T1883
Test name
Test status
Simulation time 165392789 ps
CPU time 0.78 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:08 PM PDT 24
Peak memory 206816 kb
Host smart-46c01f6c-797a-45e7-a9b4-4313af0bc12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60125
4857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.601254857
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1466352201
Short name T1093
Test name
Test status
Simulation time 161085696 ps
CPU time 0.78 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 206880 kb
Host smart-8953bf65-a08a-45c3-a902-355e18e4186d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14663
52201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1466352201
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3962787994
Short name T1921
Test name
Test status
Simulation time 204801919 ps
CPU time 0.84 seconds
Started Jul 16 06:54:05 PM PDT 24
Finished Jul 16 06:54:09 PM PDT 24
Peak memory 206884 kb
Host smart-548a80b4-82b2-4ac5-8a1e-5a1077c1bc9d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3962787994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3962787994
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.97207989
Short name T766
Test name
Test status
Simulation time 182658456 ps
CPU time 0.81 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:10 PM PDT 24
Peak memory 206732 kb
Host smart-34e99a68-a404-455d-9d3a-b4d3b3c9b235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97207
989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.97207989
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2323920434
Short name T982
Test name
Test status
Simulation time 86009954 ps
CPU time 0.7 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:07 PM PDT 24
Peak memory 206848 kb
Host smart-9249f9e4-a9e1-4929-846a-39ec5548f733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23239
20434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2323920434
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3538671808
Short name T2121
Test name
Test status
Simulation time 10227858109 ps
CPU time 21.44 seconds
Started Jul 16 06:54:19 PM PDT 24
Finished Jul 16 06:54:42 PM PDT 24
Peak memory 207180 kb
Host smart-46aa4b7b-0ba8-4ad1-882d-ae07789352d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35386
71808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3538671808
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.971973352
Short name T1300
Test name
Test status
Simulation time 165344015 ps
CPU time 0.81 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 206732 kb
Host smart-e5d0b3c6-5806-4715-9074-5a90f163d780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97197
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.971973352
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2952488073
Short name T1574
Test name
Test status
Simulation time 246774911 ps
CPU time 0.9 seconds
Started Jul 16 06:54:04 PM PDT 24
Finished Jul 16 06:54:08 PM PDT 24
Peak memory 206912 kb
Host smart-da51cdec-61d3-4989-9cc4-505758914eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29524
88073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2952488073
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2147766233
Short name T2451
Test name
Test status
Simulation time 245957590 ps
CPU time 0.87 seconds
Started Jul 16 06:54:05 PM PDT 24
Finished Jul 16 06:54:09 PM PDT 24
Peak memory 206884 kb
Host smart-74d28e74-a7cd-423b-898e-31b0d5013d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21477
66233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2147766233
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.222406852
Short name T2263
Test name
Test status
Simulation time 182481330 ps
CPU time 0.85 seconds
Started Jul 16 06:54:14 PM PDT 24
Finished Jul 16 06:54:17 PM PDT 24
Peak memory 206820 kb
Host smart-3c0a7e1f-f865-4205-bdb1-67fb314a28c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
6852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.222406852
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2612390155
Short name T621
Test name
Test status
Simulation time 132496153 ps
CPU time 0.73 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206728 kb
Host smart-6d946f2a-0321-4a8f-af9f-03f47d9359fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26123
90155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2612390155
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3019530293
Short name T430
Test name
Test status
Simulation time 161017486 ps
CPU time 0.77 seconds
Started Jul 16 06:54:08 PM PDT 24
Finished Jul 16 06:54:13 PM PDT 24
Peak memory 206904 kb
Host smart-9aa4fe00-57d9-45ff-aff2-2b68b745c83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30195
30293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3019530293
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1681414381
Short name T779
Test name
Test status
Simulation time 164419702 ps
CPU time 0.78 seconds
Started Jul 16 06:54:08 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 206860 kb
Host smart-3eab514a-ed7f-40af-95aa-798558cc1027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
14381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1681414381
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2193873093
Short name T841
Test name
Test status
Simulation time 236709467 ps
CPU time 0.96 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 206860 kb
Host smart-c1aa477c-edd3-4b52-9c22-3fce3646e3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21938
73093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2193873093
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3771784997
Short name T1058
Test name
Test status
Simulation time 5705140173 ps
CPU time 148.38 seconds
Started Jul 16 06:54:15 PM PDT 24
Finished Jul 16 06:56:45 PM PDT 24
Peak memory 207044 kb
Host smart-8ba08c46-292a-4e6e-8264-98244b2f970c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3771784997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3771784997
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3748082493
Short name T2653
Test name
Test status
Simulation time 204470045 ps
CPU time 0.85 seconds
Started Jul 16 06:54:16 PM PDT 24
Finished Jul 16 06:54:19 PM PDT 24
Peak memory 206860 kb
Host smart-91771dd6-23c3-489c-b907-3a3f50b4354f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37480
82493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3748082493
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.653176240
Short name T571
Test name
Test status
Simulation time 176240920 ps
CPU time 0.78 seconds
Started Jul 16 06:54:11 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 206856 kb
Host smart-ecb4a481-21d6-48f4-9db4-6625ff0aa7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65317
6240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.653176240
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.1504267957
Short name T741
Test name
Test status
Simulation time 1159987387 ps
CPU time 2.44 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:54:21 PM PDT 24
Peak memory 206996 kb
Host smart-6d7fce4a-cc6d-4af5-8d65-077eae81168d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15042
67957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.1504267957
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.382639884
Short name T2161
Test name
Test status
Simulation time 6433782720 ps
CPU time 63.92 seconds
Started Jul 16 06:54:12 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 207064 kb
Host smart-eb43b815-7273-4b3a-ab8b-d50ab64bbc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38263
9884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.382639884
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.978985761
Short name T1627
Test name
Test status
Simulation time 64706156 ps
CPU time 0.74 seconds
Started Jul 16 06:54:34 PM PDT 24
Finished Jul 16 06:54:35 PM PDT 24
Peak memory 206912 kb
Host smart-c931237e-74d0-4b10-83d9-580682907de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=978985761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.978985761
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2787256191
Short name T738
Test name
Test status
Simulation time 4180717033 ps
CPU time 5.49 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:54:25 PM PDT 24
Peak memory 206932 kb
Host smart-958d63d2-372f-4a0a-baec-26bcd88ae582
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2787256191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2787256191
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1818395604
Short name T668
Test name
Test status
Simulation time 13356190784 ps
CPU time 12.12 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:26 PM PDT 24
Peak memory 206940 kb
Host smart-c5e48ac4-a6a6-4fb1-9665-95872fddd29b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1818395604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1818395604
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1718090993
Short name T11
Test name
Test status
Simulation time 23362684443 ps
CPU time 26.97 seconds
Started Jul 16 06:54:08 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 207120 kb
Host smart-70feeaef-26a6-48b0-827b-058f9af2e3b9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1718090993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1718090993
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.435272508
Short name T1267
Test name
Test status
Simulation time 177503365 ps
CPU time 0.78 seconds
Started Jul 16 06:54:23 PM PDT 24
Finished Jul 16 06:54:25 PM PDT 24
Peak memory 206836 kb
Host smart-c093fbe4-8dc6-4623-b285-3cb235aff5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43527
2508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.435272508
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.4157890192
Short name T2182
Test name
Test status
Simulation time 144968346 ps
CPU time 0.77 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206872 kb
Host smart-5feb098a-b207-43ec-ad52-66919ca6fad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41578
90192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.4157890192
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.326624021
Short name T1082
Test name
Test status
Simulation time 266506646 ps
CPU time 1.03 seconds
Started Jul 16 06:54:10 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206596 kb
Host smart-acf3926f-ed47-4db7-969f-37abc12728ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
4021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.326624021
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1497560157
Short name T370
Test name
Test status
Simulation time 1190229709 ps
CPU time 2.36 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 207096 kb
Host smart-498d1820-3bac-4307-878a-d1af4df85769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14975
60157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1497560157
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3991630224
Short name T990
Test name
Test status
Simulation time 15918121831 ps
CPU time 30.86 seconds
Started Jul 16 06:54:13 PM PDT 24
Finished Jul 16 06:54:47 PM PDT 24
Peak memory 207016 kb
Host smart-985628d6-3465-4b38-b72a-afcc2af99b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39916
30224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3991630224
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1230254121
Short name T382
Test name
Test status
Simulation time 420186873 ps
CPU time 1.41 seconds
Started Jul 16 06:54:08 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 206864 kb
Host smart-75d526ce-73c8-4870-9c32-f67bcd7b079a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12302
54121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1230254121
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2888755003
Short name T1807
Test name
Test status
Simulation time 139005059 ps
CPU time 0.75 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:11 PM PDT 24
Peak memory 206844 kb
Host smart-6eeb2897-a728-408a-93dc-a084bc6172ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28887
55003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2888755003
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2017814036
Short name T1428
Test name
Test status
Simulation time 71761476 ps
CPU time 0.69 seconds
Started Jul 16 06:54:15 PM PDT 24
Finished Jul 16 06:54:18 PM PDT 24
Peak memory 206848 kb
Host smart-a8ff3f7d-c7dc-4be3-81f0-e59bc2756bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20178
14036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2017814036
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2492498118
Short name T2589
Test name
Test status
Simulation time 899753936 ps
CPU time 2.12 seconds
Started Jul 16 06:54:06 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 206880 kb
Host smart-2980501d-89c4-4f81-bb99-e4869a92cc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24924
98118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2492498118
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.614020240
Short name T2677
Test name
Test status
Simulation time 201556146 ps
CPU time 1.96 seconds
Started Jul 16 06:54:09 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206996 kb
Host smart-42f0b888-d625-46d6-a96a-c9a1740a449b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61402
0240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.614020240
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3409757522
Short name T1845
Test name
Test status
Simulation time 230918422 ps
CPU time 0.9 seconds
Started Jul 16 06:54:11 PM PDT 24
Finished Jul 16 06:54:15 PM PDT 24
Peak memory 206880 kb
Host smart-0622885a-1de3-4aa2-8eb6-69fbc8f5c6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
57522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3409757522
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1210210718
Short name T2134
Test name
Test status
Simulation time 155092844 ps
CPU time 0.74 seconds
Started Jul 16 06:54:09 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 206852 kb
Host smart-33174781-f548-46a6-9cc5-627e76f4836d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12102
10718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1210210718
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1224239487
Short name T1782
Test name
Test status
Simulation time 244946877 ps
CPU time 0.92 seconds
Started Jul 16 06:54:09 PM PDT 24
Finished Jul 16 06:54:14 PM PDT 24
Peak memory 206856 kb
Host smart-dc70d814-67ab-43dd-82e4-9e7642a2a6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12242
39487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1224239487
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.3869149410
Short name T1786
Test name
Test status
Simulation time 8456590529 ps
CPU time 76.47 seconds
Started Jul 16 06:54:11 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 207136 kb
Host smart-3d45b8dd-1f8e-4215-885f-f4c1379e224b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3869149410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.3869149410
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2817921042
Short name T1648
Test name
Test status
Simulation time 223858254 ps
CPU time 0.83 seconds
Started Jul 16 06:54:30 PM PDT 24
Finished Jul 16 06:54:32 PM PDT 24
Peak memory 206836 kb
Host smart-fe5286b9-9dcb-4b94-b06c-59b7eed4ba8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28179
21042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2817921042
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.750575441
Short name T209
Test name
Test status
Simulation time 23346430327 ps
CPU time 25.66 seconds
Started Jul 16 06:54:24 PM PDT 24
Finished Jul 16 06:54:51 PM PDT 24
Peak memory 206864 kb
Host smart-a7e07e0d-6acc-451d-9ed4-91d74c8f92b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75057
5441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.750575441
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1900703930
Short name T1420
Test name
Test status
Simulation time 3347770424 ps
CPU time 4.16 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206956 kb
Host smart-977ea0cb-5c92-427d-8e73-7a3054d13996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19007
03930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1900703930
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2843175810
Short name T793
Test name
Test status
Simulation time 9334576966 ps
CPU time 65.97 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 207076 kb
Host smart-4a71a1a8-8c23-40d3-9e71-a82b61f7365c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28431
75810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2843175810
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.734727205
Short name T1541
Test name
Test status
Simulation time 4692534894 ps
CPU time 33.74 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:45 PM PDT 24
Peak memory 207092 kb
Host smart-2a1fdd16-4309-4056-a21c-0146ceed0b58
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=734727205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.734727205
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.4047583501
Short name T656
Test name
Test status
Simulation time 265175020 ps
CPU time 0.94 seconds
Started Jul 16 06:54:13 PM PDT 24
Finished Jul 16 06:54:17 PM PDT 24
Peak memory 206880 kb
Host smart-7c797ab5-e588-4421-b25a-00b8ac52ce10
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4047583501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.4047583501
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.208799425
Short name T2662
Test name
Test status
Simulation time 207594944 ps
CPU time 0.87 seconds
Started Jul 16 06:54:23 PM PDT 24
Finished Jul 16 06:54:25 PM PDT 24
Peak memory 206808 kb
Host smart-adc7376f-dbfe-48d2-9cd2-46210f5e9255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20879
9425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.208799425
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.76968326
Short name T1800
Test name
Test status
Simulation time 4813617799 ps
CPU time 128.6 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:56:20 PM PDT 24
Peak memory 207072 kb
Host smart-387fdf63-d863-489a-8533-bef634702b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76968
326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.76968326
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.454501853
Short name T2438
Test name
Test status
Simulation time 5305670300 ps
CPU time 39.58 seconds
Started Jul 16 06:54:08 PM PDT 24
Finished Jul 16 06:54:52 PM PDT 24
Peak memory 207080 kb
Host smart-59e2313e-1fbf-4c29-8a77-4059c5af396a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=454501853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.454501853
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2987637854
Short name T748
Test name
Test status
Simulation time 161051933 ps
CPU time 0.82 seconds
Started Jul 16 06:54:24 PM PDT 24
Finished Jul 16 06:54:26 PM PDT 24
Peak memory 206864 kb
Host smart-76c6da43-3f81-4ec9-a0f1-57143069c754
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2987637854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2987637854
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2604203628
Short name T2456
Test name
Test status
Simulation time 147169321 ps
CPU time 0.74 seconds
Started Jul 16 06:54:16 PM PDT 24
Finished Jul 16 06:54:19 PM PDT 24
Peak memory 206804 kb
Host smart-af998437-492b-4dcd-8afc-24666ce2c832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26042
03628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2604203628
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.886101689
Short name T132
Test name
Test status
Simulation time 175715245 ps
CPU time 0.79 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:13 PM PDT 24
Peak memory 206896 kb
Host smart-7e1adaf9-d868-42d3-b8c2-308581b724f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88610
1689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.886101689
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2156340828
Short name T1839
Test name
Test status
Simulation time 209521547 ps
CPU time 0.92 seconds
Started Jul 16 06:54:31 PM PDT 24
Finished Jul 16 06:54:33 PM PDT 24
Peak memory 206852 kb
Host smart-e1368574-9cf0-4339-88ca-66c701dc7d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21563
40828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2156340828
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3112490485
Short name T1606
Test name
Test status
Simulation time 152452601 ps
CPU time 0.82 seconds
Started Jul 16 06:54:14 PM PDT 24
Finished Jul 16 06:54:18 PM PDT 24
Peak memory 206852 kb
Host smart-d6edcb37-8a31-4d2f-a254-38e1d5e387e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
90485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3112490485
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.682803691
Short name T310
Test name
Test status
Simulation time 190592467 ps
CPU time 0.85 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:13 PM PDT 24
Peak memory 206864 kb
Host smart-c0d06565-d13e-426e-8b42-562c396fb6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68280
3691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.682803691
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2646974510
Short name T167
Test name
Test status
Simulation time 197784072 ps
CPU time 0.82 seconds
Started Jul 16 06:54:07 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 206896 kb
Host smart-cf8213e2-f160-4784-9290-e2ff0bdf0e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
74510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2646974510
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.31162438
Short name T317
Test name
Test status
Simulation time 218903076 ps
CPU time 0.9 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:54:20 PM PDT 24
Peak memory 206804 kb
Host smart-30fd53f7-8dfa-448f-bddf-a3464799a627
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=31162438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.31162438
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2376055613
Short name T762
Test name
Test status
Simulation time 181177954 ps
CPU time 0.77 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:54:20 PM PDT 24
Peak memory 206768 kb
Host smart-17d6fa08-c7ce-4e77-af1a-6f2cdb826934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23760
55613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2376055613
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2695738101
Short name T34
Test name
Test status
Simulation time 65018878 ps
CPU time 0.66 seconds
Started Jul 16 06:54:30 PM PDT 24
Finished Jul 16 06:54:31 PM PDT 24
Peak memory 206796 kb
Host smart-ef90481c-431b-4d1e-acca-f7ff5342889e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26957
38101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2695738101
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.344774458
Short name T1824
Test name
Test status
Simulation time 8695715556 ps
CPU time 20.18 seconds
Started Jul 16 06:54:28 PM PDT 24
Finished Jul 16 06:54:49 PM PDT 24
Peak memory 207128 kb
Host smart-f13e292f-cc00-4103-84f6-ec83d3133c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34477
4458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.344774458
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3275851002
Short name T1576
Test name
Test status
Simulation time 158402765 ps
CPU time 0.81 seconds
Started Jul 16 06:54:28 PM PDT 24
Finished Jul 16 06:54:30 PM PDT 24
Peak memory 206884 kb
Host smart-6c06e946-2864-482e-ad0d-d44d40ade592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32758
51002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3275851002
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1844643059
Short name T319
Test name
Test status
Simulation time 163879488 ps
CPU time 0.8 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:54:20 PM PDT 24
Peak memory 206860 kb
Host smart-11e64728-96f5-46a8-8339-401887185f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18446
43059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1844643059
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.831036659
Short name T2463
Test name
Test status
Simulation time 221513361 ps
CPU time 0.89 seconds
Started Jul 16 06:54:18 PM PDT 24
Finished Jul 16 06:54:20 PM PDT 24
Peak memory 206888 kb
Host smart-44f2b41d-8147-4769-93a7-b0a4b0e12910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83103
6659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.831036659
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1966986508
Short name T318
Test name
Test status
Simulation time 205327797 ps
CPU time 0.88 seconds
Started Jul 16 06:54:31 PM PDT 24
Finished Jul 16 06:54:33 PM PDT 24
Peak memory 206884 kb
Host smart-88792df5-34c5-434b-a71e-c84b9d5a2784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19669
86508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1966986508
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.814032879
Short name T2594
Test name
Test status
Simulation time 174279784 ps
CPU time 0.75 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:54:20 PM PDT 24
Peak memory 206908 kb
Host smart-41c86821-bd2e-4864-a935-e4ce69f088bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81403
2879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.814032879
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3303860417
Short name T1078
Test name
Test status
Simulation time 183165448 ps
CPU time 0.81 seconds
Started Jul 16 06:54:18 PM PDT 24
Finished Jul 16 06:54:21 PM PDT 24
Peak memory 206728 kb
Host smart-79d659b5-ef85-4522-8415-e3ca3270c4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33038
60417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3303860417
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.646044345
Short name T588
Test name
Test status
Simulation time 174584788 ps
CPU time 0.8 seconds
Started Jul 16 06:54:18 PM PDT 24
Finished Jul 16 06:54:21 PM PDT 24
Peak memory 206848 kb
Host smart-8a49464c-3bc6-4811-a95b-2336c01d1089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64604
4345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.646044345
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2322741408
Short name T689
Test name
Test status
Simulation time 216619661 ps
CPU time 0.93 seconds
Started Jul 16 06:54:28 PM PDT 24
Finished Jul 16 06:54:30 PM PDT 24
Peak memory 206828 kb
Host smart-fc533e09-bd04-4bf9-9074-bd4255b4ed9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23227
41408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2322741408
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2981351923
Short name T1174
Test name
Test status
Simulation time 3162643291 ps
CPU time 23.53 seconds
Started Jul 16 06:54:25 PM PDT 24
Finished Jul 16 06:54:49 PM PDT 24
Peak memory 207272 kb
Host smart-8555387e-7dee-4530-be28-b2d71e044f1b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2981351923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2981351923
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.579511151
Short name T2111
Test name
Test status
Simulation time 182575128 ps
CPU time 0.83 seconds
Started Jul 16 06:54:27 PM PDT 24
Finished Jul 16 06:54:29 PM PDT 24
Peak memory 206832 kb
Host smart-720cc289-5f58-48a9-ac51-5a1d991188df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57951
1151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.579511151
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2580212567
Short name T1123
Test name
Test status
Simulation time 172551161 ps
CPU time 0.84 seconds
Started Jul 16 06:54:25 PM PDT 24
Finished Jul 16 06:54:27 PM PDT 24
Peak memory 206864 kb
Host smart-cf42959d-7e20-4b22-b606-f56b645d5d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25802
12567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2580212567
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1117607322
Short name T692
Test name
Test status
Simulation time 571891167 ps
CPU time 1.57 seconds
Started Jul 16 06:54:23 PM PDT 24
Finished Jul 16 06:54:26 PM PDT 24
Peak memory 206856 kb
Host smart-5d6923b8-87af-4553-b3b5-5cc760e1f816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
07322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1117607322
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.712799533
Short name T911
Test name
Test status
Simulation time 6502453371 ps
CPU time 185.63 seconds
Started Jul 16 06:54:20 PM PDT 24
Finished Jul 16 06:57:27 PM PDT 24
Peak memory 207076 kb
Host smart-0153bbac-c6f1-4410-9786-7d5d6afc6bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71279
9533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.712799533
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1240316429
Short name T2246
Test name
Test status
Simulation time 32235394 ps
CPU time 0.65 seconds
Started Jul 16 06:48:11 PM PDT 24
Finished Jul 16 06:48:12 PM PDT 24
Peak memory 206784 kb
Host smart-7348b696-98ba-4c19-a201-144ebeee4a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1240316429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1240316429
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2185250364
Short name T503
Test name
Test status
Simulation time 4300378979 ps
CPU time 4.97 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:48:05 PM PDT 24
Peak memory 206772 kb
Host smart-b4c32563-c598-4a72-b183-c7447df43f26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2185250364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2185250364
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3843053184
Short name T2608
Test name
Test status
Simulation time 13391819461 ps
CPU time 13.33 seconds
Started Jul 16 06:48:03 PM PDT 24
Finished Jul 16 06:48:17 PM PDT 24
Peak memory 206948 kb
Host smart-bb8ef2b5-2366-4c52-b0bd-ea1e50ac3be2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3843053184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3843053184
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.799601710
Short name T1047
Test name
Test status
Simulation time 23360373581 ps
CPU time 22.71 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 206900 kb
Host smart-38fd4a5d-f1b6-40ca-9259-d4381793e3eb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=799601710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.799601710
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.4029663237
Short name T377
Test name
Test status
Simulation time 241552419 ps
CPU time 0.9 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:48:00 PM PDT 24
Peak memory 206860 kb
Host smart-296b7e6b-b60f-451b-afd8-1d92fb291fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40296
63237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.4029663237
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3316275310
Short name T1556
Test name
Test status
Simulation time 192461773 ps
CPU time 0.9 seconds
Started Jul 16 06:47:59 PM PDT 24
Finished Jul 16 06:48:02 PM PDT 24
Peak memory 206868 kb
Host smart-d0d7606c-1bab-47c4-b2d2-a9bccf939a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33162
75310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3316275310
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.4126685445
Short name T63
Test name
Test status
Simulation time 141459265 ps
CPU time 0.82 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:48:00 PM PDT 24
Peak memory 206612 kb
Host smart-fb03e14d-8dcf-4a4e-90ae-6a481b67418e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
85445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.4126685445
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3122816223
Short name T1007
Test name
Test status
Simulation time 166915666 ps
CPU time 0.76 seconds
Started Jul 16 06:48:00 PM PDT 24
Finished Jul 16 06:48:02 PM PDT 24
Peak memory 206756 kb
Host smart-97e4340e-5af4-4a25-ae7b-06d329a5e489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31228
16223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3122816223
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3513615656
Short name T1437
Test name
Test status
Simulation time 372682480 ps
CPU time 1.3 seconds
Started Jul 16 06:48:00 PM PDT 24
Finished Jul 16 06:48:03 PM PDT 24
Peak memory 206860 kb
Host smart-d3eaf68e-6a38-4c72-be37-85c8c2e2db09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35136
15656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3513615656
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2958445376
Short name T462
Test name
Test status
Simulation time 347911641 ps
CPU time 1.07 seconds
Started Jul 16 06:47:59 PM PDT 24
Finished Jul 16 06:48:02 PM PDT 24
Peak memory 206880 kb
Host smart-a845d282-98d1-410e-a4e4-4c6807204933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584
45376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2958445376
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.147102967
Short name T90
Test name
Test status
Simulation time 15827743642 ps
CPU time 30.6 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 206912 kb
Host smart-42d227ce-bc8d-44ea-827a-32f6300027f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14710
2967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.147102967
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.456592856
Short name T1469
Test name
Test status
Simulation time 431561518 ps
CPU time 1.46 seconds
Started Jul 16 06:48:00 PM PDT 24
Finished Jul 16 06:48:03 PM PDT 24
Peak memory 206880 kb
Host smart-21c7c777-d275-4296-a565-cdb81d5ad987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45659
2856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.456592856
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1453450460
Short name T2640
Test name
Test status
Simulation time 139641872 ps
CPU time 0.76 seconds
Started Jul 16 06:47:56 PM PDT 24
Finished Jul 16 06:47:58 PM PDT 24
Peak memory 206772 kb
Host smart-f3947661-079f-49fc-87e5-7d3ad7d8e2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14534
50460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1453450460
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1782151691
Short name T489
Test name
Test status
Simulation time 63896751 ps
CPU time 0.69 seconds
Started Jul 16 06:47:59 PM PDT 24
Finished Jul 16 06:48:01 PM PDT 24
Peak memory 206804 kb
Host smart-9d1736a2-e3e8-4b43-8bec-a7d74b427779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17821
51691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1782151691
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3284908899
Short name T1848
Test name
Test status
Simulation time 773219464 ps
CPU time 2.15 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:48:02 PM PDT 24
Peak memory 207040 kb
Host smart-b76022af-adb0-414d-a4de-e93aeaa7c8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32849
08899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3284908899
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.4185251898
Short name T716
Test name
Test status
Simulation time 215142325 ps
CPU time 1.35 seconds
Started Jul 16 06:48:03 PM PDT 24
Finished Jul 16 06:48:05 PM PDT 24
Peak memory 206992 kb
Host smart-7b009d7e-76e0-4ab1-b3cd-8a3f70feb57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41852
51898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.4185251898
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.67824849
Short name T1508
Test name
Test status
Simulation time 101221916245 ps
CPU time 148.33 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:50:25 PM PDT 24
Peak memory 207140 kb
Host smart-08e0f37a-d8e6-4cec-941d-7f5e9d66e92a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=67824849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.67824849
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.690624019
Short name T650
Test name
Test status
Simulation time 110249860053 ps
CPU time 139.48 seconds
Started Jul 16 06:48:00 PM PDT 24
Finished Jul 16 06:50:21 PM PDT 24
Peak memory 207136 kb
Host smart-bf630b9a-2898-4046-bc58-2c2c265a558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690624019 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.690624019
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1791171147
Short name T1864
Test name
Test status
Simulation time 107103812630 ps
CPU time 166.32 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:50:46 PM PDT 24
Peak memory 206988 kb
Host smart-c17e6a27-5a94-4661-a620-d33d4a242659
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1791171147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1791171147
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1608557035
Short name T2412
Test name
Test status
Simulation time 90209734461 ps
CPU time 124.23 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:50:02 PM PDT 24
Peak memory 207152 kb
Host smart-651b0e0c-bbc4-4fb5-bf50-7d1bf0bf32db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608557035 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1608557035
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3443971273
Short name T1893
Test name
Test status
Simulation time 105140560756 ps
CPU time 128.34 seconds
Started Jul 16 06:47:59 PM PDT 24
Finished Jul 16 06:50:08 PM PDT 24
Peak memory 207112 kb
Host smart-5d0175bd-c109-4d46-831f-7284ac4e3108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34439
71273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3443971273
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1718755074
Short name T1350
Test name
Test status
Simulation time 245903062 ps
CPU time 0.93 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:47:59 PM PDT 24
Peak memory 206908 kb
Host smart-72b93717-d7be-4300-ba03-3898e7b420fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17187
55074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1718755074
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3403937130
Short name T329
Test name
Test status
Simulation time 152653583 ps
CPU time 0.8 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:48:00 PM PDT 24
Peak memory 206856 kb
Host smart-0bfd39dd-a06a-4037-a805-999170d9e323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34039
37130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3403937130
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3071750868
Short name T1190
Test name
Test status
Simulation time 226629701 ps
CPU time 0.89 seconds
Started Jul 16 06:48:03 PM PDT 24
Finished Jul 16 06:48:04 PM PDT 24
Peak memory 206880 kb
Host smart-f95a763d-68b0-4508-9ecb-609d4748f115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30717
50868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3071750868
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.1880491070
Short name T1534
Test name
Test status
Simulation time 6941815783 ps
CPU time 60.82 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:49:01 PM PDT 24
Peak memory 207132 kb
Host smart-d5717f03-af56-48a5-a146-ac2f78ed2887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18804
91070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.1880491070
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1917023045
Short name T1209
Test name
Test status
Simulation time 268703805 ps
CPU time 0.91 seconds
Started Jul 16 06:48:02 PM PDT 24
Finished Jul 16 06:48:03 PM PDT 24
Peak memory 206756 kb
Host smart-b3aacb47-6da9-4c03-990b-264da1b4c2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19170
23045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1917023045
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.4044177064
Short name T1912
Test name
Test status
Simulation time 23290517674 ps
CPU time 23.02 seconds
Started Jul 16 06:48:03 PM PDT 24
Finished Jul 16 06:48:27 PM PDT 24
Peak memory 206928 kb
Host smart-f79c1cb5-da2e-4ac5-a11a-7a95d5ab8686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40441
77064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.4044177064
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3732276316
Short name T331
Test name
Test status
Simulation time 3295967576 ps
CPU time 3.65 seconds
Started Jul 16 06:48:00 PM PDT 24
Finished Jul 16 06:48:05 PM PDT 24
Peak memory 206820 kb
Host smart-b7181eb9-96ab-44e1-bc0e-ed38fbad02b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322
76316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3732276316
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3374079490
Short name T393
Test name
Test status
Simulation time 13416518937 ps
CPU time 380.3 seconds
Started Jul 16 06:47:58 PM PDT 24
Finished Jul 16 06:54:20 PM PDT 24
Peak memory 207160 kb
Host smart-df3648db-6bd1-4333-9883-1815e8ddaa4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33740
79490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3374079490
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1055262641
Short name T2489
Test name
Test status
Simulation time 4059949056 ps
CPU time 28.83 seconds
Started Jul 16 06:47:59 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 207072 kb
Host smart-5722508c-be51-4c4b-af59-6801cc61084e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1055262641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1055262641
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2516135348
Short name T1693
Test name
Test status
Simulation time 253247513 ps
CPU time 0.96 seconds
Started Jul 16 06:47:59 PM PDT 24
Finished Jul 16 06:48:02 PM PDT 24
Peak memory 206812 kb
Host smart-ad2d058c-a38a-4ac3-b2d0-8080ae79a6a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2516135348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2516135348
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.218056078
Short name T1005
Test name
Test status
Simulation time 253240981 ps
CPU time 0.93 seconds
Started Jul 16 06:48:00 PM PDT 24
Finished Jul 16 06:48:03 PM PDT 24
Peak memory 206856 kb
Host smart-d0ed6f12-c48d-4690-bdd3-1789c1654979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21805
6078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.218056078
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2058116404
Short name T2190
Test name
Test status
Simulation time 6176252753 ps
CPU time 42.41 seconds
Started Jul 16 06:47:57 PM PDT 24
Finished Jul 16 06:48:41 PM PDT 24
Peak memory 207128 kb
Host smart-d2eb682d-42d2-4cc4-8b06-804ad824012c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20581
16404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2058116404
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.879445079
Short name T1006
Test name
Test status
Simulation time 4414109545 ps
CPU time 121.63 seconds
Started Jul 16 06:48:09 PM PDT 24
Finished Jul 16 06:50:12 PM PDT 24
Peak memory 207084 kb
Host smart-d9edd32c-5c9e-4610-bcfc-83c65fff929c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=879445079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.879445079
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2482764487
Short name T1967
Test name
Test status
Simulation time 150227656 ps
CPU time 0.77 seconds
Started Jul 16 06:48:14 PM PDT 24
Finished Jul 16 06:48:15 PM PDT 24
Peak memory 206880 kb
Host smart-e8c05e4f-d511-4fac-9fbc-8f7e5844677a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2482764487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2482764487
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.322771458
Short name T1013
Test name
Test status
Simulation time 141761648 ps
CPU time 0.77 seconds
Started Jul 16 06:48:21 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 206820 kb
Host smart-904f69dc-9e85-44f4-8e5b-387c545da7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32277
1458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.322771458
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1888558169
Short name T118
Test name
Test status
Simulation time 184195387 ps
CPU time 0.84 seconds
Started Jul 16 06:48:21 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 206824 kb
Host smart-0483440a-e358-4623-bd98-5dc8d088e4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885
58169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1888558169
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2047823602
Short name T2042
Test name
Test status
Simulation time 191119116 ps
CPU time 0.93 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 206560 kb
Host smart-d6f93e59-1a9d-4b7e-ad65-b1d55aaed78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20478
23602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2047823602
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2089864231
Short name T1889
Test name
Test status
Simulation time 235088721 ps
CPU time 0.9 seconds
Started Jul 16 06:48:13 PM PDT 24
Finished Jul 16 06:48:15 PM PDT 24
Peak memory 206796 kb
Host smart-8d3f27bf-efd7-4461-9734-b10900c833bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
64231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2089864231
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.419549795
Short name T337
Test name
Test status
Simulation time 159459122 ps
CPU time 0.82 seconds
Started Jul 16 06:48:11 PM PDT 24
Finished Jul 16 06:48:13 PM PDT 24
Peak memory 206864 kb
Host smart-14dad560-813a-4155-a28c-bee39acbecd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41954
9795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.419549795
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1704626497
Short name T2058
Test name
Test status
Simulation time 156238025 ps
CPU time 0.84 seconds
Started Jul 16 06:48:11 PM PDT 24
Finished Jul 16 06:48:13 PM PDT 24
Peak memory 206860 kb
Host smart-c984be54-70c7-4d92-8ae2-710cbc6365e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17046
26497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1704626497
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2471326947
Short name T2541
Test name
Test status
Simulation time 275267583 ps
CPU time 1.03 seconds
Started Jul 16 06:48:12 PM PDT 24
Finished Jul 16 06:48:14 PM PDT 24
Peak memory 206872 kb
Host smart-51375fa4-64d6-469d-804c-9fe1991b698b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2471326947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2471326947
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3914826652
Short name T387
Test name
Test status
Simulation time 214621491 ps
CPU time 0.88 seconds
Started Jul 16 06:48:10 PM PDT 24
Finished Jul 16 06:48:12 PM PDT 24
Peak memory 206648 kb
Host smart-45023b69-9929-452b-b64b-6d1caadad3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
26652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3914826652
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2246128688
Short name T2437
Test name
Test status
Simulation time 167907465 ps
CPU time 0.85 seconds
Started Jul 16 06:48:12 PM PDT 24
Finished Jul 16 06:48:14 PM PDT 24
Peak memory 206884 kb
Host smart-efbda2f7-3f42-4ea6-9334-9e28cdb2b5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22461
28688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2246128688
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1931030719
Short name T1519
Test name
Test status
Simulation time 51422961 ps
CPU time 0.64 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:48:21 PM PDT 24
Peak memory 206848 kb
Host smart-3450c6be-3e3d-4267-a50f-0f37e160bc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19310
30719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1931030719
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3241566331
Short name T2346
Test name
Test status
Simulation time 12237021223 ps
CPU time 31.85 seconds
Started Jul 16 06:48:10 PM PDT 24
Finished Jul 16 06:48:43 PM PDT 24
Peak memory 207108 kb
Host smart-0aca3675-e987-491b-92c5-2bfb4c8b9340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415
66331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3241566331
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.533171339
Short name T1772
Test name
Test status
Simulation time 151596542 ps
CPU time 0.76 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:48:21 PM PDT 24
Peak memory 206816 kb
Host smart-cd1abc0e-0dfb-4447-8868-9f661316410c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53317
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.533171339
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1077098712
Short name T1184
Test name
Test status
Simulation time 186493816 ps
CPU time 0.82 seconds
Started Jul 16 06:48:12 PM PDT 24
Finished Jul 16 06:48:14 PM PDT 24
Peak memory 206772 kb
Host smart-efcb5ac5-8231-42af-9fea-441d7f08f44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10770
98712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1077098712
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3302225109
Short name T147
Test name
Test status
Simulation time 16858713128 ps
CPU time 436.54 seconds
Started Jul 16 06:48:15 PM PDT 24
Finished Jul 16 06:55:32 PM PDT 24
Peak memory 207172 kb
Host smart-5e440fce-93c2-4c62-b2ce-920dd3df15ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3302225109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3302225109
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.270612096
Short name T862
Test name
Test status
Simulation time 9127584892 ps
CPU time 84.32 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:49:45 PM PDT 24
Peak memory 207096 kb
Host smart-234e1ae3-6829-4d73-9126-718a3219d0a7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=270612096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.270612096
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2647005244
Short name T143
Test name
Test status
Simulation time 14688681468 ps
CPU time 80.98 seconds
Started Jul 16 06:48:09 PM PDT 24
Finished Jul 16 06:49:31 PM PDT 24
Peak memory 207080 kb
Host smart-ccb230b6-736c-4acf-8e32-b58d906abd61
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2647005244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2647005244
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.365415727
Short name T2047
Test name
Test status
Simulation time 175164188 ps
CPU time 0.79 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 206820 kb
Host smart-ef48220f-f206-4ae7-8545-c8951512f3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36541
5727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.365415727
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.859091684
Short name T305
Test name
Test status
Simulation time 205174542 ps
CPU time 0.89 seconds
Started Jul 16 06:48:11 PM PDT 24
Finished Jul 16 06:48:13 PM PDT 24
Peak memory 206776 kb
Host smart-52447605-ece5-4a29-96ac-297c3a0e6589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85909
1684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.859091684
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.4079217774
Short name T902
Test name
Test status
Simulation time 182674989 ps
CPU time 0.76 seconds
Started Jul 16 06:48:09 PM PDT 24
Finished Jul 16 06:48:10 PM PDT 24
Peak memory 206864 kb
Host smart-374a5983-35bc-4c4f-b04a-edc792ad0d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40792
17774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.4079217774
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.149851751
Short name T76
Test name
Test status
Simulation time 172380470 ps
CPU time 0.85 seconds
Started Jul 16 06:48:12 PM PDT 24
Finished Jul 16 06:48:14 PM PDT 24
Peak memory 206880 kb
Host smart-8334ad6c-206d-46b5-81c8-d6d77fbd1410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14985
1751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.149851751
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2408384318
Short name T182
Test name
Test status
Simulation time 271216851 ps
CPU time 1.09 seconds
Started Jul 16 06:48:14 PM PDT 24
Finished Jul 16 06:48:16 PM PDT 24
Peak memory 224560 kb
Host smart-a774498c-2b56-49f6-9fc6-fe8468938c5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2408384318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2408384318
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.1661604969
Short name T1414
Test name
Test status
Simulation time 463414997 ps
CPU time 1.37 seconds
Started Jul 16 06:48:09 PM PDT 24
Finished Jul 16 06:48:12 PM PDT 24
Peak memory 206836 kb
Host smart-c97c04e8-42d3-4500-9a4e-8a7e736a9650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16616
04969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1661604969
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3601807801
Short name T1299
Test name
Test status
Simulation time 193397912 ps
CPU time 0.86 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 206504 kb
Host smart-1a56ebfa-b645-41a5-85ab-667519a98d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36018
07801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3601807801
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1940833673
Short name T2505
Test name
Test status
Simulation time 154132417 ps
CPU time 0.79 seconds
Started Jul 16 06:48:14 PM PDT 24
Finished Jul 16 06:48:16 PM PDT 24
Peak memory 206864 kb
Host smart-c1f49034-3c56-48fc-88c6-2b28472a2ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19408
33673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1940833673
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1236740504
Short name T527
Test name
Test status
Simulation time 168222144 ps
CPU time 0.77 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 206816 kb
Host smart-5d541dcb-265e-475b-9e00-49fdd64da0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12367
40504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1236740504
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.4151168301
Short name T828
Test name
Test status
Simulation time 194954454 ps
CPU time 0.89 seconds
Started Jul 16 06:48:13 PM PDT 24
Finished Jul 16 06:48:15 PM PDT 24
Peak memory 206792 kb
Host smart-9545efa8-7fbe-4235-8261-1055926f0fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41511
68301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.4151168301
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1468174408
Short name T1086
Test name
Test status
Simulation time 3628786265 ps
CPU time 33.65 seconds
Started Jul 16 06:48:11 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 207068 kb
Host smart-80d1cc8a-84ad-4e2d-8a0d-2a89cd34de84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1468174408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1468174408
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1051883859
Short name T475
Test name
Test status
Simulation time 180527788 ps
CPU time 0.82 seconds
Started Jul 16 06:48:12 PM PDT 24
Finished Jul 16 06:48:14 PM PDT 24
Peak memory 206880 kb
Host smart-df27c95b-887f-44da-ba60-38d6a3d94fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10518
83859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1051883859
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1948972621
Short name T2722
Test name
Test status
Simulation time 222943349 ps
CPU time 0.81 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:48:22 PM PDT 24
Peak memory 206736 kb
Host smart-6e5ef401-63a4-42ba-96e2-5087453fc150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19489
72621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1948972621
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2907822462
Short name T2752
Test name
Test status
Simulation time 204822261 ps
CPU time 0.94 seconds
Started Jul 16 06:48:12 PM PDT 24
Finished Jul 16 06:48:14 PM PDT 24
Peak memory 206860 kb
Host smart-600dc8f4-0982-4127-a29e-c0a49fd7c23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29078
22462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2907822462
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3181355870
Short name T2107
Test name
Test status
Simulation time 3682750687 ps
CPU time 28.53 seconds
Started Jul 16 06:48:11 PM PDT 24
Finished Jul 16 06:48:40 PM PDT 24
Peak memory 207060 kb
Host smart-379fef11-0615-42da-a270-8ff1a09c9f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31813
55870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3181355870
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.995740949
Short name T1546
Test name
Test status
Simulation time 13227521199 ps
CPU time 257.51 seconds
Started Jul 16 06:48:09 PM PDT 24
Finished Jul 16 06:52:28 PM PDT 24
Peak memory 206972 kb
Host smart-666c9cf3-5fe2-4bd6-a4f5-42b7713d38d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=995740949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.995740949
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.1998762201
Short name T1805
Test name
Test status
Simulation time 100946421 ps
CPU time 0.72 seconds
Started Jul 16 06:54:38 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 206916 kb
Host smart-59f7a445-4a5d-462b-bb2e-ab8d4ec789fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1998762201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.1998762201
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1522757402
Short name T831
Test name
Test status
Simulation time 4057397114 ps
CPU time 4.78 seconds
Started Jul 16 06:54:22 PM PDT 24
Finished Jul 16 06:54:28 PM PDT 24
Peak memory 206944 kb
Host smart-e6cd5f27-0d3a-440d-b7d9-320b3ab8617d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1522757402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1522757402
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2808721419
Short name T1634
Test name
Test status
Simulation time 13362671729 ps
CPU time 12.99 seconds
Started Jul 16 06:54:19 PM PDT 24
Finished Jul 16 06:54:34 PM PDT 24
Peak memory 206944 kb
Host smart-cb6e5fa7-efa4-443e-99d0-398f3eac2ad4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2808721419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2808721419
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3612688621
Short name T1835
Test name
Test status
Simulation time 23387129631 ps
CPU time 28.83 seconds
Started Jul 16 06:54:29 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206948 kb
Host smart-8024c99b-f67d-4dec-9cdd-daf7f437358a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3612688621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3612688621
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.4246556188
Short name T1416
Test name
Test status
Simulation time 212247452 ps
CPU time 0.88 seconds
Started Jul 16 06:54:33 PM PDT 24
Finished Jul 16 06:54:34 PM PDT 24
Peak memory 206852 kb
Host smart-35148b5c-9026-4422-9be7-783afedf995f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42465
56188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.4246556188
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.2977507165
Short name T1553
Test name
Test status
Simulation time 199354847 ps
CPU time 0.78 seconds
Started Jul 16 06:54:29 PM PDT 24
Finished Jul 16 06:54:30 PM PDT 24
Peak memory 206884 kb
Host smart-ec1ab03e-52e1-44a2-ad1e-c5b4be7bb9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29775
07165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.2977507165
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2718624383
Short name T1001
Test name
Test status
Simulation time 1427424170 ps
CPU time 3.38 seconds
Started Jul 16 06:54:25 PM PDT 24
Finished Jul 16 06:54:30 PM PDT 24
Peak memory 207016 kb
Host smart-c0cfdf76-3287-40a3-aaf2-f3984cc0e992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27186
24383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2718624383
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3944846052
Short name T2193
Test name
Test status
Simulation time 7930194957 ps
CPU time 13.7 seconds
Started Jul 16 06:54:28 PM PDT 24
Finished Jul 16 06:54:43 PM PDT 24
Peak memory 206992 kb
Host smart-c1b2f0dd-2393-4753-9b55-447f958d6fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
46052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3944846052
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3004435415
Short name T1247
Test name
Test status
Simulation time 355751912 ps
CPU time 1.19 seconds
Started Jul 16 06:54:30 PM PDT 24
Finished Jul 16 06:54:32 PM PDT 24
Peak memory 206736 kb
Host smart-acc4c757-55e5-4d28-8393-c27e014e149b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30044
35415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3004435415
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1245963330
Short name T2270
Test name
Test status
Simulation time 152347678 ps
CPU time 0.8 seconds
Started Jul 16 06:54:21 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206756 kb
Host smart-b17db928-294c-4a3f-9509-e3c7ebd7b085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12459
63330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1245963330
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1344974616
Short name T1308
Test name
Test status
Simulation time 43465641 ps
CPU time 0.62 seconds
Started Jul 16 06:54:27 PM PDT 24
Finished Jul 16 06:54:29 PM PDT 24
Peak memory 206844 kb
Host smart-12d42eaa-2f42-4767-b90b-416aac02ca10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13449
74616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1344974616
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2667321445
Short name T2036
Test name
Test status
Simulation time 701312816 ps
CPU time 1.73 seconds
Started Jul 16 06:54:24 PM PDT 24
Finished Jul 16 06:54:27 PM PDT 24
Peak memory 206992 kb
Host smart-8d16e54d-a726-4a69-8b92-702265dded3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26673
21445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2667321445
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.880664622
Short name T640
Test name
Test status
Simulation time 185656136 ps
CPU time 2.02 seconds
Started Jul 16 06:54:23 PM PDT 24
Finished Jul 16 06:54:26 PM PDT 24
Peak memory 206920 kb
Host smart-719c52ff-ec31-4511-ac84-4fd64af3915b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88066
4622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.880664622
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2069496967
Short name T583
Test name
Test status
Simulation time 172647054 ps
CPU time 0.83 seconds
Started Jul 16 06:54:20 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206888 kb
Host smart-e66312f3-bde8-43dc-af0f-77ee444913ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20694
96967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2069496967
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.526368503
Short name T1071
Test name
Test status
Simulation time 140770639 ps
CPU time 0.75 seconds
Started Jul 16 06:54:27 PM PDT 24
Finished Jul 16 06:54:29 PM PDT 24
Peak memory 206812 kb
Host smart-2a38653d-483c-4a84-8d9c-549e906c23b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52636
8503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.526368503
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3532419057
Short name T1804
Test name
Test status
Simulation time 232519877 ps
CPU time 0.95 seconds
Started Jul 16 06:54:22 PM PDT 24
Finished Jul 16 06:54:24 PM PDT 24
Peak memory 206756 kb
Host smart-57dea934-6d63-4891-a2af-bd0bfd2be022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35324
19057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3532419057
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.3440848578
Short name T1810
Test name
Test status
Simulation time 7763780400 ps
CPU time 54.19 seconds
Started Jul 16 06:54:27 PM PDT 24
Finished Jul 16 06:55:22 PM PDT 24
Peak memory 207100 kb
Host smart-30149e4f-984a-4c6e-95e6-5d4f48daf4ea
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3440848578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.3440848578
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.597584735
Short name T2645
Test name
Test status
Simulation time 3587648861 ps
CPU time 12.89 seconds
Started Jul 16 06:54:19 PM PDT 24
Finished Jul 16 06:54:33 PM PDT 24
Peak memory 207020 kb
Host smart-09e96835-4e1e-488b-ad39-3e7f041701a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59758
4735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.597584735
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2068511973
Short name T1905
Test name
Test status
Simulation time 237895188 ps
CPU time 0.89 seconds
Started Jul 16 06:54:25 PM PDT 24
Finished Jul 16 06:54:27 PM PDT 24
Peak memory 206748 kb
Host smart-1fedd843-04fd-4e60-949c-1e4ba71782c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20685
11973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2068511973
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1317513022
Short name T449
Test name
Test status
Simulation time 23326440693 ps
CPU time 22.35 seconds
Started Jul 16 06:54:19 PM PDT 24
Finished Jul 16 06:54:43 PM PDT 24
Peak memory 206796 kb
Host smart-5f353b83-c05f-4856-b695-5fad18c6c4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13175
13022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1317513022
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2429264353
Short name T1341
Test name
Test status
Simulation time 3390262201 ps
CPU time 4.38 seconds
Started Jul 16 06:54:30 PM PDT 24
Finished Jul 16 06:54:35 PM PDT 24
Peak memory 206884 kb
Host smart-47381893-0f63-4c06-a201-68abb311b7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24292
64353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2429264353
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2338339855
Short name T2251
Test name
Test status
Simulation time 13158860068 ps
CPU time 122.64 seconds
Started Jul 16 06:54:27 PM PDT 24
Finished Jul 16 06:56:31 PM PDT 24
Peak memory 207128 kb
Host smart-09f70132-c128-414c-a2d8-61641ba05cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23383
39855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2338339855
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.666144523
Short name T2290
Test name
Test status
Simulation time 4791469232 ps
CPU time 31.94 seconds
Started Jul 16 06:54:23 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 207092 kb
Host smart-14fdc6d0-26c3-48bc-ab0e-e8a15d43fd6b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=666144523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.666144523
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.4050018286
Short name T2231
Test name
Test status
Simulation time 290563095 ps
CPU time 0.93 seconds
Started Jul 16 06:54:19 PM PDT 24
Finished Jul 16 06:54:22 PM PDT 24
Peak memory 206876 kb
Host smart-2ea50a12-51cf-4c63-8df5-c5faf19b67e7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4050018286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.4050018286
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.4015523108
Short name T2673
Test name
Test status
Simulation time 204632978 ps
CPU time 0.83 seconds
Started Jul 16 06:54:23 PM PDT 24
Finished Jul 16 06:54:25 PM PDT 24
Peak memory 206796 kb
Host smart-516db2be-f27b-47bf-b383-386c97e5d84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40155
23108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.4015523108
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.465137023
Short name T145
Test name
Test status
Simulation time 4526393504 ps
CPU time 34.07 seconds
Started Jul 16 06:54:23 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 207080 kb
Host smart-deefcec7-5d02-4974-908e-045492ef3eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46513
7023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.465137023
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.448107225
Short name T653
Test name
Test status
Simulation time 4188453071 ps
CPU time 116.58 seconds
Started Jul 16 06:54:33 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 207088 kb
Host smart-29b03c82-77d1-4c64-8c48-e7c551d193c2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=448107225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.448107225
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3218896910
Short name T1254
Test name
Test status
Simulation time 150308482 ps
CPU time 0.77 seconds
Started Jul 16 06:54:28 PM PDT 24
Finished Jul 16 06:54:30 PM PDT 24
Peak memory 206884 kb
Host smart-05bd989d-ff8a-45e6-be8b-2a77036cdb4c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3218896910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3218896910
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3546480842
Short name T2634
Test name
Test status
Simulation time 134236250 ps
CPU time 0.73 seconds
Started Jul 16 06:54:19 PM PDT 24
Finished Jul 16 06:54:21 PM PDT 24
Peak memory 206876 kb
Host smart-ec5f4245-4bfc-4a87-82a2-0a5aa0b8421d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35464
80842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3546480842
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3110134203
Short name T134
Test name
Test status
Simulation time 240367891 ps
CPU time 0.84 seconds
Started Jul 16 06:54:20 PM PDT 24
Finished Jul 16 06:54:22 PM PDT 24
Peak memory 206888 kb
Host smart-6110333f-ac6a-49ec-aab1-9e95d5ba9e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31101
34203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3110134203
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3964162267
Short name T1838
Test name
Test status
Simulation time 165523232 ps
CPU time 0.79 seconds
Started Jul 16 06:54:31 PM PDT 24
Finished Jul 16 06:54:32 PM PDT 24
Peak memory 206880 kb
Host smart-1b5f1341-3c84-4887-b249-bf47ba875481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39641
62267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3964162267
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.205690483
Short name T2184
Test name
Test status
Simulation time 169805615 ps
CPU time 0.79 seconds
Started Jul 16 06:54:24 PM PDT 24
Finished Jul 16 06:54:26 PM PDT 24
Peak memory 206860 kb
Host smart-75327669-a850-49c0-93ee-9896aa4880df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20569
0483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.205690483
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.4051404681
Short name T2038
Test name
Test status
Simulation time 200252763 ps
CPU time 0.82 seconds
Started Jul 16 06:54:21 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206868 kb
Host smart-39f392ca-4607-4975-a9da-900c7fd880ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40514
04681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.4051404681
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.822769838
Short name T2459
Test name
Test status
Simulation time 181430670 ps
CPU time 0.83 seconds
Started Jul 16 06:54:35 PM PDT 24
Finished Jul 16 06:54:37 PM PDT 24
Peak memory 206888 kb
Host smart-7a57cd4e-a432-40ca-9a6c-82caa9c4bb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82276
9838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.822769838
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.843034819
Short name T930
Test name
Test status
Simulation time 255535562 ps
CPU time 0.96 seconds
Started Jul 16 06:54:25 PM PDT 24
Finished Jul 16 06:54:27 PM PDT 24
Peak memory 206876 kb
Host smart-8093f6fc-21f2-498c-9bdb-abdcabb67543
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=843034819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.843034819
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1722709061
Short name T876
Test name
Test status
Simulation time 169401085 ps
CPU time 0.79 seconds
Started Jul 16 06:54:17 PM PDT 24
Finished Jul 16 06:54:20 PM PDT 24
Peak memory 206748 kb
Host smart-7e165fb2-8f57-49a1-b6dc-946d60d18ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17227
09061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1722709061
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.679132490
Short name T1097
Test name
Test status
Simulation time 45546970 ps
CPU time 0.67 seconds
Started Jul 16 06:54:30 PM PDT 24
Finished Jul 16 06:54:31 PM PDT 24
Peak memory 206812 kb
Host smart-e9a1fb72-38f2-4f58-aeda-68264e2daf19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67913
2490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.679132490
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3085722818
Short name T2585
Test name
Test status
Simulation time 19058465572 ps
CPU time 40.17 seconds
Started Jul 16 06:54:25 PM PDT 24
Finished Jul 16 06:55:06 PM PDT 24
Peak memory 207152 kb
Host smart-b09d59ba-126e-43dc-afd2-d2278f95e073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
22818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3085722818
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.609585051
Short name T2691
Test name
Test status
Simulation time 187635130 ps
CPU time 0.84 seconds
Started Jul 16 06:54:25 PM PDT 24
Finished Jul 16 06:54:27 PM PDT 24
Peak memory 206872 kb
Host smart-e317156b-c568-4280-b89e-75583b548d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60958
5051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.609585051
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.204058939
Short name T1388
Test name
Test status
Simulation time 214685991 ps
CPU time 0.92 seconds
Started Jul 16 06:54:32 PM PDT 24
Finished Jul 16 06:54:34 PM PDT 24
Peak memory 206880 kb
Host smart-bdbaa2a4-8a9f-4e26-ad9b-4eaf0e87bb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20405
8939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.204058939
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.4056098354
Short name T795
Test name
Test status
Simulation time 191521375 ps
CPU time 0.83 seconds
Started Jul 16 06:54:29 PM PDT 24
Finished Jul 16 06:54:31 PM PDT 24
Peak memory 206868 kb
Host smart-cd2f7bdc-bc5c-486f-b226-896242650540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560
98354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.4056098354
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.390108015
Short name T2415
Test name
Test status
Simulation time 176208814 ps
CPU time 0.82 seconds
Started Jul 16 06:54:29 PM PDT 24
Finished Jul 16 06:54:31 PM PDT 24
Peak memory 206864 kb
Host smart-9b5f1524-1056-42bc-85da-5174538e728e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39010
8015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.390108015
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1745469779
Short name T700
Test name
Test status
Simulation time 144139807 ps
CPU time 0.74 seconds
Started Jul 16 06:54:26 PM PDT 24
Finished Jul 16 06:54:28 PM PDT 24
Peak memory 206848 kb
Host smart-659d6890-c37e-42ff-80d5-d943866b3f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17454
69779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1745469779
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3853939524
Short name T1861
Test name
Test status
Simulation time 158082854 ps
CPU time 0.74 seconds
Started Jul 16 06:54:21 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206740 kb
Host smart-80f91ca6-cd39-4414-85da-a1fe41f5edc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38539
39524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3853939524
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2033718156
Short name T2429
Test name
Test status
Simulation time 162072683 ps
CPU time 0.8 seconds
Started Jul 16 06:54:25 PM PDT 24
Finished Jul 16 06:54:27 PM PDT 24
Peak memory 207028 kb
Host smart-5ca6eca0-b364-460c-8cd9-24bbfe285d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20337
18156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2033718156
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1787506517
Short name T2393
Test name
Test status
Simulation time 234463268 ps
CPU time 0.9 seconds
Started Jul 16 06:54:33 PM PDT 24
Finished Jul 16 06:54:35 PM PDT 24
Peak memory 206880 kb
Host smart-87aa72dc-2f18-4f4d-b2c7-ab9a2829a9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
06517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1787506517
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3771753492
Short name T1904
Test name
Test status
Simulation time 4419779734 ps
CPU time 42.48 seconds
Started Jul 16 06:54:21 PM PDT 24
Finished Jul 16 06:55:05 PM PDT 24
Peak memory 207012 kb
Host smart-a41f01ed-432f-4e2e-a20c-144503581a8d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3771753492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3771753492
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2717619773
Short name T1682
Test name
Test status
Simulation time 200479539 ps
CPU time 0.79 seconds
Started Jul 16 06:54:21 PM PDT 24
Finished Jul 16 06:54:23 PM PDT 24
Peak memory 206728 kb
Host smart-54f99a03-6de3-477d-b4f1-f399afe76eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27176
19773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2717619773
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2888156140
Short name T1724
Test name
Test status
Simulation time 167155458 ps
CPU time 0.76 seconds
Started Jul 16 06:54:37 PM PDT 24
Finished Jul 16 06:54:38 PM PDT 24
Peak memory 206816 kb
Host smart-b8d05aec-0387-410d-b6ca-8a0f1b8c3bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
56140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2888156140
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.4018928110
Short name T572
Test name
Test status
Simulation time 614720582 ps
CPU time 1.68 seconds
Started Jul 16 06:54:42 PM PDT 24
Finished Jul 16 06:54:44 PM PDT 24
Peak memory 206808 kb
Host smart-221979cc-3ac9-419b-8cc6-7d8c5d673769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40189
28110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.4018928110
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2002122640
Short name T770
Test name
Test status
Simulation time 7312548549 ps
CPU time 211.83 seconds
Started Jul 16 06:54:35 PM PDT 24
Finished Jul 16 06:58:08 PM PDT 24
Peak memory 207088 kb
Host smart-950e9e11-44e0-41d9-ade0-4d2cc25283de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20021
22640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2002122640
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1921870957
Short name T2428
Test name
Test status
Simulation time 54836234 ps
CPU time 0.76 seconds
Started Jul 16 06:54:55 PM PDT 24
Finished Jul 16 06:55:00 PM PDT 24
Peak memory 206920 kb
Host smart-736e112f-3602-47de-82ef-d59029d8f081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1921870957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1921870957
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1805627860
Short name T1690
Test name
Test status
Simulation time 3725215233 ps
CPU time 4.32 seconds
Started Jul 16 06:54:37 PM PDT 24
Finished Jul 16 06:54:42 PM PDT 24
Peak memory 206860 kb
Host smart-b5c01070-7d41-44e0-bee1-d1cd36e320db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1805627860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1805627860
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.579257990
Short name T1681
Test name
Test status
Simulation time 13364750017 ps
CPU time 11.85 seconds
Started Jul 16 06:54:36 PM PDT 24
Finished Jul 16 06:54:48 PM PDT 24
Peak memory 207100 kb
Host smart-064b535e-6ad1-452e-894e-bc34512d6eab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=579257990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.579257990
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2232968550
Short name T2054
Test name
Test status
Simulation time 23367710756 ps
CPU time 21.26 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:55:15 PM PDT 24
Peak memory 207152 kb
Host smart-7faceb06-925c-44da-9175-55d7284b5b74
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2232968550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2232968550
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1911919224
Short name T954
Test name
Test status
Simulation time 160804818 ps
CPU time 0.87 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:54:42 PM PDT 24
Peak memory 207028 kb
Host smart-fee7febf-50de-4060-a4cc-2d02b6123585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19119
19224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1911919224
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2576192426
Short name T2448
Test name
Test status
Simulation time 146181369 ps
CPU time 0.78 seconds
Started Jul 16 06:54:38 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 206896 kb
Host smart-e8667472-3a32-42e7-b62d-f03b5704f9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25761
92426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2576192426
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3661138697
Short name T2230
Test name
Test status
Simulation time 302743377 ps
CPU time 1.3 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:55 PM PDT 24
Peak memory 206884 kb
Host smart-e9377bde-58c1-4182-babb-d9e22af1b799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36611
38697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3661138697
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1612335468
Short name T2576
Test name
Test status
Simulation time 369377521 ps
CPU time 1.1 seconds
Started Jul 16 06:54:34 PM PDT 24
Finished Jul 16 06:54:36 PM PDT 24
Peak memory 206752 kb
Host smart-6063c446-406a-4240-ab72-77838da295a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16123
35468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1612335468
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.3656716176
Short name T563
Test name
Test status
Simulation time 16417514890 ps
CPU time 34.39 seconds
Started Jul 16 06:54:37 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 207076 kb
Host smart-2b2a49a5-8704-42ab-82ac-9e393c28ae35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36567
16176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3656716176
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.4286840723
Short name T1777
Test name
Test status
Simulation time 480790029 ps
CPU time 1.46 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:55 PM PDT 24
Peak memory 206876 kb
Host smart-ef4d460d-eeef-460b-a81d-8ecfe2411961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42868
40723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.4286840723
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1253010511
Short name T2493
Test name
Test status
Simulation time 217188332 ps
CPU time 0.83 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 206884 kb
Host smart-0d5f5f0a-c102-4ba8-b551-c792fd2fa249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12530
10511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1253010511
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.214086459
Short name T2344
Test name
Test status
Simulation time 100374749 ps
CPU time 0.73 seconds
Started Jul 16 06:54:38 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 206660 kb
Host smart-4cb21afc-1f93-4196-922c-c7628b032a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21408
6459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.214086459
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2045946808
Short name T361
Test name
Test status
Simulation time 835788652 ps
CPU time 1.9 seconds
Started Jul 16 06:54:36 PM PDT 24
Finished Jul 16 06:54:39 PM PDT 24
Peak memory 207064 kb
Host smart-cbbabff5-a9ed-4153-b222-32f62e6adbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20459
46808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2045946808
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2847506922
Short name T2524
Test name
Test status
Simulation time 292800736 ps
CPU time 1.65 seconds
Started Jul 16 06:54:41 PM PDT 24
Finished Jul 16 06:54:44 PM PDT 24
Peak memory 206968 kb
Host smart-adf2f87e-64ec-41b6-b3e9-797d257a71f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28475
06922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2847506922
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2329313999
Short name T2057
Test name
Test status
Simulation time 237043931 ps
CPU time 0.95 seconds
Started Jul 16 06:54:37 PM PDT 24
Finished Jul 16 06:54:39 PM PDT 24
Peak memory 206884 kb
Host smart-6350abf8-0e58-4f60-baa2-62041a590c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23293
13999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2329313999
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.4080232595
Short name T2315
Test name
Test status
Simulation time 176047577 ps
CPU time 0.8 seconds
Started Jul 16 06:54:40 PM PDT 24
Finished Jul 16 06:54:43 PM PDT 24
Peak memory 206864 kb
Host smart-b70b8326-81ca-4311-82ab-88e8bfc064ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40802
32595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.4080232595
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1165206010
Short name T1219
Test name
Test status
Simulation time 229260409 ps
CPU time 0.93 seconds
Started Jul 16 06:54:38 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 206888 kb
Host smart-f770da15-4bfb-4311-bf99-da3b4d103553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11652
06010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1165206010
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.3390757537
Short name T1879
Test name
Test status
Simulation time 10037147232 ps
CPU time 38.06 seconds
Started Jul 16 06:54:40 PM PDT 24
Finished Jul 16 06:55:20 PM PDT 24
Peak memory 207080 kb
Host smart-ab105574-6dd8-4f14-b767-92308e79aae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33907
57537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.3390757537
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3116881207
Short name T2094
Test name
Test status
Simulation time 227741080 ps
CPU time 0.89 seconds
Started Jul 16 06:54:44 PM PDT 24
Finished Jul 16 06:54:45 PM PDT 24
Peak memory 206888 kb
Host smart-6e027822-fb3a-41d2-9b2c-018440dd8cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31168
81207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3116881207
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3121154358
Short name T2536
Test name
Test status
Simulation time 23382405553 ps
CPU time 23.37 seconds
Started Jul 16 06:54:38 PM PDT 24
Finished Jul 16 06:55:02 PM PDT 24
Peak memory 206728 kb
Host smart-32804ae7-2d37-4a93-9e6b-f5c7be913af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31211
54358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3121154358
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1316490689
Short name T1749
Test name
Test status
Simulation time 3265231969 ps
CPU time 4.29 seconds
Started Jul 16 06:54:50 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 206948 kb
Host smart-a348f7a2-220b-4e45-a439-9e2418b7e3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
90689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1316490689
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1128475499
Short name T2125
Test name
Test status
Simulation time 12711163852 ps
CPU time 355.94 seconds
Started Jul 16 06:54:42 PM PDT 24
Finished Jul 16 07:00:39 PM PDT 24
Peak memory 207092 kb
Host smart-1454cbd1-54cc-4208-89ac-bd97771d1c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11284
75499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1128475499
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2126055793
Short name T2556
Test name
Test status
Simulation time 6348493593 ps
CPU time 44.33 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 206968 kb
Host smart-49eac8c3-2ad7-4a63-9aa6-7c8ad9b11ca6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2126055793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2126055793
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.652729841
Short name T2334
Test name
Test status
Simulation time 239286726 ps
CPU time 0.95 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:54:41 PM PDT 24
Peak memory 206892 kb
Host smart-08039541-ec01-40da-8591-f2dcb83887f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=652729841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.652729841
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1367506190
Short name T1868
Test name
Test status
Simulation time 190184165 ps
CPU time 0.9 seconds
Started Jul 16 06:54:37 PM PDT 24
Finished Jul 16 06:54:39 PM PDT 24
Peak memory 206884 kb
Host smart-891445f5-7787-4a4e-88f8-7ac50109cf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13675
06190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1367506190
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3489630885
Short name T1290
Test name
Test status
Simulation time 4941613247 ps
CPU time 38.45 seconds
Started Jul 16 06:54:49 PM PDT 24
Finished Jul 16 06:55:29 PM PDT 24
Peak memory 207096 kb
Host smart-440db601-d6b5-47da-8190-268039b1234f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34896
30885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3489630885
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1813546818
Short name T2710
Test name
Test status
Simulation time 4129323544 ps
CPU time 29.59 seconds
Started Jul 16 06:54:51 PM PDT 24
Finished Jul 16 06:55:21 PM PDT 24
Peak memory 207076 kb
Host smart-b0d33bbb-4a20-43a5-a37d-7b9a8c88fd2b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1813546818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1813546818
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.401809674
Short name T1159
Test name
Test status
Simulation time 168362413 ps
CPU time 0.74 seconds
Started Jul 16 06:54:44 PM PDT 24
Finished Jul 16 06:54:45 PM PDT 24
Peak memory 206852 kb
Host smart-c6490388-9979-4f88-b94d-a56629fa01d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=401809674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.401809674
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1643087048
Short name T776
Test name
Test status
Simulation time 157759162 ps
CPU time 0.79 seconds
Started Jul 16 06:54:36 PM PDT 24
Finished Jul 16 06:54:38 PM PDT 24
Peak memory 206852 kb
Host smart-ab0cca86-95dd-4b3f-9456-2199dfa47810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16430
87048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1643087048
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.911656321
Short name T131
Test name
Test status
Simulation time 180488508 ps
CPU time 0.84 seconds
Started Jul 16 06:54:40 PM PDT 24
Finished Jul 16 06:54:42 PM PDT 24
Peak memory 206756 kb
Host smart-08d141bb-df8c-4f20-9486-ffa934b6db84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91165
6321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.911656321
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1688106908
Short name T1854
Test name
Test status
Simulation time 159405772 ps
CPU time 0.81 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:54:41 PM PDT 24
Peak memory 206812 kb
Host smart-051afc7e-85cd-401c-a524-e6a39c9a9c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16881
06908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1688106908
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.654174485
Short name T1491
Test name
Test status
Simulation time 164085879 ps
CPU time 0.81 seconds
Started Jul 16 06:54:37 PM PDT 24
Finished Jul 16 06:54:38 PM PDT 24
Peak memory 206752 kb
Host smart-ce265070-8347-4f8c-83f2-0d732fc43c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65417
4485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.654174485
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1351207932
Short name T2143
Test name
Test status
Simulation time 163909419 ps
CPU time 0.79 seconds
Started Jul 16 06:54:48 PM PDT 24
Finished Jul 16 06:54:50 PM PDT 24
Peak memory 206884 kb
Host smart-9de15234-d5ef-4181-bdc4-f4b86d90a9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13512
07932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1351207932
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1026639710
Short name T152
Test name
Test status
Simulation time 161571334 ps
CPU time 0.82 seconds
Started Jul 16 06:54:57 PM PDT 24
Finished Jul 16 06:55:01 PM PDT 24
Peak memory 206824 kb
Host smart-de9fe72b-6a74-440b-9cc7-13c7aab8b740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10266
39710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1026639710
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2480352160
Short name T1785
Test name
Test status
Simulation time 227762626 ps
CPU time 0.99 seconds
Started Jul 16 06:54:44 PM PDT 24
Finished Jul 16 06:54:46 PM PDT 24
Peak memory 206856 kb
Host smart-68c9764b-4954-47bc-bbff-648dae6678c8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2480352160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2480352160
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3852066892
Short name T1597
Test name
Test status
Simulation time 147055142 ps
CPU time 0.83 seconds
Started Jul 16 06:54:48 PM PDT 24
Finished Jul 16 06:54:50 PM PDT 24
Peak memory 206848 kb
Host smart-d71cc676-3f7c-4708-993f-79d0dadfcfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38520
66892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3852066892
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3368910366
Short name T2581
Test name
Test status
Simulation time 65215911 ps
CPU time 0.69 seconds
Started Jul 16 06:54:56 PM PDT 24
Finished Jul 16 06:55:01 PM PDT 24
Peak memory 206800 kb
Host smart-2ab47d21-1684-490b-9869-796f381224b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33689
10366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3368910366
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1230570683
Short name T261
Test name
Test status
Simulation time 21424957665 ps
CPU time 46.04 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 207184 kb
Host smart-9717ae16-325e-456b-866d-7f16a51e06b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12305
70683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1230570683
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1567288898
Short name T275
Test name
Test status
Simulation time 214981116 ps
CPU time 0.87 seconds
Started Jul 16 06:54:53 PM PDT 24
Finished Jul 16 06:54:57 PM PDT 24
Peak memory 206832 kb
Host smart-6031c230-bcea-4a16-aa53-1d3d1b3b6bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15672
88898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1567288898
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1380228951
Short name T1599
Test name
Test status
Simulation time 241362012 ps
CPU time 0.93 seconds
Started Jul 16 06:54:41 PM PDT 24
Finished Jul 16 06:54:43 PM PDT 24
Peak memory 206728 kb
Host smart-662e25a8-9d74-4ce1-b378-9ec116a3cd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13802
28951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1380228951
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3809107811
Short name T1570
Test name
Test status
Simulation time 182273527 ps
CPU time 0.9 seconds
Started Jul 16 06:54:37 PM PDT 24
Finished Jul 16 06:54:39 PM PDT 24
Peak memory 206848 kb
Host smart-5b30fcf9-7cbf-4226-bf17-fa1a11da7a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38091
07811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3809107811
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1904931490
Short name T1582
Test name
Test status
Simulation time 154884207 ps
CPU time 0.8 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:54:41 PM PDT 24
Peak memory 206868 kb
Host smart-0ca594fc-8336-469a-a08a-b511a1f74660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19049
31490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1904931490
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.3988043826
Short name T2732
Test name
Test status
Simulation time 139259494 ps
CPU time 0.75 seconds
Started Jul 16 06:55:01 PM PDT 24
Finished Jul 16 06:55:05 PM PDT 24
Peak memory 206804 kb
Host smart-07c32e55-5765-4f05-9056-dfe02d94d2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39880
43826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.3988043826
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1429515029
Short name T1795
Test name
Test status
Simulation time 157339515 ps
CPU time 0.79 seconds
Started Jul 16 06:54:40 PM PDT 24
Finished Jul 16 06:54:42 PM PDT 24
Peak memory 206880 kb
Host smart-88b329fd-9ba6-4ae0-90d0-243b8a073037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14295
15029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1429515029
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.524492781
Short name T2368
Test name
Test status
Simulation time 225056012 ps
CPU time 0.93 seconds
Started Jul 16 06:54:49 PM PDT 24
Finished Jul 16 06:54:51 PM PDT 24
Peak memory 206828 kb
Host smart-d1e28ee0-1e92-4b57-bfb8-3a1eed4e78af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52449
2781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.524492781
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3325333571
Short name T1650
Test name
Test status
Simulation time 198152779 ps
CPU time 0.88 seconds
Started Jul 16 06:54:38 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 206876 kb
Host smart-33052ad5-3416-44e7-b262-ac8b6b655ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33253
33571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3325333571
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.1123250143
Short name T1841
Test name
Test status
Simulation time 5350406063 ps
CPU time 50.84 seconds
Started Jul 16 06:54:59 PM PDT 24
Finished Jul 16 06:55:53 PM PDT 24
Peak memory 207040 kb
Host smart-d070c348-3669-47ca-9159-be769f18e091
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1123250143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.1123250143
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.4076745555
Short name T873
Test name
Test status
Simulation time 150597649 ps
CPU time 0.76 seconds
Started Jul 16 06:54:38 PM PDT 24
Finished Jul 16 06:54:40 PM PDT 24
Peak memory 206876 kb
Host smart-52b40b5d-f54e-4a21-adde-20b67460234c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40767
45555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.4076745555
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.4012137833
Short name T1087
Test name
Test status
Simulation time 167680948 ps
CPU time 0.88 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:55 PM PDT 24
Peak memory 206880 kb
Host smart-6e0cec3b-0e70-4f9b-94d3-ef1bd7def804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
37833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.4012137833
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.2988862609
Short name T2548
Test name
Test status
Simulation time 841676865 ps
CPU time 1.91 seconds
Started Jul 16 06:54:57 PM PDT 24
Finished Jul 16 06:55:02 PM PDT 24
Peak memory 207016 kb
Host smart-b17b855e-3e71-43cd-b216-5d5960395071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29888
62609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2988862609
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.4204512089
Short name T2515
Test name
Test status
Simulation time 5947667364 ps
CPU time 43.5 seconds
Started Jul 16 06:54:47 PM PDT 24
Finished Jul 16 06:55:32 PM PDT 24
Peak memory 207112 kb
Host smart-51c7278d-5d12-4685-9a98-a3d7f6c369fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42045
12089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.4204512089
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1632398354
Short name T1704
Test name
Test status
Simulation time 39241794 ps
CPU time 0.68 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 206844 kb
Host smart-8d48c259-4d3d-4e00-93e6-852ca0d87a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1632398354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1632398354
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3930756601
Short name T1016
Test name
Test status
Simulation time 3675825196 ps
CPU time 4.17 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:54:45 PM PDT 24
Peak memory 207160 kb
Host smart-d6d9ef28-370f-408b-a156-16e7ed3828d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3930756601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3930756601
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2457208032
Short name T2642
Test name
Test status
Simulation time 13347607354 ps
CPU time 11.86 seconds
Started Jul 16 06:54:37 PM PDT 24
Finished Jul 16 06:54:50 PM PDT 24
Peak memory 207120 kb
Host smart-0a15f5ec-c571-4f43-be5b-d4c74a50d11d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2457208032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2457208032
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3020905580
Short name T1695
Test name
Test status
Simulation time 23422281846 ps
CPU time 24.72 seconds
Started Jul 16 06:54:39 PM PDT 24
Finished Jul 16 06:55:04 PM PDT 24
Peak memory 207120 kb
Host smart-1878e2a2-fa60-419c-a177-8d5a80ecda0b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3020905580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3020905580
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2912526415
Short name T978
Test name
Test status
Simulation time 195464664 ps
CPU time 0.81 seconds
Started Jul 16 06:54:58 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206888 kb
Host smart-5abda688-49de-409f-8243-02d420ae6b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29125
26415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2912526415
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3631801367
Short name T60
Test name
Test status
Simulation time 152004617 ps
CPU time 0.77 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 206860 kb
Host smart-2bc6c0a5-5cd7-4e82-8d75-4acf631f96c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318
01367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3631801367
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.762524234
Short name T1149
Test name
Test status
Simulation time 662881081 ps
CPU time 1.92 seconds
Started Jul 16 06:55:00 PM PDT 24
Finished Jul 16 06:55:06 PM PDT 24
Peak memory 207028 kb
Host smart-c818cc1f-6964-44f0-9a84-ab449dcdcffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76252
4234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.762524234
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.4051473795
Short name T1031
Test name
Test status
Simulation time 1014268057 ps
CPU time 2.12 seconds
Started Jul 16 06:54:53 PM PDT 24
Finished Jul 16 06:54:59 PM PDT 24
Peak memory 207064 kb
Host smart-12554ad1-61d3-42ba-9336-863896e2a29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40514
73795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.4051473795
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.368738989
Short name T1096
Test name
Test status
Simulation time 15413157475 ps
CPU time 27.14 seconds
Started Jul 16 06:54:55 PM PDT 24
Finished Jul 16 06:55:26 PM PDT 24
Peak memory 207140 kb
Host smart-769f59c6-5f84-411c-8549-aadf09bf1150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36873
8989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.368738989
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.707202192
Short name T2571
Test name
Test status
Simulation time 383982248 ps
CPU time 1.31 seconds
Started Jul 16 06:54:51 PM PDT 24
Finished Jul 16 06:54:53 PM PDT 24
Peak memory 206796 kb
Host smart-1f5db7b5-1661-4b6a-a311-e63e2fa092ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70720
2192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.707202192
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2827914491
Short name T736
Test name
Test status
Simulation time 130623043 ps
CPU time 0.74 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:10 PM PDT 24
Peak memory 206884 kb
Host smart-744d682a-1cc0-4f02-a9a9-3abd2535cd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28279
14491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2827914491
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.4121273928
Short name T1793
Test name
Test status
Simulation time 73988627 ps
CPU time 0.73 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206660 kb
Host smart-b0ec2265-81d9-4ecc-84d2-f821142f1f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41212
73928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.4121273928
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.891793658
Short name T1394
Test name
Test status
Simulation time 759281353 ps
CPU time 1.98 seconds
Started Jul 16 06:55:02 PM PDT 24
Finished Jul 16 06:55:07 PM PDT 24
Peak memory 207028 kb
Host smart-d4346938-04b4-4ab7-9693-e01c83ca699d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89179
3658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.891793658
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3976413362
Short name T2469
Test name
Test status
Simulation time 178182341 ps
CPU time 1.75 seconds
Started Jul 16 06:54:51 PM PDT 24
Finished Jul 16 06:54:54 PM PDT 24
Peak memory 207108 kb
Host smart-1123b13e-207c-4564-937e-fd82b279e703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39764
13362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3976413362
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3989231514
Short name T2123
Test name
Test status
Simulation time 167761683 ps
CPU time 0.79 seconds
Started Jul 16 06:55:00 PM PDT 24
Finished Jul 16 06:55:04 PM PDT 24
Peak memory 206856 kb
Host smart-082f4ba9-96f1-49e2-90ea-4fd28392fbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
31514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3989231514
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2303951851
Short name T1337
Test name
Test status
Simulation time 153298866 ps
CPU time 0.83 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:55 PM PDT 24
Peak memory 206656 kb
Host smart-aceb1d1e-5d58-4702-a2dc-5f56b950a3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
51851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2303951851
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1252769232
Short name T368
Test name
Test status
Simulation time 169434880 ps
CPU time 0.8 seconds
Started Jul 16 06:54:58 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206756 kb
Host smart-9de860a4-8875-4fcc-9f25-706b57aae6bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12527
69232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1252769232
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2276907566
Short name T231
Test name
Test status
Simulation time 6516960489 ps
CPU time 44.64 seconds
Started Jul 16 06:54:57 PM PDT 24
Finished Jul 16 06:55:46 PM PDT 24
Peak memory 207104 kb
Host smart-dad4d3e9-f037-4435-83e7-9d4ddde4857a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2276907566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2276907566
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3267406720
Short name T596
Test name
Test status
Simulation time 197335483 ps
CPU time 0.86 seconds
Started Jul 16 06:55:01 PM PDT 24
Finished Jul 16 06:55:06 PM PDT 24
Peak memory 206808 kb
Host smart-a7310a6f-aaa8-4aed-9d0a-3549809cda0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32674
06720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3267406720
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.405253823
Short name T1591
Test name
Test status
Simulation time 23336906568 ps
CPU time 21.94 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206796 kb
Host smart-465e4b59-35ec-4676-b1ea-4386345d7264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
3823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.405253823
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3306917153
Short name T541
Test name
Test status
Simulation time 3323315298 ps
CPU time 4.38 seconds
Started Jul 16 06:55:00 PM PDT 24
Finished Jul 16 06:55:08 PM PDT 24
Peak memory 206920 kb
Host smart-aa18a922-fdd7-473c-8f9c-8fa118bda565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33069
17153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3306917153
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.1081823574
Short name T1084
Test name
Test status
Simulation time 7862059177 ps
CPU time 201.05 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:58:19 PM PDT 24
Peak memory 206924 kb
Host smart-1784107d-92c9-4683-96d3-01bb0af8f4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10818
23574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.1081823574
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1103514220
Short name T865
Test name
Test status
Simulation time 4521659788 ps
CPU time 134.12 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:57:09 PM PDT 24
Peak memory 207084 kb
Host smart-4ac97447-9eb3-4f0b-81c3-473b72c432f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1103514220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1103514220
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2215957732
Short name T643
Test name
Test status
Simulation time 272361234 ps
CPU time 0.96 seconds
Started Jul 16 06:55:07 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 206876 kb
Host smart-ae4aa2ab-6229-4f29-a3a3-5388bf249c28
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2215957732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2215957732
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2482704626
Short name T1811
Test name
Test status
Simulation time 193706839 ps
CPU time 0.85 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206892 kb
Host smart-17c5aec7-a10c-4c18-8e19-54506664d062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24827
04626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2482704626
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.11840739
Short name T472
Test name
Test status
Simulation time 6152729592 ps
CPU time 59.88 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:55:54 PM PDT 24
Peak memory 206864 kb
Host smart-08fbda63-5976-4043-8df3-486b3f0a32c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11840
739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.11840739
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3884740897
Short name T1583
Test name
Test status
Simulation time 4132858199 ps
CPU time 29.38 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 207148 kb
Host smart-ff47dcf3-750a-42ca-aa1e-f163dfd8d1d1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3884740897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3884740897
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2448133651
Short name T1718
Test name
Test status
Simulation time 221839628 ps
CPU time 0.83 seconds
Started Jul 16 06:54:53 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206776 kb
Host smart-7a9852d3-8805-468e-ab4c-ed884c6893a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2448133651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2448133651
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.957267811
Short name T1010
Test name
Test status
Simulation time 148219830 ps
CPU time 0.79 seconds
Started Jul 16 06:54:55 PM PDT 24
Finished Jul 16 06:55:00 PM PDT 24
Peak memory 206776 kb
Host smart-cad9c2c1-4e82-44a7-9205-2a9e6eb49f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95726
7811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.957267811
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2296517267
Short name T2700
Test name
Test status
Simulation time 159942697 ps
CPU time 0.79 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:57 PM PDT 24
Peak memory 206884 kb
Host smart-74c6d7d6-6ed2-4bcb-9ec8-c2e14c91f5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22965
17267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2296517267
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.122984198
Short name T519
Test name
Test status
Simulation time 188248975 ps
CPU time 0.85 seconds
Started Jul 16 06:54:51 PM PDT 24
Finished Jul 16 06:54:53 PM PDT 24
Peak memory 206852 kb
Host smart-90728e23-b0dc-4ae0-95d3-835108df452d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12298
4198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.122984198
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.431690085
Short name T729
Test name
Test status
Simulation time 165800426 ps
CPU time 0.87 seconds
Started Jul 16 06:54:59 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206852 kb
Host smart-c55a2c2f-1b49-43dc-8f4c-6acc42b08020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43169
0085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.431690085
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2666072076
Short name T417
Test name
Test status
Simulation time 170068374 ps
CPU time 0.83 seconds
Started Jul 16 06:54:55 PM PDT 24
Finished Jul 16 06:55:00 PM PDT 24
Peak memory 206896 kb
Host smart-238ae445-5060-4fe9-907f-13d241aee92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
72076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2666072076
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.115692079
Short name T1321
Test name
Test status
Simulation time 264862896 ps
CPU time 0.97 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 206756 kb
Host smart-406a71e2-9bbf-4e4e-9782-d8085cc2ffe8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=115692079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.115692079
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.588983596
Short name T1730
Test name
Test status
Simulation time 152533517 ps
CPU time 0.83 seconds
Started Jul 16 06:54:56 PM PDT 24
Finished Jul 16 06:55:01 PM PDT 24
Peak memory 206732 kb
Host smart-844f5839-640d-495e-939f-16fafd4c8cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58898
3596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.588983596
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1848851946
Short name T1512
Test name
Test status
Simulation time 35432329 ps
CPU time 0.65 seconds
Started Jul 16 06:54:55 PM PDT 24
Finished Jul 16 06:55:00 PM PDT 24
Peak memory 206824 kb
Host smart-c0d3b6d9-802f-4677-8a5f-6c709d8e2303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18488
51946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1848851946
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3876139990
Short name T1154
Test name
Test status
Simulation time 7264171626 ps
CPU time 16.73 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:55:13 PM PDT 24
Peak memory 207128 kb
Host smart-8eec3f0b-3e75-41b5-ad39-f6f28f43bc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38761
39990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3876139990
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2680355517
Short name T1342
Test name
Test status
Simulation time 166295949 ps
CPU time 0.84 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:55 PM PDT 24
Peak memory 206880 kb
Host smart-a733eacc-4008-4934-a222-621dd6a0a844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26803
55517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2680355517
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.414129780
Short name T979
Test name
Test status
Simulation time 203115110 ps
CPU time 0.91 seconds
Started Jul 16 06:54:55 PM PDT 24
Finished Jul 16 06:55:00 PM PDT 24
Peak memory 206864 kb
Host smart-8bd1f508-5bdc-4bfd-8556-02b7d597fbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41412
9780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.414129780
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2008252653
Short name T2225
Test name
Test status
Simulation time 172987281 ps
CPU time 0.91 seconds
Started Jul 16 06:54:57 PM PDT 24
Finished Jul 16 06:55:02 PM PDT 24
Peak memory 206868 kb
Host smart-cb2f10f3-f77a-4803-b1de-c37365c4e8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20082
52653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2008252653
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3281776508
Short name T2665
Test name
Test status
Simulation time 214529309 ps
CPU time 0.88 seconds
Started Jul 16 06:55:01 PM PDT 24
Finished Jul 16 06:55:05 PM PDT 24
Peak memory 206812 kb
Host smart-54d0e395-70a4-467e-a5ff-059fde78f874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32817
76508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3281776508
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3139799236
Short name T2196
Test name
Test status
Simulation time 151064548 ps
CPU time 0.8 seconds
Started Jul 16 06:54:51 PM PDT 24
Finished Jul 16 06:54:53 PM PDT 24
Peak memory 206772 kb
Host smart-e6f44079-c375-4ac4-b4fc-08dfe3b91147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31397
99236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3139799236
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3954872515
Short name T2592
Test name
Test status
Simulation time 149201221 ps
CPU time 0.78 seconds
Started Jul 16 06:54:53 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206808 kb
Host smart-bbd65146-6bf0-4309-9479-5040fe8f2db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39548
72515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3954872515
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3225314052
Short name T1426
Test name
Test status
Simulation time 147178570 ps
CPU time 0.74 seconds
Started Jul 16 06:54:53 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206852 kb
Host smart-d47c2629-17f4-4f32-854f-cbddd122e2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32253
14052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3225314052
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3351118732
Short name T1064
Test name
Test status
Simulation time 205379128 ps
CPU time 0.94 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 206876 kb
Host smart-df66798c-c108-46d8-b2d2-b55c5c6dc729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33511
18732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3351118732
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2229020865
Short name T354
Test name
Test status
Simulation time 4526907005 ps
CPU time 129.08 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:57:05 PM PDT 24
Peak memory 207088 kb
Host smart-02ba014b-129f-4d07-9119-018ff1e075b4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2229020865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2229020865
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1314265834
Short name T1930
Test name
Test status
Simulation time 142323054 ps
CPU time 0.75 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206648 kb
Host smart-c1977370-9dbd-41de-b2f5-0451430d9748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13142
65834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1314265834
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1992680888
Short name T1605
Test name
Test status
Simulation time 188398055 ps
CPU time 0.84 seconds
Started Jul 16 06:54:58 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206772 kb
Host smart-e338477b-be8a-41f2-94b9-e71a750091ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19926
80888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1992680888
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3684176216
Short name T1008
Test name
Test status
Simulation time 265836961 ps
CPU time 0.94 seconds
Started Jul 16 06:54:53 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206832 kb
Host smart-3e7843c7-e1b4-4701-8f77-dc9e07dffd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36841
76216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3684176216
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1891717859
Short name T1999
Test name
Test status
Simulation time 2882409325 ps
CPU time 74.5 seconds
Started Jul 16 06:55:00 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 207112 kb
Host smart-162f916f-63d3-4766-82c0-f5697794dfb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18917
17859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1891717859
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.3280944836
Short name T508
Test name
Test status
Simulation time 32455631 ps
CPU time 0.63 seconds
Started Jul 16 06:55:11 PM PDT 24
Finished Jul 16 06:55:16 PM PDT 24
Peak memory 206720 kb
Host smart-0a546ab5-641c-4244-a005-ceb61b8df40d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3280944836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.3280944836
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.63628806
Short name T1205
Test name
Test status
Simulation time 13373729753 ps
CPU time 14.21 seconds
Started Jul 16 06:55:01 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 206856 kb
Host smart-9aca8ac3-5487-4877-9d7d-9c3ac183b43d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=63628806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.63628806
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.2164941605
Short name T2016
Test name
Test status
Simulation time 23336581620 ps
CPU time 24.51 seconds
Started Jul 16 06:54:59 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 206872 kb
Host smart-33e3ab3f-6f55-4f1c-b694-c20b55630daa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2164941605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.2164941605
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1102575120
Short name T799
Test name
Test status
Simulation time 166009653 ps
CPU time 0.8 seconds
Started Jul 16 06:55:00 PM PDT 24
Finished Jul 16 06:55:04 PM PDT 24
Peak memory 206880 kb
Host smart-e93a7239-dc1a-42db-a6b5-ea553577827b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11025
75120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1102575120
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2270902292
Short name T1034
Test name
Test status
Simulation time 215645056 ps
CPU time 0.83 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 206880 kb
Host smart-8ce095e0-89c0-4f92-bf64-30a23c69a445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22709
02292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2270902292
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.1591123755
Short name T887
Test name
Test status
Simulation time 179779591 ps
CPU time 0.83 seconds
Started Jul 16 06:55:00 PM PDT 24
Finished Jul 16 06:55:04 PM PDT 24
Peak memory 206864 kb
Host smart-e171386d-89b8-4b76-8549-34c129b728e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15911
23755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.1591123755
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.472933978
Short name T957
Test name
Test status
Simulation time 1658133468 ps
CPU time 3.21 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:59 PM PDT 24
Peak memory 207004 kb
Host smart-901cae72-07e2-4473-9de1-851268042b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47293
3978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.472933978
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.4110938927
Short name T1466
Test name
Test status
Simulation time 18081046004 ps
CPU time 32.32 seconds
Started Jul 16 06:54:59 PM PDT 24
Finished Jul 16 06:55:35 PM PDT 24
Peak memory 207124 kb
Host smart-5322236e-5cb6-4b27-aac5-d4a091ac742a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
38927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.4110938927
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1468822540
Short name T510
Test name
Test status
Simulation time 348423278 ps
CPU time 1.22 seconds
Started Jul 16 06:54:55 PM PDT 24
Finished Jul 16 06:55:00 PM PDT 24
Peak memory 206880 kb
Host smart-8eb84892-2ce4-4c34-84ee-66eaf7d34706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14688
22540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1468822540
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.387635529
Short name T1522
Test name
Test status
Simulation time 160323402 ps
CPU time 0.77 seconds
Started Jul 16 06:54:51 PM PDT 24
Finished Jul 16 06:54:53 PM PDT 24
Peak memory 206908 kb
Host smart-b5a9328b-8f70-48bd-bbef-36ebe2439368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763
5529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.387635529
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3601127291
Short name T2373
Test name
Test status
Simulation time 50725338 ps
CPU time 0.67 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:54:58 PM PDT 24
Peak memory 206888 kb
Host smart-8f924ad7-11c5-4e0a-98a9-4fec0a81e810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36011
27291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3601127291
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.315037711
Short name T1696
Test name
Test status
Simulation time 888215879 ps
CPU time 2.31 seconds
Started Jul 16 06:54:56 PM PDT 24
Finished Jul 16 06:55:02 PM PDT 24
Peak memory 207024 kb
Host smart-9e98f5ee-c75a-4254-ab01-19947b7bea70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31503
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.315037711
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2991234604
Short name T2043
Test name
Test status
Simulation time 331169240 ps
CPU time 1.87 seconds
Started Jul 16 06:54:57 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 207052 kb
Host smart-45d9db28-30f8-4415-b123-16f79168c516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29912
34604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2991234604
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.740780326
Short name T987
Test name
Test status
Simulation time 153073419 ps
CPU time 0.81 seconds
Started Jul 16 06:55:05 PM PDT 24
Finished Jul 16 06:55:10 PM PDT 24
Peak memory 206880 kb
Host smart-882dc8ad-57b8-4c1a-8ee5-e95d97d8772f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74078
0326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.740780326
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1690601028
Short name T699
Test name
Test status
Simulation time 158981833 ps
CPU time 0.78 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:55:14 PM PDT 24
Peak memory 206876 kb
Host smart-83399a22-fb1b-4fde-ac33-129627bc8cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16906
01028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1690601028
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3614121666
Short name T2307
Test name
Test status
Simulation time 226205935 ps
CPU time 0.91 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 206804 kb
Host smart-d9e72262-8eba-4196-82ab-be6aafa043b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
21666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3614121666
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3692592578
Short name T759
Test name
Test status
Simulation time 240438686 ps
CPU time 0.91 seconds
Started Jul 16 06:54:58 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206748 kb
Host smart-747c8ba0-6d6a-43fb-ae36-5ae6157e3868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36925
92578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3692592578
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2883430395
Short name T1853
Test name
Test status
Simulation time 23305624033 ps
CPU time 21.05 seconds
Started Jul 16 06:54:59 PM PDT 24
Finished Jul 16 06:55:24 PM PDT 24
Peak memory 206816 kb
Host smart-593c4c81-9819-438b-89ad-f59b7d9fb223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28834
30395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2883430395
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.11705607
Short name T2244
Test name
Test status
Simulation time 3289335433 ps
CPU time 3.73 seconds
Started Jul 16 06:55:01 PM PDT 24
Finished Jul 16 06:55:09 PM PDT 24
Peak memory 206876 kb
Host smart-bbcd5dee-2813-4d37-89bf-5160a2bddd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11705
607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.11705607
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2316339754
Short name T2197
Test name
Test status
Simulation time 11922311853 ps
CPU time 326.03 seconds
Started Jul 16 06:55:05 PM PDT 24
Finished Jul 16 07:00:35 PM PDT 24
Peak memory 207156 kb
Host smart-bb163553-086e-4c42-8f85-9d2787dad814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
39754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2316339754
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.441436598
Short name T1277
Test name
Test status
Simulation time 5461946322 ps
CPU time 155.84 seconds
Started Jul 16 06:55:01 PM PDT 24
Finished Jul 16 06:57:41 PM PDT 24
Peak memory 207020 kb
Host smart-d36c92d6-20b8-4b8e-84e8-9e542b3abde8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=441436598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.441436598
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2801946336
Short name T1438
Test name
Test status
Simulation time 243164202 ps
CPU time 0.89 seconds
Started Jul 16 06:54:59 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206752 kb
Host smart-435b2d99-b50a-4c65-9697-48f1b2cb48a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2801946336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2801946336
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3729749682
Short name T2326
Test name
Test status
Simulation time 189627663 ps
CPU time 0.85 seconds
Started Jul 16 06:55:02 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 206792 kb
Host smart-700a8199-bfdb-4f87-8317-eb2a251b40dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37297
49682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3729749682
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.1385395287
Short name T1753
Test name
Test status
Simulation time 3870859094 ps
CPU time 105.33 seconds
Started Jul 16 06:54:58 PM PDT 24
Finished Jul 16 06:56:47 PM PDT 24
Peak memory 207060 kb
Host smart-be8358cc-20f2-440a-87bc-f79351ba531a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13853
95287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.1385395287
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2926438604
Short name T740
Test name
Test status
Simulation time 6960127409 ps
CPU time 61.27 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:56:00 PM PDT 24
Peak memory 207060 kb
Host smart-15bfb62e-7cae-4701-87a7-a607c10b3eb2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2926438604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2926438604
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.3660433542
Short name T639
Test name
Test status
Simulation time 163355736 ps
CPU time 0.79 seconds
Started Jul 16 06:54:53 PM PDT 24
Finished Jul 16 06:54:57 PM PDT 24
Peak memory 206852 kb
Host smart-d042cb93-5ee9-4f5b-9c96-91392933fd70
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3660433542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3660433542
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3867418577
Short name T2187
Test name
Test status
Simulation time 147683650 ps
CPU time 0.76 seconds
Started Jul 16 06:54:57 PM PDT 24
Finished Jul 16 06:55:01 PM PDT 24
Peak memory 206868 kb
Host smart-604ca110-a743-419b-93e4-8f3ed7f12d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38674
18577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3867418577
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1292934163
Short name T135
Test name
Test status
Simulation time 243973955 ps
CPU time 0.92 seconds
Started Jul 16 06:54:52 PM PDT 24
Finished Jul 16 06:54:56 PM PDT 24
Peak memory 206856 kb
Host smart-b4be3118-d0d5-4dd1-98ef-c4d446d21552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12929
34163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1292934163
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.794953724
Short name T455
Test name
Test status
Simulation time 197057816 ps
CPU time 0.85 seconds
Started Jul 16 06:54:59 PM PDT 24
Finished Jul 16 06:55:04 PM PDT 24
Peak memory 206864 kb
Host smart-c08cb57b-50cd-4e2d-b0ce-be0bdfee2a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79495
3724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.794953724
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.651879579
Short name T1723
Test name
Test status
Simulation time 188503845 ps
CPU time 0.8 seconds
Started Jul 16 06:54:57 PM PDT 24
Finished Jul 16 06:55:02 PM PDT 24
Peak memory 206872 kb
Host smart-0e34a394-804e-499b-9e86-7d165f478e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65187
9579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.651879579
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2832068896
Short name T309
Test name
Test status
Simulation time 205313441 ps
CPU time 0.85 seconds
Started Jul 16 06:55:00 PM PDT 24
Finished Jul 16 06:55:04 PM PDT 24
Peak memory 206884 kb
Host smart-5dcd89b2-5355-454e-896c-b2fecc530506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28320
68896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2832068896
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.116251527
Short name T1198
Test name
Test status
Simulation time 162497448 ps
CPU time 0.8 seconds
Started Jul 16 06:54:58 PM PDT 24
Finished Jul 16 06:55:02 PM PDT 24
Peak memory 207032 kb
Host smart-27d3708d-9b08-4d7f-a0b2-f1227dc4fba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11625
1527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.116251527
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2201644141
Short name T2597
Test name
Test status
Simulation time 258824004 ps
CPU time 0.98 seconds
Started Jul 16 06:55:03 PM PDT 24
Finished Jul 16 06:55:07 PM PDT 24
Peak memory 206884 kb
Host smart-9bf44d59-dd86-409c-8455-17197b5115be
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2201644141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2201644141
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1358893339
Short name T2052
Test name
Test status
Simulation time 172193457 ps
CPU time 0.78 seconds
Started Jul 16 06:55:01 PM PDT 24
Finished Jul 16 06:55:06 PM PDT 24
Peak memory 206876 kb
Host smart-bff0153a-4108-47a4-8ee3-6ea72b99b16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13588
93339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1358893339
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1361745806
Short name T1019
Test name
Test status
Simulation time 76449230 ps
CPU time 0.69 seconds
Started Jul 16 06:54:57 PM PDT 24
Finished Jul 16 06:55:02 PM PDT 24
Peak memory 206848 kb
Host smart-9d0944e6-1fe1-4967-8a93-b57281f98f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13617
45806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1361745806
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2896294742
Short name T2742
Test name
Test status
Simulation time 12471456674 ps
CPU time 28.47 seconds
Started Jul 16 06:54:55 PM PDT 24
Finished Jul 16 06:55:28 PM PDT 24
Peak memory 207028 kb
Host smart-6c0db819-1df9-49ef-b5f1-930bb444eff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28962
94742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2896294742
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.420606543
Short name T1107
Test name
Test status
Simulation time 160958455 ps
CPU time 0.85 seconds
Started Jul 16 06:54:58 PM PDT 24
Finished Jul 16 06:55:03 PM PDT 24
Peak memory 206872 kb
Host smart-3b6ab032-a21d-4975-bb6f-c8ca432e5ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42060
6543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.420606543
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2190341312
Short name T1398
Test name
Test status
Simulation time 289375866 ps
CPU time 1 seconds
Started Jul 16 06:55:00 PM PDT 24
Finished Jul 16 06:55:05 PM PDT 24
Peak memory 206872 kb
Host smart-40f5713e-094e-426c-b9ac-af5e53d6e31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21903
41312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2190341312
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.63388144
Short name T1232
Test name
Test status
Simulation time 176828763 ps
CPU time 0.84 seconds
Started Jul 16 06:54:54 PM PDT 24
Finished Jul 16 06:54:59 PM PDT 24
Peak memory 206748 kb
Host smart-a345ded1-95a1-4e77-ab31-daff749e30cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63388
144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.63388144
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.75741324
Short name T1406
Test name
Test status
Simulation time 143212569 ps
CPU time 0.82 seconds
Started Jul 16 06:55:05 PM PDT 24
Finished Jul 16 06:55:09 PM PDT 24
Peak memory 206864 kb
Host smart-749fa519-6105-41b5-bbe1-2821094f4668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75741
324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.75741324
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.945586518
Short name T1274
Test name
Test status
Simulation time 134853089 ps
CPU time 0.76 seconds
Started Jul 16 06:55:07 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 206820 kb
Host smart-65a76a89-aec9-42ce-8917-eb2cc6c47322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94558
6518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.945586518
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2320237257
Short name T1603
Test name
Test status
Simulation time 159558237 ps
CPU time 0.79 seconds
Started Jul 16 06:55:02 PM PDT 24
Finished Jul 16 06:55:06 PM PDT 24
Peak memory 206888 kb
Host smart-87504380-8116-4433-9f4b-77f738a3a615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
37257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2320237257
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2642425518
Short name T456
Test name
Test status
Simulation time 165809494 ps
CPU time 0.78 seconds
Started Jul 16 06:55:04 PM PDT 24
Finished Jul 16 06:55:07 PM PDT 24
Peak memory 206752 kb
Host smart-c5776c0d-7d00-46e7-830e-d39c77ef23ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26424
25518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2642425518
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1334057420
Short name T1579
Test name
Test status
Simulation time 220808055 ps
CPU time 0.89 seconds
Started Jul 16 06:55:09 PM PDT 24
Finished Jul 16 06:55:15 PM PDT 24
Peak memory 206744 kb
Host smart-eb262ede-0857-4b4e-a223-908563af8057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13340
57420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1334057420
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.4017995535
Short name T1611
Test name
Test status
Simulation time 4098666500 ps
CPU time 38.02 seconds
Started Jul 16 06:55:05 PM PDT 24
Finished Jul 16 06:55:47 PM PDT 24
Peak memory 207112 kb
Host smart-ffea28f5-c55d-4281-8519-22186b90e315
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4017995535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.4017995535
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.4131557222
Short name T348
Test name
Test status
Simulation time 161112407 ps
CPU time 0.78 seconds
Started Jul 16 06:55:07 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 206888 kb
Host smart-c1f3144c-be10-41dc-9b61-3b39c0be4dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
57222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.4131557222
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1510397208
Short name T2266
Test name
Test status
Simulation time 169690955 ps
CPU time 0.77 seconds
Started Jul 16 06:55:19 PM PDT 24
Finished Jul 16 06:55:22 PM PDT 24
Peak memory 206856 kb
Host smart-518d022a-d27e-49ff-af25-0c3459b12230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15103
97208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1510397208
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1549630351
Short name T1292
Test name
Test status
Simulation time 616271302 ps
CPU time 1.61 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:55:14 PM PDT 24
Peak memory 206864 kb
Host smart-3f782d11-c508-4b80-aece-5a3086a4dad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15496
30351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1549630351
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.116245440
Short name T2281
Test name
Test status
Simulation time 7923115810 ps
CPU time 226.5 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:58:56 PM PDT 24
Peak memory 207048 kb
Host smart-b4db81e4-2ef3-4393-ae8b-57e97ba75503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11624
5440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.116245440
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1905642888
Short name T2392
Test name
Test status
Simulation time 36449809 ps
CPU time 0.69 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:18 PM PDT 24
Peak memory 206920 kb
Host smart-e6df8452-59e9-489e-b394-37b058e12ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1905642888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1905642888
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3353115312
Short name T1645
Test name
Test status
Simulation time 4395649121 ps
CPU time 4.95 seconds
Started Jul 16 06:55:05 PM PDT 24
Finished Jul 16 06:55:13 PM PDT 24
Peak memory 206880 kb
Host smart-39e9a64f-12dc-4251-921f-55b5dc61aa4f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3353115312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3353115312
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2140203302
Short name T579
Test name
Test status
Simulation time 13493716999 ps
CPU time 15.84 seconds
Started Jul 16 06:55:03 PM PDT 24
Finished Jul 16 06:55:22 PM PDT 24
Peak memory 206988 kb
Host smart-b9d9f3dd-e6bc-44b7-84d7-66c79e1a91ba
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2140203302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2140203302
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.1565665270
Short name T1911
Test name
Test status
Simulation time 23364539058 ps
CPU time 21.68 seconds
Started Jul 16 06:55:02 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 207068 kb
Host smart-8d7785f5-8b7b-4ddd-8de8-2453f2ce9c2f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1565665270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.1565665270
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2454312927
Short name T1680
Test name
Test status
Simulation time 237438518 ps
CPU time 0.84 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:11 PM PDT 24
Peak memory 206816 kb
Host smart-504d994e-9618-4c82-a36e-af8a7ec6baec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24543
12927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2454312927
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3092788724
Short name T623
Test name
Test status
Simulation time 153526986 ps
CPU time 0.75 seconds
Started Jul 16 06:55:10 PM PDT 24
Finished Jul 16 06:55:15 PM PDT 24
Peak memory 206812 kb
Host smart-2ea5b0b5-d5a1-4510-a817-651f81c27391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927
88724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3092788724
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1889740104
Short name T1990
Test name
Test status
Simulation time 209964448 ps
CPU time 0.92 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 206856 kb
Host smart-211918ad-bd07-440d-9685-f4cd871c8392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18897
40104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1889740104
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2776743938
Short name T2359
Test name
Test status
Simulation time 5878126409 ps
CPU time 13.88 seconds
Started Jul 16 06:55:09 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 206992 kb
Host smart-f3a330b5-be80-464e-8e4e-01f69322d1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27767
43938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2776743938
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.425720245
Short name T855
Test name
Test status
Simulation time 311455649 ps
CPU time 1.09 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206700 kb
Host smart-184c22bc-348d-4230-850e-7177df8ab57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42572
0245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.425720245
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3174151866
Short name T1234
Test name
Test status
Simulation time 147664172 ps
CPU time 0.77 seconds
Started Jul 16 06:55:18 PM PDT 24
Finished Jul 16 06:55:22 PM PDT 24
Peak memory 206788 kb
Host smart-9753f1fe-bd19-4dc5-9a56-33bd592b01cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31741
51866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3174151866
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2167258786
Short name T1750
Test name
Test status
Simulation time 33374180 ps
CPU time 0.65 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:55:14 PM PDT 24
Peak memory 206876 kb
Host smart-632d4af7-f3e9-4408-a5fa-db5342a9b4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21672
58786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2167258786
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.826987340
Short name T652
Test name
Test status
Simulation time 857339271 ps
CPU time 2.15 seconds
Started Jul 16 06:55:10 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 207020 kb
Host smart-706249bc-07b6-4266-ad5a-799edd4435d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82698
7340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.826987340
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.360162608
Short name T1282
Test name
Test status
Simulation time 275245271 ps
CPU time 1.63 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206840 kb
Host smart-a4a43dd3-e81d-42d6-82f6-5287f1b6d765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36016
2608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.360162608
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2321078031
Short name T1026
Test name
Test status
Simulation time 205440236 ps
CPU time 0.92 seconds
Started Jul 16 06:55:03 PM PDT 24
Finished Jul 16 06:55:07 PM PDT 24
Peak memory 206572 kb
Host smart-193fb611-3481-458f-ac16-605dab32e3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23210
78031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2321078031
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1231960148
Short name T1662
Test name
Test status
Simulation time 151068807 ps
CPU time 0.75 seconds
Started Jul 16 06:55:04 PM PDT 24
Finished Jul 16 06:55:08 PM PDT 24
Peak memory 206804 kb
Host smart-cdff2a49-a7ba-47a6-887b-eb511ca25ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12319
60148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1231960148
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2940358101
Short name T2056
Test name
Test status
Simulation time 227555707 ps
CPU time 0.92 seconds
Started Jul 16 06:55:04 PM PDT 24
Finished Jul 16 06:55:07 PM PDT 24
Peak memory 206912 kb
Host smart-4f6963a1-51e5-4c44-bd2e-1515f039e655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
58101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2940358101
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3520083040
Short name T942
Test name
Test status
Simulation time 7750898429 ps
CPU time 219.76 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:58:50 PM PDT 24
Peak memory 206988 kb
Host smart-22ab8c13-b8b5-4206-9eac-e7542a27321f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3520083040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3520083040
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3461581589
Short name T877
Test name
Test status
Simulation time 7342396837 ps
CPU time 58.12 seconds
Started Jul 16 06:55:21 PM PDT 24
Finished Jul 16 06:56:22 PM PDT 24
Peak memory 207124 kb
Host smart-41529363-1726-443f-b84b-f8802305d795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34615
81589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3461581589
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.837915503
Short name T507
Test name
Test status
Simulation time 222154703 ps
CPU time 0.86 seconds
Started Jul 16 06:55:05 PM PDT 24
Finished Jul 16 06:55:08 PM PDT 24
Peak memory 206812 kb
Host smart-2e43d8b3-0291-4829-82a3-6754330b8853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83791
5503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.837915503
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3364770901
Short name T922
Test name
Test status
Simulation time 23321985995 ps
CPU time 28.91 seconds
Started Jul 16 06:55:04 PM PDT 24
Finished Jul 16 06:55:36 PM PDT 24
Peak memory 206908 kb
Host smart-25a60d78-eeed-492b-9013-f18a209add62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33647
70901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3364770901
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3680793024
Short name T340
Test name
Test status
Simulation time 3332490824 ps
CPU time 3.69 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:14 PM PDT 24
Peak memory 206952 kb
Host smart-a73da585-023c-45c1-871a-689d3fa582c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36807
93024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3680793024
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.554875583
Short name T1027
Test name
Test status
Simulation time 12159246423 ps
CPU time 110.31 seconds
Started Jul 16 06:55:10 PM PDT 24
Finished Jul 16 06:57:05 PM PDT 24
Peak memory 207008 kb
Host smart-6a2904d1-eea3-4ff7-8a49-530b6e923cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55487
5583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.554875583
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1209527533
Short name T517
Test name
Test status
Simulation time 7387448996 ps
CPU time 220.36 seconds
Started Jul 16 06:55:07 PM PDT 24
Finished Jul 16 06:58:52 PM PDT 24
Peak memory 207220 kb
Host smart-8bc3c9bc-a7ad-4b73-abc5-08908302266b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1209527533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1209527533
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3569225656
Short name T909
Test name
Test status
Simulation time 244268721 ps
CPU time 0.95 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:55:14 PM PDT 24
Peak memory 206880 kb
Host smart-e910be13-f63e-4893-8c3f-0a4bc3241975
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3569225656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3569225656
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.457094132
Short name T2106
Test name
Test status
Simulation time 199613288 ps
CPU time 0.86 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:10 PM PDT 24
Peak memory 206884 kb
Host smart-3815d080-3f6e-4347-91cf-85321091e24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45709
4132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.457094132
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.2143462193
Short name T2417
Test name
Test status
Simulation time 5152437249 ps
CPU time 142.4 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:57:36 PM PDT 24
Peak memory 207092 kb
Host smart-83a44dc1-1a15-44d7-8139-2bef96a6fdf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
62193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.2143462193
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.788681068
Short name T1314
Test name
Test status
Simulation time 4921730756 ps
CPU time 145.01 seconds
Started Jul 16 06:55:05 PM PDT 24
Finished Jul 16 06:57:33 PM PDT 24
Peak memory 207076 kb
Host smart-9f82a9ea-4c0b-402c-9927-529a6140688b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=788681068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.788681068
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.614687825
Short name T432
Test name
Test status
Simulation time 195199865 ps
CPU time 0.81 seconds
Started Jul 16 06:55:04 PM PDT 24
Finished Jul 16 06:55:08 PM PDT 24
Peak memory 206876 kb
Host smart-da9e1c19-66e8-4cad-a4ea-ec45e8ba11b8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=614687825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.614687825
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3495818137
Short name T23
Test name
Test status
Simulation time 151801847 ps
CPU time 0.77 seconds
Started Jul 16 06:55:09 PM PDT 24
Finished Jul 16 06:55:15 PM PDT 24
Peak memory 206744 kb
Host smart-a5de3eea-1a74-4a33-8f1b-e49f8dd2c668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958
18137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3495818137
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.937505135
Short name T2461
Test name
Test status
Simulation time 176007915 ps
CPU time 0.87 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206872 kb
Host smart-3ac25fe9-fd35-4664-9752-3fbad69d2202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93750
5135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.937505135
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3541258519
Short name T966
Test name
Test status
Simulation time 165834690 ps
CPU time 0.83 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:21 PM PDT 24
Peak memory 206748 kb
Host smart-bd98ed0f-f49b-42c7-98fe-c5375b539fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412
58519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3541258519
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.498679377
Short name T1808
Test name
Test status
Simulation time 173387642 ps
CPU time 0.79 seconds
Started Jul 16 06:55:11 PM PDT 24
Finished Jul 16 06:55:16 PM PDT 24
Peak memory 206716 kb
Host smart-aff22dda-0fe3-422c-bdf3-e8266580c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49867
9377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.498679377
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2169948567
Short name T499
Test name
Test status
Simulation time 183222947 ps
CPU time 0.85 seconds
Started Jul 16 06:55:07 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 206812 kb
Host smart-884c7d3d-48ca-49e5-8d55-94da142da411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21699
48567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2169948567
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1578255696
Short name T2723
Test name
Test status
Simulation time 153227260 ps
CPU time 0.83 seconds
Started Jul 16 06:55:26 PM PDT 24
Finished Jul 16 06:55:29 PM PDT 24
Peak memory 206756 kb
Host smart-bce5a284-b0a3-4e59-bc0f-958d6a1c5e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15782
55696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1578255696
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.416609359
Short name T786
Test name
Test status
Simulation time 213092786 ps
CPU time 0.94 seconds
Started Jul 16 06:55:03 PM PDT 24
Finished Jul 16 06:55:07 PM PDT 24
Peak memory 206860 kb
Host smart-5dc9eeb2-10cc-46c3-9339-aa9546efaaa7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=416609359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.416609359
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.624244708
Short name T1903
Test name
Test status
Simulation time 149534660 ps
CPU time 0.75 seconds
Started Jul 16 06:55:15 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 206880 kb
Host smart-a9452a56-45b6-4e32-b736-7abc232907de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62424
4708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.624244708
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2959059350
Short name T1119
Test name
Test status
Simulation time 41655916 ps
CPU time 0.65 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:18 PM PDT 24
Peak memory 206800 kb
Host smart-a0c573fc-30dd-4630-b3ad-b1a4456c14d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29590
59350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2959059350
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1193061656
Short name T2114
Test name
Test status
Simulation time 16946753620 ps
CPU time 45.21 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 207168 kb
Host smart-f285bc21-bbfc-4230-876a-c5d2b9329cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11930
61656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1193061656
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2122988195
Short name T2554
Test name
Test status
Simulation time 216042719 ps
CPU time 0.88 seconds
Started Jul 16 06:55:09 PM PDT 24
Finished Jul 16 06:55:14 PM PDT 24
Peak memory 206748 kb
Host smart-e8e7c129-6e72-4b9b-8c5f-993fbaed45c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229
88195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2122988195
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1348875818
Short name T1111
Test name
Test status
Simulation time 219850893 ps
CPU time 0.9 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:11 PM PDT 24
Peak memory 206888 kb
Host smart-ac95d8c7-2b23-451d-b590-f94bcda9f00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13488
75818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1348875818
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2848217032
Short name T486
Test name
Test status
Simulation time 229638723 ps
CPU time 0.89 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206868 kb
Host smart-08b03496-7121-4605-b8ce-9e55aebad9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28482
17032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2848217032
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.706967470
Short name T1890
Test name
Test status
Simulation time 193001672 ps
CPU time 0.82 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206852 kb
Host smart-3e25902b-5b88-443a-a0fb-6e440e721c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70696
7470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.706967470
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1523694395
Short name T2360
Test name
Test status
Simulation time 171950911 ps
CPU time 0.82 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:55:13 PM PDT 24
Peak memory 206800 kb
Host smart-e397c4a7-1556-4aff-a149-6161b3bf6c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15236
94395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1523694395
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3663537126
Short name T1202
Test name
Test status
Simulation time 158349939 ps
CPU time 0.77 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:20 PM PDT 24
Peak memory 206728 kb
Host smart-1b192f60-75e9-46fb-bfb9-ec9c81ed17a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36635
37126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3663537126
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.209659340
Short name T2220
Test name
Test status
Simulation time 153571352 ps
CPU time 0.79 seconds
Started Jul 16 06:55:09 PM PDT 24
Finished Jul 16 06:55:15 PM PDT 24
Peak memory 206852 kb
Host smart-60735f9e-a6eb-4cdb-a960-af4fade34073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20965
9340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.209659340
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1530353504
Short name T2216
Test name
Test status
Simulation time 227827395 ps
CPU time 0.94 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:18 PM PDT 24
Peak memory 206852 kb
Host smart-38bda2f5-e941-4013-8b00-2d75daa5e5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15303
53504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1530353504
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.4092622926
Short name T2383
Test name
Test status
Simulation time 3620201046 ps
CPU time 102.62 seconds
Started Jul 16 06:55:22 PM PDT 24
Finished Jul 16 06:57:07 PM PDT 24
Peak memory 207076 kb
Host smart-5ec1d707-1fe1-4cbd-b319-a9d316c5575d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4092622926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.4092622926
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1580933517
Short name T2345
Test name
Test status
Simulation time 154014851 ps
CPU time 0.77 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:20 PM PDT 24
Peak memory 206860 kb
Host smart-10704b9f-d0dc-46e3-8c58-1360b173a0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15809
33517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1580933517
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3525497780
Short name T917
Test name
Test status
Simulation time 207485143 ps
CPU time 0.83 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206856 kb
Host smart-55718dfb-660e-4bb3-84f2-c6c8538116c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35254
97780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3525497780
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.867129853
Short name T1771
Test name
Test status
Simulation time 1199891754 ps
CPU time 2.71 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 207020 kb
Host smart-2083d55b-40a8-4a94-911a-93f1b72b827c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86712
9853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.867129853
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.215540077
Short name T1275
Test name
Test status
Simulation time 5564225811 ps
CPU time 152.53 seconds
Started Jul 16 06:55:10 PM PDT 24
Finished Jul 16 06:57:47 PM PDT 24
Peak memory 206924 kb
Host smart-d8422bec-0a74-4eb9-9ffc-715f51299d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554
0077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.215540077
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.647518751
Short name T2104
Test name
Test status
Simulation time 40215744 ps
CPU time 0.71 seconds
Started Jul 16 06:55:11 PM PDT 24
Finished Jul 16 06:55:16 PM PDT 24
Peak memory 206868 kb
Host smart-7dbe4da2-83a9-4b3e-8bc6-3bb547e38832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=647518751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.647518751
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1410992142
Short name T1632
Test name
Test status
Simulation time 4367447002 ps
CPU time 4.98 seconds
Started Jul 16 06:55:07 PM PDT 24
Finished Jul 16 06:55:16 PM PDT 24
Peak memory 206932 kb
Host smart-ca2f87e6-eb39-4726-a751-ab3c4875936c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1410992142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1410992142
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3282847705
Short name T1986
Test name
Test status
Simulation time 13491961626 ps
CPU time 15.78 seconds
Started Jul 16 06:55:15 PM PDT 24
Finished Jul 16 06:55:34 PM PDT 24
Peak memory 207020 kb
Host smart-8f84cc92-e867-4364-9170-6b00f0085b72
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3282847705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3282847705
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3006971807
Short name T407
Test name
Test status
Simulation time 23393678296 ps
CPU time 23.25 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:55:35 PM PDT 24
Peak memory 207164 kb
Host smart-6ef344e1-9fbb-4430-b0d3-3a319451f273
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3006971807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3006971807
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2235361699
Short name T144
Test name
Test status
Simulation time 165086403 ps
CPU time 0.75 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206864 kb
Host smart-637f5278-5620-420a-9fa1-ac4988bbced3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22353
61699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2235361699
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1026418640
Short name T2698
Test name
Test status
Simulation time 144835098 ps
CPU time 0.84 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:55:14 PM PDT 24
Peak memory 206892 kb
Host smart-d82e1670-7701-46e5-8dfe-9098b093102f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264
18640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1026418640
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.322272941
Short name T1127
Test name
Test status
Simulation time 155203752 ps
CPU time 0.77 seconds
Started Jul 16 06:55:15 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 206816 kb
Host smart-02f479d7-085c-4f60-a429-7db547654560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32227
2941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.322272941
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3934507737
Short name T611
Test name
Test status
Simulation time 1108098976 ps
CPU time 2.7 seconds
Started Jul 16 06:55:20 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 207092 kb
Host smart-54f86c5b-22e7-44ce-a246-212916d69140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39345
07737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3934507737
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1958591912
Short name T1792
Test name
Test status
Simulation time 9557290867 ps
CPU time 17.77 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 207124 kb
Host smart-59e00109-b537-410b-9344-1c690b9923a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19585
91912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1958591912
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.1634155196
Short name T1298
Test name
Test status
Simulation time 464835665 ps
CPU time 1.37 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:21 PM PDT 24
Peak memory 206884 kb
Host smart-0af5054d-291b-4432-8369-b17c64a1f781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16341
55196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1634155196
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3150704840
Short name T1148
Test name
Test status
Simulation time 144389943 ps
CPU time 0.76 seconds
Started Jul 16 06:55:10 PM PDT 24
Finished Jul 16 06:55:15 PM PDT 24
Peak memory 206788 kb
Host smart-8517c533-e2d3-4440-b2a7-8a6242c4cece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507
04840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3150704840
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3010153354
Short name T1175
Test name
Test status
Simulation time 31646568 ps
CPU time 0.62 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206788 kb
Host smart-fdc8aef3-ddd1-45c8-98c1-abe270b88e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30101
53354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3010153354
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.57399186
Short name T1875
Test name
Test status
Simulation time 858686819 ps
CPU time 2.07 seconds
Started Jul 16 06:55:11 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 207012 kb
Host smart-c4c16148-9343-4963-adf7-2754eea830dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57399
186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.57399186
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.336673198
Short name T2522
Test name
Test status
Simulation time 173312055 ps
CPU time 1.37 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:21 PM PDT 24
Peak memory 207024 kb
Host smart-b7946d20-40df-44e0-8167-1e502e445e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33667
3198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.336673198
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1080472850
Short name T2343
Test name
Test status
Simulation time 230851249 ps
CPU time 0.85 seconds
Started Jul 16 06:55:23 PM PDT 24
Finished Jul 16 06:55:26 PM PDT 24
Peak memory 206856 kb
Host smart-ff928b5a-677a-4697-ae2e-9e50e60d1c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10804
72850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1080472850
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.271768524
Short name T1309
Test name
Test status
Simulation time 144099040 ps
CPU time 0.78 seconds
Started Jul 16 06:55:15 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 206812 kb
Host smart-b37ab4df-a11b-49ce-a6cf-641333f716dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27176
8524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.271768524
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3475343432
Short name T1150
Test name
Test status
Simulation time 174862832 ps
CPU time 0.84 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:20 PM PDT 24
Peak memory 206888 kb
Host smart-80d92637-f4ab-4f42-99bd-40b06e0b1228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34753
43432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3475343432
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.3436997657
Short name T634
Test name
Test status
Simulation time 8039921116 ps
CPU time 26.41 seconds
Started Jul 16 06:55:23 PM PDT 24
Finished Jul 16 06:55:52 PM PDT 24
Peak memory 207048 kb
Host smart-8da5564e-d541-4efe-932f-cfeb54c4cd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34369
97657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.3436997657
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2426408658
Short name T826
Test name
Test status
Simulation time 173838067 ps
CPU time 0.83 seconds
Started Jul 16 06:55:24 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 206828 kb
Host smart-ed9881ca-4105-470e-a662-a021558eba00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24264
08658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2426408658
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.788120
Short name T1287
Test name
Test status
Simulation time 23327073277 ps
CPU time 23.88 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:51 PM PDT 24
Peak memory 206404 kb
Host smart-d305b32d-98ac-4bd5-a4cf-6b5a61842089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78812
0 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.788120
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.851235973
Short name T737
Test name
Test status
Simulation time 3292427373 ps
CPU time 4.02 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 206924 kb
Host smart-df4bc09d-b832-431b-a541-9cdfff9e5c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85123
5973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.851235973
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1432718326
Short name T2546
Test name
Test status
Simulation time 9900725664 ps
CPU time 79.9 seconds
Started Jul 16 06:55:14 PM PDT 24
Finished Jul 16 06:56:37 PM PDT 24
Peak memory 207060 kb
Host smart-5f9a2036-3c6c-431c-81bb-22de9a086423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14327
18326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1432718326
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2177417202
Short name T1099
Test name
Test status
Simulation time 7005153736 ps
CPU time 200.99 seconds
Started Jul 16 06:55:20 PM PDT 24
Finished Jul 16 06:58:43 PM PDT 24
Peak memory 207044 kb
Host smart-a2a6b925-d4e5-4b3b-9f51-5f58c1a50cdb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2177417202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2177417202
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3239184128
Short name T1039
Test name
Test status
Simulation time 232902792 ps
CPU time 0.88 seconds
Started Jul 16 06:55:23 PM PDT 24
Finished Jul 16 06:55:26 PM PDT 24
Peak memory 206852 kb
Host smart-3eb75ee4-2563-452f-9d4e-8cc3d9ce3ab2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3239184128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3239184128
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4282818955
Short name T2540
Test name
Test status
Simulation time 188747845 ps
CPU time 0.85 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:28 PM PDT 24
Peak memory 206340 kb
Host smart-18f6a471-d865-4b51-b1bb-90e08de64be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42828
18955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4282818955
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.678795666
Short name T2096
Test name
Test status
Simulation time 3717348410 ps
CPU time 105.4 seconds
Started Jul 16 06:55:22 PM PDT 24
Finished Jul 16 06:57:10 PM PDT 24
Peak memory 207096 kb
Host smart-b856bfc5-9fe0-47f8-9439-d59d193facb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67879
5666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.678795666
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3512489471
Short name T1654
Test name
Test status
Simulation time 6111742584 ps
CPU time 174.05 seconds
Started Jul 16 06:55:22 PM PDT 24
Finished Jul 16 06:58:19 PM PDT 24
Peak memory 207104 kb
Host smart-c2d9151f-7fb6-4561-98ce-f4597876a8cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3512489471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3512489471
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3912105911
Short name T2490
Test name
Test status
Simulation time 174580246 ps
CPU time 0.78 seconds
Started Jul 16 06:55:22 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 206876 kb
Host smart-62e454f0-d009-4656-93e7-a9da9592003e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3912105911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3912105911
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2596886172
Short name T1457
Test name
Test status
Simulation time 161165999 ps
CPU time 0.83 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:28 PM PDT 24
Peak memory 206856 kb
Host smart-290354d3-6344-4f01-acdc-bd07221fad91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
86172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2596886172
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2080745488
Short name T2443
Test name
Test status
Simulation time 206479103 ps
CPU time 0.98 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:20 PM PDT 24
Peak memory 206728 kb
Host smart-f72605b5-a369-4822-8e54-fea01f6f715c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20807
45488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2080745488
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.129719316
Short name T2046
Test name
Test status
Simulation time 208028377 ps
CPU time 0.83 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:21 PM PDT 24
Peak memory 206748 kb
Host smart-65113ce3-316e-463c-96e4-642a0ef7307d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
9316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.129719316
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1178421982
Short name T1760
Test name
Test status
Simulation time 201002046 ps
CPU time 0.85 seconds
Started Jul 16 06:55:21 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 206860 kb
Host smart-dc60a9b9-d9ab-4dcd-be99-c1261cee3031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11784
21982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1178421982
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2357622463
Short name T2587
Test name
Test status
Simulation time 182676780 ps
CPU time 0.81 seconds
Started Jul 16 06:55:21 PM PDT 24
Finished Jul 16 06:55:24 PM PDT 24
Peak memory 206860 kb
Host smart-c0ec0e40-3eb0-4b47-927e-c19ee1f065c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23576
22463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2357622463
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.730999362
Short name T2322
Test name
Test status
Simulation time 146400285 ps
CPU time 0.81 seconds
Started Jul 16 06:55:21 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 206876 kb
Host smart-93999e13-1ed4-4cbc-b2c1-4a2f6fb85fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73099
9362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.730999362
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3454498502
Short name T974
Test name
Test status
Simulation time 242548225 ps
CPU time 0.95 seconds
Started Jul 16 06:55:21 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 206872 kb
Host smart-00676d9b-1247-4352-9da3-8cbe45380d81
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3454498502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3454498502
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3619837525
Short name T2447
Test name
Test status
Simulation time 148156227 ps
CPU time 0.8 seconds
Started Jul 16 06:55:15 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 206872 kb
Host smart-1356fcea-3f8e-44ae-b9d7-f63232d2c558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36198
37525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3619837525
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2761679925
Short name T32
Test name
Test status
Simulation time 60449404 ps
CPU time 0.69 seconds
Started Jul 16 06:55:21 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 206856 kb
Host smart-42088a9b-44d8-4cd4-b982-2bbc4f443cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27616
79925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2761679925
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2532928320
Short name T30
Test name
Test status
Simulation time 13375777496 ps
CPU time 29.31 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:46 PM PDT 24
Peak memory 207084 kb
Host smart-f94e2c1e-f33e-4adb-8607-ac646c0e9260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
28320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2532928320
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2942983763
Short name T2258
Test name
Test status
Simulation time 188594103 ps
CPU time 0.87 seconds
Started Jul 16 06:55:20 PM PDT 24
Finished Jul 16 06:55:24 PM PDT 24
Peak memory 206864 kb
Host smart-6d79c646-8427-4347-a5ad-c8e21d70a6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29429
83763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2942983763
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3292982886
Short name T1501
Test name
Test status
Simulation time 220508163 ps
CPU time 0.93 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206864 kb
Host smart-a517749d-035d-4f1f-a55a-eedeb0a868e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32929
82886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3292982886
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3977338450
Short name T2347
Test name
Test status
Simulation time 162905372 ps
CPU time 0.79 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:11 PM PDT 24
Peak memory 206636 kb
Host smart-60bab47e-7f5d-4b84-909c-faa3ed713b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39773
38450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3977338450
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2855559542
Short name T2064
Test name
Test status
Simulation time 200788454 ps
CPU time 0.84 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:55:13 PM PDT 24
Peak memory 206796 kb
Host smart-8a1069dc-a20d-4047-a2f2-3da8721c9147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28555
59542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2855559542
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.294377475
Short name T2285
Test name
Test status
Simulation time 188291215 ps
CPU time 0.83 seconds
Started Jul 16 06:55:07 PM PDT 24
Finished Jul 16 06:55:12 PM PDT 24
Peak memory 206864 kb
Host smart-0cdafdd1-2f3f-4789-a66b-8c66c4895038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29437
7475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.294377475
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.205702686
Short name T2192
Test name
Test status
Simulation time 144009269 ps
CPU time 0.75 seconds
Started Jul 16 06:55:06 PM PDT 24
Finished Jul 16 06:55:11 PM PDT 24
Peak memory 206604 kb
Host smart-890c1289-8d10-4371-9004-ab79312dce88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20570
2686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.205702686
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.4077787073
Short name T1459
Test name
Test status
Simulation time 163062895 ps
CPU time 0.81 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206864 kb
Host smart-4488e06e-72ae-4cb9-8ae6-9976e119e542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40777
87073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.4077787073
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2454790050
Short name T2012
Test name
Test status
Simulation time 211429579 ps
CPU time 0.88 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:17 PM PDT 24
Peak memory 206860 kb
Host smart-639d5249-dbcf-405a-a4ab-b9713e066dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24547
90050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2454790050
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3841386423
Short name T438
Test name
Test status
Simulation time 2930186190 ps
CPU time 79.88 seconds
Started Jul 16 06:55:20 PM PDT 24
Finished Jul 16 06:56:42 PM PDT 24
Peak memory 207072 kb
Host smart-6259bbde-1bce-4b3a-8a36-3f975c44aaef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3841386423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3841386423
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.62327445
Short name T657
Test name
Test status
Simulation time 215891589 ps
CPU time 0.85 seconds
Started Jul 16 06:55:15 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 206756 kb
Host smart-5732b97d-f721-4863-94c2-45f101403f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62327
445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.62327445
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2108072136
Short name T834
Test name
Test status
Simulation time 184080936 ps
CPU time 0.84 seconds
Started Jul 16 06:55:04 PM PDT 24
Finished Jul 16 06:55:08 PM PDT 24
Peak memory 206856 kb
Host smart-85f531f7-eb57-4792-a28a-ba45f7d79624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21080
72136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2108072136
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.1939056238
Short name T31
Test name
Test status
Simulation time 1232990017 ps
CPU time 2.44 seconds
Started Jul 16 06:55:12 PM PDT 24
Finished Jul 16 06:55:19 PM PDT 24
Peak memory 207080 kb
Host smart-f6aeac8f-5db5-44ab-8ad4-3057d642366e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19390
56238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.1939056238
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.4025372863
Short name T801
Test name
Test status
Simulation time 3616267396 ps
CPU time 100.84 seconds
Started Jul 16 06:55:08 PM PDT 24
Finished Jul 16 06:56:53 PM PDT 24
Peak memory 207064 kb
Host smart-64b90701-3db1-4d82-a878-930942bbf059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
72863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.4025372863
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.29120382
Short name T1902
Test name
Test status
Simulation time 43623679 ps
CPU time 0.67 seconds
Started Jul 16 06:55:26 PM PDT 24
Finished Jul 16 06:55:29 PM PDT 24
Peak memory 206852 kb
Host smart-a6be0b7c-3d9d-4538-8fb3-41ada6d8f35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=29120382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.29120382
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3018023322
Short name T1895
Test name
Test status
Simulation time 4106969050 ps
CPU time 5.8 seconds
Started Jul 16 06:55:13 PM PDT 24
Finished Jul 16 06:55:23 PM PDT 24
Peak memory 207136 kb
Host smart-f5fb7bb6-c758-4a4a-a0d8-13f2c7ac3362
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3018023322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3018023322
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1508279256
Short name T2655
Test name
Test status
Simulation time 13323833681 ps
CPU time 13.03 seconds
Started Jul 16 06:55:16 PM PDT 24
Finished Jul 16 06:55:32 PM PDT 24
Peak memory 206800 kb
Host smart-f188d144-e498-4407-9d3f-2ca719ad2986
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1508279256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1508279256
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3233230253
Short name T2033
Test name
Test status
Simulation time 23321555679 ps
CPU time 23.43 seconds
Started Jul 16 06:55:22 PM PDT 24
Finished Jul 16 06:55:48 PM PDT 24
Peak memory 206940 kb
Host smart-abfd1515-7d1a-456f-b0c1-90101efea656
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3233230253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3233230253
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3594048802
Short name T1467
Test name
Test status
Simulation time 151151332 ps
CPU time 0.77 seconds
Started Jul 16 06:55:23 PM PDT 24
Finished Jul 16 06:55:26 PM PDT 24
Peak memory 206868 kb
Host smart-1bf54fc9-97de-47b1-a7b5-93fa70e07796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35940
48802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3594048802
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1793552640
Short name T1506
Test name
Test status
Simulation time 181483117 ps
CPU time 0.83 seconds
Started Jul 16 06:55:22 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 206816 kb
Host smart-fe379a68-7c8c-4381-93e3-25c94e1d0e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17935
52640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1793552640
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3038291639
Short name T2353
Test name
Test status
Simulation time 227562150 ps
CPU time 1.04 seconds
Started Jul 16 06:55:30 PM PDT 24
Finished Jul 16 06:55:32 PM PDT 24
Peak memory 206864 kb
Host smart-7a1f1d4a-f942-41f7-beb0-fa8debe2eae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30382
91639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3038291639
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3005074923
Short name T2719
Test name
Test status
Simulation time 1238157966 ps
CPU time 2.84 seconds
Started Jul 16 06:55:30 PM PDT 24
Finished Jul 16 06:55:33 PM PDT 24
Peak memory 207084 kb
Host smart-c9d64a16-15fb-4983-b594-fecb14d4a9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30050
74923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3005074923
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.86236367
Short name T926
Test name
Test status
Simulation time 8024179173 ps
CPU time 17.29 seconds
Started Jul 16 06:55:19 PM PDT 24
Finished Jul 16 06:55:39 PM PDT 24
Peak memory 207076 kb
Host smart-f2e138d4-917c-418b-a3e8-094ec71f0c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86236
367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.86236367
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1307222183
Short name T933
Test name
Test status
Simulation time 410992122 ps
CPU time 1.27 seconds
Started Jul 16 06:55:24 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 206824 kb
Host smart-534eae6c-08fb-4345-8c63-f281c07cb829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13072
22183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1307222183
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.712460593
Short name T1569
Test name
Test status
Simulation time 172219294 ps
CPU time 0.82 seconds
Started Jul 16 06:55:17 PM PDT 24
Finished Jul 16 06:55:21 PM PDT 24
Peak memory 206880 kb
Host smart-c5cff307-3c04-4750-821b-320f75f984be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71246
0593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.712460593
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1661836523
Short name T1896
Test name
Test status
Simulation time 37860515 ps
CPU time 0.65 seconds
Started Jul 16 06:55:27 PM PDT 24
Finished Jul 16 06:55:30 PM PDT 24
Peak memory 206872 kb
Host smart-22079d7e-f33c-42e6-97e7-68a3afed620c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16618
36523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1661836523
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3712144536
Short name T138
Test name
Test status
Simulation time 982744093 ps
CPU time 2.29 seconds
Started Jul 16 06:55:18 PM PDT 24
Finished Jul 16 06:55:23 PM PDT 24
Peak memory 206988 kb
Host smart-15b3fefd-d07f-4289-9178-4c1743ee3fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37121
44536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3712144536
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3810436010
Short name T703
Test name
Test status
Simulation time 326540934 ps
CPU time 1.97 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:38 PM PDT 24
Peak memory 206848 kb
Host smart-af52089b-5da1-4a3b-ae3f-21163a51e061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38104
36010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3810436010
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1146773910
Short name T2062
Test name
Test status
Simulation time 223687149 ps
CPU time 0.91 seconds
Started Jul 16 06:55:19 PM PDT 24
Finished Jul 16 06:55:22 PM PDT 24
Peak memory 206748 kb
Host smart-7ee6ef20-0472-4b90-8def-ce55ff9eae74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11467
73910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1146773910
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2422809363
Short name T2103
Test name
Test status
Simulation time 168390128 ps
CPU time 0.83 seconds
Started Jul 16 06:55:17 PM PDT 24
Finished Jul 16 06:55:21 PM PDT 24
Peak memory 206892 kb
Host smart-3193f567-f5f1-4fc0-bd5d-9d452d5f06f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24228
09363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2422809363
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2680824961
Short name T2601
Test name
Test status
Simulation time 179934127 ps
CPU time 0.84 seconds
Started Jul 16 06:55:26 PM PDT 24
Finished Jul 16 06:55:28 PM PDT 24
Peak memory 206880 kb
Host smart-0f9478cc-ce84-4305-917f-dfba04cfdae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26808
24961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2680824961
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.4247458068
Short name T2237
Test name
Test status
Simulation time 11212975010 ps
CPU time 35.55 seconds
Started Jul 16 06:55:19 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 207144 kb
Host smart-5334db56-60d6-41fb-9198-f4bc094531ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474
58068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.4247458068
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.4122430299
Short name T2008
Test name
Test status
Simulation time 199575370 ps
CPU time 0.88 seconds
Started Jul 16 06:55:28 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 206908 kb
Host smart-f1cdb0a1-8934-4c94-ae4c-baf9e70c46ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41224
30299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.4122430299
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.3136589623
Short name T1155
Test name
Test status
Simulation time 23307479867 ps
CPU time 23.07 seconds
Started Jul 16 06:55:18 PM PDT 24
Finished Jul 16 06:55:44 PM PDT 24
Peak memory 206948 kb
Host smart-64a74146-8b4a-4464-b14a-40367326b92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31365
89623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.3136589623
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.924719491
Short name T1601
Test name
Test status
Simulation time 3368012970 ps
CPU time 3.91 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 206928 kb
Host smart-e57e218a-218f-497e-89cd-e0d707a1a45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92471
9491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.924719491
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2459703680
Short name T1345
Test name
Test status
Simulation time 7077413417 ps
CPU time 198.85 seconds
Started Jul 16 06:55:24 PM PDT 24
Finished Jul 16 06:58:45 PM PDT 24
Peak memory 207060 kb
Host smart-012d26b6-323b-41fc-8a75-a3f7d8055014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24597
03680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2459703680
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3512546178
Short name T2416
Test name
Test status
Simulation time 6354760520 ps
CPU time 57.89 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:56:25 PM PDT 24
Peak memory 207076 kb
Host smart-cee08618-8add-4415-81c9-46c0b4585278
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3512546178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3512546178
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1190826380
Short name T1133
Test name
Test status
Simulation time 242561604 ps
CPU time 0.96 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:28 PM PDT 24
Peak memory 206804 kb
Host smart-b0153f7f-d8fb-4d39-abb8-42bd5cccde78
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1190826380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1190826380
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.666258324
Short name T501
Test name
Test status
Simulation time 215800690 ps
CPU time 0.85 seconds
Started Jul 16 06:55:20 PM PDT 24
Finished Jul 16 06:55:23 PM PDT 24
Peak memory 206880 kb
Host smart-94f24588-0525-4228-addb-1be522590885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66625
8324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.666258324
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1446420207
Short name T1575
Test name
Test status
Simulation time 3883041129 ps
CPU time 28.65 seconds
Started Jul 16 06:55:22 PM PDT 24
Finished Jul 16 06:55:53 PM PDT 24
Peak memory 207052 kb
Host smart-d266e6cd-7022-430d-8cf3-1bd67233ae00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464
20207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1446420207
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2020808508
Short name T1612
Test name
Test status
Simulation time 6124775456 ps
CPU time 44.2 seconds
Started Jul 16 06:55:24 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 207076 kb
Host smart-c31fd632-8ccb-4df6-bd70-ea4e5f7614c1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2020808508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2020808508
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3547186319
Short name T1251
Test name
Test status
Simulation time 152775592 ps
CPU time 0.8 seconds
Started Jul 16 06:55:26 PM PDT 24
Finished Jul 16 06:55:29 PM PDT 24
Peak memory 206812 kb
Host smart-bdf309e5-4740-444c-ba62-f68e2d30c189
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3547186319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3547186319
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3917366365
Short name T1118
Test name
Test status
Simulation time 142066431 ps
CPU time 0.8 seconds
Started Jul 16 06:55:26 PM PDT 24
Finished Jul 16 06:55:29 PM PDT 24
Peak memory 206836 kb
Host smart-8ed71eeb-ffd0-4bd1-8eb7-50fcfeaf23ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39173
66365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3917366365
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3842033671
Short name T123
Test name
Test status
Simulation time 199520001 ps
CPU time 0.91 seconds
Started Jul 16 06:55:26 PM PDT 24
Finished Jul 16 06:55:29 PM PDT 24
Peak memory 206748 kb
Host smart-b21dd58e-c25f-479e-bbdd-9ddf7cd9d4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38420
33671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3842033671
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1645693726
Short name T327
Test name
Test status
Simulation time 180947490 ps
CPU time 0.85 seconds
Started Jul 16 06:55:19 PM PDT 24
Finished Jul 16 06:55:22 PM PDT 24
Peak memory 206844 kb
Host smart-c5775e21-af99-41e4-b21b-259617b8b50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16456
93726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1645693726
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2283173564
Short name T388
Test name
Test status
Simulation time 192352232 ps
CPU time 0.83 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206784 kb
Host smart-34acd33b-6cfc-463c-aa2e-8d9f12160bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22831
73564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2283173564
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1814566192
Short name T1514
Test name
Test status
Simulation time 268779614 ps
CPU time 0.9 seconds
Started Jul 16 06:55:18 PM PDT 24
Finished Jul 16 06:55:22 PM PDT 24
Peak memory 206868 kb
Host smart-58658f01-203e-4a88-9ffb-c986c848e203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18145
66192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1814566192
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.397834692
Short name T1780
Test name
Test status
Simulation time 148774320 ps
CPU time 0.76 seconds
Started Jul 16 06:55:23 PM PDT 24
Finished Jul 16 06:55:26 PM PDT 24
Peak memory 206888 kb
Host smart-4cdf5558-9d50-47fe-87a9-7b34aa4b8662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39783
4692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.397834692
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.17950032
Short name T1737
Test name
Test status
Simulation time 222822756 ps
CPU time 0.96 seconds
Started Jul 16 06:55:20 PM PDT 24
Finished Jul 16 06:55:24 PM PDT 24
Peak memory 206860 kb
Host smart-5f66a634-f733-40bd-8e1b-967130542a64
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=17950032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.17950032
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3198676059
Short name T2084
Test name
Test status
Simulation time 151422717 ps
CPU time 0.73 seconds
Started Jul 16 06:55:22 PM PDT 24
Finished Jul 16 06:55:25 PM PDT 24
Peak memory 206856 kb
Host smart-b2c04459-986f-47f8-97c4-d6ac1180282b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31986
76059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3198676059
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3247705530
Short name T26
Test name
Test status
Simulation time 33768174 ps
CPU time 0.66 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:28 PM PDT 24
Peak memory 206856 kb
Host smart-90ff27db-9d35-43e8-bf25-33341c0e5f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32477
05530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3247705530
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3402637412
Short name T1296
Test name
Test status
Simulation time 6731747392 ps
CPU time 15.78 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:42 PM PDT 24
Peak memory 207276 kb
Host smart-1647a2fc-a1d0-48d6-80b2-23a4fc79c6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34026
37412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3402637412
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2209449507
Short name T1523
Test name
Test status
Simulation time 195137567 ps
CPU time 0.88 seconds
Started Jul 16 06:55:19 PM PDT 24
Finished Jul 16 06:55:23 PM PDT 24
Peak memory 206872 kb
Host smart-97332464-bbc5-4314-9cdc-50cdd1518875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22094
49507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2209449507
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2302990422
Short name T467
Test name
Test status
Simulation time 160845292 ps
CPU time 0.81 seconds
Started Jul 16 06:55:24 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 206804 kb
Host smart-6d4336e0-cde3-47d9-9947-cdf652746296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23029
90422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2302990422
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.1428451456
Short name T2063
Test name
Test status
Simulation time 204977835 ps
CPU time 0.81 seconds
Started Jul 16 06:55:17 PM PDT 24
Finished Jul 16 06:55:21 PM PDT 24
Peak memory 206664 kb
Host smart-1ebaee51-aa94-414a-a393-4d13e6b36b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14284
51456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1428451456
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3369417938
Short name T2453
Test name
Test status
Simulation time 190322455 ps
CPU time 0.88 seconds
Started Jul 16 06:55:29 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 206860 kb
Host smart-0eb6b7dd-5bea-4091-9347-00fca5d2c240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33694
17938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3369417938
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.710233009
Short name T2696
Test name
Test status
Simulation time 159408773 ps
CPU time 0.86 seconds
Started Jul 16 06:55:28 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 206884 kb
Host smart-4084859f-ad26-46ef-aa83-4f0145090f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71023
3009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.710233009
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1985960030
Short name T923
Test name
Test status
Simulation time 144565706 ps
CPU time 0.78 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206800 kb
Host smart-4cdb14ff-4b6a-4c1d-b1b6-b8c9cf68b468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19859
60030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1985960030
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.385857110
Short name T940
Test name
Test status
Simulation time 158599477 ps
CPU time 0.84 seconds
Started Jul 16 06:55:26 PM PDT 24
Finished Jul 16 06:55:30 PM PDT 24
Peak memory 206880 kb
Host smart-04551390-17c4-4ada-b7bd-98107451f288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585
7110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.385857110
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4139133242
Short name T1756
Test name
Test status
Simulation time 302881834 ps
CPU time 1 seconds
Started Jul 16 06:55:28 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 206876 kb
Host smart-442f0e82-a9e9-47a0-8b42-833ee2be1be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41391
33242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4139133242
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.1932491909
Short name T1063
Test name
Test status
Simulation time 6184815396 ps
CPU time 58.11 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:56:34 PM PDT 24
Peak memory 207084 kb
Host smart-c006011e-9354-4013-b7d4-ace0e310584b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1932491909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.1932491909
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1305440518
Short name T495
Test name
Test status
Simulation time 145145505 ps
CPU time 0.8 seconds
Started Jul 16 06:55:29 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 206860 kb
Host smart-16465a99-72eb-45b8-83a2-85d3f4640d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13054
40518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1305440518
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3321022517
Short name T768
Test name
Test status
Simulation time 178760474 ps
CPU time 0.85 seconds
Started Jul 16 06:55:20 PM PDT 24
Finished Jul 16 06:55:24 PM PDT 24
Peak memory 206852 kb
Host smart-61f06f1a-2ee6-414d-9399-cc2b73eb4999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210
22517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3321022517
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.1703728545
Short name T2502
Test name
Test status
Simulation time 795669642 ps
CPU time 1.81 seconds
Started Jul 16 06:55:24 PM PDT 24
Finished Jul 16 06:55:28 PM PDT 24
Peak memory 206952 kb
Host smart-3d5ed59c-5303-49b2-b40d-f9baf53b1586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17037
28545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.1703728545
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3390368088
Short name T951
Test name
Test status
Simulation time 5348733772 ps
CPU time 143.68 seconds
Started Jul 16 06:55:30 PM PDT 24
Finished Jul 16 06:57:55 PM PDT 24
Peak memory 207084 kb
Host smart-ac1bbdf5-5dca-4b71-a3c1-00dd3feb1f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33903
68088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3390368088
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3391264670
Short name T177
Test name
Test status
Simulation time 44314640 ps
CPU time 0.71 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:55:41 PM PDT 24
Peak memory 206804 kb
Host smart-29dc96cc-1ab9-434f-9201-af3afacf68b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3391264670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3391264670
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.613263062
Short name T2242
Test name
Test status
Simulation time 4198872534 ps
CPU time 5.32 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:32 PM PDT 24
Peak memory 207124 kb
Host smart-549ae506-95e2-45e5-9c19-8ae609f887ae
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=613263062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.613263062
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1188043785
Short name T1765
Test name
Test status
Simulation time 13406831155 ps
CPU time 11.92 seconds
Started Jul 16 06:55:25 PM PDT 24
Finished Jul 16 06:55:39 PM PDT 24
Peak memory 206952 kb
Host smart-95913dcb-7ccb-4703-89b7-7719f5ed3aab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1188043785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1188043785
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2386127253
Short name T2388
Test name
Test status
Simulation time 23351447839 ps
CPU time 24.64 seconds
Started Jul 16 06:55:30 PM PDT 24
Finished Jul 16 06:55:56 PM PDT 24
Peak memory 206944 kb
Host smart-33e9e45b-e9c2-4174-9922-869719b7d3f6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2386127253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.2386127253
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1125032131
Short name T469
Test name
Test status
Simulation time 184271671 ps
CPU time 0.84 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206776 kb
Host smart-950fbfb0-2fe6-49eb-8d98-e71b7c7aec28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11250
32131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1125032131
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2343202048
Short name T378
Test name
Test status
Simulation time 143256511 ps
CPU time 0.79 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206824 kb
Host smart-37a35db1-7e34-4945-a5c7-89a0bc6bf04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23432
02048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2343202048
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.359142945
Short name T2711
Test name
Test status
Simulation time 451266631 ps
CPU time 1.36 seconds
Started Jul 16 06:55:26 PM PDT 24
Finished Jul 16 06:55:29 PM PDT 24
Peak memory 206888 kb
Host smart-5b542d82-3278-4e60-a4d0-a07bc4958417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35914
2945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.359142945
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1210750795
Short name T2296
Test name
Test status
Simulation time 589088014 ps
CPU time 1.6 seconds
Started Jul 16 06:55:20 PM PDT 24
Finished Jul 16 06:55:24 PM PDT 24
Peak memory 206796 kb
Host smart-6b25a31f-f57a-47f4-adad-d0033d6cebb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
50795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1210750795
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3267713983
Short name T2302
Test name
Test status
Simulation time 20668655009 ps
CPU time 36.93 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 207012 kb
Host smart-7104784e-ca5e-4940-a762-b56b83343ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32677
13983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3267713983
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3790399766
Short name T1125
Test name
Test status
Simulation time 494314960 ps
CPU time 1.54 seconds
Started Jul 16 06:55:28 PM PDT 24
Finished Jul 16 06:55:31 PM PDT 24
Peak memory 206904 kb
Host smart-5b1840bb-73be-46aa-ae5c-6f780c96d475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37903
99766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3790399766
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2763169886
Short name T2163
Test name
Test status
Simulation time 146833940 ps
CPU time 0.74 seconds
Started Jul 16 06:55:27 PM PDT 24
Finished Jul 16 06:55:30 PM PDT 24
Peak memory 206876 kb
Host smart-74d872a8-93e1-4c99-a65e-c9e29a1ab0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27631
69886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2763169886
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.704756840
Short name T221
Test name
Test status
Simulation time 43861424 ps
CPU time 0.66 seconds
Started Jul 16 06:55:23 PM PDT 24
Finished Jul 16 06:55:26 PM PDT 24
Peak memory 206876 kb
Host smart-af4996b6-7918-4fd6-a44a-32497d1a4e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70475
6840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.704756840
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2295051047
Short name T2715
Test name
Test status
Simulation time 921728062 ps
CPU time 2.34 seconds
Started Jul 16 06:55:23 PM PDT 24
Finished Jul 16 06:55:27 PM PDT 24
Peak memory 207008 kb
Host smart-dc79632c-ee5b-483b-99d2-54e24e44ed84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22950
51047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2295051047
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3617912402
Short name T1636
Test name
Test status
Simulation time 228692243 ps
CPU time 2 seconds
Started Jul 16 06:55:37 PM PDT 24
Finished Jul 16 06:55:43 PM PDT 24
Peak memory 207020 kb
Host smart-131dca93-4e64-4cf3-b634-e2e5cfbd4cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36179
12402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3617912402
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3326520181
Short name T989
Test name
Test status
Simulation time 275740507 ps
CPU time 0.92 seconds
Started Jul 16 06:55:56 PM PDT 24
Finished Jul 16 06:55:59 PM PDT 24
Peak memory 206828 kb
Host smart-9a5b22fe-3f90-44a2-ac62-e36405184078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33265
20181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3326520181
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.4109282932
Short name T1568
Test name
Test status
Simulation time 144968868 ps
CPU time 0.84 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:35 PM PDT 24
Peak memory 206892 kb
Host smart-25db4f69-8f35-4218-ad18-75b07c55b65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41092
82932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4109282932
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2758429783
Short name T2006
Test name
Test status
Simulation time 183535896 ps
CPU time 0.87 seconds
Started Jul 16 06:55:35 PM PDT 24
Finished Jul 16 06:55:39 PM PDT 24
Peak memory 206736 kb
Host smart-acb44f8a-97be-4b8a-9738-4f74f8c75674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27584
29783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2758429783
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.213016665
Short name T2019
Test name
Test status
Simulation time 7835549988 ps
CPU time 54.41 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 207136 kb
Host smart-d5f90ddc-7817-46ba-bc96-92d88fcf8cd8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=213016665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.213016665
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.2039253695
Short name T2603
Test name
Test status
Simulation time 6993725284 ps
CPU time 25.8 seconds
Started Jul 16 06:55:31 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 207084 kb
Host smart-d36718fb-7b22-4ef1-9f11-b5bcb93dd199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20392
53695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.2039253695
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.294207679
Short name T2488
Test name
Test status
Simulation time 219649128 ps
CPU time 0.92 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:55:40 PM PDT 24
Peak memory 206808 kb
Host smart-231ec17b-76df-4e3f-bbe9-f3abd2b46fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29420
7679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.294207679
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2276768805
Short name T2311
Test name
Test status
Simulation time 23356967891 ps
CPU time 23.07 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 206944 kb
Host smart-92d3f445-3dfb-4e7d-8615-2c6c07f38cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767
68805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2276768805
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.211973251
Short name T2513
Test name
Test status
Simulation time 3340798309 ps
CPU time 3.75 seconds
Started Jul 16 06:55:35 PM PDT 24
Finished Jul 16 06:55:42 PM PDT 24
Peak memory 206920 kb
Host smart-a82521c7-1f11-40bf-8f45-b38e2cde9cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21197
3251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.211973251
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.649440040
Short name T2380
Test name
Test status
Simulation time 10987885524 ps
CPU time 302.17 seconds
Started Jul 16 06:55:41 PM PDT 24
Finished Jul 16 07:00:45 PM PDT 24
Peak memory 207172 kb
Host smart-d6ecad3e-6c96-40ba-b4da-a12e637e9751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64944
0040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.649440040
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2794904364
Short name T1191
Test name
Test status
Simulation time 4959972761 ps
CPU time 44.6 seconds
Started Jul 16 06:55:45 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 207048 kb
Host smart-8c131e72-ff5a-44de-857b-20fff8642dc1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2794904364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2794904364
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.2749704071
Short name T544
Test name
Test status
Simulation time 256666409 ps
CPU time 0.9 seconds
Started Jul 16 06:55:50 PM PDT 24
Finished Jul 16 06:55:53 PM PDT 24
Peak memory 206908 kb
Host smart-e47cd477-f8e5-49c7-83e8-194217625fa4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2749704071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.2749704071
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3400793510
Short name T538
Test name
Test status
Simulation time 193231981 ps
CPU time 0.84 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 206824 kb
Host smart-420743f3-2925-400e-b72a-539a7ca5a237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34007
93510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3400793510
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.160096489
Short name T1283
Test name
Test status
Simulation time 5769312189 ps
CPU time 39.98 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:56:34 PM PDT 24
Peak memory 207116 kb
Host smart-aeb1c60f-0410-4a9c-aee2-2e1744216e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
6489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.160096489
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.1979573321
Short name T701
Test name
Test status
Simulation time 4741032538 ps
CPU time 45.65 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:56:25 PM PDT 24
Peak memory 207068 kb
Host smart-180bfb85-620f-4442-958d-e5b7793f655f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1979573321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1979573321
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2207823515
Short name T1237
Test name
Test status
Simulation time 151345256 ps
CPU time 0.81 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:35 PM PDT 24
Peak memory 206888 kb
Host smart-bcef4c03-e449-4d4d-9f19-81f746d875c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2207823515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2207823515
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1405414485
Short name T674
Test name
Test status
Simulation time 152318968 ps
CPU time 0.86 seconds
Started Jul 16 06:56:00 PM PDT 24
Finished Jul 16 06:56:02 PM PDT 24
Peak memory 206904 kb
Host smart-45d73162-45d0-4afa-94a6-fbef4d204335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14054
14485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1405414485
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1057735730
Short name T124
Test name
Test status
Simulation time 205556635 ps
CPU time 0.85 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206892 kb
Host smart-78d63ecb-84e2-4162-8604-15426f3a239d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10577
35730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1057735730
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.619513192
Short name T2283
Test name
Test status
Simulation time 197074975 ps
CPU time 0.86 seconds
Started Jul 16 06:55:32 PM PDT 24
Finished Jul 16 06:55:34 PM PDT 24
Peak memory 206856 kb
Host smart-6214cdea-744f-40fa-ba19-d9f407dbf565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61951
3192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.619513192
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.4270751844
Short name T1217
Test name
Test status
Simulation time 204203539 ps
CPU time 0.92 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206888 kb
Host smart-6626301e-2e8c-4b23-968c-8424bd3be3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42707
51844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.4270751844
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3383879188
Short name T1331
Test name
Test status
Simulation time 183393560 ps
CPU time 0.84 seconds
Started Jul 16 06:55:43 PM PDT 24
Finished Jul 16 06:55:45 PM PDT 24
Peak memory 206856 kb
Host smart-f0679f87-1426-42f8-bfd6-2ab889eac347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838
79188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3383879188
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2915042448
Short name T1366
Test name
Test status
Simulation time 162376850 ps
CPU time 0.76 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:55:41 PM PDT 24
Peak memory 206860 kb
Host smart-93b4be15-190f-44c9-985a-911ac195fb88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29150
42448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2915042448
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.1458009923
Short name T2598
Test name
Test status
Simulation time 226219414 ps
CPU time 0.95 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:55:38 PM PDT 24
Peak memory 206928 kb
Host smart-0af68acb-3db0-4682-93dc-af3d0e53760c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1458009923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1458009923
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1461413603
Short name T2487
Test name
Test status
Simulation time 138849330 ps
CPU time 0.78 seconds
Started Jul 16 06:55:38 PM PDT 24
Finished Jul 16 06:55:42 PM PDT 24
Peak memory 206752 kb
Host smart-340ac7ca-261c-49ba-a120-ddf8d3e1c6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14614
13603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1461413603
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.608363157
Short name T1820
Test name
Test status
Simulation time 49897963 ps
CPU time 0.68 seconds
Started Jul 16 06:55:37 PM PDT 24
Finished Jul 16 06:55:41 PM PDT 24
Peak memory 206872 kb
Host smart-e3efbb3f-79d1-4de1-8139-066fb18d1960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60836
3157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.608363157
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3177779351
Short name T1892
Test name
Test status
Simulation time 10718960262 ps
CPU time 24.18 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:56:01 PM PDT 24
Peak memory 207208 kb
Host smart-70286dc4-bad8-4de0-8663-436c7b67ebed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31777
79351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3177779351
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2419061591
Short name T2590
Test name
Test status
Simulation time 180326098 ps
CPU time 0.83 seconds
Started Jul 16 06:55:40 PM PDT 24
Finished Jul 16 06:55:43 PM PDT 24
Peak memory 206884 kb
Host smart-e7610bf4-443b-46e0-b151-f040eee05946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24190
61591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2419061591
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1624992133
Short name T358
Test name
Test status
Simulation time 196015191 ps
CPU time 0.85 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:35 PM PDT 24
Peak memory 206860 kb
Host smart-2372a06f-0e1a-4f52-9a5e-a86e6bd403af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16249
92133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1624992133
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.2409154897
Short name T1535
Test name
Test status
Simulation time 194452804 ps
CPU time 0.8 seconds
Started Jul 16 06:55:31 PM PDT 24
Finished Jul 16 06:55:33 PM PDT 24
Peak memory 206872 kb
Host smart-e793bca6-e08b-4104-a11f-24feeb5682e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24091
54897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.2409154897
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.2330173019
Short name T1245
Test name
Test status
Simulation time 162146893 ps
CPU time 0.78 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206868 kb
Host smart-6eefdf45-633b-4f7b-8a30-96b2d62a5524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23301
73019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.2330173019
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.938836754
Short name T1402
Test name
Test status
Simulation time 187877429 ps
CPU time 0.78 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206864 kb
Host smart-6a9d69cf-9871-4ac6-aba4-05a1f0796314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93883
6754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.938836754
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.4227668287
Short name T1319
Test name
Test status
Simulation time 157580376 ps
CPU time 0.77 seconds
Started Jul 16 06:55:35 PM PDT 24
Finished Jul 16 06:55:39 PM PDT 24
Peak memory 206788 kb
Host smart-bea5a028-cf29-4102-bf3b-6f239e1fa919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42276
68287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.4227668287
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2412047729
Short name T1910
Test name
Test status
Simulation time 189388033 ps
CPU time 0.81 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 206804 kb
Host smart-1fc70662-3c76-4c90-9e5d-98d66e649764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24120
47729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2412047729
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2359339605
Short name T2243
Test name
Test status
Simulation time 206232547 ps
CPU time 0.86 seconds
Started Jul 16 06:55:31 PM PDT 24
Finished Jul 16 06:55:33 PM PDT 24
Peak memory 206876 kb
Host smart-20489fda-f1f8-4389-8d9d-f0d4f8dc5e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23593
39605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2359339605
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.675418494
Short name T347
Test name
Test status
Simulation time 4216167062 ps
CPU time 122.04 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:57:38 PM PDT 24
Peak memory 207204 kb
Host smart-160c513e-7de5-43bc-a603-7f07ca65ef54
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=675418494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.675418494
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2541994732
Short name T1715
Test name
Test status
Simulation time 177900300 ps
CPU time 0.85 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:36 PM PDT 24
Peak memory 206872 kb
Host smart-97ba8eda-6424-4415-adc7-4b6090b8749b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25419
94732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2541994732
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.4270948330
Short name T626
Test name
Test status
Simulation time 200895353 ps
CPU time 0.88 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:55:41 PM PDT 24
Peak memory 206852 kb
Host smart-63505aed-4d6d-4505-b4c1-a40db28db351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42709
48330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.4270948330
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.658832638
Short name T1909
Test name
Test status
Simulation time 858178941 ps
CPU time 1.85 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:55:42 PM PDT 24
Peak memory 207032 kb
Host smart-90028aab-150f-4e6e-be5c-b278687b0b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65883
2638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.658832638
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1527789018
Short name T2520
Test name
Test status
Simulation time 4210733184 ps
CPU time 29.29 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:56:09 PM PDT 24
Peak memory 206960 kb
Host smart-1f842520-bb27-467f-a9e6-3f3b53a669e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
89018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1527789018
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3196816862
Short name T1531
Test name
Test status
Simulation time 34797166 ps
CPU time 0.67 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 206796 kb
Host smart-17483148-116d-499d-9786-8279d1b2d460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3196816862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3196816862
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.944405771
Short name T2051
Test name
Test status
Simulation time 4361529454 ps
CPU time 5.79 seconds
Started Jul 16 06:55:35 PM PDT 24
Finished Jul 16 06:55:44 PM PDT 24
Peak memory 207008 kb
Host smart-45950c8d-ecfb-4e59-b367-1e4f4e5bd0bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=944405771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.944405771
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2670946881
Short name T2199
Test name
Test status
Simulation time 13516034566 ps
CPU time 14.95 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206940 kb
Host smart-d479c1ea-65a1-41fb-8545-584450917265
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2670946881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2670946881
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.4211684733
Short name T2402
Test name
Test status
Simulation time 23389591556 ps
CPU time 27.21 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:56:23 PM PDT 24
Peak memory 206896 kb
Host smart-20125b3a-16dc-4533-a5b2-8e8d501dcbd3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4211684733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.4211684733
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1564179792
Short name T436
Test name
Test status
Simulation time 164843335 ps
CPU time 0.83 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:55:40 PM PDT 24
Peak memory 206820 kb
Host smart-09f70d8f-ab87-4578-8a82-4f15bd8e9798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15641
79792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1564179792
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2293346112
Short name T1621
Test name
Test status
Simulation time 144606587 ps
CPU time 0.8 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:55:40 PM PDT 24
Peak memory 206852 kb
Host smart-94565e5d-1537-4f72-914e-15bfab39d203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22933
46112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2293346112
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2945124564
Short name T101
Test name
Test status
Simulation time 372689403 ps
CPU time 1.26 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 206816 kb
Host smart-a64ed5b6-aa31-44ef-a036-928ba3cba225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29451
24564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2945124564
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3821319699
Short name T1877
Test name
Test status
Simulation time 635734107 ps
CPU time 1.59 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 206832 kb
Host smart-74ecf086-7980-4148-bffe-18ffcba895f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38213
19699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3821319699
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.3002125915
Short name T1951
Test name
Test status
Simulation time 19694424298 ps
CPU time 35.85 seconds
Started Jul 16 06:55:36 PM PDT 24
Finished Jul 16 06:56:15 PM PDT 24
Peak memory 207044 kb
Host smart-4b8717a9-39af-4cef-a0d0-99a3b1ed6ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30021
25915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3002125915
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3789361505
Short name T208
Test name
Test status
Simulation time 505229910 ps
CPU time 1.39 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206848 kb
Host smart-9b92b4c6-5e65-484c-bb7f-d1fb44028f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37893
61505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3789361505
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.68126706
Short name T899
Test name
Test status
Simulation time 143980542 ps
CPU time 0.78 seconds
Started Jul 16 06:55:35 PM PDT 24
Finished Jul 16 06:55:39 PM PDT 24
Peak memory 206736 kb
Host smart-1e798d29-014b-4b90-87bb-b91e22557927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68126
706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.68126706
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2591847731
Short name T1157
Test name
Test status
Simulation time 69406100 ps
CPU time 0.68 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:56 PM PDT 24
Peak memory 206796 kb
Host smart-59afe7f9-ca74-41e4-ac83-f7eb7e18cf77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25918
47731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2591847731
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1093892766
Short name T2638
Test name
Test status
Simulation time 1022021638 ps
CPU time 2.31 seconds
Started Jul 16 06:55:42 PM PDT 24
Finished Jul 16 06:55:45 PM PDT 24
Peak memory 206980 kb
Host smart-f718115d-0491-4509-b790-a6676873a7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10938
92766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1093892766
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.312671625
Short name T338
Test name
Test status
Simulation time 328886686 ps
CPU time 2.15 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:55:38 PM PDT 24
Peak memory 207220 kb
Host smart-eedb3dc3-fbb2-4688-b6bb-d0f9d15e087f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31267
1625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.312671625
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3206250807
Short name T2545
Test name
Test status
Simulation time 222257213 ps
CPU time 0.84 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 206816 kb
Host smart-825eee92-3494-46d3-89cb-228e18a154a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32062
50807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3206250807
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2116549600
Short name T2044
Test name
Test status
Simulation time 142187105 ps
CPU time 0.8 seconds
Started Jul 16 06:55:43 PM PDT 24
Finished Jul 16 06:55:45 PM PDT 24
Peak memory 206824 kb
Host smart-3a0649ab-6819-4381-9f8c-001f77d1a649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21165
49600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2116549600
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2558213
Short name T2465
Test name
Test status
Simulation time 216512844 ps
CPU time 0.88 seconds
Started Jul 16 06:55:55 PM PDT 24
Finished Jul 16 06:55:59 PM PDT 24
Peak memory 206828 kb
Host smart-58027d34-07f2-41af-9e21-669d032b9c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25582
13 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2558213
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.543850798
Short name T2676
Test name
Test status
Simulation time 6945514109 ps
CPU time 62.82 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:56:59 PM PDT 24
Peak memory 207092 kb
Host smart-1778b5b1-5af1-4ed2-aaad-7041d2d9896f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=543850798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.543850798
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.3758064211
Short name T2731
Test name
Test status
Simulation time 9639794130 ps
CPU time 27.66 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:56:03 PM PDT 24
Peak memory 207252 kb
Host smart-2366e203-7a23-4f60-9188-aadd507f4c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37580
64211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.3758064211
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3347224136
Short name T344
Test name
Test status
Simulation time 182393662 ps
CPU time 0.85 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:55:37 PM PDT 24
Peak memory 206868 kb
Host smart-e9bd3fb6-6ce7-47fe-a672-4c7709f2de08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33472
24136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3347224136
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2525114484
Short name T2377
Test name
Test status
Simulation time 23311927542 ps
CPU time 29.77 seconds
Started Jul 16 06:55:32 PM PDT 24
Finished Jul 16 06:56:03 PM PDT 24
Peak memory 206920 kb
Host smart-3ec7035a-fe91-446a-b70d-5bf2bca76ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25251
14484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2525114484
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2986611609
Short name T1867
Test name
Test status
Simulation time 3315664078 ps
CPU time 3.58 seconds
Started Jul 16 06:55:39 PM PDT 24
Finished Jul 16 06:55:45 PM PDT 24
Peak memory 206852 kb
Host smart-d691e46d-1513-4239-a727-6b88322bf35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29866
11609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2986611609
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1514306556
Short name T1507
Test name
Test status
Simulation time 11749470122 ps
CPU time 112.48 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:57:29 PM PDT 24
Peak memory 207140 kb
Host smart-b7b8075d-5aa9-4a1c-874d-088e18995019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15143
06556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1514306556
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.433389750
Short name T1980
Test name
Test status
Simulation time 6504800447 ps
CPU time 63.54 seconds
Started Jul 16 06:55:35 PM PDT 24
Finished Jul 16 06:56:41 PM PDT 24
Peak memory 206980 kb
Host smart-b4b64310-e481-4e28-a442-ba25f8fe82ca
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=433389750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.433389750
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1336508158
Short name T2221
Test name
Test status
Simulation time 238371604 ps
CPU time 0.93 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:55:38 PM PDT 24
Peak memory 206884 kb
Host smart-1f98d225-d98c-464b-8727-5ece19b8c345
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1336508158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1336508158
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.618430238
Short name T820
Test name
Test status
Simulation time 186522446 ps
CPU time 0.86 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:55:36 PM PDT 24
Peak memory 206748 kb
Host smart-153f02d5-8c06-4180-b154-2fce86eb15f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61843
0238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.618430238
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.552853594
Short name T1130
Test name
Test status
Simulation time 5827504994 ps
CPU time 53.04 seconds
Started Jul 16 06:55:33 PM PDT 24
Finished Jul 16 06:56:29 PM PDT 24
Peak memory 207248 kb
Host smart-f4ccd048-7aa9-4383-b224-b08bdf8b950b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55285
3594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.552853594
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.421388820
Short name T1894
Test name
Test status
Simulation time 5579061694 ps
CPU time 39.23 seconds
Started Jul 16 06:55:34 PM PDT 24
Finished Jul 16 06:56:17 PM PDT 24
Peak memory 207240 kb
Host smart-0bc356f9-aeb2-4210-82ea-a2f6ab8b026e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=421388820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.421388820
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.3978556675
Short name T1109
Test name
Test status
Simulation time 156962635 ps
CPU time 0.81 seconds
Started Jul 16 06:55:35 PM PDT 24
Finished Jul 16 06:55:39 PM PDT 24
Peak memory 206860 kb
Host smart-5d92aafd-b8d4-433c-b4dd-ac0b48da1249
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3978556675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.3978556675
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1711197387
Short name T991
Test name
Test status
Simulation time 203060475 ps
CPU time 0.82 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206792 kb
Host smart-63db6408-4551-4e29-b183-a564dbcafae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17111
97387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1711197387
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.385563325
Short name T115
Test name
Test status
Simulation time 205805836 ps
CPU time 0.85 seconds
Started Jul 16 06:55:41 PM PDT 24
Finished Jul 16 06:55:43 PM PDT 24
Peak memory 206880 kb
Host smart-304e157d-8d90-4d8c-b204-d9cda4bc74c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38556
3325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.385563325
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.611675944
Short name T2157
Test name
Test status
Simulation time 186181156 ps
CPU time 0.83 seconds
Started Jul 16 06:55:58 PM PDT 24
Finished Jul 16 06:56:00 PM PDT 24
Peak memory 206808 kb
Host smart-c1fda570-8c3e-4dca-b63b-7a1273c92731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61167
5944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.611675944
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3218030149
Short name T2430
Test name
Test status
Simulation time 169701788 ps
CPU time 0.8 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206892 kb
Host smart-c70eb0a5-2197-411d-8f67-35a27c51cd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32180
30149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3218030149
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.4110107186
Short name T1288
Test name
Test status
Simulation time 201273079 ps
CPU time 0.84 seconds
Started Jul 16 06:55:49 PM PDT 24
Finished Jul 16 06:55:50 PM PDT 24
Peak memory 206736 kb
Host smart-d598cdd1-ede5-43bc-99d4-ec14fb72af6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41101
07186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.4110107186
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1854306033
Short name T1475
Test name
Test status
Simulation time 180177379 ps
CPU time 0.81 seconds
Started Jul 16 06:55:55 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 206896 kb
Host smart-5138451a-cae5-49cb-946e-75b7e2f5c9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18543
06033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1854306033
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1518097557
Short name T1003
Test name
Test status
Simulation time 237296675 ps
CPU time 0.92 seconds
Started Jul 16 06:55:50 PM PDT 24
Finished Jul 16 06:55:53 PM PDT 24
Peak memory 206872 kb
Host smart-1f6c6e93-e45a-44ff-98ee-8d5aeeac967f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1518097557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1518097557
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3443958635
Short name T1616
Test name
Test status
Simulation time 154673350 ps
CPU time 0.82 seconds
Started Jul 16 06:55:47 PM PDT 24
Finished Jul 16 06:55:48 PM PDT 24
Peak memory 206852 kb
Host smart-b7eefa52-f1d6-4298-a28e-fc209a95a164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34439
58635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3443958635
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.4097612350
Short name T853
Test name
Test status
Simulation time 56438492 ps
CPU time 0.67 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 206868 kb
Host smart-52bd88f9-7252-4b88-a957-0a3f951fac21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40976
12350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.4097612350
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1977333099
Short name T880
Test name
Test status
Simulation time 12934978326 ps
CPU time 26.63 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:56:20 PM PDT 24
Peak memory 207100 kb
Host smart-2cc14001-4056-4e63-a293-e6c6ecef3280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19773
33099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1977333099
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2670286938
Short name T276
Test name
Test status
Simulation time 190540202 ps
CPU time 0.91 seconds
Started Jul 16 06:55:47 PM PDT 24
Finished Jul 16 06:55:49 PM PDT 24
Peak memory 206856 kb
Host smart-bd7ce92c-4d1c-4454-8c0f-fe122b9ae674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26702
86938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2670286938
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.331780606
Short name T1040
Test name
Test status
Simulation time 232506802 ps
CPU time 0.91 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 206844 kb
Host smart-f2f919b6-97ec-40f0-98bf-cb53e8d1ed2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33178
0606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.331780606
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2523196783
Short name T822
Test name
Test status
Simulation time 236922060 ps
CPU time 0.85 seconds
Started Jul 16 06:55:49 PM PDT 24
Finished Jul 16 06:55:50 PM PDT 24
Peak memory 206888 kb
Host smart-e6e16d2e-452c-4f62-90d3-7b3f7bdf2e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25231
96783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2523196783
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3096983338
Short name T300
Test name
Test status
Simulation time 147194251 ps
CPU time 0.81 seconds
Started Jul 16 06:55:47 PM PDT 24
Finished Jul 16 06:55:48 PM PDT 24
Peak memory 206900 kb
Host smart-554c6d5c-ed02-44c6-8d23-be952f4fe0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
83338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3096983338
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1713716687
Short name T2218
Test name
Test status
Simulation time 139562743 ps
CPU time 0.79 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:53 PM PDT 24
Peak memory 206836 kb
Host smart-e95e20c8-0c25-42d3-a2e7-cec02984cbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17137
16687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1713716687
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2042522875
Short name T20
Test name
Test status
Simulation time 148420015 ps
CPU time 0.81 seconds
Started Jul 16 06:56:02 PM PDT 24
Finished Jul 16 06:56:04 PM PDT 24
Peak memory 206820 kb
Host smart-c3a25713-0a64-4ccf-8e79-925dc76ffcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20425
22875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2042522875
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.711024486
Short name T1320
Test name
Test status
Simulation time 175347498 ps
CPU time 0.79 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206800 kb
Host smart-915bf434-a04f-4f5f-95e2-07301ae37b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71102
4486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.711024486
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2841904279
Short name T1347
Test name
Test status
Simulation time 242659167 ps
CPU time 0.89 seconds
Started Jul 16 06:55:55 PM PDT 24
Finished Jul 16 06:55:59 PM PDT 24
Peak memory 206868 kb
Host smart-280e224b-d064-41ee-ac4c-d602a2ca5c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28419
04279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2841904279
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3811693271
Short name T410
Test name
Test status
Simulation time 4840568598 ps
CPU time 131.29 seconds
Started Jul 16 06:55:56 PM PDT 24
Finished Jul 16 06:58:10 PM PDT 24
Peak memory 207112 kb
Host smart-eb3e19db-26a0-4558-9a04-ceb391e8dbf9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3811693271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3811693271
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1877749160
Short name T1966
Test name
Test status
Simulation time 185008868 ps
CPU time 0.82 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206864 kb
Host smart-44ecf43e-8d35-4c86-be79-69de2fd9f5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18777
49160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1877749160
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.905221942
Short name T2748
Test name
Test status
Simulation time 145698217 ps
CPU time 0.82 seconds
Started Jul 16 06:55:50 PM PDT 24
Finished Jul 16 06:55:52 PM PDT 24
Peak memory 206772 kb
Host smart-e956c940-85df-4f37-80b0-aa8740e97c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90522
1942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.905221942
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.41801866
Short name T850
Test name
Test status
Simulation time 708057200 ps
CPU time 1.78 seconds
Started Jul 16 06:55:48 PM PDT 24
Finished Jul 16 06:55:51 PM PDT 24
Peak memory 206956 kb
Host smart-2ebb97d0-3f7f-4e5a-864b-95021a345f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801
866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.41801866
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.4005304146
Short name T1637
Test name
Test status
Simulation time 5789620000 ps
CPU time 41.97 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:56:39 PM PDT 24
Peak memory 206928 kb
Host smart-583c30e0-6092-4fdf-80d7-92a941813536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40053
04146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.4005304146
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1242614513
Short name T2048
Test name
Test status
Simulation time 82793148 ps
CPU time 0.74 seconds
Started Jul 16 06:55:58 PM PDT 24
Finished Jul 16 06:56:00 PM PDT 24
Peak memory 206900 kb
Host smart-6c0a6355-9002-4e98-90b6-7ad43b7690b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1242614513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1242614513
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2637868357
Short name T1958
Test name
Test status
Simulation time 3764972912 ps
CPU time 4.9 seconds
Started Jul 16 06:55:56 PM PDT 24
Finished Jul 16 06:56:04 PM PDT 24
Peak memory 206940 kb
Host smart-9e4ed670-8031-479b-beff-5b1a38ffe08d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2637868357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.2637868357
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1900121738
Short name T2203
Test name
Test status
Simulation time 13365646747 ps
CPU time 12.04 seconds
Started Jul 16 06:55:48 PM PDT 24
Finished Jul 16 06:56:01 PM PDT 24
Peak memory 207148 kb
Host smart-e87091e3-edd2-4093-95bb-1b994e8417cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1900121738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1900121738
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1374104556
Short name T336
Test name
Test status
Simulation time 23381031254 ps
CPU time 27 seconds
Started Jul 16 06:55:46 PM PDT 24
Finished Jul 16 06:56:14 PM PDT 24
Peak memory 206956 kb
Host smart-2e021e7d-687b-4e96-a72a-b497ef0feac8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1374104556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1374104556
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3888923437
Short name T2211
Test name
Test status
Simulation time 169995697 ps
CPU time 0.82 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:56 PM PDT 24
Peak memory 206756 kb
Host smart-a41b67a9-4049-4eb7-8e00-368ed67207b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38889
23437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3888923437
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.479700605
Short name T1630
Test name
Test status
Simulation time 193789213 ps
CPU time 0.82 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:56 PM PDT 24
Peak memory 206752 kb
Host smart-ebb9e77f-4c8d-4630-acb1-7ef58bd39398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47970
0605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.479700605
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.141287750
Short name T2538
Test name
Test status
Simulation time 174074946 ps
CPU time 0.84 seconds
Started Jul 16 06:55:57 PM PDT 24
Finished Jul 16 06:56:00 PM PDT 24
Peak memory 206852 kb
Host smart-483cb957-8cdd-44fe-adf0-af0843fcf241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14128
7750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.141287750
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2452370894
Short name T2559
Test name
Test status
Simulation time 1097853022 ps
CPU time 2.55 seconds
Started Jul 16 06:55:55 PM PDT 24
Finished Jul 16 06:56:01 PM PDT 24
Peak memory 206992 kb
Host smart-742f4eb2-d4c1-440b-8c38-05e1fd2aaf54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24523
70894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2452370894
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1232205525
Short name T2746
Test name
Test status
Simulation time 9758804976 ps
CPU time 21.13 seconds
Started Jul 16 06:55:50 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 207060 kb
Host smart-a89bf4f9-5617-4691-97a2-9788f7bae4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12322
05525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1232205525
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1483318843
Short name T2259
Test name
Test status
Simulation time 483556680 ps
CPU time 1.34 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:54 PM PDT 24
Peak memory 206864 kb
Host smart-37691554-ab9e-4a7c-8b5f-287a7e03ad06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14833
18843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1483318843
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3945255205
Short name T725
Test name
Test status
Simulation time 162607128 ps
CPU time 0.74 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206796 kb
Host smart-2193abcb-98f5-4b8d-b2cd-0f914630cfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
55205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3945255205
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2514388327
Short name T830
Test name
Test status
Simulation time 48288710 ps
CPU time 0.68 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:56 PM PDT 24
Peak memory 206888 kb
Host smart-daba5fa1-bca7-4c62-84f1-2799dc0adc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25143
88327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2514388327
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1386045772
Short name T1183
Test name
Test status
Simulation time 786810456 ps
CPU time 1.88 seconds
Started Jul 16 06:55:56 PM PDT 24
Finished Jul 16 06:56:01 PM PDT 24
Peak memory 206792 kb
Host smart-c062907e-e30a-48b4-8ca6-81e356d83ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
45772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1386045772
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3138290864
Short name T1641
Test name
Test status
Simulation time 235635872 ps
CPU time 1.72 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:55:59 PM PDT 24
Peak memory 206944 kb
Host smart-c443f7a1-5a68-4c77-8385-005cf9b0b4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31382
90864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3138290864
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2216466830
Short name T2620
Test name
Test status
Simulation time 273972781 ps
CPU time 0.9 seconds
Started Jul 16 06:55:50 PM PDT 24
Finished Jul 16 06:55:52 PM PDT 24
Peak memory 206852 kb
Host smart-f724272a-7d41-4e6c-a770-ce933f0fc6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22164
66830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2216466830
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3241791594
Short name T2032
Test name
Test status
Simulation time 166935573 ps
CPU time 0.78 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:54 PM PDT 24
Peak memory 206884 kb
Host smart-9bb40ef2-e861-4446-a45c-233c9a963127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32417
91594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3241791594
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1195583554
Short name T339
Test name
Test status
Simulation time 208342411 ps
CPU time 0.84 seconds
Started Jul 16 06:55:56 PM PDT 24
Finished Jul 16 06:55:59 PM PDT 24
Peak memory 206884 kb
Host smart-f4de30ff-a1bc-4b8d-8e97-9f2f200423db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11955
83554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1195583554
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1719080039
Short name T1372
Test name
Test status
Simulation time 7973461026 ps
CPU time 77.72 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:57:13 PM PDT 24
Peak memory 207076 kb
Host smart-b8df57f6-6808-4590-8c84-10e382ee9f36
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1719080039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1719080039
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.801260630
Short name T341
Test name
Test status
Simulation time 5442553839 ps
CPU time 42.57 seconds
Started Jul 16 06:55:50 PM PDT 24
Finished Jul 16 06:56:34 PM PDT 24
Peak memory 206912 kb
Host smart-ede15b9c-77a9-4d64-9ae7-cb7dc822482a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80126
0630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.801260630
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1434059495
Short name T1678
Test name
Test status
Simulation time 232053589 ps
CPU time 0.91 seconds
Started Jul 16 06:55:57 PM PDT 24
Finished Jul 16 06:56:00 PM PDT 24
Peak memory 206844 kb
Host smart-72518bc1-ab54-4186-9a1f-6e10b7fece4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
59495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1434059495
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.2487111993
Short name T1929
Test name
Test status
Simulation time 23340996419 ps
CPU time 21.59 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:56:17 PM PDT 24
Peak memory 206904 kb
Host smart-e64e3f9e-d147-42a8-b354-944c32febde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24871
11993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.2487111993
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2943465937
Short name T502
Test name
Test status
Simulation time 3327395549 ps
CPU time 4 seconds
Started Jul 16 06:55:47 PM PDT 24
Finished Jul 16 06:55:52 PM PDT 24
Peak memory 206924 kb
Host smart-dd942747-d1d0-4234-a35d-fa5d691a9ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
65937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2943465937
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.733204831
Short name T2709
Test name
Test status
Simulation time 10427595114 ps
CPU time 101.56 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:57:38 PM PDT 24
Peak memory 207128 kb
Host smart-510a9d2f-c13a-4c5d-8a5c-4ee53c0082f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73320
4831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.733204831
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.2533692549
Short name T1862
Test name
Test status
Simulation time 4495239685 ps
CPU time 44.32 seconds
Started Jul 16 06:55:48 PM PDT 24
Finished Jul 16 06:56:33 PM PDT 24
Peak memory 207024 kb
Host smart-3ab7af53-df43-4b53-8f5c-7a0b29863bcb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2533692549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.2533692549
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1913563288
Short name T1992
Test name
Test status
Simulation time 241604699 ps
CPU time 0.93 seconds
Started Jul 16 06:55:57 PM PDT 24
Finished Jul 16 06:56:00 PM PDT 24
Peak memory 206752 kb
Host smart-b109636e-369b-459c-96ad-c5f1547dac21
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1913563288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1913563288
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2941869860
Short name T1129
Test name
Test status
Simulation time 202373674 ps
CPU time 1.04 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:54 PM PDT 24
Peak memory 206860 kb
Host smart-1bd3b789-a55b-4900-b96d-f8ea43c380b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
69860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2941869860
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1551716600
Short name T2609
Test name
Test status
Simulation time 5732667668 ps
CPU time 50.41 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:56:46 PM PDT 24
Peak memory 206948 kb
Host smart-422cf20e-57f7-4fa9-8946-47533b849506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15517
16600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1551716600
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.364918555
Short name T4
Test name
Test status
Simulation time 3951972967 ps
CPU time 37.9 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:56:32 PM PDT 24
Peak memory 207080 kb
Host smart-0bacfa74-c165-4dea-96e3-53add2f7b023
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=364918555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.364918555
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.751993707
Short name T2017
Test name
Test status
Simulation time 150686100 ps
CPU time 0.78 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 207004 kb
Host smart-0c4ec24d-472f-4508-8dba-9d059604e09f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=751993707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.751993707
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3753221622
Short name T2446
Test name
Test status
Simulation time 140509571 ps
CPU time 0.79 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206868 kb
Host smart-40f1f89a-0487-41a0-9834-40a1024ac64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37532
21622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3753221622
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.349067000
Short name T2635
Test name
Test status
Simulation time 214322722 ps
CPU time 0.92 seconds
Started Jul 16 06:55:49 PM PDT 24
Finished Jul 16 06:55:51 PM PDT 24
Peak memory 207028 kb
Host smart-5e387291-43b9-4cca-9337-affa539465ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34906
7000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.349067000
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1358586632
Short name T1132
Test name
Test status
Simulation time 189531578 ps
CPU time 0.88 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:56 PM PDT 24
Peak memory 206872 kb
Host smart-e9d68f5b-2733-48ab-95f8-76444867165b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13585
86632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1358586632
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3670247479
Short name T350
Test name
Test status
Simulation time 176980171 ps
CPU time 0.78 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:06 PM PDT 24
Peak memory 206884 kb
Host smart-0f8174a0-d007-4769-983f-274421e6aecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36702
47479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3670247479
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2095903564
Short name T1401
Test name
Test status
Simulation time 146011469 ps
CPU time 0.73 seconds
Started Jul 16 06:55:49 PM PDT 24
Finished Jul 16 06:55:51 PM PDT 24
Peak memory 206816 kb
Host smart-0528d262-1f12-497b-9e6c-846b01dce9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
03564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2095903564
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1552215239
Short name T2379
Test name
Test status
Simulation time 155547675 ps
CPU time 0.82 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 206668 kb
Host smart-52c84a95-743e-4a5c-8805-83ee29ae4082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15522
15239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1552215239
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3313690186
Short name T724
Test name
Test status
Simulation time 242836819 ps
CPU time 0.96 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:54 PM PDT 24
Peak memory 206876 kb
Host smart-f407ccd4-785b-43d5-8723-dba63841b97c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3313690186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3313690186
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.271434905
Short name T2478
Test name
Test status
Simulation time 207812521 ps
CPU time 0.88 seconds
Started Jul 16 06:55:52 PM PDT 24
Finished Jul 16 06:55:55 PM PDT 24
Peak memory 206812 kb
Host smart-69113dd6-1eb6-4c00-a21f-d9220691e689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27143
4905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.271434905
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2392166048
Short name T2126
Test name
Test status
Simulation time 65262844 ps
CPU time 0.68 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 206868 kb
Host smart-46b48994-6c75-4046-8384-a5d7488bb54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23921
66048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2392166048
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2828337529
Short name T929
Test name
Test status
Simulation time 15294368790 ps
CPU time 33.28 seconds
Started Jul 16 06:55:49 PM PDT 24
Finished Jul 16 06:56:24 PM PDT 24
Peak memory 207112 kb
Host smart-375aee74-6c87-448a-8df2-86e4142110a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28283
37529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2828337529
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.244435912
Short name T1496
Test name
Test status
Simulation time 167800920 ps
CPU time 0.86 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:57 PM PDT 24
Peak memory 206888 kb
Host smart-ac76e6df-cbf9-4ddf-b57f-7f768afb1f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24443
5912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.244435912
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2322991991
Short name T659
Test name
Test status
Simulation time 245357313 ps
CPU time 0.91 seconds
Started Jul 16 06:55:55 PM PDT 24
Finished Jul 16 06:55:59 PM PDT 24
Peak memory 206872 kb
Host smart-149194df-f0a1-40c3-bc2d-eec1bdef5e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23229
91991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2322991991
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.2369534349
Short name T311
Test name
Test status
Simulation time 235315312 ps
CPU time 0.88 seconds
Started Jul 16 06:55:53 PM PDT 24
Finished Jul 16 06:55:56 PM PDT 24
Peak memory 206884 kb
Host smart-6b3fff69-130e-4b70-8615-9e462ad5120b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23695
34349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.2369534349
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2355341278
Short name T708
Test name
Test status
Simulation time 182353881 ps
CPU time 0.86 seconds
Started Jul 16 06:55:56 PM PDT 24
Finished Jul 16 06:55:59 PM PDT 24
Peak memory 206868 kb
Host smart-8c84dc8e-980a-43bf-8ca8-09be2e25f869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23553
41278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2355341278
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.719461642
Short name T1408
Test name
Test status
Simulation time 163974283 ps
CPU time 0.86 seconds
Started Jul 16 06:55:50 PM PDT 24
Finished Jul 16 06:55:52 PM PDT 24
Peak memory 206860 kb
Host smart-fddda296-a417-4d3d-ae3d-05ee1daac72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71946
1642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.719461642
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.837755556
Short name T2067
Test name
Test status
Simulation time 168546588 ps
CPU time 0.94 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:53 PM PDT 24
Peak memory 206808 kb
Host smart-70921cf5-3e9a-44d5-8728-07fb9503a5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83775
5556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.837755556
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3662795122
Short name T427
Test name
Test status
Simulation time 164655696 ps
CPU time 0.82 seconds
Started Jul 16 06:55:51 PM PDT 24
Finished Jul 16 06:55:53 PM PDT 24
Peak memory 206776 kb
Host smart-48c2a9cd-9f86-442c-90f2-cbffc096989a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36627
95122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3662795122
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1556710579
Short name T600
Test name
Test status
Simulation time 202327603 ps
CPU time 0.9 seconds
Started Jul 16 06:55:59 PM PDT 24
Finished Jul 16 06:56:02 PM PDT 24
Peak memory 206880 kb
Host smart-885941f4-4b0f-43ff-9e0c-7bb937d4a2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15567
10579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1556710579
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1835353368
Short name T2494
Test name
Test status
Simulation time 5322867399 ps
CPU time 150.73 seconds
Started Jul 16 06:55:56 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 207028 kb
Host smart-8746ea99-59fb-4ed5-955c-977f9b13ba67
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1835353368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1835353368
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2512633356
Short name T1381
Test name
Test status
Simulation time 184261364 ps
CPU time 0.81 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 206868 kb
Host smart-40d7bc1a-f501-4deb-ace0-3a77fdbe9cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25126
33356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2512633356
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.720811659
Short name T1197
Test name
Test status
Simulation time 153549823 ps
CPU time 0.8 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:55:58 PM PDT 24
Peak memory 206620 kb
Host smart-97bb8ca5-2daa-475a-be1c-9d6931e23203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72081
1659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.720811659
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2832115757
Short name T1009
Test name
Test status
Simulation time 452472065 ps
CPU time 1.23 seconds
Started Jul 16 06:55:56 PM PDT 24
Finished Jul 16 06:56:05 PM PDT 24
Peak memory 206820 kb
Host smart-41f43e94-ea27-45c9-9171-63efe20a8864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28321
15757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2832115757
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2464813782
Short name T384
Test name
Test status
Simulation time 5014979406 ps
CPU time 137.62 seconds
Started Jul 16 06:55:54 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 207016 kb
Host smart-ba0396a4-f72d-4b13-bf18-c59d0fd0c770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24648
13782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2464813782
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.685700213
Short name T961
Test name
Test status
Simulation time 65604734 ps
CPU time 0.7 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:27 PM PDT 24
Peak memory 206940 kb
Host smart-2d19b8fe-df93-4795-b20d-099b24e9b454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=685700213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.685700213
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2051749128
Short name T409
Test name
Test status
Simulation time 3586083455 ps
CPU time 4.45 seconds
Started Jul 16 06:48:20 PM PDT 24
Finished Jul 16 06:48:26 PM PDT 24
Peak memory 206860 kb
Host smart-e5337ed0-a7df-4095-8892-bd7ada011b9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2051749128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2051749128
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3431609032
Short name T970
Test name
Test status
Simulation time 13397001476 ps
CPU time 12.11 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:41 PM PDT 24
Peak memory 206860 kb
Host smart-2e68f116-9c08-4d64-877f-efe48a43b39e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3431609032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3431609032
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.222326397
Short name T2408
Test name
Test status
Simulation time 23388745430 ps
CPU time 24.36 seconds
Started Jul 16 06:48:10 PM PDT 24
Finished Jul 16 06:48:35 PM PDT 24
Peak memory 206812 kb
Host smart-21a4573c-65f6-48bb-bb6e-49ff4b1d4dd3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=222326397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.222326397
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.837164498
Short name T323
Test name
Test status
Simulation time 185272048 ps
CPU time 0.91 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:30 PM PDT 24
Peak memory 206856 kb
Host smart-a83385be-c48e-4e6c-a8ac-34ff878f6a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83716
4498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.837164498
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2498087102
Short name T661
Test name
Test status
Simulation time 145965204 ps
CPU time 0.81 seconds
Started Jul 16 06:48:29 PM PDT 24
Finished Jul 16 06:48:33 PM PDT 24
Peak memory 206808 kb
Host smart-7c3d97e0-fd62-4fc4-890f-c084a0a2fa46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980
87102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2498087102
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.2669619606
Short name T105
Test name
Test status
Simulation time 380248955 ps
CPU time 1.18 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:48:33 PM PDT 24
Peak memory 206856 kb
Host smart-283c4ad1-dd80-4c85-977b-c015f9d764f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
19606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.2669619606
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.4189756583
Short name T894
Test name
Test status
Simulation time 575210230 ps
CPU time 1.39 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:27 PM PDT 24
Peak memory 206824 kb
Host smart-93e90f01-2253-4b5a-9cf8-24b934c743f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41897
56583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.4189756583
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.4292379067
Short name T713
Test name
Test status
Simulation time 14110809602 ps
CPU time 31.06 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:57 PM PDT 24
Peak memory 207020 kb
Host smart-a4636376-f9f4-4b25-9054-04db6b470054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
79067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.4292379067
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.2376403024
Short name T1114
Test name
Test status
Simulation time 470125218 ps
CPU time 1.48 seconds
Started Jul 16 06:48:29 PM PDT 24
Finished Jul 16 06:48:33 PM PDT 24
Peak memory 206864 kb
Host smart-473cec73-fe9e-414b-9de4-ff52a0d884dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
03024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.2376403024
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1425741441
Short name T1573
Test name
Test status
Simulation time 227951456 ps
CPU time 0.84 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 206880 kb
Host smart-328b12d8-8eb8-423c-8331-d32cd92f8bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14257
41441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1425741441
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2800246455
Short name T1887
Test name
Test status
Simulation time 32147191 ps
CPU time 0.68 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:48:31 PM PDT 24
Peak memory 206808 kb
Host smart-9c21abdd-383a-4c49-be81-f1a79f14755c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28002
46455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2800246455
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.873065847
Short name T2626
Test name
Test status
Simulation time 810608982 ps
CPU time 2.03 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:30 PM PDT 24
Peak memory 206880 kb
Host smart-3c851473-cee6-46bb-8949-be42d3234310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87306
5847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.873065847
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.332774471
Short name T2547
Test name
Test status
Simulation time 222303033 ps
CPU time 1.3 seconds
Started Jul 16 06:48:29 PM PDT 24
Finished Jul 16 06:48:33 PM PDT 24
Peak memory 206940 kb
Host smart-3be45e45-8c2c-4a12-8c8f-4dc9b91e0616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
4471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.332774471
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3463231608
Short name T1787
Test name
Test status
Simulation time 217716147 ps
CPU time 0.85 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 206852 kb
Host smart-0d63a74e-1c54-4503-aaba-bbf91fb96096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34632
31608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3463231608
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.493134537
Short name T2194
Test name
Test status
Simulation time 174328755 ps
CPU time 0.78 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:27 PM PDT 24
Peak memory 206904 kb
Host smart-73eb4fd8-9125-4e35-91e7-d53e90c90d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49313
4537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.493134537
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3394221675
Short name T1289
Test name
Test status
Simulation time 248625153 ps
CPU time 0.97 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:27 PM PDT 24
Peak memory 206876 kb
Host smart-95be8de5-ce73-40ca-be53-1c19a9410eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942
21675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3394221675
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.1049181145
Short name T72
Test name
Test status
Simulation time 6311371308 ps
CPU time 47.5 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:49:13 PM PDT 24
Peak memory 206932 kb
Host smart-cb206125-db9c-4e56-9c39-c7358d6fee3b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1049181145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.1049181145
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.637651760
Short name T2450
Test name
Test status
Simulation time 5823457888 ps
CPU time 20.55 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:46 PM PDT 24
Peak memory 206944 kb
Host smart-39084efe-86d4-48b0-86b7-98d01ee99441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63765
1760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.637651760
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.288116333
Short name T497
Test name
Test status
Simulation time 205044346 ps
CPU time 0.89 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:27 PM PDT 24
Peak memory 206852 kb
Host smart-d5e96cb7-7326-49ad-8ac8-a0a273e8fc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811
6333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.288116333
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2620018236
Short name T546
Test name
Test status
Simulation time 23280613029 ps
CPU time 23.32 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:49 PM PDT 24
Peak memory 206948 kb
Host smart-319f4036-7a94-4529-89d1-80c6f7981b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26200
18236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2620018236
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2109395303
Short name T882
Test name
Test status
Simulation time 3260507387 ps
CPU time 3.68 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:31 PM PDT 24
Peak memory 206952 kb
Host smart-ed948ded-639b-4181-aac2-b4b0b124af9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21093
95303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2109395303
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.2322302911
Short name T1280
Test name
Test status
Simulation time 15143373593 ps
CPU time 142.49 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:50:48 PM PDT 24
Peak memory 207084 kb
Host smart-0f318ceb-5495-45d6-9c39-0f13b07f3da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23223
02911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.2322302911
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.708668847
Short name T2644
Test name
Test status
Simulation time 4231005517 ps
CPU time 29.31 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:49:00 PM PDT 24
Peak memory 207128 kb
Host smart-6685e102-97e9-47fb-b25a-138712bc3746
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=708668847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.708668847
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.760671506
Short name T2007
Test name
Test status
Simulation time 239384316 ps
CPU time 0.97 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:30 PM PDT 24
Peak memory 206752 kb
Host smart-0d9dbbf7-0bf3-419a-8f41-6e5554cbbe77
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=760671506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.760671506
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.165035190
Short name T2201
Test name
Test status
Simulation time 191082658 ps
CPU time 0.85 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:48:32 PM PDT 24
Peak memory 206828 kb
Host smart-6513d07f-b60b-4733-8a42-761c6f0e7e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16503
5190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.165035190
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3446424568
Short name T2432
Test name
Test status
Simulation time 5912007987 ps
CPU time 177.49 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:51:27 PM PDT 24
Peak memory 207048 kb
Host smart-c26d6bb1-8eb5-41d7-b5ae-811b9d4f3a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34464
24568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3446424568
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.922886769
Short name T1979
Test name
Test status
Simulation time 7893744627 ps
CPU time 231.33 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:52:18 PM PDT 24
Peak memory 207156 kb
Host smart-56535114-8adf-4704-ab70-ff41b858e51e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=922886769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.922886769
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.848326686
Short name T2718
Test name
Test status
Simulation time 169901432 ps
CPU time 0.82 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 207004 kb
Host smart-30f28a99-6ceb-4fe9-a55b-56bbf6c220f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=848326686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.848326686
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2320348701
Short name T2257
Test name
Test status
Simulation time 149198264 ps
CPU time 0.8 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:48:31 PM PDT 24
Peak memory 206864 kb
Host smart-86562a7a-d01a-4cde-b295-c622b6150e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23203
48701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2320348701
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3638605109
Short name T1194
Test name
Test status
Simulation time 212709343 ps
CPU time 0.92 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:48:31 PM PDT 24
Peak memory 206856 kb
Host smart-07ed8cec-93c2-484c-b20f-d10491256481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36386
05109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3638605109
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.250524038
Short name T1676
Test name
Test status
Simulation time 159648393 ps
CPU time 0.8 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 207028 kb
Host smart-899ad5aa-0f02-4596-9005-a41f41fe8a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25052
4038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.250524038
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1736006356
Short name T2020
Test name
Test status
Simulation time 181274734 ps
CPU time 0.85 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 206896 kb
Host smart-e2d75b66-d779-429a-9f76-12f11e9c5875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17360
06356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1736006356
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1782015032
Short name T1121
Test name
Test status
Simulation time 220659402 ps
CPU time 0.81 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 206884 kb
Host smart-4c0fd1ac-6406-46f3-8222-77e091a612a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17820
15032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1782015032
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3309049072
Short name T162
Test name
Test status
Simulation time 197738315 ps
CPU time 0.82 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:26 PM PDT 24
Peak memory 206872 kb
Host smart-f622177c-6adb-4d74-9e7c-76be387d6fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33090
49072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3309049072
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2849602674
Short name T1376
Test name
Test status
Simulation time 242152934 ps
CPU time 0.96 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:48:28 PM PDT 24
Peak memory 206808 kb
Host smart-669a6619-64df-4982-8756-b80020d39d48
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2849602674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2849602674
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2002832397
Short name T2636
Test name
Test status
Simulation time 146969353 ps
CPU time 0.81 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:48:30 PM PDT 24
Peak memory 206860 kb
Host smart-2a41f5d3-69ea-4465-8e77-328130f3581f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028
32397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2002832397
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2757777917
Short name T2087
Test name
Test status
Simulation time 117091019 ps
CPU time 0.72 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:48:32 PM PDT 24
Peak memory 206868 kb
Host smart-79cc6618-1246-4d0f-99bb-df6abebdd425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27577
77917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2757777917
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2653130288
Short name T237
Test name
Test status
Simulation time 10129421519 ps
CPU time 24.89 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:54 PM PDT 24
Peak memory 215364 kb
Host smart-83039fea-7f67-4e7d-95cf-51b7f58360d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26531
30288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2653130288
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.274014460
Short name T1220
Test name
Test status
Simulation time 212260165 ps
CPU time 0.87 seconds
Started Jul 16 06:48:29 PM PDT 24
Finished Jul 16 06:48:33 PM PDT 24
Peak memory 206800 kb
Host smart-b37c4584-9621-4650-87e4-c3d7afc0a56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27401
4460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.274014460
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1195535006
Short name T2527
Test name
Test status
Simulation time 204016806 ps
CPU time 0.84 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:48:31 PM PDT 24
Peak memory 206788 kb
Host smart-2e665a23-9a11-4638-b667-264ad22e8ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11955
35006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1195535006
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2325132469
Short name T2660
Test name
Test status
Simulation time 8108031972 ps
CPU time 42.41 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:49:13 PM PDT 24
Peak memory 207088 kb
Host smart-b5dcc780-2317-480d-b7c8-dab0ab11dd12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2325132469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2325132469
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.897560728
Short name T411
Test name
Test status
Simulation time 12202532180 ps
CPU time 64.63 seconds
Started Jul 16 06:48:25 PM PDT 24
Finished Jul 16 06:49:32 PM PDT 24
Peak memory 207152 kb
Host smart-fb67ddab-384c-4def-bb3c-d0da54c37d95
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=897560728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.897560728
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2862985154
Short name T1679
Test name
Test status
Simulation time 7964947253 ps
CPU time 42.05 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:49:13 PM PDT 24
Peak memory 207096 kb
Host smart-732b35a3-3608-4154-a927-f8e13c409df8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2862985154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2862985154
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2159547234
Short name T1418
Test name
Test status
Simulation time 313573409 ps
CPU time 0.97 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:48:32 PM PDT 24
Peak memory 206856 kb
Host smart-8a5ffd64-5059-4e3d-9e0f-7887e2d9de82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21595
47234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2159547234
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2246310640
Short name T2421
Test name
Test status
Simulation time 182293817 ps
CPU time 0.91 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:48:31 PM PDT 24
Peak memory 206840 kb
Host smart-af698b9d-6af7-4f04-9874-aa5845144ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22463
10640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2246310640
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.170623727
Short name T349
Test name
Test status
Simulation time 162839509 ps
CPU time 0.73 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:48:32 PM PDT 24
Peak memory 206816 kb
Host smart-f06e3deb-342e-44ef-9608-34008224f41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17062
3727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.170623727
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2602297212
Short name T2055
Test name
Test status
Simulation time 172895310 ps
CPU time 0.79 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:30 PM PDT 24
Peak memory 206872 kb
Host smart-81169782-0f2e-41cc-80db-0c4b528ecd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26022
97212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2602297212
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1571131430
Short name T2674
Test name
Test status
Simulation time 163243010 ps
CPU time 0.81 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:48:31 PM PDT 24
Peak memory 206884 kb
Host smart-92e6f8d4-6e01-4697-aab4-e32e34ead8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15711
31430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1571131430
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.506873335
Short name T205
Test name
Test status
Simulation time 251909000 ps
CPU time 0.99 seconds
Started Jul 16 06:48:26 PM PDT 24
Finished Jul 16 06:48:29 PM PDT 24
Peak memory 206880 kb
Host smart-941f42f1-82c9-4659-9b58-4a34c90cf4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50687
3335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.506873335
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.655922505
Short name T1565
Test name
Test status
Simulation time 4854256453 ps
CPU time 130.77 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:50:42 PM PDT 24
Peak memory 207072 kb
Host smart-6c3dc201-3f83-4319-a564-47f1fedb62a3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=655922505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.655922505
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.814827858
Short name T971
Test name
Test status
Simulation time 166105459 ps
CPU time 0.8 seconds
Started Jul 16 06:48:29 PM PDT 24
Finished Jul 16 06:48:32 PM PDT 24
Peak memory 206796 kb
Host smart-9fad2956-d90c-4dfb-bb31-901ddbf3c386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81482
7858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.814827858
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3435648434
Short name T493
Test name
Test status
Simulation time 186180121 ps
CPU time 0.79 seconds
Started Jul 16 06:48:31 PM PDT 24
Finished Jul 16 06:48:33 PM PDT 24
Peak memory 206824 kb
Host smart-8a7e94bc-706a-48aa-ae3c-1c086700bc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34356
48434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3435648434
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2948514872
Short name T2147
Test name
Test status
Simulation time 352159102 ps
CPU time 1.11 seconds
Started Jul 16 06:48:31 PM PDT 24
Finished Jul 16 06:48:34 PM PDT 24
Peak memory 206832 kb
Host smart-cda6b996-87c8-47fc-8327-0f655588c2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29485
14872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2948514872
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1480633666
Short name T169
Test name
Test status
Simulation time 4926761893 ps
CPU time 49.99 seconds
Started Jul 16 06:48:28 PM PDT 24
Finished Jul 16 06:49:21 PM PDT 24
Peak memory 207080 kb
Host smart-20ffc445-c58c-4c3f-b87f-482447e0cc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14806
33666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1480633666
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1005218948
Short name T1257
Test name
Test status
Simulation time 66843022 ps
CPU time 0.75 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:43 PM PDT 24
Peak memory 206788 kb
Host smart-1d3ca5dc-9d29-45e1-a5c0-c0ac251118c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1005218948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1005218948
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3817010489
Short name T1823
Test name
Test status
Simulation time 3791322437 ps
CPU time 4.33 seconds
Started Jul 16 06:48:27 PM PDT 24
Finished Jul 16 06:48:34 PM PDT 24
Peak memory 206892 kb
Host smart-ceb328a2-0b57-46a3-b942-b62177b16410
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3817010489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3817010489
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3360293300
Short name T2313
Test name
Test status
Simulation time 13424211043 ps
CPU time 13.42 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:56 PM PDT 24
Peak memory 206940 kb
Host smart-67ed2067-e48e-47cc-b0ba-b7e4de91d13e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3360293300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3360293300
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1193536062
Short name T1748
Test name
Test status
Simulation time 23332474314 ps
CPU time 24.13 seconds
Started Jul 16 06:48:37 PM PDT 24
Finished Jul 16 06:49:01 PM PDT 24
Peak memory 207092 kb
Host smart-97b28a89-7c70-42f7-93c6-63dc86077cfb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1193536062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.1193536062
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.525605200
Short name T2525
Test name
Test status
Simulation time 192578834 ps
CPU time 0.83 seconds
Started Jul 16 06:48:42 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 206864 kb
Host smart-b93a2fd5-b20d-431d-9dc3-9a3344a3f1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52560
5200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.525605200
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3532728854
Short name T2476
Test name
Test status
Simulation time 156361805 ps
CPU time 0.8 seconds
Started Jul 16 06:48:41 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 206868 kb
Host smart-7819d39d-4d90-4600-98db-7d934c1d2bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
28854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3532728854
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1528182669
Short name T1424
Test name
Test status
Simulation time 156536121 ps
CPU time 0.78 seconds
Started Jul 16 06:48:47 PM PDT 24
Finished Jul 16 06:48:49 PM PDT 24
Peak memory 206860 kb
Host smart-248f0326-9b06-4d7a-bcbf-90f8e2ed9f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15281
82669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1528182669
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.956482640
Short name T2501
Test name
Test status
Simulation time 847247138 ps
CPU time 2.02 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 206940 kb
Host smart-10821558-7d7b-454a-9204-7213d567457b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95648
2640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.956482640
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.802113406
Short name T171
Test name
Test status
Simulation time 16979450832 ps
CPU time 31.57 seconds
Started Jul 16 06:48:41 PM PDT 24
Finished Jul 16 06:49:16 PM PDT 24
Peak memory 207044 kb
Host smart-0afdb78e-cdef-49a0-a55f-91cbcaaa4faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80211
3406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.802113406
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3479816228
Short name T1665
Test name
Test status
Simulation time 353338847 ps
CPU time 1.12 seconds
Started Jul 16 06:48:42 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 206868 kb
Host smart-4d8cd8b7-5728-43ab-9543-703424f0b372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34798
16228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3479816228
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1966555804
Short name T1740
Test name
Test status
Simulation time 204007633 ps
CPU time 0.79 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:48:41 PM PDT 24
Peak memory 206860 kb
Host smart-6a2bd6ea-28e4-4763-aed6-74f05baba6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
55804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1966555804
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.233233794
Short name T2338
Test name
Test status
Simulation time 65462086 ps
CPU time 0.69 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:48:40 PM PDT 24
Peak memory 206880 kb
Host smart-7b37b620-565b-4926-8beb-b55e2782d06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23323
3794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.233233794
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3208299734
Short name T1647
Test name
Test status
Simulation time 885767433 ps
CPU time 2.07 seconds
Started Jul 16 06:48:37 PM PDT 24
Finished Jul 16 06:48:40 PM PDT 24
Peak memory 207108 kb
Host smart-b5131629-e203-4474-852d-eb803330cce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32082
99734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3208299734
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1572509848
Short name T1988
Test name
Test status
Simulation time 166910671 ps
CPU time 1.48 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:48:41 PM PDT 24
Peak memory 207080 kb
Host smart-f5651602-bb0f-470a-93fe-fad3798751d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15725
09848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1572509848
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.586917507
Short name T2356
Test name
Test status
Simulation time 231018233 ps
CPU time 0.85 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:48:41 PM PDT 24
Peak memory 206772 kb
Host smart-ca3e5133-a6a6-4a2a-bf3e-178b28c3bba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58691
7507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.586917507
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.448315968
Short name T381
Test name
Test status
Simulation time 139284901 ps
CPU time 0.78 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:48:41 PM PDT 24
Peak memory 207028 kb
Host smart-4e894228-527b-4786-9206-be8fe95d9443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44831
5968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.448315968
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1513409924
Short name T1053
Test name
Test status
Simulation time 257945041 ps
CPU time 0.93 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:48:40 PM PDT 24
Peak memory 206776 kb
Host smart-929e7160-b465-4456-85e6-063065fb102e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
09924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1513409924
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3520723675
Short name T2118
Test name
Test status
Simulation time 8103034251 ps
CPU time 229.75 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:52:29 PM PDT 24
Peak memory 207064 kb
Host smart-373b9444-fb00-4678-8b20-cf80b7ac9058
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3520723675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3520723675
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.485397723
Short name T422
Test name
Test status
Simulation time 274865696 ps
CPU time 0.92 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:48:40 PM PDT 24
Peak memory 206876 kb
Host smart-e1d8e56b-b7a5-4de7-92da-5665292b7769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48539
7723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.485397723
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1437926156
Short name T2215
Test name
Test status
Simulation time 23304630051 ps
CPU time 23.01 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:49:04 PM PDT 24
Peak memory 206932 kb
Host smart-ac31cdba-edae-4379-b89e-e96bf2805bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14379
26156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1437926156
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.474604892
Short name T2675
Test name
Test status
Simulation time 3318929170 ps
CPU time 3.79 seconds
Started Jul 16 06:48:42 PM PDT 24
Finished Jul 16 06:48:48 PM PDT 24
Peak memory 206920 kb
Host smart-5e16186b-ae33-448e-a9fb-dd5d7e3d063b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47460
4892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.474604892
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2701989218
Short name T543
Test name
Test status
Simulation time 11081572530 ps
CPU time 293.96 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:53:36 PM PDT 24
Peak memory 207088 kb
Host smart-bfd52707-226e-41bf-8827-7e7016dada15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27019
89218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2701989218
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.206911405
Short name T1683
Test name
Test status
Simulation time 4882357981 ps
CPU time 35.43 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:49:15 PM PDT 24
Peak memory 207132 kb
Host smart-d71d62b9-045e-4c5c-a3aa-f935e09d21c8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=206911405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.206911405
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.481080253
Short name T1116
Test name
Test status
Simulation time 251244752 ps
CPU time 0.9 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:48:42 PM PDT 24
Peak memory 206772 kb
Host smart-90365579-1436-4f68-b189-7d7ab8115770
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=481080253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.481080253
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.399340057
Short name T2214
Test name
Test status
Simulation time 190690622 ps
CPU time 0.84 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:44 PM PDT 24
Peak memory 206496 kb
Host smart-3fe3768b-ffd1-4951-81be-6b47ef45646f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39934
0057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.399340057
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2010565745
Short name T142
Test name
Test status
Simulation time 6205533041 ps
CPU time 179.24 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:51:42 PM PDT 24
Peak memory 207068 kb
Host smart-362e08ce-e51d-4d14-8040-5bb3e9db6b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20105
65745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2010565745
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3432341462
Short name T1214
Test name
Test status
Simulation time 5375229146 ps
CPU time 147.95 seconds
Started Jul 16 06:48:48 PM PDT 24
Finished Jul 16 06:51:17 PM PDT 24
Peak memory 207076 kb
Host smart-097f8591-badd-4505-9f78-dae2302c9ac2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3432341462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3432341462
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.163547573
Short name T1851
Test name
Test status
Simulation time 230839170 ps
CPU time 0.97 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:43 PM PDT 24
Peak memory 206728 kb
Host smart-4137eadc-6e26-468d-84d9-c32179dadbcd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=163547573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.163547573
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1843765486
Short name T2212
Test name
Test status
Simulation time 172581449 ps
CPU time 0.79 seconds
Started Jul 16 06:48:41 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 206868 kb
Host smart-621c9acf-87de-4156-a5b2-0685c56c0693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18437
65486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1843765486
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2789651749
Short name T2523
Test name
Test status
Simulation time 218514739 ps
CPU time 0.88 seconds
Started Jul 16 06:48:45 PM PDT 24
Finished Jul 16 06:48:47 PM PDT 24
Peak memory 206812 kb
Host smart-5ee83cc8-68cd-4829-b763-7d7b5aa3900d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27896
51749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2789651749
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3898846658
Short name T2299
Test name
Test status
Simulation time 146995688 ps
CPU time 0.76 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:43 PM PDT 24
Peak memory 206884 kb
Host smart-29f45646-b13e-42fd-b6c6-a9be8581e573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38988
46658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3898846658
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.850433716
Short name T1400
Test name
Test status
Simulation time 142251778 ps
CPU time 0.79 seconds
Started Jul 16 06:48:47 PM PDT 24
Finished Jul 16 06:48:49 PM PDT 24
Peak memory 206864 kb
Host smart-2a3af093-5924-4613-92d6-647d357fdd6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85043
3716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.850433716
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3780905413
Short name T302
Test name
Test status
Simulation time 160055839 ps
CPU time 0.74 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:48:41 PM PDT 24
Peak memory 206868 kb
Host smart-54138a86-dba4-4053-b8bd-bd1f1597a86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
05413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3780905413
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3224338554
Short name T2005
Test name
Test status
Simulation time 188627615 ps
CPU time 0.86 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:44 PM PDT 24
Peak memory 206752 kb
Host smart-e0e506c1-853e-4c7c-9e8a-70bfcf3208d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32243
38554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3224338554
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.447730476
Short name T647
Test name
Test status
Simulation time 219109361 ps
CPU time 0.92 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:48:39 PM PDT 24
Peak memory 206792 kb
Host smart-a7ae52d6-d052-4b51-b365-3d025c34cdcd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=447730476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.447730476
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3134954114
Short name T2672
Test name
Test status
Simulation time 137829211 ps
CPU time 0.73 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:43 PM PDT 24
Peak memory 206872 kb
Host smart-9a042e84-e8e7-4093-9c7a-668f892947e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31349
54114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3134954114
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3625667112
Short name T35
Test name
Test status
Simulation time 120833083 ps
CPU time 0.7 seconds
Started Jul 16 06:48:41 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 206800 kb
Host smart-1ceafb01-3cf8-4fd6-8b22-0e27263ac37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36256
67112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3625667112
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.4069907755
Short name T796
Test name
Test status
Simulation time 20338532317 ps
CPU time 43.54 seconds
Started Jul 16 06:48:47 PM PDT 24
Finished Jul 16 06:49:32 PM PDT 24
Peak memory 207164 kb
Host smart-6cbb3ae5-d3a9-4324-b6f4-f01c6ee105bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40699
07755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.4069907755
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1101952084
Short name T1022
Test name
Test status
Simulation time 177848503 ps
CPU time 0.85 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:48:39 PM PDT 24
Peak memory 206876 kb
Host smart-7b46e8c8-a868-44fe-9dd7-2b648ad61594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11019
52084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1101952084
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2836141221
Short name T1619
Test name
Test status
Simulation time 227802646 ps
CPU time 0.88 seconds
Started Jul 16 06:48:43 PM PDT 24
Finished Jul 16 06:48:46 PM PDT 24
Peak memory 206744 kb
Host smart-5c9662cd-c12c-4cfc-bf24-8afc1936dcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
41221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2836141221
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3176167114
Short name T812
Test name
Test status
Simulation time 11194913809 ps
CPU time 72.34 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:49:55 PM PDT 24
Peak memory 206840 kb
Host smart-8c32e823-5e4b-49ec-8bd6-efd058db963f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3176167114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3176167114
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2387571907
Short name T157
Test name
Test status
Simulation time 10034562635 ps
CPU time 101.63 seconds
Started Jul 16 06:48:42 PM PDT 24
Finished Jul 16 06:50:27 PM PDT 24
Peak memory 206956 kb
Host smart-43ca2fbf-4c7f-4421-bf40-805db6d9d3b0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2387571907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2387571907
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3285700014
Short name T1208
Test name
Test status
Simulation time 15534728333 ps
CPU time 327.05 seconds
Started Jul 16 06:48:42 PM PDT 24
Finished Jul 16 06:54:12 PM PDT 24
Peak memory 207008 kb
Host smart-3c2fd050-20a1-4fa4-a48e-1bb22c75728e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3285700014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3285700014
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1475179999
Short name T1703
Test name
Test status
Simulation time 207209464 ps
CPU time 0.87 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:48:39 PM PDT 24
Peak memory 206888 kb
Host smart-8c922f4f-928d-45d8-8612-2459349cb732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14751
79999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1475179999
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.646806359
Short name T498
Test name
Test status
Simulation time 179808651 ps
CPU time 0.82 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:44 PM PDT 24
Peak memory 206756 kb
Host smart-1079cc75-1a72-4111-96c6-f331aed6c729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64680
6359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.646806359
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1789813945
Short name T732
Test name
Test status
Simulation time 185015231 ps
CPU time 0.76 seconds
Started Jul 16 06:48:45 PM PDT 24
Finished Jul 16 06:48:47 PM PDT 24
Peak memory 206788 kb
Host smart-5e07e16f-edcf-488c-83d0-cc3c2b6d86ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17898
13945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1789813945
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2760220794
Short name T913
Test name
Test status
Simulation time 159298311 ps
CPU time 0.76 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:48:42 PM PDT 24
Peak memory 206856 kb
Host smart-96cac559-c01a-4858-8cb5-b44d17088097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602
20794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2760220794
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3017923122
Short name T1625
Test name
Test status
Simulation time 180000282 ps
CPU time 0.8 seconds
Started Jul 16 06:48:46 PM PDT 24
Finished Jul 16 06:48:47 PM PDT 24
Peak memory 206860 kb
Host smart-fd839deb-9912-480c-99af-2034b89bfdf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30179
23122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3017923122
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.332739644
Short name T1937
Test name
Test status
Simulation time 238663926 ps
CPU time 0.94 seconds
Started Jul 16 06:48:41 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 206876 kb
Host smart-6b1cd910-5fbf-4a58-9af3-10e71038cfd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33273
9644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.332739644
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2477000819
Short name T1375
Test name
Test status
Simulation time 4254856487 ps
CPU time 31.31 seconds
Started Jul 16 06:48:41 PM PDT 24
Finished Jul 16 06:49:15 PM PDT 24
Peak memory 207080 kb
Host smart-f85279f8-28c8-4976-aa73-5ffb9bfc418c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2477000819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2477000819
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2615853786
Short name T1832
Test name
Test status
Simulation time 191978669 ps
CPU time 0.82 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:44 PM PDT 24
Peak memory 206892 kb
Host smart-da8bc282-2990-46b1-ab03-ad6d4138d1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26158
53786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2615853786
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.988820235
Short name T709
Test name
Test status
Simulation time 165980668 ps
CPU time 0.8 seconds
Started Jul 16 06:48:48 PM PDT 24
Finished Jul 16 06:48:50 PM PDT 24
Peak memory 206864 kb
Host smart-9ea0f4b6-2780-4df4-bc1a-cb2c7758337b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98882
0235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.988820235
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1672577417
Short name T1586
Test name
Test status
Simulation time 867199604 ps
CPU time 1.9 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:44 PM PDT 24
Peak memory 207056 kb
Host smart-3c7e3d24-151f-4d14-8d19-dc1658c16b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16725
77417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1672577417
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3298865203
Short name T1869
Test name
Test status
Simulation time 3501930669 ps
CPU time 33.66 seconds
Started Jul 16 06:48:45 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 206780 kb
Host smart-36715578-09a1-432b-a361-372cc5fcf107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32988
65203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3298865203
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2710989340
Short name T1977
Test name
Test status
Simulation time 55508694 ps
CPU time 0.67 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:07 PM PDT 24
Peak memory 206912 kb
Host smart-266021f8-c2ee-4e74-b167-7fb15afa8d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2710989340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2710989340
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3270742127
Short name T1334
Test name
Test status
Simulation time 3651282201 ps
CPU time 4.37 seconds
Started Jul 16 06:48:41 PM PDT 24
Finished Jul 16 06:48:48 PM PDT 24
Peak memory 206920 kb
Host smart-91ce633e-efda-422a-9f2d-37647c4c78d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3270742127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.3270742127
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3598886170
Short name T1705
Test name
Test status
Simulation time 13340448785 ps
CPU time 14.11 seconds
Started Jul 16 06:48:45 PM PDT 24
Finished Jul 16 06:49:00 PM PDT 24
Peak memory 206584 kb
Host smart-77d3b8f7-3489-417c-b6ed-4b522ba12ffd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3598886170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3598886170
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3511519275
Short name T1228
Test name
Test status
Simulation time 23357804638 ps
CPU time 28.73 seconds
Started Jul 16 06:48:39 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206932 kb
Host smart-1e841c92-d454-4074-a786-05baca050b77
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3511519275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.3511519275
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2474337882
Short name T2669
Test name
Test status
Simulation time 183787319 ps
CPU time 0.81 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:43 PM PDT 24
Peak memory 206832 kb
Host smart-cde99216-660f-4821-91af-58e18f9b4a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24743
37882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2474337882
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2258081255
Short name T1769
Test name
Test status
Simulation time 135713629 ps
CPU time 0.76 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:43 PM PDT 24
Peak memory 206860 kb
Host smart-ef67f8f7-6401-4fd0-8ff6-0cf0a81b6a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22580
81255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2258081255
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3824766101
Short name T1062
Test name
Test status
Simulation time 490996983 ps
CPU time 1.48 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:45 PM PDT 24
Peak memory 206916 kb
Host smart-7a419e79-55e1-4593-8904-aa86c401e4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
66101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3824766101
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2973452204
Short name T838
Test name
Test status
Simulation time 1585805986 ps
CPU time 3.09 seconds
Started Jul 16 06:48:40 PM PDT 24
Finished Jul 16 06:48:46 PM PDT 24
Peak memory 206900 kb
Host smart-10362020-40c7-4d5f-b4a6-3b588cbb63fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29734
52204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2973452204
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1675383667
Short name T89
Test name
Test status
Simulation time 20259828075 ps
CPU time 40.29 seconds
Started Jul 16 06:48:38 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 207128 kb
Host smart-1c2ecfdc-9146-450d-b5bd-3d8db7d66d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16753
83667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1675383667
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2358615395
Short name T952
Test name
Test status
Simulation time 451107963 ps
CPU time 1.39 seconds
Started Jul 16 06:48:53 PM PDT 24
Finished Jul 16 06:48:56 PM PDT 24
Peak memory 206884 kb
Host smart-03908cab-a71e-4eff-bf56-42fb6180035e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23586
15395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2358615395
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.4144700151
Short name T1932
Test name
Test status
Simulation time 142409259 ps
CPU time 0.84 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:48:53 PM PDT 24
Peak memory 206800 kb
Host smart-d2a14d66-96f2-4228-9366-a2a1f8087ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41447
00151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.4144700151
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2494623248
Short name T2358
Test name
Test status
Simulation time 26224878 ps
CPU time 0.64 seconds
Started Jul 16 06:48:50 PM PDT 24
Finished Jul 16 06:48:51 PM PDT 24
Peak memory 206848 kb
Host smart-59032d6b-b180-4fe5-8d71-2f42815762c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946
23248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2494623248
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2588790880
Short name T206
Test name
Test status
Simulation time 708943608 ps
CPU time 1.94 seconds
Started Jul 16 06:48:54 PM PDT 24
Finished Jul 16 06:48:57 PM PDT 24
Peak memory 207032 kb
Host smart-9d53a628-6ae6-4310-ab74-5e660fa7ce7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25887
90880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2588790880
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1027839876
Short name T1249
Test name
Test status
Simulation time 270891632 ps
CPU time 1.83 seconds
Started Jul 16 06:48:48 PM PDT 24
Finished Jul 16 06:48:51 PM PDT 24
Peak memory 207048 kb
Host smart-33d53285-6f91-4903-a60e-abe1490f7a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10278
39876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1027839876
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.99741131
Short name T771
Test name
Test status
Simulation time 195953165 ps
CPU time 0.84 seconds
Started Jul 16 06:48:54 PM PDT 24
Finished Jul 16 06:48:56 PM PDT 24
Peak memory 206860 kb
Host smart-e76664d5-16ab-4040-b657-29a0b0401a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99741
131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.99741131
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.917129473
Short name T403
Test name
Test status
Simulation time 175832392 ps
CPU time 0.76 seconds
Started Jul 16 06:48:57 PM PDT 24
Finished Jul 16 06:48:58 PM PDT 24
Peak memory 206784 kb
Host smart-4154046a-cfb7-46bb-be36-237d9b461a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91712
9473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.917129473
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.222449409
Short name T1173
Test name
Test status
Simulation time 154706533 ps
CPU time 0.87 seconds
Started Jul 16 06:48:58 PM PDT 24
Finished Jul 16 06:49:00 PM PDT 24
Peak memory 206880 kb
Host smart-14fcbf98-d456-4235-94f8-b695a21699d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22244
9409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.222449409
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.1438800937
Short name T84
Test name
Test status
Simulation time 6785285030 ps
CPU time 56.41 seconds
Started Jul 16 06:48:53 PM PDT 24
Finished Jul 16 06:49:51 PM PDT 24
Peak memory 207116 kb
Host smart-120a9261-2485-49d9-b898-01a01ecc46bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14388
00937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.1438800937
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.96406956
Short name T1240
Test name
Test status
Simulation time 225932137 ps
CPU time 0.9 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:48:55 PM PDT 24
Peak memory 206732 kb
Host smart-dfb2145a-6821-492e-abb4-2d5af274bf38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96406
956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.96406956
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2607362390
Short name T360
Test name
Test status
Simulation time 23302612058 ps
CPU time 23.55 seconds
Started Jul 16 06:48:56 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 206780 kb
Host smart-3b7d8983-ede3-408c-b099-5c6af9cda84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
62390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2607362390
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1730875492
Short name T1609
Test name
Test status
Simulation time 3335819582 ps
CPU time 4.17 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:48:58 PM PDT 24
Peak memory 206836 kb
Host smart-182151a3-a111-41b7-a8fc-0dc190cd0d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17308
75492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1730875492
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.362209153
Short name T1117
Test name
Test status
Simulation time 10146283642 ps
CPU time 292.86 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:53:45 PM PDT 24
Peak memory 207188 kb
Host smart-c1789c39-64c6-489a-a58f-d70bb55412d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36220
9153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.362209153
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2271359835
Short name T413
Test name
Test status
Simulation time 4889099289 ps
CPU time 33.15 seconds
Started Jul 16 06:48:54 PM PDT 24
Finished Jul 16 06:49:29 PM PDT 24
Peak memory 206956 kb
Host smart-417f94c6-04e5-4a62-8b80-788c1dd84754
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2271359835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2271359835
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.1035902717
Short name T1872
Test name
Test status
Simulation time 253202436 ps
CPU time 0.92 seconds
Started Jul 16 06:48:57 PM PDT 24
Finished Jul 16 06:48:59 PM PDT 24
Peak memory 206808 kb
Host smart-45279bfb-9b58-46c3-a847-a2c3e2d82597
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1035902717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.1035902717
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2117860155
Short name T2500
Test name
Test status
Simulation time 188468399 ps
CPU time 0.88 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:48:54 PM PDT 24
Peak memory 206888 kb
Host smart-2732be3a-69c2-4a81-b274-1ece264c63b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21178
60155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2117860155
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3661118611
Short name T2011
Test name
Test status
Simulation time 3698059338 ps
CPU time 29.14 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 207000 kb
Host smart-abe67bc5-6bc6-48fa-bfb5-7109852254ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36611
18611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3661118611
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.176135870
Short name T379
Test name
Test status
Simulation time 4628826637 ps
CPU time 47.7 seconds
Started Jul 16 06:48:53 PM PDT 24
Finished Jul 16 06:49:42 PM PDT 24
Peak memory 207020 kb
Host smart-e029c5ab-ca6e-4257-836c-87948f0feb66
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=176135870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.176135870
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3530798221
Short name T1278
Test name
Test status
Simulation time 153982014 ps
CPU time 0.78 seconds
Started Jul 16 06:49:01 PM PDT 24
Finished Jul 16 06:49:03 PM PDT 24
Peak memory 206884 kb
Host smart-63c549ef-a7c7-4cd3-819c-1029e1f50675
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3530798221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3530798221
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3665358187
Short name T986
Test name
Test status
Simulation time 220544122 ps
CPU time 0.87 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:48:54 PM PDT 24
Peak memory 206892 kb
Host smart-f8eb9e80-ef3a-406e-b458-0a51e56370dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36653
58187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3665358187
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.38910648
Short name T137
Test name
Test status
Simulation time 193607504 ps
CPU time 0.9 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:48:55 PM PDT 24
Peak memory 206772 kb
Host smart-f691832f-b37d-4663-b985-72a630db7883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38910
648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.38910648
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3947087071
Short name T1248
Test name
Test status
Simulation time 167120254 ps
CPU time 0.77 seconds
Started Jul 16 06:48:49 PM PDT 24
Finished Jul 16 06:48:50 PM PDT 24
Peak memory 206880 kb
Host smart-0a5c0fef-87e6-46c1-a287-ca71c324fcb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39470
87071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3947087071
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1935961651
Short name T1985
Test name
Test status
Simulation time 173739480 ps
CPU time 0.81 seconds
Started Jul 16 06:48:58 PM PDT 24
Finished Jul 16 06:49:00 PM PDT 24
Peak memory 206888 kb
Host smart-54eff97b-59ed-408e-b35a-cefb886bcb60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19359
61651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1935961651
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3637555860
Short name T965
Test name
Test status
Simulation time 165065312 ps
CPU time 0.74 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:48:54 PM PDT 24
Peak memory 206812 kb
Host smart-84a90c0b-dfc2-402d-8adb-332a85e86eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36375
55860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3637555860
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1057723685
Short name T2618
Test name
Test status
Simulation time 212629676 ps
CPU time 0.84 seconds
Started Jul 16 06:48:58 PM PDT 24
Finished Jul 16 06:49:00 PM PDT 24
Peak memory 206888 kb
Host smart-e9bbc90f-4781-4abc-ac65-6586962162a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10577
23685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1057723685
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2852623221
Short name T325
Test name
Test status
Simulation time 218166977 ps
CPU time 0.95 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:48:53 PM PDT 24
Peak memory 206876 kb
Host smart-13262143-0a5b-46e1-9f54-538fbf9a024d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2852623221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2852623221
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1290418336
Short name T2034
Test name
Test status
Simulation time 134964128 ps
CPU time 0.76 seconds
Started Jul 16 06:48:58 PM PDT 24
Finished Jul 16 06:48:59 PM PDT 24
Peak memory 206884 kb
Host smart-f5475ea6-e359-41bc-aa4e-28851911b4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12904
18336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1290418336
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1574231296
Short name T1687
Test name
Test status
Simulation time 40070130 ps
CPU time 0.7 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:48:53 PM PDT 24
Peak memory 206632 kb
Host smart-665f8e56-019b-4427-a85c-dd66afca43a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15742
31296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1574231296
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3530692266
Short name T262
Test name
Test status
Simulation time 6961068486 ps
CPU time 18.1 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206940 kb
Host smart-c9f094d8-f5b1-41bf-9fd7-adca845672d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35306
92266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3530692266
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2589717322
Short name T1182
Test name
Test status
Simulation time 181501432 ps
CPU time 0.81 seconds
Started Jul 16 06:48:57 PM PDT 24
Finished Jul 16 06:48:58 PM PDT 24
Peak memory 206792 kb
Host smart-157e2594-8a9d-467d-9f69-f3d3b7af0394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
17322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2589717322
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3065886328
Short name T1041
Test name
Test status
Simulation time 186946577 ps
CPU time 0.93 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:48:55 PM PDT 24
Peak memory 206884 kb
Host smart-a1a5d7bb-bfc7-4dfa-afe3-9a3b01cf726a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30658
86328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3065886328
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1304246723
Short name T352
Test name
Test status
Simulation time 4839848172 ps
CPU time 126.57 seconds
Started Jul 16 06:48:57 PM PDT 24
Finished Jul 16 06:51:04 PM PDT 24
Peak memory 207072 kb
Host smart-3b4e686e-c527-45bc-ba83-c3c4bb50889e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1304246723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1304246723
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.429360423
Short name T1431
Test name
Test status
Simulation time 11205185906 ps
CPU time 217.35 seconds
Started Jul 16 06:48:55 PM PDT 24
Finished Jul 16 06:52:33 PM PDT 24
Peak memory 206996 kb
Host smart-a38d2a14-869c-425f-a0e7-64972a0d12df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=429360423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.429360423
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.566328434
Short name T1814
Test name
Test status
Simulation time 242135275 ps
CPU time 0.92 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:48:54 PM PDT 24
Peak memory 206888 kb
Host smart-be62fcaa-6918-408d-879d-56fc74782090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56632
8434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.566328434
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1802211744
Short name T2049
Test name
Test status
Simulation time 180463524 ps
CPU time 0.77 seconds
Started Jul 16 06:48:50 PM PDT 24
Finished Jul 16 06:48:51 PM PDT 24
Peak memory 206868 kb
Host smart-2c8cc389-b34d-4d9a-8df3-21d595dfd356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18022
11744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1802211744
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2339801162
Short name T962
Test name
Test status
Simulation time 147341257 ps
CPU time 0.78 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:48:55 PM PDT 24
Peak memory 206860 kb
Host smart-a5d30c3e-e3ad-4269-a4c9-09929eec6de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23398
01162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2339801162
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2459349632
Short name T2384
Test name
Test status
Simulation time 149507916 ps
CPU time 0.83 seconds
Started Jul 16 06:48:55 PM PDT 24
Finished Jul 16 06:48:57 PM PDT 24
Peak memory 206712 kb
Host smart-1aa8ad87-97c4-4020-ad28-3c1bf774d031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24593
49632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2459349632
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3087087050
Short name T864
Test name
Test status
Simulation time 150693412 ps
CPU time 0.88 seconds
Started Jul 16 06:48:56 PM PDT 24
Finished Jul 16 06:48:57 PM PDT 24
Peak memory 206736 kb
Host smart-e6428f22-68f4-4a83-8723-6f0f42a9dfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30870
87050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3087087050
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2336780434
Short name T816
Test name
Test status
Simulation time 304694909 ps
CPU time 1.03 seconds
Started Jul 16 06:48:54 PM PDT 24
Finished Jul 16 06:48:56 PM PDT 24
Peak memory 206752 kb
Host smart-e48e2bc1-da93-4f3e-8286-71e009c29f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23367
80434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2336780434
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.175178485
Short name T1273
Test name
Test status
Simulation time 4541092856 ps
CPU time 30.7 seconds
Started Jul 16 06:48:52 PM PDT 24
Finished Jul 16 06:49:24 PM PDT 24
Peak memory 207100 kb
Host smart-3f5a1ed8-2e9d-47af-9b55-6298587d6d23
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=175178485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.175178485
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.407372998
Short name T383
Test name
Test status
Simulation time 180091389 ps
CPU time 0.8 seconds
Started Jul 16 06:48:51 PM PDT 24
Finished Jul 16 06:48:53 PM PDT 24
Peak memory 206848 kb
Host smart-94ea77df-1676-47d3-b0f8-7cefff783f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40737
2998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.407372998
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3747020748
Short name T423
Test name
Test status
Simulation time 163862091 ps
CPU time 0.79 seconds
Started Jul 16 06:48:53 PM PDT 24
Finished Jul 16 06:48:56 PM PDT 24
Peak memory 206748 kb
Host smart-d61f1847-4f84-4035-9a38-d0ba1d3107b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37470
20748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3747020748
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3325955356
Short name T790
Test name
Test status
Simulation time 195604172 ps
CPU time 0.89 seconds
Started Jul 16 06:48:50 PM PDT 24
Finished Jul 16 06:48:52 PM PDT 24
Peak memory 206868 kb
Host smart-8801ed0b-13f1-4b2a-b1fc-3d3566e49694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33259
55356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3325955356
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3756194618
Short name T528
Test name
Test status
Simulation time 4459274776 ps
CPU time 30.17 seconds
Started Jul 16 06:48:58 PM PDT 24
Finished Jul 16 06:49:29 PM PDT 24
Peak memory 207088 kb
Host smart-40c3181a-1b15-4895-9a27-6c4cc6061c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37561
94618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3756194618
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1422568781
Short name T2144
Test name
Test status
Simulation time 50325921 ps
CPU time 0.66 seconds
Started Jul 16 06:49:21 PM PDT 24
Finished Jul 16 06:49:25 PM PDT 24
Peak memory 206892 kb
Host smart-9a1b8f6e-3e20-4bc3-bf4f-5a3be2aad3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1422568781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1422568781
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.818010960
Short name T2079
Test name
Test status
Simulation time 3797820169 ps
CPU time 4.47 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:14 PM PDT 24
Peak memory 207072 kb
Host smart-aae13f9c-7d08-4fda-b5c1-f4ee890d0e2c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=818010960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.818010960
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1852834798
Short name T1843
Test name
Test status
Simulation time 13338190940 ps
CPU time 16.62 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:26 PM PDT 24
Peak memory 206900 kb
Host smart-25462365-596d-47d1-a9e1-e1b78df335d0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1852834798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1852834798
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2407240216
Short name T1710
Test name
Test status
Simulation time 23326381728 ps
CPU time 22.59 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:32 PM PDT 24
Peak memory 206856 kb
Host smart-0d2e0adb-c5c7-4f97-88bf-797d38b6b732
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2407240216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2407240216
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3002613095
Short name T506
Test name
Test status
Simulation time 182286906 ps
CPU time 0.83 seconds
Started Jul 16 06:49:11 PM PDT 24
Finished Jul 16 06:49:13 PM PDT 24
Peak memory 206888 kb
Host smart-860f1019-f7e2-44b4-ad8b-1cf97388edc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30026
13095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3002613095
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2059564939
Short name T58
Test name
Test status
Simulation time 174057199 ps
CPU time 0.78 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:08 PM PDT 24
Peak memory 206752 kb
Host smart-3d9c857b-5830-42ed-ab74-b2e030e60186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20595
64939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2059564939
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.1789732062
Short name T967
Test name
Test status
Simulation time 255238266 ps
CPU time 0.99 seconds
Started Jul 16 06:49:08 PM PDT 24
Finished Jul 16 06:49:11 PM PDT 24
Peak memory 206832 kb
Host smart-ec108911-b786-49ff-8fd1-1df50708f00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17897
32062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.1789732062
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3334439843
Short name T886
Test name
Test status
Simulation time 543428895 ps
CPU time 1.35 seconds
Started Jul 16 06:49:11 PM PDT 24
Finished Jul 16 06:49:13 PM PDT 24
Peak memory 206880 kb
Host smart-7957c1e2-9733-4be6-ac68-74ddef3d0576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
39843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3334439843
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.764045254
Short name T2179
Test name
Test status
Simulation time 13054068378 ps
CPU time 21.37 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:30 PM PDT 24
Peak memory 206996 kb
Host smart-b7a45194-fafe-465c-9711-349bca9fb954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76404
5254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.764045254
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1598339627
Short name T2485
Test name
Test status
Simulation time 416804755 ps
CPU time 1.21 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206860 kb
Host smart-92a8a1f7-3a48-4d48-831f-5026cb7c32bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15983
39627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1598339627
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2192195516
Short name T1964
Test name
Test status
Simulation time 162181994 ps
CPU time 0.8 seconds
Started Jul 16 06:49:05 PM PDT 24
Finished Jul 16 06:49:07 PM PDT 24
Peak memory 206820 kb
Host smart-fceb066e-c4d1-45df-a435-988770e0e701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21921
95516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2192195516
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3046052512
Short name T818
Test name
Test status
Simulation time 69565331 ps
CPU time 0.67 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206864 kb
Host smart-ad4bb132-f22a-45a5-bde8-8aa7afd0e411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30460
52512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3046052512
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1498773729
Short name T2458
Test name
Test status
Simulation time 891157964 ps
CPU time 2.19 seconds
Started Jul 16 06:49:05 PM PDT 24
Finished Jul 16 06:49:08 PM PDT 24
Peak memory 207108 kb
Host smart-633afd4e-4712-4b7a-9942-c81b0adaa8cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14987
73729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1498773729
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.510158938
Short name T1445
Test name
Test status
Simulation time 217282361 ps
CPU time 2.03 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 207020 kb
Host smart-ad3bab10-85ad-4514-b266-404ce6ac1030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51015
8938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.510158938
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2917153481
Short name T479
Test name
Test status
Simulation time 242811135 ps
CPU time 0.87 seconds
Started Jul 16 06:49:09 PM PDT 24
Finished Jul 16 06:49:12 PM PDT 24
Peak memory 206848 kb
Host smart-a63c5ff8-851e-42bd-a5cc-01af55f7354d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29171
53481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2917153481
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2044869325
Short name T2183
Test name
Test status
Simulation time 152107196 ps
CPU time 0.75 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:08 PM PDT 24
Peak memory 207024 kb
Host smart-1bb9bdd9-83bb-4db1-9f5e-14b2189a4e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
69325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2044869325
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1714224617
Short name T1918
Test name
Test status
Simulation time 231599378 ps
CPU time 0.9 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:09 PM PDT 24
Peak memory 206888 kb
Host smart-963f96ea-b3a5-4438-a139-29f2f547bf5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
24617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1714224617
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.1772827419
Short name T764
Test name
Test status
Simulation time 7604155368 ps
CPU time 28.01 seconds
Started Jul 16 06:49:09 PM PDT 24
Finished Jul 16 06:49:39 PM PDT 24
Peak memory 207116 kb
Host smart-62921d8a-89bf-4569-91e2-8b7de7154e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17728
27419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.1772827419
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3481405010
Short name T2235
Test name
Test status
Simulation time 238582074 ps
CPU time 0.97 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206872 kb
Host smart-bb6fe8ea-afdd-4f02-9921-84811a990014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34814
05010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3481405010
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.192143828
Short name T599
Test name
Test status
Simulation time 23303841823 ps
CPU time 20.62 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:29 PM PDT 24
Peak memory 206948 kb
Host smart-9f68bc19-b41a-488b-8684-7525431f5e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19214
3828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.192143828
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2507190726
Short name T2306
Test name
Test status
Simulation time 3335170705 ps
CPU time 3.95 seconds
Started Jul 16 06:49:05 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206916 kb
Host smart-0cbd4dff-6b5c-429e-9431-c4de71b668ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25071
90726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2507190726
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2423068190
Short name T2702
Test name
Test status
Simulation time 9612626206 ps
CPU time 70.62 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:50:20 PM PDT 24
Peak memory 207192 kb
Host smart-6b80bae5-2a33-4482-9318-f3d821745da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24230
68190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2423068190
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.1039470833
Short name T2303
Test name
Test status
Simulation time 4207632586 ps
CPU time 118.77 seconds
Started Jul 16 06:49:09 PM PDT 24
Finished Jul 16 06:51:10 PM PDT 24
Peak memory 207112 kb
Host smart-970c61c2-392d-4248-a9e0-8d7e2735fdd5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1039470833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.1039470833
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.796013552
Short name T1151
Test name
Test status
Simulation time 271458155 ps
CPU time 1.02 seconds
Started Jul 16 06:49:10 PM PDT 24
Finished Jul 16 06:49:12 PM PDT 24
Peak memory 206868 kb
Host smart-e278d891-309e-478b-9cb3-3db5d17d7742
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=796013552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.796013552
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.22258511
Short name T1672
Test name
Test status
Simulation time 214970869 ps
CPU time 0.95 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206772 kb
Host smart-292cb0dc-edff-41af-a2e8-85d801aa075e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22258
511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.22258511
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1591450567
Short name T1847
Test name
Test status
Simulation time 5640444138 ps
CPU time 52.85 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:50:01 PM PDT 24
Peak memory 206912 kb
Host smart-a2af4280-5f1f-478b-93b1-a36987203263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914
50567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1591450567
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3312690240
Short name T993
Test name
Test status
Simulation time 7212315767 ps
CPU time 68.49 seconds
Started Jul 16 06:49:08 PM PDT 24
Finished Jul 16 06:50:19 PM PDT 24
Peak memory 207128 kb
Host smart-fb8f87a5-0d74-4621-a5c2-17921aa61eaf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3312690240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3312690240
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1392524171
Short name T1539
Test name
Test status
Simulation time 222283549 ps
CPU time 0.86 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206856 kb
Host smart-32371805-613c-48c6-9f4f-eba34679bdba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1392524171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1392524171
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1120049645
Short name T2491
Test name
Test status
Simulation time 201470209 ps
CPU time 0.82 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:09 PM PDT 24
Peak memory 207032 kb
Host smart-d53e45c5-f34f-4a0e-a966-f93ae72b7dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11200
49645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1120049645
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1710961077
Short name T126
Test name
Test status
Simulation time 184582153 ps
CPU time 0.79 seconds
Started Jul 16 06:49:09 PM PDT 24
Finished Jul 16 06:49:12 PM PDT 24
Peak memory 206880 kb
Host smart-692eabff-6022-41a2-baae-78e583264fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17109
61077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1710961077
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.59414507
Short name T2623
Test name
Test status
Simulation time 149863442 ps
CPU time 0.78 seconds
Started Jul 16 06:49:08 PM PDT 24
Finished Jul 16 06:49:11 PM PDT 24
Peak memory 206828 kb
Host smart-f3060196-edf6-4c93-9fdc-8bcb7bc063d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59414
507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.59414507
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2717840656
Short name T2439
Test name
Test status
Simulation time 140199016 ps
CPU time 0.79 seconds
Started Jul 16 06:49:08 PM PDT 24
Finished Jul 16 06:49:11 PM PDT 24
Peak memory 206868 kb
Host smart-34b0e986-d420-41a7-8466-46755d116442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27178
40656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2717840656
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3809480199
Short name T892
Test name
Test status
Simulation time 163444975 ps
CPU time 0.81 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206832 kb
Host smart-ca2d332d-d3fe-468e-b53d-26eba09a923a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38094
80199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3809480199
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3487689195
Short name T854
Test name
Test status
Simulation time 177626003 ps
CPU time 0.78 seconds
Started Jul 16 06:49:08 PM PDT 24
Finished Jul 16 06:49:11 PM PDT 24
Peak memory 206876 kb
Host smart-6c671f1a-65a9-4293-8ca4-fdc9a7a7022f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34876
89195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3487689195
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.857195497
Short name T48
Test name
Test status
Simulation time 227923407 ps
CPU time 0.87 seconds
Started Jul 16 06:49:05 PM PDT 24
Finished Jul 16 06:49:07 PM PDT 24
Peak memory 206828 kb
Host smart-f6bf43c2-b351-4736-b39e-f7b76fef7cbe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=857195497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.857195497
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2976683638
Short name T1754
Test name
Test status
Simulation time 140998322 ps
CPU time 0.75 seconds
Started Jul 16 06:49:07 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206860 kb
Host smart-c429eea2-2ad0-40f6-a9b0-85150a0ca7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29766
83638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2976683638
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3838411303
Short name T665
Test name
Test status
Simulation time 103214210 ps
CPU time 0.69 seconds
Started Jul 16 06:49:09 PM PDT 24
Finished Jul 16 06:49:12 PM PDT 24
Peak memory 206824 kb
Host smart-b9f27725-3e57-4eb0-8735-44cf5440c4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38384
11303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3838411303
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1371194482
Short name T239
Test name
Test status
Simulation time 9884901784 ps
CPU time 22.96 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:31 PM PDT 24
Peak memory 207184 kb
Host smart-9051f24a-8971-42c3-9f77-d77e87e7639a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13711
94482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1371194482
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.285717062
Short name T2142
Test name
Test status
Simulation time 188505149 ps
CPU time 0.84 seconds
Started Jul 16 06:49:08 PM PDT 24
Finished Jul 16 06:49:10 PM PDT 24
Peak memory 206876 kb
Host smart-a167bab2-14fe-4402-a6a2-56a4c9c103c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28571
7062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.285717062
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2496369087
Short name T681
Test name
Test status
Simulation time 198839682 ps
CPU time 0.9 seconds
Started Jul 16 06:49:10 PM PDT 24
Finished Jul 16 06:49:12 PM PDT 24
Peak memory 206868 kb
Host smart-c0f1aa92-af4e-4511-a176-4e951ae8ecc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24963
69087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2496369087
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2850070348
Short name T2579
Test name
Test status
Simulation time 12671938825 ps
CPU time 106.48 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 207152 kb
Host smart-d40d02cb-8bc1-48a5-a0bf-eaf1d78e2f1f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2850070348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2850070348
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1376612212
Short name T2687
Test name
Test status
Simulation time 9195704543 ps
CPU time 162.52 seconds
Started Jul 16 06:49:21 PM PDT 24
Finished Jul 16 06:52:07 PM PDT 24
Peak memory 207156 kb
Host smart-da1ee326-4b47-4018-ab87-35b733d16f4c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1376612212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1376612212
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1993237917
Short name T1941
Test name
Test status
Simulation time 12069210076 ps
CPU time 82.6 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:50:42 PM PDT 24
Peak memory 207160 kb
Host smart-93323cfa-0d22-4e9a-93db-16ba91d2fc2a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1993237917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1993237917
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.3784796644
Short name T2736
Test name
Test status
Simulation time 243242203 ps
CPU time 0.91 seconds
Started Jul 16 06:49:09 PM PDT 24
Finished Jul 16 06:49:12 PM PDT 24
Peak memory 206852 kb
Host smart-0a424994-8b85-40af-8f32-f69fb18591cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37847
96644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.3784796644
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1450151014
Short name T2169
Test name
Test status
Simulation time 167422623 ps
CPU time 0.81 seconds
Started Jul 16 06:49:06 PM PDT 24
Finished Jul 16 06:49:08 PM PDT 24
Peak memory 206888 kb
Host smart-8b4f78b8-9f08-44eb-88df-28ed8938dcc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14501
51014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1450151014
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.581718944
Short name T896
Test name
Test status
Simulation time 170186925 ps
CPU time 0.81 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 206880 kb
Host smart-adb5f720-6acd-44ad-85bc-8246df864273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58171
8944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.581718944
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1057203300
Short name T1346
Test name
Test status
Simulation time 159290305 ps
CPU time 0.74 seconds
Started Jul 16 06:49:22 PM PDT 24
Finished Jul 16 06:49:25 PM PDT 24
Peak memory 206808 kb
Host smart-65694e3b-d9bb-4a8c-918c-80478dfc57c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10572
03300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1057203300
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.4189119854
Short name T514
Test name
Test status
Simulation time 199604495 ps
CPU time 0.8 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:23 PM PDT 24
Peak memory 206852 kb
Host smart-28b0f8f0-47b0-4271-8939-62c85099b6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41891
19854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.4189119854
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3476153321
Short name T2518
Test name
Test status
Simulation time 204674712 ps
CPU time 0.91 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:21 PM PDT 24
Peak memory 206772 kb
Host smart-ecf94870-ddf4-49e4-ae99-19e911105571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34761
53321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3476153321
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3672872240
Short name T2060
Test name
Test status
Simulation time 4898449650 ps
CPU time 34.9 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:58 PM PDT 24
Peak memory 207004 kb
Host smart-96edb3ac-47a7-40e3-9ba6-3f9d6b9b20cd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3672872240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3672872240
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1632071365
Short name T511
Test name
Test status
Simulation time 171573875 ps
CPU time 0.82 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 206864 kb
Host smart-550297c0-4d15-48e9-9795-3ab965eae025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320
71365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1632071365
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.209287560
Short name T545
Test name
Test status
Simulation time 192197421 ps
CPU time 0.82 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:24 PM PDT 24
Peak memory 206796 kb
Host smart-a9b0837b-cb92-4914-b36b-763ce522dcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20928
7560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.209287560
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.1474164808
Short name T303
Test name
Test status
Simulation time 188720765 ps
CPU time 0.8 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:23 PM PDT 24
Peak memory 206868 kb
Host smart-b709b45d-9207-4a17-a968-4f2ff08b8139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14741
64808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1474164808
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1851945545
Short name T1070
Test name
Test status
Simulation time 4325067828 ps
CPU time 31.49 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:54 PM PDT 24
Peak memory 207140 kb
Host smart-03defc25-45bf-44e5-9336-c93b30b736da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18519
45545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1851945545
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1848721217
Short name T549
Test name
Test status
Simulation time 27344234 ps
CPU time 0.67 seconds
Started Jul 16 06:49:32 PM PDT 24
Finished Jul 16 06:49:36 PM PDT 24
Peak memory 206920 kb
Host smart-9785d775-4e87-4038-82b1-5c3b6d4b5313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1848721217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1848721217
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1173460940
Short name T1065
Test name
Test status
Simulation time 3914575901 ps
CPU time 4.44 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:27 PM PDT 24
Peak memory 206864 kb
Host smart-8b98edd7-d5bf-496c-a8d5-3150125ac706
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1173460940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1173460940
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3911743030
Short name T2264
Test name
Test status
Simulation time 13346208025 ps
CPU time 11.45 seconds
Started Jul 16 06:49:24 PM PDT 24
Finished Jul 16 06:49:38 PM PDT 24
Peak memory 207080 kb
Host smart-226995e3-5a8e-4b3b-991a-da34a66cf414
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3911743030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3911743030
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.2512509326
Short name T1423
Test name
Test status
Simulation time 23347287876 ps
CPU time 27.34 seconds
Started Jul 16 06:49:17 PM PDT 24
Finished Jul 16 06:49:45 PM PDT 24
Peak memory 206944 kb
Host smart-f8996e28-7b50-4fdd-835c-081545b891e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2512509326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.2512509326
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1165951405
Short name T500
Test name
Test status
Simulation time 159588677 ps
CPU time 0.82 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:24 PM PDT 24
Peak memory 206880 kb
Host smart-16386f68-682f-4a8f-9516-d90bcbf7d00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11659
51405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1165951405
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1691862476
Short name T2205
Test name
Test status
Simulation time 148102358 ps
CPU time 0.81 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 206856 kb
Host smart-a778caab-32b6-4efe-b39f-ac8a7bb6a6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16918
62476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1691862476
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.95795281
Short name T575
Test name
Test status
Simulation time 416155689 ps
CPU time 1.3 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 206848 kb
Host smart-26055cb1-5afc-4552-ac31-98ab565b29f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95795
281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.95795281
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2542414824
Short name T857
Test name
Test status
Simulation time 1339465072 ps
CPU time 3.02 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:26 PM PDT 24
Peak memory 207004 kb
Host smart-657cb8ef-5af3-4c6a-83e6-7c3443e305da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25424
14824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2542414824
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3385344420
Short name T1222
Test name
Test status
Simulation time 15925816705 ps
CPU time 28.74 seconds
Started Jul 16 06:49:22 PM PDT 24
Finished Jul 16 06:49:54 PM PDT 24
Peak memory 207132 kb
Host smart-c62d0836-a6e1-4443-96bc-115d2b2b2fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853
44420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3385344420
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.2398351576
Short name T601
Test name
Test status
Simulation time 347531093 ps
CPU time 1.13 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 206820 kb
Host smart-d1d4b227-5f79-44a6-88ec-5a8f624cfc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23983
51576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2398351576
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1084165503
Short name T2291
Test name
Test status
Simulation time 146462916 ps
CPU time 0.77 seconds
Started Jul 16 06:49:17 PM PDT 24
Finished Jul 16 06:49:19 PM PDT 24
Peak memory 206856 kb
Host smart-8d4f3ca5-fafd-43c1-ae1a-189864ebd46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10841
65503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1084165503
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.420942437
Short name T574
Test name
Test status
Simulation time 35606883 ps
CPU time 0.68 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 207024 kb
Host smart-992ba7b8-f1e4-464a-9c9c-7d3bf06f9bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42094
2437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.420942437
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2940451091
Short name T2280
Test name
Test status
Simulation time 999824309 ps
CPU time 2.41 seconds
Started Jul 16 06:49:23 PM PDT 24
Finished Jul 16 06:49:28 PM PDT 24
Peak memory 207004 kb
Host smart-6f9369d7-d37f-4f16-9a04-8932d09c21ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29404
51091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2940451091
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1919703317
Short name T859
Test name
Test status
Simulation time 161569956 ps
CPU time 1.52 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 207076 kb
Host smart-e354d5fa-ecd4-4bcb-9be9-aa4424ddfd62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19197
03317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1919703317
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.242779028
Short name T2288
Test name
Test status
Simulation time 211230145 ps
CPU time 0.86 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 206664 kb
Host smart-5597dcb6-445c-42d5-abaa-d318860061e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24277
9028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.242779028
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.80610645
Short name T1002
Test name
Test status
Simulation time 149108814 ps
CPU time 0.77 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:23 PM PDT 24
Peak memory 206848 kb
Host smart-bbffc77b-9167-4be9-a2aa-f76ddfca40e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80610
645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.80610645
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1619314673
Short name T1996
Test name
Test status
Simulation time 200875170 ps
CPU time 0.85 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:24 PM PDT 24
Peak memory 206868 kb
Host smart-48b01d0d-c2fc-40e6-8a74-9efeace88651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16193
14673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1619314673
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3412942687
Short name T1230
Test name
Test status
Simulation time 7557404743 ps
CPU time 202.9 seconds
Started Jul 16 06:49:25 PM PDT 24
Finished Jul 16 06:52:49 PM PDT 24
Peak memory 207132 kb
Host smart-1c5a7cc5-ee61-48cb-86a5-cef6802c7631
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3412942687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3412942687
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.1037063964
Short name T1434
Test name
Test status
Simulation time 3793918293 ps
CPU time 30.11 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:54 PM PDT 24
Peak memory 207048 kb
Host smart-1b7d3ba1-b137-4e40-b4ef-9c9f57b252cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
63964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.1037063964
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3221996652
Short name T2385
Test name
Test status
Simulation time 246380867 ps
CPU time 0.96 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 206728 kb
Host smart-31ff2ff9-3162-490e-924e-f0de34cbcf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32219
96652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3221996652
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3993441564
Short name T1781
Test name
Test status
Simulation time 23340045686 ps
CPU time 23.06 seconds
Started Jul 16 06:49:21 PM PDT 24
Finished Jul 16 06:49:47 PM PDT 24
Peak memory 206940 kb
Host smart-2b1e4752-d7e2-4466-a9ae-f75568b66d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39934
41564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3993441564
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3799556150
Short name T2350
Test name
Test status
Simulation time 3336876507 ps
CPU time 3.71 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:27 PM PDT 24
Peak memory 206920 kb
Host smart-23b2685f-fdee-491c-b7f7-084af7d69b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37995
56150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3799556150
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1321117731
Short name T878
Test name
Test status
Simulation time 11599800388 ps
CPU time 320.05 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:54:44 PM PDT 24
Peak memory 207148 kb
Host smart-f8f7e5ca-6a05-434a-939c-54f50e4e5bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13211
17731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1321117731
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.734180329
Short name T2729
Test name
Test status
Simulation time 4936919172 ps
CPU time 36.01 seconds
Started Jul 16 06:49:24 PM PDT 24
Finished Jul 16 06:50:02 PM PDT 24
Peak memory 207120 kb
Host smart-624a837a-ba65-4e85-96f5-bf727e96c2d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=734180329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.734180329
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.4217021635
Short name T98
Test name
Test status
Simulation time 290352011 ps
CPU time 1 seconds
Started Jul 16 06:49:22 PM PDT 24
Finished Jul 16 06:49:26 PM PDT 24
Peak memory 206832 kb
Host smart-9be1de00-d085-4514-8953-c1c135978dd5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4217021635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.4217021635
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3117830050
Short name T2323
Test name
Test status
Simulation time 192532454 ps
CPU time 0.9 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:21 PM PDT 24
Peak memory 206812 kb
Host smart-a091407e-fba5-4bb2-877f-3dcefa3c1aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31178
30050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3117830050
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3748382154
Short name T141
Test name
Test status
Simulation time 3955788154 ps
CPU time 112.04 seconds
Started Jul 16 06:49:21 PM PDT 24
Finished Jul 16 06:51:16 PM PDT 24
Peak memory 207076 kb
Host smart-769475a8-3553-4805-a2bb-cd5d60dbba44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37483
82154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3748382154
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3791517225
Short name T540
Test name
Test status
Simulation time 5239902389 ps
CPU time 53.18 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:50:13 PM PDT 24
Peak memory 207148 kb
Host smart-23cd4745-df57-4c86-b772-f8ed55e24bab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3791517225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3791517225
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.867036140
Short name T1279
Test name
Test status
Simulation time 158218902 ps
CPU time 0.76 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:23 PM PDT 24
Peak memory 206888 kb
Host smart-6a0175a3-6b49-4d3e-8e9f-4c09ac0610b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=867036140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.867036140
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3243365048
Short name T2569
Test name
Test status
Simulation time 146303460 ps
CPU time 0.78 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 206908 kb
Host smart-5c91dec2-7af7-458e-9f8e-f58cccd773e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32433
65048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3243365048
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.562854710
Short name T117
Test name
Test status
Simulation time 197863294 ps
CPU time 0.86 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 206804 kb
Host smart-4df25ddd-3076-49d8-8802-c1cf5471ead0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56285
4710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.562854710
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2177718263
Short name T1604
Test name
Test status
Simulation time 182621614 ps
CPU time 0.83 seconds
Started Jul 16 06:49:25 PM PDT 24
Finished Jul 16 06:49:27 PM PDT 24
Peak memory 206892 kb
Host smart-f40c7b8f-906c-4995-a364-88e2a8ed69fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
18263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2177718263
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2440206607
Short name T592
Test name
Test status
Simulation time 176992934 ps
CPU time 0.84 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:23 PM PDT 24
Peak memory 206860 kb
Host smart-8fd2669e-4842-4cb1-81b8-6fac51dc9bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
06607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2440206607
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4229228284
Short name T1318
Test name
Test status
Simulation time 166649380 ps
CPU time 0.8 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:49:24 PM PDT 24
Peak memory 206868 kb
Host smart-f5c6c501-ceb1-403e-a942-52d747d50518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
28284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4229228284
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.183765105
Short name T150
Test name
Test status
Simulation time 149539230 ps
CPU time 0.81 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 206868 kb
Host smart-82eadb02-2335-4cc9-88d8-a7367cdc2363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18376
5105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.183765105
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2814317030
Short name T416
Test name
Test status
Simulation time 195183174 ps
CPU time 0.85 seconds
Started Jul 16 06:49:21 PM PDT 24
Finished Jul 16 06:49:24 PM PDT 24
Peak memory 206884 kb
Host smart-1f7274a0-d790-44e8-aca9-e5f08dac3c72
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2814317030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2814317030
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.228127129
Short name T1023
Test name
Test status
Simulation time 158625698 ps
CPU time 0.79 seconds
Started Jul 16 06:49:23 PM PDT 24
Finished Jul 16 06:49:27 PM PDT 24
Peak memory 206864 kb
Host smart-28aac6ac-ef9a-4e4b-ab2b-a3a932048ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22812
7129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.228127129
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3605658620
Short name T1075
Test name
Test status
Simulation time 43488420 ps
CPU time 0.65 seconds
Started Jul 16 06:49:17 PM PDT 24
Finished Jul 16 06:49:19 PM PDT 24
Peak memory 206748 kb
Host smart-09513b24-5854-47fb-b16a-7d4e70c3f3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36056
58620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3605658620
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.382856769
Short name T1032
Test name
Test status
Simulation time 7662544116 ps
CPU time 19.53 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:39 PM PDT 24
Peak memory 207152 kb
Host smart-b4209b09-6219-4285-b2eb-071d00ee5081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38285
6769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.382856769
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3629026111
Short name T2174
Test name
Test status
Simulation time 162650626 ps
CPU time 0.81 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:23 PM PDT 24
Peak memory 206852 kb
Host smart-f6db397e-c44f-4ba0-a5ab-6108e0d8b890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36290
26111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3629026111
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3942221652
Short name T1090
Test name
Test status
Simulation time 213351032 ps
CPU time 0.86 seconds
Started Jul 16 06:49:21 PM PDT 24
Finished Jul 16 06:49:25 PM PDT 24
Peak memory 206832 kb
Host smart-d75c2eb9-28a8-42f1-be65-d1d6e1c6189a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
21652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3942221652
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.812501151
Short name T1411
Test name
Test status
Simulation time 7778917844 ps
CPU time 55.18 seconds
Started Jul 16 06:49:23 PM PDT 24
Finished Jul 16 06:50:20 PM PDT 24
Peak memory 207132 kb
Host smart-3d82add0-6573-4fdf-8f43-ae7ebb9f0df5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=812501151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.812501151
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2146196451
Short name T1898
Test name
Test status
Simulation time 5908321453 ps
CPU time 48.63 seconds
Started Jul 16 06:49:20 PM PDT 24
Finished Jul 16 06:50:11 PM PDT 24
Peak memory 206980 kb
Host smart-4066733e-7d49-449a-8283-7e630c62cad0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2146196451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2146196451
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1410878414
Short name T1757
Test name
Test status
Simulation time 12449377729 ps
CPU time 62.35 seconds
Started Jul 16 06:49:23 PM PDT 24
Finished Jul 16 06:50:28 PM PDT 24
Peak memory 207064 kb
Host smart-862a3de7-513f-42ba-b976-3557b0e1ed99
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1410878414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1410878414
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1814644254
Short name T1660
Test name
Test status
Simulation time 240207941 ps
CPU time 0.98 seconds
Started Jul 16 06:49:21 PM PDT 24
Finished Jul 16 06:49:25 PM PDT 24
Peak memory 206756 kb
Host smart-c71a14d8-b9de-4efe-839d-7eb2e5ebe59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18146
44254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1814644254
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3279254953
Short name T1358
Test name
Test status
Simulation time 193599409 ps
CPU time 0.8 seconds
Started Jul 16 06:49:21 PM PDT 24
Finished Jul 16 06:49:25 PM PDT 24
Peak memory 206856 kb
Host smart-edf4af1b-d49d-4d9b-a9dd-771d78b41ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32792
54953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3279254953
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1280324031
Short name T1511
Test name
Test status
Simulation time 187783584 ps
CPU time 0.84 seconds
Started Jul 16 06:49:18 PM PDT 24
Finished Jul 16 06:49:20 PM PDT 24
Peak memory 206876 kb
Host smart-57ae7119-458c-4271-9083-e0199c0367a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12803
24031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1280324031
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3647843814
Short name T1624
Test name
Test status
Simulation time 185495548 ps
CPU time 0.8 seconds
Started Jul 16 06:49:19 PM PDT 24
Finished Jul 16 06:49:22 PM PDT 24
Peak memory 206868 kb
Host smart-64913f9d-04cc-474e-ad70-d2f83720c46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36478
43814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3647843814
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4153387462
Short name T1215
Test name
Test status
Simulation time 162331174 ps
CPU time 0.75 seconds
Started Jul 16 06:49:25 PM PDT 24
Finished Jul 16 06:49:27 PM PDT 24
Peak memory 206896 kb
Host smart-73eca934-6c10-4136-9922-08e0a15753fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41533
87462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4153387462
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.617712764
Short name T2031
Test name
Test status
Simulation time 257863108 ps
CPU time 0.94 seconds
Started Jul 16 06:49:25 PM PDT 24
Finished Jul 16 06:49:28 PM PDT 24
Peak memory 206892 kb
Host smart-e4217c64-ff97-4f5e-a1f3-ea2f24882c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61771
2764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.617712764
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2112823597
Short name T981
Test name
Test status
Simulation time 6151744971 ps
CPU time 54.6 seconds
Started Jul 16 06:49:23 PM PDT 24
Finished Jul 16 06:50:20 PM PDT 24
Peak memory 207128 kb
Host smart-eaa7e2e6-7938-416b-b628-896e432c15be
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2112823597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2112823597
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.605054996
Short name T2607
Test name
Test status
Simulation time 215559710 ps
CPU time 0.83 seconds
Started Jul 16 06:49:23 PM PDT 24
Finished Jul 16 06:49:26 PM PDT 24
Peak memory 206848 kb
Host smart-474c3fc9-a628-493c-b055-8507aa1b2143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60505
4996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.605054996
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2877061146
Short name T2637
Test name
Test status
Simulation time 163583312 ps
CPU time 0.79 seconds
Started Jul 16 06:49:23 PM PDT 24
Finished Jul 16 06:49:27 PM PDT 24
Peak memory 206848 kb
Host smart-b0f79a41-9ee2-4154-950f-d5a95438dcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28770
61146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2877061146
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3816062139
Short name T1383
Test name
Test status
Simulation time 859526101 ps
CPU time 1.9 seconds
Started Jul 16 06:49:24 PM PDT 24
Finished Jul 16 06:49:28 PM PDT 24
Peak memory 207076 kb
Host smart-372d73a2-738d-4c39-89e4-b953f4e0f99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38160
62139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3816062139
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1795756800
Short name T1450
Test name
Test status
Simulation time 3734107509 ps
CPU time 102.17 seconds
Started Jul 16 06:49:23 PM PDT 24
Finished Jul 16 06:51:08 PM PDT 24
Peak memory 207056 kb
Host smart-39fcd20f-0281-4000-a436-3121c610d0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17957
56800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1795756800
Directory /workspace/9.usbdev_streaming_out/latest
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