Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	79419	1		T1	4		T2	4		T3	3
all_values[1]	79419	1		T1	4		T2	4		T3	3
all_values[2]	79419	1		T1	4		T2	4		T3	3
all_values[3]	79419	1		T1	4		T2	4		T3	3
all_values[4]	79419	1		T1	4		T2	4		T3	3
all_values[5]	79419	1		T1	4		T2	4		T3	3
all_values[6]	79419	1		T1	4		T2	4		T3	3
all_values[7]	79419	1		T1	4		T2	4		T3	3
all_values[8]	79419	1		T1	4		T2	4		T3	3
all_values[9]	79419	1		T1	4		T2	4		T3	3
all_values[10]	79419	1		T1	4		T2	4		T3	3
all_values[11]	79419	1		T1	4		T2	4		T3	3
all_values[12]	79419	1		T1	4		T2	4		T3	3
all_values[13]	79419	1		T1	4		T2	4		T3	3
all_values[14]	79419	1		T1	4		T2	4		T3	3
all_values[15]	79419	1		T1	4		T2	4		T3	3
all_values[16]	79419	1		T1	4		T2	4		T3	3
all_values[17]	79419	1		T1	4		T2	4		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1422584	1		T1	72		T2	68		T3	51
auto[1]	6958	1		T2	4		T3	3		T35	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1424594	1		T1	72		T2	72		T3	54
auto[1]	4948	1		T195	70		T196	129		T197	124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	78445	1		T1	4		T3	3		T28	4
all_values[0]	auto[0]	auto[1]	130	1		T195	5		T196	2		T197	2
all_values[0]	auto[1]	auto[0]	701	1		T2	4		T48	3		T49	3
all_values[0]	auto[1]	auto[1]	143	1		T196	6		T197	4		T198	4
all_values[1]	auto[0]	auto[0]	77617	1		T1	4		T2	4		T28	4
all_values[1]	auto[0]	auto[1]	145	1		T195	4		T196	5		T198	2
all_values[1]	auto[1]	auto[0]	1518	1		T3	3		T33	3		T7	2
all_values[1]	auto[1]	auto[1]	139	1		T195	1		T196	3		T197	7
all_values[2]	auto[0]	auto[0]	79011	1		T1	4		T2	4		T3	3
all_values[2]	auto[0]	auto[1]	137	1		T196	3		T197	4		T198	3
all_values[2]	auto[1]	auto[0]	128	1		T35	2		T44	2		T67	2
all_values[2]	auto[1]	auto[1]	143	1		T195	4		T196	5		T197	4
all_values[3]	auto[0]	auto[0]	77695	1		T1	4		T2	4		T3	3
all_values[3]	auto[0]	auto[1]	115	1		T195	1		T196	3		T197	1
all_values[3]	auto[1]	auto[0]	1470	1		T68	1430		T275	1		T271	1
all_values[3]	auto[1]	auto[1]	139	1		T195	4		T196	5		T197	7
all_values[4]	auto[0]	auto[0]	79116	1		T1	4		T2	4		T3	3
all_values[4]	auto[0]	auto[1]	150	1		T195	3		T196	6		T197	3
all_values[4]	auto[1]	auto[0]	21	1		T69	2		T195	1		T275	1
all_values[4]	auto[1]	auto[1]	132	1		T195	1		T196	2		T197	5
all_values[5]	auto[0]	auto[0]	79126	1		T1	4		T2	4		T3	3
all_values[5]	auto[0]	auto[1]	119	1		T195	3		T196	3		T197	3
all_values[5]	auto[1]	auto[0]	30	1		T195	1		T196	4		T271	1
all_values[5]	auto[1]	auto[1]	144	1		T197	5		T198	6		T275	3
all_values[6]	auto[0]	auto[0]	79107	1		T1	4		T2	4		T3	3
all_values[6]	auto[0]	auto[1]	120	1		T195	1		T196	6		T197	5
all_values[6]	auto[1]	auto[0]	26	1		T196	1		T275	1		T276	2
all_values[6]	auto[1]	auto[1]	166	1		T195	3		T197	3		T198	5
all_values[7]	auto[0]	auto[0]	79104	1		T1	4		T2	4		T3	3
all_values[7]	auto[0]	auto[1]	129	1		T196	2		T197	1		T198	2
all_values[7]	auto[1]	auto[0]	44	1		T50	2		T51	2		T195	5
all_values[7]	auto[1]	auto[1]	142	1		T196	6		T197	4		T198	4
all_values[8]	auto[0]	auto[0]	79092	1		T1	4		T2	4		T3	3
all_values[8]	auto[0]	auto[1]	149	1		T195	3		T196	1		T197	3
all_values[8]	auto[1]	auto[0]	31	1		T53	11		T271	1		T272	1
all_values[8]	auto[1]	auto[1]	147	1		T195	1		T196	6		T197	5
all_values[9]	auto[0]	auto[0]	79090	1		T1	4		T2	4		T3	3
all_values[9]	auto[0]	auto[1]	123	1		T195	1		T196	4		T197	6
all_values[9]	auto[1]	auto[0]	54	1		T64	5		T65	5		T66	5
all_values[9]	auto[1]	auto[1]	152	1		T195	4		T196	4		T197	1
all_values[10]	auto[0]	auto[0]	79108	1		T1	4		T2	4		T3	3
all_values[10]	auto[0]	auto[1]	111	1		T195	5		T196	2		T197	3
all_values[10]	auto[1]	auto[0]	34	1		T198	1		T271	2		T276	1
all_values[10]	auto[1]	auto[1]	166	1		T196	6		T197	5		T198	5
all_values[11]	auto[0]	auto[0]	79022	1		T1	4		T2	4		T3	3
all_values[11]	auto[0]	auto[1]	132	1		T196	5		T197	7		T198	1
all_values[11]	auto[1]	auto[0]	127	1		T47	2		T76	2		T77	2
all_values[11]	auto[1]	auto[1]	138	1		T195	5		T196	3		T197	1
all_values[12]	auto[0]	auto[0]	79106	1		T1	4		T2	4		T3	3
all_values[12]	auto[0]	auto[1]	140	1		T196	5		T198	5		T275	2
all_values[12]	auto[1]	auto[0]	46	1		T78	3		T79	3		T80	3
all_values[12]	auto[1]	auto[1]	127	1		T195	3		T196	3		T198	2
all_values[13]	auto[0]	auto[0]	79120	1		T1	4		T2	4		T3	3
all_values[13]	auto[0]	auto[1]	127	1		T195	4		T196	6		T197	1
all_values[13]	auto[1]	auto[0]	22	1		T197	1		T198	2		T275	2
all_values[13]	auto[1]	auto[1]	150	1		T195	1		T196	2		T197	6
all_values[14]	auto[0]	auto[0]	79111	1		T1	4		T2	4		T3	3
all_values[14]	auto[0]	auto[1]	149	1		T195	1		T196	2		T197	5
all_values[14]	auto[1]	auto[0]	12	1		T197	1		T198	1		T271	1
all_values[14]	auto[1]	auto[1]	147	1		T195	4		T196	5		T197	1
all_values[15]	auto[0]	auto[0]	79119	1		T1	4		T2	4		T3	3
all_values[15]	auto[0]	auto[1]	138	1		T196	5		T197	5		T198	4
all_values[15]	auto[1]	auto[0]	23	1		T195	1		T196	1		T275	1
all_values[15]	auto[1]	auto[1]	139	1		T195	4		T196	1		T197	3
all_values[16]	auto[0]	auto[0]	79108	1		T1	4		T2	4		T3	3
all_values[16]	auto[0]	auto[1]	111	1		T196	3		T197	1		T198	4
all_values[16]	auto[1]	auto[0]	59	1		T72	8		T73	8		T74	8
all_values[16]	auto[1]	auto[1]	141	1		T195	4		T196	1		T197	5
all_values[17]	auto[0]	auto[0]	79113	1		T1	4		T2	4		T3	3
all_values[17]	auto[0]	auto[1]	149	1		T196	3		T197	1		T198	6
all_values[17]	auto[1]	auto[0]	38	1		T56	2		T57	2		T58	2
all_values[17]	auto[1]	auto[1]	119	1		T196	5		T197	7		T198	2