Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	79419	1		T1	4		T2	4		T3	3
all_pins[1]	79419	1		T1	4		T2	4		T3	3
all_pins[2]	79419	1		T1	4		T2	4		T3	3
all_pins[3]	79419	1		T1	4		T2	4		T3	3
all_pins[4]	79419	1		T1	4		T2	4		T3	3
all_pins[5]	79419	1		T1	4		T2	4		T3	3
all_pins[6]	79419	1		T1	4		T2	4		T3	3
all_pins[7]	79419	1		T1	4		T2	4		T3	3
all_pins[8]	79419	1		T1	4		T2	4		T3	3
all_pins[9]	79419	1		T1	4		T2	4		T3	3
all_pins[10]	79419	1		T1	4		T2	4		T3	3
all_pins[11]	79419	1		T1	4		T2	4		T3	3
all_pins[12]	79419	1		T1	4		T2	4		T3	3
all_pins[13]	79419	1		T1	4		T2	4		T3	3
all_pins[14]	79419	1		T1	4		T2	4		T3	3
all_pins[15]	79419	1		T1	4		T2	4		T3	3
all_pins[16]	79419	1		T1	4		T2	4		T3	3
all_pins[17]	79419	1		T1	4		T2	4		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1427199	1		T1	72		T2	71		T3	53
values[0x1]	2343	1		T2	1		T3	1		T35	1
transitions[0x0=>0x1]	2054	1		T2	1		T3	1		T35	1
transitions[0x1=>0x0]	2067	1		T2	1		T3	1		T35	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	79302	1		T1	4		T2	3		T3	3
all_pins[0]	values[0x1]	117	1		T2	1		T277	1		T278	1
all_pins[0]	transitions[0x0=>0x1]	103	1		T2	1		T277	1		T278	1
all_pins[0]	transitions[0x1=>0x0]	994	1		T3	1		T33	1		T7	1
all_pins[1]	values[0x0]	78411	1		T1	4		T2	4		T3	2
all_pins[1]	values[0x1]	1008	1		T3	1		T33	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	992	1		T3	1		T33	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	120	1		T35	1		T44	1		T67	1
all_pins[2]	values[0x0]	79283	1		T1	4		T2	4		T3	3
all_pins[2]	values[0x1]	136	1		T35	1		T44	1		T67	1
all_pins[2]	transitions[0x0=>0x1]	119	1		T35	1		T44	1		T67	1
all_pins[2]	transitions[0x1=>0x0]	43	1		T68	1		T195	1		T197	1
all_pins[3]	values[0x0]	79359	1		T1	4		T2	4		T3	3
all_pins[3]	values[0x1]	60	1		T68	1		T195	1		T196	2
all_pins[3]	transitions[0x0=>0x1]	50	1		T68	1		T195	1		T196	2
all_pins[3]	transitions[0x1=>0x0]	52	1		T69	1		T195	1		T197	3
all_pins[4]	values[0x0]	79357	1		T1	4		T2	4		T3	3
all_pins[4]	values[0x1]	62	1		T69	1		T195	1		T197	3
all_pins[4]	transitions[0x0=>0x1]	52	1		T69	1		T195	1		T197	3
all_pins[4]	transitions[0x1=>0x0]	69	1		T197	3		T198	2		T271	3
all_pins[5]	values[0x0]	79340	1		T1	4		T2	4		T3	3
all_pins[5]	values[0x1]	79	1		T197	3		T198	2		T271	3
all_pins[5]	transitions[0x0=>0x1]	60	1		T197	2		T198	1		T271	3
all_pins[5]	transitions[0x1=>0x0]	46	1		T195	2		T197	1		T272	1
all_pins[6]	values[0x0]	79354	1		T1	4		T2	4		T3	3
all_pins[6]	values[0x1]	65	1		T195	2		T197	2		T198	1
all_pins[6]	transitions[0x0=>0x1]	53	1		T195	2		T197	2		T198	1
all_pins[6]	transitions[0x1=>0x0]	58	1		T50	1		T51	1		T196	3
all_pins[7]	values[0x0]	79349	1		T1	4		T2	4		T3	3
all_pins[7]	values[0x1]	70	1		T50	1		T51	1		T196	3
all_pins[7]	transitions[0x0=>0x1]	49	1		T50	1		T51	1		T196	2
all_pins[7]	transitions[0x1=>0x0]	43	1		T53	1		T195	1		T197	1
all_pins[8]	values[0x0]	79355	1		T1	4		T2	4		T3	3
all_pins[8]	values[0x1]	64	1		T53	1		T195	1		T196	1
all_pins[8]	transitions[0x0=>0x1]	52	1		T53	1		T195	1		T196	1
all_pins[8]	transitions[0x1=>0x0]	67	1		T64	2		T65	2		T66	2
all_pins[9]	values[0x0]	79340	1		T1	4		T2	4		T3	3
all_pins[9]	values[0x1]	79	1		T64	2		T65	2		T66	2
all_pins[9]	transitions[0x0=>0x1]	57	1		T64	2		T65	2		T66	2
all_pins[9]	transitions[0x1=>0x0]	53	1		T197	2		T198	1		T272	1
all_pins[10]	values[0x0]	79344	1		T1	4		T2	4		T3	3
all_pins[10]	values[0x1]	75	1		T196	2		T197	3		T198	1
all_pins[10]	transitions[0x0=>0x1]	55	1		T196	2		T197	2		T272	1
all_pins[10]	transitions[0x1=>0x0]	109	1		T47	1		T76	1		T77	1
all_pins[11]	values[0x0]	79290	1		T1	4		T2	4		T3	3
all_pins[11]	values[0x1]	129	1		T47	1		T76	1		T77	1
all_pins[11]	transitions[0x0=>0x1]	109	1		T47	1		T76	1		T77	1
all_pins[11]	transitions[0x1=>0x0]	40	1		T78	1		T79	1		T80	1
all_pins[12]	values[0x0]	79359	1		T1	4		T2	4		T3	3
all_pins[12]	values[0x1]	60	1		T78	1		T79	1		T80	1
all_pins[12]	transitions[0x0=>0x1]	47	1		T78	1		T79	1		T80	1
all_pins[12]	transitions[0x1=>0x0]	51	1		T195	1		T197	5		T198	1
all_pins[13]	values[0x0]	79355	1		T1	4		T2	4		T3	3
all_pins[13]	values[0x1]	64	1		T195	1		T197	5		T198	1
all_pins[13]	transitions[0x0=>0x1]	56	1		T195	1		T197	5		T272	2
all_pins[13]	transitions[0x1=>0x0]	58	1		T195	3		T196	4		T198	1
all_pins[14]	values[0x0]	79353	1		T1	4		T2	4		T3	3
all_pins[14]	values[0x1]	66	1		T195	3		T196	4		T198	2
all_pins[14]	transitions[0x0=>0x1]	47	1		T195	3		T196	3		T198	2
all_pins[14]	transitions[0x1=>0x0]	54	1		T195	1		T198	1		T271	1
all_pins[15]	values[0x0]	79346	1		T1	4		T2	4		T3	3
all_pins[15]	values[0x1]	73	1		T195	1		T196	1		T198	1
all_pins[15]	transitions[0x0=>0x1]	56	1		T196	1		T198	1		T271	1
all_pins[15]	transitions[0x1=>0x0]	63	1		T72	4		T73	4		T74	4
all_pins[16]	values[0x0]	79339	1		T1	4		T2	4		T3	3
all_pins[16]	values[0x1]	80	1		T72	4		T73	4		T74	4
all_pins[16]	transitions[0x0=>0x1]	66	1		T72	4		T73	4		T74	4
all_pins[16]	transitions[0x1=>0x0]	42	1		T56	1		T57	1		T58	1
all_pins[17]	values[0x0]	79363	1		T1	4		T2	4		T3	3
all_pins[17]	values[0x1]	56	1		T56	1		T57	1		T58	1
all_pins[17]	transitions[0x0=>0x1]	31	1		T56	1		T57	1		T58	1
all_pins[17]	transitions[0x1=>0x0]	105	1		T2	1		T277	1		T278	1