Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T195	4		T196	7		T197	7
all_values[1]	278	1		T195	4		T196	7		T197	7
all_values[2]	278	1		T195	4		T196	7		T197	7
all_values[3]	278	1		T195	4		T196	7		T197	7
all_values[4]	278	1		T195	4		T196	7		T197	7
all_values[5]	278	1		T195	4		T196	7		T197	7
all_values[6]	278	1		T195	4		T196	7		T197	7
all_values[7]	278	1		T195	4		T196	7		T197	7
all_values[8]	278	1		T195	4		T196	7		T197	7
all_values[9]	278	1		T195	4		T196	7		T197	7
all_values[10]	278	1		T195	4		T196	7		T197	7
all_values[11]	278	1		T195	4		T196	7		T197	7
all_values[12]	278	1		T195	4		T196	7		T197	7
all_values[13]	278	1		T195	4		T196	7		T197	7
all_values[14]	278	1		T195	4		T196	7		T197	7
all_values[15]	278	1		T195	4		T196	7		T197	7
all_values[16]	278	1		T195	4		T196	7		T197	7
all_values[17]	278	1		T195	4		T196	7		T197	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2665	1		T195	43		T196	69		T197	49
auto[1]	2339	1		T195	29		T196	57		T197	77

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	895	1		T195	18		T196	15		T197	19
auto[1]	4109	1		T195	54		T196	111		T197	107

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2952	1		T195	44		T196	68		T197	79
auto[1]	2052	1		T195	28		T196	58		T197	47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	31	1		T198	1		T275	1		T271	1
all_values[0]	auto[0]	auto[0]	auto[1]	47	1		T195	2		T196	1		T197	2
all_values[0]	auto[0]	auto[1]	auto[0]	21	1		T197	2		T198	1		T279	1
all_values[0]	auto[0]	auto[1]	auto[1]	58	1		T196	1		T197	1		T198	1
all_values[0]	auto[1]	auto[0]	auto[1]	60	1		T195	2		T196	1		T197	1
all_values[0]	auto[1]	auto[1]	auto[1]	61	1		T196	4		T197	1		T198	2
all_values[1]	auto[0]	auto[0]	auto[0]	32	1		T198	1		T271	1		T272	2
all_values[1]	auto[0]	auto[0]	auto[1]	63	1		T195	2		T196	2		T198	2
all_values[1]	auto[0]	auto[1]	auto[0]	10	1		T197	1		T272	1		T280	1
all_values[1]	auto[0]	auto[1]	auto[1]	60	1		T196	1		T197	4		T198	2
all_values[1]	auto[1]	auto[0]	auto[1]	61	1		T195	1		T196	2		T275	2
all_values[1]	auto[1]	auto[1]	auto[1]	52	1		T195	1		T196	2		T197	2
all_values[2]	auto[0]	auto[0]	auto[0]	27	1		T195	1		T273	1		T274	1
all_values[2]	auto[0]	auto[0]	auto[1]	61	1		T197	1		T198	2		T275	1
all_values[2]	auto[0]	auto[1]	auto[0]	19	1		T279	1		T281	1		T282	2
all_values[2]	auto[0]	auto[1]	auto[1]	56	1		T195	2		T196	3		T197	1
all_values[2]	auto[1]	auto[0]	auto[1]	72	1		T195	1		T196	3		T197	3
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T196	1		T197	2		T198	1
all_values[3]	auto[0]	auto[0]	auto[0]	40	1		T275	2		T271	2		T276	3
all_values[3]	auto[0]	auto[0]	auto[1]	42	1		T196	2		T198	2		T275	1
all_values[3]	auto[0]	auto[1]	auto[0]	28	1		T276	1		T279	2		T280	4
all_values[3]	auto[0]	auto[1]	auto[1]	60	1		T195	2		T196	1		T197	5
all_values[3]	auto[1]	auto[0]	auto[1]	56	1		T195	1		T196	2		T198	2
all_values[3]	auto[1]	auto[1]	auto[1]	52	1		T195	1		T196	2		T197	2
all_values[4]	auto[0]	auto[0]	auto[0]	31	1		T195	1		T275	1		T283	2
all_values[4]	auto[0]	auto[0]	auto[1]	61	1		T195	1		T196	2		T198	1
all_values[4]	auto[0]	auto[1]	auto[0]	14	1		T275	1		T279	3		T284	2
all_values[4]	auto[0]	auto[1]	auto[1]	52	1		T196	1		T197	4		T198	4
all_values[4]	auto[1]	auto[0]	auto[1]	70	1		T195	1		T196	4		T197	2
all_values[4]	auto[1]	auto[1]	auto[1]	50	1		T195	1		T197	1		T198	1
all_values[5]	auto[0]	auto[0]	auto[0]	42	1		T195	1		T196	1		T271	1
all_values[5]	auto[0]	auto[0]	auto[1]	46	1		T195	1		T196	1		T197	1
all_values[5]	auto[0]	auto[1]	auto[0]	19	1		T195	1		T196	4		T274	1
all_values[5]	auto[0]	auto[1]	auto[1]	61	1		T197	4		T198	3		T275	1
all_values[5]	auto[1]	auto[0]	auto[1]	55	1		T195	1		T196	1		T198	1
all_values[5]	auto[1]	auto[1]	auto[1]	55	1		T197	2		T198	3		T275	1
all_values[6]	auto[0]	auto[0]	auto[0]	21	1		T195	1		T196	1		T275	1
all_values[6]	auto[0]	auto[0]	auto[1]	48	1		T196	1		T197	2		T198	1
all_values[6]	auto[0]	auto[1]	auto[0]	18	1		T196	1		T275	1		T276	2
all_values[6]	auto[0]	auto[1]	auto[1]	69	1		T195	1		T197	2		T198	2
all_values[6]	auto[1]	auto[0]	auto[1]	59	1		T195	1		T196	4		T197	2
all_values[6]	auto[1]	auto[1]	auto[1]	63	1		T195	1		T197	1		T198	3
all_values[7]	auto[0]	auto[0]	auto[0]	30	1		T195	1		T197	3		T198	2
all_values[7]	auto[0]	auto[0]	auto[1]	48	1		T197	1		T198	1		T275	3
all_values[7]	auto[0]	auto[1]	auto[0]	21	1		T195	3		T273	1		T280	1
all_values[7]	auto[0]	auto[1]	auto[1]	63	1		T196	2		T197	1		T198	1
all_values[7]	auto[1]	auto[0]	auto[1]	53	1		T196	3		T197	1		T198	1
all_values[7]	auto[1]	auto[1]	auto[1]	63	1		T196	2		T197	1		T198	2
all_values[8]	auto[0]	auto[0]	auto[0]	19	1		T195	1		T196	1		T271	1
all_values[8]	auto[0]	auto[0]	auto[1]	62	1		T195	2		T197	2		T198	2
all_values[8]	auto[0]	auto[1]	auto[0]	12	1		T272	1		T285	2		T286	1
all_values[8]	auto[0]	auto[1]	auto[1]	63	1		T196	4		T197	3		T198	2
all_values[8]	auto[1]	auto[0]	auto[1]	67	1		T195	1		T196	1		T197	1
all_values[8]	auto[1]	auto[1]	auto[1]	55	1		T196	1		T197	1		T198	1
all_values[9]	auto[0]	auto[0]	auto[0]	34	1		T197	1		T198	2		T275	1
all_values[9]	auto[0]	auto[0]	auto[1]	54	1		T196	2		T197	4		T275	1
all_values[9]	auto[0]	auto[1]	auto[0]	17	1		T279	3		T285	4		T287	2
all_values[9]	auto[0]	auto[1]	auto[1]	66	1		T195	1		T196	2		T198	3
all_values[9]	auto[1]	auto[0]	auto[1]	64	1		T195	1		T196	2		T197	2
all_values[9]	auto[1]	auto[1]	auto[1]	43	1		T195	2		T196	1		T198	1
all_values[10]	auto[0]	auto[0]	auto[0]	24	1		T198	1		T271	1		T272	1
all_values[10]	auto[0]	auto[0]	auto[1]	44	1		T195	2		T196	1		T197	1
all_values[10]	auto[0]	auto[1]	auto[0]	22	1		T271	1		T274	1		T288	2
all_values[10]	auto[0]	auto[1]	auto[1]	74	1		T196	4		T197	2		T198	2
all_values[10]	auto[1]	auto[0]	auto[1]	50	1		T195	2		T196	2		T275	2
all_values[10]	auto[1]	auto[1]	auto[1]	64	1		T197	4		T198	3		T271	1
all_values[11]	auto[0]	auto[0]	auto[0]	37	1		T275	1		T271	3		T276	1
all_values[11]	auto[0]	auto[0]	auto[1]	53	1		T196	1		T197	2		T275	1
all_values[11]	auto[0]	auto[1]	auto[0]	16	1		T275	1		T271	1		T276	3
all_values[11]	auto[0]	auto[1]	auto[1]	56	1		T195	2		T196	1		T198	3
all_values[11]	auto[1]	auto[0]	auto[1]	66	1		T195	1		T196	3		T197	4
all_values[11]	auto[1]	auto[1]	auto[1]	50	1		T195	1		T196	2		T197	1
all_values[12]	auto[0]	auto[0]	auto[0]	36	1		T195	2		T197	2		T198	1
all_values[12]	auto[0]	auto[0]	auto[1]	61	1		T196	2		T198	2		T275	1
all_values[12]	auto[0]	auto[1]	auto[0]	19	1		T197	5		T288	2		T289	1
all_values[12]	auto[0]	auto[1]	auto[1]	54	1		T195	1		T196	2		T198	1
all_values[12]	auto[1]	auto[0]	auto[1]	71	1		T196	2		T198	3		T275	1
all_values[12]	auto[1]	auto[1]	auto[1]	37	1		T195	1		T196	1		T271	1
all_values[13]	auto[0]	auto[0]	auto[0]	31	1		T198	1		T275	1		T272	3
all_values[13]	auto[0]	auto[0]	auto[1]	58	1		T195	2		T196	3		T197	1
all_values[13]	auto[0]	auto[1]	auto[0]	17	1		T197	1		T198	1		T275	1
all_values[13]	auto[0]	auto[1]	auto[1]	56	1		T196	2		T197	3		T275	1
all_values[13]	auto[1]	auto[0]	auto[1]	72	1		T195	2		T196	2		T197	1
all_values[13]	auto[1]	auto[1]	auto[1]	44	1		T197	1		T198	2		T275	1
all_values[14]	auto[0]	auto[0]	auto[0]	22	1		T196	1		T198	1		T275	1
all_values[14]	auto[0]	auto[0]	auto[1]	52	1		T196	1		T197	1		T272	4
all_values[14]	auto[0]	auto[1]	auto[0]	9	1		T197	2		T198	1		T271	1
all_values[14]	auto[0]	auto[1]	auto[1]	60	1		T195	2		T196	1		T197	1
all_values[14]	auto[1]	auto[0]	auto[1]	82	1		T195	1		T196	1		T197	2
all_values[14]	auto[1]	auto[1]	auto[1]	53	1		T195	1		T196	3		T197	1
all_values[15]	auto[0]	auto[0]	auto[0]	38	1		T195	1		T196	2		T275	2
all_values[15]	auto[0]	auto[0]	auto[1]	59	1		T196	3		T197	3		T198	3
all_values[15]	auto[0]	auto[1]	auto[0]	12	1		T272	1		T274	1		T280	1
all_values[15]	auto[0]	auto[1]	auto[1]	56	1		T195	1		T197	3		T198	3
all_values[15]	auto[1]	auto[0]	auto[1]	64	1		T196	1		T197	1		T198	1
all_values[15]	auto[1]	auto[1]	auto[1]	49	1		T195	2		T196	1		T275	1
all_values[16]	auto[0]	auto[0]	auto[0]	40	1		T195	1		T196	2		T198	2
all_values[16]	auto[0]	auto[0]	auto[1]	52	1		T196	2		T197	1		T198	2
all_values[16]	auto[0]	auto[1]	auto[0]	30	1		T196	2		T197	2		T271	1
all_values[16]	auto[0]	auto[1]	auto[1]	62	1		T195	2		T197	1		T275	2
all_values[16]	auto[1]	auto[0]	auto[1]	50	1		T195	1		T197	1		T198	2
all_values[16]	auto[1]	auto[1]	auto[1]	44	1		T196	1		T197	2		T198	1
all_values[17]	auto[0]	auto[0]	auto[0]	34	1		T195	4		T271	1		T272	2
all_values[17]	auto[0]	auto[0]	auto[1]	59	1		T196	2		T198	1		T275	1
all_values[17]	auto[0]	auto[1]	auto[0]	22	1		T274	1		T279	2		T290	3
all_values[17]	auto[0]	auto[1]	auto[1]	61	1		T196	2		T197	3		T198	2
all_values[17]	auto[1]	auto[0]	auto[1]	54	1		T196	1		T198	4		T275	3
all_values[17]	auto[1]	auto[1]	auto[1]	48	1		T196	2		T197	4		T271	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal