Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.81 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2852
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T2767 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3935972776 Jul 17 06:16:29 PM PDT 24 Jul 17 06:16:32 PM PDT 24 99153573 ps
T286 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.615849622 Jul 17 06:16:27 PM PDT 24 Jul 17 06:16:29 PM PDT 24 62619642 ps
T251 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3078238734 Jul 17 06:16:02 PM PDT 24 Jul 17 06:16:07 PM PDT 24 391355961 ps
T2768 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4117805880 Jul 17 06:16:31 PM PDT 24 Jul 17 06:16:33 PM PDT 24 39254140 ps
T226 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3514639528 Jul 17 06:16:01 PM PDT 24 Jul 17 06:16:04 PM PDT 24 118050368 ps
T2769 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3040588172 Jul 17 06:21:22 PM PDT 24 Jul 17 06:21:24 PM PDT 24 64416582 ps
T2770 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3902254789 Jul 17 06:16:25 PM PDT 24 Jul 17 06:16:27 PM PDT 24 41068748 ps
T2771 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3300735529 Jul 17 06:16:02 PM PDT 24 Jul 17 06:16:06 PM PDT 24 128987563 ps
T292 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.4258423868 Jul 17 06:16:11 PM PDT 24 Jul 17 06:16:17 PM PDT 24 854333999 ps
T2772 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1188571206 Jul 17 06:16:21 PM PDT 24 Jul 17 06:16:24 PM PDT 24 152957316 ps
T2773 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1127320277 Jul 17 06:16:00 PM PDT 24 Jul 17 06:16:05 PM PDT 24 102489051 ps
T2774 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2034811089 Jul 17 06:23:09 PM PDT 24 Jul 17 06:23:11 PM PDT 24 87294938 ps
T252 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2268521763 Jul 17 06:16:03 PM PDT 24 Jul 17 06:16:08 PM PDT 24 300154002 ps
T2775 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1984688183 Jul 17 06:16:16 PM PDT 24 Jul 17 06:16:24 PM PDT 24 1869926120 ps
T2776 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2036636297 Jul 17 06:16:20 PM PDT 24 Jul 17 06:16:25 PM PDT 24 782127583 ps
T253 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2913209544 Jul 17 06:16:01 PM PDT 24 Jul 17 06:16:05 PM PDT 24 209114243 ps
T294 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3548573196 Jul 17 06:16:04 PM PDT 24 Jul 17 06:16:10 PM PDT 24 897409710 ps
T2777 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.510819224 Jul 17 06:16:02 PM PDT 24 Jul 17 06:16:04 PM PDT 24 40461619 ps
T254 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3501080450 Jul 17 06:16:07 PM PDT 24 Jul 17 06:16:08 PM PDT 24 64675136 ps
T227 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.860032657 Jul 17 06:15:59 PM PDT 24 Jul 17 06:16:03 PM PDT 24 227776886 ps
T2778 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1709561438 Jul 17 06:21:22 PM PDT 24 Jul 17 06:21:24 PM PDT 24 102080619 ps
T2779 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.206607382 Jul 17 06:16:09 PM PDT 24 Jul 17 06:16:12 PM PDT 24 213969504 ps
T2780 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3651685361 Jul 17 06:16:59 PM PDT 24 Jul 17 06:17:03 PM PDT 24 298853970 ps
T2781 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2077610895 Jul 17 06:16:09 PM PDT 24 Jul 17 06:16:13 PM PDT 24 226023691 ps
T2782 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3556660768 Jul 17 06:16:01 PM PDT 24 Jul 17 06:16:06 PM PDT 24 508121936 ps
T2783 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4098646246 Jul 17 06:16:14 PM PDT 24 Jul 17 06:16:17 PM PDT 24 96278207 ps
T2784 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2972422830 Jul 17 06:15:58 PM PDT 24 Jul 17 06:16:00 PM PDT 24 135950026 ps
T2785 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2276519629 Jul 17 06:16:33 PM PDT 24 Jul 17 06:16:35 PM PDT 24 57735636 ps
T2786 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3494596964 Jul 17 06:16:13 PM PDT 24 Jul 17 06:16:17 PM PDT 24 501612552 ps
T2787 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.463238554 Jul 17 06:16:14 PM PDT 24 Jul 17 06:16:17 PM PDT 24 148109654 ps
T2788 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1195328180 Jul 17 06:16:29 PM PDT 24 Jul 17 06:16:33 PM PDT 24 155758298 ps
T2789 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2438524772 Jul 17 06:16:01 PM PDT 24 Jul 17 06:16:08 PM PDT 24 496178412 ps
T2790 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2749875934 Jul 17 06:16:16 PM PDT 24 Jul 17 06:16:19 PM PDT 24 211687617 ps
T2791 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1720224696 Jul 17 06:16:42 PM PDT 24 Jul 17 06:16:43 PM PDT 24 38853205 ps
T255 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3914832628 Jul 17 06:16:05 PM PDT 24 Jul 17 06:16:14 PM PDT 24 833434459 ps
T2792 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2099111732 Jul 17 06:16:15 PM PDT 24 Jul 17 06:16:17 PM PDT 24 43614518 ps
T2793 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1506321994 Jul 17 06:16:00 PM PDT 24 Jul 17 06:16:02 PM PDT 24 32123998 ps
T2794 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.683347778 Jul 17 06:16:13 PM PDT 24 Jul 17 06:16:14 PM PDT 24 40515027 ps
T256 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1233472578 Jul 17 06:16:04 PM PDT 24 Jul 17 06:16:06 PM PDT 24 110303076 ps
T2795 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.374434944 Jul 17 06:18:13 PM PDT 24 Jul 17 06:18:16 PM PDT 24 119235417 ps
T2796 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2938148571 Jul 17 06:16:00 PM PDT 24 Jul 17 06:16:04 PM PDT 24 295105786 ps
T2797 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2557248733 Jul 17 06:16:11 PM PDT 24 Jul 17 06:16:12 PM PDT 24 70581853 ps
T2798 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2838246823 Jul 17 06:16:18 PM PDT 24 Jul 17 06:16:21 PM PDT 24 90233357 ps
T2799 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.200996952 Jul 17 06:16:30 PM PDT 24 Jul 17 06:16:34 PM PDT 24 173470511 ps
T2800 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3093221381 Jul 17 06:16:07 PM PDT 24 Jul 17 06:16:12 PM PDT 24 629621845 ps
T2801 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2418795119 Jul 17 06:16:30 PM PDT 24 Jul 17 06:16:33 PM PDT 24 91328547 ps
T2802 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3704325147 Jul 17 06:16:28 PM PDT 24 Jul 17 06:16:31 PM PDT 24 79590768 ps
T2803 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2019280588 Jul 17 06:16:32 PM PDT 24 Jul 17 06:16:35 PM PDT 24 53154192 ps
T2804 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2234803493 Jul 17 06:16:22 PM PDT 24 Jul 17 06:16:23 PM PDT 24 49117962 ps
T2805 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2217523039 Jul 17 06:16:26 PM PDT 24 Jul 17 06:16:28 PM PDT 24 60701545 ps
T2806 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3131354299 Jul 17 06:16:17 PM PDT 24 Jul 17 06:16:20 PM PDT 24 65482971 ps
T2807 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2013286922 Jul 17 06:16:27 PM PDT 24 Jul 17 06:16:30 PM PDT 24 89033790 ps
T2808 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.660356693 Jul 17 06:16:07 PM PDT 24 Jul 17 06:16:09 PM PDT 24 66859607 ps
T2809 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.730104049 Jul 17 06:16:28 PM PDT 24 Jul 17 06:16:31 PM PDT 24 50859496 ps
T2810 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.74732364 Jul 17 06:16:26 PM PDT 24 Jul 17 06:16:27 PM PDT 24 53151431 ps
T2811 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3201022225 Jul 17 06:16:24 PM PDT 24 Jul 17 06:16:26 PM PDT 24 38225190 ps
T295 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2184147815 Jul 17 06:16:30 PM PDT 24 Jul 17 06:16:35 PM PDT 24 439089078 ps
T2812 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3043383925 Jul 17 06:16:26 PM PDT 24 Jul 17 06:16:30 PM PDT 24 224860327 ps
T2813 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.635388418 Jul 17 06:16:28 PM PDT 24 Jul 17 06:16:30 PM PDT 24 46499373 ps
T2814 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.173006253 Jul 17 06:16:03 PM PDT 24 Jul 17 06:16:08 PM PDT 24 239032814 ps
T2815 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1841054391 Jul 17 06:16:02 PM PDT 24 Jul 17 06:16:11 PM PDT 24 1809698600 ps
T2816 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3467611193 Jul 17 06:16:27 PM PDT 24 Jul 17 06:16:29 PM PDT 24 141391127 ps
T2817 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3896803232 Jul 17 06:16:02 PM PDT 24 Jul 17 06:16:05 PM PDT 24 97033308 ps
T298 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.792229341 Jul 17 06:16:13 PM PDT 24 Jul 17 06:16:19 PM PDT 24 764967151 ps
T2818 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1287174926 Jul 17 06:21:22 PM PDT 24 Jul 17 06:21:23 PM PDT 24 70299593 ps
T2819 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2101843817 Jul 17 06:16:27 PM PDT 24 Jul 17 06:16:29 PM PDT 24 66361729 ps
T2820 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4013171222 Jul 17 06:16:18 PM PDT 24 Jul 17 06:16:21 PM PDT 24 116619383 ps
T2821 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.403308308 Jul 17 06:16:26 PM PDT 24 Jul 17 06:16:28 PM PDT 24 62996039 ps
T2822 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.50746390 Jul 17 06:16:15 PM PDT 24 Jul 17 06:16:18 PM PDT 24 118508184 ps
T2823 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2952841559 Jul 17 06:16:00 PM PDT 24 Jul 17 06:16:03 PM PDT 24 83236140 ps
T2824 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3938289881 Jul 17 06:16:07 PM PDT 24 Jul 17 06:16:09 PM PDT 24 98033783 ps
T2825 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.37645152 Jul 17 06:16:00 PM PDT 24 Jul 17 06:16:01 PM PDT 24 53516705 ps
T2826 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2863898307 Jul 17 06:16:30 PM PDT 24 Jul 17 06:16:33 PM PDT 24 49310996 ps
T2827 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1909608726 Jul 17 06:16:27 PM PDT 24 Jul 17 06:16:29 PM PDT 24 71564190 ps
T2828 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.613237919 Jul 17 06:16:20 PM PDT 24 Jul 17 06:16:24 PM PDT 24 97404881 ps
T2829 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3241552515 Jul 17 06:16:15 PM PDT 24 Jul 17 06:16:17 PM PDT 24 54183022 ps
T229 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.786501807 Jul 17 06:20:28 PM PDT 24 Jul 17 06:20:32 PM PDT 24 567338950 ps
T299 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2095012885 Jul 17 06:16:30 PM PDT 24 Jul 17 06:16:37 PM PDT 24 779050369 ps
T2830 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2739856236 Jul 17 06:16:09 PM PDT 24 Jul 17 06:16:16 PM PDT 24 1066837058 ps
T2831 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2084148311 Jul 17 06:16:04 PM PDT 24 Jul 17 06:16:05 PM PDT 24 43408430 ps
T2832 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3538621457 Jul 17 06:16:29 PM PDT 24 Jul 17 06:16:31 PM PDT 24 58780413 ps
T2833 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1860302108 Jul 17 06:16:21 PM PDT 24 Jul 17 06:16:25 PM PDT 24 238048411 ps
T2834 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4088826653 Jul 17 06:16:17 PM PDT 24 Jul 17 06:16:20 PM PDT 24 106923959 ps
T2835 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3894183986 Jul 17 06:16:16 PM PDT 24 Jul 17 06:16:19 PM PDT 24 55674707 ps
T2836 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4228833164 Jul 17 06:16:00 PM PDT 24 Jul 17 06:16:02 PM PDT 24 112506695 ps
T2837 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2661908691 Jul 17 06:15:59 PM PDT 24 Jul 17 06:16:01 PM PDT 24 72995515 ps
T2838 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1924214193 Jul 17 06:16:14 PM PDT 24 Jul 17 06:16:18 PM PDT 24 309534709 ps
T2839 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3147703260 Jul 17 06:16:14 PM PDT 24 Jul 17 06:16:16 PM PDT 24 46600964 ps
T296 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2178043563 Jul 17 06:16:05 PM PDT 24 Jul 17 06:16:11 PM PDT 24 1035220587 ps
T2840 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.887203977 Jul 17 06:16:21 PM PDT 24 Jul 17 06:16:22 PM PDT 24 50897076 ps
T2841 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1971629122 Jul 17 06:16:01 PM PDT 24 Jul 17 06:16:05 PM PDT 24 109761078 ps
T2842 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2929509137 Jul 17 06:16:15 PM PDT 24 Jul 17 06:16:21 PM PDT 24 187035425 ps
T2843 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4284382759 Jul 17 06:16:29 PM PDT 24 Jul 17 06:16:32 PM PDT 24 96744661 ps
T2844 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3896822364 Jul 17 06:16:03 PM PDT 24 Jul 17 06:16:07 PM PDT 24 127770516 ps
T2845 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3188622153 Jul 17 06:16:35 PM PDT 24 Jul 17 06:16:36 PM PDT 24 32418021 ps
T2846 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.817556227 Jul 17 06:16:33 PM PDT 24 Jul 17 06:16:36 PM PDT 24 106768567 ps
T2847 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1204280510 Jul 17 06:16:15 PM PDT 24 Jul 17 06:16:20 PM PDT 24 285887814 ps
T2848 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.288919358 Jul 17 06:16:08 PM PDT 24 Jul 17 06:16:10 PM PDT 24 145040485 ps
T2849 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3935313430 Jul 17 06:16:30 PM PDT 24 Jul 17 06:16:33 PM PDT 24 165256391 ps
T2850 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1499633346 Jul 17 06:16:32 PM PDT 24 Jul 17 06:16:35 PM PDT 24 117627926 ps
T2851 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3010354625 Jul 17 06:16:16 PM PDT 24 Jul 17 06:16:19 PM PDT 24 41028087 ps
T2852 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3796061873 Jul 17 06:16:26 PM PDT 24 Jul 17 06:16:30 PM PDT 24 87344703 ps

Test location /workspace/coverage/default/32.usbdev_in_trans.2109006454
Short name T3
Test name
Test status
Simulation time 245614356 ps
CPU time 0.92 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206456 kb
Host smart-ace0eefe-0378-4cd0-a022-e940642a5ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090
06454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2109006454
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_device_address.2311666609
Short name T71
Test name
Test status
Simulation time 11773052857 ps
CPU time 22.15 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:36 PM PDT 24
Peak memory 206576 kb
Host smart-144c0d1e-39a0-4425-b601-3a748395b58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23116
66609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.2311666609
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.585671993
Short name T198
Test name
Test status
Simulation time 44998461 ps
CPU time 0.74 seconds
Started Jul 17 06:21:23 PM PDT 24
Finished Jul 17 06:21:25 PM PDT 24
Peak memory 206300 kb
Host smart-2744e842-fa14-48d1-a7f2-4a90efaebb68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=585671993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.585671993
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.4195786415
Short name T45
Test name
Test status
Simulation time 10391883410 ps
CPU time 89.71 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:53:59 PM PDT 24
Peak memory 206744 kb
Host smart-ba88fa96-9807-419c-80f1-d94143292aff
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4195786415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.4195786415
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.1611367706
Short name T4
Test name
Test status
Simulation time 13031050042 ps
CPU time 112.38 seconds
Started Jul 17 08:01:54 PM PDT 24
Finished Jul 17 08:03:47 PM PDT 24
Peak memory 206700 kb
Host smart-4deb85bc-8fef-449f-87d2-13eed50b54b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16113
67706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1611367706
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2013699227
Short name T186
Test name
Test status
Simulation time 499851793 ps
CPU time 4.17 seconds
Started Jul 17 06:16:20 PM PDT 24
Finished Jul 17 06:16:25 PM PDT 24
Peak memory 206484 kb
Host smart-68759cb7-2fe4-4e88-87e2-5ae4b620b750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2013699227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2013699227
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2611955574
Short name T10
Test name
Test status
Simulation time 13392001800 ps
CPU time 14.02 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:54:27 PM PDT 24
Peak memory 206504 kb
Host smart-f40fe1a1-44e8-4f2e-9e2f-06ff5441415d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2611955574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2611955574
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1909062437
Short name T533
Test name
Test status
Simulation time 156748825 ps
CPU time 0.79 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:55:43 PM PDT 24
Peak memory 206448 kb
Host smart-10626d53-69b5-45a0-b047-84d4d299649b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19090
62437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1909062437
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3652295685
Short name T279
Test name
Test status
Simulation time 86676352 ps
CPU time 0.74 seconds
Started Jul 17 06:22:04 PM PDT 24
Finished Jul 17 06:22:05 PM PDT 24
Peak memory 206308 kb
Host smart-22d93d96-94e6-4d60-b6e2-13feb472c835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3652295685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3652295685
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3415869197
Short name T217
Test name
Test status
Simulation time 301682391 ps
CPU time 3.4 seconds
Started Jul 17 06:16:16 PM PDT 24
Finished Jul 17 06:16:22 PM PDT 24
Peak memory 222396 kb
Host smart-fa0020a9-34b2-4125-ac7e-3a2d918f6fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3415869197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3415869197
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3490206469
Short name T182
Test name
Test status
Simulation time 350994316 ps
CPU time 1.15 seconds
Started Jul 17 08:01:26 PM PDT 24
Finished Jul 17 08:01:33 PM PDT 24
Peak memory 224236 kb
Host smart-ddb44564-bd4b-48c6-943f-4567fbed2da7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3490206469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3490206469
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3667136052
Short name T119
Test name
Test status
Simulation time 194536376 ps
CPU time 0.84 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:55:54 PM PDT 24
Peak memory 206444 kb
Host smart-9cc01bcd-214e-4643-85bb-412c9c15b1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36671
36052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3667136052
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.3767845830
Short name T982
Test name
Test status
Simulation time 263592031 ps
CPU time 1.06 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206452 kb
Host smart-e3374856-0870-4094-abfc-f426477db6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
45830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.3767845830
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2260711223
Short name T25
Test name
Test status
Simulation time 42973934 ps
CPU time 0.71 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:30 PM PDT 24
Peak memory 206444 kb
Host smart-1b4260c5-644d-4e46-ab19-fdf5bde6e6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22607
11223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2260711223
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.259223113
Short name T244
Test name
Test status
Simulation time 190060307 ps
CPU time 0.97 seconds
Started Jul 17 06:20:28 PM PDT 24
Finished Jul 17 06:20:30 PM PDT 24
Peak memory 206408 kb
Host smart-a707c866-5eeb-411f-b768-9018a7e7abbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=259223113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.259223113
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1895909211
Short name T280
Test name
Test status
Simulation time 53114992 ps
CPU time 0.7 seconds
Started Jul 17 06:16:32 PM PDT 24
Finished Jul 17 06:16:34 PM PDT 24
Peak memory 206336 kb
Host smart-eed7716f-e453-4f4c-829a-cd7bb1a5178b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1895909211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1895909211
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2936877195
Short name T81
Test name
Test status
Simulation time 325687403 ps
CPU time 0.93 seconds
Started Jul 17 07:52:29 PM PDT 24
Finished Jul 17 07:52:33 PM PDT 24
Peak memory 206532 kb
Host smart-73eae033-a46c-497d-a8ec-4a5f67258e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29368
77195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.2936877195
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.590236495
Short name T46
Test name
Test status
Simulation time 20160578251 ps
CPU time 20.27 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:50 PM PDT 24
Peak memory 206500 kb
Host smart-b3637531-b4ea-4f36-a1bc-b35649fc2faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59023
6495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.590236495
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2587582424
Short name T59
Test name
Test status
Simulation time 1310626509 ps
CPU time 2.82 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:42 PM PDT 24
Peak memory 206668 kb
Host smart-5c74ba48-e6e5-428d-8e98-7f4424034731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25875
82424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2587582424
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1764537074
Short name T271
Test name
Test status
Simulation time 58461169 ps
CPU time 0.68 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:16 PM PDT 24
Peak memory 206500 kb
Host smart-4e03db3d-9763-4d65-b4ac-653b7655ece1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1764537074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1764537074
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2341719617
Short name T17
Test name
Test status
Simulation time 4074737146 ps
CPU time 29.08 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:03:00 PM PDT 24
Peak memory 206424 kb
Host smart-29cdb7b7-285e-4e1e-b720-91da4369ab51
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2341719617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2341719617
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2255088175
Short name T44
Test name
Test status
Simulation time 139041314 ps
CPU time 0.76 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206460 kb
Host smart-d6739789-3de5-4efd-bd26-fad6a649b1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550
88175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2255088175
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.817737915
Short name T76
Test name
Test status
Simulation time 182216522 ps
CPU time 0.81 seconds
Started Jul 17 07:52:31 PM PDT 24
Finished Jul 17 07:52:34 PM PDT 24
Peak memory 206408 kb
Host smart-b8dba4f3-a256-4fff-be11-bf73b6cf7905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81773
7915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.817737915
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.752000700
Short name T2
Test name
Test status
Simulation time 157842067 ps
CPU time 0.78 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206444 kb
Host smart-92090ce5-4e88-4ea0-9f1e-ae8314ad9cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75200
0700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.752000700
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.792229341
Short name T298
Test name
Test status
Simulation time 764967151 ps
CPU time 5.05 seconds
Started Jul 17 06:16:13 PM PDT 24
Finished Jul 17 06:16:19 PM PDT 24
Peak memory 206500 kb
Host smart-60c25f9d-3011-4921-a982-d7dfb2bd7992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=792229341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.792229341
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.817534053
Short name T73
Test name
Test status
Simulation time 379704518 ps
CPU time 1.2 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:52:12 PM PDT 24
Peak memory 206456 kb
Host smart-fd9a31f2-7863-4eba-8365-2218ce1901e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81753
4053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.817534053
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4117805880
Short name T2768
Test name
Test status
Simulation time 39254140 ps
CPU time 0.69 seconds
Started Jul 17 06:16:31 PM PDT 24
Finished Jul 17 06:16:33 PM PDT 24
Peak memory 206336 kb
Host smart-f94e58a1-c8f7-4f54-b811-a78ae4e22b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4117805880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4117805880
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.654374223
Short name T584
Test name
Test status
Simulation time 37192505 ps
CPU time 0.66 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:55:56 PM PDT 24
Peak memory 206420 kb
Host smart-69061c02-dae9-4d7b-8da2-8c3ec766d82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=654374223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.654374223
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.224044278
Short name T374
Test name
Test status
Simulation time 3469645623 ps
CPU time 5.15 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:56:01 PM PDT 24
Peak memory 206484 kb
Host smart-feccb614-507d-486d-9eb3-ababdda8d3ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=224044278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.224044278
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2696079880
Short name T166
Test name
Test status
Simulation time 13841480491 ps
CPU time 123.2 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:54:55 PM PDT 24
Peak memory 206748 kb
Host smart-50b6f20a-f5d9-4538-8957-3e0a8ee9fd26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2696079880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2696079880
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4098646246
Short name T2783
Test name
Test status
Simulation time 96278207 ps
CPU time 2.46 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:17 PM PDT 24
Peak memory 222676 kb
Host smart-bcc62d7e-01ef-466e-a9b1-eb5966003ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098646246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4098646246
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1657661238
Short name T52
Test name
Test status
Simulation time 402179450 ps
CPU time 1.14 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:54:06 PM PDT 24
Peak memory 206436 kb
Host smart-2df77368-6c07-4199-bcd6-9a537e8fc74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16576
61238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1657661238
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3748698016
Short name T231
Test name
Test status
Simulation time 15016341220 ps
CPU time 33.15 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:43 PM PDT 24
Peak memory 206712 kb
Host smart-b1774852-2093-4a4d-be18-8f7934a7bc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37486
98016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3748698016
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2561392596
Short name T257
Test name
Test status
Simulation time 161940839 ps
CPU time 1.12 seconds
Started Jul 17 06:16:15 PM PDT 24
Finished Jul 17 06:16:18 PM PDT 24
Peak memory 206576 kb
Host smart-1845ccf5-36e1-4df4-9c23-9871c09cdfef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2561392596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2561392596
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.2863366502
Short name T83
Test name
Test status
Simulation time 154382930 ps
CPU time 0.75 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206412 kb
Host smart-1edf1ca9-ee86-4042-80d2-dc7a90814601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28633
66502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.2863366502
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2178043563
Short name T296
Test name
Test status
Simulation time 1035220587 ps
CPU time 5.15 seconds
Started Jul 17 06:16:05 PM PDT 24
Finished Jul 17 06:16:11 PM PDT 24
Peak memory 206572 kb
Host smart-315afce8-72fb-46d3-9262-f6c74e627956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2178043563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2178043563
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.95440248
Short name T196
Test name
Test status
Simulation time 51500964 ps
CPU time 0.7 seconds
Started Jul 17 06:16:04 PM PDT 24
Finished Jul 17 06:16:05 PM PDT 24
Peak memory 206036 kb
Host smart-304b1a42-3987-4ca0-8148-b91130299668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=95440248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.95440248
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.279953208
Short name T293
Test name
Test status
Simulation time 2238328383 ps
CPU time 6.88 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:34 PM PDT 24
Peak memory 206584 kb
Host smart-1ff77df7-a71f-4f8b-8102-f6f150eb4660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=279953208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.279953208
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1393096330
Short name T2309
Test name
Test status
Simulation time 19556347621 ps
CPU time 427.82 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 08:00:32 PM PDT 24
Peak memory 206660 kb
Host smart-aa1ba0af-484c-4f0b-a817-a4ab4855f13e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1393096330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1393096330
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_device_address.4142246734
Short name T164
Test name
Test status
Simulation time 21461666434 ps
CPU time 39.14 seconds
Started Jul 17 08:00:37 PM PDT 24
Finished Jul 17 08:01:22 PM PDT 24
Peak memory 206716 kb
Host smart-39cbd230-830e-4d82-8193-c992eb42097f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41422
46734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.4142246734
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3025085280
Short name T503
Test name
Test status
Simulation time 144961170 ps
CPU time 0.77 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:49 PM PDT 24
Peak memory 206308 kb
Host smart-50bf52f1-a6a0-4a2a-ba54-b71cf6c5f3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30250
85280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3025085280
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.4273816141
Short name T156
Test name
Test status
Simulation time 14312828531 ps
CPU time 288.63 seconds
Started Jul 17 07:52:54 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206756 kb
Host smart-e20cc9ab-1d5c-42ec-b408-a53013fc3057
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4273816141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.4273816141
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2208932521
Short name T609
Test name
Test status
Simulation time 370136474 ps
CPU time 1.97 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 206772 kb
Host smart-8397c730-4571-40d0-887b-aacb2ce1d114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22089
32521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2208932521
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.140470902
Short name T85
Test name
Test status
Simulation time 158925381 ps
CPU time 0.77 seconds
Started Jul 17 07:52:48 PM PDT 24
Finished Jul 17 07:52:50 PM PDT 24
Peak memory 206452 kb
Host smart-1b67081f-ef19-451d-8020-a8bc635a9c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14047
0902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.140470902
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.1249784137
Short name T75
Test name
Test status
Simulation time 7510419471 ps
CPU time 202.34 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:57:38 PM PDT 24
Peak memory 206684 kb
Host smart-c67c5d95-5e2f-45d8-9877-d35ec6659d12
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1249784137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.1249784137
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3784037725
Short name T56
Test name
Test status
Simulation time 165318702 ps
CPU time 0.83 seconds
Started Jul 17 07:52:21 PM PDT 24
Finished Jul 17 07:52:23 PM PDT 24
Peak memory 206460 kb
Host smart-42e9530e-d73e-4b89-ae44-abe806967285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37840
37725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3784037725
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.96992766
Short name T68
Test name
Test status
Simulation time 4166272120 ps
CPU time 9.87 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:17 PM PDT 24
Peak memory 206716 kb
Host smart-7a4e5345-b5cd-410d-aeeb-0ddef976a010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96992
766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.96992766
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2034658891
Short name T69
Test name
Test status
Simulation time 198855728 ps
CPU time 0.84 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:52:21 PM PDT 24
Peak memory 206268 kb
Host smart-26db1b7c-4f8c-45da-a066-ec4828cc1a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
58891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2034658891
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3177329179
Short name T53
Test name
Test status
Simulation time 293471181 ps
CPU time 1.03 seconds
Started Jul 17 07:52:26 PM PDT 24
Finished Jul 17 07:52:29 PM PDT 24
Peak memory 206416 kb
Host smart-353f21ea-5d83-4f8a-ac09-e313e37b33d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31773
29179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3177329179
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2365371758
Short name T79
Test name
Test status
Simulation time 153450237 ps
CPU time 0.75 seconds
Started Jul 17 07:53:19 PM PDT 24
Finished Jul 17 07:53:21 PM PDT 24
Peak memory 206464 kb
Host smart-2d6d2e7c-603d-40b9-9518-eea67f52d0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23653
71758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2365371758
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1794530797
Short name T684
Test name
Test status
Simulation time 53144348 ps
CPU time 0.66 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206436 kb
Host smart-954308ec-00be-4c8b-af27-58e55b8d2f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17945
30797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1794530797
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3751755282
Short name T51
Test name
Test status
Simulation time 161360776 ps
CPU time 0.76 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:52:51 PM PDT 24
Peak memory 206452 kb
Host smart-020352c6-1b6d-4b09-a80f-365d388570ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37517
55282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3751755282
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1764246270
Short name T223
Test name
Test status
Simulation time 237959566 ps
CPU time 3.14 seconds
Started Jul 17 06:16:09 PM PDT 24
Finished Jul 17 06:16:13 PM PDT 24
Peak memory 222224 kb
Host smart-1021c393-92da-45ef-ad9b-958e27ff64f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1764246270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1764246270
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.786501807
Short name T229
Test name
Test status
Simulation time 567338950 ps
CPU time 3.2 seconds
Started Jul 17 06:20:28 PM PDT 24
Finished Jul 17 06:20:32 PM PDT 24
Peak memory 206556 kb
Host smart-d31df927-348d-4d9a-9ce3-fc33cc20a84f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=786501807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.786501807
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2826627267
Short name T776
Test name
Test status
Simulation time 13987648295 ps
CPU time 24.42 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:38 PM PDT 24
Peak memory 206684 kb
Host smart-48617b20-6b94-461e-84a7-0a8420dad096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266
27267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2826627267
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.690915652
Short name T131
Test name
Test status
Simulation time 244729679 ps
CPU time 0.9 seconds
Started Jul 17 07:52:30 PM PDT 24
Finished Jul 17 07:52:33 PM PDT 24
Peak memory 206440 kb
Host smart-12d830e1-a1f9-408d-903d-3025ed98e76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69091
5652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.690915652
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2895014027
Short name T137
Test name
Test status
Simulation time 159929093 ps
CPU time 0.78 seconds
Started Jul 17 07:52:45 PM PDT 24
Finished Jul 17 07:52:47 PM PDT 24
Peak memory 206460 kb
Host smart-f9506663-1df6-440a-ae5c-2aba5e3b6e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28950
14027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2895014027
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3306644541
Short name T114
Test name
Test status
Simulation time 188116596 ps
CPU time 0.85 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:55:44 PM PDT 24
Peak memory 206452 kb
Host smart-eee53632-ad0e-43d0-b4bf-bc251404c847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33066
44541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3306644541
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3967718236
Short name T123
Test name
Test status
Simulation time 203971438 ps
CPU time 0.95 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:57:26 PM PDT 24
Peak memory 206440 kb
Host smart-d1429acf-4ab1-482c-9b87-5f8de6a1df08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39677
18236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3967718236
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4211925918
Short name T1927
Test name
Test status
Simulation time 196048616 ps
CPU time 0.86 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206460 kb
Host smart-7dcae457-02a5-4283-aa95-ce0b50c36174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42119
25918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4211925918
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.600202926
Short name T136
Test name
Test status
Simulation time 197238695 ps
CPU time 0.87 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:37 PM PDT 24
Peak memory 206456 kb
Host smart-896307c1-d62a-41dc-a770-eddce3785406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60020
2926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.600202926
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.522212277
Short name T126
Test name
Test status
Simulation time 227138783 ps
CPU time 0.9 seconds
Started Jul 17 07:57:54 PM PDT 24
Finished Jul 17 07:57:56 PM PDT 24
Peak memory 206460 kb
Host smart-b2d9530b-f728-4e79-99b8-66df6d4c3c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52221
2277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.522212277
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1975054874
Short name T117
Test name
Test status
Simulation time 190566586 ps
CPU time 0.8 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 206448 kb
Host smart-98da39b3-6809-4fdc-83ab-39508449a046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19750
54874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1975054874
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2750806353
Short name T118
Test name
Test status
Simulation time 215223465 ps
CPU time 0.83 seconds
Started Jul 17 07:57:57 PM PDT 24
Finished Jul 17 07:57:59 PM PDT 24
Peak memory 206540 kb
Host smart-b73ee454-e73e-4e75-b71c-3993896865e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27508
06353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2750806353
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2080861296
Short name T1739
Test name
Test status
Simulation time 186601155 ps
CPU time 0.93 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206448 kb
Host smart-68c76d7f-1f82-4213-b6f9-f36969d0951c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
61296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2080861296
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1344689132
Short name T127
Test name
Test status
Simulation time 196756814 ps
CPU time 0.82 seconds
Started Jul 17 08:01:57 PM PDT 24
Finished Jul 17 08:02:00 PM PDT 24
Peak memory 206456 kb
Host smart-c228cf95-35b0-4414-bc80-699ffa5cd63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13446
89132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1344689132
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2268521763
Short name T252
Test name
Test status
Simulation time 300154002 ps
CPU time 3.58 seconds
Started Jul 17 06:16:03 PM PDT 24
Finished Jul 17 06:16:08 PM PDT 24
Peak memory 206388 kb
Host smart-c3cc62fc-50a6-413b-a543-2e27b8e2e322
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2268521763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2268521763
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.173006253
Short name T2814
Test name
Test status
Simulation time 239032814 ps
CPU time 3.82 seconds
Started Jul 17 06:16:03 PM PDT 24
Finished Jul 17 06:16:08 PM PDT 24
Peak memory 206452 kb
Host smart-f417cdfc-e89d-48eb-91d8-5eed375ec8a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=173006253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.173006253
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3514639528
Short name T226
Test name
Test status
Simulation time 118050368 ps
CPU time 1.45 seconds
Started Jul 17 06:16:01 PM PDT 24
Finished Jul 17 06:16:04 PM PDT 24
Peak memory 214752 kb
Host smart-2ff48c95-a67e-421c-9e4b-5b6973dd4e45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514639528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3514639528
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2952841559
Short name T2823
Test name
Test status
Simulation time 83236140 ps
CPU time 1.05 seconds
Started Jul 17 06:16:00 PM PDT 24
Finished Jul 17 06:16:03 PM PDT 24
Peak memory 206472 kb
Host smart-c5153a4e-605c-40b8-8f8e-4a1b839696a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2952841559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2952841559
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.510819224
Short name T2777
Test name
Test status
Simulation time 40461619 ps
CPU time 0.69 seconds
Started Jul 17 06:16:02 PM PDT 24
Finished Jul 17 06:16:04 PM PDT 24
Peak memory 206332 kb
Host smart-c4bc396d-377f-43b5-b3d2-9350a5c26fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=510819224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.510819224
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2913209544
Short name T253
Test name
Test status
Simulation time 209114243 ps
CPU time 2.67 seconds
Started Jul 17 06:16:01 PM PDT 24
Finished Jul 17 06:16:05 PM PDT 24
Peak memory 214732 kb
Host smart-086c5455-b4b0-45dd-a7e3-151f2f47b2d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2913209544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2913209544
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3093221381
Short name T2800
Test name
Test status
Simulation time 629621845 ps
CPU time 4.39 seconds
Started Jul 17 06:16:07 PM PDT 24
Finished Jul 17 06:16:12 PM PDT 24
Peak memory 206568 kb
Host smart-961f8419-3bf8-4ec5-bd98-acaf272af8af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3093221381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3093221381
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.295752947
Short name T2761
Test name
Test status
Simulation time 78899273 ps
CPU time 1.21 seconds
Started Jul 17 06:16:03 PM PDT 24
Finished Jul 17 06:16:06 PM PDT 24
Peak memory 206548 kb
Host smart-31a857c5-3a41-4811-80a5-09c6cd125bac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=295752947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.295752947
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3026813157
Short name T2755
Test name
Test status
Simulation time 83549242 ps
CPU time 2.01 seconds
Started Jul 17 06:16:02 PM PDT 24
Finished Jul 17 06:16:06 PM PDT 24
Peak memory 206372 kb
Host smart-4c478335-bb30-47d4-814f-ab4b503fb156
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3026813157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3026813157
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2100717068
Short name T247
Test name
Test status
Simulation time 675680200 ps
CPU time 7.75 seconds
Started Jul 17 06:16:01 PM PDT 24
Finished Jul 17 06:16:10 PM PDT 24
Peak memory 206380 kb
Host smart-998dd68d-0c73-4055-b67e-80d7988e0690
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2100717068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2100717068
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1233472578
Short name T256
Test name
Test status
Simulation time 110303076 ps
CPU time 0.84 seconds
Started Jul 17 06:16:04 PM PDT 24
Finished Jul 17 06:16:06 PM PDT 24
Peak memory 205976 kb
Host smart-0a2805cd-7c76-4d12-a336-e7adca205cc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1233472578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1233472578
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.24619750
Short name T230
Test name
Test status
Simulation time 115436197 ps
CPU time 1.19 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 214792 kb
Host smart-4e070131-f7ca-4b09-985c-c1088cddfc5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24619750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_
csr_mem_rw_with_rand_reset.24619750
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1477619826
Short name T267
Test name
Test status
Simulation time 81194243 ps
CPU time 1.02 seconds
Started Jul 17 06:16:09 PM PDT 24
Finished Jul 17 06:16:11 PM PDT 24
Peak memory 206468 kb
Host smart-c1027379-61d2-46e8-9b8f-4bd477b27b22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1477619826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1477619826
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1360841786
Short name T250
Test name
Test status
Simulation time 77176004 ps
CPU time 2.23 seconds
Started Jul 17 06:16:00 PM PDT 24
Finished Jul 17 06:16:04 PM PDT 24
Peak memory 214676 kb
Host smart-81b2bedd-f57f-4a52-8623-d608ca4c73d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1360841786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1360841786
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2938148571
Short name T2796
Test name
Test status
Simulation time 295105786 ps
CPU time 2.7 seconds
Started Jul 17 06:16:00 PM PDT 24
Finished Jul 17 06:16:04 PM PDT 24
Peak memory 206424 kb
Host smart-8a70b502-2ebc-4165-9540-5dc5e03986b9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2938148571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2938148571
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2972422830
Short name T2784
Test name
Test status
Simulation time 135950026 ps
CPU time 1.07 seconds
Started Jul 17 06:15:58 PM PDT 24
Finished Jul 17 06:16:00 PM PDT 24
Peak memory 206536 kb
Host smart-073f2a8b-075c-4e5a-8aeb-277e20ed9231
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2972422830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2972422830
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1704307591
Short name T266
Test name
Test status
Simulation time 151594668 ps
CPU time 1.34 seconds
Started Jul 17 06:16:20 PM PDT 24
Finished Jul 17 06:16:23 PM PDT 24
Peak memory 214708 kb
Host smart-683ddb88-2e9a-421d-91b7-3c92e13517b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704307591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1704307591
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3241552515
Short name T2829
Test name
Test status
Simulation time 54183022 ps
CPU time 1.02 seconds
Started Jul 17 06:16:15 PM PDT 24
Finished Jul 17 06:16:17 PM PDT 24
Peak memory 206520 kb
Host smart-e68e18e8-59ce-4f13-8414-0e79c31ad3f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3241552515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3241552515
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3010354625
Short name T2851
Test name
Test status
Simulation time 41028087 ps
CPU time 0.68 seconds
Started Jul 17 06:16:16 PM PDT 24
Finished Jul 17 06:16:19 PM PDT 24
Peak memory 206340 kb
Host smart-490ab12e-e118-4dc7-bada-8ead1b0f911a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3010354625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3010354625
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4221514457
Short name T216
Test name
Test status
Simulation time 118136519 ps
CPU time 3.21 seconds
Started Jul 17 06:16:13 PM PDT 24
Finished Jul 17 06:16:18 PM PDT 24
Peak memory 214696 kb
Host smart-01334379-c19a-4246-80ea-07f3ba0dbc9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4221514457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4221514457
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1984688183
Short name T2775
Test name
Test status
Simulation time 1869926120 ps
CPU time 5.48 seconds
Started Jul 17 06:16:16 PM PDT 24
Finished Jul 17 06:16:24 PM PDT 24
Peak memory 206532 kb
Host smart-9a9b14b6-3a90-4a77-8ba9-7a38f5ff03ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1984688183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1984688183
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2838246823
Short name T2798
Test name
Test status
Simulation time 90233357 ps
CPU time 1.23 seconds
Started Jul 17 06:16:18 PM PDT 24
Finished Jul 17 06:16:21 PM PDT 24
Peak memory 214800 kb
Host smart-1481347f-dfa6-430e-8a70-ca06fc820752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838246823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2838246823
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2234803493
Short name T2804
Test name
Test status
Simulation time 49117962 ps
CPU time 0.81 seconds
Started Jul 17 06:16:22 PM PDT 24
Finished Jul 17 06:16:23 PM PDT 24
Peak memory 206404 kb
Host smart-50732be0-f3c9-4f23-b83a-f7196a8b420b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2234803493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2234803493
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1252883038
Short name T197
Test name
Test status
Simulation time 42640390 ps
CPU time 0.7 seconds
Started Jul 17 06:16:16 PM PDT 24
Finished Jul 17 06:16:19 PM PDT 24
Peak memory 206352 kb
Host smart-d087e506-2c78-4b64-9d95-a5d2bcebe99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1252883038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1252883038
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2081565175
Short name T190
Test name
Test status
Simulation time 148515098 ps
CPU time 1.51 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:17 PM PDT 24
Peak memory 206572 kb
Host smart-23f704eb-f352-4476-8353-a18c6237f76b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2081565175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2081565175
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.613237919
Short name T2828
Test name
Test status
Simulation time 97404881 ps
CPU time 2.63 seconds
Started Jul 17 06:16:20 PM PDT 24
Finished Jul 17 06:16:24 PM PDT 24
Peak memory 222176 kb
Host smart-15006e51-10b2-42cd-bc73-f872f5000a51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=613237919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.613237919
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2611656819
Short name T270
Test name
Test status
Simulation time 965217623 ps
CPU time 3.77 seconds
Started Jul 17 06:16:18 PM PDT 24
Finished Jul 17 06:16:23 PM PDT 24
Peak memory 206484 kb
Host smart-ff2e2063-ff46-4526-ba77-7b6377bac610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2611656819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2611656819
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4013171222
Short name T2820
Test name
Test status
Simulation time 116619383 ps
CPU time 2.09 seconds
Started Jul 17 06:16:18 PM PDT 24
Finished Jul 17 06:16:21 PM PDT 24
Peak memory 214804 kb
Host smart-b08e1c2c-ad3c-4645-ba33-432bce7c030e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013171222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.4013171222
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3131354299
Short name T2806
Test name
Test status
Simulation time 65482971 ps
CPU time 0.87 seconds
Started Jul 17 06:16:17 PM PDT 24
Finished Jul 17 06:16:20 PM PDT 24
Peak memory 206376 kb
Host smart-28c00a16-6051-4a09-8270-e71f542666c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3131354299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3131354299
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.50746390
Short name T2822
Test name
Test status
Simulation time 118508184 ps
CPU time 0.8 seconds
Started Jul 17 06:16:15 PM PDT 24
Finished Jul 17 06:16:18 PM PDT 24
Peak memory 206352 kb
Host smart-9b3fc652-fed4-4363-88fa-d69dcc3e1e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=50746390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.50746390
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4088826653
Short name T2834
Test name
Test status
Simulation time 106923959 ps
CPU time 1.17 seconds
Started Jul 17 06:16:17 PM PDT 24
Finished Jul 17 06:16:20 PM PDT 24
Peak memory 206536 kb
Host smart-8f94c630-97bb-4218-b090-dd002ba213fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4088826653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.4088826653
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1860302108
Short name T2833
Test name
Test status
Simulation time 238048411 ps
CPU time 2.86 seconds
Started Jul 17 06:16:21 PM PDT 24
Finished Jul 17 06:16:25 PM PDT 24
Peak memory 222116 kb
Host smart-5afe4c15-0503-4492-a26c-ed367cd7f820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1860302108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1860302108
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2036636297
Short name T2776
Test name
Test status
Simulation time 782127583 ps
CPU time 4.54 seconds
Started Jul 17 06:16:20 PM PDT 24
Finished Jul 17 06:16:25 PM PDT 24
Peak memory 206532 kb
Host smart-b68c51ce-c462-45f1-bea3-c4e71cb6b983
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2036636297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2036636297
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2586677836
Short name T269
Test name
Test status
Simulation time 144858346 ps
CPU time 1.39 seconds
Started Jul 17 06:16:21 PM PDT 24
Finished Jul 17 06:16:23 PM PDT 24
Peak memory 214792 kb
Host smart-89083a81-e01e-48e6-8aba-9f415782ed22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586677836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2586677836
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1287174926
Short name T2818
Test name
Test status
Simulation time 70299593 ps
CPU time 0.98 seconds
Started Jul 17 06:21:22 PM PDT 24
Finished Jul 17 06:21:23 PM PDT 24
Peak memory 206548 kb
Host smart-0653dddc-616c-4419-9973-26cf7560f9c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1287174926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1287174926
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.683347778
Short name T2794
Test name
Test status
Simulation time 40515027 ps
CPU time 0.72 seconds
Started Jul 17 06:16:13 PM PDT 24
Finished Jul 17 06:16:14 PM PDT 24
Peak memory 206296 kb
Host smart-ae56979f-8b43-4df8-b30e-33d298e6064c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=683347778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.683347778
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.322640578
Short name T2764
Test name
Test status
Simulation time 140455387 ps
CPU time 1.9 seconds
Started Jul 17 06:16:18 PM PDT 24
Finished Jul 17 06:16:21 PM PDT 24
Peak memory 206548 kb
Host smart-f73dc726-7665-44a2-b7fc-d26e197f6e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=322640578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.322640578
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1204280510
Short name T2847
Test name
Test status
Simulation time 285887814 ps
CPU time 2.79 seconds
Started Jul 17 06:16:15 PM PDT 24
Finished Jul 17 06:16:20 PM PDT 24
Peak memory 222304 kb
Host smart-8df2a625-5f25-4291-b4c7-49c4e03c2efc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1204280510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1204280510
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3467611193
Short name T2816
Test name
Test status
Simulation time 141391127 ps
CPU time 1.66 seconds
Started Jul 17 06:16:27 PM PDT 24
Finished Jul 17 06:16:29 PM PDT 24
Peak memory 214760 kb
Host smart-d3e8f222-3f1a-4b2f-9e4d-7ef0f0764ce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467611193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3467611193
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2101843817
Short name T2819
Test name
Test status
Simulation time 66361729 ps
CPU time 1 seconds
Started Jul 17 06:16:27 PM PDT 24
Finished Jul 17 06:16:29 PM PDT 24
Peak memory 206520 kb
Host smart-399b6e24-5ab3-419b-837f-f140ce995838
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2101843817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2101843817
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3201022225
Short name T2811
Test name
Test status
Simulation time 38225190 ps
CPU time 0.69 seconds
Started Jul 17 06:16:24 PM PDT 24
Finished Jul 17 06:16:26 PM PDT 24
Peak memory 206344 kb
Host smart-c2f41d03-0ccd-4289-9434-8fc4dba17ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3201022225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3201022225
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.200996952
Short name T2799
Test name
Test status
Simulation time 173470511 ps
CPU time 1.62 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:34 PM PDT 24
Peak memory 205832 kb
Host smart-7ab13495-dd62-4014-8f2a-7e9139eb05f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=200996952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.200996952
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1924214193
Short name T2838
Test name
Test status
Simulation time 309534709 ps
CPU time 3.5 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:18 PM PDT 24
Peak memory 222792 kb
Host smart-e62c36c3-c276-4896-8c10-d1b8e719edae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1924214193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1924214193
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1195328180
Short name T2788
Test name
Test status
Simulation time 155758298 ps
CPU time 1.97 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:33 PM PDT 24
Peak memory 222956 kb
Host smart-aa823c4e-b7fe-449c-97d3-169bf8f280d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195328180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1195328180
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2394182116
Short name T2757
Test name
Test status
Simulation time 43149450 ps
CPU time 0.81 seconds
Started Jul 17 06:16:24 PM PDT 24
Finished Jul 17 06:16:26 PM PDT 24
Peak memory 206396 kb
Host smart-bafe3cac-0bb5-43b5-9f00-a1595d58c408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2394182116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2394182116
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.615849622
Short name T286
Test name
Test status
Simulation time 62619642 ps
CPU time 0.67 seconds
Started Jul 17 06:16:27 PM PDT 24
Finished Jul 17 06:16:29 PM PDT 24
Peak memory 206380 kb
Host smart-e3a27d54-c9fe-4f52-9084-cea2f18c7e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=615849622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.615849622
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.403308308
Short name T2821
Test name
Test status
Simulation time 62996039 ps
CPU time 1.08 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:28 PM PDT 24
Peak memory 206544 kb
Host smart-13dc66c0-785e-457b-a7f6-bd5b15a69a0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=403308308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.403308308
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1499633346
Short name T2850
Test name
Test status
Simulation time 117627926 ps
CPU time 1.41 seconds
Started Jul 17 06:16:32 PM PDT 24
Finished Jul 17 06:16:35 PM PDT 24
Peak memory 215808 kb
Host smart-94c58ff7-094f-4deb-8494-bf9dfadf4af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1499633346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1499633346
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2855463596
Short name T220
Test name
Test status
Simulation time 884905026 ps
CPU time 5.79 seconds
Started Jul 17 06:21:23 PM PDT 24
Finished Jul 17 06:21:30 PM PDT 24
Peak memory 206488 kb
Host smart-74bd7b99-db4e-447e-8f3b-ca97d6f7569d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2855463596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2855463596
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3251293443
Short name T2762
Test name
Test status
Simulation time 107139492 ps
CPU time 2.22 seconds
Started Jul 17 06:16:25 PM PDT 24
Finished Jul 17 06:16:27 PM PDT 24
Peak memory 214796 kb
Host smart-dbb3ac7c-d0bf-4bc6-b13c-cb96fd999b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251293443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3251293443
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.74732364
Short name T2810
Test name
Test status
Simulation time 53151431 ps
CPU time 0.9 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:27 PM PDT 24
Peak memory 206380 kb
Host smart-675ff7d4-b472-4dff-988f-fbe27f6ddf85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=74732364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.74732364
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.931925731
Short name T195
Test name
Test status
Simulation time 40198292 ps
CPU time 0.68 seconds
Started Jul 17 06:16:27 PM PDT 24
Finished Jul 17 06:16:29 PM PDT 24
Peak memory 206336 kb
Host smart-de3de740-a551-463a-999b-5243c3c82bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=931925731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.931925731
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.817556227
Short name T2846
Test name
Test status
Simulation time 106768567 ps
CPU time 1.17 seconds
Started Jul 17 06:16:33 PM PDT 24
Finished Jul 17 06:16:36 PM PDT 24
Peak memory 206612 kb
Host smart-f34bc454-3e31-4de9-8dae-41beb5079f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=817556227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.817556227
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.374434944
Short name T2795
Test name
Test status
Simulation time 119235417 ps
CPU time 1.46 seconds
Started Jul 17 06:18:13 PM PDT 24
Finished Jul 17 06:18:16 PM PDT 24
Peak memory 206588 kb
Host smart-f6199074-49e1-423c-b839-50d5379c117b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=374434944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.374434944
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2184147815
Short name T295
Test name
Test status
Simulation time 439089078 ps
CPU time 3.16 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:35 PM PDT 24
Peak memory 206452 kb
Host smart-5342646d-ef7f-492f-b203-520d7cb4785f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2184147815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2184147815
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3935972776
Short name T2767
Test name
Test status
Simulation time 99153573 ps
CPU time 2.05 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 214792 kb
Host smart-5d257798-92e7-4f15-97f0-7cbbbaea428c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935972776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3935972776
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.635388418
Short name T2813
Test name
Test status
Simulation time 46499373 ps
CPU time 0.84 seconds
Started Jul 17 06:16:28 PM PDT 24
Finished Jul 17 06:16:30 PM PDT 24
Peak memory 206396 kb
Host smart-762cb21e-3098-4cba-88ae-a81e8377fa15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=635388418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.635388418
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4108370230
Short name T284
Test name
Test status
Simulation time 41528470 ps
CPU time 0.72 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 206340 kb
Host smart-ee9ee3c5-486e-4d08-9277-9f189e061d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4108370230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.4108370230
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3674166185
Short name T260
Test name
Test status
Simulation time 103608602 ps
CPU time 1.62 seconds
Started Jul 17 06:16:32 PM PDT 24
Finished Jul 17 06:16:35 PM PDT 24
Peak memory 206600 kb
Host smart-c702a684-805b-4ad4-b7b7-951645fc82ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3674166185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3674166185
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3704325147
Short name T2802
Test name
Test status
Simulation time 79590768 ps
CPU time 1.32 seconds
Started Jul 17 06:16:28 PM PDT 24
Finished Jul 17 06:16:31 PM PDT 24
Peak memory 206644 kb
Host smart-6b47daf5-1ddb-4a13-98fc-2f662e2c87e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3704325147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3704325147
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2920556627
Short name T268
Test name
Test status
Simulation time 1212760769 ps
CPU time 4.18 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:31 PM PDT 24
Peak memory 206620 kb
Host smart-1db9f161-c746-4641-a7dd-a6cfcd076d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2920556627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2920556627
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.577166072
Short name T185
Test name
Test status
Simulation time 94350405 ps
CPU time 1.22 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 214788 kb
Host smart-892ef3f7-6496-49af-999b-ba1b54667d58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577166072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.577166072
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1367283397
Short name T2763
Test name
Test status
Simulation time 129192567 ps
CPU time 1.12 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:33 PM PDT 24
Peak memory 205812 kb
Host smart-a96d9401-aac2-4cf7-a5f3-589c81d71aa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1367283397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1367283397
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2418795119
Short name T2801
Test name
Test status
Simulation time 91328547 ps
CPU time 1.16 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:33 PM PDT 24
Peak memory 206492 kb
Host smart-11ecafb1-5556-4f80-aaae-b3ed8c2a439d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2418795119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2418795119
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3796061873
Short name T2852
Test name
Test status
Simulation time 87344703 ps
CPU time 2.3 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:30 PM PDT 24
Peak memory 222492 kb
Host smart-7f80e8a2-2bf8-452f-820d-d32d28ad8918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3796061873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3796061873
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2095012885
Short name T299
Test name
Test status
Simulation time 779050369 ps
CPU time 4.88 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:37 PM PDT 24
Peak memory 206500 kb
Host smart-831715f5-07be-43e6-acf5-ce1cfa9a590c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2095012885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2095012885
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.85846851
Short name T212
Test name
Test status
Simulation time 155893210 ps
CPU time 1.78 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:29 PM PDT 24
Peak memory 214748 kb
Host smart-5f9fb09d-b259-4a7b-b235-c3928904023b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85846851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev
_csr_mem_rw_with_rand_reset.85846851
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2013286922
Short name T2807
Test name
Test status
Simulation time 89033790 ps
CPU time 1.09 seconds
Started Jul 17 06:16:27 PM PDT 24
Finished Jul 17 06:16:30 PM PDT 24
Peak memory 206464 kb
Host smart-bcadfaf4-8bdc-444d-8853-471f025c9923
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2013286922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2013286922
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3935313430
Short name T2849
Test name
Test status
Simulation time 165256391 ps
CPU time 1.63 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:33 PM PDT 24
Peak memory 206600 kb
Host smart-ee47c7b3-3aed-4077-aaec-ab62935ae2fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3935313430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3935313430
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3043383925
Short name T2812
Test name
Test status
Simulation time 224860327 ps
CPU time 2.92 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:30 PM PDT 24
Peak memory 214760 kb
Host smart-c448f343-2de2-4512-a2c5-9e3a34b24596
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3043383925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3043383925
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3078238734
Short name T251
Test name
Test status
Simulation time 391355961 ps
CPU time 3.72 seconds
Started Jul 17 06:16:02 PM PDT 24
Finished Jul 17 06:16:07 PM PDT 24
Peak memory 206372 kb
Host smart-142d8c40-9433-4124-8349-d4de96976b68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3078238734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3078238734
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1841054391
Short name T2815
Test name
Test status
Simulation time 1809698600 ps
CPU time 6.99 seconds
Started Jul 17 06:16:02 PM PDT 24
Finished Jul 17 06:16:11 PM PDT 24
Peak memory 206360 kb
Host smart-aacce192-ade6-4cf4-9830-83a27fdc3fe3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1841054391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1841054391
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2661908691
Short name T2837
Test name
Test status
Simulation time 72995515 ps
CPU time 0.85 seconds
Started Jul 17 06:15:59 PM PDT 24
Finished Jul 17 06:16:01 PM PDT 24
Peak memory 206308 kb
Host smart-d3c237ff-4e5d-4719-889e-d562a15f451e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2661908691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2661908691
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3300735529
Short name T2771
Test name
Test status
Simulation time 128987563 ps
CPU time 2.39 seconds
Started Jul 17 06:16:02 PM PDT 24
Finished Jul 17 06:16:06 PM PDT 24
Peak memory 219344 kb
Host smart-a55c765c-bbc9-44ef-b58c-44183685a539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300735529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3300735529
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2601931192
Short name T246
Test name
Test status
Simulation time 46357153 ps
CPU time 0.9 seconds
Started Jul 17 06:16:01 PM PDT 24
Finished Jul 17 06:16:03 PM PDT 24
Peak memory 206384 kb
Host smart-5922728a-2898-4215-b7ac-49f25367245f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2601931192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2601931192
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4228833164
Short name T2836
Test name
Test status
Simulation time 112506695 ps
CPU time 1.47 seconds
Started Jul 17 06:16:00 PM PDT 24
Finished Jul 17 06:16:02 PM PDT 24
Peak memory 222884 kb
Host smart-9e90ddfc-c094-4402-a351-067640518515
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4228833164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4228833164
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1127320277
Short name T2773
Test name
Test status
Simulation time 102489051 ps
CPU time 2.49 seconds
Started Jul 17 06:16:00 PM PDT 24
Finished Jul 17 06:16:05 PM PDT 24
Peak memory 206440 kb
Host smart-4007788f-5f8f-48d5-be25-15d8164bd379
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1127320277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1127320277
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1971629122
Short name T2841
Test name
Test status
Simulation time 109761078 ps
CPU time 1.6 seconds
Started Jul 17 06:16:01 PM PDT 24
Finished Jul 17 06:16:05 PM PDT 24
Peak memory 206576 kb
Host smart-cece2be1-be10-4539-a283-678b4fe73f54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1971629122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1971629122
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.288919358
Short name T2848
Test name
Test status
Simulation time 145040485 ps
CPU time 1.63 seconds
Started Jul 17 06:16:08 PM PDT 24
Finished Jul 17 06:16:10 PM PDT 24
Peak memory 206632 kb
Host smart-1e89db69-9a03-4504-9a09-0c58c69394d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=288919358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.288919358
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1066893558
Short name T297
Test name
Test status
Simulation time 2174875726 ps
CPU time 4.04 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:19 PM PDT 24
Peak memory 206668 kb
Host smart-6842c47a-6146-4b58-a8a4-010ad8367115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1066893558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1066893558
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2952455826
Short name T275
Test name
Test status
Simulation time 45412732 ps
CPU time 0.66 seconds
Started Jul 17 06:16:47 PM PDT 24
Finished Jul 17 06:16:48 PM PDT 24
Peak memory 206356 kb
Host smart-7e4fd7de-f63a-4194-a5d7-b6246c5ec2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2952455826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2952455826
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1374923048
Short name T273
Test name
Test status
Simulation time 45518529 ps
CPU time 0.68 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:27 PM PDT 24
Peak memory 206344 kb
Host smart-d29bb47f-401f-44ce-9188-6f3b4c0b009f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1374923048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1374923048
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4180162084
Short name T281
Test name
Test status
Simulation time 43904340 ps
CPU time 0.66 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:31 PM PDT 24
Peak memory 206376 kb
Host smart-c2d4bfe2-a0f5-4f44-b35c-6cd7471480ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4180162084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.4180162084
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2863898307
Short name T2826
Test name
Test status
Simulation time 49310996 ps
CPU time 0.75 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:33 PM PDT 24
Peak memory 206324 kb
Host smart-8b77217a-104c-45da-8537-98d2e3435c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2863898307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2863898307
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3742956983
Short name T2765
Test name
Test status
Simulation time 39413150 ps
CPU time 0.71 seconds
Started Jul 17 06:16:27 PM PDT 24
Finished Jul 17 06:16:29 PM PDT 24
Peak memory 206352 kb
Host smart-a88efdc6-ea63-4727-905d-e97022510a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3742956983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3742956983
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3592950386
Short name T290
Test name
Test status
Simulation time 38691588 ps
CPU time 0.7 seconds
Started Jul 17 06:16:28 PM PDT 24
Finished Jul 17 06:16:30 PM PDT 24
Peak memory 206352 kb
Host smart-d1d17af3-610f-49f1-8321-2e0a522dd7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3592950386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3592950386
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.389114910
Short name T2766
Test name
Test status
Simulation time 81221519 ps
CPU time 0.72 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 206336 kb
Host smart-dd901582-4686-4ff5-a787-2531912217c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=389114910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.389114910
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.574905363
Short name T272
Test name
Test status
Simulation time 41882614 ps
CPU time 0.73 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:33 PM PDT 24
Peak memory 206340 kb
Host smart-9747f3c3-06fe-47e3-a13e-fdb773747663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=574905363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.574905363
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1909608726
Short name T2827
Test name
Test status
Simulation time 71564190 ps
CPU time 0.7 seconds
Started Jul 17 06:16:27 PM PDT 24
Finished Jul 17 06:16:29 PM PDT 24
Peak memory 206352 kb
Host smart-c835a850-71f0-44bf-8f87-e5f3da414171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1909608726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1909608726
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3651685361
Short name T2780
Test name
Test status
Simulation time 298853970 ps
CPU time 3.61 seconds
Started Jul 17 06:16:59 PM PDT 24
Finished Jul 17 06:17:03 PM PDT 24
Peak memory 206408 kb
Host smart-9396856d-d85d-4ed9-a490-dccdf7d8f5ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3651685361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3651685361
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3914832628
Short name T255
Test name
Test status
Simulation time 833434459 ps
CPU time 9.02 seconds
Started Jul 17 06:16:05 PM PDT 24
Finished Jul 17 06:16:14 PM PDT 24
Peak memory 206404 kb
Host smart-f781806b-06b8-4e5c-a8b2-13641fc07c03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3914832628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3914832628
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3501080450
Short name T254
Test name
Test status
Simulation time 64675136 ps
CPU time 0.91 seconds
Started Jul 17 06:16:07 PM PDT 24
Finished Jul 17 06:16:08 PM PDT 24
Peak memory 206408 kb
Host smart-ca2077b0-8bfd-49f7-a181-296887d96aca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3501080450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3501080450
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3896803232
Short name T2817
Test name
Test status
Simulation time 97033308 ps
CPU time 1.42 seconds
Started Jul 17 06:16:02 PM PDT 24
Finished Jul 17 06:16:05 PM PDT 24
Peak memory 214776 kb
Host smart-366c9b7b-ea12-456e-aa86-8e86142bdd2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896803232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3896803232
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.37645152
Short name T2825
Test name
Test status
Simulation time 53516705 ps
CPU time 0.9 seconds
Started Jul 17 06:16:00 PM PDT 24
Finished Jul 17 06:16:01 PM PDT 24
Peak memory 206492 kb
Host smart-0bf30177-53e4-46bf-b5dd-a591e8ab690b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=37645152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.37645152
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1506321994
Short name T2793
Test name
Test status
Simulation time 32123998 ps
CPU time 0.65 seconds
Started Jul 17 06:16:00 PM PDT 24
Finished Jul 17 06:16:02 PM PDT 24
Peak memory 206372 kb
Host smart-318017a2-a2c5-4a3f-a61a-11ffa7c3b034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1506321994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1506321994
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4284382759
Short name T2843
Test name
Test status
Simulation time 96744661 ps
CPU time 1.46 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 214656 kb
Host smart-3f33faab-8665-4316-8b55-ff3453a5af8e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4284382759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4284382759
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2438524772
Short name T2789
Test name
Test status
Simulation time 496178412 ps
CPU time 4.69 seconds
Started Jul 17 06:16:01 PM PDT 24
Finished Jul 17 06:16:08 PM PDT 24
Peak memory 206412 kb
Host smart-eace0631-05e0-4a77-ba14-79eae3dba9ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2438524772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2438524772
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1276028655
Short name T261
Test name
Test status
Simulation time 121708667 ps
CPU time 1.22 seconds
Started Jul 17 06:15:56 PM PDT 24
Finished Jul 17 06:15:58 PM PDT 24
Peak memory 206564 kb
Host smart-01743508-6104-4d06-a795-fc1f61de422e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1276028655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1276028655
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3556660768
Short name T2782
Test name
Test status
Simulation time 508121936 ps
CPU time 3.26 seconds
Started Jul 17 06:16:01 PM PDT 24
Finished Jul 17 06:16:06 PM PDT 24
Peak memory 206556 kb
Host smart-516ac500-6550-4340-91c3-dc3da1594e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3556660768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3556660768
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2019280588
Short name T2803
Test name
Test status
Simulation time 53154192 ps
CPU time 0.75 seconds
Started Jul 17 06:16:32 PM PDT 24
Finished Jul 17 06:16:35 PM PDT 24
Peak memory 206328 kb
Host smart-7c523030-990c-4b69-a94f-2f84e4fc1f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2019280588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2019280588
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.102996454
Short name T2756
Test name
Test status
Simulation time 78840726 ps
CPU time 0.73 seconds
Started Jul 17 06:16:33 PM PDT 24
Finished Jul 17 06:16:35 PM PDT 24
Peak memory 206252 kb
Host smart-217ee44a-844a-40ae-99b6-093dbc94b497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=102996454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.102996454
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2217523039
Short name T2805
Test name
Test status
Simulation time 60701545 ps
CPU time 0.72 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:28 PM PDT 24
Peak memory 206336 kb
Host smart-4e7f9899-75e2-4e42-831b-fd5ce7b9fafe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2217523039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2217523039
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.490863981
Short name T276
Test name
Test status
Simulation time 64611448 ps
CPU time 0.66 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 206344 kb
Host smart-89a53769-0e71-41e3-9bb0-7f8fc28ca8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=490863981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.490863981
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3188622153
Short name T2845
Test name
Test status
Simulation time 32418021 ps
CPU time 0.7 seconds
Started Jul 17 06:16:35 PM PDT 24
Finished Jul 17 06:16:36 PM PDT 24
Peak memory 206336 kb
Host smart-11a64ca0-8833-431a-a7ef-943a96bf8fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3188622153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3188622153
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.164571482
Short name T287
Test name
Test status
Simulation time 42823697 ps
CPU time 0.68 seconds
Started Jul 17 06:21:22 PM PDT 24
Finished Jul 17 06:21:24 PM PDT 24
Peak memory 206352 kb
Host smart-8fc938f3-a298-4492-97e9-20607fc77c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=164571482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.164571482
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3538621457
Short name T2832
Test name
Test status
Simulation time 58780413 ps
CPU time 0.66 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:31 PM PDT 24
Peak memory 206352 kb
Host smart-2d5b5ced-8f3c-449b-813d-2e1d3e426367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3538621457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3538621457
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2276519629
Short name T2785
Test name
Test status
Simulation time 57735636 ps
CPU time 0.67 seconds
Started Jul 17 06:16:33 PM PDT 24
Finished Jul 17 06:16:35 PM PDT 24
Peak memory 206228 kb
Host smart-56a9b2ce-9a82-4aa6-96e4-8f5d9aa37fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2276519629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2276519629
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3738070890
Short name T2760
Test name
Test status
Simulation time 42882517 ps
CPU time 0.68 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 206352 kb
Host smart-77be101d-e22a-400b-8f94-00fe900ceb84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3738070890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3738070890
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3896822364
Short name T2844
Test name
Test status
Simulation time 127770516 ps
CPU time 3.2 seconds
Started Jul 17 06:16:03 PM PDT 24
Finished Jul 17 06:16:07 PM PDT 24
Peak memory 206408 kb
Host smart-6b9d404b-5316-4c5c-b27e-af77c08a8605
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3896822364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3896822364
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2929509137
Short name T2842
Test name
Test status
Simulation time 187035425 ps
CPU time 3.72 seconds
Started Jul 17 06:16:15 PM PDT 24
Finished Jul 17 06:16:21 PM PDT 24
Peak memory 206556 kb
Host smart-daf1ce55-6dc0-42fb-85bc-a320228483b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2929509137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2929509137
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1334660304
Short name T194
Test name
Test status
Simulation time 209322002 ps
CPU time 1.06 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:16 PM PDT 24
Peak memory 206472 kb
Host smart-59c54b10-2919-4d9a-a476-667d00914772
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1334660304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1334660304
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3938289881
Short name T2824
Test name
Test status
Simulation time 98033783 ps
CPU time 1.29 seconds
Started Jul 17 06:16:07 PM PDT 24
Finished Jul 17 06:16:09 PM PDT 24
Peak memory 223124 kb
Host smart-9d2e0f1d-550f-4e50-9d7b-0d3f413f95b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938289881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3938289881
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3267130246
Short name T249
Test name
Test status
Simulation time 135841230 ps
CPU time 1.14 seconds
Started Jul 17 06:16:07 PM PDT 24
Finished Jul 17 06:16:09 PM PDT 24
Peak memory 206648 kb
Host smart-a3391aae-10fb-45a2-930c-17006179a24c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3267130246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3267130246
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2084148311
Short name T2831
Test name
Test status
Simulation time 43408430 ps
CPU time 0.72 seconds
Started Jul 17 06:16:04 PM PDT 24
Finished Jul 17 06:16:05 PM PDT 24
Peak memory 206352 kb
Host smart-0ce989b2-bdd6-47ff-a4e8-f6dbdc258738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2084148311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2084148311
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.892062431
Short name T245
Test name
Test status
Simulation time 58409965 ps
CPU time 1.45 seconds
Started Jul 17 06:16:04 PM PDT 24
Finished Jul 17 06:16:06 PM PDT 24
Peak memory 222932 kb
Host smart-c5498f7d-603a-467b-8c50-51362304d4a7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=892062431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.892062431
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.825714811
Short name T2754
Test name
Test status
Simulation time 111178039 ps
CPU time 2.47 seconds
Started Jul 17 06:16:15 PM PDT 24
Finished Jul 17 06:16:19 PM PDT 24
Peak memory 206592 kb
Host smart-b95f88fb-d26b-4613-80f8-f6cc2332b572
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=825714811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.825714811
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.206607382
Short name T2779
Test name
Test status
Simulation time 213969504 ps
CPU time 1.66 seconds
Started Jul 17 06:16:09 PM PDT 24
Finished Jul 17 06:16:12 PM PDT 24
Peak memory 206536 kb
Host smart-51206101-dfd3-4ff4-9210-08249987b1ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=206607382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.206607382
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2077610895
Short name T2781
Test name
Test status
Simulation time 226023691 ps
CPU time 2.62 seconds
Started Jul 17 06:16:09 PM PDT 24
Finished Jul 17 06:16:13 PM PDT 24
Peak memory 214880 kb
Host smart-1b4b9f67-b807-4a2f-8001-567ca5bcb2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2077610895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2077610895
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3548573196
Short name T294
Test name
Test status
Simulation time 897409710 ps
CPU time 4.74 seconds
Started Jul 17 06:16:04 PM PDT 24
Finished Jul 17 06:16:10 PM PDT 24
Peak memory 206604 kb
Host smart-98ca23b8-b62e-4351-a8e2-754441ea1a13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3548573196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3548573196
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.730104049
Short name T2809
Test name
Test status
Simulation time 50859496 ps
CPU time 0.79 seconds
Started Jul 17 06:16:28 PM PDT 24
Finished Jul 17 06:16:31 PM PDT 24
Peak memory 206344 kb
Host smart-2f222a90-af24-4adc-bf9a-9f8e36069223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=730104049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.730104049
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4267291071
Short name T2759
Test name
Test status
Simulation time 42767023 ps
CPU time 0.7 seconds
Started Jul 17 06:16:29 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 206348 kb
Host smart-e4a9e5f6-2d60-4d86-92a1-51abc87449a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4267291071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4267291071
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3902254789
Short name T2770
Test name
Test status
Simulation time 41068748 ps
CPU time 0.65 seconds
Started Jul 17 06:16:25 PM PDT 24
Finished Jul 17 06:16:27 PM PDT 24
Peak memory 206336 kb
Host smart-f811b31a-6fb9-41b8-a78b-e02722b4d796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3902254789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3902254789
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.98005600
Short name T274
Test name
Test status
Simulation time 44860164 ps
CPU time 0.68 seconds
Started Jul 17 06:16:28 PM PDT 24
Finished Jul 17 06:16:31 PM PDT 24
Peak memory 206348 kb
Host smart-95ab6178-c4f9-4a74-a80e-26281a9f9f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=98005600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.98005600
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3362595077
Short name T2758
Test name
Test status
Simulation time 39182416 ps
CPU time 0.7 seconds
Started Jul 17 06:16:30 PM PDT 24
Finished Jul 17 06:16:33 PM PDT 24
Peak memory 206324 kb
Host smart-c74cf1d2-f398-4d46-b638-61ca90dfdfa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3362595077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3362595077
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.222529830
Short name T282
Test name
Test status
Simulation time 43024009 ps
CPU time 0.66 seconds
Started Jul 17 06:16:36 PM PDT 24
Finished Jul 17 06:16:37 PM PDT 24
Peak memory 206340 kb
Host smart-c150645e-6e11-44c6-92ce-67afd64a23ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=222529830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.222529830
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2006642205
Short name T289
Test name
Test status
Simulation time 42460700 ps
CPU time 0.72 seconds
Started Jul 17 06:16:45 PM PDT 24
Finished Jul 17 06:16:47 PM PDT 24
Peak memory 206320 kb
Host smart-84d02c5c-29ed-4005-a35f-9c0cfbb4bf4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2006642205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2006642205
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2034811089
Short name T2774
Test name
Test status
Simulation time 87294938 ps
CPU time 0.78 seconds
Started Jul 17 06:23:09 PM PDT 24
Finished Jul 17 06:23:11 PM PDT 24
Peak memory 206348 kb
Host smart-d245d2b7-7f23-410e-9488-92f950f636ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2034811089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2034811089
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1720224696
Short name T2791
Test name
Test status
Simulation time 38853205 ps
CPU time 0.69 seconds
Started Jul 17 06:16:42 PM PDT 24
Finished Jul 17 06:16:43 PM PDT 24
Peak memory 206360 kb
Host smart-482f274d-eb9a-4177-96b8-2a98fadc0ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1720224696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1720224696
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3045132048
Short name T288
Test name
Test status
Simulation time 35094505 ps
CPU time 0.68 seconds
Started Jul 17 06:16:37 PM PDT 24
Finished Jul 17 06:16:39 PM PDT 24
Peak memory 206308 kb
Host smart-6db34f11-cfd8-4fa9-9748-1e83680a1167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3045132048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3045132048
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2604665697
Short name T228
Test name
Test status
Simulation time 112590951 ps
CPU time 1.16 seconds
Started Jul 17 06:15:59 PM PDT 24
Finished Jul 17 06:16:01 PM PDT 24
Peak memory 216628 kb
Host smart-70c41932-254e-427c-a7da-b3b0916e9b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604665697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2604665697
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3147703260
Short name T2839
Test name
Test status
Simulation time 46600964 ps
CPU time 0.93 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:16 PM PDT 24
Peak memory 206640 kb
Host smart-db7976fb-8433-4576-8cda-dae5ac1547ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3147703260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3147703260
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2941010910
Short name T283
Test name
Test status
Simulation time 47345602 ps
CPU time 0.67 seconds
Started Jul 17 06:16:09 PM PDT 24
Finished Jul 17 06:16:10 PM PDT 24
Peak memory 206340 kb
Host smart-ff683314-42a3-4c43-8ea0-713de512f1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2941010910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2941010910
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1273788175
Short name T258
Test name
Test status
Simulation time 175798014 ps
CPU time 1.72 seconds
Started Jul 17 06:16:09 PM PDT 24
Finished Jul 17 06:16:12 PM PDT 24
Peak memory 206632 kb
Host smart-aef9f73b-372d-481c-aa55-300a29bedbe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1273788175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1273788175
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.660356693
Short name T2808
Test name
Test status
Simulation time 66859607 ps
CPU time 1.96 seconds
Started Jul 17 06:16:07 PM PDT 24
Finished Jul 17 06:16:09 PM PDT 24
Peak memory 206728 kb
Host smart-29dd7fc5-4895-43a6-97b1-bd575b3448d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=660356693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.660356693
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3494596964
Short name T2786
Test name
Test status
Simulation time 501612552 ps
CPU time 2.7 seconds
Started Jul 17 06:16:13 PM PDT 24
Finished Jul 17 06:16:17 PM PDT 24
Peak memory 206688 kb
Host smart-2ccae194-4594-4f57-babe-f4b2030ee4e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3494596964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3494596964
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1729202679
Short name T210
Test name
Test status
Simulation time 135187472 ps
CPU time 1.33 seconds
Started Jul 17 06:17:51 PM PDT 24
Finished Jul 17 06:17:53 PM PDT 24
Peak memory 214772 kb
Host smart-db1eb53f-0d2c-4ecf-b03f-7bed0b80980a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729202679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1729202679
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2968815343
Short name T248
Test name
Test status
Simulation time 132469037 ps
CPU time 1.06 seconds
Started Jul 17 06:16:11 PM PDT 24
Finished Jul 17 06:16:13 PM PDT 24
Peak memory 206496 kb
Host smart-16cf3148-0072-4a12-bc6b-3916bd450c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2968815343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2968815343
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2653435786
Short name T285
Test name
Test status
Simulation time 81712021 ps
CPU time 0.79 seconds
Started Jul 17 06:16:09 PM PDT 24
Finished Jul 17 06:16:11 PM PDT 24
Peak memory 206348 kb
Host smart-be175fec-264b-4826-8cb9-066455002b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2653435786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2653435786
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.124002323
Short name T189
Test name
Test status
Simulation time 82206824 ps
CPU time 1.12 seconds
Started Jul 17 06:21:23 PM PDT 24
Finished Jul 17 06:21:25 PM PDT 24
Peak memory 206444 kb
Host smart-f395cc10-bc63-4076-8e34-e4703d93b7ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=124002323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.124002323
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.860032657
Short name T227
Test name
Test status
Simulation time 227776886 ps
CPU time 2.48 seconds
Started Jul 17 06:15:59 PM PDT 24
Finished Jul 17 06:16:03 PM PDT 24
Peak memory 206584 kb
Host smart-8a866d0d-d18c-4263-954d-4edd4f6e1e28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=860032657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.860032657
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2739856236
Short name T2830
Test name
Test status
Simulation time 1066837058 ps
CPU time 5.24 seconds
Started Jul 17 06:16:09 PM PDT 24
Finished Jul 17 06:16:16 PM PDT 24
Peak memory 206552 kb
Host smart-72fbc448-7b39-4a8e-b801-e5ecfd5a87d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2739856236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2739856236
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1188571206
Short name T2772
Test name
Test status
Simulation time 152957316 ps
CPU time 2.05 seconds
Started Jul 17 06:16:21 PM PDT 24
Finished Jul 17 06:16:24 PM PDT 24
Peak memory 214788 kb
Host smart-efe98e28-1c7a-4d89-92e7-0525989090d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188571206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1188571206
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3894183986
Short name T2835
Test name
Test status
Simulation time 55674707 ps
CPU time 1.06 seconds
Started Jul 17 06:16:16 PM PDT 24
Finished Jul 17 06:16:19 PM PDT 24
Peak memory 206492 kb
Host smart-8125b036-fc7f-40b7-b390-8b0e60836d30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3894183986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3894183986
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2557248733
Short name T2797
Test name
Test status
Simulation time 70581853 ps
CPU time 0.7 seconds
Started Jul 17 06:16:11 PM PDT 24
Finished Jul 17 06:16:12 PM PDT 24
Peak memory 206348 kb
Host smart-193bd646-994d-4f27-b22b-be9e0a597dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2557248733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2557248733
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2553714862
Short name T213
Test name
Test status
Simulation time 124239582 ps
CPU time 1.32 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:16 PM PDT 24
Peak memory 206548 kb
Host smart-c4796f8f-ce3c-4f68-a67d-53629f7712e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2553714862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2553714862
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1533646445
Short name T187
Test name
Test status
Simulation time 90454381 ps
CPU time 2.18 seconds
Started Jul 17 06:16:26 PM PDT 24
Finished Jul 17 06:16:29 PM PDT 24
Peak memory 214912 kb
Host smart-b7cc648d-c1eb-476d-a944-10900c9b95a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1533646445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1533646445
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.4258423868
Short name T292
Test name
Test status
Simulation time 854333999 ps
CPU time 4.85 seconds
Started Jul 17 06:16:11 PM PDT 24
Finished Jul 17 06:16:17 PM PDT 24
Peak memory 206508 kb
Host smart-db5dfc63-9b0b-4094-a520-8743edcfe096
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4258423868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.4258423868
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3503956329
Short name T224
Test name
Test status
Simulation time 137424037 ps
CPU time 1.82 seconds
Started Jul 17 06:16:17 PM PDT 24
Finished Jul 17 06:16:20 PM PDT 24
Peak memory 214836 kb
Host smart-8c30b451-0fc3-4fcd-9be0-096f057999c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503956329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3503956329
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1709561438
Short name T2778
Test name
Test status
Simulation time 102080619 ps
CPU time 0.88 seconds
Started Jul 17 06:21:22 PM PDT 24
Finished Jul 17 06:21:24 PM PDT 24
Peak memory 206376 kb
Host smart-9bfd3583-4033-467f-893a-f487c89a86c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1709561438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1709561438
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.887203977
Short name T2840
Test name
Test status
Simulation time 50897076 ps
CPU time 0.66 seconds
Started Jul 17 06:16:21 PM PDT 24
Finished Jul 17 06:16:22 PM PDT 24
Peak memory 206148 kb
Host smart-35c5f992-eb87-4e56-a992-62edd9980016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=887203977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.887203977
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2749875934
Short name T2790
Test name
Test status
Simulation time 211687617 ps
CPU time 1.76 seconds
Started Jul 17 06:16:16 PM PDT 24
Finished Jul 17 06:16:19 PM PDT 24
Peak memory 206552 kb
Host smart-c9c64ef0-8180-4e11-9114-0837b6bc6477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2749875934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2749875934
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.463238554
Short name T2787
Test name
Test status
Simulation time 148109654 ps
CPU time 1.8 seconds
Started Jul 17 06:16:14 PM PDT 24
Finished Jul 17 06:16:17 PM PDT 24
Peak memory 214828 kb
Host smart-4a99c51a-ee85-4a99-aa41-80323ad841c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=463238554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.463238554
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1304768219
Short name T291
Test name
Test status
Simulation time 690321126 ps
CPU time 4.21 seconds
Started Jul 17 06:16:20 PM PDT 24
Finished Jul 17 06:16:26 PM PDT 24
Peak memory 206564 kb
Host smart-56fa9a42-f340-4b3d-b3a0-0d0dcaef900c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1304768219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1304768219
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1053914980
Short name T221
Test name
Test status
Simulation time 106208777 ps
CPU time 2.15 seconds
Started Jul 17 06:16:16 PM PDT 24
Finished Jul 17 06:16:20 PM PDT 24
Peak memory 214788 kb
Host smart-ac112827-94eb-497b-b893-b82df9e9bb5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053914980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1053914980
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3040588172
Short name T2769
Test name
Test status
Simulation time 64416582 ps
CPU time 0.84 seconds
Started Jul 17 06:21:22 PM PDT 24
Finished Jul 17 06:21:24 PM PDT 24
Peak memory 206376 kb
Host smart-3f95d7ff-62ef-4651-844c-38398986be99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3040588172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3040588172
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2099111732
Short name T2792
Test name
Test status
Simulation time 43614518 ps
CPU time 0.72 seconds
Started Jul 17 06:16:15 PM PDT 24
Finished Jul 17 06:16:17 PM PDT 24
Peak memory 206348 kb
Host smart-e4a52a1c-2298-4545-ad25-0846936170df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2099111732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2099111732
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3982094950
Short name T259
Test name
Test status
Simulation time 98882505 ps
CPU time 1.22 seconds
Started Jul 17 06:21:22 PM PDT 24
Finished Jul 17 06:21:24 PM PDT 24
Peak memory 206604 kb
Host smart-fc8f2caa-e376-4622-a2e5-8899c731167b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3982094950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3982094950
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.56357067
Short name T225
Test name
Test status
Simulation time 91970328 ps
CPU time 2.32 seconds
Started Jul 17 06:16:20 PM PDT 24
Finished Jul 17 06:16:24 PM PDT 24
Peak memory 214792 kb
Host smart-8c6920bc-cccb-49a0-96a7-7f65d46d4f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=56357067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.56357067
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3141791548
Short name T211
Test name
Test status
Simulation time 723009302 ps
CPU time 5.09 seconds
Started Jul 17 06:21:23 PM PDT 24
Finished Jul 17 06:21:29 PM PDT 24
Peak memory 206556 kb
Host smart-f9c76a0b-7b52-4361-ac9a-558d12fb95b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3141791548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3141791548
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1551141547
Short name T1148
Test name
Test status
Simulation time 35230548 ps
CPU time 0.68 seconds
Started Jul 17 07:52:29 PM PDT 24
Finished Jul 17 07:52:33 PM PDT 24
Peak memory 206420 kb
Host smart-34aad15a-d215-4c81-9cfd-2379f5888caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1551141547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1551141547
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3067271313
Short name T554
Test name
Test status
Simulation time 4051282633 ps
CPU time 4.74 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:19 PM PDT 24
Peak memory 206500 kb
Host smart-3ebc2e22-c8d7-4698-8fd8-24d2dc12434d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3067271313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3067271313
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1796000358
Short name T1212
Test name
Test status
Simulation time 13415120204 ps
CPU time 12.46 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:27 PM PDT 24
Peak memory 206496 kb
Host smart-f5ff7a89-2c77-4a0f-8b18-a4085676f198
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1796000358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1796000358
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2930375150
Short name T2688
Test name
Test status
Simulation time 23362195589 ps
CPU time 23.41 seconds
Started Jul 17 07:52:21 PM PDT 24
Finished Jul 17 07:52:46 PM PDT 24
Peak memory 206524 kb
Host smart-eef92257-8599-4851-ba05-9557581f57e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2930375150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2930375150
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3416017690
Short name T2584
Test name
Test status
Simulation time 156640783 ps
CPU time 0.74 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:15 PM PDT 24
Peak memory 206460 kb
Host smart-2a80d9a1-2ea9-42f8-a7d3-171ef17f7b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34160
17690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3416017690
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1021846646
Short name T62
Test name
Test status
Simulation time 200256167 ps
CPU time 0.8 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:15 PM PDT 24
Peak memory 206432 kb
Host smart-7793f608-5996-4e65-b518-080189749ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10218
46646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1021846646
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.54513090
Short name T1539
Test name
Test status
Simulation time 526459639 ps
CPU time 1.49 seconds
Started Jul 17 07:52:13 PM PDT 24
Finished Jul 17 07:52:16 PM PDT 24
Peak memory 206644 kb
Host smart-a8dac24b-cd6f-4bdd-b258-9bc4b8a87245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54513
090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.54513090
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.134998461
Short name T947
Test name
Test status
Simulation time 1088225138 ps
CPU time 2.44 seconds
Started Jul 17 07:52:21 PM PDT 24
Finished Jul 17 07:52:25 PM PDT 24
Peak memory 206644 kb
Host smart-573cf7ce-b3e1-430b-b08c-bd26885dfa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13499
8461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.134998461
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.1926606153
Short name T330
Test name
Test status
Simulation time 300987781 ps
CPU time 1.04 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:52:22 PM PDT 24
Peak memory 206456 kb
Host smart-65d64d69-0250-4b8e-af05-80f43a0b8fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19266
06153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.1926606153
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.663404087
Short name T1578
Test name
Test status
Simulation time 178891523 ps
CPU time 0.84 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:52:21 PM PDT 24
Peak memory 206452 kb
Host smart-3262cd03-e7b4-42f5-b71f-e31ac9644c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66340
4087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.663404087
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.87777790
Short name T2525
Test name
Test status
Simulation time 5124171079 ps
CPU time 34.58 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:52:55 PM PDT 24
Peak memory 206664 kb
Host smart-2a44cbad-5015-4e2f-a272-bc1b39520e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87777
790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.87777790
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.3223995475
Short name T840
Test name
Test status
Simulation time 33181457 ps
CPU time 0.65 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:09 PM PDT 24
Peak memory 206452 kb
Host smart-d44c9c68-c308-4d92-8418-cdbae7b98969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32239
95475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3223995475
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1349697522
Short name T2336
Test name
Test status
Simulation time 742926357 ps
CPU time 1.84 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:10 PM PDT 24
Peak memory 206812 kb
Host smart-dca8f0bc-f9aa-45ae-8818-765a4b2b4449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13496
97522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1349697522
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2699889752
Short name T1275
Test name
Test status
Simulation time 292682649 ps
CPU time 1.99 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 206608 kb
Host smart-a566645e-a921-4802-bef6-ede3fffb5779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26998
89752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2699889752
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2112580994
Short name T2082
Test name
Test status
Simulation time 84168797133 ps
CPU time 103.57 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:54:04 PM PDT 24
Peak memory 206624 kb
Host smart-0706f7b6-5c82-4128-9227-084c2049ca44
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2112580994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2112580994
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.640071547
Short name T310
Test name
Test status
Simulation time 84173538880 ps
CPU time 111.08 seconds
Started Jul 17 07:52:21 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206468 kb
Host smart-54647d25-6446-44de-8810-8eba0008afeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640071547 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.640071547
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.482549349
Short name T1036
Test name
Test status
Simulation time 105101053964 ps
CPU time 136.5 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:54:25 PM PDT 24
Peak memory 206692 kb
Host smart-40d98eed-5ad9-4059-a8a7-e107e1c51c14
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=482549349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.482549349
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.2193737812
Short name T2350
Test name
Test status
Simulation time 101281310075 ps
CPU time 128.86 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:54:15 PM PDT 24
Peak memory 206660 kb
Host smart-8a1bbb03-662f-449c-b146-8732efd327c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193737812 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2193737812
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3812667311
Short name T2661
Test name
Test status
Simulation time 97176001632 ps
CPU time 156.85 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:54:46 PM PDT 24
Peak memory 206688 kb
Host smart-8b656458-39ea-4c46-870a-fd34cf4ffe8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38126
67311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3812667311
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1035540194
Short name T1693
Test name
Test status
Simulation time 201549868 ps
CPU time 0.84 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:52:12 PM PDT 24
Peak memory 206428 kb
Host smart-21c2af66-a495-49f8-ab36-ad9c7cc122b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10355
40194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1035540194
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2048895682
Short name T317
Test name
Test status
Simulation time 144017497 ps
CPU time 0.75 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:14 PM PDT 24
Peak memory 206432 kb
Host smart-1cb10db4-e369-4012-b830-96e117253a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20488
95682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2048895682
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2812866558
Short name T2147
Test name
Test status
Simulation time 179315587 ps
CPU time 0.79 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:52:12 PM PDT 24
Peak memory 206452 kb
Host smart-4d23e939-6e44-436b-be49-edc713cba966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28128
66558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2812866558
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1199496718
Short name T1425
Test name
Test status
Simulation time 7153435826 ps
CPU time 68.83 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:53:20 PM PDT 24
Peak memory 206724 kb
Host smart-23dc42e2-c0af-4258-b2d7-01d48ef358e3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1199496718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1199496718
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1169003331
Short name T161
Test name
Test status
Simulation time 11284232143 ps
CPU time 39.66 seconds
Started Jul 17 07:52:13 PM PDT 24
Finished Jul 17 07:52:55 PM PDT 24
Peak memory 206864 kb
Host smart-697a531f-7034-45d8-961d-aff899d1ad07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11690
03331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1169003331
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1651705401
Short name T2613
Test name
Test status
Simulation time 195261417 ps
CPU time 0.85 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:52:12 PM PDT 24
Peak memory 206124 kb
Host smart-96cdcb1f-fc68-4033-817e-db5dba20345d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
05401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1651705401
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1573404404
Short name T72
Test name
Test status
Simulation time 471911882 ps
CPU time 1.4 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:52:12 PM PDT 24
Peak memory 206172 kb
Host smart-4f8224cc-6783-472c-98ec-500f6b82ce19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15734
04404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1573404404
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2934333452
Short name T1816
Test name
Test status
Simulation time 23302354442 ps
CPU time 26.34 seconds
Started Jul 17 07:52:11 PM PDT 24
Finished Jul 17 07:52:39 PM PDT 24
Peak memory 206508 kb
Host smart-2be16d2a-bbb4-4246-bd50-8525766cf272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29343
33452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2934333452
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.876994641
Short name T384
Test name
Test status
Simulation time 3340865107 ps
CPU time 4.33 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:52:24 PM PDT 24
Peak memory 206512 kb
Host smart-42080a70-ac91-4d69-b3bd-17556514cbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87699
4641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.876994641
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3248127624
Short name T521
Test name
Test status
Simulation time 7991800723 ps
CPU time 54.76 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:53:15 PM PDT 24
Peak memory 206728 kb
Host smart-12c06e8a-1874-4e09-8904-e5d711dd1450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32481
27624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3248127624
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2491321589
Short name T1302
Test name
Test status
Simulation time 6317939475 ps
CPU time 44.01 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:53:04 PM PDT 24
Peak memory 206708 kb
Host smart-ad33ece0-dddb-49d1-ba96-c2085d804683
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2491321589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2491321589
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.227386748
Short name T419
Test name
Test status
Simulation time 238806412 ps
CPU time 0.92 seconds
Started Jul 17 07:52:13 PM PDT 24
Finished Jul 17 07:52:16 PM PDT 24
Peak memory 206600 kb
Host smart-02357383-a532-484c-9e5b-c1acc2abd1a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=227386748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.227386748
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3806901626
Short name T580
Test name
Test status
Simulation time 204579513 ps
CPU time 0.9 seconds
Started Jul 17 07:52:13 PM PDT 24
Finished Jul 17 07:52:16 PM PDT 24
Peak memory 206592 kb
Host smart-e2c71674-a571-40d5-9c99-f79760c52c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38069
01626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3806901626
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.1251245365
Short name T1009
Test name
Test status
Simulation time 4963490181 ps
CPU time 137.68 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:54:29 PM PDT 24
Peak memory 206676 kb
Host smart-7d863409-91ea-42e1-8ecc-59bd62eac221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
45365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.1251245365
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.4200882300
Short name T2639
Test name
Test status
Simulation time 5634736079 ps
CPU time 159.5 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206656 kb
Host smart-5b1fa781-e158-414d-bc07-ec62171af6c4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4200882300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.4200882300
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1994443210
Short name T1593
Test name
Test status
Simulation time 157194428 ps
CPU time 0.78 seconds
Started Jul 17 07:52:26 PM PDT 24
Finished Jul 17 07:52:29 PM PDT 24
Peak memory 206408 kb
Host smart-c015eeb1-1587-400f-9c5f-e19fcbfa97bd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1994443210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1994443210
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1033925258
Short name T2521
Test name
Test status
Simulation time 146812991 ps
CPU time 0.81 seconds
Started Jul 17 07:52:25 PM PDT 24
Finished Jul 17 07:52:27 PM PDT 24
Peak memory 206456 kb
Host smart-628626df-fe61-435e-9fb2-b8bd096c1f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10339
25258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1033925258
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2169998598
Short name T74
Test name
Test status
Simulation time 510537466 ps
CPU time 1.28 seconds
Started Jul 17 07:52:35 PM PDT 24
Finished Jul 17 07:52:37 PM PDT 24
Peak memory 206440 kb
Host smart-f979c91b-53e9-46da-ad72-7f30b2bab470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21699
98598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2169998598
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2094837933
Short name T940
Test name
Test status
Simulation time 150525291 ps
CPU time 0.74 seconds
Started Jul 17 07:52:32 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 206588 kb
Host smart-732a9245-128e-4b21-ae9d-4dd4e5a7fc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20948
37933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2094837933
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.161195000
Short name T1900
Test name
Test status
Simulation time 187028894 ps
CPU time 0.85 seconds
Started Jul 17 07:52:26 PM PDT 24
Finished Jul 17 07:52:28 PM PDT 24
Peak memory 206452 kb
Host smart-476ff169-efae-49df-8b6b-67807fe2d560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
5000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.161195000
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3197474111
Short name T1340
Test name
Test status
Simulation time 171898341 ps
CPU time 0.83 seconds
Started Jul 17 07:52:28 PM PDT 24
Finished Jul 17 07:52:31 PM PDT 24
Peak memory 206452 kb
Host smart-080e4c88-bc83-453e-a01a-40cb44636edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31974
74111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3197474111
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.633296726
Short name T1200
Test name
Test status
Simulation time 150622763 ps
CPU time 0.78 seconds
Started Jul 17 07:52:29 PM PDT 24
Finished Jul 17 07:52:32 PM PDT 24
Peak memory 206436 kb
Host smart-f2c8a82c-fed1-4a17-89d3-fa78adafda46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63329
6726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.633296726
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.3848697254
Short name T852
Test name
Test status
Simulation time 179922240 ps
CPU time 0.92 seconds
Started Jul 17 07:52:33 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 206468 kb
Host smart-94459308-23ef-4b74-8425-f819bf03f507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38486
97254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.3848697254
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1272566242
Short name T2565
Test name
Test status
Simulation time 204147282 ps
CPU time 0.93 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:31 PM PDT 24
Peak memory 206464 kb
Host smart-44d50040-bf2f-45da-9071-20bc30568aad
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1272566242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1272566242
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3014356594
Short name T1507
Test name
Test status
Simulation time 278535361 ps
CPU time 0.97 seconds
Started Jul 17 07:52:26 PM PDT 24
Finished Jul 17 07:52:29 PM PDT 24
Peak memory 206432 kb
Host smart-9b0925d7-510b-4932-98b5-62af597ec98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30143
56594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3014356594
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.10926450
Short name T2409
Test name
Test status
Simulation time 218064103 ps
CPU time 0.87 seconds
Started Jul 17 07:52:26 PM PDT 24
Finished Jul 17 07:52:29 PM PDT 24
Peak memory 206440 kb
Host smart-c6a01a09-9aff-412f-aa65-2989d1d0898e
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=10926450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.10926450
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2470837154
Short name T2370
Test name
Test status
Simulation time 284209075 ps
CPU time 0.99 seconds
Started Jul 17 07:52:26 PM PDT 24
Finished Jul 17 07:52:27 PM PDT 24
Peak memory 206432 kb
Host smart-7535834e-0915-48cc-8bc1-43688acbe31c
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2470837154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2470837154
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.218890742
Short name T1380
Test name
Test status
Simulation time 190766692 ps
CPU time 0.9 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:30 PM PDT 24
Peak memory 206436 kb
Host smart-bdda81f3-2b31-4ed9-8038-323a6afae4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21889
0742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.218890742
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2923878334
Short name T243
Test name
Test status
Simulation time 7450605264 ps
CPU time 17.13 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:47 PM PDT 24
Peak memory 214868 kb
Host smart-cb507221-cfbf-4bf5-b3b1-3a490220db95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29238
78334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2923878334
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.472872737
Short name T1308
Test name
Test status
Simulation time 154012676 ps
CPU time 0.84 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:31 PM PDT 24
Peak memory 206444 kb
Host smart-dc1ff517-7c20-419a-acf5-da68086bc9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47287
2737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.472872737
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2012195738
Short name T1406
Test name
Test status
Simulation time 236242031 ps
CPU time 0.9 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:30 PM PDT 24
Peak memory 206460 kb
Host smart-a854af42-5295-4482-a29f-47e59827bfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121
95738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2012195738
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2569925298
Short name T157
Test name
Test status
Simulation time 10640808801 ps
CPU time 192.91 seconds
Started Jul 17 07:52:30 PM PDT 24
Finished Jul 17 07:55:46 PM PDT 24
Peak memory 206916 kb
Host smart-189208c8-ebc3-4321-83fd-3ffba8532fd3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2569925298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2569925298
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1713850439
Short name T152
Test name
Test status
Simulation time 12753942712 ps
CPU time 86.47 seconds
Started Jul 17 07:52:33 PM PDT 24
Finished Jul 17 07:54:01 PM PDT 24
Peak memory 206660 kb
Host smart-c7841c7d-c879-4d28-ac28-e4ed917b8731
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1713850439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1713850439
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1048286937
Short name T1316
Test name
Test status
Simulation time 25309086596 ps
CPU time 147.73 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:54:58 PM PDT 24
Peak memory 206628 kb
Host smart-84988312-c69e-48a1-a2d9-a5630089df5d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1048286937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1048286937
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.912075808
Short name T2002
Test name
Test status
Simulation time 198231309 ps
CPU time 0.81 seconds
Started Jul 17 07:52:30 PM PDT 24
Finished Jul 17 07:52:33 PM PDT 24
Peak memory 206452 kb
Host smart-4d15354c-ed3c-4161-a053-eba892283e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91207
5808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.912075808
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3640935145
Short name T719
Test name
Test status
Simulation time 230635409 ps
CPU time 0.86 seconds
Started Jul 17 07:52:28 PM PDT 24
Finished Jul 17 07:52:32 PM PDT 24
Peak memory 206448 kb
Host smart-30f05ba8-d387-47da-b271-d78476deff96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36409
35145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3640935145
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1486288886
Short name T184
Test name
Test status
Simulation time 2063010348 ps
CPU time 3.08 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:32 PM PDT 24
Peak memory 225296 kb
Host smart-feac3dda-07ff-4d79-8f0f-dfe5ff2fb6b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1486288886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1486288886
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1472851097
Short name T2427
Test name
Test status
Simulation time 373577729 ps
CPU time 1.13 seconds
Started Jul 17 07:52:35 PM PDT 24
Finished Jul 17 07:52:37 PM PDT 24
Peak memory 206456 kb
Host smart-eadec158-755a-45bb-8d3e-8da63cc37cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14728
51097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1472851097
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.1706733889
Short name T1991
Test name
Test status
Simulation time 215555607 ps
CPU time 0.89 seconds
Started Jul 17 07:52:30 PM PDT 24
Finished Jul 17 07:52:34 PM PDT 24
Peak memory 206436 kb
Host smart-711f843c-494d-4b80-8bab-6fa574b6b398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17067
33889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.1706733889
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1923247976
Short name T2701
Test name
Test status
Simulation time 201814610 ps
CPU time 0.79 seconds
Started Jul 17 07:52:41 PM PDT 24
Finished Jul 17 07:52:43 PM PDT 24
Peak memory 206452 kb
Host smart-685c9983-bd71-45d8-bc9c-dd259a272b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19232
47976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1923247976
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.329681856
Short name T678
Test name
Test status
Simulation time 148047512 ps
CPU time 0.81 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:31 PM PDT 24
Peak memory 206440 kb
Host smart-711f940c-76b1-44c4-9585-6b5b839d9d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32968
1856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.329681856
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1008243593
Short name T2680
Test name
Test status
Simulation time 246816129 ps
CPU time 0.92 seconds
Started Jul 17 07:52:26 PM PDT 24
Finished Jul 17 07:52:29 PM PDT 24
Peak memory 206452 kb
Host smart-78e96f4f-c2bb-41e9-8aab-d2845a7fb958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10082
43593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1008243593
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3252397255
Short name T1553
Test name
Test status
Simulation time 5780798470 ps
CPU time 158.88 seconds
Started Jul 17 07:52:29 PM PDT 24
Finished Jul 17 07:55:10 PM PDT 24
Peak memory 206664 kb
Host smart-ddeab8c0-ab02-4ca5-aa3c-632544631c00
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3252397255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3252397255
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2784701144
Short name T1326
Test name
Test status
Simulation time 153172877 ps
CPU time 0.81 seconds
Started Jul 17 07:52:30 PM PDT 24
Finished Jul 17 07:52:34 PM PDT 24
Peak memory 206420 kb
Host smart-0508cef2-6d0e-4539-b7ed-3570406a56e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27847
01144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2784701144
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2860563590
Short name T652
Test name
Test status
Simulation time 187105159 ps
CPU time 0.85 seconds
Started Jul 17 07:52:29 PM PDT 24
Finished Jul 17 07:52:33 PM PDT 24
Peak memory 206576 kb
Host smart-5d0362a5-2247-4aca-b8f0-c400e3715d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605
63590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2860563590
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1325359506
Short name T2445
Test name
Test status
Simulation time 1296247842 ps
CPU time 2.59 seconds
Started Jul 17 07:52:30 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 206604 kb
Host smart-cd51e2d6-d3ec-4d9e-98fe-49da18ac8c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13253
59506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1325359506
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.4187489053
Short name T2476
Test name
Test status
Simulation time 3318379504 ps
CPU time 23.45 seconds
Started Jul 17 07:52:28 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206604 kb
Host smart-704433b5-a7b8-4eb8-b679-d25479f54f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
89053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.4187489053
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3741463522
Short name T2511
Test name
Test status
Simulation time 35272942 ps
CPU time 0.66 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:52:56 PM PDT 24
Peak memory 206400 kb
Host smart-4216b99e-9c74-4516-803d-5bf9fb0e4749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3741463522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3741463522
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.4272737481
Short name T811
Test name
Test status
Simulation time 4353768892 ps
CPU time 5.2 seconds
Started Jul 17 07:52:28 PM PDT 24
Finished Jul 17 07:52:36 PM PDT 24
Peak memory 206700 kb
Host smart-d5b58602-85db-4450-9d9d-d966ffd31fbf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4272737481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.4272737481
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3216831661
Short name T1610
Test name
Test status
Simulation time 13355286555 ps
CPU time 12.93 seconds
Started Jul 17 07:52:28 PM PDT 24
Finished Jul 17 07:52:44 PM PDT 24
Peak memory 206496 kb
Host smart-f8da8d5a-7f7a-46c4-b16b-5c80654e7906
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3216831661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3216831661
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2063542178
Short name T1567
Test name
Test status
Simulation time 23391441676 ps
CPU time 22.5 seconds
Started Jul 17 07:52:27 PM PDT 24
Finished Jul 17 07:52:51 PM PDT 24
Peak memory 206732 kb
Host smart-5ac79ea9-fbcd-4494-ab3d-d98dcff28399
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2063542178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.2063542178
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1698031420
Short name T606
Test name
Test status
Simulation time 155886384 ps
CPU time 0.77 seconds
Started Jul 17 07:52:32 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 206592 kb
Host smart-c48a198a-3f83-459f-83a1-e3bfa17705ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16980
31420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1698031420
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2956509380
Short name T57
Test name
Test status
Simulation time 155746707 ps
CPU time 0.8 seconds
Started Jul 17 07:52:28 PM PDT 24
Finished Jul 17 07:52:32 PM PDT 24
Peak memory 206472 kb
Host smart-239716d7-8a73-41fc-b203-9bb8b0465a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29565
09380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2956509380
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2111606764
Short name T64
Test name
Test status
Simulation time 138725292 ps
CPU time 0.77 seconds
Started Jul 17 07:52:32 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 206440 kb
Host smart-1d92f687-bc6c-4d84-bcaf-fe079fc02397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21116
06764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2111606764
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1620772537
Short name T2616
Test name
Test status
Simulation time 165615459 ps
CPU time 0.82 seconds
Started Jul 17 07:52:42 PM PDT 24
Finished Jul 17 07:52:45 PM PDT 24
Peak memory 206452 kb
Host smart-251b4318-f382-4242-942f-162d7baf8f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16207
72537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1620772537
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.642844670
Short name T1315
Test name
Test status
Simulation time 567611900 ps
CPU time 1.51 seconds
Started Jul 17 07:52:36 PM PDT 24
Finished Jul 17 07:52:38 PM PDT 24
Peak memory 206608 kb
Host smart-8c6a2bfd-5b30-4cca-bad1-07fddda11baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64284
4670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.642844670
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1609973015
Short name T1436
Test name
Test status
Simulation time 553473781 ps
CPU time 1.39 seconds
Started Jul 17 07:52:41 PM PDT 24
Finished Jul 17 07:52:45 PM PDT 24
Peak memory 206452 kb
Host smart-b1ec390b-b620-401c-b4a6-a1ed587c2cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16099
73015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1609973015
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.3228976663
Short name T1136
Test name
Test status
Simulation time 12497082230 ps
CPU time 26.44 seconds
Started Jul 17 07:52:31 PM PDT 24
Finished Jul 17 07:53:00 PM PDT 24
Peak memory 206712 kb
Host smart-0e1e6c77-7380-44ba-96c4-80db18f2b1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32289
76663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.3228976663
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.3749917054
Short name T967
Test name
Test status
Simulation time 490472069 ps
CPU time 1.4 seconds
Started Jul 17 07:52:42 PM PDT 24
Finished Jul 17 07:52:45 PM PDT 24
Peak memory 206460 kb
Host smart-0efccaf4-b6ff-4510-b14d-4509f6ac809c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37499
17054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.3749917054
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3223438439
Short name T1467
Test name
Test status
Simulation time 148059617 ps
CPU time 0.75 seconds
Started Jul 17 07:52:41 PM PDT 24
Finished Jul 17 07:52:44 PM PDT 24
Peak memory 206452 kb
Host smart-7bfede8a-3aad-4d80-b1c1-b10953aa2eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32234
38439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3223438439
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3366497514
Short name T342
Test name
Test status
Simulation time 40771735 ps
CPU time 0.67 seconds
Started Jul 17 07:52:43 PM PDT 24
Finished Jul 17 07:52:45 PM PDT 24
Peak memory 206448 kb
Host smart-6473c8b4-77ef-4028-8274-71b8c6953fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33664
97514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3366497514
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3963541406
Short name T2666
Test name
Test status
Simulation time 926303573 ps
CPU time 2.21 seconds
Started Jul 17 07:52:31 PM PDT 24
Finished Jul 17 07:52:36 PM PDT 24
Peak memory 206652 kb
Host smart-557b0785-91f9-401a-b185-a1175e9f73af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39635
41406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3963541406
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.4291210465
Short name T2591
Test name
Test status
Simulation time 224076558 ps
CPU time 1.59 seconds
Started Jul 17 07:52:32 PM PDT 24
Finished Jul 17 07:52:36 PM PDT 24
Peak memory 206552 kb
Host smart-ee8c7be1-c3a8-4dde-b830-f2fc46280b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42912
10465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.4291210465
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1403794090
Short name T337
Test name
Test status
Simulation time 81188397431 ps
CPU time 105.66 seconds
Started Jul 17 07:52:35 PM PDT 24
Finished Jul 17 07:54:21 PM PDT 24
Peak memory 206676 kb
Host smart-1f331e57-1dc0-4294-a1d7-34869fcb7860
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1403794090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1403794090
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.615356415
Short name T1442
Test name
Test status
Simulation time 108276235792 ps
CPU time 131.28 seconds
Started Jul 17 07:52:42 PM PDT 24
Finished Jul 17 07:54:56 PM PDT 24
Peak memory 206720 kb
Host smart-f2f6cf50-a5ea-4a0d-8489-44cb33e86a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615356415 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.615356415
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2762359340
Short name T589
Test name
Test status
Simulation time 108106341343 ps
CPU time 146.57 seconds
Started Jul 17 07:52:28 PM PDT 24
Finished Jul 17 07:54:57 PM PDT 24
Peak memory 206676 kb
Host smart-29cb6c97-87c9-4d8b-b598-e63e4e36e8b9
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2762359340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2762359340
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.3568501332
Short name T2671
Test name
Test status
Simulation time 81272815914 ps
CPU time 104.46 seconds
Started Jul 17 07:52:42 PM PDT 24
Finished Jul 17 07:54:28 PM PDT 24
Peak memory 206664 kb
Host smart-fc47bef9-bf90-460b-8718-94bfb231d228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568501332 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3568501332
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1906261437
Short name T1961
Test name
Test status
Simulation time 119161672414 ps
CPU time 167.82 seconds
Started Jul 17 07:52:42 PM PDT 24
Finished Jul 17 07:55:31 PM PDT 24
Peak memory 206668 kb
Host smart-a114891f-be06-427b-8f47-9df37fbdd231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19062
61437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1906261437
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.665623911
Short name T2054
Test name
Test status
Simulation time 218569104 ps
CPU time 0.89 seconds
Started Jul 17 07:52:28 PM PDT 24
Finished Jul 17 07:52:32 PM PDT 24
Peak memory 206428 kb
Host smart-c3af840c-6726-4167-a17c-470d49c936fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66562
3911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.665623911
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2170858610
Short name T2178
Test name
Test status
Simulation time 157220092 ps
CPU time 0.71 seconds
Started Jul 17 07:52:29 PM PDT 24
Finished Jul 17 07:52:33 PM PDT 24
Peak memory 206432 kb
Host smart-4bbcace9-71fd-4b87-93f1-dbe41b0c02af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21708
58610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2170858610
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.4251111619
Short name T2611
Test name
Test status
Simulation time 180208378 ps
CPU time 0.84 seconds
Started Jul 17 07:52:26 PM PDT 24
Finished Jul 17 07:52:28 PM PDT 24
Peak memory 206452 kb
Host smart-298fa692-40c4-4922-babc-de540255e541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42511
11619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.4251111619
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.1905461962
Short name T2618
Test name
Test status
Simulation time 8723370495 ps
CPU time 30.3 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:53:21 PM PDT 24
Peak memory 206844 kb
Host smart-c8593580-d446-4ffb-af5d-f64a63cc1cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19054
61962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.1905461962
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.55919648
Short name T2110
Test name
Test status
Simulation time 165915514 ps
CPU time 0.78 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:52:52 PM PDT 24
Peak memory 206468 kb
Host smart-42d68205-698e-4e05-b818-486b8526f75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55919
648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.55919648
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.656054906
Short name T181
Test name
Test status
Simulation time 23297150035 ps
CPU time 22.72 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:53:18 PM PDT 24
Peak memory 206504 kb
Host smart-0b18d7d6-1945-412a-bd92-e9ab0ed79396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65605
4906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.656054906
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1519058707
Short name T2108
Test name
Test status
Simulation time 3317663224 ps
CPU time 4.37 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206460 kb
Host smart-dde32ba6-e6da-45f6-ba5d-83d149b8a7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15190
58707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1519058707
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3044055717
Short name T1615
Test name
Test status
Simulation time 14487537940 ps
CPU time 402.68 seconds
Started Jul 17 07:52:48 PM PDT 24
Finished Jul 17 07:59:32 PM PDT 24
Peak memory 206728 kb
Host smart-9924de8c-3807-4203-8109-40748fd0e9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30440
55717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3044055717
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.3229883875
Short name T1416
Test name
Test status
Simulation time 5049391170 ps
CPU time 35.52 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206708 kb
Host smart-acc5881b-d26a-46dd-bf01-118c86aa5383
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3229883875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3229883875
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.345550935
Short name T2391
Test name
Test status
Simulation time 247231134 ps
CPU time 0.87 seconds
Started Jul 17 07:52:48 PM PDT 24
Finished Jul 17 07:52:50 PM PDT 24
Peak memory 206416 kb
Host smart-c72b7467-eb1a-4b5f-b71a-695c2207b550
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=345550935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.345550935
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3520807903
Short name T315
Test name
Test status
Simulation time 199630559 ps
CPU time 0.83 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206460 kb
Host smart-49d01979-55f5-4428-abcf-dee212cbaf71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35208
07903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3520807903
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.297198408
Short name T1357
Test name
Test status
Simulation time 4305844838 ps
CPU time 112.7 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:54:46 PM PDT 24
Peak memory 206696 kb
Host smart-73c8760f-4293-406f-9e81-3b5443d41a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
8408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.297198408
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3290940987
Short name T2658
Test name
Test status
Simulation time 6309566390 ps
CPU time 43.59 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:53:37 PM PDT 24
Peak memory 206716 kb
Host smart-d809d8f8-3c48-456d-8916-d03143a00de1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3290940987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3290940987
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2953866455
Short name T679
Test name
Test status
Simulation time 167770932 ps
CPU time 0.81 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206452 kb
Host smart-93bcf34d-c3f9-438b-ab7c-937fc1df02fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2953866455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2953866455
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2084645952
Short name T693
Test name
Test status
Simulation time 164127464 ps
CPU time 0.76 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:52:51 PM PDT 24
Peak memory 206452 kb
Host smart-29ae229c-789a-4df6-833e-012632420edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20846
45952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2084645952
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.4031171017
Short name T1592
Test name
Test status
Simulation time 145523317 ps
CPU time 0.79 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206452 kb
Host smart-eb16cddb-104d-44af-8b68-fb4901ec21e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40311
71017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.4031171017
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1758027392
Short name T311
Test name
Test status
Simulation time 179086009 ps
CPU time 0.81 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:52:52 PM PDT 24
Peak memory 206468 kb
Host smart-015ea61f-947f-457e-9777-b3bc6292ff7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17580
27392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1758027392
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2254748252
Short name T2142
Test name
Test status
Simulation time 140493917 ps
CPU time 0.75 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206452 kb
Host smart-43acb716-5b83-4da0-a47f-7059f8747d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22547
48252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2254748252
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2856436513
Short name T2318
Test name
Test status
Simulation time 184198846 ps
CPU time 0.77 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206456 kb
Host smart-e5033431-b819-414c-9a1a-7429f6bbadda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28564
36513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2856436513
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3963569256
Short name T2014
Test name
Test status
Simulation time 228619856 ps
CPU time 0.89 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206460 kb
Host smart-31c3f2c6-8526-4fcb-804e-bd5d4a80d8a7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3963569256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3963569256
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1162482119
Short name T193
Test name
Test status
Simulation time 216750296 ps
CPU time 0.96 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206444 kb
Host smart-db8b1168-a590-4021-a0eb-61f412cbd12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11624
82119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1162482119
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.4004882055
Short name T2263
Test name
Test status
Simulation time 173114509 ps
CPU time 0.78 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206436 kb
Host smart-21495e61-7022-4ca6-a8c9-5a515de71c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40048
82055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.4004882055
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1928070148
Short name T41
Test name
Test status
Simulation time 41673528 ps
CPU time 0.67 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206416 kb
Host smart-5b9a3554-2119-4da1-9a8a-4609b0ccfdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19280
70148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1928070148
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1539415788
Short name T995
Test name
Test status
Simulation time 23987037523 ps
CPU time 56.5 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:53:49 PM PDT 24
Peak memory 206740 kb
Host smart-a9f405dc-6434-4f04-a0ef-1ce449660256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15394
15788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1539415788
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1050387627
Short name T1738
Test name
Test status
Simulation time 204533240 ps
CPU time 0.86 seconds
Started Jul 17 07:52:54 PM PDT 24
Finished Jul 17 07:52:57 PM PDT 24
Peak memory 206456 kb
Host smart-fedc632f-5c0b-4129-a215-1523e077fa53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10503
87627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1050387627
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2622035357
Short name T1800
Test name
Test status
Simulation time 233904224 ps
CPU time 0.95 seconds
Started Jul 17 07:52:54 PM PDT 24
Finished Jul 17 07:52:57 PM PDT 24
Peak memory 206448 kb
Host smart-cee0ef0a-bcf1-4cbf-9e0a-86c0936a7cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
35357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2622035357
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.88339554
Short name T2633
Test name
Test status
Simulation time 10679306207 ps
CPU time 186.63 seconds
Started Jul 17 07:52:53 PM PDT 24
Finished Jul 17 07:56:02 PM PDT 24
Peak memory 206736 kb
Host smart-e09e47ad-3d89-45a5-8b6d-e218b888b6ec
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=88339554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.88339554
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3372838479
Short name T923
Test name
Test status
Simulation time 223831056 ps
CPU time 0.88 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:52:56 PM PDT 24
Peak memory 206448 kb
Host smart-91713809-c5da-4888-887e-e80f211aaee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33728
38479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3372838479
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.639239743
Short name T2355
Test name
Test status
Simulation time 213278220 ps
CPU time 0.84 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:52:55 PM PDT 24
Peak memory 206452 kb
Host smart-3ef94f6c-7b41-460f-8d74-eb40c81a03ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63923
9743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.639239743
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1070712071
Short name T617
Test name
Test status
Simulation time 182823168 ps
CPU time 0.79 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206416 kb
Host smart-94048056-63a2-4350-9aa6-ec4af06bba19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10707
12071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1070712071
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.4153407693
Short name T80
Test name
Test status
Simulation time 186998640 ps
CPU time 0.84 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:52:56 PM PDT 24
Peak memory 206460 kb
Host smart-55ed8615-b760-47cf-8350-9d2b90ee22b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41534
07693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.4153407693
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3647374538
Short name T200
Test name
Test status
Simulation time 309528197 ps
CPU time 1.07 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:52:56 PM PDT 24
Peak memory 224244 kb
Host smart-db3dae89-6e3e-47c1-a8f7-20b0142ed84d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3647374538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3647374538
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1883249675
Short name T1971
Test name
Test status
Simulation time 445523162 ps
CPU time 1.32 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:52:55 PM PDT 24
Peak memory 206460 kb
Host smart-3e98916c-e8a9-4a19-ab7a-c2edad661556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18832
49675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1883249675
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.788006350
Short name T2303
Test name
Test status
Simulation time 233614808 ps
CPU time 0.88 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206416 kb
Host smart-825f9d72-82c5-496f-b6e9-19bc8781c6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78800
6350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.788006350
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1234588521
Short name T816
Test name
Test status
Simulation time 154527215 ps
CPU time 0.77 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206436 kb
Host smart-9451500d-8a86-4a4a-a0da-0a32faa03e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12345
88521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1234588521
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3868316279
Short name T1526
Test name
Test status
Simulation time 174932932 ps
CPU time 0.81 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206460 kb
Host smart-7de7e315-28dd-4638-81b1-4cc3c92360b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38683
16279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3868316279
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1837268672
Short name T2368
Test name
Test status
Simulation time 244168067 ps
CPU time 0.97 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:52:56 PM PDT 24
Peak memory 206456 kb
Host smart-a04179b5-4367-4de7-8d2a-d3cf7e75fa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18372
68672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1837268672
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2923255213
Short name T610
Test name
Test status
Simulation time 4205696710 ps
CPU time 32.1 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:53:27 PM PDT 24
Peak memory 206664 kb
Host smart-297cbc4e-186b-42c2-8900-dc0a8f69a44f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2923255213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2923255213
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2105541949
Short name T2640
Test name
Test status
Simulation time 192358076 ps
CPU time 0.8 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:52:56 PM PDT 24
Peak memory 206456 kb
Host smart-bdb49ee4-7847-4f6e-9cc6-0790ca97e7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21055
41949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2105541949
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.4187054127
Short name T2024
Test name
Test status
Simulation time 188513701 ps
CPU time 0.84 seconds
Started Jul 17 07:52:53 PM PDT 24
Finished Jul 17 07:52:57 PM PDT 24
Peak memory 206456 kb
Host smart-f1eda18b-2e8f-4148-b181-beb23feb6690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41870
54127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.4187054127
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1420501926
Short name T1173
Test name
Test status
Simulation time 1246027054 ps
CPU time 2.79 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:56 PM PDT 24
Peak memory 206612 kb
Host smart-7ffa21ad-20d2-4400-9da5-3b69e2d1c1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14205
01926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1420501926
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3037612921
Short name T301
Test name
Test status
Simulation time 4847642320 ps
CPU time 136.55 seconds
Started Jul 17 07:52:53 PM PDT 24
Finished Jul 17 07:55:12 PM PDT 24
Peak memory 206624 kb
Host smart-49d7808a-318d-44a7-986c-e64dc5fdc200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
12921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3037612921
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1781248084
Short name T2111
Test name
Test status
Simulation time 7022674744 ps
CPU time 174.27 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:55:49 PM PDT 24
Peak memory 206736 kb
Host smart-5b65ec4b-5af0-4bae-8155-a8bc202b2cde
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1781248084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1781248084
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1488305592
Short name T2622
Test name
Test status
Simulation time 35570793 ps
CPU time 0.79 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206436 kb
Host smart-2867eaae-2be7-4da3-89c9-68906869f09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1488305592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1488305592
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.4251311369
Short name T637
Test name
Test status
Simulation time 4071847846 ps
CPU time 4.69 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:53 PM PDT 24
Peak memory 206672 kb
Host smart-ecc90482-376d-4b6d-bb0d-591a0f970bbc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4251311369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.4251311369
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1416835706
Short name T1127
Test name
Test status
Simulation time 13379215344 ps
CPU time 13.12 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:56:09 PM PDT 24
Peak memory 206520 kb
Host smart-7c3cc32e-3745-473d-bd84-cbf9afe4f440
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1416835706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1416835706
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1277088400
Short name T2560
Test name
Test status
Simulation time 23377790603 ps
CPU time 28.86 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:56:23 PM PDT 24
Peak memory 206524 kb
Host smart-b9548bd2-c2f7-41e6-92d3-146d6e0b2dd8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1277088400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1277088400
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.833400135
Short name T2333
Test name
Test status
Simulation time 217615372 ps
CPU time 0.81 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:55:43 PM PDT 24
Peak memory 206452 kb
Host smart-66865fdc-86d8-4297-8230-bfe582b41109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83340
0135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.833400135
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2822984850
Short name T751
Test name
Test status
Simulation time 200590433 ps
CPU time 0.83 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206452 kb
Host smart-0dfcc0e2-77b1-43f2-96b7-a09880b46b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28229
84850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2822984850
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3418527047
Short name T2580
Test name
Test status
Simulation time 352981365 ps
CPU time 1.26 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206476 kb
Host smart-a2cea707-b820-487f-b906-53c64a51a04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
27047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3418527047
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.4246526891
Short name T1847
Test name
Test status
Simulation time 581892079 ps
CPU time 1.5 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:55:56 PM PDT 24
Peak memory 206440 kb
Host smart-a1d9d467-6e68-498c-8b7f-f1dba30f5fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42465
26891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.4246526891
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1353193634
Short name T2297
Test name
Test status
Simulation time 12907670626 ps
CPU time 22.43 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:56:19 PM PDT 24
Peak memory 206748 kb
Host smart-06a541db-53f1-4ccf-b481-ccebe843026c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
93634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1353193634
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.4281317137
Short name T552
Test name
Test status
Simulation time 355606653 ps
CPU time 1.2 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206456 kb
Host smart-ce8187fe-4726-47ad-affd-90e8ca52da3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42813
17137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.4281317137
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.769210291
Short name T2502
Test name
Test status
Simulation time 175170701 ps
CPU time 0.82 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206452 kb
Host smart-4476de4a-f922-4591-8f09-ba4acf2d8793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76921
0291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.769210291
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.2409636625
Short name T516
Test name
Test status
Simulation time 40507928 ps
CPU time 0.66 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206436 kb
Host smart-756ecebd-b346-4efb-838f-baabf1ea4220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
36625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2409636625
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.214884519
Short name T1681
Test name
Test status
Simulation time 838648847 ps
CPU time 1.99 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206604 kb
Host smart-5fa63852-95db-4e14-8cd0-7469d989bb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488
4519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.214884519
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3801573698
Short name T2598
Test name
Test status
Simulation time 205705076 ps
CPU time 1.9 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206652 kb
Host smart-0c5b7ee9-c36e-4c40-8eb8-a772778c8d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38015
73698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3801573698
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1216727937
Short name T1437
Test name
Test status
Simulation time 227087277 ps
CPU time 0.96 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206448 kb
Host smart-4d1fbd3d-045a-489b-893f-a83bb663c46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12167
27937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1216727937
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.778790840
Short name T2443
Test name
Test status
Simulation time 223340150 ps
CPU time 0.82 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206452 kb
Host smart-4422f8f4-db26-405d-ae52-eee9e6384c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77879
0840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.778790840
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3909870011
Short name T722
Test name
Test status
Simulation time 202570155 ps
CPU time 0.88 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206412 kb
Host smart-90e66737-cf7c-4945-8f00-14841a5d41d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
70011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3909870011
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.2170429880
Short name T2597
Test name
Test status
Simulation time 5677054887 ps
CPU time 22.24 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:56:10 PM PDT 24
Peak memory 206664 kb
Host smart-a516972b-a5ff-448a-8155-20a2440a6c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704
29880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.2170429880
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3859510848
Short name T2709
Test name
Test status
Simulation time 273978173 ps
CPU time 0.91 seconds
Started Jul 17 07:55:53 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206452 kb
Host smart-dc41f1df-98cb-4d46-8a68-0af67b31c9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38595
10848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3859510848
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2900904247
Short name T1527
Test name
Test status
Simulation time 23303112484 ps
CPU time 22.43 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:56:20 PM PDT 24
Peak memory 206512 kb
Host smart-a81526b9-0509-4f21-a123-752c8d3a879b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29009
04247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2900904247
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.65851027
Short name T2494
Test name
Test status
Simulation time 3349813891 ps
CPU time 4.46 seconds
Started Jul 17 07:55:53 PM PDT 24
Finished Jul 17 07:56:04 PM PDT 24
Peak memory 206520 kb
Host smart-89501f81-b759-4d15-8844-55c024efd717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65851
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.65851027
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3257062594
Short name T1875
Test name
Test status
Simulation time 10039801423 ps
CPU time 275.26 seconds
Started Jul 17 07:55:53 PM PDT 24
Finished Jul 17 08:00:35 PM PDT 24
Peak memory 206720 kb
Host smart-99ff057e-c282-4def-b842-1571ae34451d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570
62594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3257062594
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3757354630
Short name T2440
Test name
Test status
Simulation time 3827129662 ps
CPU time 26.71 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:56:24 PM PDT 24
Peak memory 206612 kb
Host smart-788ca807-b67b-40cd-a518-5da6a382390a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3757354630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3757354630
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1499195829
Short name T29
Test name
Test status
Simulation time 253833998 ps
CPU time 0.95 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206452 kb
Host smart-82c56a49-f08d-47a9-abcf-1140f214d0e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1499195829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1499195829
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.639668861
Short name T354
Test name
Test status
Simulation time 195607459 ps
CPU time 0.88 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:50 PM PDT 24
Peak memory 206404 kb
Host smart-371293a4-72df-4e74-bb16-2678ec95ea25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63966
8861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.639668861
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2660124779
Short name T1689
Test name
Test status
Simulation time 4224058681 ps
CPU time 31.49 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:31 PM PDT 24
Peak memory 206652 kb
Host smart-645ef9d0-55de-4374-8eec-0fc937901dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26601
24779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2660124779
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1486894730
Short name T1348
Test name
Test status
Simulation time 4713997332 ps
CPU time 42.38 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:56:40 PM PDT 24
Peak memory 206648 kb
Host smart-1943b7cb-9da3-449e-a21a-81e04ead28d1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1486894730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1486894730
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3648050357
Short name T1427
Test name
Test status
Simulation time 185324626 ps
CPU time 0.82 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206452 kb
Host smart-5e84e055-1d4d-4871-97f6-1a2c6a395776
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3648050357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3648050357
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3966957633
Short name T900
Test name
Test status
Simulation time 174976897 ps
CPU time 0.81 seconds
Started Jul 17 07:55:39 PM PDT 24
Finished Jul 17 07:55:41 PM PDT 24
Peak memory 206444 kb
Host smart-7484c7ee-ef45-4a00-bb0b-6f7ad97f4df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39669
57633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3966957633
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.621415561
Short name T999
Test name
Test status
Simulation time 155558740 ps
CPU time 0.8 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:55:55 PM PDT 24
Peak memory 206448 kb
Host smart-d8526c95-dc32-48ce-a187-1327506d7cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62141
5561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.621415561
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2113778110
Short name T1773
Test name
Test status
Simulation time 205382597 ps
CPU time 0.89 seconds
Started Jul 17 07:55:45 PM PDT 24
Finished Jul 17 07:55:52 PM PDT 24
Peak memory 206456 kb
Host smart-4b451743-d091-4b8e-a3c6-37b07bf230f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21137
78110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2113778110
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.119745348
Short name T2332
Test name
Test status
Simulation time 170367053 ps
CPU time 0.82 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:55:55 PM PDT 24
Peak memory 206456 kb
Host smart-75f1e313-2a75-44e7-bce5-6c262020201b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11974
5348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.119745348
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1063583890
Short name T165
Test name
Test status
Simulation time 153979411 ps
CPU time 0.77 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:55:44 PM PDT 24
Peak memory 206456 kb
Host smart-6b348e52-22fc-40ce-9b4d-5930dd67875b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10635
83890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1063583890
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3791475217
Short name T1711
Test name
Test status
Simulation time 266448146 ps
CPU time 0.99 seconds
Started Jul 17 07:55:42 PM PDT 24
Finished Jul 17 07:55:46 PM PDT 24
Peak memory 206452 kb
Host smart-94a33e74-fd3c-483e-9347-d1e27ab8c3bc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3791475217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3791475217
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2564201304
Short name T2697
Test name
Test status
Simulation time 95462297 ps
CPU time 0.71 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206428 kb
Host smart-8b140a72-7d26-4cfc-9744-a56d500a07c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25642
01304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2564201304
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2069228770
Short name T1002
Test name
Test status
Simulation time 7375113502 ps
CPU time 18.66 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:56:13 PM PDT 24
Peak memory 206688 kb
Host smart-53f2f923-c278-42c1-83a4-4ac4305b24e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20692
28770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2069228770
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3535984511
Short name T1621
Test name
Test status
Simulation time 148524830 ps
CPU time 0.82 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:47 PM PDT 24
Peak memory 206460 kb
Host smart-d48912c0-4155-47ed-b5c3-e1c49a65c2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35359
84511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3535984511
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2490203033
Short name T1716
Test name
Test status
Simulation time 203873664 ps
CPU time 0.89 seconds
Started Jul 17 07:55:42 PM PDT 24
Finished Jul 17 07:55:47 PM PDT 24
Peak memory 206404 kb
Host smart-207c6ce5-6402-4473-a000-024996982acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24902
03033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2490203033
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3740848537
Short name T864
Test name
Test status
Simulation time 189767523 ps
CPU time 0.85 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:49 PM PDT 24
Peak memory 206460 kb
Host smart-244c6ad9-328c-42cd-bc54-e0ad30f4f5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37408
48537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3740848537
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2079356824
Short name T1435
Test name
Test status
Simulation time 217235564 ps
CPU time 0.89 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:49 PM PDT 24
Peak memory 206444 kb
Host smart-191733a9-9980-4977-a0ce-4c4104e94ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20793
56824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2079356824
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2891609537
Short name T1997
Test name
Test status
Simulation time 150329601 ps
CPU time 0.81 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:49 PM PDT 24
Peak memory 206456 kb
Host smart-9f920870-0155-48d4-ae26-9497f4b2cac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28916
09537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2891609537
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3622922650
Short name T686
Test name
Test status
Simulation time 151326894 ps
CPU time 0.81 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206440 kb
Host smart-74297bf2-a239-4d93-b1b3-470a804e8178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36229
22650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3622922650
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1741445274
Short name T2052
Test name
Test status
Simulation time 207121742 ps
CPU time 0.85 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:49 PM PDT 24
Peak memory 206460 kb
Host smart-400fc8ed-7472-4553-a123-f7aa03f7789e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17414
45274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1741445274
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3875435651
Short name T1252
Test name
Test status
Simulation time 216250398 ps
CPU time 0.87 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206456 kb
Host smart-71a5e316-90d5-4bde-8194-341332aa9faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38754
35651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3875435651
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.4036493644
Short name T379
Test name
Test status
Simulation time 4105196326 ps
CPU time 37.56 seconds
Started Jul 17 07:55:46 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 206684 kb
Host smart-293f665d-c996-4bf2-a738-6a7b7136aad9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4036493644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.4036493644
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1722547382
Short name T2005
Test name
Test status
Simulation time 185239145 ps
CPU time 0.87 seconds
Started Jul 17 07:55:41 PM PDT 24
Finished Jul 17 07:55:45 PM PDT 24
Peak memory 206460 kb
Host smart-aea89b24-00ea-440a-9346-20dc31194910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17225
47382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1722547382
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3641418898
Short name T1563
Test name
Test status
Simulation time 250222385 ps
CPU time 0.92 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206472 kb
Host smart-15bc6843-007c-4af9-94ed-98da6668576f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36414
18898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3641418898
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1943100223
Short name T2358
Test name
Test status
Simulation time 570919917 ps
CPU time 1.43 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206480 kb
Host smart-acc3f0f1-2d3d-4541-ad26-4fbbbbdda20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19431
00223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1943100223
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.847153867
Short name T2272
Test name
Test status
Simulation time 3455257439 ps
CPU time 24.65 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:56:19 PM PDT 24
Peak memory 206692 kb
Host smart-e7154095-9be3-4d2a-874d-25c227dd319d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84715
3867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.847153867
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.133591532
Short name T1365
Test name
Test status
Simulation time 3987485598 ps
CPU time 4.66 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:56:02 PM PDT 24
Peak memory 206524 kb
Host smart-cb91233c-f2cd-4ff0-8968-70ac2d006c96
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=133591532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.133591532
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3389370306
Short name T1608
Test name
Test status
Simulation time 13349895920 ps
CPU time 12.33 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206500 kb
Host smart-35c35bfc-e7cf-44d0-a1e3-f52c11124c07
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3389370306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3389370306
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3787253044
Short name T2621
Test name
Test status
Simulation time 23375824327 ps
CPU time 22.83 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:56:21 PM PDT 24
Peak memory 206520 kb
Host smart-09d0a4cd-0b4a-4e63-bf19-7d4a91a1cc88
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3787253044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3787253044
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.4252060695
Short name T962
Test name
Test status
Simulation time 197310982 ps
CPU time 0.85 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:55:59 PM PDT 24
Peak memory 206452 kb
Host smart-fb3e1640-1fb6-41c9-9d1a-b4f265e3bb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42520
60695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.4252060695
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2266369564
Short name T733
Test name
Test status
Simulation time 149499928 ps
CPU time 0.76 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206452 kb
Host smart-ef62a5f5-f7e8-4dd0-890c-ca704da54c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22663
69564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2266369564
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2770084873
Short name T2027
Test name
Test status
Simulation time 542847462 ps
CPU time 1.53 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:01 PM PDT 24
Peak memory 206672 kb
Host smart-4a5ce55d-b958-492e-9d16-5ad1b45bfbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27700
84873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2770084873
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2762444466
Short name T2170
Test name
Test status
Simulation time 925954474 ps
CPU time 1.99 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206660 kb
Host smart-90270fce-4191-4223-bc76-bf42b1bcbbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27624
44466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2762444466
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3915276680
Short name T170
Test name
Test status
Simulation time 13389806328 ps
CPU time 22.36 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:56:18 PM PDT 24
Peak memory 206700 kb
Host smart-03920195-2842-4f62-bded-358bed27412f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39152
76680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3915276680
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2376154021
Short name T1297
Test name
Test status
Simulation time 426558133 ps
CPU time 1.43 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206460 kb
Host smart-5f5f04f7-6853-4b6a-b51b-40fd7a67eeed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
54021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2376154021
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1886540695
Short name T2255
Test name
Test status
Simulation time 143570956 ps
CPU time 0.76 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206412 kb
Host smart-2ab17732-5cc2-4f8f-950c-d839ee8bb947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
40695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1886540695
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2003638877
Short name T2343
Test name
Test status
Simulation time 41542844 ps
CPU time 0.72 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:55:59 PM PDT 24
Peak memory 206440 kb
Host smart-876eee54-aec9-4fab-8ce3-0cb93a9526d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20036
38877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2003638877
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.154815126
Short name T1796
Test name
Test status
Simulation time 889811031 ps
CPU time 2.08 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:55:59 PM PDT 24
Peak memory 206600 kb
Host smart-a43a3914-bbc1-4d73-bc17-eb011fd6e3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481
5126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.154815126
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1673244328
Short name T2634
Test name
Test status
Simulation time 161903490 ps
CPU time 1.44 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:55:59 PM PDT 24
Peak memory 206612 kb
Host smart-3c76f926-1b8a-4986-8ac8-ef97d62095c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16732
44328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1673244328
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.390083885
Short name T964
Test name
Test status
Simulation time 196804726 ps
CPU time 0.89 seconds
Started Jul 17 07:55:53 PM PDT 24
Finished Jul 17 07:56:01 PM PDT 24
Peak memory 206456 kb
Host smart-d8b7964a-cc48-4b3c-be38-5021326c36f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39008
3885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.390083885
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.206273379
Short name T2553
Test name
Test status
Simulation time 149199514 ps
CPU time 0.8 seconds
Started Jul 17 07:55:53 PM PDT 24
Finished Jul 17 07:56:01 PM PDT 24
Peak memory 206460 kb
Host smart-e61610e0-40cf-4c4b-bc0a-4701c24cf58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20627
3379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.206273379
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1139493179
Short name T1726
Test name
Test status
Simulation time 179703088 ps
CPU time 0.8 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:55:58 PM PDT 24
Peak memory 206444 kb
Host smart-422bc1cb-4c04-4b44-b2ef-8131ef3aa1e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11394
93179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1139493179
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1330849250
Short name T2215
Test name
Test status
Simulation time 9773605178 ps
CPU time 271.98 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206652 kb
Host smart-f00a2c8a-eb1e-4a51-9c6a-488d828b9ab0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1330849250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1330849250
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1864336640
Short name T1765
Test name
Test status
Simulation time 193719151 ps
CPU time 0.82 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206456 kb
Host smart-fc755336-8c44-4a0c-9528-59074f9becda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18643
36640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1864336640
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.725338616
Short name T778
Test name
Test status
Simulation time 23281181152 ps
CPU time 25.67 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:25 PM PDT 24
Peak memory 206500 kb
Host smart-a9269e89-9ff1-4d8a-a9f4-28b2341d9f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72533
8616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.725338616
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3851087229
Short name T2078
Test name
Test status
Simulation time 3259807572 ps
CPU time 4.18 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:03 PM PDT 24
Peak memory 206524 kb
Host smart-c6c847f9-458c-48e3-98de-b733ebfe3258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38510
87229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3851087229
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3919304614
Short name T1673
Test name
Test status
Simulation time 9999039256 ps
CPU time 261.75 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 08:00:18 PM PDT 24
Peak memory 206728 kb
Host smart-1b1cce01-cfc0-44b6-916a-74824537d724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39193
04614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3919304614
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.4024083852
Short name T531
Test name
Test status
Simulation time 3751362846 ps
CPU time 102.7 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:57:42 PM PDT 24
Peak memory 206664 kb
Host smart-ad360773-1e5e-4ceb-9c32-a70dc42fcffe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4024083852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.4024083852
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2570612783
Short name T356
Test name
Test status
Simulation time 243593756 ps
CPU time 0.9 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206416 kb
Host smart-888b0d06-ff93-431d-b2c3-0c15ae568953
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2570612783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2570612783
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2784430833
Short name T1
Test name
Test status
Simulation time 191807587 ps
CPU time 0.86 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:55:43 PM PDT 24
Peak memory 206448 kb
Host smart-77c36611-3a25-4343-84a0-38d3ac558c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27844
30833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2784430833
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.291891486
Short name T1259
Test name
Test status
Simulation time 5179394741 ps
CPU time 142.4 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:58:05 PM PDT 24
Peak memory 206656 kb
Host smart-0120c1fe-8df3-4cfd-a60c-a1a644ac72c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
1486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.291891486
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3555089178
Short name T1168
Test name
Test status
Simulation time 7405362269 ps
CPU time 196.41 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:59:05 PM PDT 24
Peak memory 206660 kb
Host smart-47a2b373-3f2c-48cc-911c-981f4080fc40
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3555089178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3555089178
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3099647062
Short name T447
Test name
Test status
Simulation time 160511396 ps
CPU time 0.78 seconds
Started Jul 17 07:55:38 PM PDT 24
Finished Jul 17 07:55:41 PM PDT 24
Peak memory 206448 kb
Host smart-d17dd64f-9661-472c-891f-a8038f19b835
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3099647062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3099647062
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.421387821
Short name T1882
Test name
Test status
Simulation time 162537176 ps
CPU time 0.8 seconds
Started Jul 17 07:55:45 PM PDT 24
Finished Jul 17 07:55:51 PM PDT 24
Peak memory 206444 kb
Host smart-cba4d7ff-84c1-44b9-b6b3-957f10fac0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42138
7821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.421387821
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3983808433
Short name T1703
Test name
Test status
Simulation time 209744510 ps
CPU time 0.83 seconds
Started Jul 17 07:55:38 PM PDT 24
Finished Jul 17 07:55:41 PM PDT 24
Peak memory 206444 kb
Host smart-a7d33220-6d2c-4fcc-b668-84bae06398fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39838
08433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3983808433
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2977387728
Short name T1580
Test name
Test status
Simulation time 176865212 ps
CPU time 0.84 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206436 kb
Host smart-04df803e-8c68-487d-b264-b99549ea92f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29773
87728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2977387728
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2993220503
Short name T2145
Test name
Test status
Simulation time 200855578 ps
CPU time 0.82 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:55:55 PM PDT 24
Peak memory 206456 kb
Host smart-ffb35055-59ab-42ae-b577-e174a8873ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29932
20503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2993220503
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.301674335
Short name T553
Test name
Test status
Simulation time 289241612 ps
CPU time 0.96 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206456 kb
Host smart-f29d4f38-1418-46ac-8c67-731c9722112b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=301674335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.301674335
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.926699709
Short name T2283
Test name
Test status
Simulation time 155924466 ps
CPU time 0.77 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:55:56 PM PDT 24
Peak memory 206452 kb
Host smart-c29c0452-2117-46cd-ac90-3fcf2f6a400c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92669
9709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.926699709
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2689993151
Short name T241
Test name
Test status
Simulation time 20381552706 ps
CPU time 45.56 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:56:35 PM PDT 24
Peak memory 206740 kb
Host smart-77d526ae-56dd-48a0-a034-409483d2a6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26899
93151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2689993151
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3077899994
Short name T2043
Test name
Test status
Simulation time 186197987 ps
CPU time 0.87 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:47 PM PDT 24
Peak memory 206460 kb
Host smart-e31e2c31-4858-4cc2-9859-d708a2d81d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30778
99994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3077899994
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3817965482
Short name T1063
Test name
Test status
Simulation time 206365029 ps
CPU time 0.87 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206452 kb
Host smart-54697f92-0978-447b-b98f-0e532cbfe24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38179
65482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3817965482
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.159878584
Short name T685
Test name
Test status
Simulation time 277723356 ps
CPU time 0.87 seconds
Started Jul 17 07:55:42 PM PDT 24
Finished Jul 17 07:55:46 PM PDT 24
Peak memory 206452 kb
Host smart-6ee1d78d-238f-465c-9d5b-4e771b6bc2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15987
8584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.159878584
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2903279174
Short name T2707
Test name
Test status
Simulation time 208257471 ps
CPU time 0.88 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:49 PM PDT 24
Peak memory 206464 kb
Host smart-e96604d7-1d89-4fcb-a64f-f70d8b68795e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29032
79174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2903279174
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.711005606
Short name T2676
Test name
Test status
Simulation time 134587302 ps
CPU time 0.81 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206448 kb
Host smart-75fa1c96-f6df-4f49-81b8-cb71db567f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71100
5606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.711005606
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1854778273
Short name T1216
Test name
Test status
Simulation time 163131748 ps
CPU time 0.77 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:55:56 PM PDT 24
Peak memory 206448 kb
Host smart-6dbac46b-baa3-4165-ad82-bbbf27bfc6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
78273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1854778273
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1575752323
Short name T1035
Test name
Test status
Simulation time 159195060 ps
CPU time 0.81 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:55:55 PM PDT 24
Peak memory 206436 kb
Host smart-69610979-9e91-45b2-a64a-cf0a2ddaef2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15757
52323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1575752323
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2881139368
Short name T2081
Test name
Test status
Simulation time 182486554 ps
CPU time 0.83 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:55:55 PM PDT 24
Peak memory 206436 kb
Host smart-83a6c07d-dc8a-46e8-a18f-6ec7df9d1655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811
39368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2881139368
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2920586556
Short name T1921
Test name
Test status
Simulation time 3807528913 ps
CPU time 98.3 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:57:33 PM PDT 24
Peak memory 206680 kb
Host smart-3bf897f5-39b0-4f17-b3d8-5cd21385987c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2920586556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2920586556
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2396055591
Short name T627
Test name
Test status
Simulation time 169855608 ps
CPU time 0.79 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:55:56 PM PDT 24
Peak memory 206420 kb
Host smart-510d051f-1daa-42fa-8258-b47ac1dff44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23960
55591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2396055591
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3135634264
Short name T842
Test name
Test status
Simulation time 183484818 ps
CPU time 0.79 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206460 kb
Host smart-2ff48e04-f419-4003-a70c-3db802627306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31356
34264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3135634264
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.3359165508
Short name T339
Test name
Test status
Simulation time 1287331435 ps
CPU time 2.63 seconds
Started Jul 17 07:55:50 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206636 kb
Host smart-87265eb5-cd04-490a-b021-48bbe8345c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33591
65508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.3359165508
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2091574513
Short name T1421
Test name
Test status
Simulation time 7722643701 ps
CPU time 68.23 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:57:08 PM PDT 24
Peak memory 206732 kb
Host smart-ecc8b5c1-0e18-46ab-a6ec-5e1e14eed3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
74513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2091574513
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2651431065
Short name T2431
Test name
Test status
Simulation time 38138202 ps
CPU time 0.68 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:04 PM PDT 24
Peak memory 206440 kb
Host smart-15aa8365-7edf-4150-9999-00df72132728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2651431065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2651431065
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1894169741
Short name T1280
Test name
Test status
Simulation time 13335966613 ps
CPU time 12.18 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:56:10 PM PDT 24
Peak memory 206668 kb
Host smart-6634e8a6-c560-4fda-9d06-ed633c9bd417
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1894169741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1894169741
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2655619711
Short name T738
Test name
Test status
Simulation time 23398495673 ps
CPU time 23.65 seconds
Started Jul 17 07:55:52 PM PDT 24
Finished Jul 17 07:56:23 PM PDT 24
Peak memory 206524 kb
Host smart-62725e72-878c-4fce-93c6-36fd29e96f37
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2655619711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2655619711
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.306536252
Short name T2748
Test name
Test status
Simulation time 195394179 ps
CPU time 0.84 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:55:59 PM PDT 24
Peak memory 206360 kb
Host smart-c8394c58-8673-40fa-bdef-505ac30f2823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30653
6252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.306536252
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1352980931
Short name T1570
Test name
Test status
Simulation time 142773818 ps
CPU time 0.73 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:55:59 PM PDT 24
Peak memory 206408 kb
Host smart-15ec8193-4e25-4681-a373-cc474ab43dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13529
80931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1352980931
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1412937463
Short name T105
Test name
Test status
Simulation time 550377221 ps
CPU time 1.66 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:55:59 PM PDT 24
Peak memory 206664 kb
Host smart-b2230711-9ca3-40f0-a2f5-77f0c8c1dcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14129
37463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1412937463
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1909373194
Short name T1130
Test name
Test status
Simulation time 1422990231 ps
CPU time 3.38 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:53 PM PDT 24
Peak memory 206660 kb
Host smart-e3cb8719-0eb3-45f2-9217-18d2c2e45ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19093
73194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1909373194
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.2164460310
Short name T1871
Test name
Test status
Simulation time 7256506694 ps
CPU time 15.93 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:56:14 PM PDT 24
Peak memory 206636 kb
Host smart-d63b5fb8-1331-45cd-9cb2-6e2e454fd013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21644
60310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2164460310
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.1299277989
Short name T2464
Test name
Test status
Simulation time 348195444 ps
CPU time 1.25 seconds
Started Jul 17 07:55:54 PM PDT 24
Finished Jul 17 07:56:01 PM PDT 24
Peak memory 206464 kb
Host smart-b4fcd906-82b1-44ec-bb23-945296619eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12992
77989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.1299277989
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_enable.2911002662
Short name T668
Test name
Test status
Simulation time 56915993 ps
CPU time 0.69 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:55:55 PM PDT 24
Peak memory 206444 kb
Host smart-e5dd9134-c63a-4939-8673-bf11569278bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110
02662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2911002662
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2650280254
Short name T795
Test name
Test status
Simulation time 1046325688 ps
CPU time 2.31 seconds
Started Jul 17 07:55:51 PM PDT 24
Finished Jul 17 07:56:01 PM PDT 24
Peak memory 206604 kb
Host smart-48016193-3988-4337-8f71-afd9fdbfecb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26502
80254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2650280254
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1664663668
Short name T984
Test name
Test status
Simulation time 154898327 ps
CPU time 1.37 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:05 PM PDT 24
Peak memory 206644 kb
Host smart-b02b91e7-1d2f-4aa5-957e-d70b261d7b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16646
63668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1664663668
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1795402388
Short name T1221
Test name
Test status
Simulation time 255184902 ps
CPU time 0.85 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:07 PM PDT 24
Peak memory 206448 kb
Host smart-d921d10f-6d9b-4558-b26a-b64f9857b08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
02388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1795402388
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.88045271
Short name T424
Test name
Test status
Simulation time 145847398 ps
CPU time 0.82 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206452 kb
Host smart-2ef623ef-449c-4f4a-92d9-1f6b9a954c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88045
271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.88045271
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1227813228
Short name T2495
Test name
Test status
Simulation time 212595098 ps
CPU time 0.85 seconds
Started Jul 17 07:56:05 PM PDT 24
Finished Jul 17 07:56:09 PM PDT 24
Peak memory 206456 kb
Host smart-4fdcd872-9a50-4ea8-9546-fd04a0c3a49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12278
13228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1227813228
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.2855075012
Short name T564
Test name
Test status
Simulation time 9892183664 ps
CPU time 284.29 seconds
Started Jul 17 07:56:00 PM PDT 24
Finished Jul 17 08:00:47 PM PDT 24
Peak memory 206840 kb
Host smart-7b2d4da4-548d-43fc-a85f-1f0ce9b94bb7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2855075012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2855075012
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.627118730
Short name T821
Test name
Test status
Simulation time 4769392675 ps
CPU time 17.52 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:21 PM PDT 24
Peak memory 206644 kb
Host smart-d020e040-8435-4bf4-b2a2-9c076be4633b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62711
8730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.627118730
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.294509663
Short name T1488
Test name
Test status
Simulation time 222620362 ps
CPU time 0.89 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:10 PM PDT 24
Peak memory 206444 kb
Host smart-8a3fb84e-2f97-47a2-9b20-5bd10149e1b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29450
9663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.294509663
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2871570617
Short name T2321
Test name
Test status
Simulation time 23322113885 ps
CPU time 24.44 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 206508 kb
Host smart-2c5ac5c5-990e-462e-8d9f-a0ca1d71cb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28715
70617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2871570617
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3485198425
Short name T2307
Test name
Test status
Simulation time 3264252309 ps
CPU time 3.61 seconds
Started Jul 17 07:56:04 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206524 kb
Host smart-52b774c0-37b4-4f75-9f81-488daad0b58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34851
98425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3485198425
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2747459493
Short name T492
Test name
Test status
Simulation time 12507466403 ps
CPU time 87.9 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:57:32 PM PDT 24
Peak memory 206764 kb
Host smart-731e7624-d27a-4f78-895e-4d7d48585eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27474
59493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2747459493
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3827205482
Short name T2551
Test name
Test status
Simulation time 7490918448 ps
CPU time 203.2 seconds
Started Jul 17 07:55:59 PM PDT 24
Finished Jul 17 07:59:25 PM PDT 24
Peak memory 206656 kb
Host smart-8a6a0283-99c2-453e-9447-2dc740b86302
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3827205482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3827205482
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.795187472
Short name T389
Test name
Test status
Simulation time 243187089 ps
CPU time 0.97 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:05 PM PDT 24
Peak memory 206332 kb
Host smart-e04232ff-1609-47d6-af34-fbd16e77b28e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=795187472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.795187472
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3356200235
Short name T774
Test name
Test status
Simulation time 253088713 ps
CPU time 0.96 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206456 kb
Host smart-1bdc2e8b-bd5a-48ac-a535-b85f3c8527cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562
00235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3356200235
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.797770301
Short name T2195
Test name
Test status
Simulation time 3909260079 ps
CPU time 107.44 seconds
Started Jul 17 07:56:00 PM PDT 24
Finished Jul 17 07:57:50 PM PDT 24
Peak memory 206620 kb
Host smart-f6d073cb-5abe-4a4c-a6e8-a53c00a38c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79777
0301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.797770301
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.3045378075
Short name T1256
Test name
Test status
Simulation time 4606568964 ps
CPU time 127.93 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:58:14 PM PDT 24
Peak memory 206648 kb
Host smart-e0316d87-0e34-4051-a7ea-e2dffe4ee420
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3045378075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.3045378075
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2313784401
Short name T2146
Test name
Test status
Simulation time 156516054 ps
CPU time 0.83 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:10 PM PDT 24
Peak memory 206420 kb
Host smart-0a1d364e-e11d-4a6a-b22c-d20c8f214ba0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2313784401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2313784401
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.853251277
Short name T1757
Test name
Test status
Simulation time 147698157 ps
CPU time 0.79 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:06 PM PDT 24
Peak memory 206456 kb
Host smart-ffd0e8f4-4b47-420d-a527-3ffcdba4667a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85325
1277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.853251277
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1644444066
Short name T2461
Test name
Test status
Simulation time 165702950 ps
CPU time 0.81 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206456 kb
Host smart-ba742e57-b4a9-4b2c-bde5-4c8d8e4d9bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16444
44066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1644444066
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.4132507116
Short name T2376
Test name
Test status
Simulation time 231475306 ps
CPU time 0.89 seconds
Started Jul 17 07:55:59 PM PDT 24
Finished Jul 17 07:56:03 PM PDT 24
Peak memory 206456 kb
Host smart-2be071e9-9683-42ed-bb41-e3dc76d93fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41325
07116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.4132507116
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1797323732
Short name T2629
Test name
Test status
Simulation time 180909062 ps
CPU time 0.87 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:04 PM PDT 24
Peak memory 206476 kb
Host smart-c07d43e5-93b2-464a-af88-2814d52261c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17973
23732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1797323732
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3958565097
Short name T1439
Test name
Test status
Simulation time 165603208 ps
CPU time 0.79 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:07 PM PDT 24
Peak memory 206456 kb
Host smart-91f598a6-6d38-4e0d-bf9c-33eb0c090622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
65097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3958565097
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2984735836
Short name T1346
Test name
Test status
Simulation time 154772559 ps
CPU time 0.78 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206460 kb
Host smart-fa724df3-f969-4957-8808-3b05b0835367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29847
35836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2984735836
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.369924706
Short name T1710
Test name
Test status
Simulation time 279483158 ps
CPU time 1.03 seconds
Started Jul 17 07:55:59 PM PDT 24
Finished Jul 17 07:56:03 PM PDT 24
Peak memory 206404 kb
Host smart-11f1a47e-f38b-4d48-97b6-ef69a359b0cd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=369924706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.369924706
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1932520589
Short name T773
Test name
Test status
Simulation time 149734313 ps
CPU time 0.75 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206476 kb
Host smart-88d2c715-9feb-4fdc-b68d-fde6820306d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19325
20589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1932520589
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2997584561
Short name T2259
Test name
Test status
Simulation time 32216841 ps
CPU time 0.65 seconds
Started Jul 17 07:56:00 PM PDT 24
Finished Jul 17 07:56:03 PM PDT 24
Peak memory 206452 kb
Host smart-3e712694-1f10-4e09-a2b1-5d9fbc009650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29975
84561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2997584561
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3173145128
Short name T1880
Test name
Test status
Simulation time 18742711648 ps
CPU time 41.49 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:52 PM PDT 24
Peak memory 206720 kb
Host smart-0bc9f8c4-2fd8-48de-8fcf-7869baa91fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31731
45128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3173145128
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3687446371
Short name T1727
Test name
Test status
Simulation time 154382095 ps
CPU time 0.8 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:04 PM PDT 24
Peak memory 206432 kb
Host smart-6744b0bd-00ca-4cb3-a916-29ff82d20716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36874
46371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3687446371
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2528511262
Short name T1374
Test name
Test status
Simulation time 258310824 ps
CPU time 0.94 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206460 kb
Host smart-1127ea00-142e-41a8-a396-bc72d9a3e19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25285
11262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2528511262
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1800954783
Short name T2188
Test name
Test status
Simulation time 186677162 ps
CPU time 0.88 seconds
Started Jul 17 07:55:59 PM PDT 24
Finished Jul 17 07:56:03 PM PDT 24
Peak memory 206464 kb
Host smart-a7854f46-06d1-4956-9060-a6b504593b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18009
54783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1800954783
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2562343744
Short name T232
Test name
Test status
Simulation time 167672747 ps
CPU time 0.86 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:07 PM PDT 24
Peak memory 206456 kb
Host smart-3b721138-2b72-4783-8cf1-eb667e642733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25623
43744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2562343744
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2636989403
Short name T1414
Test name
Test status
Simulation time 144315094 ps
CPU time 0.82 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:05 PM PDT 24
Peak memory 206456 kb
Host smart-86346305-d186-4021-af72-bfba7d2eef5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26369
89403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2636989403
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.936736686
Short name T440
Test name
Test status
Simulation time 164351096 ps
CPU time 0.87 seconds
Started Jul 17 07:55:59 PM PDT 24
Finished Jul 17 07:56:03 PM PDT 24
Peak memory 206448 kb
Host smart-837b9d30-e113-4208-8c48-f01804b269c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93673
6686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.936736686
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.177938468
Short name T2042
Test name
Test status
Simulation time 158643172 ps
CPU time 0.77 seconds
Started Jul 17 07:56:00 PM PDT 24
Finished Jul 17 07:56:03 PM PDT 24
Peak memory 206428 kb
Host smart-ee7c2347-65c2-435c-bba7-2fa77ea5018f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17793
8468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.177938468
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1118486823
Short name T2471
Test name
Test status
Simulation time 239173342 ps
CPU time 0.89 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206452 kb
Host smart-fd63b14b-c326-43ec-a652-632b58166f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11184
86823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1118486823
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2279287450
Short name T1314
Test name
Test status
Simulation time 5828202875 ps
CPU time 165.81 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:58:56 PM PDT 24
Peak memory 206588 kb
Host smart-b4618574-1240-446e-816a-00649b86b269
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2279287450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2279287450
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.4281502863
Short name T2505
Test name
Test status
Simulation time 170762853 ps
CPU time 0.83 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:05 PM PDT 24
Peak memory 206296 kb
Host smart-28739660-fd39-43a0-a91a-a9a4c54e5847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42815
02863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4281502863
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2248846015
Short name T1335
Test name
Test status
Simulation time 188654142 ps
CPU time 0.87 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:10 PM PDT 24
Peak memory 206460 kb
Host smart-d868999b-2aa9-427c-8132-880e73bc3429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22488
46015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2248846015
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.1534383356
Short name T2053
Test name
Test status
Simulation time 638751312 ps
CPU time 1.65 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206440 kb
Host smart-6f87e140-f57f-484c-98d9-cbf67b9fe059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15343
83356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.1534383356
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1382533235
Short name T664
Test name
Test status
Simulation time 5171205181 ps
CPU time 48.6 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:51 PM PDT 24
Peak memory 206732 kb
Host smart-d16ae5dd-790d-4302-a02d-13fe55d0aa93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13825
33235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1382533235
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3454846824
Short name T2248
Test name
Test status
Simulation time 75681689 ps
CPU time 0.7 seconds
Started Jul 17 07:56:05 PM PDT 24
Finished Jul 17 07:56:09 PM PDT 24
Peak memory 206400 kb
Host smart-dacf66db-d0da-4f28-9fc5-97cfca7112ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3454846824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3454846824
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3653469166
Short name T899
Test name
Test status
Simulation time 4123984094 ps
CPU time 5.84 seconds
Started Jul 17 07:56:04 PM PDT 24
Finished Jul 17 07:56:14 PM PDT 24
Peak memory 206668 kb
Host smart-7ebb1ec8-093d-4d83-8eda-574590518b8e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3653469166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3653469166
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3196196755
Short name T188
Test name
Test status
Simulation time 13358256234 ps
CPU time 11.93 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:19 PM PDT 24
Peak memory 206676 kb
Host smart-dc463b7e-962b-41be-8ab6-5ff06c91fc07
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3196196755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3196196755
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.196260196
Short name T2473
Test name
Test status
Simulation time 23374881534 ps
CPU time 23.22 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:26 PM PDT 24
Peak memory 206528 kb
Host smart-7dc2f105-a166-4d05-bd34-dd8d40ef04f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=196260196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.196260196
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.76889387
Short name T1395
Test name
Test status
Simulation time 191929393 ps
CPU time 0.87 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:07 PM PDT 24
Peak memory 206460 kb
Host smart-ff1bd232-2338-4328-bd29-183fff3343b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76889
387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.76889387
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.4184054943
Short name T1462
Test name
Test status
Simulation time 186404365 ps
CPU time 0.82 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206456 kb
Host smart-8fa691af-14af-40f9-99db-730267cab9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41840
54943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.4184054943
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2264185161
Short name T1968
Test name
Test status
Simulation time 495370568 ps
CPU time 1.53 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:09 PM PDT 24
Peak memory 206660 kb
Host smart-534c522a-10a5-4799-9402-c00f3fe9567c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22641
85161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2264185161
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2387144825
Short name T742
Test name
Test status
Simulation time 713492002 ps
CPU time 1.8 seconds
Started Jul 17 07:56:11 PM PDT 24
Finished Jul 17 07:56:15 PM PDT 24
Peak memory 206604 kb
Host smart-e5f4dbf5-2686-440f-a8c1-d11d15d0b9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23871
44825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2387144825
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.442249090
Short name T1629
Test name
Test status
Simulation time 19954909034 ps
CPU time 37.46 seconds
Started Jul 17 07:56:04 PM PDT 24
Finished Jul 17 07:56:45 PM PDT 24
Peak memory 206668 kb
Host smart-23f7243a-3a4c-4bba-9930-76b487009c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44224
9090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.442249090
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.216126996
Short name T428
Test name
Test status
Simulation time 489248230 ps
CPU time 1.41 seconds
Started Jul 17 07:56:04 PM PDT 24
Finished Jul 17 07:56:09 PM PDT 24
Peak memory 206472 kb
Host smart-68e3860c-918b-46d8-9577-9aaa8d1a06bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21612
6996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.216126996
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3080655544
Short name T35
Test name
Test status
Simulation time 141781351 ps
CPU time 0.79 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206456 kb
Host smart-c98949f5-4d2e-4593-9923-7e0b53514bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30806
55544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3080655544
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.3020403536
Short name T464
Test name
Test status
Simulation time 43012129 ps
CPU time 0.68 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:11 PM PDT 24
Peak memory 206444 kb
Host smart-d7d7ecdf-df50-4bac-8b3c-f8ffa8ab45bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30204
03536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3020403536
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2041973388
Short name T2326
Test name
Test status
Simulation time 734922288 ps
CPU time 2.08 seconds
Started Jul 17 07:56:04 PM PDT 24
Finished Jul 17 07:56:10 PM PDT 24
Peak memory 206612 kb
Host smart-66b5d987-31d4-464f-97e8-7c7169f7114b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20419
73388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2041973388
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2749189055
Short name T1889
Test name
Test status
Simulation time 156675591 ps
CPU time 1.23 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206668 kb
Host smart-50e213eb-1099-42c7-9618-461684bbd564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27491
89055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2749189055
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3391070776
Short name T565
Test name
Test status
Simulation time 271415294 ps
CPU time 0.9 seconds
Started Jul 17 07:56:04 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206408 kb
Host smart-c2ba5abe-d708-4d91-b818-5039dc747181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33910
70776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3391070776
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3022204604
Short name T36
Test name
Test status
Simulation time 187215993 ps
CPU time 0.81 seconds
Started Jul 17 07:56:01 PM PDT 24
Finished Jul 17 07:56:04 PM PDT 24
Peak memory 206448 kb
Host smart-616fb9ea-21f4-4f7a-808c-22c04aa38fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30222
04604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3022204604
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.926252029
Short name T509
Test name
Test status
Simulation time 185358157 ps
CPU time 0.83 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:10 PM PDT 24
Peak memory 206448 kb
Host smart-a39ec337-2c9d-47f0-bfc2-1a445ecc876f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92625
2029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.926252029
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3235984375
Short name T95
Test name
Test status
Simulation time 4642063541 ps
CPU time 116.91 seconds
Started Jul 17 07:56:08 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206668 kb
Host smart-6e9aef87-e342-4aba-92b6-e0039dd73178
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3235984375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3235984375
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.1811239421
Short name T86
Test name
Test status
Simulation time 4651234931 ps
CPU time 15.97 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:23 PM PDT 24
Peak memory 206676 kb
Host smart-ab3fe6d6-820a-4e2c-adb2-3342c45e7150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18112
39421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.1811239421
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1405378663
Short name T670
Test name
Test status
Simulation time 231516307 ps
CPU time 0.88 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:11 PM PDT 24
Peak memory 206440 kb
Host smart-3cee6232-fd88-4096-8e5d-ba425f10c26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14053
78663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1405378663
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2319368957
Short name T1161
Test name
Test status
Simulation time 23329025893 ps
CPU time 22.9 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:32 PM PDT 24
Peak memory 206504 kb
Host smart-5c6eb3e0-c7d0-480c-a6b4-f2f3a9530592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23193
68957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2319368957
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.4018365853
Short name T697
Test name
Test status
Simulation time 3304854680 ps
CPU time 4.42 seconds
Started Jul 17 07:56:05 PM PDT 24
Finished Jul 17 07:56:13 PM PDT 24
Peak memory 206512 kb
Host smart-ffa114ed-7317-4eff-9299-1a4c642abc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40183
65853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.4018365853
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.470707194
Short name T1353
Test name
Test status
Simulation time 9975665762 ps
CPU time 268.3 seconds
Started Jul 17 07:56:05 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206764 kb
Host smart-5d06acf9-4230-49c3-86b3-9066aa9ca503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47070
7194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.470707194
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1109579764
Short name T1313
Test name
Test status
Simulation time 7490583618 ps
CPU time 54.85 seconds
Started Jul 17 07:56:10 PM PDT 24
Finished Jul 17 07:57:07 PM PDT 24
Peak memory 206720 kb
Host smart-c280934c-409a-4905-98cd-1c47b549100d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1109579764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1109579764
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3723346158
Short name T1983
Test name
Test status
Simulation time 234764255 ps
CPU time 0.92 seconds
Started Jul 17 07:56:06 PM PDT 24
Finished Jul 17 07:56:11 PM PDT 24
Peak memory 206456 kb
Host smart-5bb8b2cd-0504-40ef-956c-fd3a4d04d251
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3723346158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3723346158
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.4088682565
Short name T1541
Test name
Test status
Simulation time 207367009 ps
CPU time 0.91 seconds
Started Jul 17 07:56:13 PM PDT 24
Finished Jul 17 07:56:16 PM PDT 24
Peak memory 206452 kb
Host smart-3d1c5336-cd28-4709-8226-5b54c1b67772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40886
82565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.4088682565
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.131797826
Short name T2529
Test name
Test status
Simulation time 5062674810 ps
CPU time 45.55 seconds
Started Jul 17 07:56:13 PM PDT 24
Finished Jul 17 07:57:00 PM PDT 24
Peak memory 206652 kb
Host smart-7b26f3ad-f669-4e0e-8b28-5b83e0d91ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13179
7826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.131797826
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3349316375
Short name T2357
Test name
Test status
Simulation time 3909001464 ps
CPU time 28.05 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:34 PM PDT 24
Peak memory 206708 kb
Host smart-2693914c-c8f4-4280-8159-083c1dbad358
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3349316375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3349316375
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3087400592
Short name T849
Test name
Test status
Simulation time 198376307 ps
CPU time 0.77 seconds
Started Jul 17 07:56:12 PM PDT 24
Finished Jul 17 07:56:15 PM PDT 24
Peak memory 206456 kb
Host smart-b1a546e8-64a0-4cd8-a047-541c6b4327a5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3087400592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3087400592
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.866018904
Short name T2550
Test name
Test status
Simulation time 147390514 ps
CPU time 0.75 seconds
Started Jul 17 07:56:09 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206456 kb
Host smart-7216df82-e28c-406f-ad28-a4af93117cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86601
8904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.866018904
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1458484116
Short name T133
Test name
Test status
Simulation time 205848335 ps
CPU time 0.89 seconds
Started Jul 17 07:56:13 PM PDT 24
Finished Jul 17 07:56:16 PM PDT 24
Peak memory 206456 kb
Host smart-7cdfc737-2cbe-47ba-b11a-25331aa0d3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584
84116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1458484116
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1812856623
Short name T92
Test name
Test status
Simulation time 157135095 ps
CPU time 0.85 seconds
Started Jul 17 07:56:13 PM PDT 24
Finished Jul 17 07:56:17 PM PDT 24
Peak memory 206448 kb
Host smart-c0ff5010-6364-4112-b140-fc047e3f7daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
56623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1812856623
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2851125863
Short name T1412
Test name
Test status
Simulation time 161676904 ps
CPU time 0.79 seconds
Started Jul 17 07:56:10 PM PDT 24
Finished Jul 17 07:56:13 PM PDT 24
Peak memory 206460 kb
Host smart-4fd0eae4-28ed-4499-824b-fddb9bcb5697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511
25863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2851125863
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1794478584
Short name T395
Test name
Test status
Simulation time 152572565 ps
CPU time 0.83 seconds
Started Jul 17 07:56:13 PM PDT 24
Finished Jul 17 07:56:16 PM PDT 24
Peak memory 206432 kb
Host smart-99e8cf58-1897-4893-b0a8-62de21b0191c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17944
78584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1794478584
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3768849119
Short name T154
Test name
Test status
Simulation time 153643729 ps
CPU time 0.81 seconds
Started Jul 17 07:56:13 PM PDT 24
Finished Jul 17 07:56:16 PM PDT 24
Peak memory 206456 kb
Host smart-a4889106-04a1-4cfc-b291-0d5f9f3c5b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37688
49119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3768849119
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2763647950
Short name T1115
Test name
Test status
Simulation time 216305452 ps
CPU time 0.94 seconds
Started Jul 17 07:56:10 PM PDT 24
Finished Jul 17 07:56:13 PM PDT 24
Peak memory 206464 kb
Host smart-f5d07a5b-3d1d-4789-a649-a3cb165e21b6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2763647950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2763647950
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1745681555
Short name T1779
Test name
Test status
Simulation time 173112806 ps
CPU time 0.81 seconds
Started Jul 17 07:56:10 PM PDT 24
Finished Jul 17 07:56:13 PM PDT 24
Peak memory 206464 kb
Host smart-9e4af7f5-88b8-46d5-a847-eac7c8e45be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17456
81555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1745681555
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.972307600
Short name T1812
Test name
Test status
Simulation time 30008069 ps
CPU time 0.68 seconds
Started Jul 17 07:56:13 PM PDT 24
Finished Jul 17 07:56:16 PM PDT 24
Peak memory 206424 kb
Host smart-74c3250c-da75-4693-97ff-4fc82eebdad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97230
7600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.972307600
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3808553910
Short name T1420
Test name
Test status
Simulation time 14817312811 ps
CPU time 33.28 seconds
Started Jul 17 07:56:13 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206736 kb
Host smart-c926195d-553b-46e0-b951-7d9077ce8a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38085
53910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3808553910
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1609107737
Short name T498
Test name
Test status
Simulation time 237553963 ps
CPU time 0.93 seconds
Started Jul 17 07:56:09 PM PDT 24
Finished Jul 17 07:56:13 PM PDT 24
Peak memory 206452 kb
Host smart-8880e59c-f800-4cbb-bd6e-8f759e4df716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16091
07737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1609107737
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3723134966
Short name T2684
Test name
Test status
Simulation time 188642847 ps
CPU time 0.8 seconds
Started Jul 17 07:56:09 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206448 kb
Host smart-5f72b442-46cf-4ef8-bf33-46b7159a3ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37231
34966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3723134966
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.924688533
Short name T747
Test name
Test status
Simulation time 172642837 ps
CPU time 0.8 seconds
Started Jul 17 07:56:09 PM PDT 24
Finished Jul 17 07:56:13 PM PDT 24
Peak memory 206448 kb
Host smart-28d4defb-8eb5-4f32-8ace-46226b00f128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92468
8533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.924688533
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2128837707
Short name T829
Test name
Test status
Simulation time 171950087 ps
CPU time 0.82 seconds
Started Jul 17 07:56:08 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206616 kb
Host smart-34124331-f974-473c-b161-5738ccd68ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21288
37707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2128837707
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.763664300
Short name T1881
Test name
Test status
Simulation time 149868241 ps
CPU time 0.73 seconds
Started Jul 17 07:56:08 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206452 kb
Host smart-029dfc95-6ab0-4e29-b410-6a9af013a2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76366
4300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.763664300
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2178468744
Short name T1649
Test name
Test status
Simulation time 151060435 ps
CPU time 0.74 seconds
Started Jul 17 07:56:09 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206444 kb
Host smart-b0d90fa6-f04a-484c-aaf3-c7172a689a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21784
68744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2178468744
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1244861143
Short name T854
Test name
Test status
Simulation time 191499036 ps
CPU time 0.83 seconds
Started Jul 17 07:56:11 PM PDT 24
Finished Jul 17 07:56:14 PM PDT 24
Peak memory 206456 kb
Host smart-81f72568-c58a-4ba7-9f94-67ace8295d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448
61143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1244861143
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3940360972
Short name T2624
Test name
Test status
Simulation time 208780413 ps
CPU time 0.96 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206464 kb
Host smart-b1bc3003-e1a9-4a21-a67c-7a1e4d000eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39403
60972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3940360972
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3240340165
Short name T1026
Test name
Test status
Simulation time 6228147762 ps
CPU time 175.45 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:59:00 PM PDT 24
Peak memory 206644 kb
Host smart-7f8130a2-ce98-4055-973f-ae9f01b948e8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3240340165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3240340165
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.749495770
Short name T1225
Test name
Test status
Simulation time 160040155 ps
CPU time 0.79 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:06 PM PDT 24
Peak memory 206460 kb
Host smart-983f79d1-6448-4942-b005-14ac6524654d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74949
5770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.749495770
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3905655003
Short name T99
Test name
Test status
Simulation time 161977494 ps
CPU time 0.83 seconds
Started Jul 17 07:56:08 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206400 kb
Host smart-9b75f060-1ba6-4cd2-9e5c-c25bf543f550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39056
55003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3905655003
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3314455827
Short name T20
Test name
Test status
Simulation time 675677186 ps
CPU time 1.61 seconds
Started Jul 17 07:56:04 PM PDT 24
Finished Jul 17 07:56:09 PM PDT 24
Peak memory 206656 kb
Host smart-20348c39-3d25-440c-a33e-b86f5d92c077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33144
55827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3314455827
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.1583269107
Short name T377
Test name
Test status
Simulation time 5492474116 ps
CPU time 50.23 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:55 PM PDT 24
Peak memory 206728 kb
Host smart-86998544-94aa-47c7-a97c-cb805ab41593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
69107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1583269107
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.3031597322
Short name T1456
Test name
Test status
Simulation time 36265228 ps
CPU time 0.67 seconds
Started Jul 17 07:56:36 PM PDT 24
Finished Jul 17 07:56:39 PM PDT 24
Peak memory 206608 kb
Host smart-907f8dcd-11cb-4c8e-9f3e-3a003147f78a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3031597322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.3031597322
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.835561793
Short name T1730
Test name
Test status
Simulation time 3492938609 ps
CPU time 4.24 seconds
Started Jul 17 07:56:02 PM PDT 24
Finished Jul 17 07:56:10 PM PDT 24
Peak memory 206496 kb
Host smart-92c64911-3273-4c45-9d9a-3fce54ea5013
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=835561793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.835561793
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2617820374
Short name T11
Test name
Test status
Simulation time 13365869487 ps
CPU time 13.06 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:20 PM PDT 24
Peak memory 206476 kb
Host smart-0ffe7d7e-c116-4c6f-ac9c-bb1708decbf1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2617820374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2617820374
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3602352779
Short name T996
Test name
Test status
Simulation time 23398002333 ps
CPU time 26.53 seconds
Started Jul 17 07:56:00 PM PDT 24
Finished Jul 17 07:56:29 PM PDT 24
Peak memory 206524 kb
Host smart-2a23630c-70c5-4537-9e73-2d4ca5855277
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3602352779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.3602352779
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3581749318
Short name T600
Test name
Test status
Simulation time 160640771 ps
CPU time 0.78 seconds
Started Jul 17 07:56:03 PM PDT 24
Finished Jul 17 07:56:08 PM PDT 24
Peak memory 206464 kb
Host smart-2ec043bf-e991-43f0-a4a9-49ecaac3efc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35817
49318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3581749318
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2309321739
Short name T762
Test name
Test status
Simulation time 153615675 ps
CPU time 0.75 seconds
Started Jul 17 07:56:23 PM PDT 24
Finished Jul 17 07:56:26 PM PDT 24
Peak memory 206624 kb
Host smart-7a1fef78-a568-48a7-825b-e1a1636a9c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23093
21739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2309321739
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1353372859
Short name T805
Test name
Test status
Simulation time 425723806 ps
CPU time 1.41 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:28 PM PDT 24
Peak memory 205904 kb
Host smart-6a5aab5c-f4fe-423d-b2cc-cf8c0ce62139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13533
72859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1353372859
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1658493747
Short name T965
Test name
Test status
Simulation time 546754866 ps
CPU time 1.32 seconds
Started Jul 17 07:56:22 PM PDT 24
Finished Jul 17 07:56:25 PM PDT 24
Peak memory 206452 kb
Host smart-2401939a-f952-4856-a876-5a6e64ee30ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16584
93747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1658493747
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.2066739931
Short name T1641
Test name
Test status
Simulation time 9374214748 ps
CPU time 16.18 seconds
Started Jul 17 07:56:21 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206656 kb
Host smart-8f701808-dca6-42da-a060-f9d0a9e8db44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20667
39931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.2066739931
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2819275079
Short name T1329
Test name
Test status
Simulation time 359751949 ps
CPU time 1.18 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:28 PM PDT 24
Peak memory 206460 kb
Host smart-7ab3a286-ac5f-47ee-923d-b10113f64f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28192
75079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2819275079
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.427702319
Short name T643
Test name
Test status
Simulation time 142290101 ps
CPU time 0.79 seconds
Started Jul 17 07:56:21 PM PDT 24
Finished Jul 17 07:56:23 PM PDT 24
Peak memory 206456 kb
Host smart-748aed33-9a14-4d47-8bf1-bd9411db3169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
2319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.427702319
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.236002131
Short name T927
Test name
Test status
Simulation time 35401661 ps
CPU time 0.66 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:28 PM PDT 24
Peak memory 206428 kb
Host smart-30039218-bd99-4c12-99b6-4ad6114cb211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23600
2131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.236002131
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3101942019
Short name T691
Test name
Test status
Simulation time 885287545 ps
CPU time 2.21 seconds
Started Jul 17 07:56:23 PM PDT 24
Finished Jul 17 07:56:27 PM PDT 24
Peak memory 206588 kb
Host smart-bbebba5f-0cc3-4816-9252-7acd9179cee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31019
42019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3101942019
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1196492867
Short name T2153
Test name
Test status
Simulation time 186235934 ps
CPU time 1.8 seconds
Started Jul 17 07:56:21 PM PDT 24
Finished Jul 17 07:56:24 PM PDT 24
Peak memory 206680 kb
Host smart-8b03ee6a-d26b-4bc2-9973-3e8a0c2f50e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11964
92867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1196492867
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.676269185
Short name T1190
Test name
Test status
Simulation time 188057331 ps
CPU time 0.86 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:28 PM PDT 24
Peak memory 206444 kb
Host smart-52ea5672-6404-49d9-95b5-4e59969531d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67626
9185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.676269185
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.249170904
Short name T2599
Test name
Test status
Simulation time 143170779 ps
CPU time 0.79 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:37 PM PDT 24
Peak memory 205888 kb
Host smart-e7c661b8-3eab-402a-885c-adb687df5e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24917
0904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.249170904
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3381547000
Short name T2365
Test name
Test status
Simulation time 229116808 ps
CPU time 0.86 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:26 PM PDT 24
Peak memory 206468 kb
Host smart-a94f382e-e811-453e-aa73-5e805d7ee69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33815
47000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3381547000
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.1000510709
Short name T1917
Test name
Test status
Simulation time 9871695051 ps
CPU time 91.68 seconds
Started Jul 17 07:56:27 PM PDT 24
Finished Jul 17 07:58:02 PM PDT 24
Peak memory 206720 kb
Host smart-4cd9465b-3217-4cb0-8f2d-c4a94c9dddaa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1000510709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1000510709
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.94403466
Short name T2044
Test name
Test status
Simulation time 4242246268 ps
CPU time 28.93 seconds
Started Jul 17 07:56:20 PM PDT 24
Finished Jul 17 07:56:50 PM PDT 24
Peak memory 206724 kb
Host smart-beb5e549-4ec0-4d3b-aaf9-b0e0a2af7fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94403
466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.94403466
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3924549103
Short name T875
Test name
Test status
Simulation time 255607125 ps
CPU time 0.92 seconds
Started Jul 17 07:56:21 PM PDT 24
Finished Jul 17 07:56:23 PM PDT 24
Peak memory 206432 kb
Host smart-5ba5bc0f-6b8a-421c-9ae2-9573ccf2996c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39245
49103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3924549103
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2877837708
Short name T1501
Test name
Test status
Simulation time 23324923038 ps
CPU time 23.74 seconds
Started Jul 17 07:56:23 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206516 kb
Host smart-dcc0d52f-3857-4dac-bd3e-974534a7c839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28778
37708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2877837708
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.4122274564
Short name T701
Test name
Test status
Simulation time 3340169217 ps
CPU time 4.02 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:32 PM PDT 24
Peak memory 206524 kb
Host smart-911d3d8e-f100-4bee-bbca-218c273c6290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41222
74564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.4122274564
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.192100890
Short name T2203
Test name
Test status
Simulation time 10052707773 ps
CPU time 271.79 seconds
Started Jul 17 07:56:23 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206744 kb
Host smart-ccc6ac71-ba81-4c9a-ac76-c196f37a7b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210
0890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.192100890
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.193537925
Short name T1873
Test name
Test status
Simulation time 4335429066 ps
CPU time 31.71 seconds
Started Jul 17 07:56:23 PM PDT 24
Finished Jul 17 07:56:56 PM PDT 24
Peak memory 206648 kb
Host smart-6862e36d-7cc0-4560-9865-2eac53d02031
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=193537925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.193537925
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.758142342
Short name T1741
Test name
Test status
Simulation time 292476608 ps
CPU time 0.96 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:26 PM PDT 24
Peak memory 206416 kb
Host smart-95edb901-0db6-4e14-b59c-0632d363562c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=758142342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.758142342
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3161219601
Short name T1787
Test name
Test status
Simulation time 229143440 ps
CPU time 0.9 seconds
Started Jul 17 07:56:21 PM PDT 24
Finished Jul 17 07:56:23 PM PDT 24
Peak memory 206460 kb
Host smart-6f129876-d464-4912-ba18-8f6f5ac0d36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31612
19601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3161219601
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1722881368
Short name T718
Test name
Test status
Simulation time 4915648854 ps
CPU time 35.88 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:57:03 PM PDT 24
Peak memory 206716 kb
Host smart-c3690316-95b6-456f-b795-c2d8a58efbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17228
81368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1722881368
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.1433749090
Short name T903
Test name
Test status
Simulation time 5477257541 ps
CPU time 38.03 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:57:05 PM PDT 24
Peak memory 206612 kb
Host smart-30437d64-2052-4ecb-9a17-5bc6c752bf39
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1433749090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.1433749090
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1443948896
Short name T2705
Test name
Test status
Simulation time 162147147 ps
CPU time 0.82 seconds
Started Jul 17 07:56:28 PM PDT 24
Finished Jul 17 07:56:31 PM PDT 24
Peak memory 206452 kb
Host smart-18c9e2a7-3ab3-4237-ba06-d96f7917161d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1443948896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1443948896
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.4116435111
Short name T1492
Test name
Test status
Simulation time 160156412 ps
CPU time 0.78 seconds
Started Jul 17 07:56:22 PM PDT 24
Finished Jul 17 07:56:24 PM PDT 24
Peak memory 206408 kb
Host smart-736679e0-7379-452d-8d9d-61c8c0af17b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164
35111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.4116435111
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1344691692
Short name T138
Test name
Test status
Simulation time 178964572 ps
CPU time 0.85 seconds
Started Jul 17 07:56:22 PM PDT 24
Finished Jul 17 07:56:24 PM PDT 24
Peak memory 206444 kb
Host smart-70118e2c-469f-4fc6-bede-c9cf9ddc2863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13446
91692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1344691692
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3422075984
Short name T1446
Test name
Test status
Simulation time 155459864 ps
CPU time 0.8 seconds
Started Jul 17 07:56:21 PM PDT 24
Finished Jul 17 07:56:23 PM PDT 24
Peak memory 206408 kb
Host smart-7e1a425d-f24d-4bfa-a42a-4cd0c11881b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34220
75984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3422075984
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3924004513
Short name T1883
Test name
Test status
Simulation time 182213502 ps
CPU time 0.84 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:29 PM PDT 24
Peak memory 206460 kb
Host smart-880a4aa9-51b6-44fb-8ca5-cf50e20c62ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39240
04513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3924004513
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2087860537
Short name T1477
Test name
Test status
Simulation time 176781125 ps
CPU time 0.82 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:29 PM PDT 24
Peak memory 206400 kb
Host smart-01c9d047-c92d-407d-9033-12da82f0cfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20878
60537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2087860537
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3748529138
Short name T2752
Test name
Test status
Simulation time 177667882 ps
CPU time 0.82 seconds
Started Jul 17 07:56:23 PM PDT 24
Finished Jul 17 07:56:25 PM PDT 24
Peak memory 206460 kb
Host smart-cb96e9b1-fd89-4cb7-8b12-a46b85b1300a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37485
29138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3748529138
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3025316074
Short name T1152
Test name
Test status
Simulation time 261653741 ps
CPU time 0.96 seconds
Started Jul 17 07:56:20 PM PDT 24
Finished Jul 17 07:56:21 PM PDT 24
Peak memory 206452 kb
Host smart-91a2aa54-a9ef-44cc-8c3f-c7385e4cfb97
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3025316074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3025316074
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1295072783
Short name T568
Test name
Test status
Simulation time 160794067 ps
CPU time 0.78 seconds
Started Jul 17 07:56:21 PM PDT 24
Finished Jul 17 07:56:23 PM PDT 24
Peak memory 206456 kb
Host smart-ef70bfdc-b4fc-49ea-8612-4f05eaaebf4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12950
72783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1295072783
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.83302027
Short name T26
Test name
Test status
Simulation time 33220406 ps
CPU time 0.72 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:37 PM PDT 24
Peak memory 206536 kb
Host smart-3ddb1cd3-d156-4263-846f-a716cd69cca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83302
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.83302027
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1034688303
Short name T2595
Test name
Test status
Simulation time 10391398158 ps
CPU time 24.62 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:53 PM PDT 24
Peak memory 206740 kb
Host smart-67cfa773-d038-4544-98c9-fe8e3e0c69c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10346
88303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1034688303
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1743017234
Short name T1793
Test name
Test status
Simulation time 192800991 ps
CPU time 0.86 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:27 PM PDT 24
Peak memory 206448 kb
Host smart-65c073a9-fb39-42a8-ae28-2fb3232c12ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17430
17234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1743017234
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1835759137
Short name T680
Test name
Test status
Simulation time 203740118 ps
CPU time 0.94 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206152 kb
Host smart-1d05f3af-f452-4afa-841a-71d51106f6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18357
59137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1835759137
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2014001947
Short name T1891
Test name
Test status
Simulation time 187739869 ps
CPU time 0.89 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:28 PM PDT 24
Peak memory 206456 kb
Host smart-2ac1ac5c-73fb-43d7-b882-5deee242e2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20140
01947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2014001947
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2990090017
Short name T953
Test name
Test status
Simulation time 180435996 ps
CPU time 0.83 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:27 PM PDT 24
Peak memory 206424 kb
Host smart-77a9b0bc-3b13-4bc6-b7d7-ce3c628d8ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29900
90017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2990090017
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.642092983
Short name T1966
Test name
Test status
Simulation time 155117496 ps
CPU time 0.71 seconds
Started Jul 17 07:56:20 PM PDT 24
Finished Jul 17 07:56:22 PM PDT 24
Peak memory 206452 kb
Host smart-8f7c187b-7d16-4b9f-91ac-3f1cef04a6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64209
2983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.642092983
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.133076703
Short name T22
Test name
Test status
Simulation time 148797445 ps
CPU time 0.76 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:29 PM PDT 24
Peak memory 206436 kb
Host smart-51054c29-2e3e-4c93-9e53-44c37f76cfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13307
6703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.133076703
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.327020671
Short name T689
Test name
Test status
Simulation time 162393817 ps
CPU time 0.79 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:29 PM PDT 24
Peak memory 206396 kb
Host smart-6fb29b22-ea9c-40d7-8d30-bc58d232627d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
0671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.327020671
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.634237538
Short name T1253
Test name
Test status
Simulation time 268010928 ps
CPU time 0.96 seconds
Started Jul 17 07:56:27 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 206448 kb
Host smart-9ad86643-a639-4a40-bd53-d956d3f450f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63423
7538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.634237538
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.80308053
Short name T1215
Test name
Test status
Simulation time 5391529244 ps
CPU time 150.72 seconds
Started Jul 17 07:56:22 PM PDT 24
Finished Jul 17 07:58:53 PM PDT 24
Peak memory 206676 kb
Host smart-c0f2536f-685b-420e-b32f-2b91934dc763
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=80308053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.80308053
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2528443058
Short name T2648
Test name
Test status
Simulation time 154827217 ps
CPU time 0.78 seconds
Started Jul 17 07:56:27 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 206432 kb
Host smart-c2dac538-db5e-49f4-a222-3df2e12dc270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25284
43058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2528443058
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2997504488
Short name T429
Test name
Test status
Simulation time 158145551 ps
CPU time 0.79 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:27 PM PDT 24
Peak memory 206228 kb
Host smart-12b15713-b4d9-4e93-9a14-9c67981566e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29975
04488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2997504488
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.477509952
Short name T1341
Test name
Test status
Simulation time 1026790223 ps
CPU time 2.32 seconds
Started Jul 17 07:56:23 PM PDT 24
Finished Jul 17 07:56:27 PM PDT 24
Peak memory 206636 kb
Host smart-a1b9db0b-73fb-432f-9d0c-99c34e7ed2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47750
9952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.477509952
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.361996014
Short name T2204
Test name
Test status
Simulation time 5199339906 ps
CPU time 146.49 seconds
Started Jul 17 07:56:27 PM PDT 24
Finished Jul 17 07:58:56 PM PDT 24
Peak memory 206612 kb
Host smart-799563a3-461a-435e-887b-4d4fe50660b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36199
6014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.361996014
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2649520660
Short name T2736
Test name
Test status
Simulation time 45062504 ps
CPU time 0.69 seconds
Started Jul 17 07:56:44 PM PDT 24
Finished Jul 17 07:56:47 PM PDT 24
Peak memory 206436 kb
Host smart-24be0162-ecc7-4558-9ed0-78c06b94d62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2649520660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2649520660
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2471031393
Short name T628
Test name
Test status
Simulation time 4148946774 ps
CPU time 5.15 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:43 PM PDT 24
Peak memory 206728 kb
Host smart-fe960935-7c3e-442f-92e7-722eaca64d29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2471031393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2471031393
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3692910242
Short name T1028
Test name
Test status
Simulation time 13407642861 ps
CPU time 13.74 seconds
Started Jul 17 07:56:36 PM PDT 24
Finished Jul 17 07:56:53 PM PDT 24
Peak memory 206872 kb
Host smart-a4a3073e-516c-48d5-a7ba-a86a133f941c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3692910242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3692910242
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1513955682
Short name T692
Test name
Test status
Simulation time 23319119531 ps
CPU time 30.57 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:58 PM PDT 24
Peak memory 206524 kb
Host smart-a128eff5-0dae-4682-a557-bd469fbb0860
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1513955682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1513955682
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.716348067
Short name T446
Test name
Test status
Simulation time 168535515 ps
CPU time 0.8 seconds
Started Jul 17 07:56:38 PM PDT 24
Finished Jul 17 07:56:41 PM PDT 24
Peak memory 206440 kb
Host smart-635552e2-4b23-4956-ad67-902c8eafc094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71634
8067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.716348067
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.688724704
Short name T2740
Test name
Test status
Simulation time 185257910 ps
CPU time 0.79 seconds
Started Jul 17 07:56:34 PM PDT 24
Finished Jul 17 07:56:35 PM PDT 24
Peak memory 206456 kb
Host smart-ce961203-3aa4-4528-bd28-48e0f7c031a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68872
4704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.688724704
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1469817995
Short name T937
Test name
Test status
Simulation time 242187662 ps
CPU time 0.94 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:39 PM PDT 24
Peak memory 206596 kb
Host smart-ff076b25-c016-4ce8-8135-fd7729636998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14698
17995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1469817995
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3112615610
Short name T1955
Test name
Test status
Simulation time 629296877 ps
CPU time 1.41 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:39 PM PDT 24
Peak memory 206596 kb
Host smart-717dc32e-cc8a-4dc4-9e3c-7929a62e56f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126
15610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3112615610
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3324853511
Short name T2712
Test name
Test status
Simulation time 8480919163 ps
CPU time 18.5 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:45 PM PDT 24
Peak memory 206624 kb
Host smart-c9b1a590-2549-42f9-baf7-cda733345bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248
53511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3324853511
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3982526046
Short name T2075
Test name
Test status
Simulation time 526212067 ps
CPU time 1.46 seconds
Started Jul 17 07:56:36 PM PDT 24
Finished Jul 17 07:56:41 PM PDT 24
Peak memory 206464 kb
Host smart-5fcadf12-55a3-456c-8ee0-e2232daa642e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39825
26046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3982526046
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3900301040
Short name T1163
Test name
Test status
Simulation time 160406562 ps
CPU time 0.82 seconds
Started Jul 17 07:56:36 PM PDT 24
Finished Jul 17 07:56:40 PM PDT 24
Peak memory 206592 kb
Host smart-2316367c-b82b-499d-8fc8-ccd54190b283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39003
01040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3900301040
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.543688574
Short name T802
Test name
Test status
Simulation time 38634661 ps
CPU time 0.67 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206400 kb
Host smart-0560b87c-9f85-4ca9-89cc-d035f9760ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54368
8574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.543688574
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2228556214
Short name T2200
Test name
Test status
Simulation time 904440955 ps
CPU time 2.1 seconds
Started Jul 17 07:56:27 PM PDT 24
Finished Jul 17 07:56:32 PM PDT 24
Peak memory 206584 kb
Host smart-70c5ecf5-82e0-4254-9c18-f76642a36877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22285
56214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2228556214
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3692562704
Short name T1031
Test name
Test status
Simulation time 210548359 ps
CPU time 0.94 seconds
Started Jul 17 07:56:38 PM PDT 24
Finished Jul 17 07:56:41 PM PDT 24
Peak memory 206460 kb
Host smart-6f19e0ae-373e-4ac7-b48a-5a1de70b2c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36925
62704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3692562704
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2419834522
Short name T2214
Test name
Test status
Simulation time 137089724 ps
CPU time 0.76 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:39 PM PDT 24
Peak memory 206400 kb
Host smart-2bf5f11f-98c6-4e03-b482-76ac7d0231ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24198
34522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2419834522
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3145822352
Short name T832
Test name
Test status
Simulation time 185520315 ps
CPU time 0.86 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:39 PM PDT 24
Peak memory 206420 kb
Host smart-1e006dc9-7e70-4e7f-8bfb-2f7101690f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31458
22352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3145822352
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.421364328
Short name T1359
Test name
Test status
Simulation time 10893337746 ps
CPU time 73.91 seconds
Started Jul 17 07:56:37 PM PDT 24
Finished Jul 17 07:57:54 PM PDT 24
Peak memory 206704 kb
Host smart-8ba33ab2-1e5a-4248-b431-3255e2ac70c8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=421364328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.421364328
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.1156667004
Short name T2041
Test name
Test status
Simulation time 7692539436 ps
CPU time 67.16 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206684 kb
Host smart-72b9b55d-1600-4393-b1d6-207b31b847bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11566
67004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.1156667004
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3080755640
Short name T350
Test name
Test status
Simulation time 204783046 ps
CPU time 0.81 seconds
Started Jul 17 07:56:37 PM PDT 24
Finished Jul 17 07:56:40 PM PDT 24
Peak memory 206456 kb
Host smart-3bb5a5fa-64a2-4bea-a98f-0edec4a647ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30807
55640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3080755640
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.1485725079
Short name T1399
Test name
Test status
Simulation time 23279018437 ps
CPU time 26.08 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:57:04 PM PDT 24
Peak memory 206492 kb
Host smart-4aa12fdd-36b2-48fc-ba5a-14c69c90492a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14857
25079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.1485725079
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2188540439
Short name T381
Test name
Test status
Simulation time 3326845399 ps
CPU time 3.89 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:32 PM PDT 24
Peak memory 206464 kb
Host smart-60f9ed80-24f9-491a-89d3-e82c0bb2f3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
40439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2188540439
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.3961110108
Short name T1577
Test name
Test status
Simulation time 8334103969 ps
CPU time 57.11 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:57:25 PM PDT 24
Peak memory 206716 kb
Host smart-d9d52fe6-e7ca-46e7-9333-e486828a86c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39611
10108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.3961110108
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.1599118545
Short name T2231
Test name
Test status
Simulation time 3228972652 ps
CPU time 86.96 seconds
Started Jul 17 07:56:37 PM PDT 24
Finished Jul 17 07:58:06 PM PDT 24
Peak memory 206688 kb
Host smart-84606751-e377-4fda-bde9-dacc73a23e0d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1599118545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.1599118545
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.4156676035
Short name T473
Test name
Test status
Simulation time 243610991 ps
CPU time 0.89 seconds
Started Jul 17 07:56:38 PM PDT 24
Finished Jul 17 07:56:41 PM PDT 24
Peak memory 206460 kb
Host smart-778087dc-592f-4485-b405-dc30dcc65615
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4156676035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.4156676035
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.4207357630
Short name T352
Test name
Test status
Simulation time 233604693 ps
CPU time 0.85 seconds
Started Jul 17 07:56:37 PM PDT 24
Finished Jul 17 07:56:40 PM PDT 24
Peak memory 206460 kb
Host smart-5d472282-143b-4f2f-a0d8-f1624d390de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42073
57630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.4207357630
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.2383457791
Short name T2568
Test name
Test status
Simulation time 4857842987 ps
CPU time 34.06 seconds
Started Jul 17 07:56:27 PM PDT 24
Finished Jul 17 07:57:04 PM PDT 24
Peak memory 206708 kb
Host smart-dd6fbf37-6b61-4f6b-8268-9f0a9171a7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23834
57791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.2383457791
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1624752988
Short name T1105
Test name
Test status
Simulation time 4163103618 ps
CPU time 39.3 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:57:17 PM PDT 24
Peak memory 206616 kb
Host smart-a0b70876-7365-44b8-8367-5ca37b2f65ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1624752988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1624752988
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2909760527
Short name T1802
Test name
Test status
Simulation time 181952010 ps
CPU time 0.81 seconds
Started Jul 17 07:56:26 PM PDT 24
Finished Jul 17 07:56:29 PM PDT 24
Peak memory 206456 kb
Host smart-6de199b5-578a-4538-9f09-2d40f087fdb4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2909760527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2909760527
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3345957617
Short name T2308
Test name
Test status
Simulation time 214462695 ps
CPU time 0.83 seconds
Started Jul 17 07:56:23 PM PDT 24
Finished Jul 17 07:56:26 PM PDT 24
Peak memory 206460 kb
Host smart-d4811518-a3b9-4551-b53f-9dd33e4291aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33459
57617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3345957617
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3195538787
Short name T799
Test name
Test status
Simulation time 183902330 ps
CPU time 0.87 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206064 kb
Host smart-1639c2db-78b8-4934-82e6-8ba3ce60733b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31955
38787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3195538787
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.4239925987
Short name T935
Test name
Test status
Simulation time 214926784 ps
CPU time 0.88 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206504 kb
Host smart-5cd5cb94-baf8-4db1-a7e6-2999f34bfc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42399
25987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4239925987
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2099080239
Short name T1124
Test name
Test status
Simulation time 191543255 ps
CPU time 0.9 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206092 kb
Host smart-1824db74-6b34-46cc-836a-a4f03cea33fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20990
80239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2099080239
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3111771125
Short name T2264
Test name
Test status
Simulation time 154815407 ps
CPU time 0.8 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:28 PM PDT 24
Peak memory 206424 kb
Host smart-9e5b4f26-ec43-4a2e-9903-60bec9f192c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
71125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3111771125
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1381100232
Short name T1799
Test name
Test status
Simulation time 211254350 ps
CPU time 0.94 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206540 kb
Host smart-0439a85d-cda7-4dea-914c-7340773ee09e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1381100232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1381100232
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3596342199
Short name T42
Test name
Test status
Simulation time 164469423 ps
CPU time 0.76 seconds
Started Jul 17 07:56:34 PM PDT 24
Finished Jul 17 07:56:35 PM PDT 24
Peak memory 206456 kb
Host smart-aae51933-68bd-4498-80fa-93e428dd2674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35963
42199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3596342199
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.524761497
Short name T2559
Test name
Test status
Simulation time 29517017 ps
CPU time 0.66 seconds
Started Jul 17 07:56:25 PM PDT 24
Finished Jul 17 07:56:28 PM PDT 24
Peak memory 206420 kb
Host smart-ced2d8cf-fe0c-4c99-9eb1-fd97a9c6f901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52476
1497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.524761497
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1143293983
Short name T2080
Test name
Test status
Simulation time 20485295740 ps
CPU time 40.56 seconds
Started Jul 17 07:56:34 PM PDT 24
Finished Jul 17 07:57:17 PM PDT 24
Peak memory 214944 kb
Host smart-2b2c4b9d-135f-432b-8a2e-04bbaa5ed897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11432
93983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1143293983
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.595736599
Short name T2129
Test name
Test status
Simulation time 198279734 ps
CPU time 0.84 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:27 PM PDT 24
Peak memory 206448 kb
Host smart-8260f16e-9491-47c7-808c-ae95cbbaae52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59573
6599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.595736599
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.696139839
Short name T1569
Test name
Test status
Simulation time 201643344 ps
CPU time 0.85 seconds
Started Jul 17 07:56:34 PM PDT 24
Finished Jul 17 07:56:37 PM PDT 24
Peak memory 206532 kb
Host smart-7329aa8c-0339-40fc-b702-7dd77768e2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69613
9839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.696139839
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.4089625769
Short name T410
Test name
Test status
Simulation time 150039190 ps
CPU time 0.82 seconds
Started Jul 17 07:56:24 PM PDT 24
Finished Jul 17 07:56:27 PM PDT 24
Peak memory 205776 kb
Host smart-c5290c3e-2d34-48ed-96b6-1245dcfb8a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896
25769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.4089625769
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1348496711
Short name T1390
Test name
Test status
Simulation time 152858878 ps
CPU time 0.78 seconds
Started Jul 17 07:56:27 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 206400 kb
Host smart-9b5732fd-6ab7-4bce-bbd0-596149c2435a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13484
96711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1348496711
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1547042657
Short name T2387
Test name
Test status
Simulation time 143036645 ps
CPU time 0.79 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206452 kb
Host smart-b2276ec1-002d-472f-8706-67bcd1e485bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15470
42657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1547042657
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3119649305
Short name T2139
Test name
Test status
Simulation time 150610430 ps
CPU time 0.77 seconds
Started Jul 17 07:56:27 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 206416 kb
Host smart-14b0472b-5dbb-4dec-8c88-019b3d23ac48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31196
49305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3119649305
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.851606652
Short name T1317
Test name
Test status
Simulation time 154538275 ps
CPU time 0.79 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:39 PM PDT 24
Peak memory 206600 kb
Host smart-d96ab63a-e357-40e2-8cd2-2740e22eb502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85160
6652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.851606652
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.4118092582
Short name T1718
Test name
Test status
Simulation time 256269380 ps
CPU time 0.96 seconds
Started Jul 17 07:56:34 PM PDT 24
Finished Jul 17 07:56:37 PM PDT 24
Peak memory 206380 kb
Host smart-ef340286-71e5-468c-a4dc-c5655376cb4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
92582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.4118092582
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1790442451
Short name T1184
Test name
Test status
Simulation time 4871738633 ps
CPU time 125.38 seconds
Started Jul 17 07:56:34 PM PDT 24
Finished Jul 17 07:58:41 PM PDT 24
Peak memory 206812 kb
Host smart-e65907aa-7750-4353-904e-0d0c65c9a6f8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1790442451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1790442451
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3149586463
Short name T1777
Test name
Test status
Simulation time 142773939 ps
CPU time 0.75 seconds
Started Jul 17 07:56:34 PM PDT 24
Finished Jul 17 07:56:37 PM PDT 24
Peak memory 206452 kb
Host smart-dab9c1e4-1a8f-403b-ad9c-71461c14ba44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
86463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3149586463
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.721563550
Short name T2448
Test name
Test status
Simulation time 169175426 ps
CPU time 0.84 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:37 PM PDT 24
Peak memory 206448 kb
Host smart-76a30660-463c-4378-81e9-53b239914481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72156
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.721563550
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2706922258
Short name T561
Test name
Test status
Simulation time 1086834323 ps
CPU time 2.23 seconds
Started Jul 17 07:56:35 PM PDT 24
Finished Jul 17 07:56:39 PM PDT 24
Peak memory 206772 kb
Host smart-2cd62d94-710a-4e79-97e5-1cd88da5bc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
22258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2706922258
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2355899624
Short name T726
Test name
Test status
Simulation time 5764152099 ps
CPU time 53.78 seconds
Started Jul 17 07:56:36 PM PDT 24
Finished Jul 17 07:57:33 PM PDT 24
Peak memory 206804 kb
Host smart-d4d983e8-775e-4e09-8734-689de26f9381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23558
99624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2355899624
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.767008768
Short name T2626
Test name
Test status
Simulation time 57066522 ps
CPU time 0.71 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:56:44 PM PDT 24
Peak memory 206440 kb
Host smart-0ce937cb-fde3-4aaf-9672-bc07ef33e925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=767008768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.767008768
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2359637413
Short name T660
Test name
Test status
Simulation time 4234197138 ps
CPU time 5.66 seconds
Started Jul 17 07:56:44 PM PDT 24
Finished Jul 17 07:56:52 PM PDT 24
Peak memory 206524 kb
Host smart-699e69e4-8944-4005-81dc-6714642bbd26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2359637413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2359637413
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1481741625
Short name T1143
Test name
Test status
Simulation time 13315035545 ps
CPU time 11.85 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:56:55 PM PDT 24
Peak memory 206672 kb
Host smart-71a2cf40-bf44-40c6-9542-de09823daf7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1481741625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1481741625
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2198370908
Short name T497
Test name
Test status
Simulation time 23331875200 ps
CPU time 27.06 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:57:10 PM PDT 24
Peak memory 206528 kb
Host smart-756f1acf-5a35-430a-b962-40069261b2ea
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2198370908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2198370908
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3139023912
Short name T650
Test name
Test status
Simulation time 235731341 ps
CPU time 0.84 seconds
Started Jul 17 07:56:41 PM PDT 24
Finished Jul 17 07:56:42 PM PDT 24
Peak memory 206456 kb
Host smart-68fd9353-8bc1-40d5-999a-4563981b5368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31390
23912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3139023912
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.855911992
Short name T577
Test name
Test status
Simulation time 152942799 ps
CPU time 0.76 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:56:51 PM PDT 24
Peak memory 206536 kb
Host smart-0e3268ff-dc09-45bb-a81b-1afe25c845fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85591
1992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.855911992
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1788275220
Short name T1549
Test name
Test status
Simulation time 669770667 ps
CPU time 1.78 seconds
Started Jul 17 07:56:41 PM PDT 24
Finished Jul 17 07:56:43 PM PDT 24
Peak memory 206632 kb
Host smart-09f25b57-6ad3-4109-af3d-db1b024523f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17882
75220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1788275220
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1083769977
Short name T951
Test name
Test status
Simulation time 776181954 ps
CPU time 1.83 seconds
Started Jul 17 07:56:44 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206608 kb
Host smart-56c9560d-50f1-4716-a07d-31ed5f59cc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10837
69977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1083769977
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.2283292445
Short name T1944
Test name
Test status
Simulation time 17740735982 ps
CPU time 29.79 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:57:13 PM PDT 24
Peak memory 206636 kb
Host smart-4c0d06a6-8b47-42e9-886b-4432b3e2a619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22832
92445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.2283292445
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.4000281746
Short name T1606
Test name
Test status
Simulation time 297750821 ps
CPU time 1.11 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206456 kb
Host smart-c11aca6a-07de-450a-86fd-2772eab57785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
81746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.4000281746
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2024646720
Short name T1392
Test name
Test status
Simulation time 184793984 ps
CPU time 0.82 seconds
Started Jul 17 07:56:44 PM PDT 24
Finished Jul 17 07:56:47 PM PDT 24
Peak memory 206472 kb
Host smart-9fcc45a8-f765-4f59-836d-156f2e6f20a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20246
46720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2024646720
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.942530373
Short name T2390
Test name
Test status
Simulation time 74340678 ps
CPU time 0.69 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:56:51 PM PDT 24
Peak memory 206444 kb
Host smart-80f700c6-52af-4d95-b07e-9d78576bf4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94253
0373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.942530373
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.869649156
Short name T140
Test name
Test status
Simulation time 1126869989 ps
CPU time 3.16 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:56:46 PM PDT 24
Peak memory 206604 kb
Host smart-1a51de9d-9249-4af5-9bd4-3d01f38c7a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86964
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.869649156
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.752261435
Short name T43
Test name
Test status
Simulation time 298057390 ps
CPU time 1.8 seconds
Started Jul 17 07:56:46 PM PDT 24
Finished Jul 17 07:56:51 PM PDT 24
Peak memory 206652 kb
Host smart-ba9127a8-11f6-444b-9096-6645809258d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75226
1435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.752261435
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3110643538
Short name T401
Test name
Test status
Simulation time 184806779 ps
CPU time 0.82 seconds
Started Jul 17 07:56:44 PM PDT 24
Finished Jul 17 07:56:47 PM PDT 24
Peak memory 206404 kb
Host smart-990b2a54-ad74-4a5f-b44a-ab29209dfb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31106
43538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3110643538
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.593781262
Short name T496
Test name
Test status
Simulation time 145016550 ps
CPU time 0.75 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:56:51 PM PDT 24
Peak memory 206452 kb
Host smart-4a4c7560-194f-4f92-bbd7-4fb208716192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59378
1262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.593781262
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.17555767
Short name T916
Test name
Test status
Simulation time 156597755 ps
CPU time 0.83 seconds
Started Jul 17 07:56:43 PM PDT 24
Finished Jul 17 07:56:45 PM PDT 24
Peak memory 206440 kb
Host smart-e726558b-6425-4c16-84d1-091e9cb37dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17555
767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.17555767
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.1606513173
Short name T2016
Test name
Test status
Simulation time 12308338128 ps
CPU time 105.54 seconds
Started Jul 17 07:56:49 PM PDT 24
Finished Jul 17 07:58:37 PM PDT 24
Peak memory 206708 kb
Host smart-18a62c68-98a7-4d0c-b8e1-f45dd75f4900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16065
13173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.1606513173
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2846575718
Short name T753
Test name
Test status
Simulation time 207940284 ps
CPU time 0.84 seconds
Started Jul 17 07:56:46 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206452 kb
Host smart-a32c3076-d8d7-4890-ae8f-cc14552df6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28465
75718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2846575718
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1474521967
Short name T2472
Test name
Test status
Simulation time 23296198980 ps
CPU time 23.67 seconds
Started Jul 17 07:56:46 PM PDT 24
Finished Jul 17 07:57:12 PM PDT 24
Peak memory 206524 kb
Host smart-120b93f2-12e6-4f9c-9d07-1fed0689a2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14745
21967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1474521967
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2743853582
Short name T2451
Test name
Test status
Simulation time 3319299501 ps
CPU time 3.94 seconds
Started Jul 17 07:56:51 PM PDT 24
Finished Jul 17 07:56:58 PM PDT 24
Peak memory 206504 kb
Host smart-aaf7d2e2-7405-486a-a1be-5d6092187d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27438
53582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2743853582
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1797602476
Short name T1330
Test name
Test status
Simulation time 12812254726 ps
CPU time 94.41 seconds
Started Jul 17 07:56:51 PM PDT 24
Finished Jul 17 07:58:29 PM PDT 24
Peak memory 206700 kb
Host smart-5e37697a-2920-442a-b565-6bc34917053a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17976
02476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1797602476
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1127317565
Short name T2498
Test name
Test status
Simulation time 4120714543 ps
CPU time 39.14 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206656 kb
Host smart-a3449538-da4c-440f-9ee9-7a192b55c111
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1127317565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1127317565
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1192116031
Short name T2410
Test name
Test status
Simulation time 236546688 ps
CPU time 0.9 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206396 kb
Host smart-6555ae53-b1b8-4235-8915-f564de3aee09
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1192116031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1192116031
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.4199854025
Short name T2199
Test name
Test status
Simulation time 191459085 ps
CPU time 0.9 seconds
Started Jul 17 07:56:44 PM PDT 24
Finished Jul 17 07:56:47 PM PDT 24
Peak memory 206408 kb
Host smart-19c1cf15-df4b-4a2e-b4d8-f4cd07455142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41998
54025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.4199854025
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1304986053
Short name T2341
Test name
Test status
Simulation time 3960613178 ps
CPU time 39.35 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:57:30 PM PDT 24
Peak memory 206648 kb
Host smart-b89bbaa5-3b7c-4e88-b02a-9750d10719f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
86053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1304986053
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2041790264
Short name T654
Test name
Test status
Simulation time 5038099131 ps
CPU time 146.65 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:59:20 PM PDT 24
Peak memory 206652 kb
Host smart-34f6e57e-60d0-438a-a0e1-b6ac9204c9e2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2041790264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2041790264
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.235069342
Short name T986
Test name
Test status
Simulation time 166461118 ps
CPU time 0.82 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 206420 kb
Host smart-52eee4c0-b917-4f30-897d-ef4ca402381b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=235069342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.235069342
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3036469139
Short name T1888
Test name
Test status
Simulation time 144142290 ps
CPU time 0.76 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 206444 kb
Host smart-f93276cb-d2c9-4f7e-99ef-67aeaaa3ed2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30364
69139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3036469139
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3406309966
Short name T2545
Test name
Test status
Simulation time 232997376 ps
CPU time 0.94 seconds
Started Jul 17 07:56:49 PM PDT 24
Finished Jul 17 07:56:53 PM PDT 24
Peak memory 206408 kb
Host smart-df08eb16-21af-4de1-9f88-e091d9f7a443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
09966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3406309966
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1974918361
Short name T896
Test name
Test status
Simulation time 193079152 ps
CPU time 0.86 seconds
Started Jul 17 07:56:49 PM PDT 24
Finished Jul 17 07:56:53 PM PDT 24
Peak memory 206436 kb
Host smart-0b9b83ac-6232-411d-bde8-e524f8e05b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19749
18361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1974918361
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3472410173
Short name T1954
Test name
Test status
Simulation time 180812713 ps
CPU time 0.79 seconds
Started Jul 17 07:56:46 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206452 kb
Host smart-e754d9c5-de47-4947-a1c4-af7109cdf02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34724
10173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3472410173
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1796005488
Short name T1783
Test name
Test status
Simulation time 182658657 ps
CPU time 0.88 seconds
Started Jul 17 07:56:49 PM PDT 24
Finished Jul 17 07:56:53 PM PDT 24
Peak memory 206348 kb
Host smart-7fff5c0e-478e-4d69-896d-07fb5b9a83b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17960
05488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1796005488
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3784776511
Short name T1351
Test name
Test status
Simulation time 164570767 ps
CPU time 0.82 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206460 kb
Host smart-6fd096c3-98cc-4900-9c7a-86080a1b739b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37847
76511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3784776511
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.982268611
Short name T611
Test name
Test status
Simulation time 276127588 ps
CPU time 0.95 seconds
Started Jul 17 07:56:46 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206480 kb
Host smart-d2a55990-b840-4978-b789-b84a362db655
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=982268611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.982268611
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.321327595
Short name T1350
Test name
Test status
Simulation time 165749804 ps
CPU time 0.82 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206468 kb
Host smart-203708fa-1ed8-479c-9da7-35713fc2b050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32132
7595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.321327595
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1281558658
Short name T812
Test name
Test status
Simulation time 40271427 ps
CPU time 0.66 seconds
Started Jul 17 07:57:59 PM PDT 24
Finished Jul 17 07:58:02 PM PDT 24
Peak memory 206436 kb
Host smart-ac4bcf4c-a857-45b1-9032-d29ec92b78c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815
58658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1281558658
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3888409286
Short name T242
Test name
Test status
Simulation time 22438625366 ps
CPU time 51.31 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 214884 kb
Host smart-09f24b40-4954-4ab8-b5de-e492a7c25749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38884
09286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3888409286
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.178928578
Short name T1174
Test name
Test status
Simulation time 205839604 ps
CPU time 0.94 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 206460 kb
Host smart-37f2c546-fa02-4c2b-877e-82194947d267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17892
8578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.178928578
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2673280483
Short name T1746
Test name
Test status
Simulation time 199424846 ps
CPU time 0.86 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 206460 kb
Host smart-9fbfed5a-3d23-4893-b8eb-37ebd2de5169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26732
80483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2673280483
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1379877361
Short name T1686
Test name
Test status
Simulation time 206239935 ps
CPU time 0.87 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206460 kb
Host smart-e93a549d-b5c6-492e-b89a-0355d119da4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
77361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1379877361
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2424348486
Short name T980
Test name
Test status
Simulation time 171848936 ps
CPU time 0.81 seconds
Started Jul 17 07:56:53 PM PDT 24
Finished Jul 17 07:56:56 PM PDT 24
Peak memory 206392 kb
Host smart-8e9e874a-c6f1-4cd4-b119-c2b14ca370e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
48486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2424348486
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4165664420
Short name T2638
Test name
Test status
Simulation time 177095244 ps
CPU time 0.8 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 206440 kb
Host smart-e7622e54-7975-49fc-bb69-99602d6c5144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41656
64420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4165664420
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3389350206
Short name T920
Test name
Test status
Simulation time 181811761 ps
CPU time 0.81 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206452 kb
Host smart-af5a830e-86d7-4084-a685-7f64fc8cb3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33893
50206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3389350206
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3834246761
Short name T2046
Test name
Test status
Simulation time 153092853 ps
CPU time 0.77 seconds
Started Jul 17 07:56:51 PM PDT 24
Finished Jul 17 07:56:55 PM PDT 24
Peak memory 206412 kb
Host smart-e52cfc71-5e3b-412e-b684-e64d2915b391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38342
46761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3834246761
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1562998169
Short name T2627
Test name
Test status
Simulation time 242221510 ps
CPU time 1.04 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206464 kb
Host smart-bf2c5f40-a08a-4414-870b-2a7b5a4c1551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15629
98169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1562998169
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3308902176
Short name T856
Test name
Test status
Simulation time 4370069813 ps
CPU time 111 seconds
Started Jul 17 07:56:52 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206620 kb
Host smart-d2cfbaf3-e538-42c4-950e-6b4a83d7fa97
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3308902176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3308902176
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2593084001
Short name T1810
Test name
Test status
Simulation time 195002461 ps
CPU time 0.93 seconds
Started Jul 17 07:56:43 PM PDT 24
Finished Jul 17 07:56:45 PM PDT 24
Peak memory 206440 kb
Host smart-ab0d2215-8948-41c9-8e47-c3c67eb9aec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25930
84001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2593084001
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2812385141
Short name T433
Test name
Test status
Simulation time 171137283 ps
CPU time 0.78 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:56:45 PM PDT 24
Peak memory 206456 kb
Host smart-6502a732-58d1-4074-ada4-1a1ca2a3626d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28123
85141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2812385141
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.1161935467
Short name T2441
Test name
Test status
Simulation time 384988114 ps
CPU time 1.16 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:56:44 PM PDT 24
Peak memory 206448 kb
Host smart-648b57bf-b7e2-4a0d-bfe5-bc4d69449c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11619
35467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1161935467
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2562041610
Short name T667
Test name
Test status
Simulation time 7430787365 ps
CPU time 54.93 seconds
Started Jul 17 07:56:41 PM PDT 24
Finished Jul 17 07:57:38 PM PDT 24
Peak memory 206724 kb
Host smart-a5ab5d88-a374-4f94-8547-81fe8fadbe76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25620
41610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2562041610
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.948466698
Short name T2468
Test name
Test status
Simulation time 69251892 ps
CPU time 0.69 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206436 kb
Host smart-30594cd3-09aa-44f0-a031-c1aa26449911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=948466698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.948466698
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.4271846807
Short name T1142
Test name
Test status
Simulation time 3693692600 ps
CPU time 4.41 seconds
Started Jul 17 07:56:44 PM PDT 24
Finished Jul 17 07:56:50 PM PDT 24
Peak memory 206524 kb
Host smart-b273dde9-a186-41c0-bd2f-f5b4decd4fe6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4271846807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.4271846807
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1507036791
Short name T2395
Test name
Test status
Simulation time 13472044628 ps
CPU time 16.72 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:57:00 PM PDT 24
Peak memory 206720 kb
Host smart-194bedcf-ae4e-432a-8053-d73e8afff7f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1507036791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1507036791
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.1821396711
Short name T1960
Test name
Test status
Simulation time 23364998257 ps
CPU time 24.33 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:57:07 PM PDT 24
Peak memory 206524 kb
Host smart-3354928f-0d5d-47d0-9131-c84e5220053b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1821396711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.1821396711
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.337246743
Short name T695
Test name
Test status
Simulation time 160422509 ps
CPU time 0.84 seconds
Started Jul 17 07:56:41 PM PDT 24
Finished Jul 17 07:56:42 PM PDT 24
Peak memory 206416 kb
Host smart-5640eae1-dd35-4005-9a8e-1a93d1bfbd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33724
6743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.337246743
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1747283690
Short name T910
Test name
Test status
Simulation time 185230251 ps
CPU time 0.85 seconds
Started Jul 17 07:56:44 PM PDT 24
Finished Jul 17 07:56:47 PM PDT 24
Peak memory 206412 kb
Host smart-51d3fbda-d1d7-4219-8091-14adb6a7c681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17472
83690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1747283690
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1164786066
Short name T1923
Test name
Test status
Simulation time 598945217 ps
CPU time 1.54 seconds
Started Jul 17 07:56:43 PM PDT 24
Finished Jul 17 07:56:46 PM PDT 24
Peak memory 206468 kb
Host smart-b8b7c8b7-3a51-4206-a947-8c9230eace88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11647
86066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1164786066
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3078099673
Short name T1333
Test name
Test status
Simulation time 7349228510 ps
CPU time 13.31 seconds
Started Jul 17 07:56:43 PM PDT 24
Finished Jul 17 07:56:58 PM PDT 24
Peak memory 206712 kb
Host smart-b6fbdfbd-7ac4-4884-9949-8ef5495d30f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30780
99673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3078099673
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.38295153
Short name T1648
Test name
Test status
Simulation time 331214492 ps
CPU time 1.08 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:56:52 PM PDT 24
Peak memory 206456 kb
Host smart-7396cb96-aa1e-43e8-8ec9-de7d201d1796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38295
153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.38295153
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3768810176
Short name T782
Test name
Test status
Simulation time 148911427 ps
CPU time 0.77 seconds
Started Jul 17 07:56:46 PM PDT 24
Finished Jul 17 07:56:50 PM PDT 24
Peak memory 206452 kb
Host smart-d7960a64-e0a4-4638-b9d2-ad77c4d0cf50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37688
10176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3768810176
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1390591272
Short name T1291
Test name
Test status
Simulation time 43959270 ps
CPU time 0.69 seconds
Started Jul 17 07:56:43 PM PDT 24
Finished Jul 17 07:56:45 PM PDT 24
Peak memory 206444 kb
Host smart-9bcc8934-9d46-4f67-ae17-07b6dbdd9518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13905
91272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1390591272
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1294165831
Short name T625
Test name
Test status
Simulation time 891370623 ps
CPU time 2.03 seconds
Started Jul 17 07:56:49 PM PDT 24
Finished Jul 17 07:56:53 PM PDT 24
Peak memory 206652 kb
Host smart-535c13f9-5657-4a50-afbd-f1bcfbccb113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12941
65831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1294165831
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2580557959
Short name T2290
Test name
Test status
Simulation time 160401590 ps
CPU time 1.22 seconds
Started Jul 17 07:56:42 PM PDT 24
Finished Jul 17 07:56:45 PM PDT 24
Peak memory 206604 kb
Host smart-a796d728-ba8e-409e-8d71-4e083a10a534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25805
57959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2580557959
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3133517672
Short name T2373
Test name
Test status
Simulation time 185213080 ps
CPU time 0.89 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206448 kb
Host smart-3ccd8e37-e3fd-4246-af0a-7907f25190b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31335
17672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3133517672
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1223237482
Short name T1089
Test name
Test status
Simulation time 157185017 ps
CPU time 0.78 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206448 kb
Host smart-6ffe32f7-9161-4426-a780-99c09a58336d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
37482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1223237482
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.936983129
Short name T2531
Test name
Test status
Simulation time 189362559 ps
CPU time 0.82 seconds
Started Jul 17 07:56:51 PM PDT 24
Finished Jul 17 07:56:55 PM PDT 24
Peak memory 206436 kb
Host smart-aa1b5334-aeb6-4f88-99d0-99dab5438818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93698
3129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.936983129
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.2366676292
Short name T1857
Test name
Test status
Simulation time 8647639846 ps
CPU time 72.88 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:58:03 PM PDT 24
Peak memory 206696 kb
Host smart-b551f40d-1127-45be-8c1f-ddf84daee597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23666
76292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2366676292
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2629422110
Short name T2699
Test name
Test status
Simulation time 235569537 ps
CPU time 1.01 seconds
Started Jul 17 07:56:46 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206444 kb
Host smart-6b6af31d-6206-4a06-a5aa-2d5289b1e0f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26294
22110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2629422110
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3241739155
Short name T1687
Test name
Test status
Simulation time 23290981361 ps
CPU time 26.14 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:57:17 PM PDT 24
Peak memory 206488 kb
Host smart-ff8cd5e0-212b-4a1b-a993-5649417becca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32417
39155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3241739155
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2645473074
Short name T1690
Test name
Test status
Simulation time 3265331607 ps
CPU time 4.4 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:56:55 PM PDT 24
Peak memory 206524 kb
Host smart-64333b43-a652-4f81-8d9a-5cdfd12a2d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26454
73074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2645473074
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.237717643
Short name T2091
Test name
Test status
Simulation time 13018126184 ps
CPU time 366.42 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 08:03:00 PM PDT 24
Peak memory 206728 kb
Host smart-91cbd588-9f0a-4173-9f70-efa83c887638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23771
7643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.237717643
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.758148788
Short name T1903
Test name
Test status
Simulation time 3960990302 ps
CPU time 116.24 seconds
Started Jul 17 07:56:43 PM PDT 24
Finished Jul 17 07:58:42 PM PDT 24
Peak memory 206656 kb
Host smart-4dcbeac8-e8e0-478a-9059-9cb0ff93a6cd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=758148788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.758148788
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1002283798
Short name T2528
Test name
Test status
Simulation time 238895624 ps
CPU time 0.9 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:56:52 PM PDT 24
Peak memory 206440 kb
Host smart-b891c36b-36d3-4a4a-bd4b-d0cfb98ed28f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1002283798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1002283798
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.42563035
Short name T207
Test name
Test status
Simulation time 194252172 ps
CPU time 0.92 seconds
Started Jul 17 07:56:47 PM PDT 24
Finished Jul 17 07:56:51 PM PDT 24
Peak memory 206448 kb
Host smart-5cddd64c-6978-4e70-ae55-f16b29516805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42563
035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.42563035
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2606071657
Short name T1620
Test name
Test status
Simulation time 4954694975 ps
CPU time 134.17 seconds
Started Jul 17 07:56:49 PM PDT 24
Finished Jul 17 07:59:06 PM PDT 24
Peak memory 206664 kb
Host smart-47e0c198-c34d-4f31-9383-34bf64aff286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26060
71657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2606071657
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3271024110
Short name T2037
Test name
Test status
Simulation time 4153175358 ps
CPU time 29.82 seconds
Started Jul 17 07:56:47 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206708 kb
Host smart-a8eb4e28-005d-496b-b6e5-518ed25857d2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3271024110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3271024110
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3104804313
Short name T2644
Test name
Test status
Simulation time 152676073 ps
CPU time 0.83 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 206456 kb
Host smart-31254b67-b33e-4cf2-946e-20bb3990e7bd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3104804313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3104804313
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2101548707
Short name T868
Test name
Test status
Simulation time 158753294 ps
CPU time 0.73 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 206456 kb
Host smart-dbc4a8c0-b7ef-43d7-a304-c1be929d3bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21015
48707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2101548707
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4126480125
Short name T1547
Test name
Test status
Simulation time 192719195 ps
CPU time 0.83 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 205156 kb
Host smart-331f89a7-b482-4867-be1e-4e76e3faf21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41264
80125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4126480125
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1325697736
Short name T1080
Test name
Test status
Simulation time 162177217 ps
CPU time 0.8 seconds
Started Jul 17 07:56:50 PM PDT 24
Finished Jul 17 07:56:54 PM PDT 24
Peak memory 205232 kb
Host smart-012131e0-8a54-440f-aaf0-fbbebcda9396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
97736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1325697736
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1380220458
Short name T2268
Test name
Test status
Simulation time 173247209 ps
CPU time 0.85 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:48 PM PDT 24
Peak memory 206456 kb
Host smart-bf508da2-2c17-4c1c-b418-b6baac4bb074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13802
20458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1380220458
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1748021469
Short name T870
Test name
Test status
Simulation time 187332864 ps
CPU time 0.77 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:56:51 PM PDT 24
Peak memory 206452 kb
Host smart-9f0a410d-86bc-4ea5-8cf3-fe8a8629be79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17480
21469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1748021469
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3219957942
Short name T173
Test name
Test status
Simulation time 168552920 ps
CPU time 0.87 seconds
Started Jul 17 07:56:45 PM PDT 24
Finished Jul 17 07:56:49 PM PDT 24
Peak memory 206456 kb
Host smart-990c42b8-8a95-43e8-b917-086affa32d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199
57942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3219957942
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1904473052
Short name T1537
Test name
Test status
Simulation time 196120007 ps
CPU time 0.88 seconds
Started Jul 17 07:56:48 PM PDT 24
Finished Jul 17 07:56:51 PM PDT 24
Peak memory 206452 kb
Host smart-5572ab0c-55fe-4bf3-adc4-e63e087f3265
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1904473052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1904473052
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2943730399
Short name T305
Test name
Test status
Simulation time 150985292 ps
CPU time 0.79 seconds
Started Jul 17 07:56:51 PM PDT 24
Finished Jul 17 07:56:55 PM PDT 24
Peak memory 206408 kb
Host smart-a46e1ee9-7d34-4a3f-bd77-a600bca58575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29437
30399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2943730399
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.792208130
Short name T2163
Test name
Test status
Simulation time 57110780 ps
CPU time 0.73 seconds
Started Jul 17 07:56:52 PM PDT 24
Finished Jul 17 07:56:55 PM PDT 24
Peak memory 206380 kb
Host smart-9d86d8ea-0a86-4815-9e38-227ca8efb579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79220
8130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.792208130
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.83417574
Short name T518
Test name
Test status
Simulation time 15638852993 ps
CPU time 35.11 seconds
Started Jul 17 07:56:49 PM PDT 24
Finished Jul 17 07:57:26 PM PDT 24
Peak memory 206756 kb
Host smart-de724015-9b7f-4791-b8e4-4a3caaba5662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83417
574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.83417574
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.210728690
Short name T853
Test name
Test status
Simulation time 200933862 ps
CPU time 0.85 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206460 kb
Host smart-c302a6c1-ea54-44ea-a244-8ce65944a288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21072
8690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.210728690
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1900882855
Short name T327
Test name
Test status
Simulation time 189951364 ps
CPU time 0.93 seconds
Started Jul 17 07:57:10 PM PDT 24
Finished Jul 17 07:57:13 PM PDT 24
Peak memory 206452 kb
Host smart-8309d05a-c373-4c0b-80a6-7b9b20a84d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19008
82855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1900882855
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.478499451
Short name T1342
Test name
Test status
Simulation time 170336689 ps
CPU time 0.83 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206344 kb
Host smart-ea0ef6ea-ef8b-4b7f-8e64-73f0b77dce66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47849
9451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.478499451
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3769748459
Short name T2388
Test name
Test status
Simulation time 221346144 ps
CPU time 0.85 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:17 PM PDT 24
Peak memory 206440 kb
Host smart-9894398f-9550-4afe-a4f3-8fee00806f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37697
48459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3769748459
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1907188671
Short name T2185
Test name
Test status
Simulation time 168783020 ps
CPU time 0.79 seconds
Started Jul 17 07:57:10 PM PDT 24
Finished Jul 17 07:57:12 PM PDT 24
Peak memory 206456 kb
Host smart-3ee52d42-4970-4617-ab4e-d54e706fa3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19071
88671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1907188671
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1150249659
Short name T2414
Test name
Test status
Simulation time 169436455 ps
CPU time 0.88 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:57:15 PM PDT 24
Peak memory 205888 kb
Host smart-ca3697c3-6f4f-447e-ad8e-fbdd841b60ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11502
49659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1150249659
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3308329411
Short name T1133
Test name
Test status
Simulation time 192560761 ps
CPU time 0.86 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:57:15 PM PDT 24
Peak memory 206404 kb
Host smart-06ddaa30-156e-40d0-959f-c065fb121b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33083
29411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3308329411
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1246296227
Short name T1386
Test name
Test status
Simulation time 194889123 ps
CPU time 0.86 seconds
Started Jul 17 07:57:10 PM PDT 24
Finished Jul 17 07:57:12 PM PDT 24
Peak memory 206408 kb
Host smart-dc94a989-362f-4560-98e0-76b79b4d0926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12462
96227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1246296227
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3024700212
Short name T1106
Test name
Test status
Simulation time 3860292937 ps
CPU time 27.97 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206700 kb
Host smart-cc204029-7b8a-4c1a-847d-64708b50da47
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3024700212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3024700212
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1932096883
Short name T818
Test name
Test status
Simulation time 188281742 ps
CPU time 0.81 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:18 PM PDT 24
Peak memory 206460 kb
Host smart-2e403fcb-d2d9-4a1f-9868-99887e579730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19320
96883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1932096883
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2249842130
Short name T1251
Test name
Test status
Simulation time 218727945 ps
CPU time 0.89 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:17 PM PDT 24
Peak memory 206436 kb
Host smart-2c25796a-b784-4e07-a753-f3dfefa462cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22498
42130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2249842130
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2213327787
Short name T318
Test name
Test status
Simulation time 1033019875 ps
CPU time 2.15 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206564 kb
Host smart-c5172757-2534-45a3-a9b5-c7ba11d530bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133
27787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2213327787
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2839115380
Short name T1912
Test name
Test status
Simulation time 2935082292 ps
CPU time 22.18 seconds
Started Jul 17 07:57:08 PM PDT 24
Finished Jul 17 07:57:31 PM PDT 24
Peak memory 206664 kb
Host smart-13aea698-0c4f-4230-b827-cccb7ad4f662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28391
15380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2839115380
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.1188137679
Short name T613
Test name
Test status
Simulation time 38084776 ps
CPU time 0.68 seconds
Started Jul 17 07:57:15 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206424 kb
Host smart-9a481108-0654-4b3a-8f5f-c16168f76b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1188137679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1188137679
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.4259122012
Short name T1078
Test name
Test status
Simulation time 3855659873 ps
CPU time 4.39 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206520 kb
Host smart-b65a08a2-046b-4bb5-8a33-114ac2e79e5b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4259122012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.4259122012
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1999694887
Short name T705
Test name
Test status
Simulation time 13385658069 ps
CPU time 16.33 seconds
Started Jul 17 07:57:09 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206668 kb
Host smart-ac335aea-3b60-4383-92f9-79f5489d2dda
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1999694887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1999694887
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1642044502
Short name T1556
Test name
Test status
Simulation time 23375164460 ps
CPU time 22.91 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:50 PM PDT 24
Peak memory 206532 kb
Host smart-abf02e22-0ebe-4859-a5dc-771e51600817
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1642044502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1642044502
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3131288218
Short name T985
Test name
Test status
Simulation time 238490050 ps
CPU time 0.92 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206456 kb
Host smart-6d8c85eb-c3db-4119-b489-c4af60fb6669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31312
88218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3131288218
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.4227704471
Short name T1879
Test name
Test status
Simulation time 165015648 ps
CPU time 0.83 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206468 kb
Host smart-ffeef022-eac4-4b12-a19f-5b37568019de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42277
04471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.4227704471
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.74138534
Short name T641
Test name
Test status
Simulation time 199019589 ps
CPU time 0.94 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206464 kb
Host smart-ece54d20-9fe3-4638-a777-b06e1370502e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74138
534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.74138534
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1790248876
Short name T1555
Test name
Test status
Simulation time 1326268620 ps
CPU time 2.9 seconds
Started Jul 17 07:57:10 PM PDT 24
Finished Jul 17 07:57:14 PM PDT 24
Peak memory 206832 kb
Host smart-88b7bfb4-b6e7-45bb-a94d-dda37e85f48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17902
48876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1790248876
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.40480856
Short name T1980
Test name
Test status
Simulation time 20291610783 ps
CPU time 41.71 seconds
Started Jul 17 07:57:15 PM PDT 24
Finished Jul 17 07:58:02 PM PDT 24
Peak memory 206668 kb
Host smart-85bc242d-05e1-48f4-b4b2-7fa38a2b8b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40480
856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.40480856
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.25180511
Short name T1123
Test name
Test status
Simulation time 320300891 ps
CPU time 1.09 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:16 PM PDT 24
Peak memory 206412 kb
Host smart-f44f30d8-2c2d-4640-be4e-49381fba0442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180
511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.25180511
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2755625436
Short name T2727
Test name
Test status
Simulation time 173799464 ps
CPU time 0.82 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:17 PM PDT 24
Peak memory 206448 kb
Host smart-d056b5e6-8b1e-4ba9-a08d-27690510cec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27556
25436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2755625436
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1948993532
Short name T759
Test name
Test status
Simulation time 34258456 ps
CPU time 0.64 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:15 PM PDT 24
Peak memory 206444 kb
Host smart-b36dd1ad-614e-45ab-9f00-ab86c837aa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19489
93532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1948993532
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.611805015
Short name T380
Test name
Test status
Simulation time 841225769 ps
CPU time 2.12 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:17 PM PDT 24
Peak memory 206596 kb
Host smart-6e953fe8-2be4-43e6-a9e2-66944d9e007c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61180
5015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.611805015
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1929777578
Short name T1309
Test name
Test status
Simulation time 182392565 ps
CPU time 1.79 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:22 PM PDT 24
Peak memory 206604 kb
Host smart-d7e9be30-3e7a-4450-a2cd-b185a78a1553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19297
77578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1929777578
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.222812040
Short name T700
Test name
Test status
Simulation time 245030381 ps
CPU time 0.9 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:16 PM PDT 24
Peak memory 206432 kb
Host smart-0a8f5239-9375-46ab-8f90-243afdb46151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22281
2040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.222812040
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1289603873
Short name T998
Test name
Test status
Simulation time 161993349 ps
CPU time 0.75 seconds
Started Jul 17 07:57:10 PM PDT 24
Finished Jul 17 07:57:12 PM PDT 24
Peak memory 206444 kb
Host smart-62fcc636-d4ce-47f4-8cbd-05162c99154f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12896
03873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1289603873
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.103414687
Short name T789
Test name
Test status
Simulation time 245197348 ps
CPU time 0.94 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206456 kb
Host smart-9bf42100-5035-4720-bae4-c41e2a3e823d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10341
4687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.103414687
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.250869017
Short name T1099
Test name
Test status
Simulation time 6022394525 ps
CPU time 43.59 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:58:03 PM PDT 24
Peak memory 206648 kb
Host smart-4b8696db-b6cb-4a02-a965-45d62b65eae4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=250869017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.250869017
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.2479878273
Short name T2492
Test name
Test status
Simulation time 11725085287 ps
CPU time 95.64 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206236 kb
Host smart-d9cd2dc4-89b2-4a9b-95d5-bdbddc2b10d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
78273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.2479878273
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2847018211
Short name T1530
Test name
Test status
Simulation time 180411823 ps
CPU time 0.84 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:57:15 PM PDT 24
Peak memory 206376 kb
Host smart-97b7c2a3-0683-43ae-8a88-b6743355b33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470
18211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2847018211
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.696064578
Short name T1202
Test name
Test status
Simulation time 23340234765 ps
CPU time 25.08 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:57:39 PM PDT 24
Peak memory 206468 kb
Host smart-90292127-bc3c-4f55-8d1d-0420294eb8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69606
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.696064578
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.4261197444
Short name T1576
Test name
Test status
Simulation time 3316292320 ps
CPU time 3.64 seconds
Started Jul 17 07:57:08 PM PDT 24
Finished Jul 17 07:57:12 PM PDT 24
Peak memory 206520 kb
Host smart-9abcd6d6-52b4-4381-a8a3-49685ac7bab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42611
97444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.4261197444
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.4281405933
Short name T1403
Test name
Test status
Simulation time 12171448547 ps
CPU time 89.91 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:58:48 PM PDT 24
Peak memory 206688 kb
Host smart-7c537c04-350f-48d3-aa66-079b890b5ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42814
05933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.4281405933
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3627880636
Short name T656
Test name
Test status
Simulation time 4565443159 ps
CPU time 117.72 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:59:17 PM PDT 24
Peak memory 206808 kb
Host smart-f7e8b9b4-0ed5-4fea-9d67-f00290b4962b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3627880636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3627880636
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1598428896
Short name T2558
Test name
Test status
Simulation time 236833601 ps
CPU time 0.91 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:18 PM PDT 24
Peak memory 206448 kb
Host smart-f64ec879-4e1a-4272-8da3-5b38fa2d97ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1598428896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1598428896
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1700369824
Short name T2086
Test name
Test status
Simulation time 182933611 ps
CPU time 0.87 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:21 PM PDT 24
Peak memory 206456 kb
Host smart-5d198a3a-0488-4c65-88eb-638c551452a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17003
69824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1700369824
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.4030923599
Short name T835
Test name
Test status
Simulation time 3483986953 ps
CPU time 24.44 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206652 kb
Host smart-ac96e056-0b2a-4e2a-a431-88bfdb5805e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40309
23599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.4030923599
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3464378885
Short name T976
Test name
Test status
Simulation time 4502621429 ps
CPU time 41.63 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:57:56 PM PDT 24
Peak memory 206656 kb
Host smart-098b8591-46e6-457b-848f-f04fcc0b12e2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3464378885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3464378885
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.4288548940
Short name T1951
Test name
Test status
Simulation time 153348612 ps
CPU time 0.74 seconds
Started Jul 17 07:57:07 PM PDT 24
Finished Jul 17 07:57:09 PM PDT 24
Peak memory 206456 kb
Host smart-369f7e67-43aa-4808-b405-d7da071a2b7a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4288548940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.4288548940
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1083912379
Short name T1861
Test name
Test status
Simulation time 148722128 ps
CPU time 0.75 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:57:25 PM PDT 24
Peak memory 206452 kb
Host smart-3534a14f-dd74-4857-9373-52509afa2ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10839
12379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1083912379
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3794548071
Short name T132
Test name
Test status
Simulation time 210559453 ps
CPU time 0.89 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:18 PM PDT 24
Peak memory 206448 kb
Host smart-13b32276-9fd8-4bb2-912d-96da575b90e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37945
48071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3794548071
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2849004236
Short name T1347
Test name
Test status
Simulation time 175702226 ps
CPU time 0.84 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206284 kb
Host smart-9e344bbf-7460-43c3-80a9-a36977df71b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28490
04236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2849004236
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3206375111
Short name T452
Test name
Test status
Simulation time 162998891 ps
CPU time 0.81 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:16 PM PDT 24
Peak memory 206456 kb
Host smart-9edf1416-5bb3-4222-8c40-373fa5a144ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32063
75111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3206375111
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1074199088
Short name T1101
Test name
Test status
Simulation time 160014589 ps
CPU time 0.76 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:57:14 PM PDT 24
Peak memory 206580 kb
Host smart-f8e52879-0b04-4aed-b547-74f59c8c1316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10741
99088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1074199088
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1775634719
Short name T1512
Test name
Test status
Simulation time 177713022 ps
CPU time 0.8 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:16 PM PDT 24
Peak memory 206412 kb
Host smart-a14b393f-d9db-48af-a3de-0192755740e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17756
34719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1775634719
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3950021484
Short name T1262
Test name
Test status
Simulation time 247350020 ps
CPU time 0.99 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206440 kb
Host smart-48f69c63-1d3d-42aa-9b54-67d3340c0415
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3950021484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3950021484
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3228394076
Short name T2073
Test name
Test status
Simulation time 155918821 ps
CPU time 0.78 seconds
Started Jul 17 07:57:15 PM PDT 24
Finished Jul 17 07:57:22 PM PDT 24
Peak memory 206460 kb
Host smart-98daa6e2-1ea8-42ad-a1f5-64055949248c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32283
94076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3228394076
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1166431426
Short name T1590
Test name
Test status
Simulation time 41627663 ps
CPU time 0.68 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206172 kb
Host smart-15ed0da6-305b-4278-83dc-6a9e7a0dd796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11664
31426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1166431426
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1303990210
Short name T2238
Test name
Test status
Simulation time 14600795601 ps
CPU time 31.43 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:49 PM PDT 24
Peak memory 206696 kb
Host smart-59ebd035-de28-4f95-a748-cb8f0af548ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13039
90210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1303990210
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2680420846
Short name T2172
Test name
Test status
Simulation time 180016488 ps
CPU time 0.84 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206464 kb
Host smart-a0a9e33d-857e-4cdb-a6b1-b8dd713de725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26804
20846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2680420846
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4168222871
Short name T591
Test name
Test status
Simulation time 228353088 ps
CPU time 0.94 seconds
Started Jul 17 07:57:10 PM PDT 24
Finished Jul 17 07:57:13 PM PDT 24
Peak memory 206448 kb
Host smart-96529bef-caed-4351-998c-dd4367bba531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41682
22871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4168222871
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.460032405
Short name T2567
Test name
Test status
Simulation time 247951657 ps
CPU time 0.85 seconds
Started Jul 17 07:57:11 PM PDT 24
Finished Jul 17 07:57:15 PM PDT 24
Peak memory 206452 kb
Host smart-2d510fda-a203-4c9a-942a-0ef62a56d1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46003
2405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.460032405
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1767641626
Short name T468
Test name
Test status
Simulation time 183757151 ps
CPU time 0.82 seconds
Started Jul 17 07:57:10 PM PDT 24
Finished Jul 17 07:57:12 PM PDT 24
Peak memory 206436 kb
Host smart-25e9ad55-44c7-473e-8617-7a3b8373e2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17676
41626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1767641626
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2469421839
Short name T1141
Test name
Test status
Simulation time 165481655 ps
CPU time 0.76 seconds
Started Jul 17 07:57:15 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206448 kb
Host smart-b6a640f4-0f41-4f8d-b29f-f22c6e9a7021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24694
21839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2469421839
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3584675915
Short name T1508
Test name
Test status
Simulation time 175408427 ps
CPU time 0.77 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206452 kb
Host smart-f97c388d-a454-4687-850e-34146225d5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35846
75915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3584675915
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1097933134
Short name T884
Test name
Test status
Simulation time 168957911 ps
CPU time 0.81 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206436 kb
Host smart-5d21129c-ae91-43d8-ac16-c9edf2c3e0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10979
33134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1097933134
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2109398534
Short name T2710
Test name
Test status
Simulation time 251267842 ps
CPU time 0.96 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206460 kb
Host smart-c6d6a635-3d76-41a1-8f3a-a1e645790ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21093
98534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2109398534
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1525538174
Short name T2274
Test name
Test status
Simulation time 6273232668 ps
CPU time 177.67 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 08:00:21 PM PDT 24
Peak memory 206752 kb
Host smart-7a675eec-b479-4da7-aa61-e74e4495e486
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1525538174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1525538174
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1469570161
Short name T405
Test name
Test status
Simulation time 182231833 ps
CPU time 0.84 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206404 kb
Host smart-750c4113-b070-4065-94f3-1371ab7666d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14695
70161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1469570161
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.4165822838
Short name T2544
Test name
Test status
Simulation time 185948672 ps
CPU time 0.83 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206452 kb
Host smart-e6ac1d62-d33c-44cb-889d-a422a2fe4804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41658
22838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.4165822838
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.1983400144
Short name T1079
Test name
Test status
Simulation time 1000506934 ps
CPU time 2.34 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206584 kb
Host smart-7f0e0347-63a6-4b0e-9ef5-43ae0ef24538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19834
00144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1983400144
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2710612896
Short name T992
Test name
Test status
Simulation time 5045075973 ps
CPU time 140.48 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:59:46 PM PDT 24
Peak memory 206592 kb
Host smart-9991277c-ad62-45f0-8b41-39332ba98b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27106
12896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2710612896
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.1680322607
Short name T176
Test name
Test status
Simulation time 45330922 ps
CPU time 0.7 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206428 kb
Host smart-83f7244a-ce89-4947-8f82-2ae4f3f813f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1680322607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1680322607
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1610942750
Short name T14
Test name
Test status
Simulation time 3525252491 ps
CPU time 4.28 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206732 kb
Host smart-27483b25-63de-42e1-8d4e-677315679141
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1610942750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1610942750
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1078360685
Short name T1893
Test name
Test status
Simulation time 13460323681 ps
CPU time 17.27 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206700 kb
Host smart-260b9038-7f22-4c02-9534-cde1eff67d62
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1078360685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1078360685
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2388579091
Short name T1324
Test name
Test status
Simulation time 23406259957 ps
CPU time 25.53 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:51 PM PDT 24
Peak memory 206728 kb
Host smart-97615dd2-bc70-44d7-9e69-0e2ed7f236d5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2388579091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2388579091
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2751081511
Short name T1928
Test name
Test status
Simulation time 148807231 ps
CPU time 0.78 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206452 kb
Host smart-830ab789-8221-418f-8fce-b37040e2fbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27510
81511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2751081511
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.128803696
Short name T1061
Test name
Test status
Simulation time 151459676 ps
CPU time 0.73 seconds
Started Jul 17 07:57:15 PM PDT 24
Finished Jul 17 07:57:21 PM PDT 24
Peak memory 206436 kb
Host smart-f2b08709-e81b-49af-8d34-0b24c72ce658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12880
3696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.128803696
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1148364230
Short name T867
Test name
Test status
Simulation time 347692471 ps
CPU time 1.18 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206452 kb
Host smart-7e8da6a9-0a66-4e27-aada-38f004547edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11483
64230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1148364230
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3522790813
Short name T1974
Test name
Test status
Simulation time 1266676718 ps
CPU time 2.81 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206660 kb
Host smart-d6beaabd-31dc-4b35-b13b-6353dce991c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35227
90813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3522790813
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.274452252
Short name T155
Test name
Test status
Simulation time 17955296720 ps
CPU time 29.51 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:52 PM PDT 24
Peak memory 206708 kb
Host smart-b25ebfd7-779b-4b59-be75-0704d6b11793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27445
2252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.274452252
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1076796392
Short name T939
Test name
Test status
Simulation time 342251595 ps
CPU time 1.09 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206456 kb
Host smart-bbdde2b3-f3c4-4079-ac40-cd521a8a71e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10767
96392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1076796392
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1410149569
Short name T871
Test name
Test status
Simulation time 141614588 ps
CPU time 0.73 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206448 kb
Host smart-ecc05297-06bf-49f3-b6a7-1a3ccca5e211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14101
49569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1410149569
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3273362680
Short name T634
Test name
Test status
Simulation time 79582114 ps
CPU time 0.73 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:19 PM PDT 24
Peak memory 206444 kb
Host smart-240c6a19-f9fd-4348-8859-31601498b1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733
62680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3273362680
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3967384619
Short name T1833
Test name
Test status
Simulation time 973953949 ps
CPU time 2.18 seconds
Started Jul 17 07:57:17 PM PDT 24
Finished Jul 17 07:57:26 PM PDT 24
Peak memory 206580 kb
Host smart-0e584bd0-790a-4129-bf89-c5bc90e2c324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39673
84619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3967384619
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3856802027
Short name T2606
Test name
Test status
Simulation time 225327029 ps
CPU time 1.43 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206560 kb
Host smart-384bee3c-6293-4dcf-85d7-38c60f20c9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38568
02027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3856802027
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1993460109
Short name T1518
Test name
Test status
Simulation time 214525894 ps
CPU time 0.84 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:16 PM PDT 24
Peak memory 206468 kb
Host smart-6e009a70-8f6e-43a6-a983-711d3d5eea49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19934
60109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1993460109
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.767403301
Short name T2034
Test name
Test status
Simulation time 139844735 ps
CPU time 0.8 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:57:25 PM PDT 24
Peak memory 206444 kb
Host smart-1935b009-7948-4eae-9754-320bd8fe8ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76740
3301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.767403301
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.752356022
Short name T1977
Test name
Test status
Simulation time 227660208 ps
CPU time 0.9 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206408 kb
Host smart-14104f72-fb61-4b63-b6a7-00e21ce56ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75235
6022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.752356022
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.3728522403
Short name T2737
Test name
Test status
Simulation time 11240057288 ps
CPU time 88.91 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:58:54 PM PDT 24
Peak memory 206660 kb
Host smart-4ae0a662-39a2-43cc-abfc-165b8f6e6b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37285
22403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3728522403
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1030985693
Short name T889
Test name
Test status
Simulation time 265095811 ps
CPU time 0.92 seconds
Started Jul 17 07:57:10 PM PDT 24
Finished Jul 17 07:57:12 PM PDT 24
Peak memory 206448 kb
Host smart-ca49434c-1fce-403a-836d-562432ac71e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10309
85693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1030985693
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.912143688
Short name T2097
Test name
Test status
Simulation time 23262574592 ps
CPU time 25.95 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:52 PM PDT 24
Peak memory 206476 kb
Host smart-0d315e50-730b-4e9a-b21f-8c06abab67e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91214
3688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.912143688
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.22565985
Short name T2543
Test name
Test status
Simulation time 3318317037 ps
CPU time 4.39 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:30 PM PDT 24
Peak memory 206512 kb
Host smart-976492ad-9f51-430d-8f89-d7eee96abc9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22565
985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.22565985
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.3140115299
Short name T2506
Test name
Test status
Simulation time 10873658551 ps
CPU time 78.93 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206660 kb
Host smart-1214f43e-72dd-4d28-9bc4-d32c8586219d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31401
15299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.3140115299
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1113322530
Short name T569
Test name
Test status
Simulation time 4413963700 ps
CPU time 40.4 seconds
Started Jul 17 07:57:17 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206708 kb
Host smart-003ba00a-a02f-4871-8b0a-8bbd98b22e15
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1113322530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1113322530
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1004626903
Short name T1839
Test name
Test status
Simulation time 307857025 ps
CPU time 0.95 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206448 kb
Host smart-de0d0fcf-67fe-4fa4-9ab7-77eaeaa318e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1004626903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1004626903
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2889896020
Short name T1418
Test name
Test status
Simulation time 197278079 ps
CPU time 0.85 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206452 kb
Host smart-e2634182-dc11-4c3a-a555-3de5fbbdc742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28898
96020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2889896020
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2413326836
Short name T147
Test name
Test status
Simulation time 4881566798 ps
CPU time 138.86 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:59:45 PM PDT 24
Peak memory 206696 kb
Host smart-470e65c9-79b4-4a69-bfd6-dd927e2d797b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24133
26836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2413326836
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1244068228
Short name T369
Test name
Test status
Simulation time 4922320507 ps
CPU time 45.34 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206716 kb
Host smart-058dbc1f-9f4b-4ab5-9428-c24dd9939357
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1244068228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1244068228
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.3711697550
Short name T325
Test name
Test status
Simulation time 182741114 ps
CPU time 0.87 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206456 kb
Host smart-b4544bd8-7ae3-4a1a-b735-12aee33eb304
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3711697550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.3711697550
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1805710447
Short name T2491
Test name
Test status
Simulation time 151459243 ps
CPU time 0.74 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:57:26 PM PDT 24
Peak memory 206452 kb
Host smart-88be656c-0ec6-4291-8330-1120ec028f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18057
10447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1805710447
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2837308865
Short name T122
Test name
Test status
Simulation time 176922684 ps
CPU time 0.82 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206452 kb
Host smart-b2bbfbeb-d764-4d4f-9ff2-bcc565be31fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28373
08865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2837308865
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.793554323
Short name T1260
Test name
Test status
Simulation time 189257478 ps
CPU time 0.77 seconds
Started Jul 17 07:57:21 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206444 kb
Host smart-a7f4c243-b474-44cc-9c8b-963319ac81df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79355
4323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.793554323
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3076656985
Short name T1339
Test name
Test status
Simulation time 180727189 ps
CPU time 0.85 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206448 kb
Host smart-3e5ce7ed-240d-4589-88e1-b0080ff29d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30766
56985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3076656985
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.4167162906
Short name T2694
Test name
Test status
Simulation time 166065090 ps
CPU time 0.79 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206452 kb
Host smart-bf3321a1-6b56-4129-a788-f47b89d93df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41671
62906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.4167162906
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2154849939
Short name T2190
Test name
Test status
Simulation time 161610171 ps
CPU time 0.78 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206420 kb
Host smart-6bc1d5ff-992a-444b-9b56-55c8fcd626eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21548
49939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2154849939
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.632234503
Short name T1069
Test name
Test status
Simulation time 215881780 ps
CPU time 0.94 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:21 PM PDT 24
Peak memory 206464 kb
Host smart-20eb6574-949f-47ee-ad6a-02d2c960aa4e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=632234503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.632234503
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2408676438
Short name T1516
Test name
Test status
Simulation time 186696592 ps
CPU time 0.76 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206408 kb
Host smart-64ce548a-87b4-45f0-b06c-8fb9121cee7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
76438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2408676438
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2058645891
Short name T2566
Test name
Test status
Simulation time 51437028 ps
CPU time 0.67 seconds
Started Jul 17 07:57:21 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206452 kb
Host smart-dd7b3a52-8abd-419f-a6c6-9ec76f249819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20586
45891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2058645891
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.712388410
Short name T2095
Test name
Test status
Simulation time 10246595723 ps
CPU time 23.65 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:51 PM PDT 24
Peak memory 206740 kb
Host smart-a6991708-8bdf-43a1-8086-15d56870fc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71238
8410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.712388410
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2349686991
Short name T2232
Test name
Test status
Simulation time 175443468 ps
CPU time 0.9 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206460 kb
Host smart-8be004c2-e9a0-4bb1-ac05-42d15196f65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23496
86991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2349686991
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2158802622
Short name T1475
Test name
Test status
Simulation time 181818689 ps
CPU time 0.82 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:16 PM PDT 24
Peak memory 206456 kb
Host smart-7e8d6dc8-ce11-4b65-9122-97003d67a047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21588
02622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2158802622
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2074454638
Short name T1591
Test name
Test status
Simulation time 234058971 ps
CPU time 0.88 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:17 PM PDT 24
Peak memory 206456 kb
Host smart-546655ca-63db-4213-b478-09c5f723ca40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20744
54638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2074454638
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2089806293
Short name T2161
Test name
Test status
Simulation time 151971368 ps
CPU time 0.8 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206372 kb
Host smart-4e0195cd-b13d-46c4-87fb-92858df2a5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
06293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2089806293
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1674619989
Short name T1191
Test name
Test status
Simulation time 173566055 ps
CPU time 0.78 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206348 kb
Host smart-c3066ff2-94de-4ef6-9e5f-13389f29eeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16746
19989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1674619989
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3215980161
Short name T2299
Test name
Test status
Simulation time 155594140 ps
CPU time 0.83 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206356 kb
Host smart-08b877ef-2e40-441b-8266-72dbb35b4a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32159
80161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3215980161
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.4260857146
Short name T765
Test name
Test status
Simulation time 143526982 ps
CPU time 0.79 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206448 kb
Host smart-9b5058de-4451-4543-b960-257585091ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
57146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.4260857146
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.644403477
Short name T1318
Test name
Test status
Simulation time 225351353 ps
CPU time 0.92 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:20 PM PDT 24
Peak memory 206396 kb
Host smart-e84bb70b-7b19-454d-8555-0a693d1e5c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64440
3477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.644403477
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1518906522
Short name T2378
Test name
Test status
Simulation time 3151579535 ps
CPU time 21.75 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:48 PM PDT 24
Peak memory 206708 kb
Host smart-b85ee8e1-c009-44d0-acda-95f6e471b146
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1518906522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1518906522
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2400091847
Short name T70
Test name
Test status
Simulation time 226848427 ps
CPU time 0.83 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 07:57:21 PM PDT 24
Peak memory 206464 kb
Host smart-b6146e49-b480-4c21-b751-b3e63e463121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24000
91847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2400091847
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3046656813
Short name T2100
Test name
Test status
Simulation time 178609195 ps
CPU time 0.79 seconds
Started Jul 17 07:57:12 PM PDT 24
Finished Jul 17 07:57:16 PM PDT 24
Peak memory 206452 kb
Host smart-11e29f29-3ca1-4a63-a367-aefb3f4bfe1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30466
56813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3046656813
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.3123640278
Short name T403
Test name
Test status
Simulation time 863371960 ps
CPU time 1.87 seconds
Started Jul 17 07:57:15 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206664 kb
Host smart-9249b514-05c8-4027-914d-9de653510fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
40278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3123640278
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.773255527
Short name T2104
Test name
Test status
Simulation time 5732315585 ps
CPU time 154.13 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:59:52 PM PDT 24
Peak memory 206668 kb
Host smart-722e0f56-62bf-4445-bc43-ceba4f573438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77325
5527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.773255527
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3015714883
Short name T1328
Test name
Test status
Simulation time 64167919 ps
CPU time 0.69 seconds
Started Jul 17 07:53:26 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206416 kb
Host smart-ede52827-4770-4915-9cda-24c168b265bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3015714883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3015714883
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.243053695
Short name T443
Test name
Test status
Simulation time 3534998129 ps
CPU time 4.6 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:52:59 PM PDT 24
Peak memory 206484 kb
Host smart-2ec61133-238d-48ec-b713-3a47bc5f520e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=243053695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.243053695
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.249433276
Short name T8
Test name
Test status
Simulation time 13425576131 ps
CPU time 15.97 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:53:08 PM PDT 24
Peak memory 206512 kb
Host smart-e41772f9-3aba-422c-af31-54693c0a393f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=249433276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.249433276
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2777325434
Short name T2603
Test name
Test status
Simulation time 23417553102 ps
CPU time 23.26 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:53:17 PM PDT 24
Peak memory 206520 kb
Host smart-0b0b12cb-a152-4571-bebb-c70cd24822b3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2777325434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2777325434
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3816218610
Short name T876
Test name
Test status
Simulation time 225123339 ps
CPU time 0.88 seconds
Started Jul 17 07:52:51 PM PDT 24
Finished Jul 17 07:52:55 PM PDT 24
Peak memory 206460 kb
Host smart-ae10e9dd-d92f-4a14-bdd1-efb548640676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38162
18610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3816218610
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1379603749
Short name T1914
Test name
Test status
Simulation time 165605181 ps
CPU time 0.77 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:52:51 PM PDT 24
Peak memory 206452 kb
Host smart-ca3ac39e-0d36-4bde-a4a4-0c857be1cb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13796
03749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1379603749
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.604409972
Short name T519
Test name
Test status
Simulation time 284174742 ps
CPU time 1.07 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:52:57 PM PDT 24
Peak memory 206480 kb
Host smart-cfd0792a-5861-4c62-9d05-5c9f09f5f25d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60440
9972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.604409972
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3555830057
Short name T1972
Test name
Test status
Simulation time 778562298 ps
CPU time 1.8 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:52:52 PM PDT 24
Peak memory 206664 kb
Host smart-55a2b596-54ad-44e6-acce-d21c9f7ff9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35558
30057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3555830057
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3314553649
Short name T2435
Test name
Test status
Simulation time 10420925918 ps
CPU time 18.36 seconds
Started Jul 17 07:52:48 PM PDT 24
Finished Jul 17 07:53:07 PM PDT 24
Peak memory 206604 kb
Host smart-827614be-b4d3-466e-9344-98547456f9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145
53649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3314553649
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.4245543087
Short name T366
Test name
Test status
Simulation time 394008741 ps
CPU time 1.24 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 206412 kb
Host smart-75f0c383-c675-4e08-90a8-b25ba9f387cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42455
43087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.4245543087
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1431568858
Short name T2210
Test name
Test status
Simulation time 142583160 ps
CPU time 0.75 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206408 kb
Host smart-27b8aec2-af92-4fb4-9993-701521a2213d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315
68858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1431568858
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1724202494
Short name T1953
Test name
Test status
Simulation time 30396151 ps
CPU time 0.63 seconds
Started Jul 17 07:52:50 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 206440 kb
Host smart-248a0aff-265e-4066-99ca-3d31e72bbacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17242
02494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1724202494
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3477851966
Short name T1669
Test name
Test status
Simulation time 849783690 ps
CPU time 2.04 seconds
Started Jul 17 07:52:52 PM PDT 24
Finished Jul 17 07:52:58 PM PDT 24
Peak memory 206608 kb
Host smart-d0b8371f-99cd-43a1-b3a4-d06476d20737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34778
51966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3477851966
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2757476994
Short name T1630
Test name
Test status
Simulation time 251778165 ps
CPU time 1.88 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206660 kb
Host smart-bcd822b5-3460-4d42-816f-457da67fbd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27574
76994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2757476994
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1308248919
Short name T309
Test name
Test status
Simulation time 97202594481 ps
CPU time 149.32 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:55:51 PM PDT 24
Peak memory 206648 kb
Host smart-f3f16065-b161-4d5c-8b09-a8457400c2df
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1308248919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1308248919
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.2878660518
Short name T2574
Test name
Test status
Simulation time 109293788399 ps
CPU time 147.39 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:55:51 PM PDT 24
Peak memory 206660 kb
Host smart-cd639c57-a0e3-453e-8f53-7403612e8f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878660518 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.2878660518
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.3905219296
Short name T1984
Test name
Test status
Simulation time 108137028184 ps
CPU time 139.14 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:55:43 PM PDT 24
Peak memory 206640 kb
Host smart-27984453-7db1-45a0-82dc-8bcf2f80dce8
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3905219296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.3905219296
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1708301631
Short name T1424
Test name
Test status
Simulation time 97902250332 ps
CPU time 134.48 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:55:37 PM PDT 24
Peak memory 206660 kb
Host smart-9c3105dd-5cbd-4619-bf69-11115b39316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708301631 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1708301631
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3203434402
Short name T969
Test name
Test status
Simulation time 96172188031 ps
CPU time 136.57 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:55:41 PM PDT 24
Peak memory 206492 kb
Host smart-ee703590-8539-43a1-821e-66fedd2a8872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32034
34402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3203434402
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2527644298
Short name T1185
Test name
Test status
Simulation time 206549351 ps
CPU time 0.86 seconds
Started Jul 17 07:53:26 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206444 kb
Host smart-6bb0fa51-32ca-4ecb-aa15-2730092b9cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
44298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2527644298
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.817675905
Short name T1504
Test name
Test status
Simulation time 177402219 ps
CPU time 0.82 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:53:24 PM PDT 24
Peak memory 206416 kb
Host smart-cdeff757-9f4d-470e-b7ee-7d15c50ea329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81767
5905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.817675905
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1592925562
Short name T2470
Test name
Test status
Simulation time 197233173 ps
CPU time 0.84 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:53:24 PM PDT 24
Peak memory 206472 kb
Host smart-a7d1d4ac-6e68-4381-9664-d229de4ec5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15929
25562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1592925562
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3693745424
Short name T2306
Test name
Test status
Simulation time 12538307765 ps
CPU time 97.17 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:55:01 PM PDT 24
Peak memory 206672 kb
Host smart-1db75172-95ac-401b-afe0-27e26f2206d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
45424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3693745424
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1842493635
Short name T1175
Test name
Test status
Simulation time 201128520 ps
CPU time 0.83 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:27 PM PDT 24
Peak memory 206436 kb
Host smart-ba185fdc-0af2-4288-8f3b-fab5d8fdb076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18424
93635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1842493635
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.2064815245
Short name T490
Test name
Test status
Simulation time 23278019066 ps
CPU time 21.54 seconds
Started Jul 17 07:53:20 PM PDT 24
Finished Jul 17 07:53:42 PM PDT 24
Peak memory 206500 kb
Host smart-7f52ef31-c5d4-48f9-86b6-ac9a2ca85f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
15245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.2064815245
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3212162653
Short name T2226
Test name
Test status
Simulation time 3351813862 ps
CPU time 3.73 seconds
Started Jul 17 07:53:23 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206516 kb
Host smart-0d65ed2b-8e87-4ecb-8209-79a91036fb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32121
62653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3212162653
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.4048872506
Short name T2322
Test name
Test status
Simulation time 11038335372 ps
CPU time 310.3 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:58:33 PM PDT 24
Peak memory 206760 kb
Host smart-2b73092e-ca00-49e4-b8ef-1188d51ab9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40488
72506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.4048872506
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.198271462
Short name T1850
Test name
Test status
Simulation time 5349778235 ps
CPU time 48.5 seconds
Started Jul 17 07:53:23 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206668 kb
Host smart-ad65cb7b-91ba-4e5a-9879-45252404b2d8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=198271462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.198271462
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.174408201
Short name T1828
Test name
Test status
Simulation time 265618076 ps
CPU time 0.95 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:53:23 PM PDT 24
Peak memory 206636 kb
Host smart-bb28b432-2c8e-4006-a7a4-b4346998d945
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=174408201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.174408201
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.561532289
Short name T1809
Test name
Test status
Simulation time 188033373 ps
CPU time 0.87 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206460 kb
Host smart-38d63338-e65b-484f-9dab-3386c5cb0293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56153
2289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.561532289
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3586793571
Short name T571
Test name
Test status
Simulation time 4812450706 ps
CPU time 47.1 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:54:09 PM PDT 24
Peak memory 206724 kb
Host smart-8d83891e-f914-4dd9-8ad8-e2b0c61301e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35867
93571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3586793571
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.76253180
Short name T1990
Test name
Test status
Simulation time 4756441439 ps
CPU time 34.66 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:54:01 PM PDT 24
Peak memory 206708 kb
Host smart-fd51fa04-3101-471f-8d4f-5abbc384d43d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=76253180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.76253180
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1416147745
Short name T1564
Test name
Test status
Simulation time 161285735 ps
CPU time 0.76 seconds
Started Jul 17 07:53:20 PM PDT 24
Finished Jul 17 07:53:21 PM PDT 24
Peak memory 206420 kb
Host smart-23ec5196-537a-4314-b7df-b2ade2f89a16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1416147745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1416147745
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3946121969
Short name T2594
Test name
Test status
Simulation time 150987531 ps
CPU time 0.79 seconds
Started Jul 17 07:53:23 PM PDT 24
Finished Jul 17 07:53:25 PM PDT 24
Peak memory 206404 kb
Host smart-0e861ced-39d1-4474-a099-b9f23b8ae4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39461
21969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3946121969
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.443256869
Short name T1524
Test name
Test status
Simulation time 215798636 ps
CPU time 0.86 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206456 kb
Host smart-db15805e-8244-444e-bd64-fd920a6fcbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44325
6869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.443256869
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2942065176
Short name T1370
Test name
Test status
Simulation time 233917864 ps
CPU time 0.84 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206456 kb
Host smart-e6150bdb-0e22-4948-b31f-4afef4384e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29420
65176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2942065176
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1180916420
Short name T769
Test name
Test status
Simulation time 180596348 ps
CPU time 0.79 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:53:24 PM PDT 24
Peak memory 206456 kb
Host smart-7ac86efe-cbab-4355-9d9b-539707c09d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
16420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1180916420
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.150599210
Short name T934
Test name
Test status
Simulation time 146596831 ps
CPU time 0.77 seconds
Started Jul 17 07:53:23 PM PDT 24
Finished Jul 17 07:53:26 PM PDT 24
Peak memory 206472 kb
Host smart-d7ae632f-2420-4925-a3ea-ce704e2a7c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15059
9210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.150599210
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2252639661
Short name T1447
Test name
Test status
Simulation time 185165860 ps
CPU time 0.88 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:53:23 PM PDT 24
Peak memory 206424 kb
Host smart-df43fc24-11d4-490a-a330-7d8b9ba3e8e8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2252639661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2252639661
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1997925254
Short name T2099
Test name
Test status
Simulation time 259220666 ps
CPU time 1.03 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206436 kb
Host smart-0e06441e-3c80-45ef-9b2d-2e73818f7a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19979
25254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1997925254
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.650229602
Short name T34
Test name
Test status
Simulation time 162347580 ps
CPU time 0.77 seconds
Started Jul 17 07:53:23 PM PDT 24
Finished Jul 17 07:53:25 PM PDT 24
Peak memory 206464 kb
Host smart-2c0d6860-efaa-416c-824a-2f00f04fa10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65022
9602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.650229602
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.660458889
Short name T2375
Test name
Test status
Simulation time 79223801 ps
CPU time 0.68 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:53:25 PM PDT 24
Peak memory 206428 kb
Host smart-57912e9f-bf19-4592-b1d9-c938ed7e92a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66045
8889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.660458889
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1865710822
Short name T87
Test name
Test status
Simulation time 11565315966 ps
CPU time 25.73 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:53:50 PM PDT 24
Peak memory 206420 kb
Host smart-ae2256c8-d236-42c2-afea-e8d06910ab47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
10822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1865710822
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1547796165
Short name T2564
Test name
Test status
Simulation time 160518819 ps
CPU time 0.8 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:27 PM PDT 24
Peak memory 206424 kb
Host smart-319f7244-7d01-488d-9893-48e156ab26ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
96165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1547796165
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3595079342
Short name T508
Test name
Test status
Simulation time 256192229 ps
CPU time 0.86 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:53:23 PM PDT 24
Peak memory 206436 kb
Host smart-5f234fe6-d240-4e51-8ef6-2718b7e703fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
79342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3595079342
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3379689774
Short name T2192
Test name
Test status
Simulation time 18038975733 ps
CPU time 158.07 seconds
Started Jul 17 07:53:26 PM PDT 24
Finished Jul 17 07:56:06 PM PDT 24
Peak memory 206664 kb
Host smart-96c3604d-76ee-4d18-9f2f-dedf901b6a03
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3379689774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3379689774
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2522075034
Short name T1707
Test name
Test status
Simulation time 13508045844 ps
CPU time 266.96 seconds
Started Jul 17 07:53:42 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206764 kb
Host smart-e0d5dd36-d2aa-451f-a04e-8a3fdd35c9d6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2522075034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2522075034
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.50408642
Short name T2716
Test name
Test status
Simulation time 12554882969 ps
CPU time 245.05 seconds
Started Jul 17 07:53:23 PM PDT 24
Finished Jul 17 07:57:30 PM PDT 24
Peak memory 206680 kb
Host smart-a62109a6-998e-475b-8bc6-eadcd33cbd85
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=50408642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.50408642
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3602931841
Short name T2425
Test name
Test status
Simulation time 167660755 ps
CPU time 0.8 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206468 kb
Host smart-d8d82dc0-aea8-4b15-804a-692f7b070f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36029
31841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3602931841
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.194243755
Short name T1902
Test name
Test status
Simulation time 179142020 ps
CPU time 0.84 seconds
Started Jul 17 07:53:23 PM PDT 24
Finished Jul 17 07:53:27 PM PDT 24
Peak memory 206456 kb
Host smart-d28dc411-bc52-4be2-9b1c-e8658b825559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19424
3755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.194243755
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3494590420
Short name T662
Test name
Test status
Simulation time 218039459 ps
CPU time 0.84 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:53:25 PM PDT 24
Peak memory 206452 kb
Host smart-34dee42f-7ed0-4de7-bcd9-2f22afb45d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34945
90420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3494590420
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3060845634
Short name T2314
Test name
Test status
Simulation time 196528765 ps
CPU time 0.81 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:53:23 PM PDT 24
Peak memory 206440 kb
Host smart-fe5b7a1d-f3e9-4c30-bc0a-2a02e5fe2af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30608
45634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3060845634
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3420772620
Short name T54
Test name
Test status
Simulation time 429646935 ps
CPU time 1.27 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:53:25 PM PDT 24
Peak memory 206440 kb
Host smart-3527122b-fefe-4f13-aeb7-86c9b0db0c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34207
72620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3420772620
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2108305502
Short name T1994
Test name
Test status
Simulation time 208890957 ps
CPU time 0.87 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:53:22 PM PDT 24
Peak memory 206432 kb
Host smart-83d6786a-e994-45c5-a16a-9c75079a1725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083
05502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2108305502
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3118228947
Short name T2408
Test name
Test status
Simulation time 149359067 ps
CPU time 0.77 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:27 PM PDT 24
Peak memory 206444 kb
Host smart-6967b1d7-f3b9-4876-a3d8-784049f9abc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31182
28947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3118228947
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.205301026
Short name T1155
Test name
Test status
Simulation time 176112861 ps
CPU time 0.81 seconds
Started Jul 17 07:53:26 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206444 kb
Host smart-cbcf0684-c791-41f1-acfa-cac5c3da8165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20530
1026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.205301026
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3649022413
Short name T913
Test name
Test status
Simulation time 212260437 ps
CPU time 0.95 seconds
Started Jul 17 07:53:22 PM PDT 24
Finished Jul 17 07:53:25 PM PDT 24
Peak memory 206448 kb
Host smart-bf180198-30d8-412d-ba61-d00d075292af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36490
22413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3649022413
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1083924283
Short name T5
Test name
Test status
Simulation time 3994534299 ps
CPU time 111.26 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:55:18 PM PDT 24
Peak memory 206668 kb
Host smart-c9124374-3840-4bdf-a639-5a53f1ca9939
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1083924283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1083924283
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.964769539
Short name T1129
Test name
Test status
Simulation time 237031693 ps
CPU time 0.85 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:27 PM PDT 24
Peak memory 206468 kb
Host smart-cce55347-b1c0-42a1-8fee-5fc18e2d78db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96476
9539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.964769539
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.4045614275
Short name T1241
Test name
Test status
Simulation time 161797035 ps
CPU time 0.79 seconds
Started Jul 17 07:53:26 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206452 kb
Host smart-28cca0c7-4f80-4b83-a6c2-a57d619af80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
14275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.4045614275
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1083875524
Short name T1945
Test name
Test status
Simulation time 504704554 ps
CPU time 1.45 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206468 kb
Host smart-e59eecd5-22ab-4cd9-b60c-bdaf3c46229a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10838
75524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1083875524
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2681949761
Short name T1836
Test name
Test status
Simulation time 4996035019 ps
CPU time 124.4 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:55:27 PM PDT 24
Peak memory 206660 kb
Host smart-62afc561-cfbe-4a1a-8270-a93b56994eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26819
49761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2681949761
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.3631952906
Short name T989
Test name
Test status
Simulation time 147228581 ps
CPU time 0.77 seconds
Started Jul 17 07:52:49 PM PDT 24
Finished Jul 17 07:52:51 PM PDT 24
Peak memory 206428 kb
Host smart-1a0eba81-6a16-47d9-bc4b-e74384c1739a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36319
52906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host_handshake.3631952906
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3769009107
Short name T495
Test name
Test status
Simulation time 34757746 ps
CPU time 0.66 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:57:33 PM PDT 24
Peak memory 206392 kb
Host smart-bbf89dd3-9df6-4e40-91b0-19645913c404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3769009107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3769009107
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1606817952
Short name T2066
Test name
Test status
Simulation time 3863020537 ps
CPU time 4.6 seconds
Started Jul 17 07:57:13 PM PDT 24
Finished Jul 17 07:57:23 PM PDT 24
Peak memory 206740 kb
Host smart-3bb47c1c-b198-4cfb-84fa-011f721d7efa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1606817952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1606817952
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.737519421
Short name T1055
Test name
Test status
Simulation time 13379309321 ps
CPU time 13.73 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:37 PM PDT 24
Peak memory 206480 kb
Host smart-66fc39eb-dd88-44b6-893a-f67e9d5f60db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=737519421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.737519421
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.639838395
Short name T1051
Test name
Test status
Simulation time 23371794056 ps
CPU time 27.29 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:50 PM PDT 24
Peak memory 206504 kb
Host smart-1c07186c-5303-471c-bc73-25981ac615d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=639838395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.639838395
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2896134764
Short name T588
Test name
Test status
Simulation time 181649254 ps
CPU time 0.81 seconds
Started Jul 17 07:57:16 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206432 kb
Host smart-d39b4ac5-6048-49b8-945f-e20e0d4ae6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28961
34764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2896134764
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1642891769
Short name T770
Test name
Test status
Simulation time 207611257 ps
CPU time 0.79 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206400 kb
Host smart-2f7e6c07-c72a-4768-aa3a-f7d15575228b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16428
91769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1642891769
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1578172136
Short name T2124
Test name
Test status
Simulation time 341545520 ps
CPU time 1.16 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206368 kb
Host smart-92de351f-a74d-47c1-8b14-5a4e804f986c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15781
72136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1578172136
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2292485357
Short name T445
Test name
Test status
Simulation time 1069789293 ps
CPU time 2.31 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:28 PM PDT 24
Peak memory 206592 kb
Host smart-d70a433d-1497-46b6-960e-c631f77d77fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22924
85357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2292485357
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.435196413
Short name T2324
Test name
Test status
Simulation time 8473670505 ps
CPU time 15.66 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:42 PM PDT 24
Peak memory 206644 kb
Host smart-129fd3f9-1fd0-4afc-af65-073383e8b89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43519
6413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.435196413
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.4191134208
Short name T2482
Test name
Test status
Simulation time 345841146 ps
CPU time 1.15 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:57:26 PM PDT 24
Peak memory 206452 kb
Host smart-60ff3828-dac9-400e-8ebf-9537896d338d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41911
34208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.4191134208
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1173135978
Short name T542
Test name
Test status
Simulation time 148017476 ps
CPU time 0.74 seconds
Started Jul 17 07:57:17 PM PDT 24
Finished Jul 17 07:57:25 PM PDT 24
Peak memory 206452 kb
Host smart-8069a36d-b477-4a6d-a9c6-223e5c113214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11731
35978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1173135978
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.915392816
Short name T646
Test name
Test status
Simulation time 31406213 ps
CPU time 0.63 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:57:25 PM PDT 24
Peak memory 206440 kb
Host smart-1f6c373c-a2f4-4f46-a3b3-b052bc9d6870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91539
2816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.915392816
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.4034251753
Short name T1842
Test name
Test status
Simulation time 931474740 ps
CPU time 2.05 seconds
Started Jul 17 07:57:15 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206484 kb
Host smart-70591af2-adc3-4bc4-a5f4-7e58d02962a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40342
51753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.4034251753
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1474081002
Short name T1901
Test name
Test status
Simulation time 276661335 ps
CPU time 1.66 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:29 PM PDT 24
Peak memory 206648 kb
Host smart-d8a52b57-b6fc-4d47-8ec8-e04c79ff1499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14740
81002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1474081002
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1487949177
Short name T1849
Test name
Test status
Simulation time 185407353 ps
CPU time 0.79 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206448 kb
Host smart-5b58505a-1270-47ed-8e64-9a2238662b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14879
49177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1487949177
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2639619868
Short name T1085
Test name
Test status
Simulation time 146924786 ps
CPU time 0.72 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206372 kb
Host smart-95b65e9d-2f98-493b-859a-45bf90d7631e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26396
19868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2639619868
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1194735255
Short name T993
Test name
Test status
Simulation time 166988967 ps
CPU time 0.81 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206448 kb
Host smart-c7644e78-956e-457e-92a6-2273e11bb6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
35255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1194735255
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2828688519
Short name T388
Test name
Test status
Simulation time 168820637 ps
CPU time 0.86 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206448 kb
Host smart-dca168af-48b7-48f2-913f-e75d288d346f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28286
88519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2828688519
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.2184941626
Short name T2281
Test name
Test status
Simulation time 23340310720 ps
CPU time 25.04 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:51 PM PDT 24
Peak memory 206512 kb
Host smart-750d7faa-a6d3-45de-a936-a3220492bf89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21849
41626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.2184941626
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2022085051
Short name T1027
Test name
Test status
Simulation time 3372798319 ps
CPU time 4.69 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:57:29 PM PDT 24
Peak memory 205676 kb
Host smart-b5632964-82fc-440e-8f82-333653b8babb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20220
85051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2022085051
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2511509722
Short name T1056
Test name
Test status
Simulation time 7535015516 ps
CPU time 213.54 seconds
Started Jul 17 07:57:14 PM PDT 24
Finished Jul 17 08:00:54 PM PDT 24
Peak memory 206728 kb
Host smart-c5039e8e-d4dc-4064-9743-450ba233990b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25115
09722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2511509722
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.40949593
Short name T2205
Test name
Test status
Simulation time 5757693046 ps
CPU time 157.91 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 08:00:05 PM PDT 24
Peak memory 206672 kb
Host smart-b3063ddd-984c-4772-8099-9845c73a5515
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=40949593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.40949593
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2785380647
Short name T347
Test name
Test status
Simulation time 248954631 ps
CPU time 0.9 seconds
Started Jul 17 07:57:18 PM PDT 24
Finished Jul 17 07:57:26 PM PDT 24
Peak memory 205584 kb
Host smart-075ffd02-0479-4c86-844e-645a5c39462e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2785380647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2785380647
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1406876949
Short name T1383
Test name
Test status
Simulation time 199720899 ps
CPU time 0.95 seconds
Started Jul 17 07:57:19 PM PDT 24
Finished Jul 17 07:57:27 PM PDT 24
Peak memory 206452 kb
Host smart-b6c70144-9413-45a8-8bf2-5e18202d8849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14068
76949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1406876949
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.4286279588
Short name T2109
Test name
Test status
Simulation time 4942139294 ps
CPU time 32.9 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:58:01 PM PDT 24
Peak memory 206728 kb
Host smart-ce026cff-a2da-4e74-a106-058205653211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42862
79588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.4286279588
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.4155817700
Short name T593
Test name
Test status
Simulation time 3726065787 ps
CPU time 28.18 seconds
Started Jul 17 07:57:20 PM PDT 24
Finished Jul 17 07:57:56 PM PDT 24
Peak memory 206592 kb
Host smart-bc105e37-c7be-49b0-b81f-52f53c36305f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4155817700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.4155817700
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3093080784
Short name T1715
Test name
Test status
Simulation time 204346729 ps
CPU time 0.9 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206456 kb
Host smart-c6ebe7a2-451e-42b5-a33d-f995ae16b1d0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3093080784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3093080784
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2341014371
Short name T1546
Test name
Test status
Simulation time 145938563 ps
CPU time 0.78 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206456 kb
Host smart-4e9224e4-314a-419d-bf69-6c0971e0b2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23410
14371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2341014371
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.575977498
Short name T130
Test name
Test status
Simulation time 173950216 ps
CPU time 0.87 seconds
Started Jul 17 07:57:38 PM PDT 24
Finished Jul 17 07:57:43 PM PDT 24
Peak memory 206460 kb
Host smart-16d2e13b-8f12-4a85-9fc8-0faca5518b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57597
7498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.575977498
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4054225271
Short name T326
Test name
Test status
Simulation time 186131293 ps
CPU time 0.86 seconds
Started Jul 17 07:57:30 PM PDT 24
Finished Jul 17 07:57:32 PM PDT 24
Peak memory 206464 kb
Host smart-0cc72b5a-1d6c-410a-9ef1-5a12b5e4cff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40542
25271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4054225271
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3318641002
Short name T1247
Test name
Test status
Simulation time 182080842 ps
CPU time 0.79 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:38 PM PDT 24
Peak memory 206444 kb
Host smart-3d805389-a044-451d-91e6-96d94cce68a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33186
41002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3318641002
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3822298450
Short name T1496
Test name
Test status
Simulation time 162093399 ps
CPU time 0.8 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:57:33 PM PDT 24
Peak memory 206400 kb
Host smart-8d8c8fdd-2124-4b5a-8839-62689f12ae4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38222
98450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3822298450
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1631167355
Short name T1261
Test name
Test status
Simulation time 154922455 ps
CPU time 0.79 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:36 PM PDT 24
Peak memory 206440 kb
Host smart-322bb826-cf67-43d3-bba7-dc6e3d595a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16311
67355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1631167355
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.807657314
Short name T872
Test name
Test status
Simulation time 195882843 ps
CPU time 0.85 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:38 PM PDT 24
Peak memory 206468 kb
Host smart-af16d459-bce9-4332-9337-318794949231
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=807657314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.807657314
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3054405792
Short name T1947
Test name
Test status
Simulation time 167066372 ps
CPU time 0.8 seconds
Started Jul 17 07:57:37 PM PDT 24
Finished Jul 17 07:57:42 PM PDT 24
Peak memory 206412 kb
Host smart-8ea67dc7-87cb-43ac-9e6e-fa9f183163dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
05792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3054405792
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3078116722
Short name T1499
Test name
Test status
Simulation time 46308110 ps
CPU time 0.64 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206432 kb
Host smart-803967f7-32fd-4eb9-bc4f-b529b6a1088b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781
16722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3078116722
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2301234084
Short name T746
Test name
Test status
Simulation time 21391387853 ps
CPU time 44.95 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:58:24 PM PDT 24
Peak memory 214944 kb
Host smart-07a30ddb-1f1e-4106-92b0-3d91d2badf14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23012
34084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2301234084
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2527028373
Short name T277
Test name
Test status
Simulation time 196161144 ps
CPU time 0.86 seconds
Started Jul 17 07:57:38 PM PDT 24
Finished Jul 17 07:57:43 PM PDT 24
Peak memory 206004 kb
Host smart-27153a02-2b78-40bf-b10e-6a14f4163fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25270
28373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2527028373
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.137525855
Short name T784
Test name
Test status
Simulation time 245802371 ps
CPU time 0.89 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206352 kb
Host smart-ad041fe8-556b-4f03-8975-7fdf78a8aed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
5855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.137525855
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.1104943997
Short name T524
Test name
Test status
Simulation time 202070132 ps
CPU time 0.84 seconds
Started Jul 17 07:57:30 PM PDT 24
Finished Jul 17 07:57:32 PM PDT 24
Peak memory 206456 kb
Host smart-bf3e1065-2862-4a82-bd5c-e1aa436db2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11049
43997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.1104943997
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1720887
Short name T2402
Test name
Test status
Simulation time 186968137 ps
CPU time 0.88 seconds
Started Jul 17 07:57:38 PM PDT 24
Finished Jul 17 07:57:43 PM PDT 24
Peak memory 206456 kb
Host smart-9ef2c9c6-a1de-4f24-bba3-6c36146234f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17208
87 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1720887
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2084814447
Short name T748
Test name
Test status
Simulation time 147672301 ps
CPU time 0.74 seconds
Started Jul 17 07:57:27 PM PDT 24
Finished Jul 17 07:57:30 PM PDT 24
Peak memory 206448 kb
Host smart-8c6cd841-c60e-4598-bd71-1b709a6b710e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20848
14447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2084814447
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3337801524
Short name T2149
Test name
Test status
Simulation time 154988633 ps
CPU time 0.83 seconds
Started Jul 17 07:57:32 PM PDT 24
Finished Jul 17 07:57:34 PM PDT 24
Peak memory 206472 kb
Host smart-1f4c44c7-fd1e-4b47-bd25-e6287a6d6a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33378
01524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3337801524
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.147546065
Short name T435
Test name
Test status
Simulation time 158438968 ps
CPU time 0.76 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206456 kb
Host smart-c5e87f8c-e193-4dd0-8927-b30102f60fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14754
6065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.147546065
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3013746538
Short name T2749
Test name
Test status
Simulation time 280362762 ps
CPU time 1.11 seconds
Started Jul 17 07:57:28 PM PDT 24
Finished Jul 17 07:57:30 PM PDT 24
Peak memory 206456 kb
Host smart-dcac243d-bd66-4219-83ff-be5972ce58a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30137
46538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3013746538
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.637389318
Short name T2135
Test name
Test status
Simulation time 3960060020 ps
CPU time 38.17 seconds
Started Jul 17 07:57:29 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206644 kb
Host smart-b47b8051-a543-47c5-a925-1a6f7f5a9bfa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=637389318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.637389318
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1539272382
Short name T1444
Test name
Test status
Simulation time 197680662 ps
CPU time 0.83 seconds
Started Jul 17 07:57:38 PM PDT 24
Finished Jul 17 07:57:43 PM PDT 24
Peak memory 206300 kb
Host smart-d0e4c4b4-ac4b-4100-95e7-f456c17565ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15392
72382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1539272382
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2080086602
Short name T834
Test name
Test status
Simulation time 165621192 ps
CPU time 0.78 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:38 PM PDT 24
Peak memory 206432 kb
Host smart-ab1cafc0-f47c-48ce-a935-4e899b9f6e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
86602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2080086602
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.569134825
Short name T894
Test name
Test status
Simulation time 334301928 ps
CPU time 1.05 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:36 PM PDT 24
Peak memory 206456 kb
Host smart-111d1279-53f3-458c-99fa-9aeee2d01450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56913
4825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.569134825
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2726892650
Short name T2059
Test name
Test status
Simulation time 4274286489 ps
CPU time 31.14 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:58:03 PM PDT 24
Peak memory 206728 kb
Host smart-0f65d65c-c6e8-4e07-93eb-522e57e6678e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268
92650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2726892650
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1374617660
Short name T1930
Test name
Test status
Simulation time 38197354 ps
CPU time 0.75 seconds
Started Jul 17 07:57:37 PM PDT 24
Finished Jul 17 07:57:42 PM PDT 24
Peak memory 206428 kb
Host smart-cab00a8f-29f6-4e32-a034-e4206f7dd505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1374617660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1374617660
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.4231553442
Short name T462
Test name
Test status
Simulation time 4213803031 ps
CPU time 5.28 seconds
Started Jul 17 07:57:32 PM PDT 24
Finished Jul 17 07:57:39 PM PDT 24
Peak memory 206724 kb
Host smart-b965183d-987e-4929-bb7c-fe8c3f8becac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4231553442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.4231553442
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2811386688
Short name T180
Test name
Test status
Simulation time 13310124078 ps
CPU time 13.92 seconds
Started Jul 17 07:57:30 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206484 kb
Host smart-4095c9b5-2b73-4569-9c42-aa2190909109
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2811386688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2811386688
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2953194344
Short name T1107
Test name
Test status
Simulation time 23370189536 ps
CPU time 22.23 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:58:02 PM PDT 24
Peak memory 206724 kb
Host smart-68f85466-0d7f-452c-a2e9-85798ef5ad06
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2953194344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2953194344
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.804438539
Short name T1644
Test name
Test status
Simulation time 169408175 ps
CPU time 0.81 seconds
Started Jul 17 07:57:32 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206400 kb
Host smart-a6f3b23d-d1bd-4cae-a23f-80ef7f905991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80443
8539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.804438539
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.4046703392
Short name T2198
Test name
Test status
Simulation time 214906389 ps
CPU time 0.83 seconds
Started Jul 17 07:57:29 PM PDT 24
Finished Jul 17 07:57:31 PM PDT 24
Peak memory 206464 kb
Host smart-058f78f4-7c9f-4e6e-996c-14e661de05a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40467
03392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.4046703392
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1192352744
Short name T2227
Test name
Test status
Simulation time 463955571 ps
CPU time 1.36 seconds
Started Jul 17 07:57:30 PM PDT 24
Finished Jul 17 07:57:33 PM PDT 24
Peak memory 206452 kb
Host smart-0ad9add0-a1d2-4c06-bfde-b647ab5d5a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11923
52744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1192352744
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_device_address.4273371986
Short name T675
Test name
Test status
Simulation time 8936789755 ps
CPU time 16.21 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:55 PM PDT 24
Peak memory 206632 kb
Host smart-02862c67-e19e-4204-82fa-0c2a1b38daaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42733
71986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.4273371986
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2360269598
Short name T2609
Test name
Test status
Simulation time 392626355 ps
CPU time 1.31 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206440 kb
Host smart-8dc711f2-147a-486d-a58f-13011a5bdc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
69598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2360269598
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.870439424
Short name T783
Test name
Test status
Simulation time 186318253 ps
CPU time 0.8 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:57:33 PM PDT 24
Peak memory 206452 kb
Host smart-a8701dda-f363-43b7-9f53-9fa08fda5299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87043
9424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.870439424
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1044587170
Short name T535
Test name
Test status
Simulation time 39823296 ps
CPU time 0.66 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:40 PM PDT 24
Peak memory 206244 kb
Host smart-761f186e-a261-4bd3-b65e-7a1f2757999a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10445
87170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1044587170
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.15986559
Short name T313
Test name
Test status
Simulation time 784979045 ps
CPU time 1.85 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206660 kb
Host smart-31ec5fd6-9089-4a33-a41d-730f05c3b55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15986
559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.15986559
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.207837245
Short name T19
Test name
Test status
Simulation time 153927361 ps
CPU time 1.18 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:57:34 PM PDT 24
Peak memory 206604 kb
Host smart-74bb367e-6b56-4236-aade-6b56421b2ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20783
7245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.207837245
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1521518648
Short name T417
Test name
Test status
Simulation time 217740156 ps
CPU time 0.85 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206460 kb
Host smart-4fe6c04d-61ea-4740-8026-301c2eca251e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15215
18648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1521518648
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3498572684
Short name T1878
Test name
Test status
Simulation time 145143708 ps
CPU time 0.79 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:40 PM PDT 24
Peak memory 206440 kb
Host smart-ec6a0771-5b25-422e-9cb6-52f2bf58d843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34985
72684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3498572684
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1880150918
Short name T1084
Test name
Test status
Simulation time 172220118 ps
CPU time 0.8 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206456 kb
Host smart-0f118c97-103c-49a7-8ad5-4c5d861bb2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18801
50918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1880150918
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.1642021877
Short name T1088
Test name
Test status
Simulation time 5748215553 ps
CPU time 43.53 seconds
Started Jul 17 07:57:37 PM PDT 24
Finished Jul 17 07:58:25 PM PDT 24
Peak memory 206700 kb
Host smart-3cf144c6-0d02-4bfc-9a4e-cb9df9739ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420
21877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1642021877
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1524362014
Short name T426
Test name
Test status
Simulation time 283465075 ps
CPU time 0.88 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:57:32 PM PDT 24
Peak memory 206408 kb
Host smart-670bcf36-ae28-490e-9448-24c56c8ccfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15243
62014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1524362014
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3738843619
Short name T1428
Test name
Test status
Simulation time 23287209599 ps
CPU time 22.39 seconds
Started Jul 17 07:57:39 PM PDT 24
Finished Jul 17 07:58:05 PM PDT 24
Peak memory 206524 kb
Host smart-20aee579-009a-4e23-8893-0541b5c4dff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37388
43619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3738843619
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.428439173
Short name T1472
Test name
Test status
Simulation time 3354276654 ps
CPU time 4.98 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:57:37 PM PDT 24
Peak memory 206524 kb
Host smart-ad7ce642-8728-4c4f-adef-e82753d5d75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42843
9173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.428439173
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1901481599
Short name T603
Test name
Test status
Simulation time 12704951148 ps
CPU time 85.76 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:59:04 PM PDT 24
Peak memory 206756 kb
Host smart-7f0f14f9-3f12-4827-af35-d43c91b77014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19014
81599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1901481599
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3597116859
Short name T1400
Test name
Test status
Simulation time 6384303547 ps
CPU time 60.09 seconds
Started Jul 17 07:57:30 PM PDT 24
Finished Jul 17 07:58:32 PM PDT 24
Peak memory 206708 kb
Host smart-99317cc4-db16-487e-b2e4-8c442512d4d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3597116859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3597116859
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.54607692
Short name T1736
Test name
Test status
Simulation time 254985892 ps
CPU time 0.94 seconds
Started Jul 17 07:57:32 PM PDT 24
Finished Jul 17 07:57:34 PM PDT 24
Peak memory 206468 kb
Host smart-f2c003a6-9fe2-493b-9515-df209f6028b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=54607692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.54607692
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3168798372
Short name T2068
Test name
Test status
Simulation time 194187048 ps
CPU time 0.85 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:37 PM PDT 24
Peak memory 206460 kb
Host smart-0c901b30-b94e-48c1-b4af-0fdd6bad98c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31687
98372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3168798372
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.1084897
Short name T2266
Test name
Test status
Simulation time 3997864974 ps
CPU time 38.38 seconds
Started Jul 17 07:57:37 PM PDT 24
Finished Jul 17 07:58:20 PM PDT 24
Peak memory 206648 kb
Host smart-7573572a-b32b-42ab-a515-f7137f3a981f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10848
97 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.1084897
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1423748959
Short name T1194
Test name
Test status
Simulation time 5102293032 ps
CPU time 134.33 seconds
Started Jul 17 07:57:32 PM PDT 24
Finished Jul 17 07:59:48 PM PDT 24
Peak memory 206676 kb
Host smart-16b75fb1-0574-4a82-a0f9-595ff879f724
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1423748959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1423748959
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3877190486
Short name T1604
Test name
Test status
Simulation time 149859667 ps
CPU time 0.8 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:36 PM PDT 24
Peak memory 206456 kb
Host smart-1809169d-e6f4-4624-984f-689951fdd3da
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3877190486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3877190486
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3301250082
Short name T1519
Test name
Test status
Simulation time 147823135 ps
CPU time 0.82 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206452 kb
Host smart-a05922d0-64dd-4104-98ce-8dc52daf26d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33012
50082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3301250082
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2404149862
Short name T1167
Test name
Test status
Simulation time 193973355 ps
CPU time 0.86 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206420 kb
Host smart-91bfb127-9309-4c9b-93f5-59e81b36c6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
49862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2404149862
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2987075977
Short name T547
Test name
Test status
Simulation time 180753552 ps
CPU time 0.8 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:40 PM PDT 24
Peak memory 206460 kb
Host smart-edfa5332-8f09-44c7-9fb5-11ca5d2c3eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29870
75977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2987075977
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3071240080
Short name T331
Test name
Test status
Simulation time 153425368 ps
CPU time 0.82 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:57:40 PM PDT 24
Peak memory 206452 kb
Host smart-e2e3343a-117f-4f55-ad17-3253fd9b3c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30712
40080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3071240080
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.618975155
Short name T2065
Test name
Test status
Simulation time 160652576 ps
CPU time 0.79 seconds
Started Jul 17 07:57:38 PM PDT 24
Finished Jul 17 07:57:43 PM PDT 24
Peak memory 206468 kb
Host smart-92282aba-a14e-4c44-a8f8-d7c94248ea2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61897
5155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.618975155
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3768696918
Short name T1117
Test name
Test status
Simulation time 192487504 ps
CPU time 0.85 seconds
Started Jul 17 07:57:37 PM PDT 24
Finished Jul 17 07:57:42 PM PDT 24
Peak memory 206336 kb
Host smart-9a65420a-e55d-416a-bf08-a06fe8574268
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3768696918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3768696918
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1776972545
Short name T2400
Test name
Test status
Simulation time 140679940 ps
CPU time 0.81 seconds
Started Jul 17 07:57:32 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206452 kb
Host smart-26a2acd5-bb95-47ca-a9c8-325c7f6546bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17769
72545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1776972545
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1125957926
Short name T476
Test name
Test status
Simulation time 39322132 ps
CPU time 0.66 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:57:40 PM PDT 24
Peak memory 206444 kb
Host smart-91d048ce-3559-426a-bd70-52193c45bd73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
57926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1125957926
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.704274827
Short name T1196
Test name
Test status
Simulation time 21351906806 ps
CPU time 46.63 seconds
Started Jul 17 07:57:38 PM PDT 24
Finished Jul 17 07:58:29 PM PDT 24
Peak memory 214496 kb
Host smart-1164c918-e9ce-4554-964a-ddf5ad1e49a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70427
4827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.704274827
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.955674610
Short name T2160
Test name
Test status
Simulation time 245598641 ps
CPU time 0.86 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:39 PM PDT 24
Peak memory 206460 kb
Host smart-ac2d5fb9-f4cc-4050-bd0c-b5cc41fa8c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95567
4610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.955674610
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.4199829788
Short name T582
Test name
Test status
Simulation time 167953351 ps
CPU time 0.8 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:39 PM PDT 24
Peak memory 206452 kb
Host smart-fb8254ce-9033-4c6e-a9fa-7bb23664f844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41998
29788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.4199829788
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1633742866
Short name T1505
Test name
Test status
Simulation time 193382178 ps
CPU time 0.82 seconds
Started Jul 17 07:57:38 PM PDT 24
Finished Jul 17 07:57:43 PM PDT 24
Peak memory 206364 kb
Host smart-bb2ab4b9-7443-4584-bcea-58dff221d419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16337
42866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1633742866
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3662347292
Short name T2174
Test name
Test status
Simulation time 162251222 ps
CPU time 0.79 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:39 PM PDT 24
Peak memory 206456 kb
Host smart-8aaa0772-7fe5-4f19-91e6-5c62c401c4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36623
47292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3662347292
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3236815212
Short name T47
Test name
Test status
Simulation time 160016046 ps
CPU time 0.86 seconds
Started Jul 17 07:57:43 PM PDT 24
Finished Jul 17 07:57:46 PM PDT 24
Peak memory 206592 kb
Host smart-0eff5a35-e6ff-4e2c-ba1e-d1c086c307d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32368
15212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3236815212
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.4212947729
Short name T507
Test name
Test status
Simulation time 164390440 ps
CPU time 0.79 seconds
Started Jul 17 07:57:43 PM PDT 24
Finished Jul 17 07:57:46 PM PDT 24
Peak memory 206592 kb
Host smart-b2e0c7bd-0397-41ba-ad03-e319c97330da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42129
47729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.4212947729
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.158641970
Short name T598
Test name
Test status
Simulation time 154880740 ps
CPU time 0.78 seconds
Started Jul 17 07:57:43 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206596 kb
Host smart-e20cc83a-6aed-4f98-91b2-2cc944e3d307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15864
1970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.158641970
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.4279743655
Short name T2383
Test name
Test status
Simulation time 231055171 ps
CPU time 0.91 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:37 PM PDT 24
Peak memory 206448 kb
Host smart-51f786f6-766a-4ee0-93e7-c02201db7d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42797
43655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.4279743655
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3190549901
Short name T616
Test name
Test status
Simulation time 4372656457 ps
CPU time 120.53 seconds
Started Jul 17 07:57:43 PM PDT 24
Finished Jul 17 07:59:45 PM PDT 24
Peak memory 206844 kb
Host smart-acf31f25-7aab-4e71-8f89-f8b95a84b85e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3190549901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3190549901
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.254473454
Short name T1377
Test name
Test status
Simulation time 196440259 ps
CPU time 0.85 seconds
Started Jul 17 07:57:32 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206460 kb
Host smart-77394e90-1b89-49cc-8a67-22e18a0244d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25447
3454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.254473454
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2179437598
Short name T1356
Test name
Test status
Simulation time 184867867 ps
CPU time 0.81 seconds
Started Jul 17 07:57:37 PM PDT 24
Finished Jul 17 07:57:42 PM PDT 24
Peak memory 206452 kb
Host smart-779e14c1-a865-4b7e-b167-d170f7ed3424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21794
37598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2179437598
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.4244939673
Short name T302
Test name
Test status
Simulation time 822758465 ps
CPU time 2.14 seconds
Started Jul 17 07:57:37 PM PDT 24
Finished Jul 17 07:57:43 PM PDT 24
Peak memory 206656 kb
Host smart-bcb02290-bd08-49ea-b03f-3421bea9d0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42449
39673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.4244939673
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.663420539
Short name T2280
Test name
Test status
Simulation time 4950560633 ps
CPU time 128.79 seconds
Started Jul 17 07:57:36 PM PDT 24
Finished Jul 17 07:59:49 PM PDT 24
Peak memory 206664 kb
Host smart-df654270-57c2-451d-b89d-9965cb413e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66342
0539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.663420539
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.3297003439
Short name T2683
Test name
Test status
Simulation time 39066993 ps
CPU time 0.69 seconds
Started Jul 17 07:57:50 PM PDT 24
Finished Jul 17 07:57:52 PM PDT 24
Peak memory 206436 kb
Host smart-e0a1291a-ed6d-43ec-aa0e-c60c4717ec1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3297003439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.3297003439
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.794076702
Short name T12
Test name
Test status
Simulation time 3735278078 ps
CPU time 4.99 seconds
Started Jul 17 07:57:41 PM PDT 24
Finished Jul 17 07:57:49 PM PDT 24
Peak memory 206700 kb
Host smart-9d44c2be-45f7-45ea-b477-987b382b6981
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=794076702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.794076702
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.2062108743
Short name T1093
Test name
Test status
Simulation time 13318165535 ps
CPU time 13.11 seconds
Started Jul 17 07:57:41 PM PDT 24
Finished Jul 17 07:57:57 PM PDT 24
Peak memory 206492 kb
Host smart-c6e71b7b-ab74-4d8b-b92d-1d3834edc2a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2062108743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2062108743
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.2295349232
Short name T2643
Test name
Test status
Simulation time 23352510582 ps
CPU time 24.1 seconds
Started Jul 17 07:57:43 PM PDT 24
Finished Jul 17 07:58:09 PM PDT 24
Peak memory 206676 kb
Host smart-581c6b76-f034-4ea6-aa42-40b3a8499519
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2295349232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.2295349232
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3516275592
Short name T1950
Test name
Test status
Simulation time 153030358 ps
CPU time 0.85 seconds
Started Jul 17 07:57:43 PM PDT 24
Finished Jul 17 07:57:46 PM PDT 24
Peak memory 206588 kb
Host smart-ae684cca-12d2-46a6-901f-9c9ac89ebdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35162
75592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3516275592
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3444016629
Short name T1204
Test name
Test status
Simulation time 168848446 ps
CPU time 0.89 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:40 PM PDT 24
Peak memory 206452 kb
Host smart-4d52a818-759e-49bc-8e17-450f76188525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34440
16629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3444016629
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1799602140
Short name T2384
Test name
Test status
Simulation time 650692629 ps
CPU time 1.73 seconds
Started Jul 17 07:57:31 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206656 kb
Host smart-1b640a99-00fb-4c4c-919d-e71439b514e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17996
02140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1799602140
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1871787958
Short name T2250
Test name
Test status
Simulation time 982053764 ps
CPU time 2.13 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206588 kb
Host smart-6a5f1855-4b99-4430-b80b-e85382637ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18717
87958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1871787958
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2890371985
Short name T557
Test name
Test status
Simulation time 14874513545 ps
CPU time 24.69 seconds
Started Jul 17 07:57:41 PM PDT 24
Finished Jul 17 07:58:09 PM PDT 24
Peak memory 206640 kb
Host smart-9c423565-b2cf-47fd-9757-dfddbaf96e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28903
71985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2890371985
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.449336520
Short name T2293
Test name
Test status
Simulation time 460465825 ps
CPU time 1.47 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:40 PM PDT 24
Peak memory 206440 kb
Host smart-ac57d6c4-ca6b-49b3-8342-63c72c964fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44933
6520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.449336520
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1010491702
Short name T371
Test name
Test status
Simulation time 143290909 ps
CPU time 0.77 seconds
Started Jul 17 07:57:40 PM PDT 24
Finished Jul 17 07:57:44 PM PDT 24
Peak memory 206452 kb
Host smart-bed3478c-37dd-46e4-b938-fcaef7e11c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
91702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1010491702
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.616521076
Short name T363
Test name
Test status
Simulation time 46324857 ps
CPU time 0.7 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:57:40 PM PDT 24
Peak memory 206424 kb
Host smart-9bf76caa-bd34-4458-b55f-9aab2e1d98b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61652
1076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.616521076
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2315419097
Short name T2668
Test name
Test status
Simulation time 833335244 ps
CPU time 2.17 seconds
Started Jul 17 07:57:39 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206600 kb
Host smart-431f3074-bc39-434f-94a8-fc5f4c3d296c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23154
19097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2315419097
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.691263490
Short name T794
Test name
Test status
Simulation time 262905324 ps
CPU time 1.56 seconds
Started Jul 17 07:57:40 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206592 kb
Host smart-f6e4c162-18d3-41f1-a6f0-a533d496c61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69126
3490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.691263490
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.4189233886
Short name T820
Test name
Test status
Simulation time 210905215 ps
CPU time 0.81 seconds
Started Jul 17 07:57:41 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206460 kb
Host smart-474006c6-c7f6-43d3-90d8-2b85ec740f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
33886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.4189233886
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1164504924
Short name T904
Test name
Test status
Simulation time 191060449 ps
CPU time 0.84 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:38 PM PDT 24
Peak memory 206456 kb
Host smart-238464c5-8fe5-4ac7-a001-5c1457e3e880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645
04924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1164504924
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1132632659
Short name T2001
Test name
Test status
Simulation time 211995296 ps
CPU time 0.83 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:39 PM PDT 24
Peak memory 206440 kb
Host smart-5bccde73-a22e-4e34-b9ca-177edba41ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326
32659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1132632659
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.660756652
Short name T1899
Test name
Test status
Simulation time 7709359624 ps
CPU time 68.24 seconds
Started Jul 17 07:57:40 PM PDT 24
Finished Jul 17 07:58:51 PM PDT 24
Peak memory 206680 kb
Host smart-78bbdfdd-5863-48b7-bef4-9caca078e1b0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=660756652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.660756652
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1994138810
Short name T567
Test name
Test status
Simulation time 3575442628 ps
CPU time 12.42 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:57:50 PM PDT 24
Peak memory 206668 kb
Host smart-4ba9c932-2ace-45c1-9ab6-ecf34a40a1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19941
38810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1994138810
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3391867497
Short name T2690
Test name
Test status
Simulation time 235292057 ps
CPU time 0.91 seconds
Started Jul 17 07:57:40 PM PDT 24
Finished Jul 17 07:57:44 PM PDT 24
Peak memory 206452 kb
Host smart-56327464-caf0-4ac9-bb95-abc5ccdf4f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33918
67497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3391867497
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.4204217883
Short name T925
Test name
Test status
Simulation time 23300668629 ps
CPU time 21.68 seconds
Started Jul 17 07:57:33 PM PDT 24
Finished Jul 17 07:57:57 PM PDT 24
Peak memory 206504 kb
Host smart-919290d0-ee09-4a9e-90d5-9096d31703cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42042
17883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.4204217883
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2081559214
Short name T1073
Test name
Test status
Simulation time 3261023015 ps
CPU time 3.74 seconds
Started Jul 17 07:57:40 PM PDT 24
Finished Jul 17 07:57:47 PM PDT 24
Peak memory 206524 kb
Host smart-7d42dc9d-69a9-4940-babd-e62281f1dbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20815
59214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2081559214
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.3813157428
Short name T758
Test name
Test status
Simulation time 8929258228 ps
CPU time 64.65 seconds
Started Jul 17 07:57:34 PM PDT 24
Finished Jul 17 07:58:43 PM PDT 24
Peak memory 206712 kb
Host smart-b9634e1a-883e-4749-b3d1-bd2639cf8e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38131
57428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3813157428
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1900626277
Short name T2532
Test name
Test status
Simulation time 4137837673 ps
CPU time 36.06 seconds
Started Jul 17 07:57:40 PM PDT 24
Finished Jul 17 07:58:19 PM PDT 24
Peak memory 206656 kb
Host smart-2273b946-f72c-4126-b9ae-a4371dd06d02
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1900626277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1900626277
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3045872293
Short name T1631
Test name
Test status
Simulation time 256171203 ps
CPU time 0.92 seconds
Started Jul 17 07:57:41 PM PDT 24
Finished Jul 17 07:57:45 PM PDT 24
Peak memory 206456 kb
Host smart-eba36a37-57e7-48c5-88e2-f022280930d2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3045872293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3045872293
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.17470064
Short name T1059
Test name
Test status
Simulation time 187721222 ps
CPU time 0.82 seconds
Started Jul 17 07:57:40 PM PDT 24
Finished Jul 17 07:57:44 PM PDT 24
Peak memory 206460 kb
Host smart-7a8f8724-a745-4980-86c4-1ab3156d682a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17470
064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.17470064
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2307243393
Short name T1040
Test name
Test status
Simulation time 3936363025 ps
CPU time 108.82 seconds
Started Jul 17 07:57:35 PM PDT 24
Finished Jul 17 07:59:28 PM PDT 24
Peak memory 206672 kb
Host smart-c1080f53-8970-490d-bdbe-9856edbfba61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23072
43393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2307243393
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1828601001
Short name T1775
Test name
Test status
Simulation time 4790027569 ps
CPU time 44.36 seconds
Started Jul 17 07:57:48 PM PDT 24
Finished Jul 17 07:58:33 PM PDT 24
Peak memory 206712 kb
Host smart-fbea8a0f-1cae-4cf4-92b2-268add988376
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1828601001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1828601001
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.3605035553
Short name T2517
Test name
Test status
Simulation time 161341530 ps
CPU time 0.74 seconds
Started Jul 17 07:57:47 PM PDT 24
Finished Jul 17 07:57:49 PM PDT 24
Peak memory 206460 kb
Host smart-439d3c4b-5ae7-4529-b88a-e7238867667f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3605035553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.3605035553
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3024731379
Short name T2362
Test name
Test status
Simulation time 150326588 ps
CPU time 0.8 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206460 kb
Host smart-04c3c524-1d69-452c-8624-6d0b097eab86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30247
31379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3024731379
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1771068137
Short name T2182
Test name
Test status
Simulation time 231194335 ps
CPU time 0.84 seconds
Started Jul 17 07:57:50 PM PDT 24
Finished Jul 17 07:57:51 PM PDT 24
Peak memory 206452 kb
Host smart-8f0feaeb-1010-493b-9c2e-8f31f16bb565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17710
68137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1771068137
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1087031029
Short name T2141
Test name
Test status
Simulation time 165309911 ps
CPU time 0.84 seconds
Started Jul 17 07:57:51 PM PDT 24
Finished Jul 17 07:57:53 PM PDT 24
Peak memory 206444 kb
Host smart-e9fd9602-354a-4c3b-9dce-04455093dce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10870
31029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1087031029
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3687870961
Short name T1464
Test name
Test status
Simulation time 242611302 ps
CPU time 0.88 seconds
Started Jul 17 07:57:50 PM PDT 24
Finished Jul 17 07:57:52 PM PDT 24
Peak memory 206452 kb
Host smart-5082b359-b50d-4560-bf04-a4d73b5c2eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36878
70961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3687870961
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.517860983
Short name T2028
Test name
Test status
Simulation time 159293731 ps
CPU time 0.78 seconds
Started Jul 17 07:57:58 PM PDT 24
Finished Jul 17 07:58:00 PM PDT 24
Peak memory 206412 kb
Host smart-0088893b-3286-476c-b30b-84e3aa56bb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51786
0983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.517860983
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.634557697
Short name T594
Test name
Test status
Simulation time 186089584 ps
CPU time 0.84 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206460 kb
Host smart-f4025a26-d495-49a4-8257-a4a35923fb1f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=634557697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.634557697
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3660546093
Short name T1695
Test name
Test status
Simulation time 194595972 ps
CPU time 0.82 seconds
Started Jul 17 07:57:53 PM PDT 24
Finished Jul 17 07:57:56 PM PDT 24
Peak memory 206460 kb
Host smart-26293499-c612-43f5-9f64-e3c943cdb784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36605
46093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3660546093
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3731574463
Short name T2096
Test name
Test status
Simulation time 36240807 ps
CPU time 0.65 seconds
Started Jul 17 07:57:47 PM PDT 24
Finished Jul 17 07:57:48 PM PDT 24
Peak memory 206444 kb
Host smart-4915b574-cac5-40dc-a5b7-490293f09528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37315
74463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3731574463
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.434865531
Short name T240
Test name
Test status
Simulation time 18875116062 ps
CPU time 41.02 seconds
Started Jul 17 07:57:47 PM PDT 24
Finished Jul 17 07:58:29 PM PDT 24
Peak memory 206736 kb
Host smart-42baba16-2fc5-4b79-a660-d1db1234bfa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43486
5531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.434865531
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3143699750
Short name T1470
Test name
Test status
Simulation time 156661748 ps
CPU time 0.8 seconds
Started Jul 17 07:57:53 PM PDT 24
Finished Jul 17 07:57:55 PM PDT 24
Peak memory 206456 kb
Host smart-65cc9e52-61ce-410c-b6c2-1e8d8e3cf974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31436
99750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3143699750
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2913475474
Short name T409
Test name
Test status
Simulation time 221912422 ps
CPU time 0.94 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206448 kb
Host smart-ca3b4877-d04e-4062-95ca-9bbe8e6cca68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
75474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2913475474
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.704367117
Short name T2122
Test name
Test status
Simulation time 192407982 ps
CPU time 0.86 seconds
Started Jul 17 07:58:01 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206344 kb
Host smart-c89d6741-2dcb-4d8c-8d69-dbd21887e557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70436
7117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.704367117
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1312653130
Short name T2167
Test name
Test status
Simulation time 222755796 ps
CPU time 0.82 seconds
Started Jul 17 07:57:48 PM PDT 24
Finished Jul 17 07:57:50 PM PDT 24
Peak memory 206436 kb
Host smart-3015a823-5a0f-49ca-bd6e-1f40cd69b497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13126
53130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1312653130
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1239306219
Short name T1801
Test name
Test status
Simulation time 203626006 ps
CPU time 0.76 seconds
Started Jul 17 07:57:51 PM PDT 24
Finished Jul 17 07:57:53 PM PDT 24
Peak memory 206448 kb
Host smart-471bbb0f-deda-4450-bca1-0a3b360e0c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12393
06219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1239306219
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2379056823
Short name T2503
Test name
Test status
Simulation time 169929674 ps
CPU time 0.83 seconds
Started Jul 17 07:57:51 PM PDT 24
Finished Jul 17 07:57:53 PM PDT 24
Peak memory 206452 kb
Host smart-08d2c886-ecab-4e65-9f1b-c4ccd5385db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
56823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2379056823
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1847339973
Short name T862
Test name
Test status
Simulation time 180815728 ps
CPU time 0.87 seconds
Started Jul 17 07:57:52 PM PDT 24
Finished Jul 17 07:57:55 PM PDT 24
Peak memory 206456 kb
Host smart-8c6db866-67c9-46d3-a22d-0cc8de408a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18473
39973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1847339973
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2454792914
Short name T1655
Test name
Test status
Simulation time 224155050 ps
CPU time 0.95 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206456 kb
Host smart-f851538b-2817-486c-9550-7a3aa18933eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24547
92914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2454792914
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1476435808
Short name T1455
Test name
Test status
Simulation time 4378057294 ps
CPU time 118.98 seconds
Started Jul 17 07:57:54 PM PDT 24
Finished Jul 17 07:59:54 PM PDT 24
Peak memory 206676 kb
Host smart-8541da5a-8851-4891-b831-667216885b4b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1476435808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1476435808
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3317441350
Short name T1666
Test name
Test status
Simulation time 144637157 ps
CPU time 0.78 seconds
Started Jul 17 07:57:52 PM PDT 24
Finished Jul 17 07:57:55 PM PDT 24
Peak memory 206460 kb
Host smart-bb47cd25-17ac-4e95-8f4c-bf01316050e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33174
41350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3317441350
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.137647280
Short name T908
Test name
Test status
Simulation time 152492320 ps
CPU time 0.76 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206264 kb
Host smart-a65b94fa-592d-497d-820a-ed749d86da55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764
7280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.137647280
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3563376408
Short name T1394
Test name
Test status
Simulation time 376700932 ps
CPU time 1.2 seconds
Started Jul 17 07:57:56 PM PDT 24
Finished Jul 17 07:57:58 PM PDT 24
Peak memory 206460 kb
Host smart-843493dc-39f4-4e3f-aaf3-d2016300c4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
76408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3563376408
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3301931067
Short name T1113
Test name
Test status
Simulation time 4097953346 ps
CPU time 28.13 seconds
Started Jul 17 07:57:51 PM PDT 24
Finished Jul 17 07:58:20 PM PDT 24
Peak memory 206704 kb
Host smart-38098a15-c470-4457-825e-c853b70c6f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33019
31067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3301931067
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3731698156
Short name T618
Test name
Test status
Simulation time 51699651 ps
CPU time 0.72 seconds
Started Jul 17 07:57:49 PM PDT 24
Finished Jul 17 07:57:51 PM PDT 24
Peak memory 206428 kb
Host smart-e25105ca-d462-4c53-9ad6-9b435cd4eafd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3731698156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3731698156
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1888535255
Short name T536
Test name
Test status
Simulation time 4092068678 ps
CPU time 5.25 seconds
Started Jul 17 07:57:51 PM PDT 24
Finished Jul 17 07:57:57 PM PDT 24
Peak memory 206656 kb
Host smart-a84df52c-71b4-4765-ac58-7884dc814354
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1888535255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.1888535255
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.673381333
Short name T1540
Test name
Test status
Simulation time 13351493115 ps
CPU time 13.28 seconds
Started Jul 17 07:57:51 PM PDT 24
Finished Jul 17 07:58:05 PM PDT 24
Peak memory 206524 kb
Host smart-bc823c7d-7721-4286-b075-a11bb73d2fdb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=673381333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.673381333
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1877240432
Short name T1373
Test name
Test status
Simulation time 23439976237 ps
CPU time 24.11 seconds
Started Jul 17 07:57:53 PM PDT 24
Finished Jul 17 07:58:19 PM PDT 24
Peak memory 206524 kb
Host smart-e6bf4f75-7d4f-4a14-8878-0d00c82c4b4c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1877240432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1877240432
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3478702824
Short name T146
Test name
Test status
Simulation time 146257585 ps
CPU time 0.81 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:03 PM PDT 24
Peak memory 206404 kb
Host smart-47e7d372-6b56-434d-bc65-5cb5eea243a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34787
02824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3478702824
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.361989603
Short name T2296
Test name
Test status
Simulation time 149634898 ps
CPU time 0.75 seconds
Started Jul 17 07:58:04 PM PDT 24
Finished Jul 17 07:58:09 PM PDT 24
Peak memory 206456 kb
Host smart-4f2d780e-dee1-4d57-b26e-ac8580cd45e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36198
9603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.361989603
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2103898466
Short name T1744
Test name
Test status
Simulation time 226607088 ps
CPU time 0.98 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206452 kb
Host smart-b45e6eb2-1707-4d26-83a8-8c27281cdf9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
98466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2103898466
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1352029885
Short name T2265
Test name
Test status
Simulation time 947120197 ps
CPU time 2.19 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206604 kb
Host smart-e68c2734-5845-4550-81fc-01f95d143525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13520
29885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1352029885
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2512633176
Short name T785
Test name
Test status
Simulation time 6748319783 ps
CPU time 13.06 seconds
Started Jul 17 07:58:04 PM PDT 24
Finished Jul 17 07:58:21 PM PDT 24
Peak memory 206664 kb
Host smart-9aeff1d8-fd40-40b1-b66b-35dfd773de91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25126
33176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2512633176
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.518545899
Short name T1988
Test name
Test status
Simulation time 383351345 ps
CPU time 1.33 seconds
Started Jul 17 07:57:59 PM PDT 24
Finished Jul 17 07:58:02 PM PDT 24
Peak memory 206412 kb
Host smart-5ebcac87-c3a8-4db0-a024-6f1091e26b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51854
5899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.518545899
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.871900334
Short name T2669
Test name
Test status
Simulation time 157272809 ps
CPU time 0.76 seconds
Started Jul 17 07:57:59 PM PDT 24
Finished Jul 17 07:58:02 PM PDT 24
Peak memory 206408 kb
Host smart-3ca84012-83f1-494c-a023-fd25fc066cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87190
0334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.871900334
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.190763446
Short name T551
Test name
Test status
Simulation time 30627126 ps
CPU time 0.69 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206440 kb
Host smart-5d77b6f8-5a30-4c8b-9841-5b780408fe3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
3446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.190763446
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.139847014
Short name T1808
Test name
Test status
Simulation time 766824869 ps
CPU time 1.79 seconds
Started Jul 17 07:57:50 PM PDT 24
Finished Jul 17 07:57:53 PM PDT 24
Peak memory 206660 kb
Host smart-f45ea889-a0c8-48b9-9768-9a5644f0018b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13984
7014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.139847014
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.319096206
Short name T901
Test name
Test status
Simulation time 204328892 ps
CPU time 1.3 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206592 kb
Host smart-0ffa39f3-350d-428f-81f0-45ab8aca7564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31909
6206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.319096206
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2516008464
Short name T1993
Test name
Test status
Simulation time 174912595 ps
CPU time 0.84 seconds
Started Jul 17 07:58:02 PM PDT 24
Finished Jul 17 07:58:07 PM PDT 24
Peak memory 206452 kb
Host smart-8f72898b-7477-4f53-aaa8-3f1df04db9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
08464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2516008464
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2335373597
Short name T704
Test name
Test status
Simulation time 150472041 ps
CPU time 0.8 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206444 kb
Host smart-df996a91-5f91-4d87-943f-ca95fa098e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23353
73597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2335373597
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.559861769
Short name T398
Test name
Test status
Simulation time 214225751 ps
CPU time 0.86 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:07 PM PDT 24
Peak memory 206448 kb
Host smart-26ab0b33-5137-47b5-b957-2048c34403ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55986
1769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.559861769
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1446014844
Short name T2254
Test name
Test status
Simulation time 241548228 ps
CPU time 0.94 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 206456 kb
Host smart-32b34dbb-802e-4bde-a140-934060c2b7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14460
14844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1446014844
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2963099552
Short name T1925
Test name
Test status
Simulation time 23322783919 ps
CPU time 23.2 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:35 PM PDT 24
Peak memory 206520 kb
Host smart-576709b0-0c87-4592-a803-e2690de5510c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
99552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2963099552
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3170992286
Short name T715
Test name
Test status
Simulation time 3348949615 ps
CPU time 3.87 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:15 PM PDT 24
Peak memory 206520 kb
Host smart-313f8727-ff22-48fd-b80b-5ad45fb1dd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31709
92286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3170992286
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.45863575
Short name T1344
Test name
Test status
Simulation time 7837924414 ps
CPU time 72.54 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:59:23 PM PDT 24
Peak memory 206728 kb
Host smart-e1ff7dc0-7fe3-4ec3-82e7-d98e05b894a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45863
575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.45863575
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.208135317
Short name T2219
Test name
Test status
Simulation time 4692388689 ps
CPU time 121.47 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 08:00:14 PM PDT 24
Peak memory 206692 kb
Host smart-bf21ddb9-c1d7-4b1a-a188-8c4ed4ea7fa0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=208135317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.208135317
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.373571842
Short name T303
Test name
Test status
Simulation time 248356087 ps
CPU time 0.92 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:13 PM PDT 24
Peak memory 206444 kb
Host smart-85c5a4b9-77bf-4392-bf70-3d5911bbabb1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=373571842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.373571842
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3906823811
Short name T2207
Test name
Test status
Simulation time 210120975 ps
CPU time 0.86 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206452 kb
Host smart-752c726c-d500-42e4-9eb0-fabf115c797f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39068
23811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3906823811
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2890188108
Short name T2527
Test name
Test status
Simulation time 5242869580 ps
CPU time 137.46 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 08:00:29 PM PDT 24
Peak memory 206648 kb
Host smart-6518502f-b4f4-46d9-87d3-52d923b7a946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
88108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2890188108
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1227904612
Short name T1000
Test name
Test status
Simulation time 4593754773 ps
CPU time 44.86 seconds
Started Jul 17 07:57:53 PM PDT 24
Finished Jul 17 07:58:39 PM PDT 24
Peak memory 206516 kb
Host smart-95f53edc-95cd-450b-a366-dcae99163f41
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1227904612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1227904612
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.152053678
Short name T2504
Test name
Test status
Simulation time 181751233 ps
CPU time 0.8 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206452 kb
Host smart-8aa00b53-e1c7-454d-b26f-705a87bdb778
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=152053678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.152053678
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1860206175
Short name T604
Test name
Test status
Simulation time 141201231 ps
CPU time 0.75 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 206452 kb
Host smart-e42ccfb1-c9c2-4798-89f6-455f7497be41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18602
06175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1860206175
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.322405993
Short name T2380
Test name
Test status
Simulation time 200737467 ps
CPU time 0.84 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206452 kb
Host smart-d6feb6ee-c7f7-4778-b0c9-c51d7d30ec5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32240
5993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.322405993
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.708367287
Short name T1360
Test name
Test status
Simulation time 186515640 ps
CPU time 0.93 seconds
Started Jul 17 07:57:53 PM PDT 24
Finished Jul 17 07:57:56 PM PDT 24
Peak memory 206576 kb
Host smart-ae00f525-6b23-40f2-809b-5a7ac81d2a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70836
7287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.708367287
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.4255918961
Short name T1985
Test name
Test status
Simulation time 165901387 ps
CPU time 0.8 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206448 kb
Host smart-9e94354c-1547-4133-86bf-8ad51e4ba0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42559
18961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.4255918961
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.655205332
Short name T514
Test name
Test status
Simulation time 169104862 ps
CPU time 0.79 seconds
Started Jul 17 07:58:01 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206464 kb
Host smart-7dea98d0-3058-4c00-b20a-b225080a91ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65520
5332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.655205332
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3703127285
Short name T885
Test name
Test status
Simulation time 285199933 ps
CPU time 0.9 seconds
Started Jul 17 07:57:56 PM PDT 24
Finished Jul 17 07:57:58 PM PDT 24
Peak memory 206560 kb
Host smart-d3aa152e-dc35-4a81-82b6-31d2d80a96e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3703127285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3703127285
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3262396635
Short name T2076
Test name
Test status
Simulation time 154135353 ps
CPU time 0.78 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206460 kb
Host smart-8297c6f0-242b-42f0-8e86-71051c770d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32623
96635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3262396635
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2286048069
Short name T1674
Test name
Test status
Simulation time 48629343 ps
CPU time 0.65 seconds
Started Jul 17 07:57:56 PM PDT 24
Finished Jul 17 07:57:58 PM PDT 24
Peak memory 206524 kb
Host smart-782e59e1-e413-4ec8-a605-69d8a8b17637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22860
48069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2286048069
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3900597162
Short name T1929
Test name
Test status
Simulation time 8711559651 ps
CPU time 18.24 seconds
Started Jul 17 07:57:57 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206848 kb
Host smart-8aaa7635-e059-409d-bcb0-d50b4d444468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39005
97162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3900597162
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3294647712
Short name T1712
Test name
Test status
Simulation time 199703094 ps
CPU time 0.87 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206480 kb
Host smart-5c9f95a2-be60-4190-8590-bcd0ef31ae6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32946
47712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3294647712
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2785853967
Short name T1811
Test name
Test status
Simulation time 176962683 ps
CPU time 0.88 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206472 kb
Host smart-98f8ac64-ee60-4580-8742-a1b658629be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27858
53967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2785853967
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3068843861
Short name T2117
Test name
Test status
Simulation time 158459334 ps
CPU time 0.76 seconds
Started Jul 17 07:57:59 PM PDT 24
Finished Jul 17 07:58:02 PM PDT 24
Peak memory 206460 kb
Host smart-69989be1-6699-4ac3-bd90-dc7a0e8b45ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
43861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3068843861
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1383527777
Short name T1077
Test name
Test status
Simulation time 168435440 ps
CPU time 0.84 seconds
Started Jul 17 07:57:56 PM PDT 24
Finished Jul 17 07:57:58 PM PDT 24
Peak memory 206468 kb
Host smart-375ea944-7ab5-4165-96f3-2f575e2f1112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13835
27777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1383527777
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2765565455
Short name T1234
Test name
Test status
Simulation time 161557010 ps
CPU time 0.8 seconds
Started Jul 17 07:58:01 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206432 kb
Host smart-5b456a61-89c0-4c2b-910c-2ecffe476a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27655
65455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2765565455
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2215029511
Short name T1372
Test name
Test status
Simulation time 149827864 ps
CPU time 0.78 seconds
Started Jul 17 07:57:56 PM PDT 24
Finished Jul 17 07:57:58 PM PDT 24
Peak memory 206460 kb
Host smart-7da8856f-858e-420e-a83a-1294db2e8cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22150
29511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2215029511
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.9209310
Short name T2612
Test name
Test status
Simulation time 150381643 ps
CPU time 0.77 seconds
Started Jul 17 07:57:51 PM PDT 24
Finished Jul 17 07:57:53 PM PDT 24
Peak memory 206420 kb
Host smart-374da7da-35b3-4e02-873d-51ffcf30ae16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92093
10 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.9209310
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3461132013
Short name T1998
Test name
Test status
Simulation time 232285416 ps
CPU time 0.96 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206328 kb
Host smart-de1d7d2c-f9c0-47bf-b303-d5267601f925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
32013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3461132013
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3460407787
Short name T1300
Test name
Test status
Simulation time 6918853695 ps
CPU time 50.85 seconds
Started Jul 17 07:57:54 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206732 kb
Host smart-4c6e480c-d77f-4263-a4be-bed95e7f092a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3460407787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3460407787
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3800920919
Short name T793
Test name
Test status
Simulation time 186217241 ps
CPU time 0.89 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206440 kb
Host smart-bd545f47-ab7c-44b4-974e-33d92e9af2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
20919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3800920919
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1603904905
Short name T558
Test name
Test status
Simulation time 146567038 ps
CPU time 0.8 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206452 kb
Host smart-6c92ec59-f0dd-4088-8fcb-1e824bd29694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039
04905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1603904905
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.1316585845
Short name T537
Test name
Test status
Simulation time 1072637226 ps
CPU time 2.18 seconds
Started Jul 17 07:57:50 PM PDT 24
Finished Jul 17 07:57:54 PM PDT 24
Peak memory 206620 kb
Host smart-a863a8c3-6f1c-47dc-b951-6832c57fe80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13165
85845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.1316585845
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3627662065
Short name T1599
Test name
Test status
Simulation time 3878993410 ps
CPU time 102.3 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206664 kb
Host smart-e72df6a0-6e17-407b-94f8-31811bd35ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36276
62065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3627662065
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.887741526
Short name T560
Test name
Test status
Simulation time 39424951 ps
CPU time 0.64 seconds
Started Jul 17 07:58:02 PM PDT 24
Finished Jul 17 07:58:06 PM PDT 24
Peak memory 206420 kb
Host smart-deba032c-d779-4217-a1e4-9e1416d9965e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=887741526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.887741526
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3566004972
Short name T1033
Test name
Test status
Simulation time 4070133534 ps
CPU time 4.72 seconds
Started Jul 17 07:58:02 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206808 kb
Host smart-3ade4c04-107b-4c95-878b-71bfa948aad9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3566004972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3566004972
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1055512335
Short name T2251
Test name
Test status
Simulation time 13388534775 ps
CPU time 12.4 seconds
Started Jul 17 07:58:02 PM PDT 24
Finished Jul 17 07:58:18 PM PDT 24
Peak memory 206732 kb
Host smart-de1580aa-542e-4961-8253-2fce2cedfdd2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1055512335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1055512335
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1123777929
Short name T215
Test name
Test status
Simulation time 23462052502 ps
CPU time 23.44 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:31 PM PDT 24
Peak memory 206816 kb
Host smart-ea33f279-f17a-4f7c-ac45-d91fd7d3835b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1123777929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1123777929
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.448309084
Short name T316
Test name
Test status
Simulation time 145912448 ps
CPU time 0.81 seconds
Started Jul 17 07:58:04 PM PDT 24
Finished Jul 17 07:58:09 PM PDT 24
Peak memory 206532 kb
Host smart-638cb180-9a2b-4d40-a1db-22f8ce658084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44830
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.448309084
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2265720342
Short name T2211
Test name
Test status
Simulation time 160249472 ps
CPU time 0.84 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:03 PM PDT 24
Peak memory 206456 kb
Host smart-41de66e8-710b-42da-a146-8b34d0c5adbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22657
20342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2265720342
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.653247457
Short name T106
Test name
Test status
Simulation time 285523954 ps
CPU time 1.15 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206456 kb
Host smart-661b74c6-1707-46a3-832f-e57197f59e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65324
7457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.653247457
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1447207775
Short name T104
Test name
Test status
Simulation time 1217936054 ps
CPU time 2.7 seconds
Started Jul 17 07:57:59 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206660 kb
Host smart-71ff4935-48e8-4c10-93f8-adcff49728b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14472
07775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1447207775
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2027113878
Short name T102
Test name
Test status
Simulation time 10444358112 ps
CPU time 18.55 seconds
Started Jul 17 07:57:52 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 206844 kb
Host smart-0d675e1f-662f-41a9-aff3-67defa18636a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20271
13878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2027113878
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.1839888024
Short name T2385
Test name
Test status
Simulation time 373734231 ps
CPU time 1.23 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206456 kb
Host smart-364b6a4c-465e-4a56-957d-f92d6f7c55d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18398
88024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.1839888024
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3649884469
Short name T740
Test name
Test status
Simulation time 154307023 ps
CPU time 0.74 seconds
Started Jul 17 07:58:04 PM PDT 24
Finished Jul 17 07:58:09 PM PDT 24
Peak memory 206456 kb
Host smart-e711bb34-17b6-4471-a834-a660e938c195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36498
84469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3649884469
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.3326761908
Short name T578
Test name
Test status
Simulation time 33103264 ps
CPU time 0.64 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206444 kb
Host smart-b4df947a-fe9d-4f95-8534-3b27ec0bba50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33267
61908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3326761908
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.3399209853
Short name T2234
Test name
Test status
Simulation time 913272426 ps
CPU time 2.14 seconds
Started Jul 17 07:58:04 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206660 kb
Host smart-a7b1b549-a23e-49e0-9b7b-8ea2d9c86613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33992
09853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3399209853
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1719302847
Short name T2035
Test name
Test status
Simulation time 207914923 ps
CPU time 1.43 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 206648 kb
Host smart-2bb81f12-41c1-4ffe-9244-5779c50f9edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17193
02847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1719302847
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.38590390
Short name T1381
Test name
Test status
Simulation time 228847496 ps
CPU time 0.9 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206412 kb
Host smart-06aa7347-c9e7-4f3d-b0e4-e91963543263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38590
390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.38590390
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3461202061
Short name T1109
Test name
Test status
Simulation time 156711243 ps
CPU time 0.78 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:13 PM PDT 24
Peak memory 206456 kb
Host smart-8c548f6e-df01-4c0e-8f84-38d0c09f6ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34612
02061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3461202061
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2138686106
Short name T463
Test name
Test status
Simulation time 213027075 ps
CPU time 0.84 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:13 PM PDT 24
Peak memory 206276 kb
Host smart-bdbbebe4-113a-45c2-b66b-46e0fe8e10ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21386
86106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2138686106
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.3665236470
Short name T2038
Test name
Test status
Simulation time 6521386570 ps
CPU time 57.98 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206676 kb
Host smart-40fe1762-46cc-4c1d-8476-b5ca34896f08
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3665236470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3665236470
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.2887092214
Short name T2713
Test name
Test status
Simulation time 5892241590 ps
CPU time 55.25 seconds
Started Jul 17 07:57:53 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206548 kb
Host smart-f2c11a49-e513-405c-a2bd-0864ca503e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
92214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.2887092214
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.512507824
Short name T2085
Test name
Test status
Simulation time 236533270 ps
CPU time 0.91 seconds
Started Jul 17 07:57:53 PM PDT 24
Finished Jul 17 07:57:55 PM PDT 24
Peak memory 206444 kb
Host smart-7c76b54c-c2cf-4dad-ad12-fd15dc6fbe14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51250
7824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.512507824
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.653784740
Short name T2514
Test name
Test status
Simulation time 23303493840 ps
CPU time 25.53 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:38 PM PDT 24
Peak memory 206508 kb
Host smart-880f2db2-f4f1-4d91-9cac-56f03f5fbf85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65378
4740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.653784740
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3553702
Short name T2407
Test name
Test status
Simulation time 3318400968 ps
CPU time 4.12 seconds
Started Jul 17 07:57:57 PM PDT 24
Finished Jul 17 07:58:03 PM PDT 24
Peak memory 206604 kb
Host smart-cf4bc919-e8d4-450c-886a-08255aa240e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35537
02 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3553702
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1000521999
Short name T843
Test name
Test status
Simulation time 9846952007 ps
CPU time 93.59 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:59:44 PM PDT 24
Peak memory 206728 kb
Host smart-ead159c2-175a-4185-98a1-e493b217c394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005
21999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1000521999
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2703230980
Short name T420
Test name
Test status
Simulation time 3721079594 ps
CPU time 102.87 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206648 kb
Host smart-35b6f66b-7fb8-493b-93e2-6041afc477d5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2703230980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2703230980
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3176143914
Short name T390
Test name
Test status
Simulation time 300850197 ps
CPU time 0.96 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 206448 kb
Host smart-f49be5a6-c079-4eac-93b8-4d3f0b3a4d25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3176143914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3176143914
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.411604366
Short name T2344
Test name
Test status
Simulation time 231939265 ps
CPU time 0.88 seconds
Started Jul 17 07:58:04 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206456 kb
Host smart-ec14a52d-9b62-48d7-8aab-62676b36922b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41160
4366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.411604366
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3089219559
Short name T2456
Test name
Test status
Simulation time 4018677641 ps
CPU time 37.53 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206524 kb
Host smart-6750161a-f0f8-4038-9ce5-fcc30cf3b044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892
19559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3089219559
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1787804550
Short name T479
Test name
Test status
Simulation time 2910394150 ps
CPU time 27.13 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:36 PM PDT 24
Peak memory 206648 kb
Host smart-0c1427ac-45e9-4f6e-a325-c91f7c5f6e1d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1787804550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1787804550
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.93894014
Short name T944
Test name
Test status
Simulation time 158692066 ps
CPU time 0.8 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206404 kb
Host smart-9ed281f2-dec1-4045-933a-24191929ad14
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=93894014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.93894014
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1133405413
Short name T936
Test name
Test status
Simulation time 161440971 ps
CPU time 0.77 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206480 kb
Host smart-ace7df53-312f-4bf8-ad89-8822b6bbdcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11334
05413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1133405413
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.337998905
Short name T2221
Test name
Test status
Simulation time 178143666 ps
CPU time 0.84 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206460 kb
Host smart-e5df371b-9fc4-4b21-ab8f-f457af0b571c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33799
8905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.337998905
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2058810860
Short name T981
Test name
Test status
Simulation time 183464718 ps
CPU time 0.81 seconds
Started Jul 17 07:58:01 PM PDT 24
Finished Jul 17 07:58:05 PM PDT 24
Peak memory 206464 kb
Host smart-58a6767c-c655-4855-afc1-4031365116b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20588
10860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2058810860
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.761231643
Short name T336
Test name
Test status
Simulation time 167754696 ps
CPU time 0.82 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206428 kb
Host smart-fd8bb080-191e-4cf1-9d03-7b6c1c459438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76123
1643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.761231643
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3046899962
Short name T2481
Test name
Test status
Simulation time 151817578 ps
CPU time 0.76 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:03 PM PDT 24
Peak memory 206464 kb
Host smart-0d6f3735-1a5d-4b68-8f1b-2e8ad961f80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30468
99962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3046899962
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.2316469918
Short name T393
Test name
Test status
Simulation time 207936847 ps
CPU time 0.93 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206460 kb
Host smart-7cdb0b3f-9092-435e-bbdf-8f5c555285ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2316469918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.2316469918
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3765165870
Short name T2721
Test name
Test status
Simulation time 173341784 ps
CPU time 0.81 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206460 kb
Host smart-135689b2-8879-4802-abda-a1b18ea03674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37651
65870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3765165870
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.223253702
Short name T27
Test name
Test status
Simulation time 64809313 ps
CPU time 0.67 seconds
Started Jul 17 07:57:55 PM PDT 24
Finished Jul 17 07:57:57 PM PDT 24
Peak memory 206428 kb
Host smart-bca7ca82-a3c3-4513-89be-e1deed3b4504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22325
3702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.223253702
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2335071027
Short name T630
Test name
Test status
Simulation time 5911187907 ps
CPU time 13.79 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:24 PM PDT 24
Peak memory 206752 kb
Host smart-e1f408a3-8a4d-4576-8e55-9f3d0bc98798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23350
71027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2335071027
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3835024820
Short name T1915
Test name
Test status
Simulation time 207379721 ps
CPU time 0.83 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206420 kb
Host smart-cc3978f5-b988-4200-84c8-cd368be83bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38350
24820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3835024820
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3320377017
Short name T2267
Test name
Test status
Simulation time 162345802 ps
CPU time 0.8 seconds
Started Jul 17 07:58:04 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206440 kb
Host smart-c0133ad2-79e1-41e8-afc6-7d4fbed10e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33203
77017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3320377017
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.1200066216
Short name T1007
Test name
Test status
Simulation time 183553488 ps
CPU time 0.85 seconds
Started Jul 17 07:58:01 PM PDT 24
Finished Jul 17 07:58:04 PM PDT 24
Peak memory 206316 kb
Host smart-7282b69b-01eb-4154-a8e1-ff8b6d80c7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12000
66216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.1200066216
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1582445245
Short name T1290
Test name
Test status
Simulation time 174326088 ps
CPU time 0.87 seconds
Started Jul 17 07:57:51 PM PDT 24
Finished Jul 17 07:57:54 PM PDT 24
Peak memory 206420 kb
Host smart-ff0566b1-86c2-47b5-b0e3-8806e61a21c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15824
45245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1582445245
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.669838989
Short name T806
Test name
Test status
Simulation time 161488214 ps
CPU time 0.77 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206436 kb
Host smart-91217542-e8f7-4c13-85a4-84bba14fa9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66983
8989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.669838989
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2831850445
Short name T1752
Test name
Test status
Simulation time 158361022 ps
CPU time 0.82 seconds
Started Jul 17 07:57:54 PM PDT 24
Finished Jul 17 07:57:56 PM PDT 24
Peak memory 206456 kb
Host smart-92289618-f7bf-4420-bdab-13dd7e3c18b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318
50445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2831850445
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3742567216
Short name T2003
Test name
Test status
Simulation time 152253943 ps
CPU time 0.79 seconds
Started Jul 17 07:57:54 PM PDT 24
Finished Jul 17 07:57:56 PM PDT 24
Peak memory 206468 kb
Host smart-bdd15b36-bd58-4174-b9fc-83b490944a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37425
67216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3742567216
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3206070110
Short name T383
Test name
Test status
Simulation time 275581105 ps
CPU time 0.91 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206456 kb
Host smart-c0a22313-91aa-4069-aa7a-77356945ccb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32060
70110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3206070110
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1015786
Short name T1257
Test name
Test status
Simulation time 5419676238 ps
CPU time 150.27 seconds
Started Jul 17 07:57:58 PM PDT 24
Finished Jul 17 08:00:30 PM PDT 24
Peak memory 206624 kb
Host smart-a880ac9e-1e13-4832-a55c-3b5ad985a551
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1015786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1015786
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.4220690790
Short name T2449
Test name
Test status
Simulation time 182324348 ps
CPU time 0.8 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:07 PM PDT 24
Peak memory 206544 kb
Host smart-2d5dc059-8a36-4292-9bc7-b62e84af7236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42206
90790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.4220690790
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.362786773
Short name T1258
Test name
Test status
Simulation time 143788514 ps
CPU time 0.82 seconds
Started Jul 17 07:57:58 PM PDT 24
Finished Jul 17 07:58:00 PM PDT 24
Peak memory 206392 kb
Host smart-82167a2a-4250-4a59-a11c-53cb1b1ac820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36278
6773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.362786773
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.699859891
Short name T1430
Test name
Test status
Simulation time 1361884163 ps
CPU time 2.96 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:10 PM PDT 24
Peak memory 206716 kb
Host smart-865c2d37-7a07-420a-bd75-743ca15d9185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69985
9891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.699859891
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1585590475
Short name T2284
Test name
Test status
Simulation time 5313643127 ps
CPU time 145.46 seconds
Started Jul 17 07:58:02 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206748 kb
Host smart-1e0e5c69-e689-439d-a657-0d8241e37867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15855
90475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1585590475
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2200577320
Short name T1659
Test name
Test status
Simulation time 64921984 ps
CPU time 0.75 seconds
Started Jul 17 07:58:09 PM PDT 24
Finished Jul 17 07:58:14 PM PDT 24
Peak memory 206608 kb
Host smart-8484a571-a1d4-46c3-b319-6372a3dd6aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2200577320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2200577320
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.293443143
Short name T859
Test name
Test status
Simulation time 4357947619 ps
CPU time 5.25 seconds
Started Jul 17 07:58:00 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206728 kb
Host smart-70356236-49b6-4a06-aeb7-82abb9d2478e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=293443143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.293443143
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3348874707
Short name T1702
Test name
Test status
Simulation time 13417681861 ps
CPU time 16.83 seconds
Started Jul 17 07:57:53 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206524 kb
Host smart-f6340f4c-8fc4-4000-96b1-12536f51ab03
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3348874707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3348874707
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2029899772
Short name T2298
Test name
Test status
Simulation time 23390128269 ps
CPU time 24.32 seconds
Started Jul 17 07:57:50 PM PDT 24
Finished Jul 17 07:58:15 PM PDT 24
Peak memory 206540 kb
Host smart-cf5ee049-1886-4f90-8bc9-3e94b59abf47
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2029899772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2029899772
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3499044257
Short name T1463
Test name
Test status
Simulation time 227194361 ps
CPU time 0.92 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206408 kb
Host smart-8a2942cd-5f36-41dc-89b9-24609ff44cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
44257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3499044257
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.622310045
Short name T2335
Test name
Test status
Simulation time 140651936 ps
CPU time 0.78 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206448 kb
Host smart-fc7a3323-bf1e-40f7-bf2a-38cdf613a6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62231
0045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.622310045
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.781862638
Short name T1904
Test name
Test status
Simulation time 257306956 ps
CPU time 1 seconds
Started Jul 17 07:58:03 PM PDT 24
Finished Jul 17 07:58:08 PM PDT 24
Peak memory 206456 kb
Host smart-9bddde4c-142e-4a91-a6f8-f20a0a51b333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78186
2638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.781862638
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1489730305
Short name T1840
Test name
Test status
Simulation time 358789322 ps
CPU time 1.11 seconds
Started Jul 17 07:58:05 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 206460 kb
Host smart-68c5b108-52ab-4ef2-ad55-8334fd328647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14897
30305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1489730305
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.4067111701
Short name T1096
Test name
Test status
Simulation time 15749301548 ps
CPU time 27.11 seconds
Started Jul 17 07:58:06 PM PDT 24
Finished Jul 17 07:58:38 PM PDT 24
Peak memory 206648 kb
Host smart-9ed3121f-9d3c-46b8-bd0a-f6f1d20ed7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40671
11701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.4067111701
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2969720786
Short name T1595
Test name
Test status
Simulation time 462115441 ps
CPU time 1.3 seconds
Started Jul 17 07:58:11 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206108 kb
Host smart-fc9ed09e-4d6f-4cc9-8576-a8b5271313b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29697
20786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2969720786
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3581219699
Short name T432
Test name
Test status
Simulation time 160376219 ps
CPU time 0.82 seconds
Started Jul 17 07:58:12 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206464 kb
Host smart-66753264-f2ef-4775-9f8f-65b080c7a16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35812
19699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3581219699
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3143350138
Short name T907
Test name
Test status
Simulation time 87061950 ps
CPU time 0.72 seconds
Started Jul 17 07:58:17 PM PDT 24
Finished Jul 17 07:58:21 PM PDT 24
Peak memory 206444 kb
Host smart-cd053907-410a-4f41-b9af-016852a17a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
50138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3143350138
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.42768952
Short name T1709
Test name
Test status
Simulation time 867097488 ps
CPU time 2.08 seconds
Started Jul 17 07:58:09 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206592 kb
Host smart-b954de7a-3cb0-4e86-9a14-35a8de5fee33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42768
952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.42768952
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.517864745
Short name T2548
Test name
Test status
Simulation time 258636917 ps
CPU time 1.88 seconds
Started Jul 17 07:58:11 PM PDT 24
Finished Jul 17 07:58:17 PM PDT 24
Peak memory 206544 kb
Host smart-2baed76a-570b-4049-80b5-7bbc51f09cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51786
4745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.517864745
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1797274679
Short name T1728
Test name
Test status
Simulation time 203824688 ps
CPU time 0.85 seconds
Started Jul 17 07:58:08 PM PDT 24
Finished Jul 17 07:58:14 PM PDT 24
Peak memory 206452 kb
Host smart-b81b913f-0017-4294-a636-07042068df82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17972
74679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1797274679
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2032111661
Short name T1379
Test name
Test status
Simulation time 194297952 ps
CPU time 0.8 seconds
Started Jul 17 07:58:09 PM PDT 24
Finished Jul 17 07:58:14 PM PDT 24
Peak memory 206444 kb
Host smart-b8378dd5-72f5-4204-b845-6eaaa82e27bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
11661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2032111661
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1198942239
Short name T890
Test name
Test status
Simulation time 175365280 ps
CPU time 0.84 seconds
Started Jul 17 07:58:13 PM PDT 24
Finished Jul 17 07:58:18 PM PDT 24
Peak memory 206464 kb
Host smart-68af0cb0-e386-40bd-a40e-feeffdf3062a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11989
42239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1198942239
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2980668661
Short name T493
Test name
Test status
Simulation time 6531986332 ps
CPU time 173.85 seconds
Started Jul 17 07:58:08 PM PDT 24
Finished Jul 17 08:01:07 PM PDT 24
Peak memory 206648 kb
Host smart-d90a3c98-a29f-4085-a24b-f69624f0354a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2980668661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2980668661
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1677280898
Short name T1784
Test name
Test status
Simulation time 211431506 ps
CPU time 0.9 seconds
Started Jul 17 07:58:10 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206444 kb
Host smart-69ae0c21-c038-4aad-a754-ea01d0f64af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16772
80898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1677280898
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3145530932
Short name T2223
Test name
Test status
Simulation time 23304721288 ps
CPU time 25.57 seconds
Started Jul 17 07:58:07 PM PDT 24
Finished Jul 17 07:58:38 PM PDT 24
Peak memory 206512 kb
Host smart-09ddf542-3129-4f57-a57a-2bb1df33635a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31455
30932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3145530932
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1341014413
Short name T1371
Test name
Test status
Simulation time 3356036500 ps
CPU time 3.61 seconds
Started Jul 17 07:58:11 PM PDT 24
Finished Jul 17 07:58:19 PM PDT 24
Peak memory 206516 kb
Host smart-896e81c9-50e3-4fa2-967e-c1f9b12fd0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13410
14413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1341014413
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3986643746
Short name T218
Test name
Test status
Simulation time 10199684332 ps
CPU time 93.54 seconds
Started Jul 17 07:58:10 PM PDT 24
Finished Jul 17 07:59:49 PM PDT 24
Peak memory 206748 kb
Host smart-8a7dd94c-41dc-48d6-bdfb-f84f4b0fa2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39866
43746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3986643746
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3571452215
Short name T2614
Test name
Test status
Simulation time 3197995256 ps
CPU time 21.99 seconds
Started Jul 17 07:58:09 PM PDT 24
Finished Jul 17 07:58:36 PM PDT 24
Peak memory 206712 kb
Host smart-aae1ff8d-9624-40fb-8689-7565777da91b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3571452215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3571452215
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3024020477
Short name T2404
Test name
Test status
Simulation time 240360666 ps
CPU time 0.92 seconds
Started Jul 17 07:58:10 PM PDT 24
Finished Jul 17 07:58:15 PM PDT 24
Peak memory 206432 kb
Host smart-04dedc09-46e2-4ca2-b15b-e31c8a924675
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3024020477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3024020477
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.869059222
Short name T1934
Test name
Test status
Simulation time 202451849 ps
CPU time 0.85 seconds
Started Jul 17 07:58:11 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206216 kb
Host smart-0a1af186-1efd-4190-aafb-e2db2705bef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86905
9222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.869059222
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.419458390
Short name T744
Test name
Test status
Simulation time 5367608406 ps
CPU time 50.19 seconds
Started Jul 17 07:58:11 PM PDT 24
Finished Jul 17 07:59:05 PM PDT 24
Peak memory 206624 kb
Host smart-d6654172-ce55-493d-a5c7-d66198e7d353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41945
8390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.419458390
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2596601128
Short name T1684
Test name
Test status
Simulation time 5588708884 ps
CPU time 52.33 seconds
Started Jul 17 07:58:13 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206728 kb
Host smart-2bb21490-ff11-4c5a-a7e1-b949fa2378ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2596601128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2596601128
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3727916030
Short name T233
Test name
Test status
Simulation time 190521616 ps
CPU time 0.82 seconds
Started Jul 17 07:58:11 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206440 kb
Host smart-8e20b193-865c-4ce7-8956-9409eca55ca6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3727916030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3727916030
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3948361583
Short name T2006
Test name
Test status
Simulation time 142304196 ps
CPU time 0.8 seconds
Started Jul 17 07:58:13 PM PDT 24
Finished Jul 17 07:58:18 PM PDT 24
Peak memory 206464 kb
Host smart-55da1a3d-2c4c-4cf9-9e5d-76651e82dc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483
61583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3948361583
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.758942948
Short name T129
Test name
Test status
Simulation time 192540384 ps
CPU time 0.86 seconds
Started Jul 17 07:58:11 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206436 kb
Host smart-b8b32df1-b5d7-495f-91bc-2930eae2b237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75894
2948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.758942948
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.241065181
Short name T2224
Test name
Test status
Simulation time 174894093 ps
CPU time 0.8 seconds
Started Jul 17 07:58:09 PM PDT 24
Finished Jul 17 07:58:14 PM PDT 24
Peak memory 206452 kb
Host smart-4289c718-d1c4-45e8-926c-a5fef4ef85b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24106
5181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.241065181
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.970957474
Short name T494
Test name
Test status
Simulation time 205849533 ps
CPU time 0.82 seconds
Started Jul 17 07:58:10 PM PDT 24
Finished Jul 17 07:58:15 PM PDT 24
Peak memory 206424 kb
Host smart-b9071e9b-821d-42f6-8538-26c942c3c0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97095
7474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.970957474
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1621459783
Short name T382
Test name
Test status
Simulation time 176693607 ps
CPU time 0.82 seconds
Started Jul 17 07:58:16 PM PDT 24
Finished Jul 17 07:58:21 PM PDT 24
Peak memory 206436 kb
Host smart-e84027cb-f70d-4137-b9f1-f10e6ed0ce23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16214
59783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1621459783
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2779460081
Short name T1841
Test name
Test status
Simulation time 174254798 ps
CPU time 0.82 seconds
Started Jul 17 07:58:18 PM PDT 24
Finished Jul 17 07:58:22 PM PDT 24
Peak memory 206456 kb
Host smart-a9d25e83-cf05-46d8-a0cb-7a7ee1101693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27794
60081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2779460081
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2048696463
Short name T1844
Test name
Test status
Simulation time 256628845 ps
CPU time 0.99 seconds
Started Jul 17 07:58:18 PM PDT 24
Finished Jul 17 07:58:22 PM PDT 24
Peak memory 206456 kb
Host smart-8f3bb45b-3797-4702-9de9-1e9228eb2f3a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2048696463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2048696463
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1593805552
Short name T1219
Test name
Test status
Simulation time 155525987 ps
CPU time 0.77 seconds
Started Jul 17 07:58:09 PM PDT 24
Finished Jul 17 07:58:15 PM PDT 24
Peak memory 206456 kb
Host smart-7fbcad28-d506-4540-8cef-7892d881f9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15938
05552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1593805552
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3392264411
Short name T2058
Test name
Test status
Simulation time 70061834 ps
CPU time 0.74 seconds
Started Jul 17 07:58:10 PM PDT 24
Finished Jul 17 07:58:15 PM PDT 24
Peak memory 206440 kb
Host smart-00a69363-5ec2-4146-8bac-a4cec8142fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33922
64411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3392264411
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1094607077
Short name T2048
Test name
Test status
Simulation time 13604655705 ps
CPU time 32.97 seconds
Started Jul 17 07:58:12 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206752 kb
Host smart-490c9887-b447-4b64-96ac-07766aa0d5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10946
07077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1094607077
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3937634938
Short name T1935
Test name
Test status
Simulation time 146228559 ps
CPU time 0.79 seconds
Started Jul 17 07:58:11 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206420 kb
Host smart-2afa586e-995b-4d57-8b60-37416f3afd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39376
34938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3937634938
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1104370606
Short name T1676
Test name
Test status
Simulation time 263728169 ps
CPU time 0.9 seconds
Started Jul 17 07:58:17 PM PDT 24
Finished Jul 17 07:58:22 PM PDT 24
Peak memory 206448 kb
Host smart-24101f66-83f4-4d26-b52f-98afd3b2bad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11043
70606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1104370606
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2475898673
Short name T1481
Test name
Test status
Simulation time 222367812 ps
CPU time 0.94 seconds
Started Jul 17 07:58:10 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206436 kb
Host smart-ba1e352c-ce2a-4ab9-a1ed-acd4b1f7fadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24758
98673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2475898673
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3629939347
Short name T2417
Test name
Test status
Simulation time 206373823 ps
CPU time 0.87 seconds
Started Jul 17 07:58:12 PM PDT 24
Finished Jul 17 07:58:17 PM PDT 24
Peak memory 206448 kb
Host smart-6a3c7ab4-5dfc-47a0-af5f-8ff2db06b46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36299
39347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3629939347
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1659599587
Short name T756
Test name
Test status
Simulation time 190443643 ps
CPU time 0.81 seconds
Started Jul 17 07:58:20 PM PDT 24
Finished Jul 17 07:58:23 PM PDT 24
Peak memory 206280 kb
Host smart-0443cd95-af4f-4498-a69d-cc8ea88064cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16595
99587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1659599587
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1386023746
Short name T351
Test name
Test status
Simulation time 160713328 ps
CPU time 0.81 seconds
Started Jul 17 07:58:16 PM PDT 24
Finished Jul 17 07:58:21 PM PDT 24
Peak memory 206456 kb
Host smart-6c45f9c4-d4e4-41ae-9985-20fc070aa7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
23746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1386023746
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.636160355
Short name T888
Test name
Test status
Simulation time 150527713 ps
CPU time 0.79 seconds
Started Jul 17 07:58:09 PM PDT 24
Finished Jul 17 07:58:15 PM PDT 24
Peak memory 206624 kb
Host smart-cd1daec7-52fa-4e68-bdcd-eb233a0ce3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63616
0355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.636160355
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2777186511
Short name T1831
Test name
Test status
Simulation time 222904556 ps
CPU time 0.89 seconds
Started Jul 17 07:58:12 PM PDT 24
Finished Jul 17 07:58:17 PM PDT 24
Peak memory 206452 kb
Host smart-36c49559-3c21-4c75-b1fc-08e15dbe6f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27771
86511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2777186511
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.52825149
Short name T615
Test name
Test status
Simulation time 5124635731 ps
CPU time 48.05 seconds
Started Jul 17 07:58:13 PM PDT 24
Finished Jul 17 07:59:05 PM PDT 24
Peak memory 206728 kb
Host smart-1bf36df7-5481-4652-ac6b-9e1eda869ace
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=52825149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.52825149
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3621287103
Short name T396
Test name
Test status
Simulation time 219215045 ps
CPU time 0.9 seconds
Started Jul 17 07:58:12 PM PDT 24
Finished Jul 17 07:58:17 PM PDT 24
Peak memory 206444 kb
Host smart-747c8d7e-2b63-4182-af7f-7cf461d9f641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212
87103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3621287103
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.565094542
Short name T2397
Test name
Test status
Simulation time 151718411 ps
CPU time 0.76 seconds
Started Jul 17 07:58:10 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 206436 kb
Host smart-a30d05bd-dd3e-42e3-b7af-d598448d6054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56509
4542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.565094542
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.2835389228
Short name T550
Test name
Test status
Simulation time 372015092 ps
CPU time 1.27 seconds
Started Jul 17 07:58:18 PM PDT 24
Finished Jul 17 07:58:23 PM PDT 24
Peak memory 206448 kb
Host smart-605aa789-3c34-4ad0-b351-dd1c3fc141c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28353
89228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2835389228
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.471500918
Short name T2424
Test name
Test status
Simulation time 5308405868 ps
CPU time 47.38 seconds
Started Jul 17 07:58:16 PM PDT 24
Finished Jul 17 07:59:08 PM PDT 24
Peak memory 206712 kb
Host smart-cbd34668-b171-4f6f-a891-b5430d9e3621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47150
0918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.471500918
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.1307854898
Short name T178
Test name
Test status
Simulation time 40502184 ps
CPU time 0.66 seconds
Started Jul 17 07:58:31 PM PDT 24
Finished Jul 17 07:58:33 PM PDT 24
Peak memory 206436 kb
Host smart-704fd3f9-c6e3-49fe-86dd-b4f041fe5de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1307854898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.1307854898
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.386252231
Short name T586
Test name
Test status
Simulation time 4335114361 ps
CPU time 5.94 seconds
Started Jul 17 07:58:12 PM PDT 24
Finished Jul 17 07:58:22 PM PDT 24
Peak memory 206484 kb
Host smart-5185dd66-fae8-4096-bd21-ee18147d1371
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=386252231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.386252231
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3586530044
Short name T2652
Test name
Test status
Simulation time 13400093742 ps
CPU time 13.54 seconds
Started Jul 17 07:58:18 PM PDT 24
Finished Jul 17 07:58:35 PM PDT 24
Peak memory 206492 kb
Host smart-439d370c-25a9-4656-850b-2eaa348f1890
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3586530044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3586530044
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1367249035
Short name T2641
Test name
Test status
Simulation time 23420513861 ps
CPU time 23.22 seconds
Started Jul 17 07:58:20 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206292 kb
Host smart-df35fc55-c235-4e7a-b605-7740b0372931
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1367249035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.1367249035
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3777712334
Short name T2374
Test name
Test status
Simulation time 198878795 ps
CPU time 0.88 seconds
Started Jul 17 07:58:15 PM PDT 24
Finished Jul 17 07:58:19 PM PDT 24
Peak memory 206444 kb
Host smart-2edf62f1-2adc-4e72-b5c8-b1afeb6c12ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
12334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3777712334
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2245217023
Short name T882
Test name
Test status
Simulation time 148912450 ps
CPU time 0.84 seconds
Started Jul 17 07:58:15 PM PDT 24
Finished Jul 17 07:58:19 PM PDT 24
Peak memory 206460 kb
Host smart-152bf104-3150-4f8b-b1f3-c3da4cfb1013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22452
17023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2245217023
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3432966352
Short name T1144
Test name
Test status
Simulation time 175245725 ps
CPU time 0.83 seconds
Started Jul 17 07:58:14 PM PDT 24
Finished Jul 17 07:58:18 PM PDT 24
Peak memory 206456 kb
Host smart-7e74641d-5b1b-4d47-936e-2cdd91e4129e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34329
66352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3432966352
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1457494656
Short name T60
Test name
Test status
Simulation time 1332339699 ps
CPU time 2.77 seconds
Started Jul 17 07:58:20 PM PDT 24
Finished Jul 17 07:58:25 PM PDT 24
Peak memory 206628 kb
Host smart-090f5b51-9e00-4d9b-ab5b-8a313c15f066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14574
94656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1457494656
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.272114238
Short name T2437
Test name
Test status
Simulation time 17948142465 ps
CPU time 34.76 seconds
Started Jul 17 07:58:14 PM PDT 24
Finished Jul 17 07:58:52 PM PDT 24
Peak memory 206720 kb
Host smart-0fb50152-89ef-4dfd-9cea-fceb4faad915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27211
4238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.272114238
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1171196483
Short name T1322
Test name
Test status
Simulation time 390906828 ps
CPU time 1.31 seconds
Started Jul 17 07:58:15 PM PDT 24
Finished Jul 17 07:58:19 PM PDT 24
Peak memory 206460 kb
Host smart-c6a19cfd-94a8-43b0-9930-f132e9d5a9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711
96483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1171196483
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2095869773
Short name T346
Test name
Test status
Simulation time 134594357 ps
CPU time 0.74 seconds
Started Jul 17 07:58:16 PM PDT 24
Finished Jul 17 07:58:20 PM PDT 24
Peak memory 206468 kb
Host smart-91b82b98-0997-4063-af7a-523c14a99c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20958
69773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2095869773
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3477540374
Short name T2007
Test name
Test status
Simulation time 57322961 ps
CPU time 0.69 seconds
Started Jul 17 07:58:14 PM PDT 24
Finished Jul 17 07:58:18 PM PDT 24
Peak memory 206452 kb
Host smart-c4fe088f-8c10-480e-af06-0db453782017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34775
40374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3477540374
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.1752549755
Short name T2742
Test name
Test status
Simulation time 903347170 ps
CPU time 2.17 seconds
Started Jul 17 07:58:15 PM PDT 24
Finished Jul 17 07:58:20 PM PDT 24
Peak memory 206620 kb
Host smart-b09c6024-b2dc-4c3c-97cc-e5b40e70d325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17525
49755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.1752549755
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3838704187
Short name T2379
Test name
Test status
Simulation time 234235092 ps
CPU time 1.27 seconds
Started Jul 17 07:58:16 PM PDT 24
Finished Jul 17 07:58:21 PM PDT 24
Peak memory 206664 kb
Host smart-40ea60ea-644a-49b0-9f35-f882bafdb4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38387
04187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3838704187
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2966549407
Short name T1926
Test name
Test status
Simulation time 171486674 ps
CPU time 0.83 seconds
Started Jul 17 07:58:18 PM PDT 24
Finished Jul 17 07:58:22 PM PDT 24
Peak memory 206456 kb
Host smart-805c9426-ef3c-452d-b548-4a5182f33021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29665
49407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2966549407
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1909603345
Short name T2287
Test name
Test status
Simulation time 146895281 ps
CPU time 0.83 seconds
Started Jul 17 07:58:18 PM PDT 24
Finished Jul 17 07:58:22 PM PDT 24
Peak memory 206456 kb
Host smart-02cdc13e-ae11-4aef-98d6-66b3faec5b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19096
03345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1909603345
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.814850529
Short name T357
Test name
Test status
Simulation time 192495631 ps
CPU time 0.88 seconds
Started Jul 17 07:58:15 PM PDT 24
Finished Jul 17 07:58:19 PM PDT 24
Peak memory 206456 kb
Host smart-b9604930-a9ca-408b-8867-e4e099608313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81485
0529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.814850529
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.3177411123
Short name T219
Test name
Test status
Simulation time 8045548452 ps
CPU time 71.63 seconds
Started Jul 17 07:58:15 PM PDT 24
Finished Jul 17 07:59:30 PM PDT 24
Peak memory 206736 kb
Host smart-ad429e85-9b17-4b35-8438-94ef306f1cd5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3177411123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3177411123
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.766717496
Short name T1698
Test name
Test status
Simulation time 237970203 ps
CPU time 0.9 seconds
Started Jul 17 07:58:35 PM PDT 24
Finished Jul 17 07:58:39 PM PDT 24
Peak memory 206440 kb
Host smart-34f7c4af-c119-4a65-b813-7d42d4c3fee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76671
7496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.766717496
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3514678353
Short name T671
Test name
Test status
Simulation time 23327172894 ps
CPU time 22.67 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:59:05 PM PDT 24
Peak memory 206500 kb
Host smart-10db02a7-cdae-485d-862b-2bdbb4b55944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35146
78353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3514678353
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1250932638
Short name T1145
Test name
Test status
Simulation time 3274543609 ps
CPU time 3.51 seconds
Started Jul 17 07:58:31 PM PDT 24
Finished Jul 17 07:58:36 PM PDT 24
Peak memory 206512 kb
Host smart-2303a06b-7ff9-4419-a855-defff3343863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12509
32638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1250932638
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.430626002
Short name T706
Test name
Test status
Simulation time 10133121829 ps
CPU time 291.67 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 08:03:40 PM PDT 24
Peak memory 206768 kb
Host smart-14665f6e-d2df-42a8-96b2-d479436fde01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43062
6002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.430626002
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1395468417
Short name T1996
Test name
Test status
Simulation time 4085633188 ps
CPU time 113.53 seconds
Started Jul 17 07:58:29 PM PDT 24
Finished Jul 17 08:00:23 PM PDT 24
Peak memory 206656 kb
Host smart-e8e77793-082e-4c4f-9aa9-1cb5e6d5ddc8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1395468417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1395468417
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1563134038
Short name T2225
Test name
Test status
Simulation time 254136867 ps
CPU time 0.98 seconds
Started Jul 17 07:58:32 PM PDT 24
Finished Jul 17 07:58:34 PM PDT 24
Peak memory 206444 kb
Host smart-a47c6b7c-c20a-4204-bf39-60cd83e6c361
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1563134038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1563134038
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.304795059
Short name T1201
Test name
Test status
Simulation time 229055196 ps
CPU time 0.87 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:42 PM PDT 24
Peak memory 206460 kb
Host smart-3990d320-e1a3-45fb-93a9-dc19f46ac875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30479
5059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.304795059
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.535347510
Short name T499
Test name
Test status
Simulation time 4960467207 ps
CPU time 130.7 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 08:00:58 PM PDT 24
Peak memory 206652 kb
Host smart-9df81810-25f1-4c9e-a630-ff0ff5323a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53534
7510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.535347510
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1350342511
Short name T942
Test name
Test status
Simulation time 5281343568 ps
CPU time 150 seconds
Started Jul 17 07:58:32 PM PDT 24
Finished Jul 17 08:01:03 PM PDT 24
Peak memory 206684 kb
Host smart-8ee454e7-591d-4a19-8cec-57b0e380c6c3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1350342511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1350342511
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3333730780
Short name T411
Test name
Test status
Simulation time 157285407 ps
CPU time 0.77 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:37 PM PDT 24
Peak memory 206464 kb
Host smart-05b394fe-f68a-43fc-a354-241f5da224d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3333730780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3333730780
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3658556288
Short name T2413
Test name
Test status
Simulation time 144694003 ps
CPU time 0.79 seconds
Started Jul 17 07:58:32 PM PDT 24
Finished Jul 17 07:58:34 PM PDT 24
Peak memory 206468 kb
Host smart-fc6ff191-25f0-412a-bae0-44435b5ce904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36585
56288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3658556288
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1696852392
Short name T2115
Test name
Test status
Simulation time 252785486 ps
CPU time 0.89 seconds
Started Jul 17 07:58:31 PM PDT 24
Finished Jul 17 07:58:33 PM PDT 24
Peak memory 206464 kb
Host smart-3d350761-73ea-4da4-a8d1-75b2aa5613fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16968
52392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1696852392
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2657463216
Short name T2751
Test name
Test status
Simulation time 182595663 ps
CPU time 0.84 seconds
Started Jul 17 07:58:33 PM PDT 24
Finished Jul 17 07:58:35 PM PDT 24
Peak memory 206444 kb
Host smart-92bb39a7-e77d-47ed-9a56-42fd4381a860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26574
63216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2657463216
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3971391430
Short name T1170
Test name
Test status
Simulation time 225353164 ps
CPU time 0.85 seconds
Started Jul 17 07:58:30 PM PDT 24
Finished Jul 17 07:58:31 PM PDT 24
Peak memory 206456 kb
Host smart-bcbc5f14-9db5-441d-b6ab-62eddcda3c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
91430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3971391430
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.894857416
Short name T1131
Test name
Test status
Simulation time 191286549 ps
CPU time 0.88 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:38 PM PDT 24
Peak memory 206452 kb
Host smart-a812d218-8b0f-400f-a12d-98b0c8728d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89485
7416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.894857416
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.156529998
Short name T2516
Test name
Test status
Simulation time 162531189 ps
CPU time 0.83 seconds
Started Jul 17 07:58:33 PM PDT 24
Finished Jul 17 07:58:36 PM PDT 24
Peak memory 206448 kb
Host smart-adf7d153-1e65-4dc0-ac92-3383906cdb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15652
9998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.156529998
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.384049231
Short name T886
Test name
Test status
Simulation time 217767927 ps
CPU time 0.9 seconds
Started Jul 17 07:58:31 PM PDT 24
Finished Jul 17 07:58:33 PM PDT 24
Peak memory 206464 kb
Host smart-2e441a26-3c30-44e9-b3dd-d255c4d46240
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=384049231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.384049231
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.354899174
Short name T529
Test name
Test status
Simulation time 146688282 ps
CPU time 0.76 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:42 PM PDT 24
Peak memory 206456 kb
Host smart-53771ab2-2756-4bf4-91a1-a89a176fc501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35489
9174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.354899174
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2746635270
Short name T1941
Test name
Test status
Simulation time 48343947 ps
CPU time 0.67 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:42 PM PDT 24
Peak memory 206436 kb
Host smart-13f7150e-30ff-4b6b-94f7-e34ad01e8113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27466
35270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2746635270
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.4191333911
Short name T1240
Test name
Test status
Simulation time 21163395617 ps
CPU time 51.68 seconds
Started Jul 17 07:58:33 PM PDT 24
Finished Jul 17 07:59:27 PM PDT 24
Peak memory 206676 kb
Host smart-6702ff48-f600-4089-ae87-30d207aef35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41913
33911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.4191333911
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2151139805
Short name T2576
Test name
Test status
Simulation time 188348342 ps
CPU time 0.79 seconds
Started Jul 17 07:58:30 PM PDT 24
Finished Jul 17 07:58:31 PM PDT 24
Peak memory 206456 kb
Host smart-9530d380-6ee1-4506-8785-91ffcaee8d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21511
39805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2151139805
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1754815284
Short name T687
Test name
Test status
Simulation time 184758020 ps
CPU time 0.82 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:43 PM PDT 24
Peak memory 206400 kb
Host smart-c731adce-c64b-46a0-b029-ad70a631f81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17548
15284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1754815284
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2069820190
Short name T1743
Test name
Test status
Simulation time 251848403 ps
CPU time 1 seconds
Started Jul 17 07:58:33 PM PDT 24
Finished Jul 17 07:58:36 PM PDT 24
Peak memory 206448 kb
Host smart-19d55280-18c2-4c2f-b23f-6f732010b103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20698
20190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2069820190
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2685596241
Short name T1385
Test name
Test status
Simulation time 222657929 ps
CPU time 0.89 seconds
Started Jul 17 07:58:30 PM PDT 24
Finished Jul 17 07:58:32 PM PDT 24
Peak memory 206444 kb
Host smart-3bc4c509-6b10-4e85-aac1-c218f63da380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26855
96241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2685596241
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2200737695
Short name T2023
Test name
Test status
Simulation time 185422312 ps
CPU time 0.81 seconds
Started Jul 17 07:58:32 PM PDT 24
Finished Jul 17 07:58:34 PM PDT 24
Peak memory 206436 kb
Host smart-a44f82b6-5f0b-4630-b972-baa782af6cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22007
37695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2200737695
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3595661117
Short name T1859
Test name
Test status
Simulation time 153465322 ps
CPU time 0.82 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:37 PM PDT 24
Peak memory 206404 kb
Host smart-bc72ee6c-f795-4ca4-b2b8-e1f4b1700d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35956
61117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3595661117
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1770583560
Short name T2304
Test name
Test status
Simulation time 151062920 ps
CPU time 0.79 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206460 kb
Host smart-3afe47c4-ceb6-4348-902f-9e11e9afba6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17705
83560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1770583560
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4204801151
Short name T2021
Test name
Test status
Simulation time 209413547 ps
CPU time 0.86 seconds
Started Jul 17 07:58:35 PM PDT 24
Finished Jul 17 07:58:39 PM PDT 24
Peak memory 206460 kb
Host smart-181c96f1-3518-43f6-8ec2-17c882a55435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42048
01151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4204801151
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.3958070626
Short name T1159
Test name
Test status
Simulation time 3717207456 ps
CPU time 36.07 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:59:17 PM PDT 24
Peak memory 206700 kb
Host smart-72d71f15-9bb8-47ff-af00-13faadc6aead
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3958070626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.3958070626
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1514513197
Short name T1391
Test name
Test status
Simulation time 179179614 ps
CPU time 0.81 seconds
Started Jul 17 07:58:33 PM PDT 24
Finished Jul 17 07:58:35 PM PDT 24
Peak memory 206428 kb
Host smart-895cb705-b296-4fa1-8c9d-e1d100007224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15145
13197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1514513197
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3393638791
Short name T2180
Test name
Test status
Simulation time 162318066 ps
CPU time 0.79 seconds
Started Jul 17 07:58:30 PM PDT 24
Finished Jul 17 07:58:31 PM PDT 24
Peak memory 206472 kb
Host smart-6a75a8d2-41b6-4862-9477-3471ebeac206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33936
38791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3393638791
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.1511205441
Short name T2157
Test name
Test status
Simulation time 384390254 ps
CPU time 1.18 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:38 PM PDT 24
Peak memory 206444 kb
Host smart-28d4bf79-c608-458d-a788-068883dbcf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15112
05441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1511205441
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.3746695222
Short name T1277
Test name
Test status
Simulation time 7083095847 ps
CPU time 187.59 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 08:01:50 PM PDT 24
Peak memory 206688 kb
Host smart-c3198df0-99d4-40b8-a8fd-7d2b196d9087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37466
95222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.3746695222
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2332663969
Short name T1068
Test name
Test status
Simulation time 86259303 ps
CPU time 0.71 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206228 kb
Host smart-e03f07f0-38a6-4aef-ace0-52196f919123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2332663969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2332663969
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1457672002
Short name T933
Test name
Test status
Simulation time 4359251114 ps
CPU time 4.7 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:41 PM PDT 24
Peak memory 206652 kb
Host smart-8fe05032-69af-49eb-9122-7fbdd5caff6d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1457672002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1457672002
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.594947471
Short name T1166
Test name
Test status
Simulation time 13458460030 ps
CPU time 13.28 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:55 PM PDT 24
Peak memory 206616 kb
Host smart-61b816a9-972c-4d46-8c3d-85930f93a135
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=594947471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.594947471
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.4223853755
Short name T1908
Test name
Test status
Simulation time 23302755012 ps
CPU time 23.24 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:59 PM PDT 24
Peak memory 206472 kb
Host smart-455affdc-f8ea-48c1-8b20-9d786868bb15
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4223853755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.4223853755
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.4285523119
Short name T399
Test name
Test status
Simulation time 179873766 ps
CPU time 0.8 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:43 PM PDT 24
Peak memory 206456 kb
Host smart-8e5a1cf3-a99d-4a18-8634-d0045543b010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42855
23119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.4285523119
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1216226221
Short name T912
Test name
Test status
Simulation time 140255141 ps
CPU time 0.75 seconds
Started Jul 17 07:58:33 PM PDT 24
Finished Jul 17 07:58:35 PM PDT 24
Peak memory 206428 kb
Host smart-06dddd7b-dc32-4c05-8706-75fe40566afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12162
26221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1216226221
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2234461369
Short name T1411
Test name
Test status
Simulation time 437533019 ps
CPU time 1.34 seconds
Started Jul 17 07:58:33 PM PDT 24
Finished Jul 17 07:58:35 PM PDT 24
Peak memory 206560 kb
Host smart-efd582e7-2257-41f1-bd0c-722fd98f2ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22344
61369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2234461369
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3308885728
Short name T1393
Test name
Test status
Simulation time 1502039470 ps
CPU time 3.71 seconds
Started Jul 17 07:58:35 PM PDT 24
Finished Jul 17 07:58:43 PM PDT 24
Peak memory 206668 kb
Host smart-2109eb51-e806-44e6-8db9-dcaf8b024f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33088
85728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3308885728
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2340272221
Short name T1022
Test name
Test status
Simulation time 6741200541 ps
CPU time 12.57 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:58 PM PDT 24
Peak memory 206704 kb
Host smart-017da27d-81c1-4818-bc40-1e99e03b1fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23402
72221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2340272221
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.2210245912
Short name T724
Test name
Test status
Simulation time 419859597 ps
CPU time 1.42 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:38 PM PDT 24
Peak memory 206456 kb
Host smart-6a183f1a-764a-409f-a00c-cacce27292d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22102
45912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.2210245912
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.3141500073
Short name T335
Test name
Test status
Simulation time 152913776 ps
CPU time 0.76 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:37 PM PDT 24
Peak memory 206448 kb
Host smart-5f050270-a3af-4caa-b1d7-53e621ef12c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31415
00073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.3141500073
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1119093741
Short name T539
Test name
Test status
Simulation time 35800294 ps
CPU time 0.67 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206444 kb
Host smart-b2269e41-e846-4da4-8a22-47718813d8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11190
93741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1119093741
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1688871233
Short name T757
Test name
Test status
Simulation time 945173579 ps
CPU time 2.41 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206488 kb
Host smart-1c5e420e-ee88-4cf2-8764-84d9dede0d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16888
71233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1688871233
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.759931029
Short name T1949
Test name
Test status
Simulation time 232514150 ps
CPU time 1.62 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:42 PM PDT 24
Peak memory 206648 kb
Host smart-513112ef-1687-4b81-b5d1-9a83d64143b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75993
1029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.759931029
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1711107634
Short name T1617
Test name
Test status
Simulation time 209429473 ps
CPU time 0.88 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206452 kb
Host smart-1ae0ea59-463f-4ede-8ed9-993839b25cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17111
07634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1711107634
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.392563435
Short name T2360
Test name
Test status
Simulation time 143494173 ps
CPU time 0.78 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206592 kb
Host smart-6904ce97-7d8c-4e86-a158-204a652ff707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39256
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.392563435
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.964245966
Short name T1183
Test name
Test status
Simulation time 199799535 ps
CPU time 0.82 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206416 kb
Host smart-def5bc96-958d-4855-aa0a-5301a35749e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96424
5966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.964245966
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.1875155453
Short name T714
Test name
Test status
Simulation time 6201239245 ps
CPU time 19.59 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:59:04 PM PDT 24
Peak memory 206804 kb
Host smart-cb8e78ad-3e2e-47a5-913f-2346ad1ebff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18751
55453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.1875155453
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3384070862
Short name T1162
Test name
Test status
Simulation time 214841443 ps
CPU time 0.93 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:41 PM PDT 24
Peak memory 206452 kb
Host smart-9d7c7716-8567-4cce-bc54-f62a59ba834c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33840
70862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3384070862
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3690856186
Short name T2617
Test name
Test status
Simulation time 23264640677 ps
CPU time 30.06 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:59:14 PM PDT 24
Peak memory 206512 kb
Host smart-8a131cc0-9894-4077-87b7-30656297fd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36908
56186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3690856186
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.4128374461
Short name T1019
Test name
Test status
Simulation time 3275791504 ps
CPU time 3.91 seconds
Started Jul 17 07:58:31 PM PDT 24
Finished Jul 17 07:58:36 PM PDT 24
Peak memory 206516 kb
Host smart-0b3eedc7-ac31-4686-96aa-df1bebbbb7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41283
74461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.4128374461
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2422328673
Short name T1513
Test name
Test status
Simulation time 6659385088 ps
CPU time 63.4 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:59:46 PM PDT 24
Peak memory 206732 kb
Host smart-0b7011f2-99a6-4d04-a1d4-7831c9a74a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24223
28673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2422328673
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3465120379
Short name T581
Test name
Test status
Simulation time 6001276301 ps
CPU time 157.79 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206460 kb
Host smart-6c02bc3e-99f6-43c6-8942-80917e1df2b0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3465120379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3465120379
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2023903806
Short name T767
Test name
Test status
Simulation time 243398192 ps
CPU time 0.93 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206452 kb
Host smart-662749c7-b3e3-4acd-9867-9e83e6bf7344
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2023903806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2023903806
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2724373067
Short name T2732
Test name
Test status
Simulation time 192869850 ps
CPU time 0.92 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206408 kb
Host smart-fa0834f8-378a-44e8-bba8-d49b9f6d43d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
73067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2724373067
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.4090841807
Short name T160
Test name
Test status
Simulation time 4403607965 ps
CPU time 32.27 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:59:20 PM PDT 24
Peak memory 206668 kb
Host smart-2abe5bde-92a5-4b66-9127-656c52c693f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40908
41807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.4090841807
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2360465624
Short name T1087
Test name
Test status
Simulation time 4430575639 ps
CPU time 40.44 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:59:26 PM PDT 24
Peak memory 206664 kb
Host smart-4207b94f-b8c5-4dee-bd64-a184e85e4767
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2360465624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2360465624
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.138811722
Short name T1037
Test name
Test status
Simulation time 154796591 ps
CPU time 0.75 seconds
Started Jul 17 07:58:31 PM PDT 24
Finished Jul 17 07:58:33 PM PDT 24
Peak memory 206460 kb
Host smart-515a7ff3-0018-4764-b89f-4409653a5bb1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=138811722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.138811722
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2252276187
Short name T2490
Test name
Test status
Simulation time 148811201 ps
CPU time 0.83 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206464 kb
Host smart-3dfedbf3-44d8-4399-98ce-fccb6435f271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22522
76187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2252276187
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2581918639
Short name T2534
Test name
Test status
Simulation time 177298784 ps
CPU time 0.81 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:40 PM PDT 24
Peak memory 206448 kb
Host smart-4ba83d17-8474-4ed0-be20-62c2f6a446d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25819
18639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2581918639
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3555763921
Short name T1694
Test name
Test status
Simulation time 166254142 ps
CPU time 0.8 seconds
Started Jul 17 07:58:32 PM PDT 24
Finished Jul 17 07:58:35 PM PDT 24
Peak memory 206448 kb
Host smart-55ee7b60-b0d8-47e1-98ae-fa33611ef94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557
63921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3555763921
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1540293450
Short name T1872
Test name
Test status
Simulation time 169395471 ps
CPU time 0.8 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:41 PM PDT 24
Peak memory 206456 kb
Host smart-48cbf765-23ab-4e34-bea9-6a84ff779eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15402
93450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1540293450
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.4094645482
Short name T1046
Test name
Test status
Simulation time 182297729 ps
CPU time 0.87 seconds
Started Jul 17 07:58:31 PM PDT 24
Finished Jul 17 07:58:33 PM PDT 24
Peak memory 206444 kb
Host smart-e4940419-cb20-4827-8d37-a0e1ead58f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40946
45482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.4094645482
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2669325733
Short name T1623
Test name
Test status
Simulation time 150892769 ps
CPU time 0.76 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:40 PM PDT 24
Peak memory 206460 kb
Host smart-428c040e-9c92-4827-a2e8-58d33cad047c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26693
25733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2669325733
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2637768013
Short name T1024
Test name
Test status
Simulation time 207524182 ps
CPU time 0.9 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:37 PM PDT 24
Peak memory 206448 kb
Host smart-9ac8fedf-e813-41fc-8e0e-cbbe8603c743
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2637768013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2637768013
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3675757115
Short name T710
Test name
Test status
Simulation time 142876634 ps
CPU time 0.78 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:42 PM PDT 24
Peak memory 206248 kb
Host smart-9218b3f1-e2d0-4808-9fd1-49900afae08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36757
57115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3675757115
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.823715746
Short name T938
Test name
Test status
Simulation time 58660627 ps
CPU time 0.66 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206452 kb
Host smart-f24482bc-2df1-444e-a973-954f142eb7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82371
5746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.823715746
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.41299755
Short name T1782
Test name
Test status
Simulation time 15821364898 ps
CPU time 34.41 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:59:22 PM PDT 24
Peak memory 206764 kb
Host smart-eac0c98d-1813-4b4b-86db-a7a18e5cd94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41299
755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.41299755
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2552472750
Short name T1132
Test name
Test status
Simulation time 177064532 ps
CPU time 0.81 seconds
Started Jul 17 07:58:35 PM PDT 24
Finished Jul 17 07:58:40 PM PDT 24
Peak memory 206464 kb
Host smart-d508f36d-a762-46d4-b2ee-3b549714c9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
72750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2552472750
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2500142193
Short name T979
Test name
Test status
Simulation time 204044799 ps
CPU time 0.87 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206456 kb
Host smart-c03c431d-6fd0-439f-b7da-2299bb9c5302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25001
42193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2500142193
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1846985261
Short name T31
Test name
Test status
Simulation time 222657126 ps
CPU time 0.96 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206372 kb
Host smart-fe020f3e-f1cf-4254-b8e6-3ed341571912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18469
85261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1846985261
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.534096330
Short name T348
Test name
Test status
Simulation time 213284146 ps
CPU time 0.87 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206452 kb
Host smart-7ddf412c-fe00-4fd1-b027-782a07c93e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53409
6330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.534096330
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2572098464
Short name T1645
Test name
Test status
Simulation time 141532088 ps
CPU time 0.77 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206440 kb
Host smart-73c0cc2c-ff4f-4608-9160-b938c2e8db1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25720
98464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2572098464
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.2411856884
Short name T149
Test name
Test status
Simulation time 173714224 ps
CPU time 0.77 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206456 kb
Host smart-68512630-3b07-46f2-b51e-a587bc20f8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24118
56884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.2411856884
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.128980728
Short name T2105
Test name
Test status
Simulation time 145523895 ps
CPU time 0.78 seconds
Started Jul 17 07:58:42 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206248 kb
Host smart-c80ab8ff-1284-473e-a2dc-f4ef1c73aa93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
0728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.128980728
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3496528351
Short name T2292
Test name
Test status
Simulation time 237920616 ps
CPU time 0.95 seconds
Started Jul 17 07:58:43 PM PDT 24
Finished Jul 17 07:58:51 PM PDT 24
Peak memory 206436 kb
Host smart-36c561ca-c697-467b-aeec-f5c6a1d192d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34965
28351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3496528351
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.519200470
Short name T914
Test name
Test status
Simulation time 4145048661 ps
CPU time 38.38 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:59:25 PM PDT 24
Peak memory 206732 kb
Host smart-fa7b5432-29d2-4bf1-898f-d0d3683da3c6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=519200470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.519200470
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2797199110
Short name T418
Test name
Test status
Simulation time 151637851 ps
CPU time 0.78 seconds
Started Jul 17 07:58:42 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206212 kb
Host smart-5de00b59-4b4d-4055-8421-dee6437f1705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27971
99110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2797199110
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2633836993
Short name T2213
Test name
Test status
Simulation time 201721493 ps
CPU time 0.89 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206452 kb
Host smart-1e807578-e23a-4a5d-85d1-0221ec3e390b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26338
36993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2633836993
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.194966099
Short name T431
Test name
Test status
Simulation time 1320190065 ps
CPU time 2.78 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206644 kb
Host smart-d34da5f7-60e1-42e4-b26d-cf3ea98fc565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19496
6099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.194966099
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.3233550700
Short name T1268
Test name
Test status
Simulation time 7201623981 ps
CPU time 66.91 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:59:46 PM PDT 24
Peak memory 206804 kb
Host smart-884ebcc4-a40a-421f-a32c-b3b41a95e207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32335
50700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.3233550700
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.41148755
Short name T1664
Test name
Test status
Simulation time 43197331 ps
CPU time 0.68 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 07:59:03 PM PDT 24
Peak memory 206428 kb
Host smart-96fc0e4b-2e1e-4f73-9edc-815e040241e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=41148755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.41148755
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2582008666
Short name T2447
Test name
Test status
Simulation time 3591984337 ps
CPU time 4.13 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:58:52 PM PDT 24
Peak memory 206292 kb
Host smart-c2536fcc-e43f-4c66-b3eb-a3008bb6bee9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2582008666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.2582008666
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.823445620
Short name T2423
Test name
Test status
Simulation time 13510987760 ps
CPU time 13.43 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:59:01 PM PDT 24
Peak memory 206644 kb
Host smart-6fcb8535-5168-455c-bad4-ca305dafb451
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=823445620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.823445620
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2457925158
Short name T945
Test name
Test status
Simulation time 23350459020 ps
CPU time 21.39 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:59:05 PM PDT 24
Peak memory 206752 kb
Host smart-3f333c4c-4bd1-4320-807c-47af4df9dfb3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2457925158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.2457925158
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.93312172
Short name T145
Test name
Test status
Simulation time 174716459 ps
CPU time 0.78 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206448 kb
Host smart-0e665a25-2432-491f-8ba1-521f41d4d983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93312
172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.93312172
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.192621566
Short name T1813
Test name
Test status
Simulation time 223447867 ps
CPU time 0.91 seconds
Started Jul 17 07:58:45 PM PDT 24
Finished Jul 17 07:58:51 PM PDT 24
Peak memory 206440 kb
Host smart-20cf42cb-768e-426b-86e9-81971060462c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19262
1566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.192621566
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3374091910
Short name T1015
Test name
Test status
Simulation time 385535533 ps
CPU time 1.2 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206464 kb
Host smart-5c809ad9-ff1e-449c-985a-23511b5f5c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33740
91910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3374091910
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.4152641227
Short name T1485
Test name
Test status
Simulation time 955950542 ps
CPU time 2.26 seconds
Started Jul 17 07:58:45 PM PDT 24
Finished Jul 17 07:58:53 PM PDT 24
Peak memory 206588 kb
Host smart-e635bdeb-2b23-4b7c-8641-fc5d8d2d99bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41526
41227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.4152641227
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2828184436
Short name T1605
Test name
Test status
Simulation time 8472788082 ps
CPU time 14.11 seconds
Started Jul 17 07:58:33 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206644 kb
Host smart-3e87c533-a728-4f66-ad8b-53ab5587cea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28281
84436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2828184436
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.2104379767
Short name T2735
Test name
Test status
Simulation time 410387958 ps
CPU time 1.37 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206460 kb
Host smart-bfd97d8e-7e72-4be6-bafa-689c83fb95f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043
79767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.2104379767
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3555622442
Short name T2367
Test name
Test status
Simulation time 150953080 ps
CPU time 0.78 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206592 kb
Host smart-85b911fd-a374-4e4c-824e-a176cb452893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35556
22442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3555622442
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1402632624
Short name T2722
Test name
Test status
Simulation time 40550338 ps
CPU time 0.66 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206452 kb
Host smart-b0060cde-1469-4e3e-955c-40dcca8b99ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14026
32624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1402632624
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1587176152
Short name T141
Test name
Test status
Simulation time 977854663 ps
CPU time 2.08 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206644 kb
Host smart-969cdebb-6734-4ade-a868-9b1f8bd4ce93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
76152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1587176152
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.342996951
Short name T208
Test name
Test status
Simulation time 272223856 ps
CPU time 1.61 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:41 PM PDT 24
Peak memory 206592 kb
Host smart-c6ca74cd-aa5a-45c9-8084-794dd10e1792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34299
6951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.342996951
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.738778760
Short name T761
Test name
Test status
Simulation time 216900425 ps
CPU time 0.91 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:45 PM PDT 24
Peak memory 206592 kb
Host smart-c7e59e36-96fe-4fcb-be49-5d156cddae49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73877
8760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.738778760
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1741599978
Short name T1188
Test name
Test status
Simulation time 165138500 ps
CPU time 0.76 seconds
Started Jul 17 07:58:35 PM PDT 24
Finished Jul 17 07:58:39 PM PDT 24
Peak memory 206444 kb
Host smart-631508ad-53fd-4b30-b020-3c359bbb9e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17415
99978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1741599978
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3556604681
Short name T308
Test name
Test status
Simulation time 180513871 ps
CPU time 0.85 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206460 kb
Host smart-9cd82603-ec25-4bb5-92a1-c8bb7530a940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35566
04681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3556604681
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.3068543653
Short name T897
Test name
Test status
Simulation time 6761110863 ps
CPU time 57.19 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:59:40 PM PDT 24
Peak memory 206728 kb
Host smart-1c849afb-7a78-4aa2-b407-729fbe8883ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30685
43653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.3068543653
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2631421886
Short name T1890
Test name
Test status
Simulation time 197592154 ps
CPU time 0.82 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:42 PM PDT 24
Peak memory 206448 kb
Host smart-0b7ec597-ec07-445c-9ed7-d86e0aa1607d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26314
21886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2631421886
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1793013861
Short name T2702
Test name
Test status
Simulation time 23297032163 ps
CPU time 22.46 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:59:08 PM PDT 24
Peak memory 206384 kb
Host smart-afe1ddf0-cbab-4480-bb52-214cbf8ed192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17930
13861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1793013861
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3889132893
Short name T328
Test name
Test status
Simulation time 3323933576 ps
CPU time 3.72 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:58:52 PM PDT 24
Peak memory 206484 kb
Host smart-568e2536-18f7-45e0-9df6-1ba2f3a7409e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38891
32893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3889132893
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1602062155
Short name T456
Test name
Test status
Simulation time 12188718695 ps
CPU time 111.55 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206672 kb
Host smart-af13b9be-501e-4a9a-a84e-050dfad3f87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16020
62155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1602062155
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3227992297
Short name T2329
Test name
Test status
Simulation time 4937926346 ps
CPU time 45.99 seconds
Started Jul 17 07:58:32 PM PDT 24
Finished Jul 17 07:59:20 PM PDT 24
Peak memory 206848 kb
Host smart-473049ae-297f-4b5f-8490-64dd2bb6d752
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3227992297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3227992297
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2179565274
Short name T2596
Test name
Test status
Simulation time 249797689 ps
CPU time 0.89 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206412 kb
Host smart-91afbbb5-544c-4616-9758-470841ab08ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2179565274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2179565274
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.132343775
Short name T1287
Test name
Test status
Simulation time 182948872 ps
CPU time 0.83 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:48 PM PDT 24
Peak memory 206408 kb
Host smart-7a5e2ee8-dc6e-4774-85ae-bee91912ce08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13234
3775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.132343775
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.1055169903
Short name T737
Test name
Test status
Simulation time 3984140153 ps
CPU time 111.86 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 08:00:33 PM PDT 24
Peak memory 206472 kb
Host smart-da4fed3e-e168-4c43-a973-6d748d83b508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10551
69903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.1055169903
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.4001752181
Short name T2260
Test name
Test status
Simulation time 4764052116 ps
CPU time 44.45 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:59:33 PM PDT 24
Peak memory 206612 kb
Host smart-135d8f6b-03f7-4c77-a922-0f1465502d48
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4001752181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.4001752181
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.4152881055
Short name T1214
Test name
Test status
Simulation time 179219942 ps
CPU time 0.79 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206460 kb
Host smart-52945be9-872d-4e1c-b58a-861d8fa59c67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4152881055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.4152881055
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.718361852
Short name T966
Test name
Test status
Simulation time 140320756 ps
CPU time 0.77 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206408 kb
Host smart-16842cdb-2b84-4825-b2c1-321e4d444a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71836
1852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.718361852
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3640681497
Short name T115
Test name
Test status
Simulation time 251260661 ps
CPU time 0.88 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206456 kb
Host smart-e225a60b-5117-427d-a27f-ec84976f234f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
81497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3640681497
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.929325465
Short name T2438
Test name
Test status
Simulation time 179529335 ps
CPU time 0.9 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:42 PM PDT 24
Peak memory 206448 kb
Host smart-8fd8fd19-e417-4f89-a53f-eb7cf75ae058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92932
5465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.929325465
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2057281181
Short name T2194
Test name
Test status
Simulation time 165002267 ps
CPU time 0.8 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206456 kb
Host smart-13d4d39e-d485-4274-8a96-32d0c368b1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20572
81181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2057281181
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2255745927
Short name T2389
Test name
Test status
Simulation time 172086932 ps
CPU time 0.81 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206412 kb
Host smart-78dcc66d-74da-4bd6-93a6-887e04b5d06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
45927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2255745927
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1120391418
Short name T159
Test name
Test status
Simulation time 152503900 ps
CPU time 0.78 seconds
Started Jul 17 07:58:38 PM PDT 24
Finished Jul 17 07:58:46 PM PDT 24
Peak memory 206464 kb
Host smart-2b788f0c-accf-4d0c-aeda-05b8cf482873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11203
91418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1120391418
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3974792848
Short name T2025
Test name
Test status
Simulation time 214092034 ps
CPU time 0.92 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206456 kb
Host smart-bd14a82d-3db0-4978-a3e7-61869a7e69e3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3974792848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3974792848
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.43148302
Short name T676
Test name
Test status
Simulation time 157947019 ps
CPU time 0.81 seconds
Started Jul 17 07:58:41 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206440 kb
Host smart-215c8341-6e3c-4194-9c67-6967e8104ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43148
302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.43148302
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.613829525
Short name T1679
Test name
Test status
Simulation time 30116777 ps
CPU time 0.66 seconds
Started Jul 17 07:58:45 PM PDT 24
Finished Jul 17 07:58:51 PM PDT 24
Peak memory 206408 kb
Host smart-88836add-a1de-443f-aa92-5f61828adc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61382
9525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.613829525
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2052100483
Short name T264
Test name
Test status
Simulation time 16342432290 ps
CPU time 39.07 seconds
Started Jul 17 07:58:42 PM PDT 24
Finished Jul 17 07:59:28 PM PDT 24
Peak memory 206688 kb
Host smart-202427a8-a90c-46b5-88e2-5e6dee565d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20521
00483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2052100483
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2948605395
Short name T2291
Test name
Test status
Simulation time 153148481 ps
CPU time 0.84 seconds
Started Jul 17 07:58:45 PM PDT 24
Finished Jul 17 07:58:51 PM PDT 24
Peak memory 206432 kb
Host smart-38e07073-3bbe-46f4-b517-e3dd5150b1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29486
05395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2948605395
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.480369402
Short name T1003
Test name
Test status
Simulation time 214711807 ps
CPU time 0.9 seconds
Started Jul 17 07:58:42 PM PDT 24
Finished Jul 17 07:58:50 PM PDT 24
Peak memory 206368 kb
Host smart-00c41ad4-48f4-42ff-a1f8-e577079209cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48036
9402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.480369402
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1850513052
Short name T1160
Test name
Test status
Simulation time 237349941 ps
CPU time 0.86 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:44 PM PDT 24
Peak memory 206456 kb
Host smart-d17c9536-8931-49f5-a215-1fc2644a4485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
13052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1850513052
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1326621035
Short name T814
Test name
Test status
Simulation time 172826805 ps
CPU time 0.86 seconds
Started Jul 17 07:58:36 PM PDT 24
Finished Jul 17 07:58:43 PM PDT 24
Peak memory 206428 kb
Host smart-72eca92b-0e91-4452-9800-f8ee9328e37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13266
21035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1326621035
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.4016648146
Short name T599
Test name
Test status
Simulation time 137756169 ps
CPU time 0.78 seconds
Started Jul 17 07:58:45 PM PDT 24
Finished Jul 17 07:58:51 PM PDT 24
Peak memory 206420 kb
Host smart-bbad5e9a-39cd-46df-bea9-65908b750b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40166
48146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.4016648146
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2285159518
Short name T1920
Test name
Test status
Simulation time 153414876 ps
CPU time 0.75 seconds
Started Jul 17 07:58:37 PM PDT 24
Finished Jul 17 07:58:43 PM PDT 24
Peak memory 206452 kb
Host smart-e7dccc3a-b406-44eb-ab1f-29b482808c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22851
59518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2285159518
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.4031844792
Short name T1226
Test name
Test status
Simulation time 154760056 ps
CPU time 0.76 seconds
Started Jul 17 07:58:39 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 206460 kb
Host smart-bd2f6eff-4cc7-4cb7-9541-61c68e4f8a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40318
44792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.4031844792
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.162328134
Short name T739
Test name
Test status
Simulation time 241919794 ps
CPU time 0.94 seconds
Started Jul 17 07:58:44 PM PDT 24
Finished Jul 17 07:58:51 PM PDT 24
Peak memory 206432 kb
Host smart-2714957b-a661-45c1-b667-65802aba9f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
8134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.162328134
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3764084891
Short name T2154
Test name
Test status
Simulation time 6240227921 ps
CPU time 58.8 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:59:47 PM PDT 24
Peak memory 206648 kb
Host smart-932b76a6-d89b-4f53-8347-68e77af3d440
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3764084891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3764084891
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2263716810
Short name T2703
Test name
Test status
Simulation time 233086096 ps
CPU time 0.89 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206464 kb
Host smart-229a250f-a448-4404-9572-a443e1ea9aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22637
16810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2263716810
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.755487460
Short name T436
Test name
Test status
Simulation time 205403482 ps
CPU time 0.86 seconds
Started Jul 17 07:58:40 PM PDT 24
Finished Jul 17 07:58:49 PM PDT 24
Peak memory 206476 kb
Host smart-c1795e73-9fb7-4a53-89de-f1053fab3021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75548
7460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.755487460
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.2025074153
Short name T1407
Test name
Test status
Simulation time 432120527 ps
CPU time 1.25 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:58:38 PM PDT 24
Peak memory 206452 kb
Host smart-95e0cbb0-f82c-4c09-aa8e-cbc5d2d88eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20250
74153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2025074153
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2784121547
Short name T2166
Test name
Test status
Simulation time 5241283733 ps
CPU time 47.48 seconds
Started Jul 17 07:58:34 PM PDT 24
Finished Jul 17 07:59:25 PM PDT 24
Peak memory 206716 kb
Host smart-79c68720-f795-4487-bdbb-34f24d2f15bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27841
21547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2784121547
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1216249050
Short name T1781
Test name
Test status
Simulation time 36808011 ps
CPU time 0.69 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:08 PM PDT 24
Peak memory 206444 kb
Host smart-d977596d-1a67-483d-a41e-c10c031d8f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1216249050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1216249050
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1697455416
Short name T619
Test name
Test status
Simulation time 3601221278 ps
CPU time 4.62 seconds
Started Jul 17 07:58:59 PM PDT 24
Finished Jul 17 07:59:04 PM PDT 24
Peak memory 206664 kb
Host smart-2dc97c3f-1d81-4af0-aa19-a020de615121
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1697455416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1697455416
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1596758207
Short name T16
Test name
Test status
Simulation time 13376429589 ps
CPU time 13.32 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 07:59:17 PM PDT 24
Peak memory 206520 kb
Host smart-28bb8358-6427-4c7c-8161-8edbb3fb0560
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1596758207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1596758207
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2423688045
Short name T2031
Test name
Test status
Simulation time 23403563604 ps
CPU time 24.73 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 07:59:28 PM PDT 24
Peak memory 206524 kb
Host smart-18163c5c-539c-4927-9299-a67732333ab3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2423688045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2423688045
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.4221696826
Short name T143
Test name
Test status
Simulation time 196465447 ps
CPU time 0.8 seconds
Started Jul 17 07:59:07 PM PDT 24
Finished Jul 17 07:59:12 PM PDT 24
Peak memory 206460 kb
Host smart-87cf9e08-1731-42fd-bcbf-5a49c8c29619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42216
96826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4221696826
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3497651668
Short name T1049
Test name
Test status
Simulation time 178786875 ps
CPU time 0.83 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:07 PM PDT 24
Peak memory 206588 kb
Host smart-616f4854-4ea4-40a2-a5bb-889a7d5f5066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34976
51668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3497651668
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3655673969
Short name T2118
Test name
Test status
Simulation time 514646686 ps
CPU time 1.4 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:10 PM PDT 24
Peak memory 206660 kb
Host smart-bca11f21-edf0-47a7-89fb-82b54b0258ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36556
73969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3655673969
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2847246534
Short name T1165
Test name
Test status
Simulation time 578270826 ps
CPU time 1.42 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206460 kb
Host smart-70dcac10-26e1-4b72-895d-22ab24d2a807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28472
46534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2847246534
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3945229159
Short name T2319
Test name
Test status
Simulation time 17136762150 ps
CPU time 32.39 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:40 PM PDT 24
Peak memory 206652 kb
Host smart-47f4da72-ca88-449f-ae80-20cb1783a957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
29159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3945229159
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.727924297
Short name T321
Test name
Test status
Simulation time 428000286 ps
CPU time 1.21 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206408 kb
Host smart-1a42fdea-97a6-4da0-84d7-7293ab04ca0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72792
4297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.727924297
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.839537847
Short name T67
Test name
Test status
Simulation time 141745337 ps
CPU time 0.76 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:06 PM PDT 24
Peak memory 206456 kb
Host smart-f8db6ab9-de87-4112-99b0-4c73ab5ab687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83953
7847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.839537847
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1029009322
Short name T874
Test name
Test status
Simulation time 43240817 ps
CPU time 0.65 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:07 PM PDT 24
Peak memory 206392 kb
Host smart-c2def24b-41b1-49dd-a685-9fa5a81bb05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10290
09322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1029009322
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2176031901
Short name T1465
Test name
Test status
Simulation time 839170961 ps
CPU time 1.86 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:11 PM PDT 24
Peak memory 206608 kb
Host smart-be11dfe9-212b-4b2e-bb70-fc3f6fcecfe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21760
31901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2176031901
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2042937963
Short name T2412
Test name
Test status
Simulation time 260426130 ps
CPU time 1.71 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:07 PM PDT 24
Peak memory 206608 kb
Host smart-17c6f934-162a-4089-8147-328ba15fe5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20429
37963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2042937963
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2096439077
Short name T1568
Test name
Test status
Simulation time 213386726 ps
CPU time 0.88 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:06 PM PDT 24
Peak memory 206468 kb
Host smart-b4040512-753f-443b-bfb3-0fef9b250c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20964
39077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2096439077
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.13134327
Short name T922
Test name
Test status
Simulation time 151476402 ps
CPU time 0.81 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 07:59:04 PM PDT 24
Peak memory 206440 kb
Host smart-e44e07ca-147c-4023-87f7-656f3ac12245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.13134327
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.4290135251
Short name T1963
Test name
Test status
Simulation time 191971946 ps
CPU time 0.81 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206436 kb
Host smart-b0965749-ae53-48a2-97bb-81ab1f6ad619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42901
35251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4290135251
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1586751297
Short name T1100
Test name
Test status
Simulation time 13672842828 ps
CPU time 55.38 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 08:00:04 PM PDT 24
Peak memory 206800 kb
Host smart-b50e339e-3dc1-4f91-890a-4765f781b3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
51297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1586751297
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3523176249
Short name T791
Test name
Test status
Simulation time 180728655 ps
CPU time 0.8 seconds
Started Jul 17 07:59:05 PM PDT 24
Finished Jul 17 07:59:11 PM PDT 24
Peak memory 206440 kb
Host smart-81e36740-6e29-4d80-95cb-85295804c49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35231
76249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3523176249
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1538612645
Short name T772
Test name
Test status
Simulation time 23343103160 ps
CPU time 22.53 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:28 PM PDT 24
Peak memory 206524 kb
Host smart-4f50a3f8-5509-42f5-97bd-934f5877b0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15386
12645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1538612645
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.114572303
Short name T612
Test name
Test status
Simulation time 3320927777 ps
CPU time 3.68 seconds
Started Jul 17 07:59:00 PM PDT 24
Finished Jul 17 07:59:05 PM PDT 24
Peak memory 206524 kb
Host smart-07162c02-ee9a-4538-b1f5-0acbcb1fd7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11457
2303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.114572303
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3624588167
Short name T400
Test name
Test status
Simulation time 10392385122 ps
CPU time 69.89 seconds
Started Jul 17 07:59:00 PM PDT 24
Finished Jul 17 08:00:11 PM PDT 24
Peak memory 206720 kb
Host smart-67308bdc-6d95-46e4-a1e7-6486eb8d4e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36245
88167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3624588167
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3235552130
Short name T2610
Test name
Test status
Simulation time 6513386793 ps
CPU time 58.25 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 08:00:06 PM PDT 24
Peak memory 206664 kb
Host smart-2923e943-b8bb-4d40-99a1-14213109d8ae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3235552130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3235552130
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3408272055
Short name T2469
Test name
Test status
Simulation time 237005289 ps
CPU time 0.88 seconds
Started Jul 17 07:58:59 PM PDT 24
Finished Jul 17 07:59:01 PM PDT 24
Peak memory 206448 kb
Host smart-4274e33d-3f21-436b-8165-a7f32ffc02de
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3408272055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3408272055
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1753387015
Short name T1355
Test name
Test status
Simulation time 192339909 ps
CPU time 0.87 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:08 PM PDT 24
Peak memory 206468 kb
Host smart-e361b053-3834-4674-a399-c5178ee5800b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17533
87015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1753387015
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2773345864
Short name T1210
Test name
Test status
Simulation time 4116008854 ps
CPU time 38.32 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:47 PM PDT 24
Peak memory 206704 kb
Host smart-a8a8db87-5347-4d4b-81c5-0da77f04bb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27733
45864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2773345864
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3776588259
Short name T2453
Test name
Test status
Simulation time 6207019433 ps
CPU time 57.27 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 08:00:00 PM PDT 24
Peak memory 206668 kb
Host smart-aff39299-4ca4-4ca2-87c4-33994e8098b1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3776588259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3776588259
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2636716826
Short name T2526
Test name
Test status
Simulation time 159369736 ps
CPU time 0.78 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:07 PM PDT 24
Peak memory 206412 kb
Host smart-95e40a22-c535-472e-be88-b334c37af587
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2636716826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2636716826
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.747870998
Short name T314
Test name
Test status
Simulation time 211458337 ps
CPU time 0.84 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 07:59:03 PM PDT 24
Peak memory 206448 kb
Host smart-619e557c-e31e-4e48-875a-669f04186a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74787
0998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.747870998
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.4267633693
Short name T2418
Test name
Test status
Simulation time 197861586 ps
CPU time 0.83 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:08 PM PDT 24
Peak memory 206456 kb
Host smart-16bb4eb6-5221-4dbb-a1fe-d6f143b59423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42676
33693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.4267633693
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2330065223
Short name T2285
Test name
Test status
Simulation time 171947368 ps
CPU time 0.82 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:07 PM PDT 24
Peak memory 206448 kb
Host smart-1ef17b59-8c13-4a37-978a-427d987b680f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23300
65223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2330065223
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.26176817
Short name T887
Test name
Test status
Simulation time 191331515 ps
CPU time 0.82 seconds
Started Jul 17 07:58:59 PM PDT 24
Finished Jul 17 07:59:01 PM PDT 24
Peak memory 206456 kb
Host smart-d0f90f24-99a7-4480-bc31-b43d3e15a208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26176
817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.26176817
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.127708092
Short name T544
Test name
Test status
Simulation time 199324293 ps
CPU time 0.81 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 07:59:03 PM PDT 24
Peak memory 206436 kb
Host smart-013d49f1-c682-46b0-be43-3b065c8f7d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12770
8092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.127708092
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2223252298
Short name T2102
Test name
Test status
Simulation time 155540952 ps
CPU time 0.77 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206452 kb
Host smart-5fcfca11-f843-4844-98d6-195dbe615349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22232
52298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2223252298
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1530329240
Short name T144
Test name
Test status
Simulation time 253763704 ps
CPU time 0.94 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:07 PM PDT 24
Peak memory 206628 kb
Host smart-26427d11-a0b3-4ede-84f2-80a4ec205211
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1530329240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1530329240
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.195010862
Short name T1860
Test name
Test status
Simulation time 141484683 ps
CPU time 0.74 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:06 PM PDT 24
Peak memory 206464 kb
Host smart-b364ad0c-5682-4222-bf9e-b446b92d43ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19501
0862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.195010862
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1897737188
Short name T1494
Test name
Test status
Simulation time 39825035 ps
CPU time 0.65 seconds
Started Jul 17 07:59:07 PM PDT 24
Finished Jul 17 07:59:12 PM PDT 24
Peak memory 206432 kb
Host smart-02fee9ad-09ed-4ac5-b4db-224826000484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18977
37188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1897737188
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.695146349
Short name T717
Test name
Test status
Simulation time 10175361469 ps
CPU time 21.78 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:27 PM PDT 24
Peak memory 206760 kb
Host smart-732f1db1-17e4-4e95-a0b1-9e46ce603fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69514
6349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.695146349
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.478670791
Short name T1369
Test name
Test status
Simulation time 235497402 ps
CPU time 0.85 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:06 PM PDT 24
Peak memory 206452 kb
Host smart-69d1913f-a3d3-4830-ac06-43193cfc2a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47867
0791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.478670791
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.881861393
Short name T528
Test name
Test status
Simulation time 162368705 ps
CPU time 0.78 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 07:59:04 PM PDT 24
Peak memory 206440 kb
Host smart-95b4275f-3106-4ea9-9086-975bdabe269e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88186
1393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.881861393
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.276488946
Short name T2608
Test name
Test status
Simulation time 210828450 ps
CPU time 0.84 seconds
Started Jul 17 07:59:00 PM PDT 24
Finished Jul 17 07:59:02 PM PDT 24
Peak memory 206464 kb
Host smart-7d99879d-7a78-4a2a-874e-98cec594f624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
8946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.276488946
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.2309107854
Short name T681
Test name
Test status
Simulation time 182463857 ps
CPU time 0.83 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:10 PM PDT 24
Peak memory 206460 kb
Host smart-45a99045-a52d-4c16-b889-85acc20d1ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23091
07854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.2309107854
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3506927367
Short name T1791
Test name
Test status
Simulation time 167035545 ps
CPU time 0.74 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:07 PM PDT 24
Peak memory 206432 kb
Host smart-c875f4a0-50ef-4e7a-8410-efd622740ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35069
27367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3506927367
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3182911000
Short name T1827
Test name
Test status
Simulation time 177895310 ps
CPU time 0.8 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206580 kb
Host smart-875b2877-6722-4ce2-b8a4-93dd19e621ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31829
11000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3182911000
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1014872370
Short name T657
Test name
Test status
Simulation time 156971049 ps
CPU time 0.76 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:08 PM PDT 24
Peak memory 206436 kb
Host smart-3eb058f0-88fa-47c0-b317-df0b47c83a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10148
72370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1014872370
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1621078633
Short name T527
Test name
Test status
Simulation time 235018145 ps
CPU time 0.92 seconds
Started Jul 17 08:00:06 PM PDT 24
Finished Jul 17 08:00:07 PM PDT 24
Peak memory 206436 kb
Host smart-ed43f330-efd0-447e-a5b9-05b53a041919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16210
78633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1621078633
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.146255979
Short name T1375
Test name
Test status
Simulation time 4132320279 ps
CPU time 117.88 seconds
Started Jul 17 07:59:07 PM PDT 24
Finished Jul 17 08:01:09 PM PDT 24
Peak memory 206668 kb
Host smart-e662b246-3306-4eb0-a19d-8c9fe28b78af
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=146255979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.146255979
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2163138865
Short name T1905
Test name
Test status
Simulation time 162480282 ps
CPU time 0.77 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:06 PM PDT 24
Peak memory 206460 kb
Host smart-06102103-f222-4220-85df-538f5104ac1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
38865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2163138865
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2784114733
Short name T958
Test name
Test status
Simulation time 159322566 ps
CPU time 0.79 seconds
Started Jul 17 07:59:01 PM PDT 24
Finished Jul 17 07:59:03 PM PDT 24
Peak memory 206452 kb
Host smart-c82abb28-95ab-4a4c-9e4f-0c8da43f3c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27841
14733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2784114733
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.333446794
Short name T2501
Test name
Test status
Simulation time 900083992 ps
CPU time 2.03 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:08 PM PDT 24
Peak memory 206636 kb
Host smart-ae9c4117-bdc8-4237-8860-d0fe55bc7688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
6794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.333446794
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.4000872245
Short name T2093
Test name
Test status
Simulation time 5350383614 ps
CPU time 50.77 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206732 kb
Host smart-f46bc03a-4cf3-4ed9-923d-adc459fc8fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40008
72245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.4000872245
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.569519305
Short name T1404
Test name
Test status
Simulation time 86870784 ps
CPU time 0.75 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206452 kb
Host smart-516edf73-2a0d-4987-9f72-d59182e132c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=569519305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.569519305
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1908990825
Short name T2601
Test name
Test status
Simulation time 3441731942 ps
CPU time 4.14 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:31 PM PDT 24
Peak memory 206672 kb
Host smart-21fcc467-5258-4ead-a355-8d1b2c87d259
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1908990825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.1908990825
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.885759522
Short name T2169
Test name
Test status
Simulation time 13412038933 ps
CPU time 12.4 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:53:40 PM PDT 24
Peak memory 206464 kb
Host smart-b1d229b8-5932-4694-8c4e-9cf6644b34e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=885759522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.885759522
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3140892373
Short name T921
Test name
Test status
Simulation time 23377405528 ps
CPU time 30.15 seconds
Started Jul 17 07:53:26 PM PDT 24
Finished Jul 17 07:53:59 PM PDT 24
Peak memory 206524 kb
Host smart-3ce86c18-0276-4269-a3c1-b4926013f0d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3140892373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3140892373
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2678509000
Short name T2209
Test name
Test status
Simulation time 149968275 ps
CPU time 0.76 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206408 kb
Host smart-e19aaa9c-432e-4116-968a-5febb122fb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26785
09000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2678509000
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.468961013
Short name T58
Test name
Test status
Simulation time 183224853 ps
CPU time 0.82 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:53:28 PM PDT 24
Peak memory 206444 kb
Host smart-8a31151a-a0e5-40c9-9f86-bcdc2c5949ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46896
1013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.468961013
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3392638487
Short name T66
Test name
Test status
Simulation time 144525469 ps
CPU time 0.77 seconds
Started Jul 17 07:53:26 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206452 kb
Host smart-cff966db-51e3-4c74-a248-f4118f64a101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33926
38487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3392638487
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1084701058
Short name T1091
Test name
Test status
Simulation time 177264282 ps
CPU time 0.82 seconds
Started Jul 17 07:53:25 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 206460 kb
Host smart-2e52721e-96b6-4aab-9ab4-d762a806e5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10847
01058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1084701058
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1380626193
Short name T534
Test name
Test status
Simulation time 523257978 ps
CPU time 1.59 seconds
Started Jul 17 07:53:26 PM PDT 24
Finished Jul 17 07:53:30 PM PDT 24
Peak memory 206600 kb
Host smart-42cb7a9b-cb01-422c-92a1-bbb5326255b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13806
26193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1380626193
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2400910993
Short name T1104
Test name
Test status
Simulation time 491289167 ps
CPU time 1.44 seconds
Started Jul 17 07:53:21 PM PDT 24
Finished Jul 17 07:53:24 PM PDT 24
Peak memory 206452 kb
Host smart-7acc42a9-c008-44d1-a265-8c1d3f43cfce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24009
10993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2400910993
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2223185890
Short name T1559
Test name
Test status
Simulation time 13472504402 ps
CPU time 23.19 seconds
Started Jul 17 07:53:24 PM PDT 24
Finished Jul 17 07:53:50 PM PDT 24
Peak memory 206696 kb
Host smart-0a730787-f811-40cb-b409-6bd08a4b0b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22231
85890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2223185890
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3729825741
Short name T324
Test name
Test status
Simulation time 507459845 ps
CPU time 1.52 seconds
Started Jul 17 07:53:55 PM PDT 24
Finished Jul 17 07:53:58 PM PDT 24
Peak memory 206424 kb
Host smart-3ae355cc-26cf-483f-ba1a-2ae5f726f03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37298
25741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3729825741
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.750550374
Short name T444
Test name
Test status
Simulation time 139999942 ps
CPU time 0.79 seconds
Started Jul 17 07:53:55 PM PDT 24
Finished Jul 17 07:53:57 PM PDT 24
Peak memory 206464 kb
Host smart-72719ae9-6acd-4894-93fb-8eab00442c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75055
0374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.750550374
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3379699906
Short name T2018
Test name
Test status
Simulation time 39488807 ps
CPU time 0.71 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206440 kb
Host smart-813663ce-6642-494f-9c15-ed99e82a3df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33796
99906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3379699906
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.994203030
Short name T1229
Test name
Test status
Simulation time 776942768 ps
CPU time 1.95 seconds
Started Jul 17 07:53:57 PM PDT 24
Finished Jul 17 07:54:02 PM PDT 24
Peak memory 206540 kb
Host smart-94b45a68-322f-407e-9532-22b476f70678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99420
3030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.994203030
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.340092544
Short name T1245
Test name
Test status
Simulation time 198706086 ps
CPU time 1.5 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:04 PM PDT 24
Peak memory 206768 kb
Host smart-7258da21-fca4-4d92-9f13-ad771fc75a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34009
2544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.340092544
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.2324061458
Short name T1150
Test name
Test status
Simulation time 86185030497 ps
CPU time 124.96 seconds
Started Jul 17 07:53:54 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206624 kb
Host smart-8ae030da-5bc9-482c-82ab-de0a18ded2c7
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2324061458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.2324061458
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.1233307869
Short name T2602
Test name
Test status
Simulation time 94318936049 ps
CPU time 120.25 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:55:59 PM PDT 24
Peak memory 206720 kb
Host smart-6bfbf62f-e9fe-4b92-8426-6ab6066d421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233307869 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.1233307869
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.908741319
Short name T1542
Test name
Test status
Simulation time 121115239945 ps
CPU time 156.33 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:56:35 PM PDT 24
Peak memory 206724 kb
Host smart-b59a68ae-eb5e-4eef-a40c-5be4d0d16928
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=908741319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.908741319
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.974563715
Short name T1942
Test name
Test status
Simulation time 99171930967 ps
CPU time 131.3 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:56:09 PM PDT 24
Peak memory 206660 kb
Host smart-8790191f-0617-44e8-acee-a367e050e002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974563715 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.974563715
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.775905329
Short name T474
Test name
Test status
Simulation time 92117208721 ps
CPU time 143.84 seconds
Started Jul 17 07:53:54 PM PDT 24
Finished Jul 17 07:56:19 PM PDT 24
Peak memory 206676 kb
Host smart-a2fe6b4b-a654-4267-af98-a0e4cae38bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77590
5329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.775905329
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1416338244
Short name T2711
Test name
Test status
Simulation time 178293540 ps
CPU time 0.8 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:02 PM PDT 24
Peak memory 206408 kb
Host smart-35be1801-fd48-4fcb-931c-1afd8fe2885e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14163
38244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1416338244
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2782568045
Short name T201
Test name
Test status
Simulation time 165769328 ps
CPU time 0.82 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:00 PM PDT 24
Peak memory 206456 kb
Host smart-db1a639e-aad9-459e-b0ec-470fdaaadac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27825
68045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2782568045
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3737501775
Short name T469
Test name
Test status
Simulation time 176712573 ps
CPU time 0.86 seconds
Started Jul 17 07:54:14 PM PDT 24
Finished Jul 17 07:54:18 PM PDT 24
Peak memory 206444 kb
Host smart-50bacfcd-11f7-4ab2-a2f9-695ffbf2f943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37375
01775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3737501775
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.1535378947
Short name T1612
Test name
Test status
Simulation time 6753812594 ps
CPU time 21.31 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:24 PM PDT 24
Peak memory 206656 kb
Host smart-beb503bd-8f12-4b04-96f3-14c9b42954d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15353
78947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.1535378947
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2071704989
Short name T2337
Test name
Test status
Simulation time 179294667 ps
CPU time 0.83 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:54:06 PM PDT 24
Peak memory 206436 kb
Host smart-a012888a-3081-443d-b1c2-9c5479ef80eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20717
04989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2071704989
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3844824911
Short name T2733
Test name
Test status
Simulation time 23299180088 ps
CPU time 24.98 seconds
Started Jul 17 07:53:55 PM PDT 24
Finished Jul 17 07:54:21 PM PDT 24
Peak memory 206492 kb
Host smart-00fa4a32-1e15-43bf-8514-bbd95474d66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38448
24911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3844824911
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2855857361
Short name T1408
Test name
Test status
Simulation time 3308895521 ps
CPU time 3.71 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:07 PM PDT 24
Peak memory 206520 kb
Host smart-a4b25d32-a093-473a-a48e-82eb42766d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28558
57361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2855857361
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1501798669
Short name T1246
Test name
Test status
Simulation time 7653021863 ps
CPU time 211.79 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:57:35 PM PDT 24
Peak memory 206732 kb
Host smart-642698d3-0565-4390-ae96-c4f797824835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15017
98669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1501798669
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3341104584
Short name T1680
Test name
Test status
Simulation time 4971758230 ps
CPU time 46.79 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:50 PM PDT 24
Peak memory 206660 kb
Host smart-743b6289-e8d9-4386-ac27-18c2956a7ccd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3341104584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3341104584
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2666128983
Short name T707
Test name
Test status
Simulation time 234368949 ps
CPU time 0.93 seconds
Started Jul 17 07:53:54 PM PDT 24
Finished Jul 17 07:53:56 PM PDT 24
Peak memory 206452 kb
Host smart-03e77b17-537f-4ce4-9a2b-d18f47e90a47
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2666128983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2666128983
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.4126837337
Short name T823
Test name
Test status
Simulation time 231829476 ps
CPU time 0.88 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:53:58 PM PDT 24
Peak memory 206416 kb
Host smart-b4639a45-86da-4d9d-b4f7-001c651a7d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41268
37337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4126837337
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1314665215
Short name T421
Test name
Test status
Simulation time 3623078111 ps
CPU time 98.34 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:55:43 PM PDT 24
Peak memory 206684 kb
Host smart-0dd3a465-84c4-4997-a6f9-aa5a70d2735c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13146
65215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1314665215
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3096378480
Short name T1478
Test name
Test status
Simulation time 7487312251 ps
CPU time 51.82 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:54 PM PDT 24
Peak memory 206664 kb
Host smart-6f889a78-59fe-4c77-b9cd-d4046b2bc11e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3096378480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3096378480
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3278879204
Short name T1932
Test name
Test status
Simulation time 151691896 ps
CPU time 0.79 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:53:58 PM PDT 24
Peak memory 206468 kb
Host smart-d03a7667-7790-4f05-848f-c401a305037f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3278879204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3278879204
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1272074772
Short name T709
Test name
Test status
Simulation time 140968462 ps
CPU time 0.77 seconds
Started Jul 17 07:53:57 PM PDT 24
Finished Jul 17 07:54:01 PM PDT 24
Peak memory 206348 kb
Host smart-386c25e9-618b-4f4a-aab7-7707fcf580be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12720
74772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1272074772
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2056381406
Short name T2275
Test name
Test status
Simulation time 216230734 ps
CPU time 0.86 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:53:59 PM PDT 24
Peak memory 206472 kb
Host smart-6587c7ce-f325-48d0-9b8e-0fbdcea1c824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20563
81406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2056381406
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2000296307
Short name T1461
Test name
Test status
Simulation time 147095692 ps
CPU time 0.87 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:05 PM PDT 24
Peak memory 206444 kb
Host smart-605d5e7a-66cc-44d8-8c73-82765e531329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20002
96307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2000296307
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3017405787
Short name T991
Test name
Test status
Simulation time 235162572 ps
CPU time 0.94 seconds
Started Jul 17 07:53:57 PM PDT 24
Finished Jul 17 07:54:01 PM PDT 24
Peak memory 206324 kb
Host smart-4151e398-b236-4e5f-ba34-7478e7761499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30174
05787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3017405787
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1291467664
Short name T2340
Test name
Test status
Simulation time 160073650 ps
CPU time 0.82 seconds
Started Jul 17 07:53:57 PM PDT 24
Finished Jul 17 07:54:02 PM PDT 24
Peak memory 206444 kb
Host smart-e28aa4f1-91f7-4ecc-9f39-f2eb633ab95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12914
67664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1291467664
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3540574910
Short name T2349
Test name
Test status
Simulation time 155614062 ps
CPU time 0.81 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:00 PM PDT 24
Peak memory 206456 kb
Host smart-08759b9d-14e9-48d1-8382-0f20ff44b670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35405
74910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3540574910
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.1534272149
Short name T2363
Test name
Test status
Simulation time 248579477 ps
CPU time 1.02 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:53:59 PM PDT 24
Peak memory 206416 kb
Host smart-a3299638-9c3b-4125-8d3d-8d78324b19fa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1534272149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.1534272149
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3951969628
Short name T192
Test name
Test status
Simulation time 243390777 ps
CPU time 1.03 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:04 PM PDT 24
Peak memory 206444 kb
Host smart-8a1b3056-3e8e-4bbf-9749-3ba8dc146da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39519
69628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3951969628
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.4125714640
Short name T1295
Test name
Test status
Simulation time 197468682 ps
CPU time 0.87 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:02 PM PDT 24
Peak memory 206408 kb
Host smart-449fc136-a7f9-4a92-93d7-cf29310d95f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
14640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.4125714640
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1026684412
Short name T2522
Test name
Test status
Simulation time 31476163 ps
CPU time 0.64 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:00 PM PDT 24
Peak memory 206424 kb
Host smart-30a78c6b-fa63-418d-bd6a-ca079afbd135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10266
84412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1026684412
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1190888643
Short name T1422
Test name
Test status
Simulation time 18859180947 ps
CPU time 41.94 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:41 PM PDT 24
Peak memory 206704 kb
Host smart-3c806028-459d-4866-a789-1aac0fd45429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11908
88643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1190888643
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1912889750
Short name T1118
Test name
Test status
Simulation time 170250536 ps
CPU time 0.85 seconds
Started Jul 17 07:53:53 PM PDT 24
Finished Jul 17 07:53:55 PM PDT 24
Peak memory 206448 kb
Host smart-4591954c-8ec6-49b2-8a3b-1256917ae855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19128
89750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1912889750
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.278020332
Short name T895
Test name
Test status
Simulation time 233044834 ps
CPU time 0.89 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:05 PM PDT 24
Peak memory 206452 kb
Host smart-e1e6afc4-2751-4e8c-afac-2b05182eb4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27802
0332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.278020332
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.707052055
Short name T153
Test name
Test status
Simulation time 10499969186 ps
CPU time 51.92 seconds
Started Jul 17 07:53:55 PM PDT 24
Finished Jul 17 07:54:49 PM PDT 24
Peak memory 206736 kb
Host smart-19ff3e83-f4fd-4d7b-a05f-f2a495032367
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=707052055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.707052055
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.4249665181
Short name T162
Test name
Test status
Simulation time 8191600609 ps
CPU time 50.14 seconds
Started Jul 17 07:53:55 PM PDT 24
Finished Jul 17 07:54:46 PM PDT 24
Peak memory 206764 kb
Host smart-f3ebe8db-1926-44f2-976f-3b464eb7775d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4249665181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.4249665181
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3173620941
Short name T648
Test name
Test status
Simulation time 7785890085 ps
CPU time 32.28 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:35 PM PDT 24
Peak memory 206676 kb
Host smart-fedca4d9-3585-464e-9735-fdf6ed71e93d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3173620941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3173620941
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3560932964
Short name T1042
Test name
Test status
Simulation time 183409455 ps
CPU time 0.8 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:53:58 PM PDT 24
Peak memory 206476 kb
Host smart-8d082a67-ee82-48f8-96f5-2b5d984e368c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35609
32964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3560932964
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3614801257
Short name T312
Test name
Test status
Simulation time 173310706 ps
CPU time 0.76 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:53:59 PM PDT 24
Peak memory 206452 kb
Host smart-922ec99c-be01-4e60-bb11-93be36b641a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36148
01257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3614801257
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1619709144
Short name T2047
Test name
Test status
Simulation time 143022658 ps
CPU time 0.78 seconds
Started Jul 17 07:53:55 PM PDT 24
Finished Jul 17 07:53:57 PM PDT 24
Peak memory 206448 kb
Host smart-86f7372c-6566-469e-b979-5b83ac072a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16197
09144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1619709144
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2230444001
Short name T2637
Test name
Test status
Simulation time 197989195 ps
CPU time 0.81 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:00 PM PDT 24
Peak memory 206432 kb
Host smart-fe6d7b29-f555-4c99-b7f6-75e61096333b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22304
44001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2230444001
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2258343065
Short name T199
Test name
Test status
Simulation time 950464890 ps
CPU time 1.78 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:10 PM PDT 24
Peak memory 224084 kb
Host smart-a7f04648-d023-47c3-9a4c-7c18cd98c436
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2258343065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2258343065
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.3966497788
Short name T174
Test name
Test status
Simulation time 206397633 ps
CPU time 0.85 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:05 PM PDT 24
Peak memory 206444 kb
Host smart-4c13a2ba-986c-434e-bf49-97bd859057bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
97788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.3966497788
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1401208335
Short name T2474
Test name
Test status
Simulation time 191652748 ps
CPU time 0.78 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:53:59 PM PDT 24
Peak memory 206396 kb
Host smart-4799c9f0-4a77-4d31-86cf-f9db2a9b4995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14012
08335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1401208335
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2266454696
Short name T1958
Test name
Test status
Simulation time 148951577 ps
CPU time 0.77 seconds
Started Jul 17 07:53:55 PM PDT 24
Finished Jul 17 07:53:57 PM PDT 24
Peak memory 206444 kb
Host smart-8a7fc53b-81f1-4ad4-9753-41d1ee42f2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22664
54696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2266454696
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1523639518
Short name T459
Test name
Test status
Simulation time 221450095 ps
CPU time 0.9 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:53:58 PM PDT 24
Peak memory 206416 kb
Host smart-9c9c26f6-c61e-4791-a8f4-9e9f4e5d6ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15236
39518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1523639518
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.224545040
Short name T2667
Test name
Test status
Simulation time 5996480414 ps
CPU time 55.01 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:55:00 PM PDT 24
Peak memory 206672 kb
Host smart-e2aeb9ab-eb2b-4c2b-9d4f-8f2f11129e24
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=224545040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.224545040
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3630339624
Short name T960
Test name
Test status
Simulation time 166087674 ps
CPU time 0.8 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:00 PM PDT 24
Peak memory 206456 kb
Host smart-7542d0e4-581d-4e7a-b7f1-93d62a0fe257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
39624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3630339624
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2622412220
Short name T1946
Test name
Test status
Simulation time 182132276 ps
CPU time 0.85 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:04 PM PDT 24
Peak memory 206580 kb
Host smart-fcf7f1d3-e59b-4640-b780-242392a2e71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26224
12220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2622412220
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2778664503
Short name T1493
Test name
Test status
Simulation time 882685164 ps
CPU time 1.87 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:06 PM PDT 24
Peak memory 206580 kb
Host smart-b8e65c6e-1e2c-4148-be6e-c814897ef88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
64503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2778664503
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1077132206
Short name T1276
Test name
Test status
Simulation time 6542853723 ps
CPU time 48.81 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:48 PM PDT 24
Peak memory 206716 kb
Host smart-8adfcce7-c64d-4f5f-ac30-ba145d9c07ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10771
32206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1077132206
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1974126980
Short name T2454
Test name
Test status
Simulation time 12611423933 ps
CPU time 313.63 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206704 kb
Host smart-a280d89c-07be-4e44-98e3-c95b690fe51e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1974126980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1974126980
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3738599138
Short name T1429
Test name
Test status
Simulation time 82799117 ps
CPU time 0.69 seconds
Started Jul 17 07:59:06 PM PDT 24
Finished Jul 17 07:59:11 PM PDT 24
Peak memory 206424 kb
Host smart-b6181797-25d7-4779-8ad5-9b831d1e1cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3738599138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3738599138
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3447209618
Short name T15
Test name
Test status
Simulation time 4440897991 ps
CPU time 5.21 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:12 PM PDT 24
Peak memory 206648 kb
Host smart-db5195bd-c205-4329-a06f-2d6213fd1d01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3447209618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.3447209618
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1005985081
Short name T2382
Test name
Test status
Simulation time 13338081725 ps
CPU time 14.06 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:20 PM PDT 24
Peak memory 206536 kb
Host smart-cd27fb9b-8542-4df0-b541-3484519d57fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1005985081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1005985081
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.4073963744
Short name T633
Test name
Test status
Simulation time 23301637301 ps
CPU time 24.56 seconds
Started Jul 17 07:59:02 PM PDT 24
Finished Jul 17 07:59:30 PM PDT 24
Peak memory 206688 kb
Host smart-ed81ef5a-cbee-40da-ac1e-2d090772473a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4073963744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.4073963744
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2061865784
Short name T2244
Test name
Test status
Simulation time 176205368 ps
CPU time 0.81 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206444 kb
Host smart-1254bbaa-305c-4d2d-9480-16e9050e4047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20618
65784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2061865784
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1732222931
Short name T2394
Test name
Test status
Simulation time 232731668 ps
CPU time 0.86 seconds
Started Jul 17 07:59:03 PM PDT 24
Finished Jul 17 07:59:07 PM PDT 24
Peak memory 206456 kb
Host smart-d223cfd1-bb46-449a-bfa0-b6810a7a2dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17322
22931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1732222931
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.4230908456
Short name T1798
Test name
Test status
Simulation time 175795118 ps
CPU time 0.81 seconds
Started Jul 17 07:59:05 PM PDT 24
Finished Jul 17 07:59:10 PM PDT 24
Peak memory 206448 kb
Host smart-d42adaf6-2f6f-4794-969a-456d199d2b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42309
08456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.4230908456
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.539872263
Short name T585
Test name
Test status
Simulation time 856763280 ps
CPU time 2.05 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:10 PM PDT 24
Peak memory 206656 kb
Host smart-e03e2bb9-8b7f-432a-a471-0ffeff42979c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53987
2263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.539872263
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3449185241
Short name T1919
Test name
Test status
Simulation time 6073378544 ps
CPU time 13.01 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:27 PM PDT 24
Peak memory 206576 kb
Host smart-051b6ce3-f61a-47ea-91b4-a48c72a3f009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
85241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3449185241
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.181838388
Short name T2033
Test name
Test status
Simulation time 531619434 ps
CPU time 1.52 seconds
Started Jul 17 07:59:07 PM PDT 24
Finished Jul 17 07:59:12 PM PDT 24
Peak memory 206468 kb
Host smart-3614347f-07f4-404d-b7cc-6f9f6fbb8cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
8388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.181838388
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.77120517
Short name T204
Test name
Test status
Simulation time 157370177 ps
CPU time 0.76 seconds
Started Jul 17 07:59:06 PM PDT 24
Finished Jul 17 07:59:11 PM PDT 24
Peak memory 206468 kb
Host smart-15728e86-b73b-4a38-be42-aaae8182c9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77120
517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.77120517
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2548515431
Short name T1701
Test name
Test status
Simulation time 37311253 ps
CPU time 0.64 seconds
Started Jul 17 07:59:08 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206432 kb
Host smart-362cc172-1ccf-4819-a189-ccbe14824b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25485
15431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2548515431
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.4016057945
Short name T674
Test name
Test status
Simulation time 727749964 ps
CPU time 1.73 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:14 PM PDT 24
Peak memory 206636 kb
Host smart-0983dda6-3904-4a18-b456-df5f98b4eb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40160
57945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.4016057945
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2994360027
Short name T2393
Test name
Test status
Simulation time 351537390 ps
CPU time 2.35 seconds
Started Jul 17 07:59:06 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206660 kb
Host smart-8eb776b0-5626-47b0-977c-26e7672b846c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29943
60027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2994360027
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.717513157
Short name T1426
Test name
Test status
Simulation time 210915934 ps
CPU time 0.89 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206408 kb
Host smart-f8a410bb-8ab5-4c87-b006-37a684373e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71751
3157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.717513157
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.303454682
Short name T1006
Test name
Test status
Simulation time 148354151 ps
CPU time 0.81 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206444 kb
Host smart-d7cd8c5d-aca2-40c8-a669-526e0d741893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345
4682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.303454682
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.319208995
Short name T926
Test name
Test status
Simulation time 199353252 ps
CPU time 0.86 seconds
Started Jul 17 07:59:11 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206452 kb
Host smart-f55e5c58-53fc-4c69-9132-cc0be49fa206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31920
8995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.319208995
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.1593043838
Short name T1759
Test name
Test status
Simulation time 6119108978 ps
CPU time 24.2 seconds
Started Jul 17 07:59:12 PM PDT 24
Finished Jul 17 07:59:39 PM PDT 24
Peak memory 206660 kb
Host smart-bc59f571-4fac-46df-8371-e8ae89404c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15930
43838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1593043838
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.767423406
Short name T1658
Test name
Test status
Simulation time 244477081 ps
CPU time 0.94 seconds
Started Jul 17 07:59:12 PM PDT 24
Finished Jul 17 07:59:16 PM PDT 24
Peak memory 206448 kb
Host smart-f7bf3e4c-7942-4e91-b007-72b1a3b27ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76742
3406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.767423406
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1332925110
Short name T721
Test name
Test status
Simulation time 23349026261 ps
CPU time 22.17 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:36 PM PDT 24
Peak memory 206504 kb
Host smart-34b075e3-d4ba-4dd8-8e46-a3cb60f310a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13329
25110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1332925110
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3726512248
Short name T2459
Test name
Test status
Simulation time 3262620722 ps
CPU time 4.23 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:17 PM PDT 24
Peak memory 206468 kb
Host smart-bf246815-9e4b-4c49-894a-ffa9d921b12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37265
12248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3726512248
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.729322711
Short name T1388
Test name
Test status
Simulation time 12009957310 ps
CPU time 341.11 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 08:04:55 PM PDT 24
Peak memory 206680 kb
Host smart-7d3217e6-47ec-4efb-b8e0-7107b936d662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72932
2711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.729322711
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1485727311
Short name T2513
Test name
Test status
Simulation time 3525620187 ps
CPU time 33.11 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:47 PM PDT 24
Peak memory 206712 kb
Host smart-afd6f076-68d2-460b-b810-fa24c27e47e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1485727311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1485727311
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.4046047437
Short name T1304
Test name
Test status
Simulation time 249752631 ps
CPU time 0.87 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:14 PM PDT 24
Peak memory 206448 kb
Host smart-a7d68426-141f-4baf-befa-3d04c9ca0975
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4046047437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.4046047437
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1719494894
Short name T1892
Test name
Test status
Simulation time 185624658 ps
CPU time 0.86 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:14 PM PDT 24
Peak memory 206452 kb
Host smart-79839368-db74-4ac8-a2ea-9e0b3cd300ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17194
94894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1719494894
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.284519863
Short name T1760
Test name
Test status
Simulation time 3080190574 ps
CPU time 87.18 seconds
Started Jul 17 07:59:12 PM PDT 24
Finished Jul 17 08:00:42 PM PDT 24
Peak memory 206664 kb
Host smart-02066e1e-0cf1-4902-a3ec-f0bb76f0d450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28451
9863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.284519863
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2929079352
Short name T2620
Test name
Test status
Simulation time 3393561821 ps
CPU time 95.41 seconds
Started Jul 17 07:59:12 PM PDT 24
Finished Jul 17 08:00:51 PM PDT 24
Peak memory 206680 kb
Host smart-51b87be0-db23-4a04-b5e9-c99bf5a0cf90
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2929079352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2929079352
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2914102346
Short name T1248
Test name
Test status
Simulation time 160727667 ps
CPU time 0.79 seconds
Started Jul 17 07:59:11 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206448 kb
Host smart-407bea7d-8178-446c-916f-6259a190c6e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2914102346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2914102346
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2844788287
Short name T1498
Test name
Test status
Simulation time 149082059 ps
CPU time 0.75 seconds
Started Jul 17 07:59:12 PM PDT 24
Finished Jul 17 07:59:16 PM PDT 24
Peak memory 206452 kb
Host smart-cd68d080-9817-40b4-aeaa-3139e9eb35eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28447
88287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2844788287
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3001898938
Short name T2352
Test name
Test status
Simulation time 197263292 ps
CPU time 0.86 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:14 PM PDT 24
Peak memory 206452 kb
Host smart-51801fc1-59b0-41bb-b0d4-e88952f7d867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30018
98938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3001898938
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3371742749
Short name T1538
Test name
Test status
Simulation time 182896322 ps
CPU time 0.79 seconds
Started Jul 17 07:59:06 PM PDT 24
Finished Jul 17 07:59:11 PM PDT 24
Peak memory 206540 kb
Host smart-ecdfd5df-11a5-4382-bb69-3f977e86884d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33717
42749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3371742749
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1215527961
Short name T2009
Test name
Test status
Simulation time 212964160 ps
CPU time 0.82 seconds
Started Jul 17 07:59:06 PM PDT 24
Finished Jul 17 07:59:11 PM PDT 24
Peak memory 206536 kb
Host smart-6a955ed9-015b-4dd4-ab3d-f574217396a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12155
27961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1215527961
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4102566200
Short name T1325
Test name
Test status
Simulation time 207100189 ps
CPU time 0.89 seconds
Started Jul 17 07:59:11 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206464 kb
Host smart-6ce6e7a5-dc3d-4b8b-bb5f-18aeef98e8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41025
66200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4102566200
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.675580123
Short name T1285
Test name
Test status
Simulation time 236911487 ps
CPU time 0.93 seconds
Started Jul 17 07:59:11 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206468 kb
Host smart-ba50a681-c52b-483d-8a74-3ae78aefed56
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=675580123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.675580123
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1231410239
Short name T1797
Test name
Test status
Simulation time 157918872 ps
CPU time 0.75 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206452 kb
Host smart-6cab3774-8890-4727-a88c-2fa7a8a619f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12314
10239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1231410239
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2493670233
Short name T1751
Test name
Test status
Simulation time 57864131 ps
CPU time 0.66 seconds
Started Jul 17 07:59:11 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206432 kb
Host smart-e04a722a-4ee4-49c3-80a9-e8ea70b8ed59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24936
70233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2493670233
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1731620010
Short name T763
Test name
Test status
Simulation time 14261935791 ps
CPU time 32.12 seconds
Started Jul 17 07:59:11 PM PDT 24
Finished Jul 17 07:59:47 PM PDT 24
Peak memory 206740 kb
Host smart-8b548874-dafe-46cb-945f-394cdd2b04b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17316
20010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1731620010
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2022711246
Short name T278
Test name
Test status
Simulation time 197172888 ps
CPU time 0.88 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206452 kb
Host smart-74701444-d148-44d3-a0c6-ac3d94b0810c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20227
11246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2022711246
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4125130067
Short name T2354
Test name
Test status
Simulation time 228849075 ps
CPU time 0.86 seconds
Started Jul 17 07:59:08 PM PDT 24
Finished Jul 17 07:59:12 PM PDT 24
Peak memory 206456 kb
Host smart-6bcd4a89-8e83-439a-9ac5-07140d9dfcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41251
30067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4125130067
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.348911136
Short name T1910
Test name
Test status
Simulation time 165498448 ps
CPU time 0.77 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:14 PM PDT 24
Peak memory 206464 kb
Host smart-e6a8949e-04bd-4428-ac1d-5a7db4a8ae73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34891
1136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.348911136
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.342846605
Short name T973
Test name
Test status
Simulation time 202073735 ps
CPU time 0.82 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206452 kb
Host smart-3d2469d7-fe83-4101-b796-084598d74a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34284
6605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.342846605
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.536422655
Short name T2128
Test name
Test status
Simulation time 177242322 ps
CPU time 0.9 seconds
Started Jul 17 07:59:08 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206452 kb
Host smart-9cef18b0-39c3-458a-a0d2-921956866412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53642
2655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.536422655
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2968948807
Short name T1354
Test name
Test status
Simulation time 154545367 ps
CPU time 0.74 seconds
Started Jul 17 07:59:11 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206460 kb
Host smart-2924f7de-6eb1-4c7e-a834-f44a52089f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29689
48807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2968948807
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3389988523
Short name T520
Test name
Test status
Simulation time 149428312 ps
CPU time 0.78 seconds
Started Jul 17 07:59:05 PM PDT 24
Finished Jul 17 07:59:10 PM PDT 24
Peak memory 206448 kb
Host smart-b5e9e5c9-ea0e-4d0b-870f-95ff5dae3c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
88523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3389988523
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1438886036
Short name T2242
Test name
Test status
Simulation time 294237102 ps
CPU time 1.03 seconds
Started Jul 17 07:59:05 PM PDT 24
Finished Jul 17 07:59:10 PM PDT 24
Peak memory 206464 kb
Host smart-c01010da-8d4a-4ee6-ae64-8f446d1adcd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14388
86036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1438886036
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1700355821
Short name T878
Test name
Test status
Simulation time 4313338465 ps
CPU time 31.87 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:40 PM PDT 24
Peak memory 206732 kb
Host smart-34b8d750-a712-471b-b958-3633565cf77f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1700355821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1700355821
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2422928479
Short name T2687
Test name
Test status
Simulation time 167434098 ps
CPU time 0.8 seconds
Started Jul 17 07:59:07 PM PDT 24
Finished Jul 17 07:59:12 PM PDT 24
Peak memory 206440 kb
Host smart-0311edf7-ec1c-47ac-848f-22ce95409a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24229
28479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2422928479
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1957700825
Short name T1197
Test name
Test status
Simulation time 223630948 ps
CPU time 0.91 seconds
Started Jul 17 07:59:04 PM PDT 24
Finished Jul 17 07:59:09 PM PDT 24
Peak memory 206464 kb
Host smart-6cd6c2f3-b6af-43a7-8574-5c5678e43084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19577
00825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1957700825
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3872247009
Short name T624
Test name
Test status
Simulation time 615805293 ps
CPU time 1.46 seconds
Started Jul 17 07:59:05 PM PDT 24
Finished Jul 17 07:59:11 PM PDT 24
Peak memory 206452 kb
Host smart-f9328e10-7468-44d1-9a4f-4242a862ba44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38722
47009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3872247009
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2666259720
Short name T1502
Test name
Test status
Simulation time 4414301749 ps
CPU time 32.35 seconds
Started Jul 17 07:59:05 PM PDT 24
Finished Jul 17 07:59:42 PM PDT 24
Peak memory 206720 kb
Host smart-b73db008-de1d-4dd6-ba07-81baf0218542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26662
59720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2666259720
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.4251032342
Short name T2455
Test name
Test status
Simulation time 50704432 ps
CPU time 0.68 seconds
Started Jul 17 07:59:42 PM PDT 24
Finished Jul 17 07:59:45 PM PDT 24
Peak memory 206424 kb
Host smart-44454e92-d879-4c98-8d92-1a51fb863689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4251032342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.4251032342
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.445119514
Short name T2282
Test name
Test status
Simulation time 3457595039 ps
CPU time 5.01 seconds
Started Jul 17 07:59:05 PM PDT 24
Finished Jul 17 07:59:14 PM PDT 24
Peak memory 206688 kb
Host smart-6915446f-2a4c-46fd-adfb-f9641b704886
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=445119514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.445119514
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2432679275
Short name T2015
Test name
Test status
Simulation time 13436144922 ps
CPU time 13.79 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:26 PM PDT 24
Peak memory 206656 kb
Host smart-dcc97c9a-ee1a-4b71-8ac7-719d7d8b9e66
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2432679275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2432679275
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1577930897
Short name T2588
Test name
Test status
Simulation time 23371990777 ps
CPU time 28.14 seconds
Started Jul 17 07:59:06 PM PDT 24
Finished Jul 17 07:59:38 PM PDT 24
Peak memory 206520 kb
Host smart-1d162456-3c12-499a-8812-9ae924f29d26
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1577930897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.1577930897
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.898402382
Short name T1139
Test name
Test status
Simulation time 190483158 ps
CPU time 0.86 seconds
Started Jul 17 07:59:06 PM PDT 24
Finished Jul 17 07:59:11 PM PDT 24
Peak memory 206460 kb
Host smart-2a938edf-89c7-4a9d-867f-15d3c7bd1ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89840
2382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.898402382
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.741462235
Short name T597
Test name
Test status
Simulation time 170746408 ps
CPU time 0.76 seconds
Started Jul 17 07:59:09 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 206444 kb
Host smart-d3b6a295-268d-4779-8a30-3c8ba7f67fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74146
2235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.741462235
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1426007313
Short name T2301
Test name
Test status
Simulation time 266618759 ps
CPU time 1.01 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:14 PM PDT 24
Peak memory 206436 kb
Host smart-0d8573db-f031-41ca-b01d-ddbbbcfab098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14260
07313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1426007313
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3603982333
Short name T1156
Test name
Test status
Simulation time 630581773 ps
CPU time 1.6 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206456 kb
Host smart-7a2029ba-b3bd-439e-a0a4-da4c41bf703d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36039
82333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3603982333
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.565366447
Short name T1361
Test name
Test status
Simulation time 460269570 ps
CPU time 1.4 seconds
Started Jul 17 07:59:11 PM PDT 24
Finished Jul 17 07:59:16 PM PDT 24
Peak memory 206456 kb
Host smart-37964c67-371b-4e32-8701-fe607bd2c2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56536
6447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.565366447
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.914896811
Short name T780
Test name
Test status
Simulation time 171063445 ps
CPU time 0.79 seconds
Started Jul 17 07:59:10 PM PDT 24
Finished Jul 17 07:59:15 PM PDT 24
Peak memory 206456 kb
Host smart-04eb4404-6266-4bee-8122-c7c32e385c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91489
6811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.914896811
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3156833954
Short name T1236
Test name
Test status
Simulation time 31315274 ps
CPU time 0.63 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 07:59:45 PM PDT 24
Peak memory 206376 kb
Host smart-e5d88af9-6f6d-4409-9224-cca84bc105ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31568
33954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3156833954
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1896500205
Short name T850
Test name
Test status
Simulation time 931591707 ps
CPU time 2.37 seconds
Started Jul 17 07:59:41 PM PDT 24
Finished Jul 17 07:59:44 PM PDT 24
Peak memory 206604 kb
Host smart-7d7fd0b4-ae24-4f8c-91cc-392dc1d0949d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18965
00205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1896500205
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2502992827
Short name T2508
Test name
Test status
Simulation time 230080252 ps
CPU time 1.29 seconds
Started Jul 17 07:59:50 PM PDT 24
Finished Jul 17 07:59:59 PM PDT 24
Peak memory 206572 kb
Host smart-8035d33c-6c25-41bb-bf29-3dacd2f5ebcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25029
92827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2502992827
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1420679429
Short name T1981
Test name
Test status
Simulation time 238746959 ps
CPU time 0.89 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 07:59:46 PM PDT 24
Peak memory 206448 kb
Host smart-8b3476b2-20b4-47c4-a7eb-d99066fa30be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14206
79429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1420679429
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1300633629
Short name T2327
Test name
Test status
Simulation time 178661426 ps
CPU time 0.79 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206448 kb
Host smart-b1b266d2-fb61-467c-b4a0-e4af7a82f649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13006
33629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1300633629
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3645668083
Short name T2158
Test name
Test status
Simulation time 239408204 ps
CPU time 0.91 seconds
Started Jul 17 07:59:51 PM PDT 24
Finished Jul 17 08:00:00 PM PDT 24
Peak memory 206280 kb
Host smart-5259f13b-59c7-4559-8436-32916f515f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36456
68083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3645668083
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.2690861324
Short name T2116
Test name
Test status
Simulation time 9161857206 ps
CPU time 257.34 seconds
Started Jul 17 07:59:40 PM PDT 24
Finished Jul 17 08:03:58 PM PDT 24
Peak memory 206692 kb
Host smart-717368a7-1a2d-4bd9-9a0b-ddf343a90789
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2690861324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.2690861324
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.301232713
Short name T1952
Test name
Test status
Simulation time 184219292 ps
CPU time 0.82 seconds
Started Jul 17 07:59:41 PM PDT 24
Finished Jul 17 07:59:43 PM PDT 24
Peak memory 206444 kb
Host smart-0d027386-02f7-47ef-a057-b80981484197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30123
2713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.301232713
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3426267592
Short name T1211
Test name
Test status
Simulation time 23351068602 ps
CPU time 23.57 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 08:00:14 PM PDT 24
Peak memory 206488 kb
Host smart-b03535c5-871f-446f-ae6e-47ac396c33be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34262
67592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3426267592
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.4040103895
Short name T1719
Test name
Test status
Simulation time 3358225701 ps
CPU time 3.96 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206500 kb
Host smart-9754435d-d8e0-4ef6-a249-7691f9c7fdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40401
03895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.4040103895
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2489716684
Short name T2294
Test name
Test status
Simulation time 7963031992 ps
CPU time 75.52 seconds
Started Jul 17 07:59:41 PM PDT 24
Finished Jul 17 08:00:58 PM PDT 24
Peak memory 206672 kb
Host smart-eb37f438-52b9-409d-be14-e6ae5c0a91c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
16684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2489716684
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.3341526640
Short name T2295
Test name
Test status
Simulation time 3271400866 ps
CPU time 32.06 seconds
Started Jul 17 07:59:41 PM PDT 24
Finished Jul 17 08:00:14 PM PDT 24
Peak memory 206704 kb
Host smart-cde51bbd-364f-4735-98d8-1355d97fddf4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3341526640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.3341526640
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.435335042
Short name T2019
Test name
Test status
Simulation time 243106900 ps
CPU time 0.85 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 07:59:46 PM PDT 24
Peak memory 206452 kb
Host smart-929e5aaf-2982-4df0-9269-35c078250d2e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=435335042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.435335042
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.431785870
Short name T1586
Test name
Test status
Simulation time 233522016 ps
CPU time 0.89 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206368 kb
Host smart-7e571642-56e9-4755-877f-b8e807d2aea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43178
5870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.431785870
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2200890949
Short name T621
Test name
Test status
Simulation time 5118372239 ps
CPU time 47.65 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206728 kb
Host smart-38c058e2-d8a7-4048-a014-a7b51cbb901d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22008
90949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2200890949
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3179583113
Short name T1108
Test name
Test status
Simulation time 6479682408 ps
CPU time 182.2 seconds
Started Jul 17 07:59:41 PM PDT 24
Finished Jul 17 08:02:44 PM PDT 24
Peak memory 206648 kb
Host smart-8d0f7acb-8fd3-43f7-9f22-bfa88527f7f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3179583113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3179583113
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3022536843
Short name T2573
Test name
Test status
Simulation time 169720962 ps
CPU time 0.81 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:49 PM PDT 24
Peak memory 206464 kb
Host smart-24fe5621-04d7-4509-a3ee-979d9641f806
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3022536843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3022536843
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.134695404
Short name T1628
Test name
Test status
Simulation time 208870208 ps
CPU time 0.78 seconds
Started Jul 17 07:59:44 PM PDT 24
Finished Jul 17 07:59:47 PM PDT 24
Peak memory 206436 kb
Host smart-ebe9eb94-0b7b-4c28-9732-363462da0ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13469
5404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.134695404
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2455661726
Short name T120
Test name
Test status
Simulation time 220439362 ps
CPU time 0.89 seconds
Started Jul 17 07:59:44 PM PDT 24
Finished Jul 17 07:59:48 PM PDT 24
Peak memory 206476 kb
Host smart-a5bd0ed6-c0d2-4feb-9ef9-e3109fe893c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24556
61726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2455661726
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1670980589
Short name T319
Test name
Test status
Simulation time 186706480 ps
CPU time 0.9 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206448 kb
Host smart-127f9a5c-8745-472d-a290-fb55f4b06090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16709
80589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1670980589
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1875959149
Short name T1724
Test name
Test status
Simulation time 191664046 ps
CPU time 0.79 seconds
Started Jul 17 07:59:40 PM PDT 24
Finished Jul 17 07:59:41 PM PDT 24
Peak memory 206456 kb
Host smart-793ceb24-ca00-4a74-a108-cc15323abc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18759
59149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1875959149
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3864910891
Short name T2486
Test name
Test status
Simulation time 154408351 ps
CPU time 0.74 seconds
Started Jul 17 07:59:42 PM PDT 24
Finished Jul 17 07:59:44 PM PDT 24
Peak memory 206436 kb
Host smart-51cd373d-de99-435e-8e7e-acaf48a2bb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649
10891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3864910891
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2489138402
Short name T2228
Test name
Test status
Simulation time 162553582 ps
CPU time 0.76 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 07:59:46 PM PDT 24
Peak memory 206464 kb
Host smart-d8265e57-3b50-4443-a136-4b6466e54f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24891
38402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2489138402
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.507795816
Short name T2695
Test name
Test status
Simulation time 241220500 ps
CPU time 0.91 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:50 PM PDT 24
Peak memory 206472 kb
Host smart-0a770c84-fdb2-4883-a6b3-679d257b76f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=507795816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.507795816
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2567058924
Short name T918
Test name
Test status
Simulation time 155344137 ps
CPU time 0.76 seconds
Started Jul 17 07:59:50 PM PDT 24
Finished Jul 17 07:59:58 PM PDT 24
Peak memory 206440 kb
Host smart-ba4e8c1f-5bf3-406c-9c7b-02effb4cee58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25670
58924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2567058924
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.457276459
Short name T1594
Test name
Test status
Simulation time 62472011 ps
CPU time 0.68 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:56 PM PDT 24
Peak memory 206384 kb
Host smart-92fe17ec-acff-4c9b-8afd-5469d8e31129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45727
6459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.457276459
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.163223216
Short name T24
Test name
Test status
Simulation time 15502304478 ps
CPU time 33.62 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 08:00:19 PM PDT 24
Peak memory 206732 kb
Host smart-7979f849-a665-4b3a-a95b-f63f7246a171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16322
3216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.163223216
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.967584605
Short name T731
Test name
Test status
Simulation time 190320202 ps
CPU time 0.83 seconds
Started Jul 17 07:59:42 PM PDT 24
Finished Jul 17 07:59:45 PM PDT 24
Peak memory 206460 kb
Host smart-8e131183-f710-46d8-8059-70e798d968ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96758
4605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.967584605
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2984906604
Short name T1785
Test name
Test status
Simulation time 261867477 ps
CPU time 0.89 seconds
Started Jul 17 07:59:44 PM PDT 24
Finished Jul 17 07:59:48 PM PDT 24
Peak memory 206448 kb
Host smart-b4068875-e6b7-4cf5-b2b5-942b9ba8f722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29849
06604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2984906604
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.230080002
Short name T1060
Test name
Test status
Simulation time 223922506 ps
CPU time 0.85 seconds
Started Jul 17 07:59:41 PM PDT 24
Finished Jul 17 07:59:43 PM PDT 24
Peak memory 206452 kb
Host smart-e62c60fa-63b1-4f49-9835-8a59697e2cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23008
0002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.230080002
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3968776989
Short name T2672
Test name
Test status
Simulation time 210277605 ps
CPU time 0.87 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206460 kb
Host smart-0493cc0b-6020-42ec-a956-a79bdd8daae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39687
76989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3968776989
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.51882665
Short name T1094
Test name
Test status
Simulation time 179167580 ps
CPU time 0.8 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206372 kb
Host smart-6537a056-08cc-417a-8c91-f757b0e4b4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51882
665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.51882665
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1485588467
Short name T1178
Test name
Test status
Simulation time 159107131 ps
CPU time 0.74 seconds
Started Jul 17 07:59:42 PM PDT 24
Finished Jul 17 07:59:44 PM PDT 24
Peak memory 206460 kb
Host smart-7d216480-93b4-411a-b877-e683ae06d459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14855
88467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1485588467
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1917671175
Short name T1323
Test name
Test status
Simulation time 179776939 ps
CPU time 0.78 seconds
Started Jul 17 07:59:41 PM PDT 24
Finished Jul 17 07:59:43 PM PDT 24
Peak memory 206452 kb
Host smart-de59b64c-5e29-49a7-8e6b-b803a736205a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19176
71175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1917671175
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.910037492
Short name T1583
Test name
Test status
Simulation time 206194568 ps
CPU time 0.89 seconds
Started Jul 17 07:59:42 PM PDT 24
Finished Jul 17 07:59:45 PM PDT 24
Peak memory 206464 kb
Host smart-855c5107-e98f-4c07-a678-7a3deb31f704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91003
7492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.910037492
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3423582486
Short name T1121
Test name
Test status
Simulation time 5482513290 ps
CPU time 53.15 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206608 kb
Host smart-14300021-74ed-4eb9-ba69-7b456cc6a871
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3423582486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3423582486
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3590502647
Short name T2168
Test name
Test status
Simulation time 167826971 ps
CPU time 0.78 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206460 kb
Host smart-15c59a3b-a707-4c1b-8da8-77108d628786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
02647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3590502647
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1584401666
Short name T827
Test name
Test status
Simulation time 190357387 ps
CPU time 0.82 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:49 PM PDT 24
Peak memory 206464 kb
Host smart-a5c7ba22-8e7e-490e-8c20-6a4fa6141e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
01666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1584401666
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2217817477
Short name T320
Test name
Test status
Simulation time 624650985 ps
CPU time 1.57 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:50 PM PDT 24
Peak memory 206400 kb
Host smart-03c324ff-7c47-4e0c-b192-c04421f25e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22178
17477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2217817477
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1725835608
Short name T1283
Test name
Test status
Simulation time 6788433950 ps
CPU time 191.84 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 08:03:04 PM PDT 24
Peak memory 206692 kb
Host smart-5bc8c289-ece9-4621-975f-635481b8ef58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17258
35608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1725835608
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1548393479
Short name T1999
Test name
Test status
Simulation time 35639161 ps
CPU time 0.67 seconds
Started Jul 17 07:59:51 PM PDT 24
Finished Jul 17 07:59:59 PM PDT 24
Peak memory 206428 kb
Host smart-c715a977-73a3-484c-b891-8255e2708320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1548393479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1548393479
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2368733340
Short name T203
Test name
Test status
Simulation time 4387386292 ps
CPU time 4.92 seconds
Started Jul 17 07:59:42 PM PDT 24
Finished Jul 17 07:59:48 PM PDT 24
Peak memory 206732 kb
Host smart-39bcd099-eb92-4016-8945-28886201f2fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2368733340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2368733340
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.1978835299
Short name T2530
Test name
Test status
Simulation time 13345633623 ps
CPU time 14.58 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 08:00:00 PM PDT 24
Peak memory 206528 kb
Host smart-ee1fb851-bf88-4c78-909e-b35db7a905e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1978835299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.1978835299
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3577152022
Short name T2056
Test name
Test status
Simulation time 23373797744 ps
CPU time 21.5 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 08:00:12 PM PDT 24
Peak memory 206724 kb
Host smart-ebcad14f-084a-46e7-b899-aca6a4695ab6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3577152022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3577152022
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2627612875
Short name T2679
Test name
Test status
Simulation time 162753177 ps
CPU time 0.78 seconds
Started Jul 17 07:59:50 PM PDT 24
Finished Jul 17 07:59:58 PM PDT 24
Peak memory 206412 kb
Host smart-b10a5a81-fcda-4d71-a175-449d6c0a85e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26276
12875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2627612875
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.4100136686
Short name T831
Test name
Test status
Simulation time 196888614 ps
CPU time 0.76 seconds
Started Jul 17 07:59:41 PM PDT 24
Finished Jul 17 07:59:42 PM PDT 24
Peak memory 206452 kb
Host smart-fd6a4e92-91ac-45d2-9540-ca92643a62ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41001
36686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.4100136686
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1115059463
Short name T478
Test name
Test status
Simulation time 437308541 ps
CPU time 1.38 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:52 PM PDT 24
Peak memory 206456 kb
Host smart-352be8fa-b2de-4b54-bb94-f1a6e5f2a82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11150
59463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1115059463
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2382134062
Short name T2229
Test name
Test status
Simulation time 954456146 ps
CPU time 2.39 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206568 kb
Host smart-d36b494f-0b55-4444-99bf-41dbb0fb804e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821
34062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2382134062
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2263846121
Short name T1943
Test name
Test status
Simulation time 7753057085 ps
CPU time 16.89 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 08:00:06 PM PDT 24
Peak memory 206624 kb
Host smart-d0d9cad4-a8e6-4315-a361-842385073e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22638
46121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2263846121
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.334892795
Short name T1865
Test name
Test status
Simulation time 420072014 ps
CPU time 1.3 seconds
Started Jul 17 07:59:44 PM PDT 24
Finished Jul 17 07:59:48 PM PDT 24
Peak memory 206476 kb
Host smart-14428816-0d8e-4bab-a6a3-83e0bf653e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33489
2795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.334892795
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.987033723
Short name T683
Test name
Test status
Simulation time 197644184 ps
CPU time 0.79 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:55 PM PDT 24
Peak memory 206464 kb
Host smart-54284e2f-4a40-48d7-b1c2-55ca34b0e6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98703
3723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.987033723
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2542685358
Short name T2744
Test name
Test status
Simulation time 34999292 ps
CPU time 0.65 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:54 PM PDT 24
Peak memory 206440 kb
Host smart-92dea44f-db83-42c5-878a-38f009745ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25426
85358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2542685358
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3109154711
Short name T1948
Test name
Test status
Simulation time 855494808 ps
CPU time 2.63 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:58 PM PDT 24
Peak memory 206600 kb
Host smart-4cbf6810-bc28-4a63-890d-b1a72f38388f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31091
54711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3109154711
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3862488974
Short name T1164
Test name
Test status
Simulation time 192066995 ps
CPU time 1.78 seconds
Started Jul 17 07:59:44 PM PDT 24
Finished Jul 17 07:59:50 PM PDT 24
Peak memory 206576 kb
Host smart-d92adbb0-f61a-4f06-83aa-6a758e74c7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38624
88974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3862488974
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4003143612
Short name T1646
Test name
Test status
Simulation time 248490803 ps
CPU time 0.86 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206460 kb
Host smart-bdf31872-8386-494f-9e5f-042f8542907e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40031
43612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4003143612
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2438441503
Short name T1039
Test name
Test status
Simulation time 155033579 ps
CPU time 0.77 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:50 PM PDT 24
Peak memory 206452 kb
Host smart-02283c52-7c5d-4458-aa60-20f1a8b99989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24384
41503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2438441503
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.2653722936
Short name T2436
Test name
Test status
Simulation time 10804209380 ps
CPU time 33.33 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 08:00:24 PM PDT 24
Peak memory 206676 kb
Host smart-9136c197-1427-4e1a-8907-d9bfc4fb5290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26537
22936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2653722936
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1657073130
Short name T483
Test name
Test status
Simulation time 184968061 ps
CPU time 0.83 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:55 PM PDT 24
Peak memory 206440 kb
Host smart-4fca47ad-4d91-47a3-941a-b096246ff102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16570
73130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1657073130
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.954120624
Short name T2029
Test name
Test status
Simulation time 23355675627 ps
CPU time 28.51 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 08:00:21 PM PDT 24
Peak memory 206472 kb
Host smart-d6f380cb-d66a-484d-82bb-63b51f67f36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95412
0624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.954120624
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.4244151191
Short name T1471
Test name
Test status
Simulation time 3273391746 ps
CPU time 3.5 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:54 PM PDT 24
Peak memory 206528 kb
Host smart-ae1a434f-9586-4a88-9648-f5b130ce3415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42441
51191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.4244151191
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1732680419
Short name T148
Test name
Test status
Simulation time 9675188197 ps
CPU time 64.93 seconds
Started Jul 17 07:59:28 PM PDT 24
Finished Jul 17 08:00:34 PM PDT 24
Peak memory 206732 kb
Host smart-a89fed2c-750a-4de2-9785-6dc4c6663ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17326
80419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1732680419
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2580061846
Short name T517
Test name
Test status
Simulation time 2847772924 ps
CPU time 20.55 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 08:00:05 PM PDT 24
Peak memory 206724 kb
Host smart-6aa87ec4-49cd-42eb-ad42-e366037b371c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2580061846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2580061846
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3975827140
Short name T1299
Test name
Test status
Simulation time 295994849 ps
CPU time 0.89 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 07:59:52 PM PDT 24
Peak memory 206456 kb
Host smart-4107161e-074c-4d49-9f5f-af41609c2c84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3975827140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3975827140
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3900437153
Short name T860
Test name
Test status
Simulation time 191078926 ps
CPU time 0.87 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206452 kb
Host smart-7a51c834-e663-4e04-9a7a-ff8ddf52e649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39004
37153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3900437153
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.3681249900
Short name T655
Test name
Test status
Simulation time 4951410611 ps
CPU time 139.89 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 08:02:16 PM PDT 24
Peak memory 206644 kb
Host smart-c2419fc9-83b5-498e-bc0d-deaed4df94ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36812
49900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.3681249900
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.801187791
Short name T1654
Test name
Test status
Simulation time 4782587157 ps
CPU time 32.73 seconds
Started Jul 17 07:59:51 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206724 kb
Host smart-b468a818-b415-4edc-9f0d-2586ce2795af
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=801187791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.801187791
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3834554060
Short name T1067
Test name
Test status
Simulation time 165096110 ps
CPU time 0.81 seconds
Started Jul 17 07:59:50 PM PDT 24
Finished Jul 17 07:59:58 PM PDT 24
Peak memory 206456 kb
Host smart-53ad8248-c731-4eed-9969-1e3558ad9ebc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3834554060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3834554060
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.984618956
Short name T924
Test name
Test status
Simulation time 161142832 ps
CPU time 0.77 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206464 kb
Host smart-30c302f3-507e-47cc-8b57-e096f07036cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98461
8956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.984618956
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1865309468
Short name T112
Test name
Test status
Simulation time 190792590 ps
CPU time 0.81 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:55 PM PDT 24
Peak memory 206456 kb
Host smart-75df68b7-2ecb-4926-86d7-a8bf03038856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18653
09468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1865309468
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3420866318
Short name T93
Test name
Test status
Simulation time 194077998 ps
CPU time 0.86 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:56 PM PDT 24
Peak memory 206456 kb
Host smart-043de382-674c-4fd2-aba7-b5f37c46a7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34208
66318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3420866318
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.4004337104
Short name T800
Test name
Test status
Simulation time 211561447 ps
CPU time 0.82 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:54 PM PDT 24
Peak memory 206448 kb
Host smart-b94d1cd6-a844-4d70-91de-101ab2ca8aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
37104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.4004337104
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3928837228
Short name T1838
Test name
Test status
Simulation time 184712226 ps
CPU time 0.88 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206452 kb
Host smart-6627e78c-0010-4a33-8a88-4c3064f70235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
37228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3928837228
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2608979326
Short name T2398
Test name
Test status
Simulation time 176933295 ps
CPU time 0.79 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 07:59:52 PM PDT 24
Peak memory 206468 kb
Host smart-dd9a94a6-366f-427a-8370-033e01a84ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26089
79326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2608979326
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.831117150
Short name T556
Test name
Test status
Simulation time 269995755 ps
CPU time 0.95 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:56 PM PDT 24
Peak memory 206440 kb
Host smart-d9e73ffd-951e-4ca3-8f89-a85fe6903e6b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=831117150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.831117150
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3028384277
Short name T1209
Test name
Test status
Simulation time 186257637 ps
CPU time 0.88 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:55 PM PDT 24
Peak memory 206452 kb
Host smart-b86b8ae5-ebdd-4ed2-a24d-79b09aec0b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30283
84277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3028384277
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3273334160
Short name T40
Test name
Test status
Simulation time 41014332 ps
CPU time 0.64 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:49 PM PDT 24
Peak memory 206428 kb
Host smart-f2486780-c1b4-4262-99eb-981a8f0e2adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733
34160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3273334160
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1939426468
Short name T2685
Test name
Test status
Simulation time 12370332843 ps
CPU time 30.72 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 08:00:25 PM PDT 24
Peak memory 206676 kb
Host smart-65670fd5-0276-4462-9dec-efa2ff57fb36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
26468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1939426468
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3611568124
Short name T1352
Test name
Test status
Simulation time 161418378 ps
CPU time 0.82 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206408 kb
Host smart-1be9cdac-dc47-422a-8ec7-28b644950f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36115
68124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3611568124
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3301101773
Short name T378
Test name
Test status
Simulation time 218788023 ps
CPU time 0.88 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206416 kb
Host smart-ae514552-6bfc-4c45-80ce-38c5b7f05754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33011
01773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3301101773
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1394850699
Short name T2253
Test name
Test status
Simulation time 178483867 ps
CPU time 0.88 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:55 PM PDT 24
Peak memory 206452 kb
Host smart-c1cdc337-1ba9-4bca-bb04-2173f8747fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13948
50699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1394850699
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1439166146
Short name T365
Test name
Test status
Simulation time 179769644 ps
CPU time 0.85 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206440 kb
Host smart-9677bbdf-ba34-45b6-96a7-89838d5b4bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14391
66146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1439166146
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.170975152
Short name T810
Test name
Test status
Simulation time 137972573 ps
CPU time 0.76 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206460 kb
Host smart-a292a696-793a-48ba-845f-54a8fbbd0ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17097
5152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.170975152
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.817067347
Short name T1218
Test name
Test status
Simulation time 158907038 ps
CPU time 0.81 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:55 PM PDT 24
Peak memory 206428 kb
Host smart-55066421-8707-44ad-9bf0-666e1c9cf175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81706
7347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.817067347
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.802010250
Short name T2665
Test name
Test status
Simulation time 191868806 ps
CPU time 0.77 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 07:59:46 PM PDT 24
Peak memory 206448 kb
Host smart-34d0b2c9-af19-4b9e-b95d-3b6a627f4d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80201
0250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.802010250
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2108345752
Short name T415
Test name
Test status
Simulation time 272328850 ps
CPU time 0.97 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:50 PM PDT 24
Peak memory 206416 kb
Host smart-ded66f0c-163e-4003-be34-84361f4c96fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083
45752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2108345752
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1403344229
Short name T1244
Test name
Test status
Simulation time 5808716937 ps
CPU time 55.63 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 08:00:46 PM PDT 24
Peak memory 206672 kb
Host smart-319a0406-a360-490a-9fa9-98b854f8ae27
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1403344229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1403344229
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2333289347
Short name T1048
Test name
Test status
Simulation time 242963146 ps
CPU time 0.86 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206408 kb
Host smart-f3521ca4-9f42-43e3-80fe-9eb1efabfe9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332
89347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2333289347
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1371981405
Short name T2133
Test name
Test status
Simulation time 202630082 ps
CPU time 0.85 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:50 PM PDT 24
Peak memory 206416 kb
Host smart-7d19e2eb-62eb-4228-af0e-7be9ad77e06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13719
81405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1371981405
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1788540231
Short name T978
Test name
Test status
Simulation time 644358209 ps
CPU time 1.55 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:56 PM PDT 24
Peak memory 206460 kb
Host smart-8dfbe967-17a2-48ad-843e-7851426ad6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17885
40231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1788540231
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2073240137
Short name T1574
Test name
Test status
Simulation time 7513139924 ps
CPU time 197.73 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 08:03:12 PM PDT 24
Peak memory 206656 kb
Host smart-bc79661d-c536-4f7e-83bf-bb913c968581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20732
40137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2073240137
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.1997065743
Short name T2055
Test name
Test status
Simulation time 39405776 ps
CPU time 0.7 seconds
Started Jul 17 07:59:52 PM PDT 24
Finished Jul 17 08:00:00 PM PDT 24
Peak memory 206424 kb
Host smart-ef332c3c-2a1d-4fe4-a242-fb63895f100a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1997065743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.1997065743
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2601714185
Short name T549
Test name
Test status
Simulation time 4150868402 ps
CPU time 5.88 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 08:00:02 PM PDT 24
Peak memory 206476 kb
Host smart-0818e632-67b5-417c-8567-9161a1a0f76c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2601714185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2601714185
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.639697221
Short name T642
Test name
Test status
Simulation time 13321334428 ps
CPU time 11.7 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 08:00:06 PM PDT 24
Peak memory 206700 kb
Host smart-8351f1c1-8756-4f19-847d-97561553b9dd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=639697221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.639697221
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3477240383
Short name T450
Test name
Test status
Simulation time 23407448740 ps
CPU time 23.89 seconds
Started Jul 17 07:59:51 PM PDT 24
Finished Jul 17 08:00:22 PM PDT 24
Peak memory 206432 kb
Host smart-1e0865a2-a076-4836-9b09-2b978befbc52
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3477240383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.3477240383
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3118674670
Short name T1876
Test name
Test status
Simulation time 205334436 ps
CPU time 0.9 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206596 kb
Host smart-bb64515f-dd5a-4a06-9f46-d40a1ce9b626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31186
74670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3118674670
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.586096995
Short name T1835
Test name
Test status
Simulation time 165677803 ps
CPU time 0.77 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:58 PM PDT 24
Peak memory 206460 kb
Host smart-aa48cbda-4539-402d-93fa-666247d9802d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58609
6995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.586096995
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.821224439
Short name T2664
Test name
Test status
Simulation time 183812171 ps
CPU time 0.83 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206616 kb
Host smart-aa3881c3-cafb-4351-b5ed-01bf07378d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82122
4439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.821224439
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3541711102
Short name T1338
Test name
Test status
Simulation time 1632695603 ps
CPU time 3.45 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:00:03 PM PDT 24
Peak memory 206664 kb
Host smart-8c282a71-2b7a-4daa-80ad-926b13236835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
11102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3541711102
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2379198315
Short name T1151
Test name
Test status
Simulation time 14712954725 ps
CPU time 25.49 seconds
Started Jul 17 07:59:54 PM PDT 24
Finished Jul 17 08:00:26 PM PDT 24
Peak memory 206720 kb
Host smart-fcc401ee-475b-4eca-ae05-61fa6739960a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
98315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2379198315
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1324596583
Short name T2121
Test name
Test status
Simulation time 332355319 ps
CPU time 1.12 seconds
Started Jul 17 07:59:50 PM PDT 24
Finished Jul 17 07:59:59 PM PDT 24
Peak memory 206464 kb
Host smart-f9ae68ba-5214-414e-9c7b-d3c9128292e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13245
96583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1324596583
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.3555859070
Short name T1305
Test name
Test status
Simulation time 172228333 ps
CPU time 0.76 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:55 PM PDT 24
Peak memory 206460 kb
Host smart-a3fcc571-bec6-4f52-a38c-d7caae62ca34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35558
59070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3555859070
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.259978351
Short name T442
Test name
Test status
Simulation time 51151315 ps
CPU time 0.68 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:49 PM PDT 24
Peak memory 206460 kb
Host smart-7f415884-69d8-42f5-84dc-8dcf86353f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25997
8351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.259978351
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2396986412
Short name T2136
Test name
Test status
Simulation time 961713979 ps
CPU time 2.19 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:59 PM PDT 24
Peak memory 206644 kb
Host smart-ef138002-1222-48de-87ca-1b5e89c8e151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23969
86412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2396986412
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3890777907
Short name T1792
Test name
Test status
Simulation time 224978289 ps
CPU time 1.48 seconds
Started Jul 17 07:59:55 PM PDT 24
Finished Jul 17 08:00:02 PM PDT 24
Peak memory 206800 kb
Host smart-0fa62518-42cf-462c-bc85-cc257e0ae771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38907
77907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3890777907
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.139890601
Short name T344
Test name
Test status
Simulation time 233168194 ps
CPU time 0.95 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206448 kb
Host smart-dcd4abb0-eb98-45b6-bbab-7c1b6c180873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13989
0601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.139890601
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2599311564
Short name T1807
Test name
Test status
Simulation time 138487941 ps
CPU time 0.79 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206456 kb
Host smart-b11ff994-5247-446c-b27d-5a9de69dd6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25993
11564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2599311564
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1216941909
Short name T946
Test name
Test status
Simulation time 234329332 ps
CPU time 0.95 seconds
Started Jul 17 07:59:52 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206452 kb
Host smart-bc6af56a-1920-486d-aeac-8ba1c56ee8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12169
41909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1216941909
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.2410417466
Short name T209
Test name
Test status
Simulation time 6539976666 ps
CPU time 182.49 seconds
Started Jul 17 07:59:50 PM PDT 24
Finished Jul 17 08:03:00 PM PDT 24
Peak memory 206676 kb
Host smart-5a1733c7-477e-4586-b82d-9cf4ad47d3c1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2410417466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.2410417466
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.1868709490
Short name T2347
Test name
Test status
Simulation time 12859562993 ps
CPU time 102.84 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 08:01:27 PM PDT 24
Peak memory 206740 kb
Host smart-869a97cc-eba9-4140-b9e0-4bcd25a96b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18687
09490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.1868709490
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.201122838
Short name T1685
Test name
Test status
Simulation time 155537780 ps
CPU time 0.79 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:58 PM PDT 24
Peak memory 206448 kb
Host smart-acd30397-2793-4a52-b95d-a7fabc8ab86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20112
2838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.201122838
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.3144588683
Short name T1387
Test name
Test status
Simulation time 23325407544 ps
CPU time 21.71 seconds
Started Jul 17 07:59:43 PM PDT 24
Finished Jul 17 08:00:06 PM PDT 24
Peak memory 206604 kb
Host smart-98cb8ffa-b873-498c-bcb9-22b3ff9972ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31445
88683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.3144588683
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.797074256
Short name T1491
Test name
Test status
Simulation time 3323036613 ps
CPU time 4.03 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206524 kb
Host smart-cc103c71-df96-49c7-80bb-eeb443910c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79707
4256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.797074256
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2570859524
Short name T2734
Test name
Test status
Simulation time 10814172913 ps
CPU time 95.43 seconds
Started Jul 17 07:59:55 PM PDT 24
Finished Jul 17 08:01:37 PM PDT 24
Peak memory 206696 kb
Host smart-d8e60a8e-24e3-41ad-a83c-ad5944fc3e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25708
59524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2570859524
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.3504728089
Short name T1298
Test name
Test status
Simulation time 5696108441 ps
CPU time 40.89 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 08:00:33 PM PDT 24
Peak memory 206688 kb
Host smart-a25c2533-9bae-4ac4-9d7c-01ea118a528d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3504728089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.3504728089
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2681600107
Short name T2252
Test name
Test status
Simulation time 235856045 ps
CPU time 0.96 seconds
Started Jul 17 07:59:51 PM PDT 24
Finished Jul 17 08:00:00 PM PDT 24
Peak memory 206372 kb
Host smart-57e14abd-bd82-4893-b1d8-c3272981c878
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2681600107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2681600107
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2113935722
Short name T659
Test name
Test status
Simulation time 188382744 ps
CPU time 0.84 seconds
Started Jul 17 07:59:55 PM PDT 24
Finished Jul 17 08:00:02 PM PDT 24
Peak memory 206436 kb
Host smart-0f5629ee-9de8-4006-8b4e-b3a967421ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21139
35722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2113935722
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1875535642
Short name T2741
Test name
Test status
Simulation time 5732209197 ps
CPU time 147.39 seconds
Started Jul 17 07:59:54 PM PDT 24
Finished Jul 17 08:02:28 PM PDT 24
Peak memory 206680 kb
Host smart-d4f28d08-fff4-42fe-8e55-f4de10c09da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18755
35642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1875535642
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2023316896
Short name T723
Test name
Test status
Simulation time 4073220966 ps
CPU time 38.46 seconds
Started Jul 17 07:59:51 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206660 kb
Host smart-f7e5aa83-32e9-4de0-abf1-6267f73a125f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2023316896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2023316896
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.850807373
Short name T1402
Test name
Test status
Simulation time 149530356 ps
CPU time 0.78 seconds
Started Jul 17 07:59:55 PM PDT 24
Finished Jul 17 08:00:02 PM PDT 24
Peak memory 206436 kb
Host smart-c13e2446-2fe6-4f11-9273-61c8d54c268b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=850807373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.850807373
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3211863654
Short name T2245
Test name
Test status
Simulation time 142432623 ps
CPU time 0.76 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206460 kb
Host smart-c035bb5f-9ae1-42c4-be3b-7a75472e93fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
63654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3211863654
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3791457823
Short name T1562
Test name
Test status
Simulation time 216830542 ps
CPU time 0.92 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206444 kb
Host smart-7b931f67-c7a9-472c-8eee-8c219c85927f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
57823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3791457823
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2179911344
Short name T1343
Test name
Test status
Simulation time 145325034 ps
CPU time 0.77 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206456 kb
Host smart-381077e0-9146-4c44-ba38-432cdd798a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21799
11344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2179911344
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2648104563
Short name T2377
Test name
Test status
Simulation time 178379850 ps
CPU time 0.86 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:54 PM PDT 24
Peak memory 206448 kb
Host smart-4e34cdfc-b306-47d9-b26b-9087bd35c13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26481
04563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2648104563
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.449220126
Short name T2569
Test name
Test status
Simulation time 198284135 ps
CPU time 0.86 seconds
Started Jul 17 07:59:56 PM PDT 24
Finished Jul 17 08:00:02 PM PDT 24
Peak memory 206392 kb
Host smart-36325b71-329d-4a97-95dd-a56ca9b00e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44922
0126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.449220126
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1086080226
Short name T2123
Test name
Test status
Simulation time 149620106 ps
CPU time 0.77 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206460 kb
Host smart-26b0650a-3584-4213-a857-46169c3e0ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10860
80226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1086080226
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.690274625
Short name T48
Test name
Test status
Simulation time 195733292 ps
CPU time 0.88 seconds
Started Jul 17 07:59:44 PM PDT 24
Finished Jul 17 07:59:47 PM PDT 24
Peak memory 206632 kb
Host smart-42ba5f1c-5cf4-47fe-b45b-184ac3f80a57
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=690274625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.690274625
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3518735809
Short name T595
Test name
Test status
Simulation time 150878238 ps
CPU time 0.77 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206452 kb
Host smart-cfafab8d-1ae5-46e4-b274-f02f99ba754e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35187
35809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3518735809
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1084414583
Short name T1663
Test name
Test status
Simulation time 38489187 ps
CPU time 0.66 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206448 kb
Host smart-c349875f-1f70-44c3-8b5f-c56a21171e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10844
14583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1084414583
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.95765534
Short name T1282
Test name
Test status
Simulation time 18689853258 ps
CPU time 44.41 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 08:00:36 PM PDT 24
Peak memory 206756 kb
Host smart-db0476bb-24b6-4eb6-8cce-d2624ecbbeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95765
534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.95765534
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3730655536
Short name T1735
Test name
Test status
Simulation time 212238432 ps
CPU time 0.87 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206456 kb
Host smart-0577732d-b704-45ec-960f-62eee4f152ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37306
55536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3730655536
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3771205527
Short name T362
Test name
Test status
Simulation time 209684467 ps
CPU time 0.88 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:56 PM PDT 24
Peak memory 206432 kb
Host smart-3a98b97c-059a-4831-826b-bd0af74b81c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37712
05527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3771205527
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.1117392141
Short name T1137
Test name
Test status
Simulation time 189457100 ps
CPU time 0.8 seconds
Started Jul 17 07:59:46 PM PDT 24
Finished Jul 17 07:59:51 PM PDT 24
Peak memory 206452 kb
Host smart-bbbb8273-eed7-45c0-b0d7-699e3e2551e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11173
92141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1117392141
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3303132932
Short name T1064
Test name
Test status
Simulation time 194653308 ps
CPU time 0.8 seconds
Started Jul 17 07:59:47 PM PDT 24
Finished Jul 17 07:59:53 PM PDT 24
Peak memory 206464 kb
Host smart-0e79be8d-4d60-4f8a-be4e-2d2dc69c4280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33031
32932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3303132932
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1527815611
Short name T1250
Test name
Test status
Simulation time 146661723 ps
CPU time 0.75 seconds
Started Jul 17 07:59:50 PM PDT 24
Finished Jul 17 07:59:58 PM PDT 24
Peak memory 206452 kb
Host smart-6f5f8898-5a14-43e4-bfff-aeae5a0cab17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15278
15611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1527815611
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3150183836
Short name T361
Test name
Test status
Simulation time 179353769 ps
CPU time 0.85 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206408 kb
Host smart-c0b1c5a2-0733-4ff8-94fb-aa7368968e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31501
83836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3150183836
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.940198454
Short name T2353
Test name
Test status
Simulation time 162213893 ps
CPU time 0.78 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:55 PM PDT 24
Peak memory 206456 kb
Host smart-3d651253-7f28-46af-b5d9-100c955fbb9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94019
8454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.940198454
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2666407938
Short name T1207
Test name
Test status
Simulation time 238311413 ps
CPU time 1.06 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206452 kb
Host smart-3a9f7a6e-268d-4093-a829-6a2326c87067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26664
07938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2666407938
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.4260922764
Short name T1897
Test name
Test status
Simulation time 4278094976 ps
CPU time 39.96 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 08:00:29 PM PDT 24
Peak memory 206668 kb
Host smart-bce43613-a349-4c78-b215-e7bb0e7d6c7c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4260922764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.4260922764
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2364364260
Short name T2646
Test name
Test status
Simulation time 182306249 ps
CPU time 0.83 seconds
Started Jul 17 07:59:54 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206460 kb
Host smart-2b927544-571e-4bec-aae6-d6b26af8814a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23643
64260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2364364260
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1805624424
Short name T696
Test name
Test status
Simulation time 179928027 ps
CPU time 0.89 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206452 kb
Host smart-52f3400a-58dd-4abf-9284-bbea81ec3d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
24424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1805624424
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.2894944473
Short name T2140
Test name
Test status
Simulation time 553003249 ps
CPU time 1.46 seconds
Started Jul 17 07:59:50 PM PDT 24
Finished Jul 17 07:59:59 PM PDT 24
Peak memory 206456 kb
Host smart-2e6e6080-c0d0-4982-908f-94a2f0768427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
44473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.2894944473
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3273614632
Short name T457
Test name
Test status
Simulation time 7069487664 ps
CPU time 48.51 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:00:49 PM PDT 24
Peak memory 206660 kb
Host smart-1816b12d-df3f-4518-baa5-3c727a54b735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32736
14632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3273614632
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3272333482
Short name T1964
Test name
Test status
Simulation time 90329191 ps
CPU time 0.74 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206428 kb
Host smart-f8903e53-6b68-48a4-bfb7-8ce8b83ff151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3272333482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3272333482
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3872622235
Short name T525
Test name
Test status
Simulation time 4031620786 ps
CPU time 5.39 seconds
Started Jul 17 07:59:48 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206728 kb
Host smart-0a65a9c3-8614-4588-a4c8-c4a048783bca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3872622235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3872622235
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.4079579663
Short name T2406
Test name
Test status
Simulation time 13398248800 ps
CPU time 12.7 seconds
Started Jul 17 07:59:55 PM PDT 24
Finished Jul 17 08:00:14 PM PDT 24
Peak memory 206812 kb
Host smart-624478b9-1024-41b2-9534-7d7af5191d68
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4079579663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.4079579663
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3778058142
Short name T1293
Test name
Test status
Simulation time 23352081318 ps
CPU time 23.19 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 08:00:20 PM PDT 24
Peak memory 206528 kb
Host smart-14382a84-9688-477e-b77f-b8bd3706b6b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3778058142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3778058142
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1168232015
Short name T2202
Test name
Test status
Simulation time 175536585 ps
CPU time 0.83 seconds
Started Jul 17 07:59:45 PM PDT 24
Finished Jul 17 07:59:49 PM PDT 24
Peak memory 206476 kb
Host smart-b8c0df49-23f7-4dce-a0ad-5ed227670a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682
32015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1168232015
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2361696390
Short name T1767
Test name
Test status
Simulation time 154020853 ps
CPU time 0.76 seconds
Started Jul 17 07:59:51 PM PDT 24
Finished Jul 17 08:00:00 PM PDT 24
Peak memory 206352 kb
Host smart-0bad80e1-5263-465a-8654-a7948dd99bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23616
96390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2361696390
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3454356826
Short name T640
Test name
Test status
Simulation time 234770977 ps
CPU time 0.96 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:57 PM PDT 24
Peak memory 206440 kb
Host smart-bffe2e43-5469-41d1-83e9-c40cffae247a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34543
56826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3454356826
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.931700482
Short name T2499
Test name
Test status
Simulation time 1102727815 ps
CPU time 2.75 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 07:59:59 PM PDT 24
Peak memory 206612 kb
Host smart-1676f82b-1222-44d1-af6a-8637a5381e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93170
0482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.931700482
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.4170189214
Short name T1146
Test name
Test status
Simulation time 9979534445 ps
CPU time 18.12 seconds
Started Jul 17 07:59:49 PM PDT 24
Finished Jul 17 08:00:15 PM PDT 24
Peak memory 206648 kb
Host smart-35eb1479-746e-4289-9dbc-c2837774bb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701
89214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.4170189214
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.924449522
Short name T2704
Test name
Test status
Simulation time 484145002 ps
CPU time 1.34 seconds
Started Jul 17 07:59:52 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206460 kb
Host smart-85885589-572a-412e-a7ac-5de977c16f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92444
9522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.924449522
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.879507113
Short name T2429
Test name
Test status
Simulation time 139582390 ps
CPU time 0.8 seconds
Started Jul 17 07:59:52 PM PDT 24
Finished Jul 17 08:00:00 PM PDT 24
Peak memory 206456 kb
Host smart-0968f393-f822-4c5f-94fc-f9d31214f13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87950
7113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.879507113
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.166630311
Short name T2512
Test name
Test status
Simulation time 38367828 ps
CPU time 0.66 seconds
Started Jul 17 07:59:52 PM PDT 24
Finished Jul 17 08:00:00 PM PDT 24
Peak memory 206440 kb
Host smart-96dd7071-524a-4945-bbd9-a68e365071b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16663
0311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.166630311
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.441845553
Short name T2045
Test name
Test status
Simulation time 674214069 ps
CPU time 1.93 seconds
Started Jul 17 07:59:56 PM PDT 24
Finished Jul 17 08:00:04 PM PDT 24
Peak memory 206496 kb
Host smart-6f59a2da-f2eb-4621-b1e6-bc7bcf3b0d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44184
5553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.441845553
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1497950190
Short name T1532
Test name
Test status
Simulation time 211601186 ps
CPU time 1.45 seconds
Started Jul 17 07:59:56 PM PDT 24
Finished Jul 17 08:00:03 PM PDT 24
Peak memory 206640 kb
Host smart-977a7b00-dc1b-475e-899f-a27be6b8058d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14979
50190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1497950190
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3687281952
Short name T1626
Test name
Test status
Simulation time 236302576 ps
CPU time 0.87 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:00:01 PM PDT 24
Peak memory 206424 kb
Host smart-4481dfbf-7fe5-4b67-81ce-a95fad6fca7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872
81952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3687281952
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1079657764
Short name T358
Test name
Test status
Simulation time 149069846 ps
CPU time 0.76 seconds
Started Jul 17 07:59:55 PM PDT 24
Finished Jul 17 08:00:02 PM PDT 24
Peak memory 206440 kb
Host smart-0ae8cfd7-d24f-4a3b-aaf7-96c029e0c4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10796
57764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1079657764
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.550795233
Short name T1561
Test name
Test status
Simulation time 186286079 ps
CPU time 0.82 seconds
Started Jul 17 07:59:44 PM PDT 24
Finished Jul 17 07:59:49 PM PDT 24
Peak memory 206456 kb
Host smart-5c9141d3-97c6-48df-b766-88068c840b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55079
5233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.550795233
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.4272927144
Short name T562
Test name
Test status
Simulation time 11340191729 ps
CPU time 94.04 seconds
Started Jul 17 07:59:53 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206668 kb
Host smart-3ce410f2-d8be-4448-8df4-d7ce1752ec47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42729
27144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.4272927144
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.603864057
Short name T1852
Test name
Test status
Simulation time 216279657 ps
CPU time 0.85 seconds
Started Jul 17 07:59:56 PM PDT 24
Finished Jul 17 08:00:03 PM PDT 24
Peak memory 206412 kb
Host smart-d67925de-1179-4859-b9d1-e4b3bce5131b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60386
4057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.603864057
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1351323462
Short name T1199
Test name
Test status
Simulation time 23376545667 ps
CPU time 24.33 seconds
Started Jul 17 07:59:55 PM PDT 24
Finished Jul 17 08:00:26 PM PDT 24
Peak memory 206496 kb
Host smart-fcb3153c-1db0-4b50-9ed9-0a2bf4109f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513
23462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1351323462
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2709540400
Short name T1310
Test name
Test status
Simulation time 3322148983 ps
CPU time 4.51 seconds
Started Jul 17 08:00:21 PM PDT 24
Finished Jul 17 08:00:27 PM PDT 24
Peak memory 206540 kb
Host smart-616f4e9c-f9ac-401e-bd70-cc9dc785849b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27095
40400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2709540400
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.4051039678
Short name T2191
Test name
Test status
Simulation time 10536570609 ps
CPU time 279.07 seconds
Started Jul 17 08:00:18 PM PDT 24
Finished Jul 17 08:05:00 PM PDT 24
Peak memory 206720 kb
Host smart-360aff7e-7a92-43c0-bd12-a99a73ccb8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40510
39678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.4051039678
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1154913440
Short name T1956
Test name
Test status
Simulation time 5766617079 ps
CPU time 55.42 seconds
Started Jul 17 08:00:17 PM PDT 24
Finished Jul 17 08:01:13 PM PDT 24
Peak memory 206660 kb
Host smart-5d0f7f6d-69d9-4d90-897f-f11f54f78f0f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1154913440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1154913440
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.4230087451
Short name T30
Test name
Test status
Simulation time 242600170 ps
CPU time 0.9 seconds
Started Jul 17 08:00:17 PM PDT 24
Finished Jul 17 08:00:19 PM PDT 24
Peak memory 206444 kb
Host smart-a3932690-620a-4049-bd8b-d2e640960bb1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4230087451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.4230087451
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2024165283
Short name T861
Test name
Test status
Simulation time 201164050 ps
CPU time 0.87 seconds
Started Jul 17 08:00:24 PM PDT 24
Finished Jul 17 08:00:27 PM PDT 24
Peak memory 206452 kb
Host smart-e1c25398-0a52-4cf2-96a1-4bafc9233c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20241
65283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2024165283
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.2365257253
Short name T1607
Test name
Test status
Simulation time 5644100756 ps
CPU time 50.12 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:01:11 PM PDT 24
Peak memory 206732 kb
Host smart-026b4a52-e310-4989-b0e8-3fd8c3aceb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23652
57253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.2365257253
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1196536379
Short name T1230
Test name
Test status
Simulation time 4533067903 ps
CPU time 30.35 seconds
Started Jul 17 08:00:22 PM PDT 24
Finished Jul 17 08:00:54 PM PDT 24
Peak memory 206724 kb
Host smart-b9979bf2-c614-4369-b68a-1dbf66638d68
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1196536379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1196536379
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1610755944
Short name T1660
Test name
Test status
Simulation time 156914286 ps
CPU time 0.78 seconds
Started Jul 17 08:00:15 PM PDT 24
Finished Jul 17 08:00:17 PM PDT 24
Peak memory 206404 kb
Host smart-997eec45-ba60-4d66-81f4-7d48864aa438
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1610755944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1610755944
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2498167165
Short name T1474
Test name
Test status
Simulation time 174905004 ps
CPU time 0.78 seconds
Started Jul 17 08:00:21 PM PDT 24
Finished Jul 17 08:00:24 PM PDT 24
Peak memory 206468 kb
Host smart-4143d4b3-7003-447c-a744-e0b9b4cbd94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24981
67165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2498167165
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1003933654
Short name T1885
Test name
Test status
Simulation time 232239083 ps
CPU time 0.86 seconds
Started Jul 17 08:00:24 PM PDT 24
Finished Jul 17 08:00:26 PM PDT 24
Peak memory 206460 kb
Host smart-4e6b32a2-1c92-4c29-bf67-02667b199041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10039
33654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1003933654
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2809971991
Short name T2572
Test name
Test status
Simulation time 176157370 ps
CPU time 0.82 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:39 PM PDT 24
Peak memory 206388 kb
Host smart-8ddb615a-1805-4ce6-8390-d27a562b8c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28099
71991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2809971991
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2267779470
Short name T1533
Test name
Test status
Simulation time 213225315 ps
CPU time 0.87 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206412 kb
Host smart-1ff043c4-b98f-45e5-938d-acf83b61462c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22677
79470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2267779470
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.851352485
Short name T1770
Test name
Test status
Simulation time 185081867 ps
CPU time 0.8 seconds
Started Jul 17 08:00:24 PM PDT 24
Finished Jul 17 08:00:26 PM PDT 24
Peak memory 206440 kb
Host smart-bc4f3c91-fb87-4d69-958c-c65c7f199824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85135
2485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.851352485
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1775999316
Short name T158
Test name
Test status
Simulation time 151851339 ps
CPU time 0.79 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206468 kb
Host smart-a02dfb6d-e74f-4003-bd18-6e977376cea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17759
99316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1775999316
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1937023107
Short name T1419
Test name
Test status
Simulation time 225257935 ps
CPU time 0.96 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206452 kb
Host smart-812b70c8-5bd3-4229-ae40-8464e70ec795
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1937023107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1937023107
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3417561862
Short name T824
Test name
Test status
Simulation time 146307785 ps
CPU time 0.76 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206420 kb
Host smart-42323584-47a0-47ab-b385-af27073a3f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34175
61862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3417561862
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3656998509
Short name T1017
Test name
Test status
Simulation time 32785514 ps
CPU time 0.65 seconds
Started Jul 17 08:00:24 PM PDT 24
Finished Jul 17 08:00:27 PM PDT 24
Peak memory 206444 kb
Host smart-71514e14-28a6-4c21-9dc9-aacf58658b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36569
98509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3656998509
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.50414626
Short name T18
Test name
Test status
Simulation time 10991047113 ps
CPU time 23.33 seconds
Started Jul 17 08:00:24 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 214948 kb
Host smart-010bceea-25dd-41d9-86a0-baf537362b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50414
626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.50414626
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4059937902
Short name T1819
Test name
Test status
Simulation time 224270848 ps
CPU time 0.92 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:32 PM PDT 24
Peak memory 206448 kb
Host smart-3d53bd78-cdf8-41aa-92b3-12497fcc2193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40599
37902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4059937902
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3079379026
Short name T2348
Test name
Test status
Simulation time 171557584 ps
CPU time 0.85 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:00:29 PM PDT 24
Peak memory 206456 kb
Host smart-6cc94f3c-a670-465e-9a3b-8b1683e6d0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30793
79026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3079379026
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3877076431
Short name T1909
Test name
Test status
Simulation time 170311690 ps
CPU time 0.8 seconds
Started Jul 17 08:00:22 PM PDT 24
Finished Jul 17 08:00:25 PM PDT 24
Peak memory 206532 kb
Host smart-2c281ee5-1e66-4a57-a7d5-9eac02ae0a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38770
76431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3877076431
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.4205248520
Short name T1102
Test name
Test status
Simulation time 134569722 ps
CPU time 0.74 seconds
Started Jul 17 08:00:37 PM PDT 24
Finished Jul 17 08:00:44 PM PDT 24
Peak memory 206456 kb
Host smart-bb549650-1c27-44cd-ab64-6bedd9962bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42052
48520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.4205248520
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.954440099
Short name T1931
Test name
Test status
Simulation time 177865394 ps
CPU time 0.82 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206448 kb
Host smart-34497a08-290a-4fbd-90ac-11e6005431b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95444
0099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.954440099
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1900980865
Short name T416
Test name
Test status
Simulation time 169436730 ps
CPU time 0.79 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206444 kb
Host smart-3139dc46-a0a0-4ed6-86a9-7ad9bf364700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19009
80865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1900980865
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2499723171
Short name T1522
Test name
Test status
Simulation time 239228733 ps
CPU time 0.97 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206248 kb
Host smart-b33b1034-77cf-4169-992c-1c6c49ab9293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24997
23171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2499723171
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.151656164
Short name T171
Test name
Test status
Simulation time 4476213194 ps
CPU time 120.46 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:02:43 PM PDT 24
Peak memory 206668 kb
Host smart-50bba453-7b9d-4c5c-b402-a23f021cdb18
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=151656164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.151656164
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.568103889
Short name T1389
Test name
Test status
Simulation time 157306799 ps
CPU time 0.75 seconds
Started Jul 17 08:00:37 PM PDT 24
Finished Jul 17 08:00:44 PM PDT 24
Peak memory 206464 kb
Host smart-d1f58a61-f235-4a39-ac99-a653ad53da27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56810
3889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.568103889
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.364898419
Short name T1278
Test name
Test status
Simulation time 158997331 ps
CPU time 0.78 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206444 kb
Host smart-408f0096-09d8-4c3d-bdbc-8823c9bcbc84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36489
8419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.364898419
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.3863833545
Short name T441
Test name
Test status
Simulation time 637101971 ps
CPU time 1.54 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:44 PM PDT 24
Peak memory 205976 kb
Host smart-e383da49-c7b2-4361-8b49-83fb391155ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38638
33545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.3863833545
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2487404086
Short name T2144
Test name
Test status
Simulation time 6644270914 ps
CPU time 189.63 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:03:42 PM PDT 24
Peak memory 206660 kb
Host smart-672bb4f4-815b-4441-9890-207a01236698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
04086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2487404086
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.4094863816
Short name T1147
Test name
Test status
Simulation time 72919662 ps
CPU time 0.69 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206452 kb
Host smart-d12cfd3f-414c-4ae3-bf12-625e0260fd60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4094863816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.4094863816
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.4265790040
Short name T1327
Test name
Test status
Simulation time 4071581883 ps
CPU time 4.79 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:47 PM PDT 24
Peak memory 206664 kb
Host smart-ed134990-3ae7-466f-b89d-a860a8b1c473
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4265790040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.4265790040
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1103856856
Short name T9
Test name
Test status
Simulation time 13445085835 ps
CPU time 16.11 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:01:00 PM PDT 24
Peak memory 206464 kb
Host smart-f3b3e9c1-0d1e-4be3-bad7-2bfa0031f138
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1103856856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1103856856
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2808038345
Short name T2026
Test name
Test status
Simulation time 23386982086 ps
CPU time 27.34 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:01:03 PM PDT 24
Peak memory 206588 kb
Host smart-abf34102-c1eb-4ddc-bbd6-73dba8e2a4b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2808038345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.2808038345
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1938438671
Short name T622
Test name
Test status
Simulation time 219346682 ps
CPU time 0.84 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206452 kb
Host smart-486cffb1-2fa3-4e9f-8a0c-8a27b7076f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19384
38671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1938438671
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.788199185
Short name T1916
Test name
Test status
Simulation time 154738078 ps
CPU time 0.82 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:36 PM PDT 24
Peak memory 206460 kb
Host smart-3c612888-72e8-4aa8-a5b7-4a8387dfa09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78819
9185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.788199185
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2940988486
Short name T2008
Test name
Test status
Simulation time 529619027 ps
CPU time 1.42 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206604 kb
Host smart-73f46b9c-fb01-4a78-ba8d-0bd501ee50f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29409
88486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2940988486
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.845494538
Short name T1937
Test name
Test status
Simulation time 761642845 ps
CPU time 1.86 seconds
Started Jul 17 08:00:37 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206536 kb
Host smart-f69c75fa-42bc-49bc-adcf-0c07f24dfec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84549
4538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.845494538
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2687354671
Short name T1913
Test name
Test status
Simulation time 368084559 ps
CPU time 1.31 seconds
Started Jul 17 08:00:40 PM PDT 24
Finished Jul 17 08:00:46 PM PDT 24
Peak memory 206456 kb
Host smart-ddf094c7-2dc0-49b5-8259-5c79d882d584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26873
54671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2687354671
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3326656137
Short name T741
Test name
Test status
Simulation time 136159240 ps
CPU time 0.74 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:39 PM PDT 24
Peak memory 206456 kb
Host smart-6d2d31c1-fb5c-4d3b-b70b-d734fa3c4043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33266
56137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3326656137
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.897410064
Short name T1044
Test name
Test status
Simulation time 43717160 ps
CPU time 0.64 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:00:48 PM PDT 24
Peak memory 206444 kb
Host smart-3bd0209b-103c-415d-b80d-338c6479ebea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89741
0064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.897410064
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1316526373
Short name T949
Test name
Test status
Simulation time 945537265 ps
CPU time 2.43 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:40 PM PDT 24
Peak memory 206608 kb
Host smart-a56f96d7-fb11-4960-8b72-ce0f0cdf5c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13165
26373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1316526373
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1655443731
Short name T2592
Test name
Test status
Simulation time 257084260 ps
CPU time 1.77 seconds
Started Jul 17 08:00:40 PM PDT 24
Finished Jul 17 08:00:47 PM PDT 24
Peak memory 206660 kb
Host smart-c189382f-63e7-4d5d-84b5-8d09fdef965e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16554
43731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1655443731
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2386281100
Short name T863
Test name
Test status
Simulation time 200960548 ps
CPU time 0.84 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:00:47 PM PDT 24
Peak memory 206448 kb
Host smart-242d2617-8c03-40b9-abab-df17ed59f9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23862
81100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2386281100
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3509270865
Short name T768
Test name
Test status
Simulation time 179248631 ps
CPU time 0.8 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:00:22 PM PDT 24
Peak memory 206456 kb
Host smart-c38be58c-3ed7-48b7-9f59-5f2d6ffec28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35092
70865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3509270865
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3594942862
Short name T2032
Test name
Test status
Simulation time 173763343 ps
CPU time 0.91 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206468 kb
Host smart-3acef071-cdb6-4b44-8cae-fbe810b59f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35949
42862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3594942862
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.3729747791
Short name T1867
Test name
Test status
Simulation time 12445862574 ps
CPU time 39.89 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206724 kb
Host smart-93691ac9-6e6f-4e1a-982e-18627aa11404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37297
47791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.3729747791
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1871455947
Short name T61
Test name
Test status
Simulation time 293250882 ps
CPU time 0.93 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:00:28 PM PDT 24
Peak memory 206408 kb
Host smart-4c66bf66-2861-4a5a-8686-7d3802b960db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18714
55947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1871455947
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.2215324717
Short name T2399
Test name
Test status
Simulation time 23360161973 ps
CPU time 26.71 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:00:48 PM PDT 24
Peak memory 206528 kb
Host smart-7e195b4b-56b9-4b52-96c2-a898c2f6da97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22153
24717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.2215324717
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2232657483
Short name T2125
Test name
Test status
Simulation time 3356737889 ps
CPU time 3.8 seconds
Started Jul 17 08:00:15 PM PDT 24
Finished Jul 17 08:00:20 PM PDT 24
Peak memory 206516 kb
Host smart-3189656b-1631-451e-89e0-0a34ea6ce3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
57483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2232657483
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.3574370451
Short name T804
Test name
Test status
Simulation time 6769923339 ps
CPU time 50.59 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:01:18 PM PDT 24
Peak memory 206700 kb
Host smart-44414360-b58e-450a-93da-f47ad8453695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35743
70451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.3574370451
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2167594225
Short name T1525
Test name
Test status
Simulation time 4542049165 ps
CPU time 33.88 seconds
Started Jul 17 08:00:24 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206660 kb
Host smart-cec2657c-df6d-472c-86f7-3ba1567f14a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2167594225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2167594225
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2108459629
Short name T1572
Test name
Test status
Simulation time 235875289 ps
CPU time 0.91 seconds
Started Jul 17 08:00:17 PM PDT 24
Finished Jul 17 08:00:20 PM PDT 24
Peak memory 206452 kb
Host smart-77e67fd7-8a94-47a1-837d-fca5b03f8b3a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2108459629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2108459629
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.4254940755
Short name T694
Test name
Test status
Simulation time 211501229 ps
CPU time 0.9 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:00:28 PM PDT 24
Peak memory 206448 kb
Host smart-6015b015-85f0-4a90-a220-f7510e47d20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42549
40755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.4254940755
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2025292122
Short name T2208
Test name
Test status
Simulation time 5570512475 ps
CPU time 149.34 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:02:50 PM PDT 24
Peak memory 206844 kb
Host smart-1fc06738-0011-47a6-89e6-7bb98c8134a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20252
92122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2025292122
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2501979547
Short name T1814
Test name
Test status
Simulation time 4595071689 ps
CPU time 44.64 seconds
Started Jul 17 08:00:32 PM PDT 24
Finished Jul 17 08:01:24 PM PDT 24
Peak memory 206708 kb
Host smart-f47f7c1e-5ce1-40ef-abab-ad2e87a81a2d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2501979547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2501979547
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2730173721
Short name T626
Test name
Test status
Simulation time 227310246 ps
CPU time 0.84 seconds
Started Jul 17 08:00:20 PM PDT 24
Finished Jul 17 08:00:23 PM PDT 24
Peak memory 206468 kb
Host smart-0b19e45c-157d-4fe3-9ab9-b00ceb5be649
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2730173721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2730173721
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3930859461
Short name T2458
Test name
Test status
Simulation time 151892036 ps
CPU time 0.76 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206328 kb
Host smart-4022be38-2593-4fff-b324-f51ee49c21e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39308
59461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3930859461
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2732245610
Short name T1579
Test name
Test status
Simulation time 183618525 ps
CPU time 0.86 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:40 PM PDT 24
Peak memory 206460 kb
Host smart-327e01e3-b828-41b3-b79b-ac816c42f740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27322
45610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2732245610
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3342882603
Short name T2593
Test name
Test status
Simulation time 187819761 ps
CPU time 0.86 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206464 kb
Host smart-8c3c76ef-be5c-459f-b7ab-c80cf1949741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33428
82603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3342882603
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1994871781
Short name T2181
Test name
Test status
Simulation time 157564188 ps
CPU time 0.78 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206316 kb
Host smart-c2964fed-99e5-407c-83b5-6267c1845f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19948
71781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1994871781
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1197077079
Short name T2487
Test name
Test status
Simulation time 173737069 ps
CPU time 0.81 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206444 kb
Host smart-3bc24c07-58e2-48b4-bbea-0fbf8e926a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11970
77079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1197077079
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3757001346
Short name T1409
Test name
Test status
Simulation time 156640445 ps
CPU time 0.78 seconds
Started Jul 17 08:00:29 PM PDT 24
Finished Jul 17 08:00:34 PM PDT 24
Peak memory 206412 kb
Host smart-884ba1b2-9c5c-47e4-94f2-9c56d8b19274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37570
01346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3757001346
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.735713261
Short name T2689
Test name
Test status
Simulation time 249715381 ps
CPU time 0.93 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206324 kb
Host smart-c401ea44-c3ce-46cd-80a1-7b55712db52d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=735713261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.735713261
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1729724293
Short name T1050
Test name
Test status
Simulation time 151334963 ps
CPU time 0.74 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:32 PM PDT 24
Peak memory 206408 kb
Host smart-dd38b705-4ad5-42d0-a812-db5b11c53f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17297
24293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1729724293
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.214812820
Short name T801
Test name
Test status
Simulation time 65222667 ps
CPU time 0.66 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:30 PM PDT 24
Peak memory 206444 kb
Host smart-fe41c601-c6c4-4c8d-a0a4-e1a1ae062819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21481
2820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.214812820
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1093645568
Short name T1097
Test name
Test status
Simulation time 19915160974 ps
CPU time 42.16 seconds
Started Jul 17 08:00:29 PM PDT 24
Finished Jul 17 08:01:15 PM PDT 24
Peak memory 206768 kb
Host smart-b5d5ec71-a7a4-4a72-abff-1704cec25dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10936
45568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1093645568
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3474442320
Short name T1484
Test name
Test status
Simulation time 147214313 ps
CPU time 0.76 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206404 kb
Host smart-f23e07e9-3425-44cd-ae7a-481f2cda5891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34744
42320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3474442320
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1222276463
Short name T1054
Test name
Test status
Simulation time 235159132 ps
CPU time 0.88 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206444 kb
Host smart-c9e6c70a-fc77-42c8-8041-b39c5676d422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12222
76463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1222276463
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1464746365
Short name T2647
Test name
Test status
Simulation time 240428917 ps
CPU time 0.88 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206456 kb
Host smart-831b7112-b7b2-43e0-8fdb-38423fdc4a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14647
46365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1464746365
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2379203674
Short name T2137
Test name
Test status
Simulation time 161971140 ps
CPU time 0.87 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206464 kb
Host smart-a29d19c0-d15a-4a96-8694-4a32ce141805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
03674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2379203674
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.993636195
Short name T2738
Test name
Test status
Simulation time 178547618 ps
CPU time 0.74 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:33 PM PDT 24
Peak memory 206436 kb
Host smart-95bc63d0-d39b-4e23-a054-b9414427c701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99363
6195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.993636195
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1825062536
Short name T881
Test name
Test status
Simulation time 174951782 ps
CPU time 0.77 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206428 kb
Host smart-b169ae67-d1fe-4bb6-a917-8a349a89cc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18250
62536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1825062536
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1850901550
Short name T1665
Test name
Test status
Simulation time 153769609 ps
CPU time 0.76 seconds
Started Jul 17 08:00:29 PM PDT 24
Finished Jul 17 08:00:35 PM PDT 24
Peak memory 206456 kb
Host smart-a4da2595-a625-4652-8974-101b4c9dfa95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18509
01550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1850901550
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.498189071
Short name T2030
Test name
Test status
Simulation time 232627864 ps
CPU time 0.96 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 205928 kb
Host smart-0514264b-2a25-4421-a8e7-5e79b84355df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49818
9071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.498189071
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3652707788
Short name T414
Test name
Test status
Simulation time 5715690021 ps
CPU time 161.02 seconds
Started Jul 17 08:00:29 PM PDT 24
Finished Jul 17 08:03:16 PM PDT 24
Peak memory 206664 kb
Host smart-4bffec94-660c-4321-a6f9-9b85eb208d38
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3652707788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3652707788
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2553864454
Short name T2693
Test name
Test status
Simulation time 196970096 ps
CPU time 0.86 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:40 PM PDT 24
Peak memory 206444 kb
Host smart-4b460c07-f784-4db6-9e4a-1de3c25142d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25538
64454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2553864454
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.81583498
Short name T1486
Test name
Test status
Simulation time 232606721 ps
CPU time 0.9 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:00:29 PM PDT 24
Peak memory 206440 kb
Host smart-c587e949-560a-4d32-ad4a-89eb1d1797db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81583
498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.81583498
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.1645952443
Short name T1671
Test name
Test status
Simulation time 888827192 ps
CPU time 2.16 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206540 kb
Host smart-315b3b1c-a48f-44af-8a79-a29e0263a3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16459
52443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1645952443
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2059345479
Short name T454
Test name
Test status
Simulation time 5105512741 ps
CPU time 46.72 seconds
Started Jul 17 08:00:32 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206716 kb
Host smart-16ae0726-6c20-4165-aec7-a74c11b6335a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20593
45479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2059345479
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2053734200
Short name T2236
Test name
Test status
Simulation time 66621527 ps
CPU time 0.71 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206428 kb
Host smart-19736be0-5bfe-484d-8307-ec5e8fe80274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2053734200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2053734200
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.742268751
Short name T1722
Test name
Test status
Simulation time 3589580998 ps
CPU time 4.11 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:40 PM PDT 24
Peak memory 206360 kb
Host smart-ed3c44c4-b857-491c-8e43-2cf61302ae29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=742268751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.742268751
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1172701148
Short name T1866
Test name
Test status
Simulation time 13434002949 ps
CPU time 12.53 seconds
Started Jul 17 08:00:37 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206728 kb
Host smart-fd0df7e7-d857-497f-9124-0fbc1579bad9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1172701148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1172701148
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2508152277
Short name T2650
Test name
Test status
Simulation time 23376048608 ps
CPU time 24.44 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206448 kb
Host smart-226dacba-3ec8-4570-9124-06173b489159
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2508152277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.2508152277
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1605001736
Short name T2542
Test name
Test status
Simulation time 205436642 ps
CPU time 0.92 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206396 kb
Host smart-9bb5700d-0edb-43a3-b46b-54e31ddb00b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16050
01736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1605001736
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2525765176
Short name T1780
Test name
Test status
Simulation time 174536863 ps
CPU time 0.77 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:49 PM PDT 24
Peak memory 205684 kb
Host smart-bbef68ac-76d9-410f-b640-90a0f743a92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25257
65176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2525765176
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.990101357
Short name T2239
Test name
Test status
Simulation time 215681110 ps
CPU time 0.88 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206528 kb
Host smart-93b8f935-4e2f-47a4-8605-dfbba7e1728a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99010
1357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.990101357
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.4261223967
Short name T645
Test name
Test status
Simulation time 669784619 ps
CPU time 1.71 seconds
Started Jul 17 08:00:37 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206472 kb
Host smart-f5470dce-f5c8-4578-bb2b-2c7b4ec5dbac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42612
23967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.4261223967
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.397986045
Short name T1235
Test name
Test status
Simulation time 10831126534 ps
CPU time 19.01 seconds
Started Jul 17 08:00:37 PM PDT 24
Finished Jul 17 08:01:02 PM PDT 24
Peak memory 206724 kb
Host smart-40adcd45-29c7-4fb3-bed6-122feeecd5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39798
6045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.397986045
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.4131934447
Short name T1176
Test name
Test status
Simulation time 413245687 ps
CPU time 1.25 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206544 kb
Host smart-f4bb4ccb-9667-4d6f-ac3a-6c2003e01a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41319
34447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.4131934447
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3910990691
Short name T475
Test name
Test status
Simulation time 148915630 ps
CPU time 0.84 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206168 kb
Host smart-d0861394-0464-414e-bb80-ccb94234d225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39109
90691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3910990691
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3681514513
Short name T1289
Test name
Test status
Simulation time 46005775 ps
CPU time 0.71 seconds
Started Jul 17 08:00:18 PM PDT 24
Finished Jul 17 08:00:21 PM PDT 24
Peak memory 206580 kb
Host smart-3e538c78-f790-4ac9-a275-1fb8588f2a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36815
14513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3681514513
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3498189663
Short name T2442
Test name
Test status
Simulation time 924579270 ps
CPU time 2.03 seconds
Started Jul 17 08:00:23 PM PDT 24
Finished Jul 17 08:00:26 PM PDT 24
Peak memory 206648 kb
Host smart-e78fec01-1faa-4f8f-9fe9-cfc7f9c703a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34981
89663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3498189663
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3680737359
Short name T1511
Test name
Test status
Simulation time 169223993 ps
CPU time 1.99 seconds
Started Jul 17 08:00:15 PM PDT 24
Finished Jul 17 08:00:18 PM PDT 24
Peak memory 206536 kb
Host smart-972f15a3-25cc-4218-b664-8c9c2d3c3df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36807
37359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3680737359
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.4170101267
Short name T1254
Test name
Test status
Simulation time 158643770 ps
CPU time 0.79 seconds
Started Jul 17 08:00:21 PM PDT 24
Finished Jul 17 08:00:23 PM PDT 24
Peak memory 206460 kb
Host smart-7f86fa0a-9db9-4fbf-8a3f-fb1ab599daaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701
01267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.4170101267
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4107303821
Short name T1092
Test name
Test status
Simulation time 151004669 ps
CPU time 0.75 seconds
Started Jul 17 08:00:17 PM PDT 24
Finished Jul 17 08:00:20 PM PDT 24
Peak memory 206448 kb
Host smart-07a33fbd-6d0a-4ab6-989c-4d0759f052c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41073
03821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4107303821
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.4047791254
Short name T1135
Test name
Test status
Simulation time 181851574 ps
CPU time 0.93 seconds
Started Jul 17 08:00:17 PM PDT 24
Finished Jul 17 08:00:20 PM PDT 24
Peak memory 206448 kb
Host smart-7684338d-1271-42e7-8684-53cb1eea97fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40477
91254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.4047791254
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.3747857914
Short name T2278
Test name
Test status
Simulation time 5404508924 ps
CPU time 39.49 seconds
Started Jul 17 08:00:26 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206632 kb
Host smart-fa6275a3-fb67-42ab-bcbb-421b7b838ec0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3747857914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.3747857914
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.1180073677
Short name T2654
Test name
Test status
Simulation time 7233298157 ps
CPU time 58.36 seconds
Started Jul 17 08:00:14 PM PDT 24
Finished Jul 17 08:01:13 PM PDT 24
Peak memory 206708 kb
Host smart-56dd84bb-15e4-4b82-ae5d-3fff2d16b60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11800
73677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.1180073677
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.646705809
Short name T1805
Test name
Test status
Simulation time 226095883 ps
CPU time 0.87 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:32 PM PDT 24
Peak memory 206440 kb
Host smart-b767bffb-c309-4413-8beb-3acb0647ffda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64670
5809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.646705809
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.19189998
Short name T2323
Test name
Test status
Simulation time 23330163618 ps
CPU time 23.35 seconds
Started Jul 17 08:00:14 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206516 kb
Host smart-2434f6c2-04b0-445a-aae3-4ccbfbe010e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19189
998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.19189998
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.645104879
Short name T1473
Test name
Test status
Simulation time 3314394124 ps
CPU time 3.88 seconds
Started Jul 17 08:00:18 PM PDT 24
Finished Jul 17 08:00:24 PM PDT 24
Peak memory 206680 kb
Host smart-4d637e92-c52f-4dd1-bc11-a56a6e2a314b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64510
4879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.645104879
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.825544593
Short name T451
Test name
Test status
Simulation time 7666434879 ps
CPU time 205.6 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:03:46 PM PDT 24
Peak memory 206924 kb
Host smart-f761101d-531f-4b17-b584-d1759a81b5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82554
4593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.825544593
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3625183546
Short name T1627
Test name
Test status
Simulation time 7497124645 ps
CPU time 214.81 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:03:55 PM PDT 24
Peak memory 206648 kb
Host smart-e4cdf427-169b-4e78-af1c-51794e83d7f8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3625183546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3625183546
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2481551833
Short name T844
Test name
Test status
Simulation time 249225204 ps
CPU time 0.89 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206456 kb
Host smart-f75fcc8b-e9f0-465a-adf2-000ca11bb2fd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2481551833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2481551833
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3202565628
Short name T2717
Test name
Test status
Simulation time 258667537 ps
CPU time 0.92 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206448 kb
Host smart-b826a0dd-4d5f-4bd1-ab0d-380c2f189f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32025
65628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3202565628
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1926485229
Short name T1597
Test name
Test status
Simulation time 5461839045 ps
CPU time 48.61 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:01:09 PM PDT 24
Peak memory 206668 kb
Host smart-5a3cda45-b44c-425d-a1f7-cbd8482bddf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19264
85229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1926485229
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1900862471
Short name T1509
Test name
Test status
Simulation time 6846931631 ps
CPU time 46.46 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:01:17 PM PDT 24
Peak memory 206552 kb
Host smart-7f2234a5-149e-4983-8ccc-54e3ac1f34f1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1900862471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1900862471
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.769552641
Short name T2446
Test name
Test status
Simulation time 153806523 ps
CPU time 0.79 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206452 kb
Host smart-a96a27d7-3e50-4954-a146-3228595a372b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=769552641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.769552641
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.781693597
Short name T2586
Test name
Test status
Simulation time 141131634 ps
CPU time 0.73 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:30 PM PDT 24
Peak memory 206456 kb
Host smart-25a5bf59-e5bf-4b28-be9c-482a3f29527d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78169
3597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.781693597
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3955883063
Short name T135
Test name
Test status
Simulation time 213670757 ps
CPU time 0.9 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206416 kb
Host smart-6eaf4f63-f546-4027-8fdf-a4090698920b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
83063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3955883063
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1054429011
Short name T413
Test name
Test status
Simulation time 152075331 ps
CPU time 0.79 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206440 kb
Host smart-72c1306c-add4-4245-b12e-e9e96f447089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544
29011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1054429011
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.372380676
Short name T523
Test name
Test status
Simulation time 178391381 ps
CPU time 0.8 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206448 kb
Host smart-95c8de20-07d4-4d47-94b0-7ac374cc8c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
0676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.372380676
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3738550936
Short name T2359
Test name
Test status
Simulation time 236421287 ps
CPU time 0.86 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:33 PM PDT 24
Peak memory 206392 kb
Host smart-dd004594-1f68-449c-975b-547e01e4d958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385
50936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3738550936
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3780964332
Short name T1468
Test name
Test status
Simulation time 144849868 ps
CPU time 0.74 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:00:28 PM PDT 24
Peak memory 206456 kb
Host smart-c4627dd9-5538-449f-b38a-e47bbf5237d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
64332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3780964332
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3119871513
Short name T1818
Test name
Test status
Simulation time 232073504 ps
CPU time 1 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206456 kb
Host smart-ffe284f8-3524-4fa0-9420-6f7bc1b2c0b4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3119871513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3119871513
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.4148230577
Short name T2563
Test name
Test status
Simulation time 173205241 ps
CPU time 0.85 seconds
Started Jul 17 08:00:29 PM PDT 24
Finished Jul 17 08:00:34 PM PDT 24
Peak memory 206440 kb
Host smart-3773d314-4b30-48d6-b106-f05b263be093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41482
30577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.4148230577
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1030895103
Short name T963
Test name
Test status
Simulation time 41413594 ps
CPU time 0.64 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206416 kb
Host smart-62841db4-46cb-4120-a5eb-446b4be70ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10308
95103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1030895103
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2540546831
Short name T1939
Test name
Test status
Simulation time 14957349562 ps
CPU time 36.68 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:01:19 PM PDT 24
Peak memory 214888 kb
Host smart-76868518-576c-46e5-a1d5-33fd61b0896e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25405
46831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2540546831
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1454740779
Short name T2151
Test name
Test status
Simulation time 190537063 ps
CPU time 0.88 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:30 PM PDT 24
Peak memory 206452 kb
Host smart-c05cdb0b-ff7a-443b-a3ee-0488780b5ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
40779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1454740779
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1338190920
Short name T2649
Test name
Test status
Simulation time 241538785 ps
CPU time 0.92 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206460 kb
Host smart-1676f2a1-4cae-46d5-b09c-7011830f65c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13381
90920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1338190920
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3137642718
Short name T1120
Test name
Test status
Simulation time 207610208 ps
CPU time 0.84 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206452 kb
Host smart-1be407cd-d979-40cb-8dea-c532f6325121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31376
42718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3137642718
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.1629133
Short name T1358
Test name
Test status
Simulation time 189301795 ps
CPU time 0.87 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206452 kb
Host smart-6d7e352a-83ee-499c-89cb-53965cf5f9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16291
33 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.1629133
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.4140088970
Short name T2589
Test name
Test status
Simulation time 147531537 ps
CPU time 0.78 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206388 kb
Host smart-2975b376-4861-450b-a81b-1707a99cf8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41400
88970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.4140088970
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2733443356
Short name T1588
Test name
Test status
Simulation time 191680847 ps
CPU time 0.8 seconds
Started Jul 17 08:00:29 PM PDT 24
Finished Jul 17 08:00:35 PM PDT 24
Peak memory 206452 kb
Host smart-3e50b063-ee41-45fd-85d5-c3ce8bec99fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27334
43356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2733443356
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2211152569
Short name T1301
Test name
Test status
Simulation time 162290083 ps
CPU time 0.76 seconds
Started Jul 17 08:00:39 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206448 kb
Host smart-ae7077b2-c006-4b22-8111-6dddf886714b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
52569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2211152569
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2502641090
Short name T1898
Test name
Test status
Simulation time 253793935 ps
CPU time 0.98 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:36 PM PDT 24
Peak memory 206452 kb
Host smart-ad669d8f-61d2-413f-84cf-c64b8b052e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25026
41090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2502641090
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3053205811
Short name T1032
Test name
Test status
Simulation time 5049104068 ps
CPU time 34.81 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:01:14 PM PDT 24
Peak memory 206716 kb
Host smart-7b3a65d7-cfbe-42aa-88da-29c9a54919cd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3053205811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3053205811
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.425490976
Short name T2258
Test name
Test status
Simulation time 191712660 ps
CPU time 0.86 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206616 kb
Host smart-6d3458b3-3924-4642-8d69-6fa77026ad46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42549
0976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.425490976
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3260974742
Short name T1266
Test name
Test status
Simulation time 195150533 ps
CPU time 0.84 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206380 kb
Host smart-4ff414cc-98f8-4080-961d-e2d81df4b3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32609
74742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3260974742
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.3135690416
Short name T2237
Test name
Test status
Simulation time 518074975 ps
CPU time 1.5 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206324 kb
Host smart-00b189b6-9027-4052-b10e-bcd97ac6e872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31356
90416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3135690416
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.2034439471
Short name T2662
Test name
Test status
Simulation time 4214109084 ps
CPU time 37.23 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:01:13 PM PDT 24
Peak memory 206636 kb
Host smart-f7a22851-aa1d-48e6-8671-7af81fd1b1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20344
39471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2034439471
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3735896323
Short name T647
Test name
Test status
Simulation time 34552541 ps
CPU time 0.65 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206432 kb
Host smart-0f5cebc0-3db6-4a94-a189-36fc0c9d1907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3735896323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3735896323
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3029599222
Short name T974
Test name
Test status
Simulation time 4129557705 ps
CPU time 4.83 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:54 PM PDT 24
Peak memory 206716 kb
Host smart-d211be67-2459-476b-925e-dbf0bd27a57d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3029599222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.3029599222
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.518878470
Short name T1829
Test name
Test status
Simulation time 13550404009 ps
CPU time 12.73 seconds
Started Jul 17 08:00:33 PM PDT 24
Finished Jul 17 08:00:53 PM PDT 24
Peak memory 206640 kb
Host smart-70911098-df1a-42d9-ba6d-b58c9de70515
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=518878470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.518878470
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.567824840
Short name T572
Test name
Test status
Simulation time 23429072035 ps
CPU time 22.39 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206732 kb
Host smart-8cbd7f66-f516-47d7-a447-cc6c56888c48
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=567824840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.567824840
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2368979789
Short name T2072
Test name
Test status
Simulation time 158528300 ps
CPU time 0.79 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:00:48 PM PDT 24
Peak memory 206460 kb
Host smart-f5dc069f-5cae-4732-8b06-f99ec260aa6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23689
79789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2368979789
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3547012777
Short name T1098
Test name
Test status
Simulation time 169149993 ps
CPU time 0.82 seconds
Started Jul 17 08:00:33 PM PDT 24
Finished Jul 17 08:00:41 PM PDT 24
Peak memory 206456 kb
Host smart-3a0e5e2b-b7b8-4754-8cd5-1ed55b5c2c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35470
12777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3547012777
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.19916162
Short name T100
Test name
Test status
Simulation time 218754019 ps
CPU time 0.92 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206460 kb
Host smart-428e6993-12e2-4628-b2f9-cc5b75bcbecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19916
162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.19916162
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2552267200
Short name T2660
Test name
Test status
Simulation time 877253751 ps
CPU time 2.16 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:00:48 PM PDT 24
Peak memory 206664 kb
Host smart-2e95f7d0-90fa-4d8a-b661-06b106e52977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25522
67200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2552267200
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3845984617
Short name T103
Test name
Test status
Simulation time 9417406695 ps
CPU time 19.16 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206712 kb
Host smart-bde4fd6b-403c-4f77-bfb5-478546d5f536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38459
84617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3845984617
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.220261077
Short name T720
Test name
Test status
Simulation time 408570157 ps
CPU time 1.27 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:00:22 PM PDT 24
Peak memory 206404 kb
Host smart-dd0c1da2-a7dd-4be1-a5e7-678115498428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22026
1077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.220261077
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.111832843
Short name T338
Test name
Test status
Simulation time 142874582 ps
CPU time 0.78 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:31 PM PDT 24
Peak memory 206460 kb
Host smart-3490c626-4a67-493f-931d-a6599ff15bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11183
2843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.111832843
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.204938431
Short name T486
Test name
Test status
Simulation time 72864780 ps
CPU time 0.69 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:00:21 PM PDT 24
Peak memory 206440 kb
Host smart-fee713ae-54ce-4b3d-99e2-fedbc9415e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20493
8431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.204938431
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2527164735
Short name T977
Test name
Test status
Simulation time 1045509218 ps
CPU time 2.45 seconds
Started Jul 17 08:00:24 PM PDT 24
Finished Jul 17 08:00:27 PM PDT 24
Peak memory 206588 kb
Host smart-7ab62ef0-a7b8-404e-b61f-bb47eb5ff233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25271
64735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2527164735
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2146299328
Short name T1180
Test name
Test status
Simulation time 357015030 ps
CPU time 2.51 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:33 PM PDT 24
Peak memory 206656 kb
Host smart-ce3fd029-cfc1-4d84-939d-74f49034434c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21462
99328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2146299328
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.4132244607
Short name T1625
Test name
Test status
Simulation time 230227718 ps
CPU time 0.88 seconds
Started Jul 17 08:00:20 PM PDT 24
Finished Jul 17 08:00:23 PM PDT 24
Peak memory 206448 kb
Host smart-fa1dab79-0869-413e-9e5a-6a193412492c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41322
44607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.4132244607
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2977391178
Short name T407
Test name
Test status
Simulation time 176127352 ps
CPU time 0.8 seconds
Started Jul 17 08:00:19 PM PDT 24
Finished Jul 17 08:00:21 PM PDT 24
Peak memory 206452 kb
Host smart-108298da-2601-4453-9d73-e805e018b33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29773
91178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2977391178
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3094413667
Short name T2651
Test name
Test status
Simulation time 198287854 ps
CPU time 0.85 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:30 PM PDT 24
Peak memory 206452 kb
Host smart-a6054499-61e4-417f-bbfc-26e866a0390d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944
13667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3094413667
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.3482495257
Short name T2256
Test name
Test status
Simulation time 9569183370 ps
CPU time 256.9 seconds
Started Jul 17 08:00:20 PM PDT 24
Finished Jul 17 08:04:39 PM PDT 24
Peak memory 206656 kb
Host smart-df0c723b-a503-4cbb-9ce8-de37d961fb60
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3482495257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.3482495257
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.1883065169
Short name T1548
Test name
Test status
Simulation time 7627059198 ps
CPU time 26.42 seconds
Started Jul 17 08:00:23 PM PDT 24
Finished Jul 17 08:00:51 PM PDT 24
Peak memory 206676 kb
Host smart-c6b254f1-7b9d-44ea-9b8a-6b827dee3632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18830
65169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.1883065169
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1034396852
Short name T822
Test name
Test status
Simulation time 167445201 ps
CPU time 0.83 seconds
Started Jul 17 08:00:32 PM PDT 24
Finished Jul 17 08:00:40 PM PDT 24
Peak memory 206440 kb
Host smart-fbba01e5-2866-4a41-96d1-a0eb91d3aee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10343
96852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1034396852
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2376081523
Short name T1070
Test name
Test status
Simulation time 23323653966 ps
CPU time 25.97 seconds
Started Jul 17 08:00:22 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206604 kb
Host smart-8bcff231-d7e7-4bf8-9fe7-fbbd18fa277d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23760
81523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2376081523
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.4181962241
Short name T559
Test name
Test status
Simulation time 3300372403 ps
CPU time 4.03 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:00:32 PM PDT 24
Peak memory 206512 kb
Host smart-5241aa07-0d3d-438c-b833-64799a585ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41819
62241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.4181962241
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1397233888
Short name T1817
Test name
Test status
Simulation time 9266009777 ps
CPU time 92.64 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:02:15 PM PDT 24
Peak memory 206720 kb
Host smart-8852132e-d899-49ce-88cb-319adcce4daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13972
33888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1397233888
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3000146610
Short name T636
Test name
Test status
Simulation time 4882443801 ps
CPU time 34.94 seconds
Started Jul 17 08:00:32 PM PDT 24
Finished Jul 17 08:01:14 PM PDT 24
Peak memory 206384 kb
Host smart-7d75d05b-a87b-40cc-9659-7dfc6aa34069
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3000146610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3000146610
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.3539076926
Short name T502
Test name
Test status
Simulation time 255087630 ps
CPU time 0.91 seconds
Started Jul 17 08:00:37 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206460 kb
Host smart-24cde8ea-82ab-4fca-9967-758f9eeecf71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3539076926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.3539076926
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1038534787
Short name T1653
Test name
Test status
Simulation time 274012216 ps
CPU time 0.96 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206276 kb
Host smart-e33ee464-b837-405e-b46c-76566f542ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10385
34787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1038534787
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1102657301
Short name T470
Test name
Test status
Simulation time 4308831874 ps
CPU time 41.7 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:01:24 PM PDT 24
Peak memory 206656 kb
Host smart-cd55fe33-5d53-472f-8501-4c2e82bd9c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11026
57301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1102657301
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2079559593
Short name T1976
Test name
Test status
Simulation time 7075091795 ps
CPU time 204.16 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:04:06 PM PDT 24
Peak memory 206664 kb
Host smart-16b8394f-1d8c-4075-8ddd-fedef99ec539
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2079559593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2079559593
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.190696910
Short name T1231
Test name
Test status
Simulation time 167599111 ps
CPU time 0.8 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206456 kb
Host smart-b60d610d-e5ab-426e-b3da-8cf9cc938832
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=190696910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.190696910
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3490997628
Short name T2636
Test name
Test status
Simulation time 179366159 ps
CPU time 0.77 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206452 kb
Host smart-07676b79-a982-4776-ac05-48f7dfd367ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
97628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3490997628
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3476783455
Short name T2653
Test name
Test status
Simulation time 210627278 ps
CPU time 0.85 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206444 kb
Host smart-0f912e46-ed47-49e8-8677-68783ded02b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34767
83455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3476783455
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2780144509
Short name T2010
Test name
Test status
Simulation time 160722714 ps
CPU time 0.84 seconds
Started Jul 17 08:00:29 PM PDT 24
Finished Jul 17 08:00:36 PM PDT 24
Peak memory 206456 kb
Host smart-3e72ee4d-a7db-48e7-b1c8-f57f90e78138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27801
44509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2780144509
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1049871862
Short name T682
Test name
Test status
Simulation time 211230312 ps
CPU time 0.89 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:34 PM PDT 24
Peak memory 206436 kb
Host smart-3b208f65-81cf-4bb0-b019-566ada1db6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10498
71862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1049871862
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3842743863
Short name T1851
Test name
Test status
Simulation time 155623974 ps
CPU time 0.77 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:36 PM PDT 24
Peak memory 206432 kb
Host smart-b5a7660c-f7e7-4978-8d4b-c2550d7714b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38427
43863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3842743863
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1539994201
Short name T2334
Test name
Test status
Simulation time 164686133 ps
CPU time 0.8 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206452 kb
Host smart-4e757d9b-db2b-41b2-985b-47c85abaa4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15399
94201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1539994201
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.4219364415
Short name T729
Test name
Test status
Simulation time 229264615 ps
CPU time 0.93 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206456 kb
Host smart-17910608-17eb-4574-be9b-a37e69cc20b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4219364415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.4219364415
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2310579792
Short name T1331
Test name
Test status
Simulation time 191429260 ps
CPU time 0.79 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206376 kb
Host smart-3ebe3744-a127-45fb-8269-b64181d58525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23105
79792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2310579792
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2457526256
Short name T2523
Test name
Test status
Simulation time 40310694 ps
CPU time 0.66 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206392 kb
Host smart-d463660a-efd9-4979-9e11-0055cc33600d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24575
26256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2457526256
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1036695444
Short name T263
Test name
Test status
Simulation time 11878382457 ps
CPU time 25.64 seconds
Started Jul 17 08:00:39 PM PDT 24
Finished Jul 17 08:01:10 PM PDT 24
Peak memory 206636 kb
Host smart-adbb5785-0f23-407b-b3a2-ba387bc42134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10366
95444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1036695444
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2249134457
Short name T2051
Test name
Test status
Simulation time 174144412 ps
CPU time 0.82 seconds
Started Jul 17 08:00:39 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206388 kb
Host smart-96625598-584d-4ff6-be13-fbf3a09763f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22491
34457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2249134457
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2700285309
Short name T665
Test name
Test status
Simulation time 251285433 ps
CPU time 0.89 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206532 kb
Host smart-b59dca92-526c-4568-a352-a64fd1323c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27002
85309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2700285309
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1503835007
Short name T663
Test name
Test status
Simulation time 239766694 ps
CPU time 0.89 seconds
Started Jul 17 08:00:30 PM PDT 24
Finished Jul 17 08:00:37 PM PDT 24
Peak memory 206448 kb
Host smart-ed320b30-51ae-4c7b-a307-9d7d49013822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15038
35007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1503835007
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3292061362
Short name T1742
Test name
Test status
Simulation time 164943801 ps
CPU time 0.8 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:49 PM PDT 24
Peak memory 206532 kb
Host smart-1869eaf7-6d4d-4f31-a910-249157152b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32920
61362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3292061362
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3639989350
Short name T915
Test name
Test status
Simulation time 214572090 ps
CPU time 0.85 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:45 PM PDT 24
Peak memory 206428 kb
Host smart-b5b58d95-8dcd-4b18-8671-1913e5c62b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36399
89350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3639989350
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1318278659
Short name T1778
Test name
Test status
Simulation time 151089188 ps
CPU time 0.75 seconds
Started Jul 17 08:00:29 PM PDT 24
Finished Jul 17 08:00:35 PM PDT 24
Peak memory 206452 kb
Host smart-34ff6a20-8e5d-433f-991d-c9aecde32300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13182
78659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1318278659
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2325243971
Short name T1065
Test name
Test status
Simulation time 146107569 ps
CPU time 0.82 seconds
Started Jul 17 08:00:36 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206252 kb
Host smart-68feb401-e0ea-4cb8-8ef9-ae5cddf0cb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23252
43971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2325243971
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.586260299
Short name T1364
Test name
Test status
Simulation time 221627501 ps
CPU time 0.94 seconds
Started Jul 17 08:00:32 PM PDT 24
Finished Jul 17 08:00:40 PM PDT 24
Peak memory 206448 kb
Host smart-e5e40bc1-5920-43f8-9331-ad7d54c148ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58626
0299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.586260299
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1779261499
Short name T1870
Test name
Test status
Simulation time 4632273873 ps
CPU time 34.96 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206728 kb
Host smart-8fad3257-df1a-49b5-bdbe-9105abde3881
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1779261499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1779261499
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.589524942
Short name T1624
Test name
Test status
Simulation time 151350451 ps
CPU time 0.78 seconds
Started Jul 17 08:00:22 PM PDT 24
Finished Jul 17 08:00:24 PM PDT 24
Peak memory 206460 kb
Host smart-7e4fc167-1323-420d-8e75-3fc5dc643bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58952
4942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.589524942
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.721617559
Short name T1989
Test name
Test status
Simulation time 189755791 ps
CPU time 0.87 seconds
Started Jul 17 08:00:17 PM PDT 24
Finished Jul 17 08:00:20 PM PDT 24
Peak memory 206444 kb
Host smart-3bc9d0f1-6510-4258-a9a8-4f5deeb61358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72161
7559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.721617559
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2622501348
Short name T2546
Test name
Test status
Simulation time 786280313 ps
CPU time 1.81 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:41 PM PDT 24
Peak memory 206620 kb
Host smart-d02ba485-bcad-4f22-a4ae-ce742b9fea62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
01348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2622501348
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3297009638
Short name T2313
Test name
Test status
Simulation time 4801176383 ps
CPU time 132.01 seconds
Started Jul 17 08:00:17 PM PDT 24
Finished Jul 17 08:02:31 PM PDT 24
Peak memory 206656 kb
Host smart-536fdaa0-c925-4afa-b8d4-48aad638cd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32970
09638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3297009638
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.3105854639
Short name T1602
Test name
Test status
Simulation time 66698877 ps
CPU time 0.69 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206420 kb
Host smart-d1d9f97d-6458-40bc-8235-ec44b9a4d930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3105854639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3105854639
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.829841877
Short name T1126
Test name
Test status
Simulation time 4395132865 ps
CPU time 5.21 seconds
Started Jul 17 08:00:15 PM PDT 24
Finished Jul 17 08:00:21 PM PDT 24
Peak memory 206440 kb
Host smart-4a9335cb-a8c3-4a9f-9e85-7fb2e1ff3b05
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=829841877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.829841877
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2692747166
Short name T2570
Test name
Test status
Simulation time 13443501783 ps
CPU time 13.87 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:00:42 PM PDT 24
Peak memory 206728 kb
Host smart-4c2b4e95-c108-498a-b693-b553294be5ce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2692747166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2692747166
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.339485057
Short name T2098
Test name
Test status
Simulation time 23381406153 ps
CPU time 23.35 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206676 kb
Host smart-10da2855-65b1-4dc8-a4f6-379ec724b285
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=339485057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.339485057
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.4033005874
Short name T2554
Test name
Test status
Simulation time 169737800 ps
CPU time 0.85 seconds
Started Jul 17 08:00:28 PM PDT 24
Finished Jul 17 08:00:32 PM PDT 24
Peak memory 206460 kb
Host smart-e358ffe4-a902-465c-852a-bc662d598396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40330
05874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.4033005874
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1327201077
Short name T202
Test name
Test status
Simulation time 180816186 ps
CPU time 0.8 seconds
Started Jul 17 08:00:20 PM PDT 24
Finished Jul 17 08:00:23 PM PDT 24
Peak memory 206448 kb
Host smart-26b79db0-eee6-4a63-ac1e-9538d572d54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13272
01077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1327201077
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2874502133
Short name T635
Test name
Test status
Simulation time 294933823 ps
CPU time 1.07 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:38 PM PDT 24
Peak memory 206452 kb
Host smart-ef9f7be0-88a5-4635-9793-641f135e2d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745
02133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2874502133
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2187261605
Short name T2579
Test name
Test status
Simulation time 511430246 ps
CPU time 1.27 seconds
Started Jul 17 08:00:20 PM PDT 24
Finished Jul 17 08:00:23 PM PDT 24
Peak memory 206468 kb
Host smart-e6ae7f5a-cc18-44a8-9087-0f0f0c7f48fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21872
61605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2187261605
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1548498528
Short name T2488
Test name
Test status
Simulation time 8381547239 ps
CPU time 15.19 seconds
Started Jul 17 08:00:31 PM PDT 24
Finished Jul 17 08:00:52 PM PDT 24
Peak memory 206708 kb
Host smart-dad23af4-9dba-4d21-8a4f-5660178cb480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15484
98528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1548498528
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3474691124
Short name T2571
Test name
Test status
Simulation time 424673411 ps
CPU time 1.25 seconds
Started Jul 17 08:00:25 PM PDT 24
Finished Jul 17 08:00:28 PM PDT 24
Peak memory 206456 kb
Host smart-e16ef489-ef7b-4607-a100-f49d2b59e3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34746
91124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3474691124
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3637715132
Short name T943
Test name
Test status
Simulation time 138320314 ps
CPU time 0.74 seconds
Started Jul 17 08:00:32 PM PDT 24
Finished Jul 17 08:00:40 PM PDT 24
Peak memory 206448 kb
Host smart-4e235f8e-36e7-46bf-8ce5-382b622383db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36377
15132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3637715132
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1598630113
Short name T540
Test name
Test status
Simulation time 37539040 ps
CPU time 0.66 seconds
Started Jul 17 08:00:27 PM PDT 24
Finished Jul 17 08:00:30 PM PDT 24
Peak memory 206396 kb
Host smart-1c72738b-efbd-4198-ac88-1ea716498d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15986
30113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1598630113
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1664779164
Short name T2575
Test name
Test status
Simulation time 738219978 ps
CPU time 1.87 seconds
Started Jul 17 08:00:38 PM PDT 24
Finished Jul 17 08:00:46 PM PDT 24
Peak memory 206600 kb
Host smart-70fa6778-ed46-444c-80b3-bbb3235f81a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16647
79164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1664779164
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1108175329
Short name T84
Test name
Test status
Simulation time 167872170 ps
CPU time 1.64 seconds
Started Jul 17 08:00:34 PM PDT 24
Finished Jul 17 08:00:43 PM PDT 24
Peak memory 206744 kb
Host smart-8d26108c-7189-4f8e-a309-ddf741804ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
75329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1108175329
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3459722272
Short name T2187
Test name
Test status
Simulation time 171679089 ps
CPU time 0.82 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:00:47 PM PDT 24
Peak memory 206424 kb
Host smart-c865a6b1-b741-4f71-a83f-02d1aebe436f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34597
22272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3459722272
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3992078669
Short name T1001
Test name
Test status
Simulation time 148217143 ps
CPU time 0.76 seconds
Started Jul 17 08:00:48 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206464 kb
Host smart-816e87ee-040b-4216-956d-a77fe8311af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39920
78669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3992078669
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.14076885
Short name T2587
Test name
Test status
Simulation time 264364808 ps
CPU time 0.95 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206444 kb
Host smart-2cbd71ca-19f5-46c0-ba4e-2f137a6c8f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14076
885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.14076885
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.2775383787
Short name T1749
Test name
Test status
Simulation time 8352755395 ps
CPU time 53.84 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:01:50 PM PDT 24
Peak memory 206704 kb
Host smart-00f67d08-fee9-43b2-b5e9-27841bea211c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2775383787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2775383787
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.1384698051
Short name T375
Test name
Test status
Simulation time 7080198813 ps
CPU time 25.26 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:01:17 PM PDT 24
Peak memory 206608 kb
Host smart-d54006bc-0eb3-4087-acd8-218dc2239a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
98051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.1384698051
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1805813142
Short name T2315
Test name
Test status
Simulation time 208715677 ps
CPU time 0.85 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:00:47 PM PDT 24
Peak memory 206428 kb
Host smart-36f156aa-acba-4abe-bbb7-fcda4e49df33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18058
13142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1805813142
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.4101756156
Short name T708
Test name
Test status
Simulation time 23311683371 ps
CPU time 23.69 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:01:16 PM PDT 24
Peak memory 206460 kb
Host smart-e5db43fa-26c6-42ea-8d34-7304e65a0e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41017
56156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.4101756156
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3104550606
Short name T2103
Test name
Test status
Simulation time 3338451210 ps
CPU time 4.19 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:00:55 PM PDT 24
Peak memory 206532 kb
Host smart-e04af09b-732b-4b64-b66a-874a4a4e259e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31045
50606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3104550606
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1542908048
Short name T1242
Test name
Test status
Simulation time 7383694894 ps
CPU time 53.12 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:01:45 PM PDT 24
Peak memory 206724 kb
Host smart-a4c3f482-2bf3-4506-92dd-a1d42911ff0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15429
08048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1542908048
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.937210576
Short name T1401
Test name
Test status
Simulation time 3969304690 ps
CPU time 38.14 seconds
Started Jul 17 08:00:42 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206652 kb
Host smart-a0d02d3b-11fa-414d-b0ce-1dd0a2357973
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=937210576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.937210576
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.4206987071
Short name T2089
Test name
Test status
Simulation time 260625388 ps
CPU time 0.92 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206404 kb
Host smart-b7e48ad9-5541-4b7d-8639-2f28c6abac6d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4206987071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.4206987071
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1552116986
Short name T2320
Test name
Test status
Simulation time 223741042 ps
CPU time 0.87 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206328 kb
Host smart-21392dfb-644a-4908-8dfe-0529d5bf5bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15521
16986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1552116986
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3787695914
Short name T1762
Test name
Test status
Simulation time 3912406438 ps
CPU time 106.75 seconds
Started Jul 17 08:00:41 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206660 kb
Host smart-1e585886-39bc-498e-b94b-c63e74a598c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37876
95914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3787695914
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2384874047
Short name T1609
Test name
Test status
Simulation time 2958243087 ps
CPU time 82.49 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:02:18 PM PDT 24
Peak memory 206580 kb
Host smart-21862b35-6c2a-47df-81e6-b344ea06e9a3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2384874047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2384874047
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3110968720
Short name T728
Test name
Test status
Simulation time 199033177 ps
CPU time 0.89 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206448 kb
Host smart-1e43be96-c64c-44a2-826e-2bb5af5c1321
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3110968720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3110968720
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.4193246433
Short name T1521
Test name
Test status
Simulation time 186715113 ps
CPU time 0.82 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:00:52 PM PDT 24
Peak memory 206460 kb
Host smart-98783b48-230c-4513-8331-c958a59fa0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
46433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.4193246433
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2798623185
Short name T110
Test name
Test status
Simulation time 197869187 ps
CPU time 0.86 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:00:52 PM PDT 24
Peak memory 206448 kb
Host smart-a5fdc9c7-4577-45e0-b3db-61227a1cb754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27986
23185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2798623185
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1374669452
Short name T2179
Test name
Test status
Simulation time 156169254 ps
CPU time 0.76 seconds
Started Jul 17 08:00:48 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206416 kb
Host smart-be2fcadb-ebfc-4416-8bcd-b2677225c6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13746
69452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1374669452
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1369928758
Short name T1292
Test name
Test status
Simulation time 186568816 ps
CPU time 0.88 seconds
Started Jul 17 08:00:43 PM PDT 24
Finished Jul 17 08:00:49 PM PDT 24
Peak memory 206428 kb
Host smart-e0115de6-3187-493e-956e-47723e6b1726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13699
28758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1369928758
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3305886163
Short name T1083
Test name
Test status
Simulation time 170149105 ps
CPU time 0.81 seconds
Started Jul 17 08:00:48 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206440 kb
Host smart-e32a3575-aa64-4d13-b04b-25f69a6c46fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33058
86163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3305886163
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1336544325
Short name T541
Test name
Test status
Simulation time 179919558 ps
CPU time 0.86 seconds
Started Jul 17 08:00:48 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206408 kb
Host smart-8af66393-2009-4a57-a394-354246b8456b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13365
44325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1336544325
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.512870064
Short name T1172
Test name
Test status
Simulation time 199114508 ps
CPU time 0.93 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206464 kb
Host smart-42bd9788-d449-43b2-8c25-1ecaeb80a97e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=512870064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.512870064
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.210189130
Short name T575
Test name
Test status
Simulation time 140752980 ps
CPU time 0.76 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:00:52 PM PDT 24
Peak memory 206392 kb
Host smart-a77f9ec2-552c-4a28-ab65-002ca0b94add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21018
9130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.210189130
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.18053766
Short name T38
Test name
Test status
Simulation time 94595049 ps
CPU time 0.7 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:00:53 PM PDT 24
Peak memory 206428 kb
Host smart-47953b10-a4b6-4e4d-a8f3-d23050fa5914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18053
766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.18053766
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3159898694
Short name T262
Test name
Test status
Simulation time 22325737822 ps
CPU time 50.03 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:01:41 PM PDT 24
Peak memory 214796 kb
Host smart-2ac9861f-f00c-452c-9f77-6ccd27189819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31598
98694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3159898694
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.781690273
Short name T1720
Test name
Test status
Simulation time 178359793 ps
CPU time 0.82 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:00:51 PM PDT 24
Peak memory 206464 kb
Host smart-dec1595e-51f9-4f7b-b039-19ecb4414b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78169
0273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.781690273
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3058506663
Short name T345
Test name
Test status
Simulation time 216526357 ps
CPU time 0.83 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:00:54 PM PDT 24
Peak memory 206444 kb
Host smart-c3c3686a-48e4-4c0d-9e90-9e6ceac9bd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30585
06663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3058506663
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.871761270
Short name T1700
Test name
Test status
Simulation time 232025422 ps
CPU time 0.89 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:00:53 PM PDT 24
Peak memory 206456 kb
Host smart-8351adcb-5b63-4fb5-84d9-8ed99abe6011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87176
1270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.871761270
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3341702006
Short name T1896
Test name
Test status
Simulation time 207156091 ps
CPU time 0.83 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:00:54 PM PDT 24
Peak memory 206456 kb
Host smart-6f85b651-2b3a-4da6-a1f7-83b8b193077e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33417
02006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3341702006
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2071348606
Short name T77
Test name
Test status
Simulation time 196005461 ps
CPU time 0.83 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206432 kb
Host smart-7fe45fd0-16ae-4aa0-b7f9-021631346b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20713
48606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2071348606
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1995248298
Short name T1125
Test name
Test status
Simulation time 153947041 ps
CPU time 0.77 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:00:53 PM PDT 24
Peak memory 206448 kb
Host smart-83c33336-f314-4b39-9bb4-c1e4729c6e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19952
48298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1995248298
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3241183012
Short name T2753
Test name
Test status
Simulation time 155075942 ps
CPU time 0.84 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:00:51 PM PDT 24
Peak memory 206460 kb
Host smart-7e2ee8b3-ec92-4eae-823a-df0960909cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32411
83012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3241183012
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2728409873
Short name T2233
Test name
Test status
Simulation time 288360787 ps
CPU time 0.99 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:00:50 PM PDT 24
Peak memory 206460 kb
Host smart-ea0a1e51-295d-47d9-826c-c8b812e95d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27284
09873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2728409873
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2042459262
Short name T620
Test name
Test status
Simulation time 3910295141 ps
CPU time 28.86 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:01:18 PM PDT 24
Peak memory 206644 kb
Host smart-9d687b5d-e8e6-4be0-90e3-be4e389c22f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2042459262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2042459262
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.212326341
Short name T590
Test name
Test status
Simulation time 202810261 ps
CPU time 0.83 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:00:54 PM PDT 24
Peak memory 206420 kb
Host smart-9210ec60-ac19-43d4-9cc8-285ddcf93fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21232
6341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.212326341
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2330866372
Short name T2600
Test name
Test status
Simulation time 146055591 ps
CPU time 0.77 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:00:51 PM PDT 24
Peak memory 206456 kb
Host smart-f4ad8ba4-5da8-4817-8c35-d0d9775d1bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23308
66372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2330866372
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2125526447
Short name T2049
Test name
Test status
Simulation time 1226879400 ps
CPU time 2.74 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206600 kb
Host smart-b9cbc789-2019-4203-916f-5c352c122d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21255
26447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2125526447
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3851254772
Short name T1410
Test name
Test status
Simulation time 6527311067 ps
CPU time 46.05 seconds
Started Jul 17 08:00:44 PM PDT 24
Finished Jul 17 08:01:35 PM PDT 24
Peak memory 206724 kb
Host smart-ffca3b69-7a8a-40c4-ba22-d6dff8a3299f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38512
54772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3851254772
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.3649087411
Short name T1848
Test name
Test status
Simulation time 69273806 ps
CPU time 0.69 seconds
Started Jul 17 08:00:53 PM PDT 24
Finished Jul 17 08:01:00 PM PDT 24
Peak memory 206424 kb
Host smart-92e6985b-4c33-47f8-899b-98976b6700f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3649087411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3649087411
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.619489155
Short name T1729
Test name
Test status
Simulation time 4346997979 ps
CPU time 4.91 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:00:59 PM PDT 24
Peak memory 206492 kb
Host smart-984cb3a9-6587-4931-8f86-a70d11f9cb67
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=619489155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.619489155
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1455278364
Short name T214
Test name
Test status
Simulation time 13461544646 ps
CPU time 12.83 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:01:03 PM PDT 24
Peak memory 206672 kb
Host smart-8a0b5bab-4190-4cff-8eb6-2bc7cd0e73e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1455278364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1455278364
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1813828637
Short name T387
Test name
Test status
Simulation time 23376494701 ps
CPU time 22.55 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206708 kb
Host smart-253df5a6-f64b-4c4b-845f-9d5fa099430e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1813828637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1813828637
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.49859201
Short name T911
Test name
Test status
Simulation time 149530253 ps
CPU time 0.79 seconds
Started Jul 17 08:00:50 PM PDT 24
Finished Jul 17 08:00:58 PM PDT 24
Peak memory 206456 kb
Host smart-67c7a6f8-b047-4607-8ada-a5c933cbe4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49859
201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.49859201
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2153786550
Short name T1495
Test name
Test status
Simulation time 187617452 ps
CPU time 0.79 seconds
Started Jul 17 08:00:48 PM PDT 24
Finished Jul 17 08:00:55 PM PDT 24
Peak memory 206460 kb
Host smart-1e160fb5-9ea4-421a-8d8c-3a1bff00de3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21537
86550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2153786550
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.4203510663
Short name T491
Test name
Test status
Simulation time 267322938 ps
CPU time 1.03 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:00:52 PM PDT 24
Peak memory 206460 kb
Host smart-2abbd056-f615-4ea6-a449-3578e2325de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42035
10663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.4203510663
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.765927053
Short name T1668
Test name
Test status
Simulation time 1041311365 ps
CPU time 2.31 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:00:55 PM PDT 24
Peak memory 206608 kb
Host smart-98df2d45-f9dc-4f22-95ac-447ce320d68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76592
7053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.765927053
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3180938898
Short name T2537
Test name
Test status
Simulation time 6957918964 ps
CPU time 14.79 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206708 kb
Host smart-6db81555-4ac7-44ef-80d7-9ca37b590d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31809
38898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3180938898
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1206383023
Short name T2475
Test name
Test status
Simulation time 425826890 ps
CPU time 1.37 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:00:53 PM PDT 24
Peak memory 206456 kb
Host smart-0bd51ab1-3454-446c-a660-abbf24079847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12063
83023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1206383023
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3056945664
Short name T2519
Test name
Test status
Simulation time 192815764 ps
CPU time 0.8 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206404 kb
Host smart-e241b66d-911c-4fc4-91bb-b82e041bc9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30569
45664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3056945664
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3309377135
Short name T1128
Test name
Test status
Simulation time 37797455 ps
CPU time 0.68 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:00:59 PM PDT 24
Peak memory 206448 kb
Host smart-3ed1ef21-e025-4dcf-b3b6-0b6267dea1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33093
77135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3309377135
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.703485343
Short name T855
Test name
Test status
Simulation time 876300460 ps
CPU time 2.23 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:02 PM PDT 24
Peak memory 206568 kb
Host smart-125765b8-14f2-41a1-8993-233d6ce1b321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70348
5343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.703485343
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1220973758
Short name T1529
Test name
Test status
Simulation time 190989591 ps
CPU time 1.23 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:00:54 PM PDT 24
Peak memory 206592 kb
Host smart-f38dc6cb-1053-43f1-9e2c-d3d426d150eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12209
73758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1220973758
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2260388352
Short name T1149
Test name
Test status
Simulation time 237199336 ps
CPU time 0.91 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206364 kb
Host smart-ed56f989-ca18-44a4-b57d-22e6d4fc3c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22603
88352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2260388352
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2244508481
Short name T2196
Test name
Test status
Simulation time 151346323 ps
CPU time 0.75 seconds
Started Jul 17 08:00:50 PM PDT 24
Finished Jul 17 08:00:58 PM PDT 24
Peak memory 206448 kb
Host smart-7fd017a9-a498-4e7c-8dfd-039d7494c560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22445
08481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2244508481
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.222516618
Short name T1747
Test name
Test status
Simulation time 219319988 ps
CPU time 0.87 seconds
Started Jul 17 08:00:50 PM PDT 24
Finished Jul 17 08:00:58 PM PDT 24
Peak memory 206452 kb
Host smart-9a1f7b0f-703c-4a24-85b0-942becf822be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22251
6618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.222516618
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3640170356
Short name T2036
Test name
Test status
Simulation time 238765919 ps
CPU time 0.86 seconds
Started Jul 17 08:00:46 PM PDT 24
Finished Jul 17 08:00:53 PM PDT 24
Peak memory 206444 kb
Host smart-96ce7675-6a21-4cfa-b525-fd4451ea25df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36401
70356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3640170356
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1200082975
Short name T592
Test name
Test status
Simulation time 23351162419 ps
CPU time 22.82 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206516 kb
Host smart-4e97fa4a-1da9-4a25-9b79-462bc2ee9881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12000
82975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1200082975
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.993425314
Short name T846
Test name
Test status
Simulation time 3327420869 ps
CPU time 3.91 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:01:00 PM PDT 24
Peak memory 206408 kb
Host smart-3bce6656-c544-4ea8-b57f-b4e02257abee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99342
5314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.993425314
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2674246276
Short name T1490
Test name
Test status
Simulation time 7549070986 ps
CPU time 50.77 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:51 PM PDT 24
Peak memory 206564 kb
Host smart-777aa56d-d176-4686-806e-b5b60411c38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26742
46276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2674246276
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.440462656
Short name T869
Test name
Test status
Simulation time 4318093349 ps
CPU time 29.92 seconds
Started Jul 17 08:00:50 PM PDT 24
Finished Jul 17 08:01:27 PM PDT 24
Peak memory 206708 kb
Host smart-489e9129-6955-4fd7-b10f-25dacdc2024e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=440462656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.440462656
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3152848294
Short name T1825
Test name
Test status
Simulation time 234552680 ps
CPU time 0.87 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206432 kb
Host smart-92c3dbcb-043c-4922-b10e-daab90bbe14a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3152848294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3152848294
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1715628189
Short name T2540
Test name
Test status
Simulation time 191009361 ps
CPU time 0.88 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:00:59 PM PDT 24
Peak memory 206452 kb
Host smart-1996e0cd-b9c0-4b49-8dd6-bf03338340bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17156
28189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1715628189
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1444772958
Short name T928
Test name
Test status
Simulation time 5372303317 ps
CPU time 136 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:03:14 PM PDT 24
Peak memory 206672 kb
Host smart-4f4efe84-4299-4a8b-8614-f072bf308a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
72958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1444772958
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3306707372
Short name T2730
Test name
Test status
Simulation time 2859868401 ps
CPU time 26.65 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:01:22 PM PDT 24
Peak memory 206588 kb
Host smart-d6cbebce-780b-46e0-9dbf-b438a51ebc09
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3306707372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3306707372
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2850672773
Short name T1656
Test name
Test status
Simulation time 181888634 ps
CPU time 0.82 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:00:59 PM PDT 24
Peak memory 206448 kb
Host smart-df5dd1a7-e1d8-4d15-af59-f80bbb0e4615
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2850672773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2850672773
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1886359398
Short name T1222
Test name
Test status
Simulation time 197962229 ps
CPU time 0.79 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:00:59 PM PDT 24
Peak memory 206456 kb
Host smart-9c30446a-187f-4c5b-a732-ad3d5639ceb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18863
59398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1886359398
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2461824173
Short name T124
Test name
Test status
Simulation time 220829521 ps
CPU time 0.89 seconds
Started Jul 17 08:00:48 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206412 kb
Host smart-6c75ac19-8b17-42ef-83b2-1b8e556996c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24618
24173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2461824173
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2716724657
Short name T2119
Test name
Test status
Simulation time 202038005 ps
CPU time 0.84 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:00:59 PM PDT 24
Peak memory 206452 kb
Host smart-d126b160-0eb2-4ed3-be05-565c9f622179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
24657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2716724657
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.127897165
Short name T2261
Test name
Test status
Simulation time 194340314 ps
CPU time 0.85 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:00:59 PM PDT 24
Peak memory 206452 kb
Host smart-f4eab496-dc9a-4aa5-923e-ec603a8c6e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12789
7165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.127897165
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2563888624
Short name T1457
Test name
Test status
Simulation time 161590571 ps
CPU time 0.78 seconds
Started Jul 17 08:00:51 PM PDT 24
Finished Jul 17 08:00:59 PM PDT 24
Peak memory 206452 kb
Host smart-2b882c40-c9c7-4d35-9979-93700a7a1378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25638
88624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2563888624
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1779399948
Short name T730
Test name
Test status
Simulation time 157987266 ps
CPU time 0.8 seconds
Started Jul 17 08:00:43 PM PDT 24
Finished Jul 17 08:00:49 PM PDT 24
Peak memory 206540 kb
Host smart-7da52bff-a885-4d4b-b7d7-d3fa4db41f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17793
99948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1779399948
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.2206244317
Short name T2509
Test name
Test status
Simulation time 229062820 ps
CPU time 0.94 seconds
Started Jul 17 08:00:56 PM PDT 24
Finished Jul 17 08:01:02 PM PDT 24
Peak memory 206256 kb
Host smart-04065656-10c7-41bc-8396-f930fc3a36a1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2206244317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.2206244317
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3853079548
Short name T1480
Test name
Test status
Simulation time 156867943 ps
CPU time 0.76 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206460 kb
Host smart-518e45a8-7d19-42be-9aa0-f96bc13ab931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
79548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3853079548
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1569689423
Short name T2216
Test name
Test status
Simulation time 48713090 ps
CPU time 0.67 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206452 kb
Host smart-bea725f0-e8dd-4bf1-876a-181e02765868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15696
89423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1569689423
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1410821822
Short name T1766
Test name
Test status
Simulation time 9924477259 ps
CPU time 22.07 seconds
Started Jul 17 08:00:56 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206836 kb
Host smart-ab4fa7e4-0713-4df5-aefc-6d2846b7c97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14108
21822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1410821822
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1263078237
Short name T605
Test name
Test status
Simulation time 197183741 ps
CPU time 0.86 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206460 kb
Host smart-8a4e2515-2fbe-41db-94ab-018226de25d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12630
78237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1263078237
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2939111792
Short name T1479
Test name
Test status
Simulation time 206607914 ps
CPU time 0.89 seconds
Started Jul 17 08:00:48 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206448 kb
Host smart-ab526015-ad41-4944-b7e9-bbb1dd5fa136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29391
11792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2939111792
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.521704065
Short name T1642
Test name
Test status
Simulation time 197182829 ps
CPU time 0.85 seconds
Started Jul 17 08:00:45 PM PDT 24
Finished Jul 17 08:00:51 PM PDT 24
Peak memory 206464 kb
Host smart-7033ecc6-1008-4902-a52b-f67b692f9fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52170
4065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.521704065
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.128492523
Short name T2310
Test name
Test status
Simulation time 155075625 ps
CPU time 0.79 seconds
Started Jul 17 08:00:50 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206460 kb
Host smart-212db5d7-70d7-4c50-a152-339c4bf4bd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
2523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.128492523
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2314237629
Short name T638
Test name
Test status
Simulation time 140503080 ps
CPU time 0.79 seconds
Started Jul 17 08:00:56 PM PDT 24
Finished Jul 17 08:01:02 PM PDT 24
Peak memory 206320 kb
Host smart-68967897-7bf6-44e0-ad26-406850780dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23142
37629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2314237629
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.4272002016
Short name T781
Test name
Test status
Simulation time 154631547 ps
CPU time 0.79 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206456 kb
Host smart-c7ec73e8-6e7d-477f-9c69-5d4982f1c093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42720
02016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.4272002016
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.802463408
Short name T1551
Test name
Test status
Simulation time 198155125 ps
CPU time 0.85 seconds
Started Jul 17 08:00:56 PM PDT 24
Finished Jul 17 08:01:02 PM PDT 24
Peak memory 206604 kb
Host smart-8758c7a9-1bd2-4c65-ab38-bd63cd1a8c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80246
3408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.802463408
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1936667568
Short name T2130
Test name
Test status
Simulation time 242966791 ps
CPU time 0.93 seconds
Started Jul 17 08:00:50 PM PDT 24
Finished Jul 17 08:00:58 PM PDT 24
Peak memory 206456 kb
Host smart-67d8e9f3-4145-4ea2-b183-1f8a0aff1771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19366
67568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1936667568
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1348553422
Short name T1855
Test name
Test status
Simulation time 5941100406 ps
CPU time 55.86 seconds
Started Jul 17 08:00:42 PM PDT 24
Finished Jul 17 08:01:43 PM PDT 24
Peak memory 206648 kb
Host smart-d084aed2-226a-43cd-91cc-935416c0a6f3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1348553422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1348553422
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2292913067
Short name T1112
Test name
Test status
Simulation time 189509344 ps
CPU time 0.82 seconds
Started Jul 17 08:00:48 PM PDT 24
Finished Jul 17 08:00:56 PM PDT 24
Peak memory 206456 kb
Host smart-bfb77078-9b53-42d5-b8db-cef8736f1f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929
13067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2292913067
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1148449252
Short name T2604
Test name
Test status
Simulation time 169392795 ps
CPU time 0.85 seconds
Started Jul 17 08:00:56 PM PDT 24
Finished Jul 17 08:01:02 PM PDT 24
Peak memory 206588 kb
Host smart-5e8030fd-91bb-40eb-b017-02422dcdeab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11484
49252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1148449252
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1541689692
Short name T602
Test name
Test status
Simulation time 718171801 ps
CPU time 1.8 seconds
Started Jul 17 08:00:55 PM PDT 24
Finished Jul 17 08:01:03 PM PDT 24
Peak memory 206796 kb
Host smart-a948a27f-b445-4d05-a3f1-32d8570b0a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
89692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1541689692
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2451666468
Short name T2112
Test name
Test status
Simulation time 4585392892 ps
CPU time 32.85 seconds
Started Jul 17 08:00:43 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206700 kb
Host smart-fac1cd6f-1fad-42c1-a230-af1cc404597c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24516
66468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2451666468
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1836609651
Short name T2582
Test name
Test status
Simulation time 63405640 ps
CPU time 0.7 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206420 kb
Host smart-a43aeea7-2cce-4b98-815b-26bcdac40104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1836609651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1836609651
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1218028822
Short name T574
Test name
Test status
Simulation time 4057272567 ps
CPU time 4.5 seconds
Started Jul 17 07:54:03 PM PDT 24
Finished Jul 17 07:54:13 PM PDT 24
Peak memory 206436 kb
Host smart-e16def1b-535d-4d4b-8530-98371871f071
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1218028822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.1218028822
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.133790874
Short name T983
Test name
Test status
Simulation time 13425551752 ps
CPU time 11.99 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:15 PM PDT 24
Peak memory 206704 kb
Host smart-d7036631-869b-42b4-8585-1d889508eac0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=133790874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.133790874
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.519623974
Short name T2700
Test name
Test status
Simulation time 23379031956 ps
CPU time 22.62 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:54:27 PM PDT 24
Peak memory 206516 kb
Host smart-50ea94a7-f8a0-4de7-afbc-5f47f8b3fc36
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=519623974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.519623974
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.4098624444
Short name T23
Test name
Test status
Simulation time 165023002 ps
CPU time 0.8 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:07 PM PDT 24
Peak memory 206428 kb
Host smart-209452be-aba8-4c9c-af5c-78a2802da6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40986
24444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.4098624444
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.4203983328
Short name T50
Test name
Test status
Simulation time 226969481 ps
CPU time 0.86 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:03 PM PDT 24
Peak memory 206448 kb
Host smart-010acacd-9f01-4d25-b96f-a5eb0ec9acad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42039
83328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.4203983328
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.3023863713
Short name T65
Test name
Test status
Simulation time 212231876 ps
CPU time 0.8 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:07 PM PDT 24
Peak memory 206440 kb
Host smart-6c0cdcab-f328-44ec-8bba-bffcdba20313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30238
63713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.3023863713
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3043562766
Short name T1503
Test name
Test status
Simulation time 167219290 ps
CPU time 0.79 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206452 kb
Host smart-00491a44-6e7f-4916-a0d3-2c33395d564d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30435
62766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3043562766
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1810445802
Short name T2678
Test name
Test status
Simulation time 298259038 ps
CPU time 1.11 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206432 kb
Host smart-5f62b88c-123b-46a3-ac0a-4f7a28738b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18104
45802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1810445802
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1914728254
Short name T563
Test name
Test status
Simulation time 314042110 ps
CPU time 1.06 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:07 PM PDT 24
Peak memory 206448 kb
Host smart-41cc597f-38fd-4c53-87f7-13e070219a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19147
28254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1914728254
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.465408213
Short name T1074
Test name
Test status
Simulation time 13076273684 ps
CPU time 25.72 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:33 PM PDT 24
Peak memory 206724 kb
Host smart-cfc9e6d9-a9ea-49ab-a56f-9f43c328d3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46540
8213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.465408213
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1479641225
Short name T386
Test name
Test status
Simulation time 412992997 ps
CPU time 1.25 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206456 kb
Host smart-026d78a8-c829-4c11-ae7a-d8f7eb0a7b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14796
41225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1479641225
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3545783392
Short name T2386
Test name
Test status
Simulation time 149433625 ps
CPU time 0.75 seconds
Started Jul 17 07:54:03 PM PDT 24
Finished Jul 17 07:54:10 PM PDT 24
Peak memory 206456 kb
Host smart-0725b6ea-20ed-4e3c-bda3-59648d808749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35457
83392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3545783392
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3861026443
Short name T376
Test name
Test status
Simulation time 50112744 ps
CPU time 0.68 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:10 PM PDT 24
Peak memory 206532 kb
Host smart-becd32c3-4600-4697-a888-e8bccd44c579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38610
26443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3861026443
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3948229457
Short name T1041
Test name
Test status
Simulation time 795431819 ps
CPU time 1.8 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:11 PM PDT 24
Peak memory 206592 kb
Host smart-219650a1-22e7-45eb-b1c5-55c4eeabb4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39482
29457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3948229457
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2401976799
Short name T2063
Test name
Test status
Simulation time 152598692 ps
CPU time 1.13 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:11 PM PDT 24
Peak memory 206592 kb
Host smart-94cfb72d-820d-4286-b210-e6ff666c023e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24019
76799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2401976799
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2599972125
Short name T837
Test name
Test status
Simulation time 104237188773 ps
CPU time 142.88 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:56:35 PM PDT 24
Peak memory 206648 kb
Host smart-0ac8abeb-d88d-42c1-ab04-58cec9f9eac1
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2599972125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2599972125
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.977356107
Short name T1699
Test name
Test status
Simulation time 91287306438 ps
CPU time 151.36 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:56:44 PM PDT 24
Peak memory 206668 kb
Host smart-afbc974d-e45b-4bc6-aede-1773febe1de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977356107 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.977356107
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.3893335425
Short name T1086
Test name
Test status
Simulation time 82111531088 ps
CPU time 113.97 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:56:05 PM PDT 24
Peak memory 206676 kb
Host smart-bf3ed4ee-ecb4-424f-8d83-8d6192f89139
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3893335425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3893335425
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.772344818
Short name T1181
Test name
Test status
Simulation time 112892738689 ps
CPU time 164.97 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:56:55 PM PDT 24
Peak memory 206680 kb
Host smart-f34d793b-c951-4baa-864d-b8efdd3c69ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772344818 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.772344818
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3178486604
Short name T2070
Test name
Test status
Simulation time 108109674965 ps
CPU time 145.56 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:56:38 PM PDT 24
Peak memory 206652 kb
Host smart-d8d14bbf-7061-4cfd-9122-8a4ace380409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31784
86604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3178486604
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.4210454862
Short name T735
Test name
Test status
Simulation time 174792954 ps
CPU time 0.79 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206456 kb
Host smart-62ae9324-b835-47f9-877c-2a94cac9714c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42104
54862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.4210454862
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1759827352
Short name T892
Test name
Test status
Simulation time 179822356 ps
CPU time 0.77 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:54:13 PM PDT 24
Peak memory 206432 kb
Host smart-b1571d4f-99ea-4e70-b883-fb7dda7f26e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17598
27352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1759827352
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3327693209
Short name T893
Test name
Test status
Simulation time 189591624 ps
CPU time 0.89 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206448 kb
Host smart-638db5ac-7ac7-43bd-bc9e-51fc4ff47e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33276
93209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3327693209
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.2405442861
Short name T1111
Test name
Test status
Simulation time 6731058481 ps
CPU time 23.73 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:39 PM PDT 24
Peak memory 206712 kb
Host smart-c98528ff-8c73-44ff-b494-8fd60b59eaaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24054
42861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.2405442861
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3019445259
Short name T2743
Test name
Test status
Simulation time 214277718 ps
CPU time 0.93 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206424 kb
Host smart-e6b5a918-4a01-4103-b5ef-acf9502a2c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30194
45259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3019445259
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.943429003
Short name T607
Test name
Test status
Simulation time 23306897314 ps
CPU time 23.31 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:37 PM PDT 24
Peak memory 206508 kb
Host smart-75bf5f72-af1a-44c4-b693-e21afa325a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94342
9003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.943429003
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1165650882
Short name T2439
Test name
Test status
Simulation time 3312497730 ps
CPU time 4.13 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:20 PM PDT 24
Peak memory 206388 kb
Host smart-02b6b203-1192-463c-ae2c-a2b330812620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
50882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1165650882
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3036230963
Short name T1584
Test name
Test status
Simulation time 7799675082 ps
CPU time 69.1 seconds
Started Jul 17 07:54:07 PM PDT 24
Finished Jul 17 07:55:23 PM PDT 24
Peak memory 206728 kb
Host smart-2ad670ce-b6f5-40b3-8abf-109bb4c68830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30362
30963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3036230963
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2770912683
Short name T1452
Test name
Test status
Simulation time 7425346486 ps
CPU time 206.07 seconds
Started Jul 17 07:54:07 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206652 kb
Host smart-c88e6e58-63f5-42e5-afaa-a83a97c512da
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2770912683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2770912683
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2125827719
Short name T2715
Test name
Test status
Simulation time 235095557 ps
CPU time 0.87 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206452 kb
Host smart-850b24f8-5ac0-41b8-93ec-aa8272585d45
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2125827719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2125827719
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3095207938
Short name T2088
Test name
Test status
Simulation time 201007347 ps
CPU time 0.87 seconds
Started Jul 17 07:54:07 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206172 kb
Host smart-16847429-5c48-4756-b285-8502dcbbe806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30952
07938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3095207938
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.549756255
Short name T1397
Test name
Test status
Simulation time 6957516058 ps
CPU time 63.66 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:55:19 PM PDT 24
Peak memory 206556 kb
Host smart-dad8f601-29cc-4f98-b6f9-384c19dc54a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54975
6255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.549756255
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3815564808
Short name T1182
Test name
Test status
Simulation time 4608769258 ps
CPU time 40.51 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:55 PM PDT 24
Peak memory 206620 kb
Host smart-a63382af-f698-4d67-b474-74477bd608de
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3815564808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3815564808
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.704546673
Short name T1047
Test name
Test status
Simulation time 152487580 ps
CPU time 0.77 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206244 kb
Host smart-9ce717c1-7090-4600-80f3-5a2e7ea094c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=704546673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.704546673
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1274545958
Short name T2220
Test name
Test status
Simulation time 155229427 ps
CPU time 0.77 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206460 kb
Host smart-5ab31158-d4c7-4cf6-a6f3-e21ab93e1392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12745
45958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1274545958
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3796885166
Short name T98
Test name
Test status
Simulation time 176159465 ps
CPU time 0.82 seconds
Started Jul 17 07:54:03 PM PDT 24
Finished Jul 17 07:54:10 PM PDT 24
Peak memory 206536 kb
Host smart-ec9aeec0-0376-439c-aa8c-1e60bd66b30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37968
85166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3796885166
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2163103366
Short name T1233
Test name
Test status
Simulation time 155766470 ps
CPU time 0.76 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206460 kb
Host smart-44fb554b-7241-4a1a-a6c0-23c0b155bfce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
03366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2163103366
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2665634645
Short name T788
Test name
Test status
Simulation time 178465192 ps
CPU time 0.85 seconds
Started Jul 17 07:54:10 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206376 kb
Host smart-f6177ee7-78b7-4415-9475-b985dc618022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26656
34645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2665634645
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1073280498
Short name T2173
Test name
Test status
Simulation time 185362547 ps
CPU time 0.79 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206460 kb
Host smart-f175e680-ec6c-47f6-a4ee-91a0dbc02bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10732
80498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1073280498
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.171098864
Short name T1788
Test name
Test status
Simulation time 174855223 ps
CPU time 0.76 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206464 kb
Host smart-97450150-0341-48ee-871a-a302757387d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17109
8864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.171098864
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3894378583
Short name T2619
Test name
Test status
Simulation time 221388952 ps
CPU time 0.89 seconds
Started Jul 17 07:54:10 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206464 kb
Host smart-d5472705-c1af-4767-b10f-bf652edf3ede
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3894378583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3894378583
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3471355716
Short name T191
Test name
Test status
Simulation time 231237790 ps
CPU time 0.96 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206468 kb
Host smart-a6714d61-8377-4f23-a710-da744728d9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34713
55716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3471355716
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.4204751289
Short name T2720
Test name
Test status
Simulation time 182107488 ps
CPU time 0.85 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:54:13 PM PDT 24
Peak memory 206468 kb
Host smart-33003cf6-8b41-4fb9-97ce-ec77e9f9342e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42047
51289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.4204751289
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.529115719
Short name T1986
Test name
Test status
Simulation time 38125229 ps
CPU time 0.68 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:54:06 PM PDT 24
Peak memory 206432 kb
Host smart-1ef6e399-237a-4344-af89-8f88fa2c8cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52911
5719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.529115719
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1320178787
Short name T1066
Test name
Test status
Simulation time 21130476447 ps
CPU time 47 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:55:02 PM PDT 24
Peak memory 206708 kb
Host smart-c4bfc006-453d-41d4-8766-c209c4897d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13201
78787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1320178787
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3804036604
Short name T1443
Test name
Test status
Simulation time 204492016 ps
CPU time 0.87 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:03 PM PDT 24
Peak memory 206460 kb
Host smart-0e22f8be-876e-481a-940c-79742b742477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38040
36604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3804036604
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3781089938
Short name T2493
Test name
Test status
Simulation time 214994555 ps
CPU time 0.97 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:04 PM PDT 24
Peak memory 206448 kb
Host smart-9db3e053-155f-4067-b5e0-e6f05af29e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37810
89938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3781089938
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1908441607
Short name T172
Test name
Test status
Simulation time 8173980320 ps
CPU time 51.59 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:54:57 PM PDT 24
Peak memory 206668 kb
Host smart-af860faf-e108-4bef-bbda-e047fb028486
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1908441607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1908441607
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1930121448
Short name T2745
Test name
Test status
Simulation time 7327910915 ps
CPU time 105.75 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:55:47 PM PDT 24
Peak memory 206724 kb
Host smart-66aa0077-0039-4d71-b1ac-a13ebc8b7761
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1930121448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1930121448
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2643640601
Short name T1845
Test name
Test status
Simulation time 17597977580 ps
CPU time 132.38 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:56:15 PM PDT 24
Peak memory 206708 kb
Host smart-ae64f73b-05e2-4c98-8204-329bdcff125b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2643640601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2643640601
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1846112248
Short name T775
Test name
Test status
Simulation time 168994189 ps
CPU time 0.81 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:03 PM PDT 24
Peak memory 206464 kb
Host smart-9cfbc8c4-52fe-45ae-b28a-10ce22fc9b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18461
12248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1846112248
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1128574898
Short name T1021
Test name
Test status
Simulation time 218718502 ps
CPU time 0.88 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:09 PM PDT 24
Peak memory 206436 kb
Host smart-b4475bb2-9d73-4986-a3e5-d5f32199bdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11285
74898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1128574898
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3968795205
Short name T1987
Test name
Test status
Simulation time 182475170 ps
CPU time 0.8 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:09 PM PDT 24
Peak memory 206436 kb
Host smart-ecb9c14d-e1e2-47aa-a2e6-4b8d58535aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39687
95205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3968795205
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.4165023235
Short name T78
Test name
Test status
Simulation time 182895058 ps
CPU time 0.87 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:07 PM PDT 24
Peak memory 206432 kb
Host smart-6121d2b4-868d-4d22-acdc-1a9b59e03a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41650
23235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.4165023235
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3362894110
Short name T183
Test name
Test status
Simulation time 306882039 ps
CPU time 1.21 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:01 PM PDT 24
Peak memory 224288 kb
Host smart-b5d53c06-e0a0-4608-a43f-b424d67614a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3362894110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3362894110
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.3031913458
Short name T55
Test name
Test status
Simulation time 390397921 ps
CPU time 1.25 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206428 kb
Host smart-563c9db5-7204-4ee7-a3c1-39c379ea6fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30319
13458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3031913458
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3726145233
Short name T826
Test name
Test status
Simulation time 206326583 ps
CPU time 0.9 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:09 PM PDT 24
Peak memory 206432 kb
Host smart-96614e19-4538-43b2-917e-359cc0cc1a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37261
45233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3726145233
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.283861612
Short name T1696
Test name
Test status
Simulation time 158981630 ps
CPU time 0.79 seconds
Started Jul 17 07:54:03 PM PDT 24
Finished Jul 17 07:54:09 PM PDT 24
Peak memory 206428 kb
Host smart-00612683-9403-4c2a-b605-2bb9b7779645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28386
1612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.283861612
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3162615895
Short name T2655
Test name
Test status
Simulation time 162982666 ps
CPU time 0.81 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206448 kb
Host smart-7b9cf9b2-2fa8-4909-9090-aeb83d9b85e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31626
15895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3162615895
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.299052946
Short name T2371
Test name
Test status
Simulation time 188415677 ps
CPU time 0.84 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:12 PM PDT 24
Peak memory 206532 kb
Host smart-0b70018f-9342-49c4-bcc3-a8ebde773ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29905
2946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.299052946
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.562046352
Short name T1263
Test name
Test status
Simulation time 5923838655 ps
CPU time 41.41 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:51 PM PDT 24
Peak memory 206732 kb
Host smart-b943874e-0291-49dd-b8bc-d656dcdb0627
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=562046352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.562046352
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.799055008
Short name T1826
Test name
Test status
Simulation time 155671290 ps
CPU time 0.78 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:10 PM PDT 24
Peak memory 206448 kb
Host smart-0546b007-e605-4a62-ad5b-0104f7d5df11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79905
5008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.799055008
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2063678512
Short name T329
Test name
Test status
Simulation time 181195029 ps
CPU time 0.82 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:10 PM PDT 24
Peak memory 206440 kb
Host smart-ca6fa9d5-a87b-4a95-a95f-b323c5c211ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20636
78512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2063678512
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.4014550851
Short name T515
Test name
Test status
Simulation time 421193393 ps
CPU time 1.17 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:11 PM PDT 24
Peak memory 206448 kb
Host smart-86434a56-db03-4bff-b7bd-ae01398aa653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40145
50851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.4014550851
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1050889577
Short name T1482
Test name
Test status
Simulation time 7169339977 ps
CPU time 192.61 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:57:24 PM PDT 24
Peak memory 206660 kb
Host smart-b36eff65-6a30-477c-bfa0-0feb59c35bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10508
89577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1050889577
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1426652931
Short name T168
Test name
Test status
Simulation time 7797446007 ps
CPU time 68.76 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:55:21 PM PDT 24
Peak memory 206732 kb
Host smart-38fedcb1-f705-4c9b-a27d-ccb6abc12607
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1426652931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1426652931
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.2016278024
Short name T1550
Test name
Test status
Simulation time 68926669 ps
CPU time 0.68 seconds
Started Jul 17 08:01:15 PM PDT 24
Finished Jul 17 08:01:18 PM PDT 24
Peak memory 206436 kb
Host smart-5796b150-d29c-4b1c-a621-f23416371802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2016278024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.2016278024
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1516068058
Short name T2698
Test name
Test status
Simulation time 3591590611 ps
CPU time 4.24 seconds
Started Jul 17 08:01:03 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206668 kb
Host smart-6ffd7532-9aae-4e1d-b46c-f0a951154428
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1516068058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1516068058
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1783714097
Short name T465
Test name
Test status
Simulation time 13331599705 ps
CPU time 12.64 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:12 PM PDT 24
Peak memory 206284 kb
Host smart-2a1f1a5e-ce3c-4070-a3ef-f6f028945592
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1783714097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1783714097
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.977979439
Short name T13
Test name
Test status
Simulation time 23443598857 ps
CPU time 22.61 seconds
Started Jul 17 08:00:56 PM PDT 24
Finished Jul 17 08:01:24 PM PDT 24
Peak memory 206788 kb
Host smart-1061670a-d2d7-4327-8d31-290c758513ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=977979439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.977979439
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1952183722
Short name T1843
Test name
Test status
Simulation time 248796914 ps
CPU time 0.85 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206440 kb
Host smart-1ea4cc5f-152a-4845-8de4-44a32c8ad54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
83722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1952183722
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3897987012
Short name T1095
Test name
Test status
Simulation time 183870355 ps
CPU time 0.81 seconds
Started Jul 17 08:00:53 PM PDT 24
Finished Jul 17 08:01:00 PM PDT 24
Peak memory 206452 kb
Host smart-28b7f906-0ea2-46a9-b0e6-5e0d15881aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38979
87012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3897987012
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1089681424
Short name T1581
Test name
Test status
Simulation time 517599994 ps
CPU time 1.5 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:02 PM PDT 24
Peak memory 206496 kb
Host smart-2a7a2838-830d-4165-b784-3fce38673abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10896
81424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1089681424
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.4070293491
Short name T961
Test name
Test status
Simulation time 435319259 ps
CPU time 1.16 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 206428 kb
Host smart-5c5a1027-3cb9-4eeb-bce4-c72ebd0bb067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40702
93491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.4070293491
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3813812037
Short name T1157
Test name
Test status
Simulation time 17474881996 ps
CPU time 31.34 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:32 PM PDT 24
Peak memory 206520 kb
Host smart-ad0c3837-3d6c-4e29-8b93-7a0b6367173e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138
12037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3813812037
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2354084229
Short name T2230
Test name
Test status
Simulation time 494394412 ps
CPU time 1.48 seconds
Started Jul 17 08:00:54 PM PDT 24
Finished Jul 17 08:01:02 PM PDT 24
Peak memory 206456 kb
Host smart-769eb29b-f2e3-4599-bb4a-5992275a7ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23540
84229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2354084229
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.809779582
Short name T631
Test name
Test status
Simulation time 191224287 ps
CPU time 0.81 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:00:55 PM PDT 24
Peak memory 206460 kb
Host smart-ac9880a9-b72b-434d-b2cf-6ae945c1e686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80977
9582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.809779582
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.404160465
Short name T2156
Test name
Test status
Simulation time 38929268 ps
CPU time 0.65 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206396 kb
Host smart-a91a7098-ffff-4899-b4cf-0c3a84c227e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40416
0465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.404160465
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.4125465956
Short name T1122
Test name
Test status
Simulation time 669352380 ps
CPU time 1.69 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:00:55 PM PDT 24
Peak memory 206612 kb
Host smart-97cd67e5-114d-4c5f-af2a-a9f6a46e804f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41254
65956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.4125465956
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1884607969
Short name T2706
Test name
Test status
Simulation time 260641916 ps
CPU time 1.77 seconds
Started Jul 17 08:00:47 PM PDT 24
Finished Jul 17 08:00:55 PM PDT 24
Peak memory 206588 kb
Host smart-58639e4a-d820-4bb3-91e1-79da08b97094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18846
07969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1884607969
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2280509757
Short name T596
Test name
Test status
Simulation time 253988808 ps
CPU time 0.92 seconds
Started Jul 17 08:00:49 PM PDT 24
Finished Jul 17 08:00:57 PM PDT 24
Peak memory 206408 kb
Host smart-267c14e5-e9a2-49c1-a8a6-3121ff74afbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22805
09757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2280509757
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3000947958
Short name T614
Test name
Test status
Simulation time 160325468 ps
CPU time 0.79 seconds
Started Jul 17 08:01:01 PM PDT 24
Finished Jul 17 08:01:03 PM PDT 24
Peak memory 206448 kb
Host smart-93118d91-b90e-4e84-821f-f2385893d6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30009
47958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3000947958
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2009402992
Short name T460
Test name
Test status
Simulation time 205297550 ps
CPU time 0.91 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206460 kb
Host smart-05d2fe8e-3612-4205-91b5-b961d52f7c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20094
02992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2009402992
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.204512290
Short name T2171
Test name
Test status
Simulation time 10826924308 ps
CPU time 82.18 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:02:44 PM PDT 24
Peak memory 206700 kb
Host smart-da4d9aca-2aaa-4235-aa9b-a049ca0b20dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20451
2290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.204512290
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2536893058
Short name T1672
Test name
Test status
Simulation time 179942311 ps
CPU time 0.81 seconds
Started Jul 17 08:01:08 PM PDT 24
Finished Jul 17 08:01:10 PM PDT 24
Peak memory 206448 kb
Host smart-7086925f-cf0b-4114-9271-a3e8601f7484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25368
93058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2536893058
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1283949047
Short name T1823
Test name
Test status
Simulation time 23275707480 ps
CPU time 22.04 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206488 kb
Host smart-29693726-cccc-4ba2-b5ca-2acae8ec9671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12839
49047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1283949047
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2279256067
Short name T1697
Test name
Test status
Simulation time 3318667393 ps
CPU time 3.79 seconds
Started Jul 17 08:01:01 PM PDT 24
Finished Jul 17 08:01:06 PM PDT 24
Peak memory 206512 kb
Host smart-e2f1d9ca-7380-459d-ae0d-53ae0e418929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22792
56067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2279256067
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2659141425
Short name T879
Test name
Test status
Simulation time 9153951825 ps
CPU time 265.17 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:05:32 PM PDT 24
Peak memory 206748 kb
Host smart-9177c3c6-e00b-489f-ac12-e4bffe59c9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
41425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2659141425
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2175039627
Short name T2656
Test name
Test status
Simulation time 4881560654 ps
CPU time 33.27 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:58 PM PDT 24
Peak memory 206468 kb
Host smart-956b7908-0028-4616-8c4f-cd6cf8ce23ce
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2175039627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2175039627
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.1014971503
Short name T566
Test name
Test status
Simulation time 251940371 ps
CPU time 0.95 seconds
Started Jul 17 08:01:03 PM PDT 24
Finished Jul 17 08:01:05 PM PDT 24
Peak memory 206420 kb
Host smart-306e366e-6908-4766-8aee-7693e53e7dda
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1014971503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.1014971503
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.4234289607
Short name T2675
Test name
Test status
Simulation time 181105863 ps
CPU time 0.83 seconds
Started Jul 17 08:01:15 PM PDT 24
Finished Jul 17 08:01:17 PM PDT 24
Peak memory 206456 kb
Host smart-b9ad5450-e04c-493b-bc8a-1e05def29a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42342
89607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.4234289607
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.385379497
Short name T1959
Test name
Test status
Simulation time 4221923782 ps
CPU time 113.82 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:03:18 PM PDT 24
Peak memory 206648 kb
Host smart-875fe1f9-1508-438b-a5c8-eeebabf98d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38537
9497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.385379497
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.943987502
Short name T1433
Test name
Test status
Simulation time 5154664972 ps
CPU time 37.16 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:56 PM PDT 24
Peak memory 206720 kb
Host smart-2fa83776-e622-4287-8ad7-eac43091bbb3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=943987502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.943987502
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3237254278
Short name T2062
Test name
Test status
Simulation time 171907304 ps
CPU time 0.79 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206396 kb
Host smart-198601ce-d629-4449-8c38-397d5bb283ea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3237254278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3237254278
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1114622714
Short name T1208
Test name
Test status
Simulation time 159406212 ps
CPU time 0.77 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:13 PM PDT 24
Peak memory 206436 kb
Host smart-4d10cfa4-c7a1-43e8-ae0a-8adf3422e366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11146
22714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1114622714
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2524103290
Short name T121
Test name
Test status
Simulation time 242094922 ps
CPU time 0.86 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:14 PM PDT 24
Peak memory 206440 kb
Host smart-cb88c660-3e19-47e4-93c2-a26ec868e675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25241
03290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2524103290
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.860013520
Short name T94
Test name
Test status
Simulation time 188592647 ps
CPU time 0.82 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206424 kb
Host smart-ca5afe1f-787c-4a75-b80c-f74482b9c849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86001
3520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.860013520
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.365753141
Short name T2484
Test name
Test status
Simulation time 229832314 ps
CPU time 0.86 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:20 PM PDT 24
Peak memory 206460 kb
Host smart-15808e96-57ed-4d04-aa42-c0e51a31aabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575
3141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.365753141
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2012040987
Short name T510
Test name
Test status
Simulation time 200099419 ps
CPU time 0.88 seconds
Started Jul 17 08:01:02 PM PDT 24
Finished Jul 17 08:01:04 PM PDT 24
Peak memory 206452 kb
Host smart-80516346-806b-4915-b54a-bab2e3bb5769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
40987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2012040987
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2519146432
Short name T1821
Test name
Test status
Simulation time 144540231 ps
CPU time 0.78 seconds
Started Jul 17 08:01:03 PM PDT 24
Finished Jul 17 08:01:05 PM PDT 24
Peak memory 206456 kb
Host smart-a23bdce8-44f5-44d1-b366-65ea5d529d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25191
46432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2519146432
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3693418375
Short name T1415
Test name
Test status
Simulation time 209674851 ps
CPU time 0.91 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:13 PM PDT 24
Peak memory 206420 kb
Host smart-106b982f-8f2e-454c-81f5-f58fbe261b74
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3693418375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3693418375
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2071464503
Short name T2489
Test name
Test status
Simulation time 145381219 ps
CPU time 0.77 seconds
Started Jul 17 08:01:04 PM PDT 24
Finished Jul 17 08:01:06 PM PDT 24
Peak memory 206448 kb
Host smart-15b4de4f-0d34-4c76-8d83-87e1e285a384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20714
64503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2071464503
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.223740185
Short name T2218
Test name
Test status
Simulation time 35619924 ps
CPU time 0.66 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:19 PM PDT 24
Peak memory 206432 kb
Host smart-374a4ed9-d002-47ff-aff1-d16ff9ab8202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22374
0185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.223740185
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3133071572
Short name T239
Test name
Test status
Simulation time 17962172544 ps
CPU time 38.77 seconds
Started Jul 17 08:00:59 PM PDT 24
Finished Jul 17 08:01:41 PM PDT 24
Peak memory 206884 kb
Host smart-972d8b3f-ba8a-40f4-90ab-d401d4e5b0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31330
71572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3133071572
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3744659689
Short name T2552
Test name
Test status
Simulation time 149163575 ps
CPU time 0.79 seconds
Started Jul 17 08:01:01 PM PDT 24
Finished Jul 17 08:01:04 PM PDT 24
Peak memory 206448 kb
Host smart-dc9d9490-f4d1-4a84-830a-95c8daf9639b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37446
59689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3744659689
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3760781731
Short name T33
Test name
Test status
Simulation time 237242031 ps
CPU time 0.91 seconds
Started Jul 17 08:01:07 PM PDT 24
Finished Jul 17 08:01:10 PM PDT 24
Peak memory 206400 kb
Host smart-3b71db7e-a9dc-4c7a-8f22-0d9fb067e86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37607
81731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3760781731
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.4247473826
Short name T397
Test name
Test status
Simulation time 204875474 ps
CPU time 0.93 seconds
Started Jul 17 08:01:01 PM PDT 24
Finished Jul 17 08:01:04 PM PDT 24
Peak memory 206460 kb
Host smart-64681335-c5f5-4130-8c0f-4d81bcaa300b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474
73826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.4247473826
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2344116824
Short name T448
Test name
Test status
Simulation time 176672759 ps
CPU time 0.83 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:12 PM PDT 24
Peak memory 206416 kb
Host smart-7b631917-895d-4e8e-87b3-fab1f070d728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23441
16824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2344116824
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3675765530
Short name T815
Test name
Test status
Simulation time 140507079 ps
CPU time 0.75 seconds
Started Jul 17 08:01:07 PM PDT 24
Finished Jul 17 08:01:09 PM PDT 24
Peak memory 206448 kb
Host smart-81e6442c-6597-4cd7-b738-4b309f7e7e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36757
65530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3675765530
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.589425956
Short name T1758
Test name
Test status
Simulation time 154711776 ps
CPU time 0.76 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:07 PM PDT 24
Peak memory 206456 kb
Host smart-50c392d9-9f42-4a36-9c30-101456c2bce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58942
5956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.589425956
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.986362609
Short name T1704
Test name
Test status
Simulation time 182990292 ps
CPU time 0.8 seconds
Started Jul 17 08:01:09 PM PDT 24
Finished Jul 17 08:01:11 PM PDT 24
Peak memory 206448 kb
Host smart-47cb7acd-2f28-4823-ae96-fdfe6e8baa40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98636
2609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.986362609
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1904678462
Short name T1303
Test name
Test status
Simulation time 232630226 ps
CPU time 0.94 seconds
Started Jul 17 08:01:07 PM PDT 24
Finished Jul 17 08:01:10 PM PDT 24
Peak memory 206360 kb
Host smart-74c3c3ac-29d5-48fe-addd-bdc9dab0cc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19046
78462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1904678462
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.4017781326
Short name T690
Test name
Test status
Simulation time 5929168578 ps
CPU time 52.44 seconds
Started Jul 17 08:01:02 PM PDT 24
Finished Jul 17 08:01:56 PM PDT 24
Peak memory 206648 kb
Host smart-9f285cf5-863c-4b83-b427-bac2b59d704b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4017781326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.4017781326
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.4211089915
Short name T532
Test name
Test status
Simulation time 166717950 ps
CPU time 0.84 seconds
Started Jul 17 08:01:12 PM PDT 24
Finished Jul 17 08:01:14 PM PDT 24
Peak memory 206472 kb
Host smart-2d8c8f4b-b2f1-4dad-8030-87a379531800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42110
89915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.4211089915
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1426969177
Short name T1858
Test name
Test status
Simulation time 166233159 ps
CPU time 0.8 seconds
Started Jul 17 08:01:07 PM PDT 24
Finished Jul 17 08:01:09 PM PDT 24
Peak memory 206416 kb
Host smart-0cbe33c5-1740-4fde-8e4b-bac2ca4d75ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14269
69177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1426969177
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.2607557188
Short name T2020
Test name
Test status
Simulation time 377562279 ps
CPU time 1.33 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:14 PM PDT 24
Peak memory 206176 kb
Host smart-54e54ea9-2184-442e-88f8-7d23c20a4e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26075
57188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.2607557188
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1576994487
Short name T372
Test name
Test status
Simulation time 4667680448 ps
CPU time 130.41 seconds
Started Jul 17 08:01:15 PM PDT 24
Finished Jul 17 08:03:27 PM PDT 24
Peak memory 206668 kb
Host smart-a7c0c260-9e9b-429f-b0e6-359462f02de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
94487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1576994487
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1166952047
Short name T975
Test name
Test status
Simulation time 42180839 ps
CPU time 0.65 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:20 PM PDT 24
Peak memory 206428 kb
Host smart-69ea4af4-bd48-47b4-a952-0e5ed33684ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1166952047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1166952047
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3061063622
Short name T988
Test name
Test status
Simulation time 3919230790 ps
CPU time 5.12 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:12 PM PDT 24
Peak memory 206668 kb
Host smart-d63d4dbf-1343-4165-984a-85f2e77e4430
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3061063622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3061063622
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2622477420
Short name T2143
Test name
Test status
Simulation time 13490893945 ps
CPU time 13.35 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206652 kb
Host smart-03c353ef-260d-422f-8f8d-273cbae2a930
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2622477420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2622477420
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1467191458
Short name T500
Test name
Test status
Simulation time 23427329141 ps
CPU time 27.46 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206520 kb
Host smart-383c9f16-2d05-4cbd-8a2c-cdfb25417b93
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1467191458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.1467191458
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2971684879
Short name T1307
Test name
Test status
Simulation time 154268795 ps
CPU time 0.78 seconds
Started Jul 17 08:01:04 PM PDT 24
Finished Jul 17 08:01:06 PM PDT 24
Peak memory 206448 kb
Host smart-f2c784c6-47e1-4f71-a59f-0ee398c94b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29716
84879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2971684879
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3445657451
Short name T2478
Test name
Test status
Simulation time 154390663 ps
CPU time 0.76 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206456 kb
Host smart-6bce78e3-5273-45c2-b496-86eeebfbdfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34456
57451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3445657451
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2265975601
Short name T1053
Test name
Test status
Simulation time 292262377 ps
CPU time 1.06 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206196 kb
Host smart-1ef31b78-fe04-4114-aa77-1e1839b2c761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22659
75601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2265975601
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1985555759
Short name T522
Test name
Test status
Simulation time 274770012 ps
CPU time 0.88 seconds
Started Jul 17 08:01:01 PM PDT 24
Finished Jul 17 08:01:03 PM PDT 24
Peak memory 206540 kb
Host smart-02523fc1-26ac-4629-a0ea-bae94d165dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19855
55759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1985555759
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2168310134
Short name T1213
Test name
Test status
Simulation time 20369850903 ps
CPU time 37.87 seconds
Started Jul 17 08:01:01 PM PDT 24
Finished Jul 17 08:01:41 PM PDT 24
Peak memory 206724 kb
Host smart-45c3fc89-d915-4c8b-b1e5-60fe598ea5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21683
10134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2168310134
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.1376967512
Short name T2331
Test name
Test status
Simulation time 437370912 ps
CPU time 1.27 seconds
Started Jul 17 08:01:03 PM PDT 24
Finished Jul 17 08:01:05 PM PDT 24
Peak memory 206456 kb
Host smart-85b0a15d-4835-4a1e-992a-80b848726545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13769
67512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.1376967512
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3533421213
Short name T2480
Test name
Test status
Simulation time 134984906 ps
CPU time 0.73 seconds
Started Jul 17 08:01:15 PM PDT 24
Finished Jul 17 08:01:17 PM PDT 24
Peak memory 206460 kb
Host smart-7347e178-44ca-4ee8-a322-d02a43f805a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35334
21213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3533421213
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2423173516
Short name T1025
Test name
Test status
Simulation time 38980564 ps
CPU time 0.69 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:13 PM PDT 24
Peak memory 206160 kb
Host smart-6e4419a5-a547-483d-bc9c-77d9a3158212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24231
73516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2423173516
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.703604952
Short name T1565
Test name
Test status
Simulation time 812874859 ps
CPU time 1.94 seconds
Started Jul 17 08:01:10 PM PDT 24
Finished Jul 17 08:01:13 PM PDT 24
Peak memory 206740 kb
Host smart-73381729-9797-4df8-abcd-bc092fc529ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70360
4952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.703604952
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2898597439
Short name T306
Test name
Test status
Simulation time 181219963 ps
CPU time 1.92 seconds
Started Jul 17 08:01:03 PM PDT 24
Finished Jul 17 08:01:06 PM PDT 24
Peak memory 206724 kb
Host smart-f21c2b7c-6db3-4b55-af08-3df8b8010825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28985
97439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2898597439
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.236502981
Short name T932
Test name
Test status
Simulation time 237747226 ps
CPU time 0.86 seconds
Started Jul 17 08:01:15 PM PDT 24
Finished Jul 17 08:01:18 PM PDT 24
Peak memory 206456 kb
Host smart-afa97666-a960-4193-9fde-5ecf07b5a977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23650
2981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.236502981
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.4293173187
Short name T543
Test name
Test status
Simulation time 146380092 ps
CPU time 0.81 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:20 PM PDT 24
Peak memory 206456 kb
Host smart-8a5fa69e-9ced-49a9-9883-f66704417b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42931
73187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.4293173187
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1234175356
Short name T1611
Test name
Test status
Simulation time 203594483 ps
CPU time 0.84 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:25 PM PDT 24
Peak memory 206208 kb
Host smart-cb8614fa-8946-400e-8fa5-8a5a0684d404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12341
75356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1234175356
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2517966668
Short name T546
Test name
Test status
Simulation time 4906497853 ps
CPU time 44.67 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:51 PM PDT 24
Peak memory 206700 kb
Host smart-0c5ad76f-9d28-4908-8bd7-2a1d60108474
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2517966668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2517966668
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.3243872471
Short name T1640
Test name
Test status
Simulation time 6101157426 ps
CPU time 22.88 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:36 PM PDT 24
Peak memory 206708 kb
Host smart-978e344b-e770-4e36-ba7c-d983ea9d0c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32438
72471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.3243872471
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2468011983
Short name T1449
Test name
Test status
Simulation time 195746253 ps
CPU time 0.87 seconds
Started Jul 17 08:01:12 PM PDT 24
Finished Jul 17 08:01:15 PM PDT 24
Peak memory 206452 kb
Host smart-7af1511c-efcd-4bcd-a2aa-cfd10a736447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680
11983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2468011983
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.949529558
Short name T2430
Test name
Test status
Simulation time 23285222830 ps
CPU time 23.01 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:30 PM PDT 24
Peak memory 206516 kb
Host smart-3e70de80-4521-46ba-a111-efb3b17b8c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94952
9558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.949529558
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.720173826
Short name T1982
Test name
Test status
Simulation time 3301957401 ps
CPU time 4.18 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206516 kb
Host smart-f9d074f0-0701-41c8-9031-5f6037ee331e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72017
3826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.720173826
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1938962503
Short name T917
Test name
Test status
Simulation time 9938075364 ps
CPU time 70.88 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206732 kb
Host smart-1ed9b693-9af8-42dd-9eb3-0a1b1bfb2d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19389
62503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1938962503
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2272349767
Short name T629
Test name
Test status
Simulation time 5291639786 ps
CPU time 50.77 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:02:15 PM PDT 24
Peak memory 206396 kb
Host smart-b21931ae-9bdc-45cc-b26a-a2192c9397f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2272349767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2272349767
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.2017402602
Short name T817
Test name
Test status
Simulation time 243771887 ps
CPU time 0.93 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206444 kb
Host smart-489f55c5-678c-4dcd-867b-583944020a14
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2017402602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.2017402602
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.451585305
Short name T972
Test name
Test status
Simulation time 211140777 ps
CPU time 0.89 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206432 kb
Host smart-9bf41175-99ce-4661-bfde-89eacf7863b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45158
5305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.451585305
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.719400392
Short name T139
Test name
Test status
Simulation time 4277840252 ps
CPU time 28.85 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:54 PM PDT 24
Peak memory 206704 kb
Host smart-6b91a60d-a653-41d2-bc06-ad3eb3344bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71940
0392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.719400392
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.440030966
Short name T1714
Test name
Test status
Simulation time 3962106014 ps
CPU time 36.81 seconds
Started Jul 17 08:01:02 PM PDT 24
Finished Jul 17 08:01:40 PM PDT 24
Peak memory 206672 kb
Host smart-fcf8c743-5369-4a53-bc37-c32fbfb67f42
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=440030966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.440030966
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2613762902
Short name T359
Test name
Test status
Simulation time 159771629 ps
CPU time 0.8 seconds
Started Jul 17 08:01:07 PM PDT 24
Finished Jul 17 08:01:09 PM PDT 24
Peak memory 206372 kb
Host smart-9f39239b-59b0-4f96-8aac-fa3b70290d89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2613762902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2613762902
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.913562283
Short name T2577
Test name
Test status
Simulation time 142833549 ps
CPU time 0.78 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206452 kb
Host smart-66f0eb06-7a1d-4ab5-a09d-0980261b1268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91356
2283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.913562283
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2239080982
Short name T128
Test name
Test status
Simulation time 166760055 ps
CPU time 0.83 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206452 kb
Host smart-ba2d27fc-bacc-44af-8f92-2db5b924440f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22390
80982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2239080982
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2122710937
Short name T1296
Test name
Test status
Simulation time 153437040 ps
CPU time 0.78 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206452 kb
Host smart-21f0ed6b-0323-4788-b0a5-e6d278f7cad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21227
10937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2122710937
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2238830333
Short name T526
Test name
Test status
Simulation time 164781990 ps
CPU time 0.79 seconds
Started Jul 17 08:01:13 PM PDT 24
Finished Jul 17 08:01:15 PM PDT 24
Peak memory 206452 kb
Host smart-94792e9f-b576-41cb-822f-7d2430a0769a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
30333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2238830333
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3326633138
Short name T2659
Test name
Test status
Simulation time 255143368 ps
CPU time 0.89 seconds
Started Jul 17 08:01:13 PM PDT 24
Finished Jul 17 08:01:16 PM PDT 24
Peak memory 206392 kb
Host smart-e0c18634-7953-4a8b-89f6-fa26fe6d8056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33266
33138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3326633138
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1120622640
Short name T2067
Test name
Test status
Simulation time 156994696 ps
CPU time 0.79 seconds
Started Jul 17 08:01:13 PM PDT 24
Finished Jul 17 08:01:16 PM PDT 24
Peak memory 206460 kb
Host smart-7c6ebad7-8f6f-4786-b914-5142983be9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11206
22640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1120622640
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3531486921
Short name T1228
Test name
Test status
Simulation time 222392006 ps
CPU time 0.95 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206452 kb
Host smart-cf7c3fbb-cd4d-48a5-8952-6d7482b69218
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3531486921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3531486921
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2509999545
Short name T1970
Test name
Test status
Simulation time 147076488 ps
CPU time 0.78 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206452 kb
Host smart-77a4a203-d131-4fac-9c18-cf4a6fe27fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25099
99545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2509999545
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3336262197
Short name T2164
Test name
Test status
Simulation time 79297389 ps
CPU time 0.65 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:22 PM PDT 24
Peak memory 206444 kb
Host smart-0f8ee149-b6f7-465e-9e0b-0fb5c37fe7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33362
62197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3336262197
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3673890319
Short name T713
Test name
Test status
Simulation time 8957175001 ps
CPU time 22.11 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:47 PM PDT 24
Peak memory 206272 kb
Host smart-c6e46a86-81a6-44fd-ae5a-a9efa7847449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36738
90319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3673890319
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.174779508
Short name T2392
Test name
Test status
Simulation time 193233102 ps
CPU time 0.92 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206448 kb
Host smart-c48aa8bc-bc91-4606-9231-05a542e4ad46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17477
9508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.174779508
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2990849489
Short name T1438
Test name
Test status
Simulation time 231458591 ps
CPU time 0.87 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:25 PM PDT 24
Peak memory 206460 kb
Host smart-6a353947-cc95-425f-aad9-894e7bf4930a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29908
49489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2990849489
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3976123457
Short name T1321
Test name
Test status
Simulation time 203019092 ps
CPU time 0.82 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:20 PM PDT 24
Peak memory 206452 kb
Host smart-1918f82d-3215-4d67-8cd1-ea90f9792f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39761
23457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3976123457
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3619064331
Short name T1834
Test name
Test status
Simulation time 226177139 ps
CPU time 0.84 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:24 PM PDT 24
Peak memory 206440 kb
Host smart-dde91ee9-2bbd-4899-98e2-92b577d0c5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36190
64331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3619064331
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.4095418651
Short name T1868
Test name
Test status
Simulation time 187480240 ps
CPU time 0.84 seconds
Started Jul 17 08:01:07 PM PDT 24
Finished Jul 17 08:01:10 PM PDT 24
Peak memory 206436 kb
Host smart-29d31b33-d527-4436-bd4e-d285f4a02a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40954
18651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.4095418651
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.137936616
Short name T1763
Test name
Test status
Simulation time 188162248 ps
CPU time 0.8 seconds
Started Jul 17 08:01:08 PM PDT 24
Finished Jul 17 08:01:10 PM PDT 24
Peak memory 206440 kb
Host smart-d1f30378-ad0d-46d9-be4c-66405bbd24a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13793
6616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.137936616
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2319710760
Short name T1978
Test name
Test status
Simulation time 151139240 ps
CPU time 0.78 seconds
Started Jul 17 08:01:10 PM PDT 24
Finished Jul 17 08:01:11 PM PDT 24
Peak memory 206592 kb
Host smart-bec5ef34-5ffc-4097-91d2-a91f36eecb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23197
10760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2319710760
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.321755434
Short name T2346
Test name
Test status
Simulation time 225659883 ps
CPU time 0.92 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:22 PM PDT 24
Peak memory 206448 kb
Host smart-e386475f-e006-43a3-b694-9c38f58aee0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32175
5434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.321755434
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.321905272
Short name T360
Test name
Test status
Simulation time 5828046918 ps
CPU time 159.03 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:03:45 PM PDT 24
Peak memory 206672 kb
Host smart-5e015628-394f-4694-9baa-296096fa654f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=321905272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.321905272
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2043723382
Short name T2477
Test name
Test status
Simulation time 225715770 ps
CPU time 0.86 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206440 kb
Host smart-be198be1-b17c-426a-a7f3-accd63adc23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20437
23382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2043723382
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.610476962
Short name T2625
Test name
Test status
Simulation time 170458074 ps
CPU time 0.78 seconds
Started Jul 17 08:01:10 PM PDT 24
Finished Jul 17 08:01:12 PM PDT 24
Peak memory 206416 kb
Host smart-9c5ec398-17b0-4aac-9473-b7b8272e0808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61047
6962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.610476962
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.2403324056
Short name T1717
Test name
Test status
Simulation time 1231775257 ps
CPU time 2.53 seconds
Started Jul 17 08:01:15 PM PDT 24
Finished Jul 17 08:01:19 PM PDT 24
Peak memory 206632 kb
Host smart-de57e4ae-b830-4b40-baa3-4f4e7493216d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24033
24056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2403324056
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2968355600
Short name T1643
Test name
Test status
Simulation time 4759468205 ps
CPU time 135.89 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:03:40 PM PDT 24
Peak memory 206696 kb
Host smart-f2d5a2bb-bda9-4806-834f-636e7ee281d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29683
55600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2968355600
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3239431758
Short name T1489
Test name
Test status
Simulation time 43552555 ps
CPU time 0.71 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:22 PM PDT 24
Peak memory 206416 kb
Host smart-12fe248c-5e05-48ed-ac3b-2a78c90d6e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3239431758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3239431758
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1294351878
Short name T2615
Test name
Test status
Simulation time 3880386917 ps
CPU time 4.58 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:22 PM PDT 24
Peak memory 206516 kb
Host smart-5e6698f7-dd66-435f-905b-6fd4c1202ab1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1294351878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1294351878
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3490471582
Short name T482
Test name
Test status
Simulation time 13340667786 ps
CPU time 12.09 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206520 kb
Host smart-f9b77981-9865-4f3f-824f-5a7deeb098da
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3490471582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3490471582
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.2032459765
Short name T179
Test name
Test status
Simulation time 23463804050 ps
CPU time 21.88 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:47 PM PDT 24
Peak memory 206728 kb
Host smart-0e0e8dea-de2d-456e-9893-8ab5115074df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2032459765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2032459765
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1298827159
Short name T1440
Test name
Test status
Simulation time 147093368 ps
CPU time 0.78 seconds
Started Jul 17 08:01:21 PM PDT 24
Finished Jul 17 08:01:27 PM PDT 24
Peak memory 206456 kb
Host smart-18b39be1-9fad-46b1-93a7-f25aa6809fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12988
27159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1298827159
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3782169514
Short name T750
Test name
Test status
Simulation time 170094694 ps
CPU time 0.82 seconds
Started Jul 17 08:01:21 PM PDT 24
Finished Jul 17 08:01:27 PM PDT 24
Peak memory 206460 kb
Host smart-f958f5d4-0b40-40cd-be1a-34fa00431259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37821
69514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3782169514
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3325481503
Short name T2366
Test name
Test status
Simulation time 518035871 ps
CPU time 1.45 seconds
Started Jul 17 08:01:21 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206660 kb
Host smart-727040c9-4011-42f4-bc94-bb1207e68842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
81503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3325481503
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.2191208097
Short name T2356
Test name
Test status
Simulation time 1523103678 ps
CPU time 3.13 seconds
Started Jul 17 08:01:21 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206608 kb
Host smart-37a8da93-6111-430b-9b36-4609057aeed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21912
08097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.2191208097
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3677483048
Short name T2467
Test name
Test status
Simulation time 12040654636 ps
CPU time 22.15 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:46 PM PDT 24
Peak memory 206648 kb
Host smart-c3fa90b9-d974-4f94-98c7-0c41f59cc8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36774
83048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3677483048
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.222822519
Short name T2434
Test name
Test status
Simulation time 411060070 ps
CPU time 1.35 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:22 PM PDT 24
Peak memory 206464 kb
Host smart-aa340e39-f2bf-4894-aae6-7b9cfac70d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282
2519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.222822519
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.692931072
Short name T404
Test name
Test status
Simulation time 142703187 ps
CPU time 0.74 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 205996 kb
Host smart-feb82f42-131d-47aa-af1e-56ce576e6163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69293
1072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.692931072
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.3317541289
Short name T954
Test name
Test status
Simulation time 54380814 ps
CPU time 0.66 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206436 kb
Host smart-da8ecce3-3cbd-4863-bcb8-79509cdfbf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33175
41289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3317541289
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3360471396
Short name T1566
Test name
Test status
Simulation time 835650509 ps
CPU time 1.83 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206588 kb
Host smart-d46be855-5ecd-422d-95a4-2767c98cd74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33604
71396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3360471396
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.597066181
Short name T1992
Test name
Test status
Simulation time 211926924 ps
CPU time 1.46 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206596 kb
Host smart-1ebb589a-d927-45d3-b59e-ff13a4b98ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59706
6181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.597066181
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3517497806
Short name T1769
Test name
Test status
Simulation time 208652933 ps
CPU time 0.91 seconds
Started Jul 17 08:01:12 PM PDT 24
Finished Jul 17 08:01:15 PM PDT 24
Peak memory 206452 kb
Host smart-71477b19-344d-4dfe-ba97-68c2cc96940c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35174
97806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3517497806
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2947480158
Short name T109
Test name
Test status
Simulation time 143522423 ps
CPU time 0.78 seconds
Started Jul 17 08:01:13 PM PDT 24
Finished Jul 17 08:01:16 PM PDT 24
Peak memory 206448 kb
Host smart-682a3b7f-9ccd-4e83-b668-9944a9e8d403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29474
80158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2947480158
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2779239618
Short name T1281
Test name
Test status
Simulation time 225332701 ps
CPU time 0.99 seconds
Started Jul 17 08:01:04 PM PDT 24
Finished Jul 17 08:01:07 PM PDT 24
Peak memory 206428 kb
Host smart-899d0597-8e7d-43d2-864f-56a3f2c5f8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27792
39618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2779239618
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2068420844
Short name T1924
Test name
Test status
Simulation time 7907904631 ps
CPU time 78.36 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:02:42 PM PDT 24
Peak memory 206720 kb
Host smart-8753fbba-08b5-4fb2-ba22-6319cba46ba2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2068420844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2068420844
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.3357414274
Short name T1396
Test name
Test status
Simulation time 4255188872 ps
CPU time 14.49 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:36 PM PDT 24
Peak memory 206644 kb
Host smart-0beba3c2-0df2-46e6-b3f1-b2a7f07d0d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33574
14274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3357414274
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3579016464
Short name T1753
Test name
Test status
Simulation time 197510637 ps
CPU time 0.84 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206452 kb
Host smart-418b8e4b-f7a2-4d31-bf77-59a3b521319f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35790
16464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3579016464
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2730734977
Short name T2673
Test name
Test status
Simulation time 23317646987 ps
CPU time 24.91 seconds
Started Jul 17 08:01:13 PM PDT 24
Finished Jul 17 08:01:39 PM PDT 24
Peak memory 206512 kb
Host smart-a59b7848-8eaf-4a00-8f16-c5621837a983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27307
34977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2730734977
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.4148893360
Short name T2184
Test name
Test status
Simulation time 3270516993 ps
CPU time 4.44 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206516 kb
Host smart-67de266b-5a88-448e-a5e5-14968b36d430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41488
93360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.4148893360
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3517444320
Short name T1750
Test name
Test status
Simulation time 7354053901 ps
CPU time 69.06 seconds
Started Jul 17 08:01:13 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206732 kb
Host smart-4cd39d26-3a46-4680-a07a-ba7fd21aa9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35174
44320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3517444320
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.155378402
Short name T1725
Test name
Test status
Simulation time 5071700557 ps
CPU time 47.17 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206660 kb
Host smart-3c318447-b5f1-4204-8088-154207d802f3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=155378402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.155378402
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.298108038
Short name T343
Test name
Test status
Simulation time 319518314 ps
CPU time 1.06 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:25 PM PDT 24
Peak memory 206448 kb
Host smart-4bba713d-bbd4-4526-9922-093ed07cd5ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=298108038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.298108038
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.870716917
Short name T1034
Test name
Test status
Simulation time 188465406 ps
CPU time 0.91 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:20 PM PDT 24
Peak memory 206452 kb
Host smart-f0ef1dd2-8410-4f72-86bd-3aa47ef84345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87071
6917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.870716917
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.3515149545
Short name T1294
Test name
Test status
Simulation time 3348016174 ps
CPU time 22.31 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:44 PM PDT 24
Peak memory 206724 kb
Host smart-fff18832-a58e-4a0e-9a5d-d44312f866db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
49545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.3515149545
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3714774562
Short name T406
Test name
Test status
Simulation time 6767079926 ps
CPU time 47.92 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206716 kb
Host smart-122550fc-9096-450e-87e7-8fb10d0282e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3714774562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3714774562
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3887244136
Short name T334
Test name
Test status
Simulation time 151607384 ps
CPU time 0.81 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206452 kb
Host smart-f5cd5bba-3429-4f2a-94b6-8a6aefe17411
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3887244136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3887244136
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2521348766
Short name T2520
Test name
Test status
Simulation time 149011912 ps
CPU time 0.78 seconds
Started Jul 17 08:01:04 PM PDT 24
Finished Jul 17 08:01:06 PM PDT 24
Peak memory 206452 kb
Host smart-d30da63c-05e0-4278-86ee-e8713b4eaac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25213
48766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2521348766
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.54798026
Short name T125
Test name
Test status
Simulation time 205191544 ps
CPU time 0.84 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:20 PM PDT 24
Peak memory 206444 kb
Host smart-f1848710-7c53-4d4e-a31d-959725a54bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54798
026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.54798026
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2396305730
Short name T2541
Test name
Test status
Simulation time 208335733 ps
CPU time 0.83 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206408 kb
Host smart-a104d57e-19b1-4839-b9e3-3dca4a3f2457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23963
05730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2396305730
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3114876308
Short name T1774
Test name
Test status
Simulation time 162604668 ps
CPU time 0.8 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 205992 kb
Host smart-2174307a-682b-4413-9936-e1edd0e0ba02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31148
76308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3114876308
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.81225166
Short name T1272
Test name
Test status
Simulation time 175331232 ps
CPU time 0.79 seconds
Started Jul 17 08:01:05 PM PDT 24
Finished Jul 17 08:01:08 PM PDT 24
Peak memory 206452 kb
Host smart-6ef8e60b-f284-43a6-aa8f-76d7423935ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81225
166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.81225166
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3646553043
Short name T866
Test name
Test status
Simulation time 171436593 ps
CPU time 0.75 seconds
Started Jul 17 08:01:16 PM PDT 24
Finished Jul 17 08:01:20 PM PDT 24
Peak memory 206456 kb
Host smart-af8e063f-9ce9-4aba-bc70-80cda81ced26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36465
53043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3646553043
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.811299047
Short name T2432
Test name
Test status
Simulation time 240996255 ps
CPU time 0.93 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:24 PM PDT 24
Peak memory 206456 kb
Host smart-a95e7c59-7e01-499e-9bc2-c344e0aae31f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=811299047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.811299047
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2413166874
Short name T796
Test name
Test status
Simulation time 213845913 ps
CPU time 0.83 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206412 kb
Host smart-846862b6-dd79-47e9-ab31-9f9a6b327345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24131
66874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2413166874
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1820934972
Short name T37
Test name
Test status
Simulation time 47372296 ps
CPU time 0.69 seconds
Started Jul 17 08:01:07 PM PDT 24
Finished Jul 17 08:01:09 PM PDT 24
Peak memory 206448 kb
Host smart-92adc3bd-f231-4d8b-b5e2-57f404cf7caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18209
34972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1820934972
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.426016530
Short name T236
Test name
Test status
Simulation time 14848463165 ps
CPU time 32.7 seconds
Started Jul 17 08:01:11 PM PDT 24
Finished Jul 17 08:01:46 PM PDT 24
Peak memory 206768 kb
Host smart-49427a96-76fa-488e-9793-a65075158aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601
6530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.426016530
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.548884833
Short name T639
Test name
Test status
Simulation time 172165106 ps
CPU time 0.84 seconds
Started Jul 17 08:01:04 PM PDT 24
Finished Jul 17 08:01:06 PM PDT 24
Peak memory 206452 kb
Host smart-789829be-6168-4d22-9ada-6c77556e6070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54888
4833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.548884833
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.4058100985
Short name T1754
Test name
Test status
Simulation time 206029091 ps
CPU time 0.89 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206392 kb
Host smart-8d1d9b24-0617-456a-b580-49c8e77b4d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40581
00985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4058100985
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.3543816749
Short name T1688
Test name
Test status
Simulation time 243011621 ps
CPU time 0.9 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:24 PM PDT 24
Peak memory 206452 kb
Host smart-d2351fbc-4717-4d1a-b857-a6ce985d966b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35438
16749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.3543816749
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.160496392
Short name T1938
Test name
Test status
Simulation time 185004671 ps
CPU time 0.82 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:24 PM PDT 24
Peak memory 206452 kb
Host smart-1a839e8f-440c-40e6-b812-55a3ed53663d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16049
6392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.160496392
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1623653316
Short name T2279
Test name
Test status
Simulation time 201391279 ps
CPU time 0.78 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206440 kb
Host smart-8559cd1e-d1e1-43d9-9361-0babdca2aa1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16236
53316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1623653316
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1238807997
Short name T787
Test name
Test status
Simulation time 155010999 ps
CPU time 0.75 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:23 PM PDT 24
Peak memory 206436 kb
Host smart-af6455c0-af8e-4c62-a1ea-cc08f5f38848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12388
07997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1238807997
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1919672399
Short name T1600
Test name
Test status
Simulation time 174942261 ps
CPU time 0.79 seconds
Started Jul 17 08:01:20 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206460 kb
Host smart-fe2f270a-69af-4c74-b193-a68ee4f8f348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19196
72399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1919672399
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1213853433
Short name T1448
Test name
Test status
Simulation time 260457682 ps
CPU time 0.97 seconds
Started Jul 17 08:01:21 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 206448 kb
Host smart-e9d7797e-60f3-46ad-b8c0-70e2ac871c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12138
53433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1213853433
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.454376798
Short name T1936
Test name
Test status
Simulation time 5894689160 ps
CPU time 163.25 seconds
Started Jul 17 08:01:19 PM PDT 24
Finished Jul 17 08:04:07 PM PDT 24
Peak memory 206668 kb
Host smart-41581512-7fd8-4b56-bffa-c15e725e2fd2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=454376798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.454376798
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1514082759
Short name T2212
Test name
Test status
Simulation time 180088066 ps
CPU time 0.81 seconds
Started Jul 17 08:01:20 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206464 kb
Host smart-4da10151-6547-4caf-8ad5-579941b77146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15140
82759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1514082759
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3061137112
Short name T1434
Test name
Test status
Simulation time 221950697 ps
CPU time 0.81 seconds
Started Jul 17 08:01:20 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206456 kb
Host smart-3725706b-ae2c-45a7-b280-4a046e04cc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30611
37112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3061137112
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.1672082606
Short name T1018
Test name
Test status
Simulation time 960624795 ps
CPU time 2.08 seconds
Started Jul 17 08:01:20 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 206660 kb
Host smart-cf1a2274-1ce7-4eb6-b59c-19d4974f9f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16720
82606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.1672082606
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3075336126
Short name T1227
Test name
Test status
Simulation time 6267581423 ps
CPU time 57.3 seconds
Started Jul 17 08:01:20 PM PDT 24
Finished Jul 17 08:02:23 PM PDT 24
Peak memory 206664 kb
Host smart-45b02be1-4937-4040-a8eb-a73e65f9f8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30753
36126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3075336126
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.2863179961
Short name T177
Test name
Test status
Simulation time 45877795 ps
CPU time 0.69 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:01:32 PM PDT 24
Peak memory 206400 kb
Host smart-498161a0-4e78-40fa-8385-0ca7102f0955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2863179961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2863179961
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1171183426
Short name T2670
Test name
Test status
Simulation time 3579740461 ps
CPU time 4.12 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 206524 kb
Host smart-fedf724c-1aa4-415c-b1e4-f12b59f472ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1171183426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1171183426
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3052299167
Short name T7
Test name
Test status
Simulation time 13316807582 ps
CPU time 13.71 seconds
Started Jul 17 08:01:21 PM PDT 24
Finished Jul 17 08:01:40 PM PDT 24
Peak memory 206528 kb
Host smart-444447f4-8be1-4275-81d6-c7fa366c024f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3052299167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3052299167
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3974857611
Short name T2578
Test name
Test status
Simulation time 23360576829 ps
CPU time 25.29 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:47 PM PDT 24
Peak memory 206732 kb
Host smart-e23b6d5b-3dec-4ef4-b336-6eeb3fa63935
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3974857611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3974857611
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.704363928
Short name T2134
Test name
Test status
Simulation time 152781797 ps
CPU time 0.75 seconds
Started Jul 17 08:01:18 PM PDT 24
Finished Jul 17 08:01:24 PM PDT 24
Peak memory 206460 kb
Host smart-1a29a499-f4a4-4ee9-aabc-b2fcff6d9462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70436
3928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.704363928
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.168046766
Short name T63
Test name
Test status
Simulation time 147442336 ps
CPU time 0.73 seconds
Started Jul 17 08:01:17 PM PDT 24
Finished Jul 17 08:01:21 PM PDT 24
Peak memory 206044 kb
Host smart-123c57ab-9883-4e00-8111-75a3f333d501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16804
6766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.168046766
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2824508406
Short name T1856
Test name
Test status
Simulation time 403883041 ps
CPU time 1.24 seconds
Started Jul 17 08:01:04 PM PDT 24
Finished Jul 17 08:01:07 PM PDT 24
Peak memory 206448 kb
Host smart-bf605ed7-f2bb-401d-84e2-2ce7213b4fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28245
08406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2824508406
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3265088408
Short name T1894
Test name
Test status
Simulation time 999475027 ps
CPU time 2.45 seconds
Started Jul 17 08:01:23 PM PDT 24
Finished Jul 17 08:01:30 PM PDT 24
Peak memory 206648 kb
Host smart-acdca7cc-7c26-4950-967a-e021a128afcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32650
88408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3265088408
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.1746755188
Short name T764
Test name
Test status
Simulation time 6403624737 ps
CPU time 10.7 seconds
Started Jul 17 08:01:23 PM PDT 24
Finished Jul 17 08:01:39 PM PDT 24
Peak memory 206800 kb
Host smart-42e61e87-ae7f-4262-b401-85ab77baafc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17467
55188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.1746755188
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1394752780
Short name T891
Test name
Test status
Simulation time 393008869 ps
CPU time 1.29 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:01:31 PM PDT 24
Peak memory 206628 kb
Host smart-52281aed-c05f-4cea-a637-ccf3c943d6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13947
52780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1394752780
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.4257955391
Short name T661
Test name
Test status
Simulation time 146928020 ps
CPU time 0.78 seconds
Started Jul 17 08:01:23 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206412 kb
Host smart-d9ec2e6b-defa-4684-b7c4-98de30abc720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42579
55391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.4257955391
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1866702016
Short name T1776
Test name
Test status
Simulation time 42875337 ps
CPU time 0.65 seconds
Started Jul 17 08:01:22 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 206444 kb
Host smart-496e1d55-3e2b-4af6-b9d0-7ffcc56b7453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18667
02016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1866702016
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3809267777
Short name T1249
Test name
Test status
Simulation time 871711953 ps
CPU time 2.2 seconds
Started Jul 17 08:01:21 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 206604 kb
Host smart-04550afb-d4a1-465b-80c2-2bcea50a722f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
67777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3809267777
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3903700467
Short name T1713
Test name
Test status
Simulation time 345477065 ps
CPU time 2.19 seconds
Started Jul 17 08:01:26 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206604 kb
Host smart-ff7861cd-609f-499c-8438-af23905b064c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39037
00467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3903700467
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.4135292393
Short name T2311
Test name
Test status
Simulation time 179716768 ps
CPU time 0.88 seconds
Started Jul 17 08:01:21 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 206460 kb
Host smart-d6c943eb-631b-4b14-8f61-dc2f36b0db78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41352
92393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.4135292393
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.229998448
Short name T1573
Test name
Test status
Simulation time 152952469 ps
CPU time 0.79 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206472 kb
Host smart-ea4aadff-34d9-41aa-a20f-cf645bdbd30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22999
8448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.229998448
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1856863123
Short name T206
Test name
Test status
Simulation time 224784691 ps
CPU time 0.98 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:01:31 PM PDT 24
Peak memory 206448 kb
Host smart-0d096916-1cc8-44a6-ab67-80018f4fcb55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18568
63123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1856863123
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.2793417666
Short name T2561
Test name
Test status
Simulation time 8739433353 ps
CPU time 26.45 seconds
Started Jul 17 08:01:26 PM PDT 24
Finished Jul 17 08:01:58 PM PDT 24
Peak memory 206616 kb
Host smart-df4af2ae-07cd-4656-9f1c-a0c2a96d95f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27934
17666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.2793417666
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3739316921
Short name T1618
Test name
Test status
Simulation time 286790034 ps
CPU time 0.91 seconds
Started Jul 17 08:01:22 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206456 kb
Host smart-334f5d12-6e5c-4602-bfa3-27ed0486b1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37393
16921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3739316921
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1001917352
Short name T623
Test name
Test status
Simulation time 23353295974 ps
CPU time 26.08 seconds
Started Jul 17 08:01:26 PM PDT 24
Finished Jul 17 08:01:58 PM PDT 24
Peak memory 206516 kb
Host smart-9e3a78cc-7d9b-4af7-9afa-9fa912841ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10019
17352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1001917352
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1100025341
Short name T1745
Test name
Test status
Simulation time 3342797583 ps
CPU time 3.64 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206512 kb
Host smart-25aecdbd-06ae-4e3b-be68-0912993b4967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11000
25341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1100025341
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.527194397
Short name T2642
Test name
Test status
Simulation time 9688544598 ps
CPU time 272.55 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:06:03 PM PDT 24
Peak memory 206732 kb
Host smart-0a2db16c-a31f-468f-80be-4224c9a457a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52719
4397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.527194397
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.331492684
Short name T385
Test name
Test status
Simulation time 4919440050 ps
CPU time 139.84 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:03:50 PM PDT 24
Peak memory 206648 kb
Host smart-5b34218f-749e-4b9f-b34d-7ff2b65590be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=331492684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.331492684
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3703735037
Short name T1962
Test name
Test status
Simulation time 232412818 ps
CPU time 0.94 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:01:31 PM PDT 24
Peak memory 206444 kb
Host smart-877e3016-2df7-4ae8-8bf3-28ff265ccd2f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3703735037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3703735037
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1701681101
Short name T1193
Test name
Test status
Simulation time 244455158 ps
CPU time 0.92 seconds
Started Jul 17 08:01:23 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206452 kb
Host smart-64a4d2bc-65ce-4291-a7ce-d5cdcc7ee80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17016
81101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1701681101
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.1017009324
Short name T1186
Test name
Test status
Simulation time 5429748144 ps
CPU time 49.28 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:02:20 PM PDT 24
Peak memory 206656 kb
Host smart-ecdac360-cdd4-48b9-b882-74caa9a02798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10170
09324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.1017009324
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3195799584
Short name T2316
Test name
Test status
Simulation time 5919672297 ps
CPU time 161.15 seconds
Started Jul 17 08:01:22 PM PDT 24
Finished Jul 17 08:04:09 PM PDT 24
Peak memory 206628 kb
Host smart-12a4490f-bd2d-489d-9965-b17f632ec061
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3195799584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3195799584
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2275584394
Short name T1337
Test name
Test status
Simulation time 160430329 ps
CPU time 0.76 seconds
Started Jul 17 08:01:20 PM PDT 24
Finished Jul 17 08:01:27 PM PDT 24
Peak memory 206456 kb
Host smart-3736890d-d320-4205-9cf2-70581ff896af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2275584394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2275584394
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.943009550
Short name T1255
Test name
Test status
Simulation time 149480366 ps
CPU time 0.81 seconds
Started Jul 17 08:01:29 PM PDT 24
Finished Jul 17 08:01:35 PM PDT 24
Peak memory 206456 kb
Host smart-20f1ab72-e21d-4f53-83e1-82ff0f960bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94300
9550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.943009550
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.4042059939
Short name T111
Test name
Test status
Simulation time 209871528 ps
CPU time 0.86 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:33 PM PDT 24
Peak memory 206456 kb
Host smart-a3d69847-bee1-4d79-b64b-b2f5fc7c14f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40420
59939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.4042059939
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1487279180
Short name T2077
Test name
Test status
Simulation time 205636459 ps
CPU time 0.93 seconds
Started Jul 17 08:01:22 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 206460 kb
Host smart-0e6264c0-225d-4a77-89a7-daeab9e9adab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14872
79180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1487279180
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2716108071
Short name T2585
Test name
Test status
Simulation time 201652861 ps
CPU time 0.8 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206396 kb
Host smart-439cc355-3e1e-48a0-8c98-1e6f248165c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27161
08071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2716108071
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2687194300
Short name T1830
Test name
Test status
Simulation time 230308168 ps
CPU time 0.86 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:33 PM PDT 24
Peak memory 206440 kb
Host smart-cb5793c4-85de-4eee-a073-132930ebf372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
94300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2687194300
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1303235976
Short name T458
Test name
Test status
Simulation time 178585918 ps
CPU time 0.78 seconds
Started Jul 17 08:01:20 PM PDT 24
Finished Jul 17 08:01:26 PM PDT 24
Peak memory 206544 kb
Host smart-31dbb943-58a2-4e5a-b884-cc0394e97aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13032
35976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1303235976
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.584014303
Short name T1154
Test name
Test status
Simulation time 248151633 ps
CPU time 0.95 seconds
Started Jul 17 08:01:35 PM PDT 24
Finished Jul 17 08:01:38 PM PDT 24
Peak memory 206468 kb
Host smart-0c4c6a45-c036-4099-9cac-0a2bc13ae648
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=584014303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.584014303
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3542776610
Short name T1206
Test name
Test status
Simulation time 168774165 ps
CPU time 0.83 seconds
Started Jul 17 08:01:22 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 206456 kb
Host smart-46bd4a71-6e91-4402-b207-c8764df16c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35427
76610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3542776610
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1827483656
Short name T836
Test name
Test status
Simulation time 64501212 ps
CPU time 0.67 seconds
Started Jul 17 08:01:35 PM PDT 24
Finished Jul 17 08:01:37 PM PDT 24
Peak memory 206456 kb
Host smart-5d6bb9c9-7993-4c99-9dfe-9577db7639fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18274
83656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1827483656
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.3216342510
Short name T2338
Test name
Test status
Simulation time 21061244206 ps
CPU time 44.13 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:02:14 PM PDT 24
Peak memory 206700 kb
Host smart-e4afd53d-fee4-4cb8-9235-8e8a084ed9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32163
42510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.3216342510
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1151698969
Short name T2083
Test name
Test status
Simulation time 188673185 ps
CPU time 0.94 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:01:32 PM PDT 24
Peak memory 206420 kb
Host smart-6dd8dae7-0109-4e29-b5e4-53a137a9a749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11516
98969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1151698969
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3516728951
Short name T2462
Test name
Test status
Simulation time 186644364 ps
CPU time 0.83 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:01:32 PM PDT 24
Peak memory 206436 kb
Host smart-be7ba09d-12ef-4e94-89ea-9970dea32551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35167
28951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3516728951
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1118177022
Short name T1869
Test name
Test status
Simulation time 171041106 ps
CPU time 0.82 seconds
Started Jul 17 08:01:31 PM PDT 24
Finished Jul 17 08:01:36 PM PDT 24
Peak memory 206464 kb
Host smart-fb73a143-5dac-4910-92e7-79f3079741e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11181
77022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1118177022
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2564115914
Short name T688
Test name
Test status
Simulation time 176300506 ps
CPU time 0.86 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:01:30 PM PDT 24
Peak memory 206436 kb
Host smart-f19a448d-c079-4993-81fc-3fd7b760f72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25641
15914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2564115914
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1318906325
Short name T1238
Test name
Test status
Simulation time 142448785 ps
CPU time 0.8 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:33 PM PDT 24
Peak memory 206452 kb
Host smart-b927840e-91a4-4fca-95c0-2726cf546451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13189
06325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1318906325
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3817632820
Short name T752
Test name
Test status
Simulation time 146564023 ps
CPU time 0.76 seconds
Started Jul 17 08:01:22 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206456 kb
Host smart-efc0b2d6-b5ec-4539-b9bd-70166d04e439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
32820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3817632820
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2885851204
Short name T1020
Test name
Test status
Simulation time 163901937 ps
CPU time 0.79 seconds
Started Jul 17 08:01:22 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206452 kb
Host smart-89229549-c378-45db-b899-4b9c84578ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
51204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2885851204
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1438248452
Short name T1822
Test name
Test status
Simulation time 269488170 ps
CPU time 0.95 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:01:31 PM PDT 24
Peak memory 206448 kb
Host smart-8d39e15c-d1b2-4855-b224-ee4fb7a33392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14382
48452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1438248452
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1165960535
Short name T2193
Test name
Test status
Simulation time 4466757837 ps
CPU time 40.48 seconds
Started Jul 17 08:01:23 PM PDT 24
Finished Jul 17 08:02:09 PM PDT 24
Peak memory 206652 kb
Host smart-1da0d5d7-48f0-48a4-bdc6-c84ed14cae49
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1165960535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1165960535
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2438303978
Short name T732
Test name
Test status
Simulation time 159450274 ps
CPU time 0.82 seconds
Started Jul 17 08:01:23 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206456 kb
Host smart-9e392181-dac7-43d7-98e8-c9b40dbf555f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24383
03978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2438303978
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2362962631
Short name T449
Test name
Test status
Simulation time 213440131 ps
CPU time 0.88 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:01:31 PM PDT 24
Peak memory 206448 kb
Host smart-dd1815af-86e9-4a3d-901d-0363435315ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23629
62631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2362962631
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.2039441573
Short name T2538
Test name
Test status
Simulation time 646740257 ps
CPU time 1.56 seconds
Started Jul 17 08:01:26 PM PDT 24
Finished Jul 17 08:01:33 PM PDT 24
Peak memory 206408 kb
Host smart-9c890ff7-3634-40cd-b25e-9bee45d5bd9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20394
41573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.2039441573
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.2903539289
Short name T1650
Test name
Test status
Simulation time 5296902449 ps
CPU time 147.79 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:04:00 PM PDT 24
Peak memory 206664 kb
Host smart-837343f8-68a6-448c-a509-2ec6afa39c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29035
39289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2903539289
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3172817870
Short name T839
Test name
Test status
Simulation time 43141109 ps
CPU time 0.7 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:07 PM PDT 24
Peak memory 206432 kb
Host smart-6424bd99-d302-424c-90fd-002a0f2a5b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3172817870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3172817870
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.300877874
Short name T2064
Test name
Test status
Simulation time 3461502408 ps
CPU time 4.2 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:37 PM PDT 24
Peak memory 206544 kb
Host smart-4230c929-888a-430c-a853-75fe1cda0fe3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=300877874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.300877874
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.416752991
Short name T1045
Test name
Test status
Simulation time 13368710871 ps
CPU time 12.38 seconds
Started Jul 17 08:01:29 PM PDT 24
Finished Jul 17 08:01:47 PM PDT 24
Peak memory 206492 kb
Host smart-dbbad73b-387f-484f-a9f1-9268b5c3f70b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=416752991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.416752991
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2083980655
Short name T1376
Test name
Test status
Simulation time 23338941485 ps
CPU time 24.39 seconds
Started Jul 17 08:01:31 PM PDT 24
Finished Jul 17 08:02:00 PM PDT 24
Peak memory 206736 kb
Host smart-9c458c7c-d932-40e5-9f39-77c96bea40eb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2083980655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2083980655
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2156877212
Short name T2017
Test name
Test status
Simulation time 158393603 ps
CPU time 0.76 seconds
Started Jul 17 08:01:31 PM PDT 24
Finished Jul 17 08:01:36 PM PDT 24
Peak memory 206452 kb
Host smart-83a4f65a-e6ab-4d0f-b7af-11e65b61b809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568
77212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2156877212
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1456569465
Short name T1906
Test name
Test status
Simulation time 145702351 ps
CPU time 0.77 seconds
Started Jul 17 08:01:26 PM PDT 24
Finished Jul 17 08:01:32 PM PDT 24
Peak memory 206408 kb
Host smart-b03cd82f-6986-403b-83fd-8c98af350ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14565
69465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1456569465
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.242369390
Short name T323
Test name
Test status
Simulation time 183788394 ps
CPU time 0.87 seconds
Started Jul 17 08:01:26 PM PDT 24
Finished Jul 17 08:01:33 PM PDT 24
Peak memory 206412 kb
Host smart-611c3723-653f-49b1-b0ed-2b76463d36aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24236
9390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.242369390
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2548350343
Short name T1450
Test name
Test status
Simulation time 947249933 ps
CPU time 2.31 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:01:33 PM PDT 24
Peak memory 206608 kb
Host smart-643209a4-6a3e-4930-bdf1-9ac00cc7634d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25483
50343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2548350343
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2933959774
Short name T1071
Test name
Test status
Simulation time 8363009278 ps
CPU time 16.41 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:01:50 PM PDT 24
Peak memory 206664 kb
Host smart-e6857c8c-0002-4fc7-bfc8-60d3a20f23c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
59774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2933959774
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1408130987
Short name T651
Test name
Test status
Simulation time 403112126 ps
CPU time 1.34 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:33 PM PDT 24
Peak memory 206476 kb
Host smart-ea473994-36dc-4803-a01d-ec41c573afa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14081
30987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1408130987
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3910661301
Short name T583
Test name
Test status
Simulation time 167725068 ps
CPU time 0.81 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206448 kb
Host smart-e0a37058-ff98-4eb6-bec7-b2a74a9983ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39106
61301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3910661301
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3726642378
Short name T222
Test name
Test status
Simulation time 86743962 ps
CPU time 0.72 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206388 kb
Host smart-171f9ccb-8b0a-4bc8-bd75-8a6143aa5222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37266
42378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3726642378
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2273643556
Short name T2746
Test name
Test status
Simulation time 988927378 ps
CPU time 2.48 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:35 PM PDT 24
Peak memory 206552 kb
Host smart-435a105a-9de9-4d61-8ee2-eccd145998d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22736
43556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2273643556
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3526261723
Short name T307
Test name
Test status
Simulation time 235585873 ps
CPU time 1.58 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:01:35 PM PDT 24
Peak memory 206652 kb
Host smart-4be33227-5774-418e-8848-8f30ba73934e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35262
61723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3526261723
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.4198971126
Short name T1764
Test name
Test status
Simulation time 194549206 ps
CPU time 0.88 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206444 kb
Host smart-6a963cc7-424a-4859-9a68-d8ef2eeab36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41989
71126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.4198971126
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2201923546
Short name T994
Test name
Test status
Simulation time 141413967 ps
CPU time 0.77 seconds
Started Jul 17 08:01:29 PM PDT 24
Finished Jul 17 08:01:35 PM PDT 24
Peak memory 206448 kb
Host smart-0fef03e1-b764-4fcd-9660-fda524007a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22019
23546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2201923546
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3152535100
Short name T2507
Test name
Test status
Simulation time 209539429 ps
CPU time 0.9 seconds
Started Jul 17 08:01:35 PM PDT 24
Finished Jul 17 08:01:37 PM PDT 24
Peak memory 206148 kb
Host smart-2ce232c8-68c4-4e18-9419-377d5fd6b303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31525
35100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3152535100
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.2246038207
Short name T1824
Test name
Test status
Simulation time 6981022473 ps
CPU time 59.31 seconds
Started Jul 17 08:01:35 PM PDT 24
Finished Jul 17 08:02:36 PM PDT 24
Peak memory 206472 kb
Host smart-2405a51b-aa88-474f-a387-6d702de1e099
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2246038207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.2246038207
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3846972880
Short name T2692
Test name
Test status
Simulation time 13130711206 ps
CPU time 45.33 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:02:19 PM PDT 24
Peak memory 206668 kb
Host smart-c96364d3-0028-4126-b06b-758d492a0930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38469
72880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3846972880
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2152350117
Short name T698
Test name
Test status
Simulation time 165002946 ps
CPU time 0.86 seconds
Started Jul 17 08:01:27 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206440 kb
Host smart-15f331f6-0b8e-4b55-9f10-4971677d073e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21523
50117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2152350117
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3799160708
Short name T1405
Test name
Test status
Simulation time 23272535448 ps
CPU time 22.04 seconds
Started Jul 17 08:01:30 PM PDT 24
Finished Jul 17 08:01:57 PM PDT 24
Peak memory 206508 kb
Host smart-7aca91b3-89a0-41f6-9e7b-899b411c71fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37991
60708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3799160708
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3201374269
Short name T632
Test name
Test status
Simulation time 3335725163 ps
CPU time 4.04 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:01:37 PM PDT 24
Peak memory 206520 kb
Host smart-b80c4487-75c2-446f-8956-60c8ca5957e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32013
74269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3201374269
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.588038630
Short name T2300
Test name
Test status
Simulation time 14458758644 ps
CPU time 419.24 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:08:30 PM PDT 24
Peak memory 206752 kb
Host smart-87c186dc-f27c-4ecd-b7d5-178877de7f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58803
8630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.588038630
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3161201015
Short name T959
Test name
Test status
Simulation time 3649289008 ps
CPU time 101.32 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:03:14 PM PDT 24
Peak memory 206648 kb
Host smart-c603a54b-a8c1-436e-9f61-5b576a557ca1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3161201015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3161201015
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2851246755
Short name T766
Test name
Test status
Simulation time 243405873 ps
CPU time 0.91 seconds
Started Jul 17 08:01:29 PM PDT 24
Finished Jul 17 08:01:35 PM PDT 24
Peak memory 206452 kb
Host smart-48ee9248-27cf-4704-a61b-2f3de45370f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2851246755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2851246755
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2208880123
Short name T1466
Test name
Test status
Simulation time 195312475 ps
CPU time 0.88 seconds
Started Jul 17 08:01:34 PM PDT 24
Finished Jul 17 08:01:37 PM PDT 24
Peak memory 206464 kb
Host smart-a94f472c-56f6-4ae1-999e-c482b0d6f85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22088
80123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2208880123
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1143116412
Short name T1445
Test name
Test status
Simulation time 4744103339 ps
CPU time 36.61 seconds
Started Jul 17 08:01:30 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206648 kb
Host smart-ad4cb5ce-a5b9-46f4-adb6-030c69be5a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11431
16412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1143116412
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.2940807669
Short name T1004
Test name
Test status
Simulation time 5231767694 ps
CPU time 147.52 seconds
Started Jul 17 08:01:30 PM PDT 24
Finished Jul 17 08:04:03 PM PDT 24
Peak memory 206652 kb
Host smart-481b56d5-0f23-45d6-b52e-e3f1e350b51c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2940807669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.2940807669
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3327134898
Short name T711
Test name
Test status
Simulation time 158337363 ps
CPU time 0.81 seconds
Started Jul 17 08:01:30 PM PDT 24
Finished Jul 17 08:01:36 PM PDT 24
Peak memory 206448 kb
Host smart-2f818d4a-b0f9-4132-bcef-8e51f4213573
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3327134898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3327134898
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3123502766
Short name T2630
Test name
Test status
Simulation time 167773982 ps
CPU time 0.76 seconds
Started Jul 17 08:01:35 PM PDT 24
Finished Jul 17 08:01:37 PM PDT 24
Peak memory 206464 kb
Host smart-46ac6796-f2c4-4d56-afc5-e1e80b24e739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31235
02766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3123502766
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.620149830
Short name T1336
Test name
Test status
Simulation time 209908516 ps
CPU time 0.9 seconds
Started Jul 17 08:01:30 PM PDT 24
Finished Jul 17 08:01:36 PM PDT 24
Peak memory 206448 kb
Host smart-ec485522-8e7a-4ee8-b2dd-2584952c67bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62014
9830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.620149830
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.4266484577
Short name T1269
Test name
Test status
Simulation time 164063946 ps
CPU time 0.81 seconds
Started Jul 17 08:01:24 PM PDT 24
Finished Jul 17 08:01:31 PM PDT 24
Peak memory 206424 kb
Host smart-86790008-9d48-4856-b2dc-819bd58c5a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42664
84577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.4266484577
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2612276051
Short name T2623
Test name
Test status
Simulation time 190347231 ps
CPU time 0.86 seconds
Started Jul 17 08:01:30 PM PDT 24
Finished Jul 17 08:01:35 PM PDT 24
Peak memory 206452 kb
Host smart-39b5c707-8e0a-4f50-903e-eb94ac148cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26122
76051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2612276051
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1547224461
Short name T2312
Test name
Test status
Simulation time 165864570 ps
CPU time 0.85 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:01:32 PM PDT 24
Peak memory 206580 kb
Host smart-45720c56-e84b-4c6f-8d60-50ccc3d5bb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15472
24461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1547224461
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3295305404
Short name T792
Test name
Test status
Simulation time 166081803 ps
CPU time 0.84 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206460 kb
Host smart-ba4922ab-a435-4e07-b244-15336340ce4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32953
05404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3295305404
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.2716934362
Short name T2691
Test name
Test status
Simulation time 210614350 ps
CPU time 0.86 seconds
Started Jul 17 08:01:23 PM PDT 24
Finished Jul 17 08:01:29 PM PDT 24
Peak memory 206464 kb
Host smart-28bcf408-d88f-498e-a1bd-ec54d1037da4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2716934362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.2716934362
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2188604869
Short name T2040
Test name
Test status
Simulation time 144742196 ps
CPU time 0.8 seconds
Started Jul 17 08:01:31 PM PDT 24
Finished Jul 17 08:01:36 PM PDT 24
Peak memory 206452 kb
Host smart-d13867fe-2042-445b-b76e-bbaf186700a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21886
04869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2188604869
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3463723578
Short name T1217
Test name
Test status
Simulation time 55665889 ps
CPU time 0.69 seconds
Started Jul 17 08:01:30 PM PDT 24
Finished Jul 17 08:01:36 PM PDT 24
Peak memory 206424 kb
Host smart-fa4a00e7-f673-435a-bff5-b42610bbf840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637
23578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3463723578
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3505937589
Short name T771
Test name
Test status
Simulation time 7913647948 ps
CPU time 19.47 seconds
Started Jul 17 08:01:25 PM PDT 24
Finished Jul 17 08:01:51 PM PDT 24
Peak memory 206736 kb
Host smart-fe151dbb-f623-42e5-9d09-de35dc323a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35059
37589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3505937589
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3224410832
Short name T2536
Test name
Test status
Simulation time 189767790 ps
CPU time 0.87 seconds
Started Jul 17 08:01:30 PM PDT 24
Finished Jul 17 08:01:35 PM PDT 24
Peak memory 206456 kb
Host smart-2700e6ce-bd84-43a3-8a0f-4d55141ef74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32244
10832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3224410832
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3287530542
Short name T1153
Test name
Test status
Simulation time 198963142 ps
CPU time 0.89 seconds
Started Jul 17 08:01:28 PM PDT 24
Finished Jul 17 08:01:34 PM PDT 24
Peak memory 206452 kb
Host smart-28214457-289c-4062-b943-5634f888fbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32875
30542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3287530542
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3688217330
Short name T702
Test name
Test status
Simulation time 189374204 ps
CPU time 0.81 seconds
Started Jul 17 08:01:54 PM PDT 24
Finished Jul 17 08:01:55 PM PDT 24
Peak memory 206452 kb
Host smart-b14e21f9-8053-45ec-b2da-8a71b07723fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36882
17330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3688217330
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.941889997
Short name T1081
Test name
Test status
Simulation time 211855798 ps
CPU time 0.88 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206436 kb
Host smart-a07112bf-0946-4411-adf7-ca534bb6ea79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94188
9997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.941889997
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1886202534
Short name T2631
Test name
Test status
Simulation time 142300104 ps
CPU time 0.75 seconds
Started Jul 17 08:01:53 PM PDT 24
Finished Jul 17 08:01:54 PM PDT 24
Peak memory 206620 kb
Host smart-56e83a4a-6b78-41ae-81d3-369b71fc1462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18862
02534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1886202534
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.4256165702
Short name T1008
Test name
Test status
Simulation time 176398720 ps
CPU time 0.81 seconds
Started Jul 17 08:01:53 PM PDT 24
Finished Jul 17 08:01:54 PM PDT 24
Peak memory 206436 kb
Host smart-af671fef-a2bc-46ba-bc80-5ad1489bdd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42561
65702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.4256165702
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2382447418
Short name T1622
Test name
Test status
Simulation time 154128861 ps
CPU time 0.77 seconds
Started Jul 17 08:01:57 PM PDT 24
Finished Jul 17 08:02:00 PM PDT 24
Peak memory 206456 kb
Host smart-70751458-d021-4072-985a-b6c5d133b5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23824
47418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2382447418
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.199245282
Short name T2071
Test name
Test status
Simulation time 211659484 ps
CPU time 0.93 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206316 kb
Host smart-80b4d3b4-f84e-438c-ae62-c5a0fc89a756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924
5282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.199245282
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3416211966
Short name T1820
Test name
Test status
Simulation time 4435021832 ps
CPU time 127.28 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:04:08 PM PDT 24
Peak memory 206640 kb
Host smart-4254d824-3cfa-48bc-92df-3686745aef83
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3416211966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3416211966
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2870309662
Short name T2728
Test name
Test status
Simulation time 203780753 ps
CPU time 0.83 seconds
Started Jul 17 08:01:53 PM PDT 24
Finished Jul 17 08:01:55 PM PDT 24
Peak memory 206444 kb
Host smart-174cdd04-7430-47a2-bcff-afb961640e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28703
09662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2870309662
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.4198511578
Short name T1582
Test name
Test status
Simulation time 185783163 ps
CPU time 0.85 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206224 kb
Host smart-138e98a3-062c-4008-ae9c-cdf343c9ba58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41985
11578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.4198511578
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.1893538753
Short name T798
Test name
Test status
Simulation time 919196967 ps
CPU time 2.04 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:07 PM PDT 24
Peak memory 206656 kb
Host smart-cec76c2a-37e9-4bf3-b1d7-354c8890e812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18935
38753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1893538753
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.232069914
Short name T175
Test name
Test status
Simulation time 5541637058 ps
CPU time 37.82 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:02:35 PM PDT 24
Peak memory 206664 kb
Host smart-6954b53e-7507-41ed-88ee-473b888fe93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23206
9914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.232069914
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3983130088
Short name T2500
Test name
Test status
Simulation time 47858599 ps
CPU time 0.69 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206432 kb
Host smart-f5b12ce4-f436-4df2-8898-8e5bc381f873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3983130088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3983130088
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.112656006
Short name T838
Test name
Test status
Simulation time 3921917627 ps
CPU time 5.58 seconds
Started Jul 17 08:01:57 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206636 kb
Host smart-41819fcc-99c8-4e5e-8cde-29b9d8198be4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=112656006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.112656006
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1724594787
Short name T2240
Test name
Test status
Simulation time 13374746855 ps
CPU time 16.16 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:25 PM PDT 24
Peak memory 206520 kb
Host smart-8daa1f50-c9f8-4c60-8c7d-964c237f8d9d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1724594787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1724594787
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.699949849
Short name T2090
Test name
Test status
Simulation time 23398835582 ps
CPU time 26.25 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206524 kb
Host smart-f45d11bb-9499-45bb-a7ee-9dbc725b49d1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=699949849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.699949849
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.30353928
Short name T373
Test name
Test status
Simulation time 151324565 ps
CPU time 0.81 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:06 PM PDT 24
Peak memory 206448 kb
Host smart-4ad36d2e-ee79-4ddd-b7e5-27a6699e4f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.30353928
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.498820545
Short name T1224
Test name
Test status
Simulation time 168590876 ps
CPU time 0.86 seconds
Started Jul 17 08:01:55 PM PDT 24
Finished Jul 17 08:01:56 PM PDT 24
Peak memory 206452 kb
Host smart-3548f97f-0ab3-46b8-b104-5e10b5f805e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49882
0545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.498820545
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.701114878
Short name T353
Test name
Test status
Simulation time 432093486 ps
CPU time 1.3 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:01:58 PM PDT 24
Peak memory 206476 kb
Host smart-48c9824d-22dc-43d6-87d8-41dcf734bd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70111
4878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.701114878
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.4292424024
Short name T1957
Test name
Test status
Simulation time 577323548 ps
CPU time 1.55 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206456 kb
Host smart-1b2d56da-1b3e-4f16-ae41-eccbabe419e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42924
24024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.4292424024
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3703125245
Short name T931
Test name
Test status
Simulation time 15763597567 ps
CPU time 30.54 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:38 PM PDT 24
Peak memory 206648 kb
Host smart-34a0bbeb-563e-4b9b-83bb-68baf5c27818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
25245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3703125245
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3917914702
Short name T1076
Test name
Test status
Simulation time 312211791 ps
CPU time 1.15 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:01:59 PM PDT 24
Peak memory 206428 kb
Host smart-74dd594b-c3ae-41fb-857e-2d11b0adf839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39179
14702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3917914702
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1392289206
Short name T2084
Test name
Test status
Simulation time 138231342 ps
CPU time 0.81 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206172 kb
Host smart-307a99e8-05bf-4290-99de-ef703235d9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13922
89206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1392289206
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2916803476
Short name T427
Test name
Test status
Simulation time 47458107 ps
CPU time 0.69 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206440 kb
Host smart-6cee1f70-245f-49f5-9bbf-0662448c190f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29168
03476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2916803476
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3020641971
Short name T570
Test name
Test status
Simulation time 926695297 ps
CPU time 2.18 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:02:00 PM PDT 24
Peak memory 206588 kb
Host smart-1731af8b-2990-426c-a10c-e87ff1596d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30206
41971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3020641971
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1676337377
Short name T1790
Test name
Test status
Simulation time 287841251 ps
CPU time 1.99 seconds
Started Jul 17 08:01:54 PM PDT 24
Finished Jul 17 08:01:57 PM PDT 24
Peak memory 206224 kb
Host smart-b9fc61b3-b579-477e-8987-3dec1fc4ad39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16763
37377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1676337377
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1848191209
Short name T2396
Test name
Test status
Simulation time 197254458 ps
CPU time 0.84 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:01:58 PM PDT 24
Peak memory 206464 kb
Host smart-3baa47e9-4145-4572-a51d-eaac835ea701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18481
91209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1848191209
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1462347949
Short name T340
Test name
Test status
Simulation time 144044363 ps
CPU time 0.79 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206448 kb
Host smart-f7f9c85d-9162-412b-9963-a8689becaac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
47949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1462347949
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3767547732
Short name T1933
Test name
Test status
Simulation time 202188277 ps
CPU time 0.84 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206388 kb
Host smart-97751d6d-bb5f-46ed-8d3e-21c7f4312746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37675
47732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3767547732
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1969864222
Short name T367
Test name
Test status
Simulation time 227464943 ps
CPU time 0.88 seconds
Started Jul 17 08:01:54 PM PDT 24
Finished Jul 17 08:01:56 PM PDT 24
Peak memory 205960 kb
Host smart-b30e3bf8-fa5f-40bb-b29d-35148194cb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
64222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1969864222
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.1009216529
Short name T2120
Test name
Test status
Simulation time 23320312773 ps
CPU time 25.4 seconds
Started Jul 17 08:01:59 PM PDT 24
Finished Jul 17 08:02:27 PM PDT 24
Peak memory 206516 kb
Host smart-25f0c9c5-9637-408a-8ee4-e0a3fe40d972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10092
16529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1009216529
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3244427522
Short name T1721
Test name
Test status
Simulation time 3374613670 ps
CPU time 3.74 seconds
Started Jul 17 08:01:59 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206524 kb
Host smart-bd71b067-d39c-488c-9336-799f2b04d9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32444
27522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3244427522
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.806268014
Short name T2714
Test name
Test status
Simulation time 10544322891 ps
CPU time 298.94 seconds
Started Jul 17 08:01:57 PM PDT 24
Finished Jul 17 08:06:58 PM PDT 24
Peak memory 206720 kb
Host smart-13efad30-eab1-4866-ac15-199339140ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80626
8014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.806268014
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.681221261
Short name T1536
Test name
Test status
Simulation time 5578448897 ps
CPU time 149.12 seconds
Started Jul 17 08:01:59 PM PDT 24
Finished Jul 17 08:04:32 PM PDT 24
Peak memory 206656 kb
Host smart-5b1025ad-d325-48c5-aebb-b99f1727d913
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=681221261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.681221261
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.151634683
Short name T955
Test name
Test status
Simulation time 293226022 ps
CPU time 0.9 seconds
Started Jul 17 08:01:50 PM PDT 24
Finished Jul 17 08:01:52 PM PDT 24
Peak memory 206448 kb
Host smart-fd643cdb-061a-4e2b-bab6-1cb848db2086
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=151634683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.151634683
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3361864185
Short name T1177
Test name
Test status
Simulation time 194982493 ps
CPU time 0.89 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206444 kb
Host smart-02fc9c72-1b59-43d0-8dd6-31146ef3dccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33618
64185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3361864185
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3446024246
Short name T2094
Test name
Test status
Simulation time 4925942044 ps
CPU time 128.56 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:04:09 PM PDT 24
Peak memory 206668 kb
Host smart-fc937222-940e-408b-89a2-6ea4988ed548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34460
24246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3446024246
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.4114181006
Short name T2450
Test name
Test status
Simulation time 6940353078 ps
CPU time 184.07 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:05:02 PM PDT 24
Peak memory 206664 kb
Host smart-7887f283-2f50-4ad8-9053-fd6a151259e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4114181006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.4114181006
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3944192176
Short name T779
Test name
Test status
Simulation time 152914310 ps
CPU time 0.79 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206456 kb
Host smart-db4c01a0-ae2d-49f3-9aa6-c9b1a9c43093
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3944192176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3944192176
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3905438595
Short name T1453
Test name
Test status
Simulation time 152879620 ps
CPU time 0.79 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:01:58 PM PDT 24
Peak memory 206468 kb
Host smart-a09ce139-1771-41a3-847d-39872d469026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39054
38595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3905438595
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3312796883
Short name T2050
Test name
Test status
Simulation time 179004651 ps
CPU time 0.85 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206396 kb
Host smart-463e7628-e3c6-4491-a8f6-ca8c9680f154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33127
96883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3312796883
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2447236317
Short name T2605
Test name
Test status
Simulation time 197973662 ps
CPU time 0.84 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206368 kb
Host smart-3d3ebade-a708-4198-8b58-3952160cfc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24472
36317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2447236317
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.353083547
Short name T2403
Test name
Test status
Simulation time 162949582 ps
CPU time 0.83 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206460 kb
Host smart-352397c3-15c7-408c-919c-9d672b7a1381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35308
3547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.353083547
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1277658721
Short name T1557
Test name
Test status
Simulation time 149375172 ps
CPU time 0.86 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206396 kb
Host smart-9c031d04-ec7b-4246-8cd1-7d6848387032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12776
58721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1277658721
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.586378450
Short name T545
Test name
Test status
Simulation time 175366726 ps
CPU time 0.9 seconds
Started Jul 17 08:01:54 PM PDT 24
Finished Jul 17 08:01:56 PM PDT 24
Peak memory 206456 kb
Host smart-c8c4b404-46cf-4a52-98c1-bd216d07b38c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=586378450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.586378450
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1504801554
Short name T88
Test name
Test status
Simulation time 145286222 ps
CPU time 0.82 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:02 PM PDT 24
Peak memory 206404 kb
Host smart-58d7702a-5a4d-4063-8f53-f0d9a5c9f3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15048
01554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1504801554
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2421271930
Short name T601
Test name
Test status
Simulation time 34070345 ps
CPU time 0.66 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206448 kb
Host smart-babd4be6-637e-46c3-98ae-dc61912753ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24212
71930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2421271930
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1246353149
Short name T32
Test name
Test status
Simulation time 15924055995 ps
CPU time 38.93 seconds
Started Jul 17 08:01:55 PM PDT 24
Finished Jul 17 08:02:34 PM PDT 24
Peak memory 206724 kb
Host smart-2e02c0d3-abdd-4d26-87a9-4554670b2a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463
53149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1246353149
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3623789413
Short name T1158
Test name
Test status
Simulation time 143308383 ps
CPU time 0.78 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:01:58 PM PDT 24
Peak memory 206468 kb
Host smart-79c796f8-a9d2-4b1d-b64a-b4be0c2744f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
89413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3623789413
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2411353229
Short name T1264
Test name
Test status
Simulation time 240811878 ps
CPU time 1.03 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206424 kb
Host smart-22c582d9-0bb4-4b61-97a8-5edaac2e15ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24113
53229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2411353229
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3136827095
Short name T300
Test name
Test status
Simulation time 200121430 ps
CPU time 0.88 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206332 kb
Host smart-cbc3bd01-9c45-4782-8b23-620b04fbf3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31368
27095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3136827095
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.387903146
Short name T658
Test name
Test status
Simulation time 175865722 ps
CPU time 0.9 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206452 kb
Host smart-93c59e56-ff5d-4f7b-b232-5aeda5fe2460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38790
3146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.387903146
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1716503838
Short name T819
Test name
Test status
Simulation time 143544643 ps
CPU time 0.79 seconds
Started Jul 17 08:02:02 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206448 kb
Host smart-c5d48804-7e2f-40ae-aa34-17d8489f34a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17165
03838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1716503838
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3527684737
Short name T1441
Test name
Test status
Simulation time 150964706 ps
CPU time 0.78 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206460 kb
Host smart-08b49480-e453-4ef4-8a90-ef13eae1f2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
84737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3527684737
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3946097625
Short name T1771
Test name
Test status
Simulation time 145470028 ps
CPU time 0.76 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:07 PM PDT 24
Peak memory 206460 kb
Host smart-4237997a-5970-45cb-86db-570558c6624e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39460
97625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3946097625
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1696704133
Short name T2345
Test name
Test status
Simulation time 272467848 ps
CPU time 1.05 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206448 kb
Host smart-29f01642-9a4b-4a59-a313-42d322f610d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16967
04133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1696704133
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3838258699
Short name T2138
Test name
Test status
Simulation time 4719000878 ps
CPU time 34.16 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:39 PM PDT 24
Peak memory 206648 kb
Host smart-e446337a-2c71-4f2c-902c-b4b4922eef83
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3838258699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3838258699
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.320295234
Short name T1734
Test name
Test status
Simulation time 155756250 ps
CPU time 0.79 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206412 kb
Host smart-51271b34-cc99-404a-a4a4-6781fb003551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32029
5234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.320295234
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1456778080
Short name T2131
Test name
Test status
Simulation time 183303251 ps
CPU time 0.81 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206452 kb
Host smart-88df35f9-1ba5-45b7-88a2-3c7206a5ffdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14567
78080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1456778080
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.1686327705
Short name T1476
Test name
Test status
Simulation time 325070327 ps
CPU time 1.06 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206380 kb
Host smart-545417d6-8a25-448d-b905-79aec24840be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16863
27705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.1686327705
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.700034100
Short name T2696
Test name
Test status
Simulation time 7109133662 ps
CPU time 205.56 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:05:37 PM PDT 24
Peak memory 206664 kb
Host smart-aec75ee8-283e-445a-8089-94907b4bdde2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70003
4100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.700034100
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1852806907
Short name T2515
Test name
Test status
Simulation time 38154023 ps
CPU time 0.67 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206100 kb
Host smart-8d7e864a-f40a-43bc-ab7a-72c140460f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1852806907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1852806907
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3094036624
Short name T1619
Test name
Test status
Simulation time 4329145873 ps
CPU time 6 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:17 PM PDT 24
Peak memory 206520 kb
Host smart-274ff3ad-e015-4f23-a3e3-e7a29e75520b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3094036624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3094036624
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2216520174
Short name T1506
Test name
Test status
Simulation time 13346408353 ps
CPU time 13.31 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:20 PM PDT 24
Peak memory 206736 kb
Host smart-6bcdbb55-13a3-4e8f-bb45-0b8375f8d910
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2216520174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2216520174
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2945032983
Short name T472
Test name
Test status
Simulation time 23338773220 ps
CPU time 23.53 seconds
Started Jul 17 08:02:02 PM PDT 24
Finished Jul 17 08:02:31 PM PDT 24
Peak memory 206532 kb
Host smart-ab22f368-de47-46d1-a615-1d187b43b7e8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2945032983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2945032983
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2338332758
Short name T2719
Test name
Test status
Simulation time 143855764 ps
CPU time 0.78 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206356 kb
Host smart-6c624b21-6a19-42e6-a663-3868be735b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23383
32758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2338332758
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2979333663
Short name T2723
Test name
Test status
Simulation time 148159873 ps
CPU time 0.8 seconds
Started Jul 17 08:02:02 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206468 kb
Host smart-4f9e776a-8374-4c09-a67a-e6fd499304a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29793
33663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2979333663
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.4185143277
Short name T1270
Test name
Test status
Simulation time 238460096 ps
CPU time 0.93 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206460 kb
Host smart-8a59c233-2a25-4d9a-bebd-ede1b71d740f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41851
43277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.4185143277
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.19884728
Short name T1187
Test name
Test status
Simulation time 363623594 ps
CPU time 1.07 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:06 PM PDT 24
Peak memory 206456 kb
Host smart-4eddf38b-7cce-4b5d-b0fc-a2b8342786e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19884
728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.19884728
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.4238853285
Short name T89
Test name
Test status
Simulation time 20829306899 ps
CPU time 35.26 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:47 PM PDT 24
Peak memory 206592 kb
Host smart-f3b1e361-c37d-4ee1-aed4-5a220bfa0bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42388
53285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.4238853285
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.4264651705
Short name T666
Test name
Test status
Simulation time 473691938 ps
CPU time 1.42 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206348 kb
Host smart-a237c541-d1af-4666-abf6-26b2f4982e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646
51705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.4264651705
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2600467710
Short name T453
Test name
Test status
Simulation time 157792073 ps
CPU time 0.82 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:12 PM PDT 24
Peak memory 206456 kb
Host smart-2605a847-8829-4ee9-b67e-0cedf5a80423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26004
67710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2600467710
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.853507816
Short name T930
Test name
Test status
Simulation time 72537231 ps
CPU time 0.7 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:06 PM PDT 24
Peak memory 206396 kb
Host smart-18ddc5e4-2ee1-4461-b5eb-512ebb59b0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85350
7816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.853507816
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.4263865097
Short name T857
Test name
Test status
Simulation time 786116947 ps
CPU time 1.87 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:06 PM PDT 24
Peak memory 206668 kb
Host smart-cbeb6f03-403a-4e94-b4dc-c354a63600d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42638
65097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.4263865097
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.211631632
Short name T1075
Test name
Test status
Simulation time 440350998 ps
CPU time 2.39 seconds
Started Jul 17 08:01:56 PM PDT 24
Finished Jul 17 08:02:01 PM PDT 24
Peak memory 206624 kb
Host smart-394a3e46-99af-4c47-ac27-1d5680bd8924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21163
1632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.211631632
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1559438071
Short name T1334
Test name
Test status
Simulation time 213050166 ps
CPU time 0.92 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206404 kb
Host smart-72d215d6-8a91-4d86-8389-5b933f43f87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15594
38071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1559438071
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1666317567
Short name T2421
Test name
Test status
Simulation time 147233643 ps
CPU time 0.79 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206448 kb
Host smart-e294ec4e-f1f7-43df-989b-27118ffb569a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16663
17567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1666317567
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2817313574
Short name T1596
Test name
Test status
Simulation time 245566282 ps
CPU time 0.92 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206356 kb
Host smart-3e1d6cb7-2703-4673-8264-2bc422680b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28173
13574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2817313574
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3996061868
Short name T1423
Test name
Test status
Simulation time 7863150170 ps
CPU time 60.28 seconds
Started Jul 17 08:01:59 PM PDT 24
Finished Jul 17 08:03:03 PM PDT 24
Peak memory 206728 kb
Host smart-34c9f82b-4da3-48ec-a191-136eb3cd89b3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3996061868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3996061868
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.1177613704
Short name T1877
Test name
Test status
Simulation time 12343515537 ps
CPU time 100.8 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:03:45 PM PDT 24
Peak memory 206728 kb
Host smart-5ecaf6fe-2dc9-441a-92cf-e669263f8d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776
13704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1177613704
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2804443377
Short name T333
Test name
Test status
Simulation time 200582121 ps
CPU time 0.94 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:02 PM PDT 24
Peak memory 206436 kb
Host smart-9616b786-a4d9-48be-9c1a-8f0cc51470d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28044
43377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2804443377
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.3102883886
Short name T1806
Test name
Test status
Simulation time 23279839523 ps
CPU time 23.24 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:32 PM PDT 24
Peak memory 206500 kb
Host smart-8e43c2a6-2cf3-4bb4-b49c-905444b138ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31028
83886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.3102883886
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3961658412
Short name T608
Test name
Test status
Simulation time 3265135913 ps
CPU time 3.88 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206460 kb
Host smart-2649f584-41ef-48ef-add2-b78b46a18245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
58412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3961658412
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2305539288
Short name T1967
Test name
Test status
Simulation time 11170262416 ps
CPU time 80.88 seconds
Started Jul 17 08:02:02 PM PDT 24
Finished Jul 17 08:03:28 PM PDT 24
Peak memory 206652 kb
Host smart-c1efa678-3508-4340-a354-94798b3248d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23055
39288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2305539288
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.253370846
Short name T1114
Test name
Test status
Simulation time 3968788134 ps
CPU time 26.61 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:36 PM PDT 24
Peak memory 206616 kb
Host smart-e03a1275-dfff-4602-8122-d045450688c9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=253370846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.253370846
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2376341318
Short name T2747
Test name
Test status
Simulation time 253747369 ps
CPU time 0.92 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206448 kb
Host smart-5fded523-7d6d-4f7f-9f49-9d2970bb6be8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2376341318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2376341318
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2111446691
Short name T1552
Test name
Test status
Simulation time 200126940 ps
CPU time 0.85 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206440 kb
Host smart-ba664da7-bc4b-4d36-82a7-28f37f2f36f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21114
46691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2111446691
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.800914247
Short name T1311
Test name
Test status
Simulation time 5533002899 ps
CPU time 154.99 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:04:45 PM PDT 24
Peak memory 206732 kb
Host smart-34969b24-d086-4f2e-91cc-b3238433d02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80091
4247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.800914247
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1304119920
Short name T2106
Test name
Test status
Simulation time 4508812928 ps
CPU time 32.5 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:42 PM PDT 24
Peak memory 206656 kb
Host smart-935cdefb-406f-45a7-950c-c3237bc09544
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1304119920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1304119920
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.526471890
Short name T716
Test name
Test status
Simulation time 184604302 ps
CPU time 0.77 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:06 PM PDT 24
Peak memory 206464 kb
Host smart-475dca92-8a82-47f8-9be8-89aa85a17f23
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=526471890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.526471890
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3160447284
Short name T2000
Test name
Test status
Simulation time 142438517 ps
CPU time 0.82 seconds
Started Jul 17 08:02:02 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206464 kb
Host smart-52ead771-36d3-4084-a30d-3a6736b71e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31604
47284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3160447284
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2706678749
Short name T2381
Test name
Test status
Simulation time 214139492 ps
CPU time 0.85 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206468 kb
Host smart-f9153989-60be-4bca-8da7-2023842b1c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27066
78749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2706678749
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3040827913
Short name T1454
Test name
Test status
Simulation time 197170544 ps
CPU time 0.88 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206436 kb
Host smart-3c15d3fd-4379-4343-a9d0-0d5252c3ceee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30408
27913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3040827913
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.929378511
Short name T1832
Test name
Test status
Simulation time 191282445 ps
CPU time 0.8 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:06 PM PDT 24
Peak memory 206464 kb
Host smart-3c34f4f8-bb83-43c4-a942-524eba0f95f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92937
8511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.929378511
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2736849109
Short name T1862
Test name
Test status
Simulation time 236800868 ps
CPU time 0.87 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:12 PM PDT 24
Peak memory 206420 kb
Host smart-329b5213-6665-4a9b-b536-67c44e8045dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27368
49109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2736849109
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.270740454
Short name T1090
Test name
Test status
Simulation time 192870446 ps
CPU time 0.82 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206464 kb
Host smart-5aafca5c-e245-4fdb-848d-a2be178743d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27074
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.270740454
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.973716037
Short name T2092
Test name
Test status
Simulation time 250009923 ps
CPU time 1.08 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:12 PM PDT 24
Peak memory 206444 kb
Host smart-206de836-c01f-4c57-9882-6da905929cf1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=973716037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.973716037
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3056793864
Short name T2342
Test name
Test status
Simulation time 159125061 ps
CPU time 0.81 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206112 kb
Host smart-89bfed42-fc55-4a1c-bbc5-887fc94db617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30567
93864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3056793864
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.852892682
Short name T39
Test name
Test status
Simulation time 35570089 ps
CPU time 0.7 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206040 kb
Host smart-22025222-0b35-452b-8814-c262b4c2d491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85289
2682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.852892682
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.895030422
Short name T2401
Test name
Test status
Simulation time 6224181709 ps
CPU time 13.4 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206736 kb
Host smart-7c36b1cc-171f-453a-a36e-2db67c9bd98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89503
0422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.895030422
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2198599494
Short name T2725
Test name
Test status
Simulation time 145060887 ps
CPU time 0.77 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206444 kb
Host smart-8cc9cc58-19eb-481a-90a2-6d2d96a17de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21985
99494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2198599494
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4105117124
Short name T1320
Test name
Test status
Simulation time 232797102 ps
CPU time 0.88 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206448 kb
Host smart-0a9e099d-30a1-487a-96d3-fb6884efeb19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41051
17124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4105117124
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2683610644
Short name T1398
Test name
Test status
Simulation time 255751935 ps
CPU time 0.88 seconds
Started Jul 17 08:02:02 PM PDT 24
Finished Jul 17 08:02:09 PM PDT 24
Peak memory 206464 kb
Host smart-1f4253e8-e41a-4335-8267-e70687e81576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26836
10644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2683610644
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1913282287
Short name T2557
Test name
Test status
Simulation time 169222599 ps
CPU time 0.84 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206424 kb
Host smart-a1c4c0be-aa70-435d-8dc6-6cbcadc86071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19132
82287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1913282287
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2538963686
Short name T2302
Test name
Test status
Simulation time 201320119 ps
CPU time 0.83 seconds
Started Jul 17 08:02:02 PM PDT 24
Finished Jul 17 08:02:09 PM PDT 24
Peak memory 206452 kb
Host smart-3627f39c-2e0b-400c-8219-428dc9e2b44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25389
63686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2538963686
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3385384328
Short name T364
Test name
Test status
Simulation time 160487365 ps
CPU time 0.83 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206216 kb
Host smart-066fc4db-5c27-4002-b7cb-8b23fe7cdc18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853
84328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3385384328
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1203092496
Short name T2686
Test name
Test status
Simulation time 150620276 ps
CPU time 0.77 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206444 kb
Host smart-c1481210-c2c7-4eb5-9b7e-e84113cefb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12030
92496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1203092496
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4267295101
Short name T1119
Test name
Test status
Simulation time 241410942 ps
CPU time 0.96 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206448 kb
Host smart-6f9a3735-10a8-4ebf-90c7-2da9db1cedae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42672
95101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4267295101
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.1164835796
Short name T1651
Test name
Test status
Simulation time 3706867579 ps
CPU time 33.86 seconds
Started Jul 17 08:01:57 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206644 kb
Host smart-56bc6701-2e65-44f6-b423-1c83f655b593
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1164835796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.1164835796
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.425591850
Short name T2581
Test name
Test status
Simulation time 202843132 ps
CPU time 0.82 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:07 PM PDT 24
Peak memory 206460 kb
Host smart-614c0357-340c-47fb-8760-dbc5881cab9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42559
1850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.425591850
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3336557490
Short name T1198
Test name
Test status
Simulation time 205617932 ps
CPU time 0.87 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:12 PM PDT 24
Peak memory 206456 kb
Host smart-7ca2c2a8-1ad3-409e-a44e-ef4d6104d497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33365
57490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3336557490
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3195926822
Short name T2155
Test name
Test status
Simulation time 1060939397 ps
CPU time 2.37 seconds
Started Jul 17 08:02:02 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206664 kb
Host smart-d5d5c1ee-f521-4e16-93d3-504d4e15b024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31959
26822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3195926822
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.4150531630
Short name T1554
Test name
Test status
Simulation time 4585267830 ps
CPU time 32.19 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:44 PM PDT 24
Peak memory 206660 kb
Host smart-ba2396b8-65bf-4371-84fe-45cc5323717f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41505
31630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.4150531630
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.2966850325
Short name T1639
Test name
Test status
Simulation time 118311566 ps
CPU time 0.77 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:23 PM PDT 24
Peak memory 206416 kb
Host smart-98d46722-3f5e-429b-8dd5-e69d2ee7a1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2966850325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.2966850325
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.492751309
Short name T669
Test name
Test status
Simulation time 3890462375 ps
CPU time 4.74 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206700 kb
Host smart-d36cd2f4-1276-427a-96f7-dbe4ca28d979
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=492751309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.492751309
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2693763053
Short name T1366
Test name
Test status
Simulation time 13371644659 ps
CPU time 11.61 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:18 PM PDT 24
Peak memory 206672 kb
Host smart-43903dc4-2797-4cd1-805d-937c23ff52c6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2693763053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2693763053
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.728172161
Short name T2186
Test name
Test status
Simulation time 23426594028 ps
CPU time 22.56 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:35 PM PDT 24
Peak memory 206448 kb
Host smart-d7f1fe68-3f3a-42d9-88bc-4a970e1a949e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=728172161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.728172161
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3470468729
Short name T28
Test name
Test status
Simulation time 186191732 ps
CPU time 0.83 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206412 kb
Host smart-7861d594-c3d8-4216-bf69-5c46300ac697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
68729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3470468729
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1489342110
Short name T2555
Test name
Test status
Simulation time 143065337 ps
CPU time 0.83 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:12 PM PDT 24
Peak memory 206460 kb
Host smart-3a765c79-5789-46f2-8261-f66094f35d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14893
42110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1489342110
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.1158282806
Short name T808
Test name
Test status
Simulation time 255987823 ps
CPU time 0.98 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206456 kb
Host smart-987631f3-f1e6-40ae-bf7f-f94b2d31ac94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11582
82806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1158282806
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2223544843
Short name T2126
Test name
Test status
Simulation time 721959515 ps
CPU time 1.77 seconds
Started Jul 17 08:02:05 PM PDT 24
Finished Jul 17 08:02:14 PM PDT 24
Peak memory 206656 kb
Host smart-8b76c9c1-aae0-4908-90b9-f3176c47dd91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22235
44843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2223544843
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.1729503009
Short name T1062
Test name
Test status
Simulation time 11270269584 ps
CPU time 19.87 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:21 PM PDT 24
Peak memory 206660 kb
Host smart-a6efc495-8fb7-4707-b0e2-9efde16e41ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17295
03009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1729503009
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2141117300
Short name T1652
Test name
Test status
Simulation time 424080826 ps
CPU time 1.38 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:06 PM PDT 24
Peak memory 206460 kb
Host smart-f9702483-af3d-4562-8d25-27eacd4b08e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21411
17300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2141117300
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1247524342
Short name T2479
Test name
Test status
Simulation time 146101552 ps
CPU time 0.74 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:05 PM PDT 24
Peak memory 206464 kb
Host smart-6df8481f-a7d4-48cc-82a2-3ebe2c6c0338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12475
24342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1247524342
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.853946047
Short name T82
Test name
Test status
Simulation time 53174159 ps
CPU time 0.67 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206452 kb
Host smart-63967220-e24c-41fc-b840-fb127f459ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85394
6047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.853946047
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.4095201540
Short name T1417
Test name
Test status
Simulation time 898186995 ps
CPU time 1.98 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:13 PM PDT 24
Peak memory 206596 kb
Host smart-0b80a524-6f23-4de3-91dc-4ca682744b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952
01540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.4095201540
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.531895541
Short name T2317
Test name
Test status
Simulation time 331233863 ps
CPU time 1.97 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:02:07 PM PDT 24
Peak memory 206656 kb
Host smart-16327607-d41f-46b5-a654-57364542e1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53189
5541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.531895541
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2051737576
Short name T1804
Test name
Test status
Simulation time 313415214 ps
CPU time 1.08 seconds
Started Jul 17 08:01:58 PM PDT 24
Finished Jul 17 08:02:02 PM PDT 24
Peak memory 206452 kb
Host smart-cc0928aa-aac1-4bd2-9ca5-b135eda93ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20517
37576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2051737576
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.771826643
Short name T1682
Test name
Test status
Simulation time 146632260 ps
CPU time 0.83 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206444 kb
Host smart-41d9dea3-3fce-4513-8751-a276da2ca5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77182
6643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.771826643
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2596797708
Short name T736
Test name
Test status
Simulation time 234925577 ps
CPU time 0.94 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206400 kb
Host smart-2165fc36-1fbd-4579-b6b7-cfd0a0ad5699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25967
97708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2596797708
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.542347503
Short name T1510
Test name
Test status
Simulation time 7957126847 ps
CPU time 225.6 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:05:52 PM PDT 24
Peak memory 206672 kb
Host smart-e4eb0aeb-2afb-45d2-ad96-a9782dd8032d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=542347503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.542347503
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.3301972907
Short name T1755
Test name
Test status
Simulation time 6119653725 ps
CPU time 53.71 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:03:04 PM PDT 24
Peak memory 206664 kb
Host smart-ceba26b0-591d-4c4c-a92d-fac91d1c1cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33019
72907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.3301972907
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3513501977
Short name T1616
Test name
Test status
Simulation time 168718015 ps
CPU time 0.81 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:11 PM PDT 24
Peak memory 206440 kb
Host smart-853879f5-f2fc-451b-b619-3ec5697740e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35135
01977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3513501977
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.4245192256
Short name T1010
Test name
Test status
Simulation time 23270335225 ps
CPU time 23.84 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:34 PM PDT 24
Peak memory 206512 kb
Host smart-2f86a060-99b9-4c61-b370-634f63368b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42451
92256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.4245192256
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.145086412
Short name T2074
Test name
Test status
Simulation time 3352662131 ps
CPU time 3.87 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:14 PM PDT 24
Peak memory 206524 kb
Host smart-babed84c-3de3-4f90-8097-a65bdf2cb9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14508
6412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.145086412
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2483194205
Short name T790
Test name
Test status
Simulation time 9578639862 ps
CPU time 250.77 seconds
Started Jul 17 08:02:00 PM PDT 24
Finished Jul 17 08:06:15 PM PDT 24
Peak memory 206664 kb
Host smart-4cb55616-0f08-42c5-a48e-44ba24d82ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24831
94205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2483194205
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.530815908
Short name T2635
Test name
Test status
Simulation time 4699302141 ps
CPU time 126.83 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:04:18 PM PDT 24
Peak memory 206680 kb
Host smart-0ebb1fa1-1d15-4842-8f2a-8a72cc6c5664
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=530815908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.530815908
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1485768391
Short name T513
Test name
Test status
Simulation time 239900811 ps
CPU time 0.93 seconds
Started Jul 17 08:02:03 PM PDT 24
Finished Jul 17 08:02:10 PM PDT 24
Peak memory 206448 kb
Host smart-d9dcc593-1510-4568-9262-af2e71c30eef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1485768391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1485768391
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1342401053
Short name T2222
Test name
Test status
Simulation time 188448494 ps
CPU time 0.88 seconds
Started Jul 17 08:02:04 PM PDT 24
Finished Jul 17 08:02:12 PM PDT 24
Peak memory 206456 kb
Host smart-371a655a-fcea-4391-9cb9-477896569ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13424
01053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1342401053
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2172202664
Short name T408
Test name
Test status
Simulation time 5694372765 ps
CPU time 43.91 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:49 PM PDT 24
Peak memory 206676 kb
Host smart-12f80d33-2abe-4538-90d0-276587f7e26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21722
02664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2172202664
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.1347295658
Short name T956
Test name
Test status
Simulation time 3640470325 ps
CPU time 101.39 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:03:47 PM PDT 24
Peak memory 206656 kb
Host smart-3e2318c1-76b0-42dd-82c0-ccf01bb3f677
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1347295658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1347295658
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2641555161
Short name T349
Test name
Test status
Simulation time 178477383 ps
CPU time 0.86 seconds
Started Jul 17 08:02:01 PM PDT 24
Finished Jul 17 08:02:08 PM PDT 24
Peak memory 206460 kb
Host smart-bf6fd1bc-2652-47bf-9df8-4264c9a6d206
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2641555161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2641555161
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4029515485
Short name T1560
Test name
Test status
Simulation time 150172757 ps
CPU time 0.83 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:23 PM PDT 24
Peak memory 206448 kb
Host smart-a0d581fc-d457-4cfa-befe-596d6adc404f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40295
15485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4029515485
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2066990431
Short name T2325
Test name
Test status
Simulation time 198102489 ps
CPU time 0.86 seconds
Started Jul 17 08:02:14 PM PDT 24
Finished Jul 17 08:02:16 PM PDT 24
Peak memory 206456 kb
Host smart-d275e165-4629-410b-8dca-7c39b7de4096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20669
90431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2066990431
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2966748830
Short name T1288
Test name
Test status
Simulation time 154616237 ps
CPU time 0.82 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:02:18 PM PDT 24
Peak memory 206460 kb
Host smart-c639b058-f028-4b79-9357-41f79e844240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29667
48830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2966748830
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3899243769
Short name T2731
Test name
Test status
Simulation time 187659558 ps
CPU time 0.81 seconds
Started Jul 17 08:02:18 PM PDT 24
Finished Jul 17 08:02:22 PM PDT 24
Peak memory 206408 kb
Host smart-da65121e-02ca-463c-ab6e-81e7224d1034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38992
43769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3899243769
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3304177549
Short name T2657
Test name
Test status
Simulation time 187649983 ps
CPU time 0.86 seconds
Started Jul 17 08:02:22 PM PDT 24
Finished Jul 17 08:02:28 PM PDT 24
Peak memory 206464 kb
Host smart-95ce92b7-dcd9-41bf-8475-d7c06b8be5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33041
77549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3304177549
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.1801138514
Short name T2177
Test name
Test status
Simulation time 184146824 ps
CPU time 0.84 seconds
Started Jul 17 08:02:28 PM PDT 24
Finished Jul 17 08:02:34 PM PDT 24
Peak memory 206456 kb
Host smart-8c58da5f-3bee-4af4-bb75-a7af8eb2c875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18011
38514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1801138514
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.740561806
Short name T1531
Test name
Test status
Simulation time 209194956 ps
CPU time 0.88 seconds
Started Jul 17 08:02:14 PM PDT 24
Finished Jul 17 08:02:15 PM PDT 24
Peak memory 206432 kb
Host smart-6b41ab8c-0172-44fd-b4e7-5be47414fb9a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=740561806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.740561806
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.4039863381
Short name T703
Test name
Test status
Simulation time 161334886 ps
CPU time 0.79 seconds
Started Jul 17 08:02:15 PM PDT 24
Finished Jul 17 08:02:16 PM PDT 24
Peak memory 206632 kb
Host smart-02b16436-272c-4a54-a908-cb43b629bc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40398
63381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.4039863381
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2402231453
Short name T727
Test name
Test status
Simulation time 37979713 ps
CPU time 0.67 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:02:19 PM PDT 24
Peak memory 206444 kb
Host smart-b158959b-a299-446a-9e06-e814ab335365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24022
31453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2402231453
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3052660096
Short name T1675
Test name
Test status
Simulation time 18591379509 ps
CPU time 42.13 seconds
Started Jul 17 08:02:12 PM PDT 24
Finished Jul 17 08:02:56 PM PDT 24
Peak memory 206692 kb
Host smart-6b7c86d5-c98e-4785-9a91-8d1b6afd6f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30526
60096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3052660096
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.650807083
Short name T1979
Test name
Test status
Simulation time 171214739 ps
CPU time 0.85 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:02:18 PM PDT 24
Peak memory 206460 kb
Host smart-f900eab6-5994-4008-9e22-36810ad59826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65080
7083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.650807083
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2198005202
Short name T2004
Test name
Test status
Simulation time 195433956 ps
CPU time 0.91 seconds
Started Jul 17 08:02:15 PM PDT 24
Finished Jul 17 08:02:17 PM PDT 24
Peak memory 206580 kb
Host smart-3770ed36-f9ee-42d9-9f61-d41eaf3c8d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
05202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2198005202
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.2791398286
Short name T2057
Test name
Test status
Simulation time 175043712 ps
CPU time 0.78 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:02:19 PM PDT 24
Peak memory 206460 kb
Host smart-a4a9008b-3390-420a-bd88-67d9778fe6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27913
98286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.2791398286
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.4212540529
Short name T1138
Test name
Test status
Simulation time 178681718 ps
CPU time 0.85 seconds
Started Jul 17 08:02:11 PM PDT 24
Finished Jul 17 08:02:14 PM PDT 24
Peak memory 206452 kb
Host smart-41b303ba-23cf-4a2e-94e2-b5713e97dd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42125
40529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.4212540529
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.652370789
Short name T1895
Test name
Test status
Simulation time 140684062 ps
CPU time 0.77 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:02:20 PM PDT 24
Peak memory 206436 kb
Host smart-cf137d8f-4d19-406d-8753-e4ddbf6572bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65237
0789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.652370789
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1273786243
Short name T919
Test name
Test status
Simulation time 154941849 ps
CPU time 0.78 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:23 PM PDT 24
Peak memory 206444 kb
Host smart-995f58e2-f3ed-4288-930a-fcb633497a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737
86243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1273786243
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.4122716613
Short name T368
Test name
Test status
Simulation time 182997923 ps
CPU time 0.81 seconds
Started Jul 17 08:02:15 PM PDT 24
Finished Jul 17 08:02:17 PM PDT 24
Peak memory 206468 kb
Host smart-4d068662-76df-484b-a981-534eb7d523ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41227
16613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.4122716613
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3951440359
Short name T1975
Test name
Test status
Simulation time 203116609 ps
CPU time 0.88 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206376 kb
Host smart-2f44bfb5-0af2-4a91-afbb-9e3a37744916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39514
40359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3951440359
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2295079654
Short name T511
Test name
Test status
Simulation time 5247003070 ps
CPU time 145.72 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:04:47 PM PDT 24
Peak memory 206620 kb
Host smart-fa7519ff-e008-4fa1-80cc-bd0cbad90c11
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2295079654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2295079654
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2716119732
Short name T2079
Test name
Test status
Simulation time 147430247 ps
CPU time 0.74 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206400 kb
Host smart-38ac1ba6-7f90-4982-9b47-2cee3beb6750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27161
19732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2716119732
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2410590246
Short name T1043
Test name
Test status
Simulation time 145671283 ps
CPU time 0.76 seconds
Started Jul 17 08:02:14 PM PDT 24
Finished Jul 17 08:02:16 PM PDT 24
Peak memory 206436 kb
Host smart-97dc6111-6ede-4e5c-92c5-4732a120c45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24105
90246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2410590246
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.2798837412
Short name T2022
Test name
Test status
Simulation time 266241899 ps
CPU time 0.96 seconds
Started Jul 17 08:02:15 PM PDT 24
Finished Jul 17 08:02:17 PM PDT 24
Peak memory 206456 kb
Host smart-3f4dda95-82ab-469c-a6d3-693396486168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
37412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.2798837412
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2365300955
Short name T1368
Test name
Test status
Simulation time 4512758764 ps
CPU time 43.32 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:03:03 PM PDT 24
Peak memory 206672 kb
Host smart-655012d3-31a6-4ad4-a1d1-c685522e977c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23653
00955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2365300955
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3808074883
Short name T2483
Test name
Test status
Simulation time 107384082 ps
CPU time 0.73 seconds
Started Jul 17 08:02:31 PM PDT 24
Finished Jul 17 08:02:36 PM PDT 24
Peak memory 206428 kb
Host smart-0336c704-4793-4d8f-a04c-a720880bd2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3808074883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3808074883
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3331657733
Short name T423
Test name
Test status
Simulation time 3841686332 ps
CPU time 4.17 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:28 PM PDT 24
Peak memory 206668 kb
Host smart-5ae92465-dd79-4650-8c98-cb6f4c1c1950
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3331657733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3331657733
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.304418471
Short name T1016
Test name
Test status
Simulation time 13384471163 ps
CPU time 14.23 seconds
Started Jul 17 08:02:15 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206492 kb
Host smart-ad34f71d-a882-42bd-9c80-fd19a5fef0a9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=304418471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.304418471
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2363382416
Short name T950
Test name
Test status
Simulation time 23365557033 ps
CPU time 22.59 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:46 PM PDT 24
Peak memory 206656 kb
Host smart-d0803651-545e-40c4-a758-5e585456a023
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2363382416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.2363382416
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3471706370
Short name T2012
Test name
Test status
Simulation time 157706515 ps
CPU time 0.77 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:02:18 PM PDT 24
Peak memory 206456 kb
Host smart-5e49ece9-441c-4e61-9896-1ad8dee96222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34717
06370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3471706370
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2373668695
Short name T1683
Test name
Test status
Simulation time 188503531 ps
CPU time 0.89 seconds
Started Jul 17 08:02:18 PM PDT 24
Finished Jul 17 08:02:22 PM PDT 24
Peak memory 206400 kb
Host smart-28be236e-70cf-4f50-9023-3ce842567437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23736
68695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2373668695
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3016703104
Short name T1634
Test name
Test status
Simulation time 164251407 ps
CPU time 0.86 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206440 kb
Host smart-60f374b8-9848-401a-be11-d7d6502bcaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30167
03104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3016703104
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.575275959
Short name T1571
Test name
Test status
Simulation time 1347589648 ps
CPU time 2.96 seconds
Started Jul 17 08:02:18 PM PDT 24
Finished Jul 17 08:02:23 PM PDT 24
Peak memory 206576 kb
Host smart-e556d160-172f-4b07-942f-2adb0925c5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57527
5959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.575275959
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.4281097797
Short name T1345
Test name
Test status
Simulation time 13802035391 ps
CPU time 25.64 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:50 PM PDT 24
Peak memory 206724 kb
Host smart-730ea5ed-1042-4dda-ba97-68ac6727ca44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42810
97797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.4281097797
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.958240605
Short name T488
Test name
Test status
Simulation time 420346762 ps
CPU time 1.36 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:25 PM PDT 24
Peak memory 206464 kb
Host smart-b3ac7a16-b083-4a26-90fa-514ebac51e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95824
0605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.958240605
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.4204564777
Short name T941
Test name
Test status
Simulation time 199155383 ps
CPU time 0.78 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:02:18 PM PDT 24
Peak memory 206452 kb
Host smart-bc2d776f-6d49-4c31-8f40-d881a86c5f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42045
64777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.4204564777
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2967693632
Short name T777
Test name
Test status
Simulation time 47419211 ps
CPU time 0.66 seconds
Started Jul 17 08:02:27 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206448 kb
Host smart-3dd82699-4229-45ef-ae31-253d7d83406a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29676
93632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2967693632
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.480286769
Short name T576
Test name
Test status
Simulation time 918397946 ps
CPU time 2.2 seconds
Started Jul 17 08:02:23 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206664 kb
Host smart-c7516240-e12e-48a3-926d-ccceaffd051e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48028
6769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.480286769
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.576180758
Short name T848
Test name
Test status
Simulation time 168362319 ps
CPU time 1.5 seconds
Started Jul 17 08:02:28 PM PDT 24
Finished Jul 17 08:02:35 PM PDT 24
Peak memory 206644 kb
Host smart-a17eefa9-5dee-4700-9993-8c8fa71f58a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57618
0758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.576180758
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2310062535
Short name T2276
Test name
Test status
Simulation time 152025424 ps
CPU time 0.77 seconds
Started Jul 17 08:02:27 PM PDT 24
Finished Jul 17 08:02:34 PM PDT 24
Peak memory 206444 kb
Host smart-be800821-69c3-4850-98bb-707fa893bed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23100
62535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2310062535
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3971662170
Short name T1116
Test name
Test status
Simulation time 140182028 ps
CPU time 0.73 seconds
Started Jul 17 08:02:23 PM PDT 24
Finished Jul 17 08:02:28 PM PDT 24
Peak memory 206452 kb
Host smart-d197f24f-dad1-40fc-bb44-ab21ae876190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39716
62170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3971662170
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2889315076
Short name T1487
Test name
Test status
Simulation time 198423488 ps
CPU time 0.93 seconds
Started Jul 17 08:02:30 PM PDT 24
Finished Jul 17 08:02:35 PM PDT 24
Peak memory 206448 kb
Host smart-49f61e6e-db2a-4c4c-a31c-3ea098485e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
15076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2889315076
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1652231139
Short name T2289
Test name
Test status
Simulation time 6374212784 ps
CPU time 47.42 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:03:16 PM PDT 24
Peak memory 206716 kb
Host smart-e9bb02bc-7ce9-4dc0-8732-ba41dd0e40af
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1652231139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1652231139
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.4018006136
Short name T1332
Test name
Test status
Simulation time 206700773 ps
CPU time 0.83 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206212 kb
Host smart-238faf66-ac98-42de-9393-683c3d5745b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40180
06136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.4018006136
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2821954904
Short name T1886
Test name
Test status
Simulation time 23257363704 ps
CPU time 22.48 seconds
Started Jul 17 08:02:32 PM PDT 24
Finished Jul 17 08:03:04 PM PDT 24
Peak memory 206512 kb
Host smart-90e5daa1-4a64-448f-af5f-b4cf9d5a91ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28219
54904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2821954904
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2495865627
Short name T1220
Test name
Test status
Simulation time 3324411666 ps
CPU time 3.92 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:02:35 PM PDT 24
Peak memory 206188 kb
Host smart-165cd492-9c79-433a-b1c0-4f745b4c1d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24958
65627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2495865627
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.108723341
Short name T1378
Test name
Test status
Simulation time 12035115817 ps
CPU time 88.82 seconds
Started Jul 17 08:02:18 PM PDT 24
Finished Jul 17 08:03:49 PM PDT 24
Peak memory 206732 kb
Host smart-1239fc73-fc06-4519-965f-f8c42658ae03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10872
3341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.108723341
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2520380410
Short name T477
Test name
Test status
Simulation time 5924835516 ps
CPU time 165.62 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:05:05 PM PDT 24
Peak memory 206668 kb
Host smart-3c7cdd33-51d4-4972-b0a1-03de02f84c9d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2520380410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2520380410
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2270766048
Short name T2518
Test name
Test status
Simulation time 274694188 ps
CPU time 0.91 seconds
Started Jul 17 08:02:18 PM PDT 24
Finished Jul 17 08:02:22 PM PDT 24
Peak memory 206448 kb
Host smart-1611aad4-99ce-4c80-84fe-6c5d94fd1c5e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2270766048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2270766048
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3334285297
Short name T745
Test name
Test status
Simulation time 188995954 ps
CPU time 0.86 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:22 PM PDT 24
Peak memory 206428 kb
Host smart-494a3544-0f7c-4a95-8af7-f7ae7a70b962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33342
85297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3334285297
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.1717861357
Short name T1737
Test name
Test status
Simulation time 4690023157 ps
CPU time 127.94 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:04:30 PM PDT 24
Peak memory 206644 kb
Host smart-fbd13683-7bb4-4d42-b216-beda1cefe184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17178
61357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.1717861357
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.1108476732
Short name T1413
Test name
Test status
Simulation time 5435348050 ps
CPU time 145.96 seconds
Started Jul 17 08:02:38 PM PDT 24
Finished Jul 17 08:05:08 PM PDT 24
Peak memory 206692 kb
Host smart-3f9af096-ddbc-4c23-a7c0-e7a41639ca2a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1108476732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.1108476732
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.485798807
Short name T1203
Test name
Test status
Simulation time 177898080 ps
CPU time 0.82 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:22 PM PDT 24
Peak memory 206448 kb
Host smart-ff4e8451-a908-4c88-81b4-6998800cb271
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=485798807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.485798807
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1456805674
Short name T1589
Test name
Test status
Simulation time 151615533 ps
CPU time 0.81 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:23 PM PDT 24
Peak memory 206444 kb
Host smart-991c6ee8-0aa9-4366-bbfe-a3f1d1e121f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14568
05674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1456805674
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2619676093
Short name T97
Test name
Test status
Simulation time 206350931 ps
CPU time 0.88 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206448 kb
Host smart-8c0b1cac-0886-470c-a65f-e05f1dc4edd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26196
76093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2619676093
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.22145599
Short name T2069
Test name
Test status
Simulation time 242733842 ps
CPU time 0.9 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:25 PM PDT 24
Peak memory 206412 kb
Host smart-3dd3a431-5cba-48fd-a294-748a81457b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22145
599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.22145599
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3851716714
Short name T1483
Test name
Test status
Simulation time 154940639 ps
CPU time 0.77 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:22 PM PDT 24
Peak memory 206416 kb
Host smart-8b9345c3-6cb3-42d0-a5c7-a0d76f3c1ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
16714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3851716714
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2493403975
Short name T538
Test name
Test status
Simulation time 169741943 ps
CPU time 0.8 seconds
Started Jul 17 08:02:18 PM PDT 24
Finished Jul 17 08:02:22 PM PDT 24
Peak memory 206408 kb
Host smart-81be25fd-bd1d-448b-8306-515fef5900ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24934
03975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2493403975
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2254725966
Short name T1995
Test name
Test status
Simulation time 192007523 ps
CPU time 0.83 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:23 PM PDT 24
Peak memory 206420 kb
Host smart-a381bf8f-38c6-4e40-9d1a-3759cca525a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22547
25966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2254725966
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1685543044
Short name T1887
Test name
Test status
Simulation time 214551903 ps
CPU time 0.95 seconds
Started Jul 17 08:02:19 PM PDT 24
Finished Jul 17 08:02:24 PM PDT 24
Peak memory 206460 kb
Host smart-67c24832-904c-4c59-9636-1d30fcabb072
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1685543044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1685543044
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4133654070
Short name T2243
Test name
Test status
Simulation time 144877455 ps
CPU time 0.74 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:02:20 PM PDT 24
Peak memory 206452 kb
Host smart-cc2784c8-1b21-4002-93c3-01fc6760cb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41336
54070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4133654070
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3102253374
Short name T653
Test name
Test status
Simulation time 39270103 ps
CPU time 0.65 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:02:20 PM PDT 24
Peak memory 206428 kb
Host smart-20f46f3b-0c6f-439f-8ce7-eceda5512f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31022
53374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3102253374
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2944921579
Short name T2328
Test name
Test status
Simulation time 17842035875 ps
CPU time 39.13 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:02:57 PM PDT 24
Peak memory 214948 kb
Host smart-d3f8ff28-b753-47b6-8d05-731d3bf79dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29449
21579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2944921579
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.684332228
Short name T754
Test name
Test status
Simulation time 171128032 ps
CPU time 0.83 seconds
Started Jul 17 08:02:27 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206460 kb
Host smart-aca9b7fd-510a-46be-9bfe-1561c36cdb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68433
2228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.684332228
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1726924406
Short name T1534
Test name
Test status
Simulation time 214539811 ps
CPU time 0.87 seconds
Started Jul 17 08:02:27 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206448 kb
Host smart-aa85d836-e41e-42b5-bc34-959c3b4eed6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17269
24406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1726924406
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.119247601
Short name T422
Test name
Test status
Simulation time 212680555 ps
CPU time 0.89 seconds
Started Jul 17 08:02:29 PM PDT 24
Finished Jul 17 08:02:35 PM PDT 24
Peak memory 206456 kb
Host smart-0749d940-f192-466a-9413-123102cbaab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
7601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.119247601
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2086632896
Short name T809
Test name
Test status
Simulation time 257465526 ps
CPU time 0.88 seconds
Started Jul 17 08:02:34 PM PDT 24
Finished Jul 17 08:02:37 PM PDT 24
Peak memory 206456 kb
Host smart-4757d7ff-3f47-4abd-9eb5-54640c713d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20866
32896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2086632896
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3413546533
Short name T1140
Test name
Test status
Simulation time 181014649 ps
CPU time 0.86 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206368 kb
Host smart-ffbff7fa-6525-4336-9b73-1eab99298387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34135
46533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3413546533
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3619742466
Short name T1803
Test name
Test status
Simulation time 160456609 ps
CPU time 0.82 seconds
Started Jul 17 08:02:33 PM PDT 24
Finished Jul 17 08:02:37 PM PDT 24
Peak memory 206444 kb
Host smart-3e536a1f-97ac-4d4d-91a7-1e5651692014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197
42466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3619742466
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2394974427
Short name T2087
Test name
Test status
Simulation time 179206812 ps
CPU time 0.8 seconds
Started Jul 17 08:02:23 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206476 kb
Host smart-0d0dfefa-3f96-4109-888d-e23b77b379ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23949
74427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2394974427
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2603890155
Short name T906
Test name
Test status
Simulation time 207864030 ps
CPU time 0.88 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206376 kb
Host smart-f8588853-092b-45de-b367-c8f0571f048d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26038
90155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2603890155
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2144370478
Short name T760
Test name
Test status
Simulation time 162581226 ps
CPU time 0.78 seconds
Started Jul 17 08:02:27 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206464 kb
Host smart-47717c5d-f439-4ada-a2ca-d35900ae4f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21443
70478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2144370478
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.720414190
Short name T1911
Test name
Test status
Simulation time 149289197 ps
CPU time 0.77 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:02:32 PM PDT 24
Peak memory 205912 kb
Host smart-f9d5560e-ede9-4cb7-b4fe-44160707e63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72041
4190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.720414190
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2101458698
Short name T1761
Test name
Test status
Simulation time 1032976628 ps
CPU time 2.12 seconds
Started Jul 17 08:02:34 PM PDT 24
Finished Jul 17 08:02:39 PM PDT 24
Peak memory 206664 kb
Host smart-6d245fe6-c8e1-43ac-90d4-3a0474d0a01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21014
58698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2101458698
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3439218413
Short name T968
Test name
Test status
Simulation time 6821011899 ps
CPU time 189.16 seconds
Started Jul 17 08:02:28 PM PDT 24
Finished Jul 17 08:05:42 PM PDT 24
Peak memory 206688 kb
Host smart-742f2b50-f743-4177-8e1f-ba071a7406f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
18413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3439218413
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.4221153364
Short name T487
Test name
Test status
Simulation time 61162257 ps
CPU time 0.75 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206440 kb
Host smart-ff834001-01f0-4556-b823-047949e46fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4221153364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.4221153364
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2510236656
Short name T898
Test name
Test status
Simulation time 3709869460 ps
CPU time 5.27 seconds
Started Jul 17 08:02:31 PM PDT 24
Finished Jul 17 08:02:40 PM PDT 24
Peak memory 206664 kb
Host smart-64052763-b6be-48a4-a76b-1c9803ee6953
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2510236656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.2510236656
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2923508900
Short name T858
Test name
Test status
Simulation time 13355800142 ps
CPU time 14.6 seconds
Started Jul 17 08:02:31 PM PDT 24
Finished Jul 17 08:02:49 PM PDT 24
Peak memory 206516 kb
Host smart-5c252996-9374-4e7a-82b4-997b53ab7286
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2923508900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2923508900
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.613772274
Short name T1012
Test name
Test status
Simulation time 23330953056 ps
CPU time 29.38 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:03:01 PM PDT 24
Peak memory 206516 kb
Host smart-1316b730-dece-4be1-b93a-23ea710c57d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=613772274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.613772274
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.354850700
Short name T2420
Test name
Test status
Simulation time 204610561 ps
CPU time 0.85 seconds
Started Jul 17 08:02:25 PM PDT 24
Finished Jul 17 08:02:31 PM PDT 24
Peak memory 206324 kb
Host smart-c14a4838-a77c-4d34-932c-1fe94a079ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
0700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.354850700
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.4182991305
Short name T929
Test name
Test status
Simulation time 167427215 ps
CPU time 0.74 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206452 kb
Host smart-0338497e-6924-4e42-bfc9-3c870cd4eeba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41829
91305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.4182991305
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1043077971
Short name T1708
Test name
Test status
Simulation time 255392164 ps
CPU time 0.97 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:02:32 PM PDT 24
Peak memory 206452 kb
Host smart-5f32d20b-7829-4e86-a7c2-087369e3962b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10430
77971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1043077971
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.363037804
Short name T101
Test name
Test status
Simulation time 797808719 ps
CPU time 1.87 seconds
Started Jul 17 08:02:30 PM PDT 24
Finished Jul 17 08:02:36 PM PDT 24
Peak memory 206652 kb
Host smart-9b2dc523-da39-49b8-b015-eace6810c379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
7804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.363037804
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1873948505
Short name T2148
Test name
Test status
Simulation time 6533953370 ps
CPU time 12.28 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:02:42 PM PDT 24
Peak memory 206704 kb
Host smart-af7e9a53-6afd-45b1-ab01-058361cbf41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18739
48505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1873948505
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1989508027
Short name T1005
Test name
Test status
Simulation time 464276747 ps
CPU time 1.33 seconds
Started Jul 17 08:02:40 PM PDT 24
Finished Jul 17 08:02:46 PM PDT 24
Peak memory 206456 kb
Host smart-9ed29a3a-5f66-4037-94b1-93d3d8a2920c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
08027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1989508027
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3350394432
Short name T434
Test name
Test status
Simulation time 178910520 ps
CPU time 0.76 seconds
Started Jul 17 08:02:23 PM PDT 24
Finished Jul 17 08:02:28 PM PDT 24
Peak memory 206456 kb
Host smart-24a02602-58f8-469f-be94-b78d50b02a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33503
94432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3350394432
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1694161428
Short name T1517
Test name
Test status
Simulation time 62038425 ps
CPU time 0.71 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206448 kb
Host smart-eab779fd-bfbc-4e6e-916e-2a6adc33c1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16941
61428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1694161428
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.4093796105
Short name T2452
Test name
Test status
Simulation time 978803315 ps
CPU time 2.05 seconds
Started Jul 17 08:02:28 PM PDT 24
Finished Jul 17 08:02:36 PM PDT 24
Peak memory 206636 kb
Host smart-f21ffdbc-abe7-475e-b54f-aae854bbc440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
96105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.4093796105
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1040801106
Short name T1772
Test name
Test status
Simulation time 351395357 ps
CPU time 2.05 seconds
Started Jul 17 08:02:36 PM PDT 24
Finished Jul 17 08:02:41 PM PDT 24
Peak memory 206648 kb
Host smart-0b085941-958f-4a27-99f5-aef23f0fa0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10408
01106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1040801106
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1663342776
Short name T2549
Test name
Test status
Simulation time 158260366 ps
CPU time 0.8 seconds
Started Jul 17 08:02:23 PM PDT 24
Finished Jul 17 08:02:28 PM PDT 24
Peak memory 206444 kb
Host smart-ec17a145-082d-4300-8338-84f939171deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16633
42776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1663342776
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3240800488
Short name T530
Test name
Test status
Simulation time 145635190 ps
CPU time 0.82 seconds
Started Jul 17 08:02:23 PM PDT 24
Finished Jul 17 08:02:28 PM PDT 24
Peak memory 206456 kb
Host smart-19c68ab4-ee5e-4d9a-b5aa-135399fb9954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32408
00488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3240800488
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1121869341
Short name T725
Test name
Test status
Simulation time 178566680 ps
CPU time 0.81 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:02:19 PM PDT 24
Peak memory 206452 kb
Host smart-5684b237-70f1-47bf-be61-fdea26fd0c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11218
69341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1121869341
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1887526497
Short name T2369
Test name
Test status
Simulation time 7523405332 ps
CPU time 208.59 seconds
Started Jul 17 08:02:33 PM PDT 24
Finished Jul 17 08:06:04 PM PDT 24
Peak memory 206636 kb
Host smart-8c7c00b4-0655-4d78-8b24-2cd6a6e97c46
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1887526497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1887526497
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.3733406335
Short name T237
Test name
Test status
Simulation time 10229849403 ps
CPU time 38.21 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:02:57 PM PDT 24
Peak memory 206656 kb
Host smart-e8cc2235-f3d1-4c7a-808b-25290dbb3114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37334
06335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.3733406335
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.816335671
Short name T1884
Test name
Test status
Simulation time 245791693 ps
CPU time 0.92 seconds
Started Jul 17 08:02:15 PM PDT 24
Finished Jul 17 08:02:17 PM PDT 24
Peak memory 206448 kb
Host smart-36757ee4-edab-4f23-a69b-ee3c74791da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81633
5671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.816335671
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1008270804
Short name T506
Test name
Test status
Simulation time 23396882905 ps
CPU time 22.98 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:47 PM PDT 24
Peak memory 206520 kb
Host smart-cc44dc26-e0ea-4303-b37a-14b3fe95ea06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10082
70804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1008270804
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.319157459
Short name T1057
Test name
Test status
Simulation time 3270144976 ps
CPU time 3.83 seconds
Started Jul 17 08:02:15 PM PDT 24
Finished Jul 17 08:02:20 PM PDT 24
Peak memory 206516 kb
Host smart-2d8c1a13-9def-42a1-b71b-a2cd3a12f4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915
7459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.319157459
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.847273919
Short name T2183
Test name
Test status
Simulation time 10171844713 ps
CPU time 91.74 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:03:49 PM PDT 24
Peak memory 206732 kb
Host smart-d2a9b6d0-04dc-4688-8caa-77f1f9ecf106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84727
3919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.847273919
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3693385055
Short name T734
Test name
Test status
Simulation time 4733851395 ps
CPU time 45.99 seconds
Started Jul 17 08:02:15 PM PDT 24
Finished Jul 17 08:03:02 PM PDT 24
Peak memory 206652 kb
Host smart-abc3c489-04e7-4f82-abae-61d978102a81
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3693385055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3693385055
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.900857196
Short name T2107
Test name
Test status
Simulation time 242414699 ps
CPU time 0.89 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:02:20 PM PDT 24
Peak memory 206312 kb
Host smart-ac51cbf9-b064-4162-ad47-fbff76f7ccc5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=900857196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.900857196
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1994726346
Short name T699
Test name
Test status
Simulation time 212169539 ps
CPU time 0.87 seconds
Started Jul 17 08:02:16 PM PDT 24
Finished Jul 17 08:02:18 PM PDT 24
Peak memory 206452 kb
Host smart-907ba49b-31b5-445e-972f-51b32d5822b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19947
26346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1994726346
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2170260624
Short name T2270
Test name
Test status
Simulation time 4581473082 ps
CPU time 33.37 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:02:53 PM PDT 24
Peak memory 206564 kb
Host smart-b178004d-bba5-4bf9-8191-49198c898a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21702
60624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2170260624
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3197023237
Short name T1082
Test name
Test status
Simulation time 6007125978 ps
CPU time 42.91 seconds
Started Jul 17 08:02:27 PM PDT 24
Finished Jul 17 08:03:15 PM PDT 24
Peak memory 206656 kb
Host smart-b870d955-8bfb-43ea-99da-77eaef049230
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3197023237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3197023237
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.430485589
Short name T2496
Test name
Test status
Simulation time 162289130 ps
CPU time 0.83 seconds
Started Jul 17 08:02:27 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206460 kb
Host smart-5d30309a-960c-4ed0-90f5-c708f812013f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=430485589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.430485589
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3426237367
Short name T2206
Test name
Test status
Simulation time 148363393 ps
CPU time 0.76 seconds
Started Jul 17 08:02:21 PM PDT 24
Finished Jul 17 08:02:26 PM PDT 24
Peak memory 206444 kb
Host smart-83d6af28-c521-47f3-89f7-44f0d3148569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34262
37367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3426237367
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.718340729
Short name T2556
Test name
Test status
Simulation time 208314928 ps
CPU time 0.89 seconds
Started Jul 17 08:02:21 PM PDT 24
Finished Jul 17 08:02:26 PM PDT 24
Peak memory 206448 kb
Host smart-ec869d26-5c38-44d3-906b-e5c6e5717d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71834
0729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.718340729
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2564740335
Short name T743
Test name
Test status
Simulation time 150715986 ps
CPU time 0.8 seconds
Started Jul 17 08:02:17 PM PDT 24
Finished Jul 17 08:02:19 PM PDT 24
Peak memory 206440 kb
Host smart-a70f54cc-29db-4922-bc25-ce9dc09bb769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25647
40335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2564740335
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3502281495
Short name T2590
Test name
Test status
Simulation time 164629445 ps
CPU time 0.78 seconds
Started Jul 17 08:02:20 PM PDT 24
Finished Jul 17 08:02:25 PM PDT 24
Peak memory 206448 kb
Host smart-14f9e25a-587c-4388-80c2-c8915884e4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35022
81495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3502281495
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.380529266
Short name T957
Test name
Test status
Simulation time 198261670 ps
CPU time 0.81 seconds
Started Jul 17 08:02:27 PM PDT 24
Finished Jul 17 08:02:33 PM PDT 24
Peak memory 206456 kb
Host smart-a960bb40-b1a9-44b7-a695-ac698c944df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38052
9266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.380529266
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.4006601449
Short name T833
Test name
Test status
Simulation time 144038906 ps
CPU time 0.83 seconds
Started Jul 17 08:02:21 PM PDT 24
Finished Jul 17 08:02:26 PM PDT 24
Peak memory 206448 kb
Host smart-2c3ebb3e-b47b-437c-b48a-32e9136f32a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066
01449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.4006601449
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.506074295
Short name T438
Test name
Test status
Simulation time 220693712 ps
CPU time 0.95 seconds
Started Jul 17 08:02:21 PM PDT 24
Finished Jul 17 08:02:26 PM PDT 24
Peak memory 206452 kb
Host smart-476efbda-796d-4049-bd10-bfadec72bea8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=506074295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.506074295
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.462837564
Short name T461
Test name
Test status
Simulation time 136803594 ps
CPU time 0.77 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:02:32 PM PDT 24
Peak memory 206140 kb
Host smart-fc9abc1e-be97-4637-8b93-b446142e6290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46283
7564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.462837564
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.343818768
Short name T1349
Test name
Test status
Simulation time 47626452 ps
CPU time 0.63 seconds
Started Jul 17 08:02:33 PM PDT 24
Finished Jul 17 08:02:36 PM PDT 24
Peak memory 206452 kb
Host smart-26bd6b10-bfbb-4413-8c03-451ee046c266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34381
8768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.343818768
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1903591193
Short name T238
Test name
Test status
Simulation time 17215606162 ps
CPU time 35.73 seconds
Started Jul 17 08:02:28 PM PDT 24
Finished Jul 17 08:03:09 PM PDT 24
Peak memory 206704 kb
Host smart-58a5ec69-f2ab-4bd5-81eb-12c399c2586b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19035
91193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1903591193
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2227615500
Short name T948
Test name
Test status
Simulation time 193138318 ps
CPU time 0.79 seconds
Started Jul 17 08:02:28 PM PDT 24
Finished Jul 17 08:02:34 PM PDT 24
Peak memory 206448 kb
Host smart-16a13ebd-ef16-4c1d-bb1a-d038b8f5fa75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22276
15500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2227615500
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3429494897
Short name T322
Test name
Test status
Simulation time 220759899 ps
CPU time 0.89 seconds
Started Jul 17 08:02:28 PM PDT 24
Finished Jul 17 08:02:34 PM PDT 24
Peak memory 206452 kb
Host smart-c9eeafe5-68be-46b9-b77e-280e365b385e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34294
94897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3429494897
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1506062018
Short name T235
Test name
Test status
Simulation time 182548704 ps
CPU time 0.81 seconds
Started Jul 17 08:02:33 PM PDT 24
Finished Jul 17 08:02:37 PM PDT 24
Peak memory 206460 kb
Host smart-3d158fc9-1d68-4855-8bd2-d58afb3bdbf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15060
62018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1506062018
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2694313704
Short name T755
Test name
Test status
Simulation time 174664650 ps
CPU time 0.84 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:02:32 PM PDT 24
Peak memory 206380 kb
Host smart-be3c210f-8da8-4ba0-9cad-832d9a73cfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26943
13704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2694313704
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3982400386
Short name T1239
Test name
Test status
Simulation time 165930358 ps
CPU time 0.79 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:02:32 PM PDT 24
Peak memory 206148 kb
Host smart-93c93771-3d4c-478f-a1bf-6d3de4314c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39824
00386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3982400386
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2677822243
Short name T1274
Test name
Test status
Simulation time 157609150 ps
CPU time 0.74 seconds
Started Jul 17 08:02:32 PM PDT 24
Finished Jul 17 08:02:36 PM PDT 24
Peak memory 206456 kb
Host smart-89fc5361-4e6e-4aed-b00f-ac8392ce352b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26778
22243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2677822243
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3477791517
Short name T1271
Test name
Test status
Simulation time 148912973 ps
CPU time 0.79 seconds
Started Jul 17 08:02:25 PM PDT 24
Finished Jul 17 08:02:31 PM PDT 24
Peak memory 206312 kb
Host smart-601dfe1b-b6b7-4da1-8106-d63bae7766d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34777
91517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3477791517
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1069798095
Short name T548
Test name
Test status
Simulation time 209244463 ps
CPU time 0.86 seconds
Started Jul 17 08:02:29 PM PDT 24
Finished Jul 17 08:02:34 PM PDT 24
Peak memory 206448 kb
Host smart-2f2b234e-783e-4be8-87e7-fb20631a9075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10697
98095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1069798095
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1746087672
Short name T2428
Test name
Test status
Simulation time 5492879612 ps
CPU time 50.88 seconds
Started Jul 17 08:02:38 PM PDT 24
Finished Jul 17 08:03:33 PM PDT 24
Peak memory 206612 kb
Host smart-83e1e5c7-8895-4ce0-87e0-ff261dd7c829
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1746087672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1746087672
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1708776364
Short name T2372
Test name
Test status
Simulation time 195375607 ps
CPU time 0.78 seconds
Started Jul 17 08:02:26 PM PDT 24
Finished Jul 17 08:02:32 PM PDT 24
Peak memory 206456 kb
Host smart-b4a1979b-5e9a-48fb-883d-365fbb5b15e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17087
76364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1708776364
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.4249370151
Short name T2262
Test name
Test status
Simulation time 182295747 ps
CPU time 0.79 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 206440 kb
Host smart-26273c3e-e26b-446c-bd22-7bd88a4fa6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493
70151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.4249370151
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.757524137
Short name T2175
Test name
Test status
Simulation time 1139801728 ps
CPU time 2.75 seconds
Started Jul 17 08:02:23 PM PDT 24
Finished Jul 17 08:02:31 PM PDT 24
Peak memory 206616 kb
Host smart-b2a823f2-b563-44f4-bb6a-97ec82719a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75752
4137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.757524137
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.4251315460
Short name T1223
Test name
Test status
Simulation time 7699927679 ps
CPU time 76.55 seconds
Started Jul 17 08:02:24 PM PDT 24
Finished Jul 17 08:03:46 PM PDT 24
Peak memory 206668 kb
Host smart-5dbeda71-4a5c-451f-bc81-f66bdf8f5cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42513
15460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.4251315460
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2966772412
Short name T2241
Test name
Test status
Simulation time 37982390 ps
CPU time 0.7 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206424 kb
Host smart-249a7fb2-ca73-4c4c-a14a-5c43a86de367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2966772412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2966772412
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1688829308
Short name T1863
Test name
Test status
Simulation time 3490431292 ps
CPU time 4.79 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:18 PM PDT 24
Peak memory 206716 kb
Host smart-9c9c2b9e-4bc2-4045-8a57-7ba6b4350320
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1688829308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1688829308
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.147292079
Short name T1733
Test name
Test status
Simulation time 23428721134 ps
CPU time 24.3 seconds
Started Jul 17 07:54:07 PM PDT 24
Finished Jul 17 07:54:38 PM PDT 24
Peak memory 206640 kb
Host smart-78af91e4-56b4-49b3-98c6-cfc8f1c7fe27
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=147292079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.147292079
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2337354136
Short name T2176
Test name
Test status
Simulation time 188662029 ps
CPU time 0.83 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206444 kb
Host smart-4e0c7071-a22e-4abe-aabb-1e3faa58dc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23373
54136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2337354136
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3492628110
Short name T1633
Test name
Test status
Simulation time 144027857 ps
CPU time 0.73 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206456 kb
Host smart-ad130291-022b-4177-9385-876a08bf689e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34926
28110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3492628110
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.866998440
Short name T1706
Test name
Test status
Simulation time 382046541 ps
CPU time 1.25 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206460 kb
Host smart-c5fd3e1b-133b-4e8b-9166-fcdf81615d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86699
8440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.866998440
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1006771523
Short name T1940
Test name
Test status
Simulation time 746327431 ps
CPU time 1.86 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:15 PM PDT 24
Peak memory 206644 kb
Host smart-baa40ea6-160a-472d-b8d4-e7125a5b21fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10067
71523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1006771523
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1812987116
Short name T91
Test name
Test status
Simulation time 11486680196 ps
CPU time 20.97 seconds
Started Jul 17 07:53:56 PM PDT 24
Finished Jul 17 07:54:20 PM PDT 24
Peak memory 206648 kb
Host smart-e927d2fb-6d39-4006-b490-fad30eda87fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18129
87116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1812987116
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.2581824839
Short name T1535
Test name
Test status
Simulation time 355656627 ps
CPU time 1.15 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206440 kb
Host smart-394dc3f3-b868-4d04-9dba-fda199c17752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25818
24839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.2581824839
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2818698638
Short name T1907
Test name
Test status
Simulation time 187940404 ps
CPU time 0.81 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206460 kb
Host smart-e088173c-a5a1-4ca1-a383-553a4317c747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28186
98638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2818698638
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1146121217
Short name T1267
Test name
Test status
Simulation time 38892804 ps
CPU time 0.63 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206440 kb
Host smart-ebbd87bc-e28f-41b4-8091-06a200e22697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11461
21217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1146121217
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.737631313
Short name T1789
Test name
Test status
Simulation time 842969053 ps
CPU time 1.98 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 206500 kb
Host smart-496f3f1c-7b41-4ef1-8b4d-8a7f13ab5caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73763
1313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.737631313
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3749758658
Short name T370
Test name
Test status
Simulation time 285709824 ps
CPU time 1.95 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:18 PM PDT 24
Peak memory 206528 kb
Host smart-128edfdb-1963-410c-901d-73722cbca14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37497
58658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3749758658
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2354641841
Short name T108
Test name
Test status
Simulation time 162668737 ps
CPU time 0.83 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206436 kb
Host smart-31765da8-eaea-49a9-a81b-79210318ed6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23546
41841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2354641841
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3018634025
Short name T2361
Test name
Test status
Simulation time 151524033 ps
CPU time 0.76 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206456 kb
Host smart-a5f4e7ba-4e0b-43d9-9772-b37c902737f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30186
34025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3018634025
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2225013829
Short name T1286
Test name
Test status
Simulation time 231338797 ps
CPU time 0.96 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:04 PM PDT 24
Peak memory 206456 kb
Host smart-025a6e7e-1b4e-4204-b138-4b89e1d422fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22250
13829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2225013829
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1249169510
Short name T1677
Test name
Test status
Simulation time 7445689330 ps
CPU time 61.71 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:55:17 PM PDT 24
Peak memory 206728 kb
Host smart-9395ef87-84c0-47c9-9b1a-28c01e057a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12491
69510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1249169510
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.549549315
Short name T873
Test name
Test status
Simulation time 215605259 ps
CPU time 0.89 seconds
Started Jul 17 07:53:57 PM PDT 24
Finished Jul 17 07:54:02 PM PDT 24
Peak memory 206436 kb
Host smart-5243738e-164f-4631-93d1-574fdb977f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54954
9315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.549549315
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1129673957
Short name T394
Test name
Test status
Simulation time 23271506184 ps
CPU time 20.54 seconds
Started Jul 17 07:54:10 PM PDT 24
Finished Jul 17 07:54:37 PM PDT 24
Peak memory 206404 kb
Host smart-e1fdb656-8bb8-4796-bb5a-920d6e34dd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296
73957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1129673957
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1397915215
Short name T2739
Test name
Test status
Simulation time 3294196606 ps
CPU time 3.98 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:19 PM PDT 24
Peak memory 206516 kb
Host smart-ecce01f5-26b7-476e-b6e9-e5e621b4f424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13979
15215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1397915215
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1695443655
Short name T1367
Test name
Test status
Simulation time 9399145031 ps
CPU time 252.39 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:58:27 PM PDT 24
Peak memory 206732 kb
Host smart-4552e701-fe90-41a9-ad4c-4a26ec5dc052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16954
43655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1695443655
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2349379711
Short name T555
Test name
Test status
Simulation time 5573531030 ps
CPU time 158.27 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:56:44 PM PDT 24
Peak memory 206668 kb
Host smart-2977cfe4-f904-41c0-86b3-ab52a96da472
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2349379711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2349379711
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.67629327
Short name T2277
Test name
Test status
Simulation time 248210641 ps
CPU time 0.98 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206436 kb
Host smart-ceb870a9-c576-4cd5-976c-8d00ceee5427
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=67629327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.67629327
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.44059610
Short name T1601
Test name
Test status
Simulation time 195384470 ps
CPU time 0.82 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:03 PM PDT 24
Peak memory 206460 kb
Host smart-91bd5534-27f5-432b-b24c-81ed0de9c411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44059
610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.44059610
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3043433000
Short name T1837
Test name
Test status
Simulation time 5120278869 ps
CPU time 50.26 seconds
Started Jul 17 07:53:58 PM PDT 24
Finished Jul 17 07:54:53 PM PDT 24
Peak memory 206668 kb
Host smart-0dcb3830-2a05-47d1-beed-2ddba1ea5b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30434
33000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3043433000
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.750615429
Short name T1171
Test name
Test status
Simulation time 4747559178 ps
CPU time 129.86 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:56:16 PM PDT 24
Peak memory 206628 kb
Host smart-add30c92-3d6a-45de-9ed2-711b4cf2b82e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=750615429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.750615429
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3983375025
Short name T2269
Test name
Test status
Simulation time 160362987 ps
CPU time 0.79 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:07 PM PDT 24
Peak memory 206456 kb
Host smart-95e65d55-bef4-4c44-8ab2-d31503ce5902
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3983375025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3983375025
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2940283512
Short name T851
Test name
Test status
Simulation time 232201673 ps
CPU time 0.9 seconds
Started Jul 17 07:54:00 PM PDT 24
Finished Jul 17 07:54:06 PM PDT 24
Peak memory 206460 kb
Host smart-2208f7e7-8b99-45c2-a0c5-8fb41ff6efbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29402
83512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2940283512
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.4210074121
Short name T1469
Test name
Test status
Simulation time 206771465 ps
CPU time 0.88 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:09 PM PDT 24
Peak memory 206456 kb
Host smart-cfe60edf-e199-4ee7-bbad-dc0db584ba76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42100
74121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.4210074121
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2519783311
Short name T2539
Test name
Test status
Simulation time 241608388 ps
CPU time 0.89 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206236 kb
Host smart-d6a0d8a8-60c2-467d-b347-4c8cabeb392b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25197
83311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2519783311
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.769353218
Short name T2011
Test name
Test status
Simulation time 162313964 ps
CPU time 0.84 seconds
Started Jul 17 07:54:02 PM PDT 24
Finished Jul 17 07:54:09 PM PDT 24
Peak memory 206452 kb
Host smart-5deabb4e-b3ea-42f3-9f56-4c05ddbcdd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76935
3218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.769353218
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2317623503
Short name T2645
Test name
Test status
Simulation time 228975774 ps
CPU time 0.84 seconds
Started Jul 17 07:53:59 PM PDT 24
Finished Jul 17 07:54:04 PM PDT 24
Peak memory 206460 kb
Host smart-130fa8ef-3f5b-4349-be52-d59cb9b4f908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23176
23503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2317623503
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.218340048
Short name T1922
Test name
Test status
Simulation time 217147557 ps
CPU time 0.82 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:07 PM PDT 24
Peak memory 206460 kb
Host smart-29ebdde4-8df6-406f-a74b-8be3e68af9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21834
0048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.218340048
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2350796478
Short name T880
Test name
Test status
Simulation time 250441136 ps
CPU time 0.96 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:11 PM PDT 24
Peak memory 206544 kb
Host smart-ab4c64af-fa16-4ec8-b02e-cdca8fa65680
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2350796478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2350796478
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2172168202
Short name T2524
Test name
Test status
Simulation time 155512904 ps
CPU time 0.77 seconds
Started Jul 17 07:54:01 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 206456 kb
Host smart-8e0bd002-c4b1-48f6-a4c9-8bacba026a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21721
68202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2172168202
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3386524700
Short name T2060
Test name
Test status
Simulation time 36615065 ps
CPU time 0.66 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:11 PM PDT 24
Peak memory 206528 kb
Host smart-afe93404-f258-4843-a845-b9799ce85330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33865
24700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3386524700
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3978006527
Short name T2422
Test name
Test status
Simulation time 201746892 ps
CPU time 0.91 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:11 PM PDT 24
Peak memory 206540 kb
Host smart-4b41bdde-828d-448b-a11a-690b7c878437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39780
06527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3978006527
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1806326333
Short name T1279
Test name
Test status
Simulation time 240869810 ps
CPU time 0.92 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:11 PM PDT 24
Peak memory 206392 kb
Host smart-50654ce8-39fe-4ae2-91ba-473272ad1cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18063
26333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1806326333
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.4286005091
Short name T1705
Test name
Test status
Simulation time 12107415009 ps
CPU time 59.68 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:55:11 PM PDT 24
Peak memory 206696 kb
Host smart-8c6a0387-0760-4bc0-bfb8-e6c05818d8ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4286005091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.4286005091
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2424880634
Short name T2411
Test name
Test status
Simulation time 7599719360 ps
CPU time 183.98 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:57:15 PM PDT 24
Peak memory 206728 kb
Host smart-51fb511c-0556-43e9-b14c-549a65953d0e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2424880634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2424880634
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.637943072
Short name T1103
Test name
Test status
Simulation time 14756675166 ps
CPU time 290.11 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:59:02 PM PDT 24
Peak memory 206756 kb
Host smart-c9c768b7-604c-49cb-a02f-a7eef9c906e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=637943072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.637943072
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1700197884
Short name T2466
Test name
Test status
Simulation time 205029765 ps
CPU time 0.88 seconds
Started Jul 17 07:54:03 PM PDT 24
Finished Jul 17 07:54:10 PM PDT 24
Peak memory 206456 kb
Host smart-f5aa9cf6-f156-41cc-b2eb-65e86b54f5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17001
97884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1700197884
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1283696611
Short name T234
Test name
Test status
Simulation time 193332469 ps
CPU time 0.88 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:54:13 PM PDT 24
Peak memory 206380 kb
Host smart-925ed780-9191-4ad1-9348-98081472a940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12836
96611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1283696611
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.835933024
Short name T2159
Test name
Test status
Simulation time 156543928 ps
CPU time 0.74 seconds
Started Jul 17 07:54:04 PM PDT 24
Finished Jul 17 07:54:11 PM PDT 24
Peak memory 206440 kb
Host smart-0aabd88a-6e60-4a32-9b8e-faa28adac7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83593
3024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.835933024
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.136299708
Short name T2286
Test name
Test status
Simulation time 151524330 ps
CPU time 0.77 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206448 kb
Host smart-c07c3c62-1cb1-47fa-ae6b-d5fb61ccfa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
9708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.136299708
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.462719288
Short name T2510
Test name
Test status
Simulation time 180002764 ps
CPU time 0.81 seconds
Started Jul 17 07:54:05 PM PDT 24
Finished Jul 17 07:54:13 PM PDT 24
Peak memory 206448 kb
Host smart-3a17dad7-0d00-4adc-b167-806cb8df0e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46271
9288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.462719288
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1484204887
Short name T2101
Test name
Test status
Simulation time 207692376 ps
CPU time 0.87 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206436 kb
Host smart-d0a306ab-c2b1-422d-ac4a-e7bb44c3ea69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842
04887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1484204887
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1093067292
Short name T2114
Test name
Test status
Simulation time 5296512945 ps
CPU time 46.8 seconds
Started Jul 17 07:53:39 PM PDT 24
Finished Jul 17 07:54:27 PM PDT 24
Peak memory 206720 kb
Host smart-a0841179-0a16-4986-9f5f-e0b902fa88c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1093067292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1093067292
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3221643533
Short name T825
Test name
Test status
Simulation time 200098133 ps
CPU time 0.8 seconds
Started Jul 17 07:54:06 PM PDT 24
Finished Jul 17 07:54:14 PM PDT 24
Peak memory 206456 kb
Host smart-1805f930-74e3-4d57-990a-d7eb706dd195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
43533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3221643533
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1075620002
Short name T587
Test name
Test status
Simulation time 204464186 ps
CPU time 0.82 seconds
Started Jul 17 07:54:07 PM PDT 24
Finished Jul 17 07:54:15 PM PDT 24
Peak memory 206364 kb
Host smart-7acc0b94-424c-4b25-af84-8ba4b7cf2133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10756
20002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1075620002
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.1915412619
Short name T304
Test name
Test status
Simulation time 448493822 ps
CPU time 1.27 seconds
Started Jul 17 07:54:07 PM PDT 24
Finished Jul 17 07:54:16 PM PDT 24
Peak memory 206440 kb
Host smart-5c924f47-09eb-40fd-8440-95f5418e3516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19154
12619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.1915412619
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2845510095
Short name T1613
Test name
Test status
Simulation time 5495012116 ps
CPU time 51.4 seconds
Started Jul 17 07:54:07 PM PDT 24
Finished Jul 17 07:55:05 PM PDT 24
Peak memory 206440 kb
Host smart-370fdb1d-7021-4d42-b5eb-786ae28542d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28455
10095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2845510095
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1251061382
Short name T1013
Test name
Test status
Simulation time 50690247 ps
CPU time 0.71 seconds
Started Jul 17 07:54:39 PM PDT 24
Finished Jul 17 07:54:41 PM PDT 24
Peak memory 206448 kb
Host smart-d23a5b9d-eabd-4caa-b3da-9ec91617a94f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1251061382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1251061382
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.4087184668
Short name T455
Test name
Test status
Simulation time 3538178112 ps
CPU time 4.2 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:20 PM PDT 24
Peak memory 206496 kb
Host smart-2ca1d0eb-0116-47a9-813d-9bb6f13513a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4087184668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.4087184668
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.2589520852
Short name T2127
Test name
Test status
Simulation time 13397458182 ps
CPU time 14.95 seconds
Started Jul 17 07:54:09 PM PDT 24
Finished Jul 17 07:54:31 PM PDT 24
Peak memory 206644 kb
Host smart-8866a411-6163-41cd-bb6e-ce2b938aa54e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2589520852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.2589520852
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3885615250
Short name T205
Test name
Test status
Simulation time 23374779462 ps
CPU time 26.71 seconds
Started Jul 17 07:54:08 PM PDT 24
Finished Jul 17 07:54:42 PM PDT 24
Peak memory 206500 kb
Host smart-f998486b-c8e7-4f28-8af3-96780bd88f9c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3885615250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3885615250
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2915540047
Short name T1192
Test name
Test status
Simulation time 180170239 ps
CPU time 0.82 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:33 PM PDT 24
Peak memory 206448 kb
Host smart-8b754ebe-5954-403d-98e2-e99bb259338f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29155
40047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2915540047
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.774294517
Short name T644
Test name
Test status
Simulation time 139874009 ps
CPU time 0.73 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:34 PM PDT 24
Peak memory 206452 kb
Host smart-df03dfde-0746-4e12-86b8-9b8395486b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77429
4517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.774294517
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2041421663
Short name T2547
Test name
Test status
Simulation time 345663401 ps
CPU time 1.17 seconds
Started Jul 17 07:54:26 PM PDT 24
Finished Jul 17 07:54:29 PM PDT 24
Peak memory 206468 kb
Host smart-6052b5ee-4528-4e67-b7ca-0373b06a66c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20414
21663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2041421663
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2321706650
Short name T437
Test name
Test status
Simulation time 520185260 ps
CPU time 1.39 seconds
Started Jul 17 07:54:26 PM PDT 24
Finished Jul 17 07:54:29 PM PDT 24
Peak memory 206420 kb
Host smart-bd3d14ac-adb6-42dd-8c34-1cdaac770e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23217
06650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2321706650
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3780924350
Short name T1662
Test name
Test status
Simulation time 21657579155 ps
CPU time 41.91 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206648 kb
Host smart-3d8afa03-12e3-44c8-ac5c-88cfc8e8bec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
24350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3780924350
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.539193887
Short name T2583
Test name
Test status
Simulation time 335994971 ps
CPU time 1.23 seconds
Started Jul 17 07:54:26 PM PDT 24
Finished Jul 17 07:54:29 PM PDT 24
Peak memory 206452 kb
Host smart-ec99dec6-f4d9-4a79-9ff1-624b989df96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53919
3887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.539193887
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.634520765
Short name T1523
Test name
Test status
Simulation time 167074968 ps
CPU time 0.75 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:54:34 PM PDT 24
Peak memory 206448 kb
Host smart-22be1542-987c-4580-8d02-a2379a83e133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63452
0765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.634520765
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2947963966
Short name T1382
Test name
Test status
Simulation time 32068898 ps
CPU time 0.66 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:54:26 PM PDT 24
Peak memory 206384 kb
Host smart-98a3a40a-22ac-44f9-a3cb-acc0c8981e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29479
63966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2947963966
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3472527276
Short name T1265
Test name
Test status
Simulation time 787542293 ps
CPU time 1.99 seconds
Started Jul 17 07:54:24 PM PDT 24
Finished Jul 17 07:54:27 PM PDT 24
Peak memory 206644 kb
Host smart-5d4a340c-e454-418e-a244-b868b11243b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725
27276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3472527276
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3709928052
Short name T481
Test name
Test status
Simulation time 202923240 ps
CPU time 1.21 seconds
Started Jul 17 07:54:24 PM PDT 24
Finished Jul 17 07:54:26 PM PDT 24
Peak memory 206624 kb
Host smart-0c0d6cb9-e503-4050-8f5e-a709ee3fd31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37099
28052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3709928052
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1773399333
Short name T1637
Test name
Test status
Simulation time 232591008 ps
CPU time 0.9 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:54:28 PM PDT 24
Peak memory 206452 kb
Host smart-a8466bd2-d4a7-4ef0-af0b-3848d9e40fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17733
99333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1773399333
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3474472208
Short name T2247
Test name
Test status
Simulation time 198222418 ps
CPU time 0.83 seconds
Started Jul 17 07:54:27 PM PDT 24
Finished Jul 17 07:54:31 PM PDT 24
Peak memory 206620 kb
Host smart-f3db2c1a-db00-48c3-b6c2-8dbc8ff8ea09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34744
72208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3474472208
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.409948034
Short name T1520
Test name
Test status
Simulation time 193453698 ps
CPU time 0.85 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:54:28 PM PDT 24
Peak memory 206456 kb
Host smart-ed633acb-6557-4585-836c-f5b3c4b9441a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994
8034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.409948034
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.1172467897
Short name T6
Test name
Test status
Simulation time 6216008198 ps
CPU time 46.15 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:55:17 PM PDT 24
Peak memory 206724 kb
Host smart-c38ba80b-1aaf-4d9f-900a-39ad1babc728
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1172467897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.1172467897
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.3668051948
Short name T1691
Test name
Test status
Simulation time 12524396420 ps
CPU time 47.53 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:55:14 PM PDT 24
Peak memory 206720 kb
Host smart-68922fd6-e5f5-434d-8ebf-64cea703bc85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36680
51948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.3668051948
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2827337453
Short name T883
Test name
Test status
Simulation time 193458450 ps
CPU time 0.83 seconds
Started Jul 17 07:54:26 PM PDT 24
Finished Jul 17 07:54:28 PM PDT 24
Peak memory 206428 kb
Host smart-d4fa723d-007d-4720-b58b-97193726c221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28273
37453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2827337453
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2355913824
Short name T1815
Test name
Test status
Simulation time 23265132000 ps
CPU time 21.8 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:54:55 PM PDT 24
Peak memory 206492 kb
Host smart-d33778b4-955e-45b2-8ec1-942b2b149bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23559
13824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2355913824
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3782407147
Short name T2677
Test name
Test status
Simulation time 3300898140 ps
CPU time 4.47 seconds
Started Jul 17 07:54:26 PM PDT 24
Finished Jul 17 07:54:32 PM PDT 24
Peak memory 206480 kb
Host smart-340ba131-7559-4915-8764-0b23e31705cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37824
07147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3782407147
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1405902611
Short name T573
Test name
Test status
Simulation time 7989257525 ps
CPU time 223.16 seconds
Started Jul 17 07:54:26 PM PDT 24
Finished Jul 17 07:58:11 PM PDT 24
Peak memory 206748 kb
Host smart-a8cb16e6-0320-47ff-b1ac-a386553d329d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
02611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1405902611
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.242094113
Short name T2433
Test name
Test status
Simulation time 4690907740 ps
CPU time 42.32 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:55:13 PM PDT 24
Peak memory 206628 kb
Host smart-8777af23-4767-4b48-8f8b-be04362d65dc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=242094113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.242094113
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.3462330834
Short name T21
Test name
Test status
Simulation time 239004867 ps
CPU time 0.9 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:54:27 PM PDT 24
Peak memory 206460 kb
Host smart-402bf2bf-496b-4785-b23e-bac9f3777536
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3462330834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.3462330834
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.923663079
Short name T471
Test name
Test status
Simulation time 181436507 ps
CPU time 0.86 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:32 PM PDT 24
Peak memory 206432 kb
Host smart-29fd87bb-2f9e-42f4-85e8-5aea0fdab00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92366
3079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.923663079
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2027512059
Short name T505
Test name
Test status
Simulation time 5127390807 ps
CPU time 47.26 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:55:20 PM PDT 24
Peak memory 206660 kb
Host smart-02525126-c51f-40e4-8189-ff62a9032963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
12059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2027512059
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3274566363
Short name T2288
Test name
Test status
Simulation time 4198252220 ps
CPU time 30.87 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:55:03 PM PDT 24
Peak memory 206716 kb
Host smart-415a8e15-3931-4f0c-be7e-282a26b4671b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3274566363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3274566363
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.4042660433
Short name T971
Test name
Test status
Simulation time 181515609 ps
CPU time 0.82 seconds
Started Jul 17 07:54:30 PM PDT 24
Finished Jul 17 07:54:35 PM PDT 24
Peak memory 206452 kb
Host smart-6b30d75d-dc41-46af-812d-7a8b14e85cd4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4042660433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.4042660433
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.334705658
Short name T649
Test name
Test status
Simulation time 146259447 ps
CPU time 0.76 seconds
Started Jul 17 07:54:30 PM PDT 24
Finished Jul 17 07:54:34 PM PDT 24
Peak memory 206428 kb
Host smart-fd857262-9f8f-432f-a6ce-f017bef70898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33470
5658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.334705658
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3195515415
Short name T134
Test name
Test status
Simulation time 204469047 ps
CPU time 0.87 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:54:26 PM PDT 24
Peak memory 206456 kb
Host smart-e694dc16-c403-4ae0-8205-1a318519e944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31955
15415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3195515415
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3021619973
Short name T2419
Test name
Test status
Simulation time 167974572 ps
CPU time 0.8 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:54:34 PM PDT 24
Peak memory 206452 kb
Host smart-64b6f334-3b4b-4c75-bd67-8b312499ac47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
19973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3021619973
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1307671309
Short name T391
Test name
Test status
Simulation time 157508341 ps
CPU time 0.8 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:54:27 PM PDT 24
Peak memory 206452 kb
Host smart-d554f148-72e1-43cb-9b7c-19ccc586da5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13076
71309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1307671309
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3995585842
Short name T1030
Test name
Test status
Simulation time 189978120 ps
CPU time 0.82 seconds
Started Jul 17 07:54:32 PM PDT 24
Finished Jul 17 07:54:36 PM PDT 24
Peak memory 206448 kb
Host smart-0c482f6c-2be6-41e9-a4dc-2d98b84e42ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
85842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3995585842
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2444070415
Short name T1284
Test name
Test status
Simulation time 161550453 ps
CPU time 0.83 seconds
Started Jul 17 07:54:25 PM PDT 24
Finished Jul 17 07:54:27 PM PDT 24
Peak memory 206412 kb
Host smart-dc70b84f-3413-409f-8555-9c534eb2da41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24440
70415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2444070415
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1433724260
Short name T1723
Test name
Test status
Simulation time 248247488 ps
CPU time 0.96 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:54:34 PM PDT 24
Peak memory 206448 kb
Host smart-11b8a0ea-c7d1-4f5f-ad37-380fbbb07307
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1433724260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1433724260
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2689728447
Short name T402
Test name
Test status
Simulation time 164667243 ps
CPU time 0.79 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:33 PM PDT 24
Peak memory 206464 kb
Host smart-c6473f23-a40a-4973-a77f-d28c645885f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26897
28447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2689728447
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.370007277
Short name T1205
Test name
Test status
Simulation time 71305426 ps
CPU time 0.66 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:33 PM PDT 24
Peak memory 206452 kb
Host smart-e7f0de76-54fc-4737-a652-b8c5c7610bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37000
7277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.370007277
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1142062377
Short name T1237
Test name
Test status
Simulation time 22106842516 ps
CPU time 48.91 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:55:22 PM PDT 24
Peak memory 206700 kb
Host smart-9a7e8c36-6428-48a0-825c-8bf873c98836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11420
62377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1142062377
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2249472775
Short name T1635
Test name
Test status
Simulation time 166464673 ps
CPU time 0.81 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:54:34 PM PDT 24
Peak memory 206452 kb
Host smart-4018aa2f-37ec-42db-954a-2571cc9e79e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22494
72775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2249472775
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3668922797
Short name T1362
Test name
Test status
Simulation time 242217819 ps
CPU time 0.96 seconds
Started Jul 17 07:54:26 PM PDT 24
Finished Jul 17 07:54:28 PM PDT 24
Peak memory 206404 kb
Host smart-bd3a48d4-10fc-47d6-b7c3-d5f2faa0e02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36689
22797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3668922797
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3015483142
Short name T1598
Test name
Test status
Simulation time 8650746825 ps
CPU time 50.4 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:55:22 PM PDT 24
Peak memory 206700 kb
Host smart-db182c7b-2227-4a4f-9685-44479c19f51c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3015483142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3015483142
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.735625322
Short name T167
Test name
Test status
Simulation time 10244745964 ps
CPU time 90.18 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:56:02 PM PDT 24
Peak memory 206668 kb
Host smart-d9fd6a9f-3e70-49c3-b469-15db61e83886
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=735625322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.735625322
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.211845978
Short name T2039
Test name
Test status
Simulation time 10492660242 ps
CPU time 186.96 seconds
Started Jul 17 07:54:30 PM PDT 24
Finished Jul 17 07:57:41 PM PDT 24
Peak memory 206692 kb
Host smart-b17b3281-d2f3-4890-b1a8-b6d768e8121b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=211845978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.211845978
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.129460203
Short name T2708
Test name
Test status
Simulation time 218413267 ps
CPU time 0.89 seconds
Started Jul 17 07:54:30 PM PDT 24
Finished Jul 17 07:54:35 PM PDT 24
Peak memory 206448 kb
Host smart-75425816-8835-4f90-8d76-e8f8376aa524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12946
0203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.129460203
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2748425075
Short name T467
Test name
Test status
Simulation time 194967266 ps
CPU time 0.81 seconds
Started Jul 17 07:54:27 PM PDT 24
Finished Jul 17 07:54:31 PM PDT 24
Peak memory 206452 kb
Host smart-3bd5c5f3-ad53-4617-816a-126d441f2ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27484
25075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2748425075
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1301592915
Short name T439
Test name
Test status
Simulation time 183386116 ps
CPU time 0.82 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:33 PM PDT 24
Peak memory 206436 kb
Host smart-537fbe16-55c4-438f-bc21-625dfaeaa98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13015
92915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1301592915
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.366411507
Short name T1515
Test name
Test status
Simulation time 156387591 ps
CPU time 0.76 seconds
Started Jul 17 07:54:27 PM PDT 24
Finished Jul 17 07:54:30 PM PDT 24
Peak memory 206444 kb
Host smart-6a98d72e-114e-4686-a07b-ba4075049031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36641
1507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.366411507
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.392822671
Short name T672
Test name
Test status
Simulation time 167238775 ps
CPU time 0.8 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:33 PM PDT 24
Peak memory 206448 kb
Host smart-ae9c339a-2f47-46cc-9764-f5951d7b9fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282
2671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.392822671
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.952354160
Short name T990
Test name
Test status
Simulation time 209088980 ps
CPU time 0.87 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:54:34 PM PDT 24
Peak memory 206408 kb
Host smart-53830d60-0411-459e-93c3-c869fcc9cee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95235
4160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.952354160
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.4161080201
Short name T1052
Test name
Test status
Simulation time 4423467382 ps
CPU time 122 seconds
Started Jul 17 07:54:31 PM PDT 24
Finished Jul 17 07:56:37 PM PDT 24
Peak memory 206664 kb
Host smart-35cc5769-d544-4ff7-ace0-e241aa6d5e17
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4161080201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.4161080201
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.253447561
Short name T905
Test name
Test status
Simulation time 190818241 ps
CPU time 0.8 seconds
Started Jul 17 07:54:31 PM PDT 24
Finished Jul 17 07:54:36 PM PDT 24
Peak memory 206448 kb
Host smart-c8c1b59e-1d39-4b96-8891-1f4a5c13abfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
7561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.253447561
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1820165636
Short name T1846
Test name
Test status
Simulation time 173564624 ps
CPU time 0.8 seconds
Started Jul 17 07:54:36 PM PDT 24
Finished Jul 17 07:54:38 PM PDT 24
Peak memory 206448 kb
Host smart-1f8a796d-e3fe-4c0c-9c2d-66b483b64a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18201
65636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1820165636
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1145193138
Short name T489
Test name
Test status
Simulation time 650258382 ps
CPU time 1.58 seconds
Started Jul 17 07:54:31 PM PDT 24
Finished Jul 17 07:54:36 PM PDT 24
Peak memory 206448 kb
Host smart-63291987-d81c-46fd-b279-b9f37f82337a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11451
93138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1145193138
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3538005117
Short name T579
Test name
Test status
Simulation time 4859620645 ps
CPU time 32.73 seconds
Started Jul 17 07:54:30 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206720 kb
Host smart-c19f79d3-ae7e-4baa-b7bf-48a95460828c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35380
05117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3538005117
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2717475582
Short name T1514
Test name
Test status
Simulation time 50617013 ps
CPU time 0.68 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:11 PM PDT 24
Peak memory 206428 kb
Host smart-4c320a9b-c2ed-4825-acd8-5e7efa6d258e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2717475582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2717475582
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.181842887
Short name T2113
Test name
Test status
Simulation time 3715428484 ps
CPU time 4.54 seconds
Started Jul 17 07:54:31 PM PDT 24
Finished Jul 17 07:54:40 PM PDT 24
Peak memory 206660 kb
Host smart-129310e8-da09-4ab0-8493-9e32833751bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=181842887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.181842887
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.835582746
Short name T2562
Test name
Test status
Simulation time 13394242560 ps
CPU time 12.6 seconds
Started Jul 17 07:54:38 PM PDT 24
Finished Jul 17 07:54:53 PM PDT 24
Peak memory 206528 kb
Host smart-00bc6ba2-a439-40b6-b58a-6282a2bdde76
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=835582746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.835582746
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3364494741
Short name T2415
Test name
Test status
Simulation time 23373826920 ps
CPU time 23.17 seconds
Started Jul 17 07:54:36 PM PDT 24
Finished Jul 17 07:55:01 PM PDT 24
Peak memory 205780 kb
Host smart-7dc82a10-2270-4147-b852-48508b2af6b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3364494741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.3364494741
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3298474886
Short name T970
Test name
Test status
Simulation time 154629364 ps
CPU time 0.81 seconds
Started Jul 17 07:54:39 PM PDT 24
Finished Jul 17 07:54:41 PM PDT 24
Peak memory 206456 kb
Host smart-08386b2e-e1d4-40d9-aead-e0cc78d0e1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32984
74886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3298474886
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3935553789
Short name T1874
Test name
Test status
Simulation time 181629922 ps
CPU time 0.82 seconds
Started Jul 17 07:54:34 PM PDT 24
Finished Jul 17 07:54:37 PM PDT 24
Peak memory 206460 kb
Host smart-accf430e-96cb-43b1-b42c-455bcd5c6abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39355
53789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3935553789
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3631933488
Short name T1543
Test name
Test status
Simulation time 332794067 ps
CPU time 1.13 seconds
Started Jul 17 07:54:36 PM PDT 24
Finished Jul 17 07:54:39 PM PDT 24
Peak memory 206460 kb
Host smart-a6a8e789-312d-4d19-b0b3-866ce8f8bea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36319
33488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3631933488
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3054234431
Short name T1072
Test name
Test status
Simulation time 1382280066 ps
CPU time 2.96 seconds
Started Jul 17 07:54:36 PM PDT 24
Finished Jul 17 07:54:40 PM PDT 24
Peak memory 206040 kb
Host smart-f0dc52c0-e4ca-4333-8769-9a4fbfefd419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30542
34431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3054234431
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2431107348
Short name T2162
Test name
Test status
Simulation time 10447912316 ps
CPU time 21.13 seconds
Started Jul 17 07:54:38 PM PDT 24
Finished Jul 17 07:55:00 PM PDT 24
Peak memory 206708 kb
Host smart-57957ec8-181a-4bff-ae98-68403338d9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24311
07348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2431107348
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.1355660369
Short name T150
Test name
Test status
Simulation time 372799773 ps
CPU time 1.26 seconds
Started Jul 17 07:54:38 PM PDT 24
Finished Jul 17 07:54:41 PM PDT 24
Peak memory 206460 kb
Host smart-a3e3838c-87a6-4738-9ffd-f7db0c79a5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13556
60369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.1355660369
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1348553531
Short name T2465
Test name
Test status
Simulation time 159766520 ps
CPU time 0.8 seconds
Started Jul 17 07:54:35 PM PDT 24
Finished Jul 17 07:54:38 PM PDT 24
Peak memory 206452 kb
Host smart-fc4b898f-de23-42aa-89d2-097dd3b8d88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13485
53531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1348553531
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.627813316
Short name T2273
Test name
Test status
Simulation time 40936218 ps
CPU time 0.67 seconds
Started Jul 17 07:54:37 PM PDT 24
Finished Jul 17 07:54:39 PM PDT 24
Peak memory 206452 kb
Host smart-fe580f24-fe72-4689-91c1-8f7ec79a0038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62781
3316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.627813316
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1141559276
Short name T1169
Test name
Test status
Simulation time 893782548 ps
CPU time 2.04 seconds
Started Jul 17 07:54:35 PM PDT 24
Finished Jul 17 07:54:39 PM PDT 24
Peak memory 206672 kb
Host smart-2c509550-b2b4-4846-8d95-f516b3ea85a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11415
59276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1141559276
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1899997494
Short name T1458
Test name
Test status
Simulation time 288245970 ps
CPU time 2.19 seconds
Started Jul 17 07:54:34 PM PDT 24
Finished Jul 17 07:54:39 PM PDT 24
Peak memory 206612 kb
Host smart-3df63fee-4077-437e-b516-90c5d8e7c985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18999
97494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1899997494
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2197859582
Short name T786
Test name
Test status
Simulation time 189311102 ps
CPU time 0.82 seconds
Started Jul 17 07:54:35 PM PDT 24
Finished Jul 17 07:54:38 PM PDT 24
Peak memory 206452 kb
Host smart-25c17408-4db8-4d24-8f39-9bd8261ab49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978
59582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2197859582
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3848510881
Short name T1038
Test name
Test status
Simulation time 141782828 ps
CPU time 0.77 seconds
Started Jul 17 07:54:35 PM PDT 24
Finished Jul 17 07:54:38 PM PDT 24
Peak memory 206452 kb
Host smart-35c03106-6e47-4e60-a299-33aa1bdb0cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38485
10881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3848510881
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1883851451
Short name T1667
Test name
Test status
Simulation time 187224331 ps
CPU time 0.89 seconds
Started Jul 17 07:54:33 PM PDT 24
Finished Jul 17 07:54:37 PM PDT 24
Peak memory 206440 kb
Host smart-bd68dad4-1b5b-4c85-87e9-bdf63fcd85ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18838
51451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1883851451
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.86630482
Short name T2257
Test name
Test status
Simulation time 14030730833 ps
CPU time 43.25 seconds
Started Jul 17 07:54:32 PM PDT 24
Finished Jul 17 07:55:19 PM PDT 24
Peak memory 206704 kb
Host smart-40ac502d-27b8-4eb7-a997-69e92e4b7c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86630
482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.86630482
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2199277177
Short name T1544
Test name
Test status
Simulation time 207522179 ps
CPU time 0.83 seconds
Started Jul 17 07:54:34 PM PDT 24
Finished Jul 17 07:54:37 PM PDT 24
Peak memory 206428 kb
Host smart-9402d0e6-b67b-4d1b-83f4-f4dd7a9c5b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21992
77177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2199277177
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1918955056
Short name T2132
Test name
Test status
Simulation time 23292256376 ps
CPU time 25.08 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:54:58 PM PDT 24
Peak memory 206488 kb
Host smart-dbd4d683-ecc8-4142-8c37-55b260ebc554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19189
55056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1918955056
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2523312492
Short name T2152
Test name
Test status
Simulation time 3298318337 ps
CPU time 3.69 seconds
Started Jul 17 07:54:32 PM PDT 24
Finished Jul 17 07:54:39 PM PDT 24
Peak memory 206504 kb
Host smart-8e884be3-e9a9-48fc-99aa-c1b3e46afdee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25233
12492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2523312492
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.694611970
Short name T1603
Test name
Test status
Simulation time 8694523167 ps
CPU time 76.99 seconds
Started Jul 17 07:54:33 PM PDT 24
Finished Jul 17 07:55:53 PM PDT 24
Peak memory 206720 kb
Host smart-4c297c51-db6e-4dba-8765-405c95168768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69461
1970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.694611970
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2131783010
Short name T412
Test name
Test status
Simulation time 4465684916 ps
CPU time 30.22 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:55:01 PM PDT 24
Peak memory 206664 kb
Host smart-330f0f56-cdce-43eb-8c1b-0f861a631198
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2131783010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2131783010
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.1582275689
Short name T2460
Test name
Test status
Simulation time 236692958 ps
CPU time 0.91 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:32 PM PDT 24
Peak memory 206452 kb
Host smart-7d086e67-ed90-41ab-a7e3-03f3bc918293
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1582275689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.1582275689
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.4124285061
Short name T845
Test name
Test status
Simulation time 185187934 ps
CPU time 0.82 seconds
Started Jul 17 07:54:30 PM PDT 24
Finished Jul 17 07:54:35 PM PDT 24
Peak memory 206460 kb
Host smart-fb1afe96-39bb-4eff-bddb-203cd07e8104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41242
85061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.4124285061
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2555468258
Short name T2463
Test name
Test status
Simulation time 4018370304 ps
CPU time 108.89 seconds
Started Jul 17 07:54:29 PM PDT 24
Finished Jul 17 07:56:22 PM PDT 24
Peak memory 206668 kb
Host smart-04014ce9-a9a8-4943-ac07-4e96fd68d9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25554
68258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2555468258
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3155637543
Short name T1756
Test name
Test status
Simulation time 4464099649 ps
CPU time 119.37 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:56:31 PM PDT 24
Peak memory 206664 kb
Host smart-dfdb7d45-772f-403b-ada1-dd937ae48eda
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3155637543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3155637543
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2904098179
Short name T1614
Test name
Test status
Simulation time 158043029 ps
CPU time 0.8 seconds
Started Jul 17 07:54:27 PM PDT 24
Finished Jul 17 07:54:31 PM PDT 24
Peak memory 206456 kb
Host smart-49739dd7-b846-454c-86de-39f57dc88f19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2904098179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2904098179
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4281081131
Short name T1384
Test name
Test status
Simulation time 177854806 ps
CPU time 0.75 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:32 PM PDT 24
Peak memory 206456 kb
Host smart-29b439d7-adde-4fb8-bf97-3e1cb31e75fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42810
81131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4281081131
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1827492704
Short name T113
Test name
Test status
Simulation time 192777371 ps
CPU time 0.82 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:32 PM PDT 24
Peak memory 206448 kb
Host smart-89b5e0cb-28f9-4afa-9d1c-5d9280334589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18274
92704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1827492704
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.733219701
Short name T1014
Test name
Test status
Simulation time 212503150 ps
CPU time 0.86 seconds
Started Jul 17 07:54:28 PM PDT 24
Finished Jul 17 07:54:32 PM PDT 24
Peak memory 206448 kb
Host smart-b33339bb-5f1e-4c4d-ac5b-9ceab4537ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73321
9701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.733219701
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.358463514
Short name T1432
Test name
Test status
Simulation time 149745675 ps
CPU time 0.81 seconds
Started Jul 17 07:55:09 PM PDT 24
Finished Jul 17 07:55:15 PM PDT 24
Peak memory 206452 kb
Host smart-9603aa2f-4322-45f4-80ed-310426ecccdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35846
3514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.358463514
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3846735067
Short name T2150
Test name
Test status
Simulation time 150624126 ps
CPU time 0.74 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:11 PM PDT 24
Peak memory 206456 kb
Host smart-836a29d6-27a6-4d30-8f7b-59767dc67836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38467
35067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3846735067
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.343906729
Short name T1179
Test name
Test status
Simulation time 160890652 ps
CPU time 0.81 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:08 PM PDT 24
Peak memory 206464 kb
Host smart-6dd1480c-4999-4f95-8f7e-8e4f5d1590ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
6729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.343906729
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.561221802
Short name T1528
Test name
Test status
Simulation time 251690072 ps
CPU time 0.92 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:08 PM PDT 24
Peak memory 206480 kb
Host smart-b643d5ba-766d-4576-ba1a-7d5bbe962ae4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=561221802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.561221802
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2000693349
Short name T2663
Test name
Test status
Simulation time 164175037 ps
CPU time 0.79 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206460 kb
Host smart-3cdb8778-3c6c-4941-8040-80ab4c483269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20006
93349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2000693349
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.994306860
Short name T2607
Test name
Test status
Simulation time 44726157 ps
CPU time 0.67 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:06 PM PDT 24
Peak memory 206432 kb
Host smart-ad6be5eb-2495-46ef-b2e7-59353864745c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99430
6860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.994306860
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.4285951383
Short name T1134
Test name
Test status
Simulation time 8279060763 ps
CPU time 19.43 seconds
Started Jul 17 07:55:01 PM PDT 24
Finished Jul 17 07:55:22 PM PDT 24
Peak memory 206672 kb
Host smart-360cf6f4-1fa7-41f1-b37a-1a46b9f06be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42859
51383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.4285951383
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.4136725676
Short name T902
Test name
Test status
Simulation time 228298211 ps
CPU time 0.87 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206464 kb
Host smart-3e03b74f-9544-4851-a170-8df76d8a1782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41367
25676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.4136725676
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2074398960
Short name T712
Test name
Test status
Simulation time 223854725 ps
CPU time 0.91 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:08 PM PDT 24
Peak memory 206460 kb
Host smart-98418ce2-287a-467c-ab5f-ee703dd03c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20743
98960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2074398960
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1398721464
Short name T2535
Test name
Test status
Simulation time 8497114300 ps
CPU time 148.61 seconds
Started Jul 17 07:55:00 PM PDT 24
Finished Jul 17 07:57:29 PM PDT 24
Peak memory 206716 kb
Host smart-a5bf166b-6708-4bf7-b58c-14ec879f629a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1398721464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1398721464
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1605568288
Short name T169
Test name
Test status
Simulation time 9499190788 ps
CPU time 67 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:56:12 PM PDT 24
Peak memory 206764 kb
Host smart-50f5376d-7f77-481d-98a3-4a0258f91ea9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1605568288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1605568288
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2432910905
Short name T1786
Test name
Test status
Simulation time 13390598409 ps
CPU time 92.58 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:56:43 PM PDT 24
Peak memory 206696 kb
Host smart-345246d9-74e3-4d6b-982c-02d6ebe9baba
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2432910905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2432910905
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3694604324
Short name T2681
Test name
Test status
Simulation time 244975908 ps
CPU time 0.97 seconds
Started Jul 17 07:55:06 PM PDT 24
Finished Jul 17 07:55:13 PM PDT 24
Peak memory 206416 kb
Host smart-cdb3b53f-7941-45b7-aa07-fa33485369c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36946
04324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3694604324
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1292629789
Short name T480
Test name
Test status
Simulation time 184530781 ps
CPU time 0.86 seconds
Started Jul 17 07:55:01 PM PDT 24
Finished Jul 17 07:55:05 PM PDT 24
Peak memory 206456 kb
Host smart-26dfd5ba-f637-4b39-a059-8626b5fc3aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12926
29789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1292629789
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.682187456
Short name T2339
Test name
Test status
Simulation time 236027338 ps
CPU time 0.87 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:10 PM PDT 24
Peak memory 206448 kb
Host smart-3dc3da49-8d8d-4a68-9866-e70907c023d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68218
7456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.682187456
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2076103343
Short name T2197
Test name
Test status
Simulation time 206888314 ps
CPU time 0.81 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206456 kb
Host smart-5567def0-4654-4dc5-a018-9def505c582d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20761
03343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2076103343
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3840734735
Short name T1232
Test name
Test status
Simulation time 199075838 ps
CPU time 0.82 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206460 kb
Host smart-09e7699b-6c11-4330-8a8e-8979f9aa369f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38407
34735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3840734735
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1642745194
Short name T1011
Test name
Test status
Simulation time 304125499 ps
CPU time 1.03 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206448 kb
Host smart-4c86a69f-a325-4553-97e0-c417ddbbc48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16427
45194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1642745194
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.501957866
Short name T2632
Test name
Test status
Simulation time 6431941386 ps
CPU time 175.53 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:58:05 PM PDT 24
Peak memory 206668 kb
Host smart-085eb90e-8c67-4a55-898f-84fcc859a303
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=501957866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.501957866
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.546115665
Short name T1273
Test name
Test status
Simulation time 183294799 ps
CPU time 0.84 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206460 kb
Host smart-72379056-f9aa-493d-b3cd-5388f9d26b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54611
5665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.546115665
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1684719581
Short name T987
Test name
Test status
Simulation time 209729211 ps
CPU time 0.83 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:08 PM PDT 24
Peak memory 206404 kb
Host smart-209acf25-1f47-470a-ade6-9dbab68f9cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
19581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1684719581
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.598246778
Short name T1431
Test name
Test status
Simulation time 1094755635 ps
CPU time 2.24 seconds
Started Jul 17 07:54:59 PM PDT 24
Finished Jul 17 07:55:02 PM PDT 24
Peak memory 206656 kb
Host smart-4a806341-dd8e-434c-ae91-2869e41831e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59824
6778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.598246778
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.832835213
Short name T1748
Test name
Test status
Simulation time 4952385424 ps
CPU time 48.17 seconds
Started Jul 17 07:55:00 PM PDT 24
Finished Jul 17 07:55:50 PM PDT 24
Peak memory 206724 kb
Host smart-f6bef14d-a21b-454c-b63e-e8b844849387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83283
5213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.832835213
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2018136014
Short name T2426
Test name
Test status
Simulation time 52836824 ps
CPU time 0.69 seconds
Started Jul 17 07:55:06 PM PDT 24
Finished Jul 17 07:55:13 PM PDT 24
Peak memory 206396 kb
Host smart-f8e3a599-89ae-4584-bde7-3f099fd28d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2018136014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2018136014
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3635356419
Short name T1243
Test name
Test status
Simulation time 4316778256 ps
CPU time 4.81 seconds
Started Jul 17 07:55:01 PM PDT 24
Finished Jul 17 07:55:08 PM PDT 24
Peak memory 206672 kb
Host smart-cf7993db-03d8-46b6-8dc6-13c9877d2471
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3635356419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3635356419
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2708790706
Short name T1058
Test name
Test status
Simulation time 13430150120 ps
CPU time 15.44 seconds
Started Jul 17 07:55:01 PM PDT 24
Finished Jul 17 07:55:19 PM PDT 24
Peak memory 206532 kb
Host smart-039b7f71-b680-4b99-b204-55332581d596
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2708790706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2708790706
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2535361842
Short name T677
Test name
Test status
Simulation time 23402256583 ps
CPU time 24.74 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:32 PM PDT 24
Peak memory 206672 kb
Host smart-1a313219-e99b-4233-822a-1a8d4fad9cf7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2535361842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2535361842
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.592959754
Short name T2628
Test name
Test status
Simulation time 216112619 ps
CPU time 0.89 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:08 PM PDT 24
Peak memory 206428 kb
Host smart-360228fb-2d05-456c-bf62-8fc7b5d57c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59295
9754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.592959754
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2443751100
Short name T1973
Test name
Test status
Simulation time 148702095 ps
CPU time 0.74 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:10 PM PDT 24
Peak memory 206460 kb
Host smart-e84dd28a-859f-4b68-aaa5-a6a75a185a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437
51100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2443751100
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2552036414
Short name T107
Test name
Test status
Simulation time 383692946 ps
CPU time 1.34 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206464 kb
Host smart-c8baafc7-aabe-4caf-9c16-af5bafa56a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
36414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2552036414
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3955026950
Short name T1692
Test name
Test status
Simulation time 1266082105 ps
CPU time 2.64 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206636 kb
Host smart-2da8467b-4e99-429c-97b7-080c89a9e4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
26950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3955026950
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2031213961
Short name T2485
Test name
Test status
Simulation time 13996901590 ps
CPU time 27.13 seconds
Started Jul 17 07:55:07 PM PDT 24
Finished Jul 17 07:55:39 PM PDT 24
Peak memory 206708 kb
Host smart-f9df216b-029b-4303-a3c1-41cd69c61d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20312
13961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2031213961
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.820410081
Short name T2271
Test name
Test status
Simulation time 365643811 ps
CPU time 1.16 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:11 PM PDT 24
Peak memory 206456 kb
Host smart-94824987-9466-44c2-9c1b-d38ce6c8634e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82041
0081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.820410081
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.521149290
Short name T1864
Test name
Test status
Simulation time 149490815 ps
CPU time 0.78 seconds
Started Jul 17 07:55:08 PM PDT 24
Finished Jul 17 07:55:14 PM PDT 24
Peak memory 206448 kb
Host smart-e2104aab-7e9d-4d8c-a904-fd42f5ce2dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52114
9290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.521149290
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2150201532
Short name T1558
Test name
Test status
Simulation time 36544041 ps
CPU time 0.65 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206460 kb
Host smart-2310f21a-4eaa-4ef7-b109-18f392c821b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21502
01532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2150201532
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1563354588
Short name T1731
Test name
Test status
Simulation time 878958359 ps
CPU time 2.16 seconds
Started Jul 17 07:55:00 PM PDT 24
Finished Jul 17 07:55:04 PM PDT 24
Peak memory 206604 kb
Host smart-e0d43cca-805f-4658-9dbb-6b66e861bcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15633
54588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1563354588
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1807297445
Short name T430
Test name
Test status
Simulation time 316239542 ps
CPU time 2.52 seconds
Started Jul 17 07:55:06 PM PDT 24
Finished Jul 17 07:55:14 PM PDT 24
Peak memory 206596 kb
Host smart-08721e4a-ed7e-4ebf-9cdb-8447163aab2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18072
97445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1807297445
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.395257434
Short name T2674
Test name
Test status
Simulation time 232820418 ps
CPU time 0.89 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206392 kb
Host smart-6718ab99-bc76-4ab5-b220-86133c84a0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
7434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.395257434
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2814096620
Short name T1500
Test name
Test status
Simulation time 144301577 ps
CPU time 0.8 seconds
Started Jul 17 07:55:08 PM PDT 24
Finished Jul 17 07:55:14 PM PDT 24
Peak memory 206452 kb
Host smart-d4bc7857-4729-4d84-b6ca-4dca0727be2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
96620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2814096620
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1556085193
Short name T466
Test name
Test status
Simulation time 262939003 ps
CPU time 0.98 seconds
Started Jul 17 07:55:01 PM PDT 24
Finished Jul 17 07:55:04 PM PDT 24
Peak memory 206452 kb
Host smart-4ee0ed93-f2d9-4d4e-84e1-b13b3c32b004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15560
85193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1556085193
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.2072872532
Short name T265
Test name
Test status
Simulation time 6488945190 ps
CPU time 61.99 seconds
Started Jul 17 07:55:01 PM PDT 24
Finished Jul 17 07:56:04 PM PDT 24
Peak memory 206716 kb
Host smart-66326009-008c-4072-8854-cb21b2f44ebd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2072872532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.2072872532
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.3166532676
Short name T2457
Test name
Test status
Simulation time 12439378982 ps
CPU time 97.64 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:56:47 PM PDT 24
Peak memory 206712 kb
Host smart-d40ef504-f287-4056-a1cb-588047877cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31665
32676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.3166532676
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.327203533
Short name T1460
Test name
Test status
Simulation time 168228989 ps
CPU time 0.87 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206400 kb
Host smart-29f623c4-14e7-444d-b5c5-b1c77e1a527f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32720
3533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.327203533
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.1436325334
Short name T501
Test name
Test status
Simulation time 23293243107 ps
CPU time 24.63 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:33 PM PDT 24
Peak memory 206508 kb
Host smart-046088ba-e377-4b7d-a8c6-b977e943c8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363
25334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.1436325334
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3501873347
Short name T2330
Test name
Test status
Simulation time 3299917555 ps
CPU time 4.07 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:14 PM PDT 24
Peak memory 206516 kb
Host smart-13abe30f-9885-457d-863b-11540a3d7934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35018
73347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3501873347
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.716454044
Short name T2165
Test name
Test status
Simulation time 11345018065 ps
CPU time 309.78 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 08:00:18 PM PDT 24
Peak memory 206920 kb
Host smart-e6298026-4e90-467b-a521-c8a71aa13f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71645
4044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.716454044
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4273523826
Short name T1794
Test name
Test status
Simulation time 4637812328 ps
CPU time 43.31 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:50 PM PDT 24
Peak memory 206732 kb
Host smart-c4df79f6-58ef-4cd1-b9ec-fcef9eaca059
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4273523826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4273523826
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.2750117114
Short name T2416
Test name
Test status
Simulation time 245068809 ps
CPU time 0.94 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:06 PM PDT 24
Peak memory 206452 kb
Host smart-f78a96b5-3f09-4b50-b134-6bbac2b62e21
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2750117114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.2750117114
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2217460498
Short name T355
Test name
Test status
Simulation time 224344097 ps
CPU time 0.91 seconds
Started Jul 17 07:55:01 PM PDT 24
Finished Jul 17 07:55:04 PM PDT 24
Peak memory 206456 kb
Host smart-814c74da-592f-4bd8-9e4b-179d8495e741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22174
60498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2217460498
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2464703848
Short name T1768
Test name
Test status
Simulation time 5115655298 ps
CPU time 141.29 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:57:32 PM PDT 24
Peak memory 206852 kb
Host smart-856fe891-720e-4be3-8f63-5a152980d170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24647
03848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2464703848
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.474866677
Short name T1363
Test name
Test status
Simulation time 5574476712 ps
CPU time 40.69 seconds
Started Jul 17 07:55:01 PM PDT 24
Finished Jul 17 07:55:45 PM PDT 24
Peak memory 206676 kb
Host smart-643ed43d-922a-4f86-b4db-c0d9778f72c9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=474866677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.474866677
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1775416712
Short name T425
Test name
Test status
Simulation time 157869439 ps
CPU time 0.76 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:10 PM PDT 24
Peak memory 206468 kb
Host smart-c37a63b5-1111-4f83-883b-9bbc068dbb87
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1775416712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1775416712
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.304832902
Short name T2013
Test name
Test status
Simulation time 144717912 ps
CPU time 0.76 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:10 PM PDT 24
Peak memory 206436 kb
Host smart-4ba77ee8-e887-4fcd-b1db-e50b33f6382e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30483
2902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.304832902
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.422809763
Short name T865
Test name
Test status
Simulation time 191776682 ps
CPU time 0.87 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:11 PM PDT 24
Peak memory 206464 kb
Host smart-df1c7cc6-9987-4193-8377-189448c3d3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42280
9763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.422809763
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.3634898389
Short name T392
Test name
Test status
Simulation time 186208649 ps
CPU time 0.87 seconds
Started Jul 17 07:55:08 PM PDT 24
Finished Jul 17 07:55:14 PM PDT 24
Peak memory 206452 kb
Host smart-e4df6886-4918-4e8d-8a2a-821bd212d764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36348
98389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3634898389
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.631445245
Short name T1319
Test name
Test status
Simulation time 195755945 ps
CPU time 0.79 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:11 PM PDT 24
Peak memory 206580 kb
Host smart-b9cb5e01-58c5-4cf1-8d13-2332d673fa01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63144
5245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.631445245
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3240913719
Short name T1195
Test name
Test status
Simulation time 155290512 ps
CPU time 0.82 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206408 kb
Host smart-b284a146-5b8d-478d-9d92-326f05af4d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32409
13719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3240913719
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1537569143
Short name T2217
Test name
Test status
Simulation time 170735691 ps
CPU time 0.83 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:07 PM PDT 24
Peak memory 206444 kb
Host smart-1817a02d-456f-40e6-b152-1eb9b03c9b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15375
69143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1537569143
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2693721352
Short name T2364
Test name
Test status
Simulation time 197167017 ps
CPU time 0.83 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:12 PM PDT 24
Peak memory 206464 kb
Host smart-981edccf-f2ec-46c9-82e4-ae6c6c062b6b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2693721352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2693721352
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.4103467786
Short name T749
Test name
Test status
Simulation time 147936731 ps
CPU time 0.75 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:08 PM PDT 24
Peak memory 206468 kb
Host smart-cd1a4978-b8de-4d4b-994f-ed12f021a291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41034
67786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.4103467786
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3389654201
Short name T1918
Test name
Test status
Simulation time 27309462 ps
CPU time 0.62 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:10 PM PDT 24
Peak memory 206452 kb
Host smart-47abf6cb-1d87-4a81-abbc-53beb67c6b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33896
54201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3389654201
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3805744329
Short name T1110
Test name
Test status
Simulation time 11463871158 ps
CPU time 23.83 seconds
Started Jul 17 07:55:03 PM PDT 24
Finished Jul 17 07:55:31 PM PDT 24
Peak memory 206644 kb
Host smart-ce21db58-6131-4fb9-a684-d8c572783d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38057
44329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3805744329
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.4143304720
Short name T2718
Test name
Test status
Simulation time 174811754 ps
CPU time 0.83 seconds
Started Jul 17 07:55:07 PM PDT 24
Finished Jul 17 07:55:13 PM PDT 24
Peak memory 206412 kb
Host smart-17b7c305-c3eb-4de6-9c6f-1a62c596e0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41433
04720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.4143304720
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1087570819
Short name T1636
Test name
Test status
Simulation time 173188256 ps
CPU time 0.82 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:12 PM PDT 24
Peak memory 206452 kb
Host smart-4c88c7da-e091-4a25-9bb0-063ee2dcb3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10875
70819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1087570819
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1453221344
Short name T1029
Test name
Test status
Simulation time 7836318477 ps
CPU time 205.78 seconds
Started Jul 17 07:55:06 PM PDT 24
Finished Jul 17 07:58:38 PM PDT 24
Peak memory 206472 kb
Host smart-451378bf-09a9-4d57-a71b-7b0289c01d53
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1453221344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1453221344
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.76106253
Short name T151
Test name
Test status
Simulation time 4646139032 ps
CPU time 100.91 seconds
Started Jul 17 07:55:06 PM PDT 24
Finished Jul 17 07:56:53 PM PDT 24
Peak memory 206760 kb
Host smart-e196a1ab-939f-48cb-aced-9a13217ed277
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=76106253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.76106253
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2653990059
Short name T877
Test name
Test status
Simulation time 28767082129 ps
CPU time 224.21 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:58:54 PM PDT 24
Peak memory 206760 kb
Host smart-eb72d6e6-078a-4f84-9694-13993e4629da
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2653990059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2653990059
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.283836260
Short name T2201
Test name
Test status
Simulation time 187209231 ps
CPU time 0.87 seconds
Started Jul 17 07:55:07 PM PDT 24
Finished Jul 17 07:55:13 PM PDT 24
Peak memory 206460 kb
Host smart-77f08773-4661-4ddf-a8f2-ac7be26aaa64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28383
6260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.283836260
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.4166657674
Short name T504
Test name
Test status
Simulation time 166224646 ps
CPU time 0.81 seconds
Started Jul 17 07:55:06 PM PDT 24
Finished Jul 17 07:55:13 PM PDT 24
Peak memory 206160 kb
Host smart-cdb00721-4a58-46e2-bb8d-529797a43654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41666
57674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.4166657674
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2723953126
Short name T803
Test name
Test status
Simulation time 194912713 ps
CPU time 0.85 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:06 PM PDT 24
Peak memory 206480 kb
Host smart-1d7d4153-ddbf-4f0e-b15a-3b340816395a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27239
53126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2723953126
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3896870655
Short name T1575
Test name
Test status
Simulation time 149966518 ps
CPU time 0.81 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206404 kb
Host smart-37d5e975-017c-4951-a637-d956a2a1fe35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968
70655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3896870655
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3762769434
Short name T2497
Test name
Test status
Simulation time 198945611 ps
CPU time 0.9 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206448 kb
Host smart-e07ceedb-24cb-444d-8094-6c321bb9ad4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37627
69434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3762769434
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1709599003
Short name T142
Test name
Test status
Simulation time 226482679 ps
CPU time 0.93 seconds
Started Jul 17 07:55:07 PM PDT 24
Finished Jul 17 07:55:13 PM PDT 24
Peak memory 206456 kb
Host smart-587195a3-35a9-40fc-9200-e35f64516054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095
99003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1709599003
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.4031125184
Short name T1459
Test name
Test status
Simulation time 2924387845 ps
CPU time 80.41 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 206668 kb
Host smart-84f83ca4-d0dd-488a-ac30-820951aa1f32
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4031125184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.4031125184
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2045911884
Short name T1969
Test name
Test status
Simulation time 217925285 ps
CPU time 0.84 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:11 PM PDT 24
Peak memory 206460 kb
Host smart-3e6e030a-1fb6-4473-b989-913748db2fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20459
11884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2045911884
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1070557617
Short name T847
Test name
Test status
Simulation time 167820220 ps
CPU time 0.78 seconds
Started Jul 17 07:55:05 PM PDT 24
Finished Jul 17 07:55:11 PM PDT 24
Peak memory 206440 kb
Host smart-8647e5c6-b0c3-4efa-b127-cb2120421f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
57617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1070557617
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.1631749605
Short name T2405
Test name
Test status
Simulation time 832330214 ps
CPU time 1.94 seconds
Started Jul 17 07:55:02 PM PDT 24
Finished Jul 17 07:55:09 PM PDT 24
Peak memory 206636 kb
Host smart-3157039e-c80a-4930-8bbb-79e762af2079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
49605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1631749605
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3791406354
Short name T512
Test name
Test status
Simulation time 3795743598 ps
CPU time 28.68 seconds
Started Jul 17 07:55:07 PM PDT 24
Finished Jul 17 07:55:40 PM PDT 24
Peak memory 206608 kb
Host smart-adf9c298-9cd3-4240-8119-3c2458f2720f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
06354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3791406354
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1075780329
Short name T1585
Test name
Test status
Simulation time 47967381 ps
CPU time 0.71 seconds
Started Jul 17 07:55:46 PM PDT 24
Finished Jul 17 07:55:53 PM PDT 24
Peak memory 206404 kb
Host smart-45f0c327-1979-4238-90ac-843dd86000d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1075780329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1075780329
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2910864603
Short name T1632
Test name
Test status
Simulation time 4407066925 ps
CPU time 5.43 seconds
Started Jul 17 07:55:06 PM PDT 24
Finished Jul 17 07:55:16 PM PDT 24
Peak memory 206500 kb
Host smart-f101f977-42bb-4e0f-b54a-41edccb2621e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2910864603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2910864603
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.426871572
Short name T1545
Test name
Test status
Simulation time 13382464981 ps
CPU time 12.76 seconds
Started Jul 17 07:55:04 PM PDT 24
Finished Jul 17 07:55:22 PM PDT 24
Peak memory 206504 kb
Host smart-75b361a0-9249-49db-99bf-ce887703311f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=426871572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.426871572
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3170248818
Short name T1678
Test name
Test status
Simulation time 23318048592 ps
CPU time 23.18 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 206516 kb
Host smart-fef56e1f-55fb-4357-8947-c63476ee19a3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3170248818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.3170248818
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.857565739
Short name T997
Test name
Test status
Simulation time 157391018 ps
CPU time 0.82 seconds
Started Jul 17 07:55:41 PM PDT 24
Finished Jul 17 07:55:44 PM PDT 24
Peak memory 206452 kb
Host smart-b25f7a9f-4744-4ff3-9ee5-a126dde540fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85756
5739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.857565739
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.716886779
Short name T1795
Test name
Test status
Simulation time 179029132 ps
CPU time 0.88 seconds
Started Jul 17 07:55:36 PM PDT 24
Finished Jul 17 07:55:39 PM PDT 24
Peak memory 206416 kb
Host smart-7f18bde2-c940-41bc-83cc-68986d758ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71688
6779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.716886779
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.955957556
Short name T1587
Test name
Test status
Simulation time 450119823 ps
CPU time 1.46 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:55:38 PM PDT 24
Peak memory 206460 kb
Host smart-3e0b4c8a-24d7-46b1-b8ff-509034361646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95595
7556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.955957556
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1864911116
Short name T1854
Test name
Test status
Simulation time 666597930 ps
CPU time 1.98 seconds
Started Jul 17 07:55:36 PM PDT 24
Finished Jul 17 07:55:40 PM PDT 24
Peak memory 206568 kb
Host smart-69a7ab32-73c7-4675-82fd-7a6038ecb5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
11116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1864911116
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.429710056
Short name T90
Test name
Test status
Simulation time 12351483724 ps
CPU time 23.31 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:56:19 PM PDT 24
Peak memory 206724 kb
Host smart-ef39304d-1af8-4b17-bb1b-86053ed0a3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42971
0056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.429710056
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3184658204
Short name T2246
Test name
Test status
Simulation time 445009294 ps
CPU time 1.3 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:55:39 PM PDT 24
Peak memory 206460 kb
Host smart-5cb4de8c-9c8a-4f4b-b8b7-8bffb09fe4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31846
58204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3184658204
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.552870594
Short name T2726
Test name
Test status
Simulation time 151321962 ps
CPU time 0.81 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:55:57 PM PDT 24
Peak memory 206448 kb
Host smart-02fc5c48-ec92-4ff0-9caf-99e9f06d33d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55287
0594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.552870594
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.436393330
Short name T2750
Test name
Test status
Simulation time 63032766 ps
CPU time 0.69 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:55:50 PM PDT 24
Peak memory 206448 kb
Host smart-20dc4691-5623-4146-88b9-1fd48330a420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43639
3330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.436393330
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2177248515
Short name T1740
Test name
Test status
Simulation time 925948546 ps
CPU time 2.28 seconds
Started Jul 17 07:55:47 PM PDT 24
Finished Jul 17 07:55:56 PM PDT 24
Peak memory 206676 kb
Host smart-4e3e0bfb-74ee-441a-8922-4f7479fe8c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21772
48515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2177248515
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1057312923
Short name T1638
Test name
Test status
Simulation time 403029699 ps
CPU time 2.5 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:55:39 PM PDT 24
Peak memory 206600 kb
Host smart-f077f61e-cb9a-4b54-b3f1-19657683db29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10573
12923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1057312923
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3327736463
Short name T807
Test name
Test status
Simulation time 292441074 ps
CPU time 1.06 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:55:38 PM PDT 24
Peak memory 206460 kb
Host smart-c633afd5-4270-48f1-ac59-bf12c019f9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
36463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3327736463
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3036160569
Short name T2249
Test name
Test status
Simulation time 143875947 ps
CPU time 0.72 seconds
Started Jul 17 07:55:34 PM PDT 24
Finished Jul 17 07:55:36 PM PDT 24
Peak memory 206408 kb
Host smart-daecaa76-58fe-4a66-b2c6-a4ad80653e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30361
60569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3036160569
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.4158638422
Short name T2444
Test name
Test status
Simulation time 237929996 ps
CPU time 0.97 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206448 kb
Host smart-8e2177ea-5d97-4b59-bef1-670d0c56b192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41586
38422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.4158638422
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3885071005
Short name T96
Test name
Test status
Simulation time 9863632316 ps
CPU time 271.69 seconds
Started Jul 17 07:55:46 PM PDT 24
Finished Jul 17 08:00:25 PM PDT 24
Peak memory 206668 kb
Host smart-a1022341-8a83-466f-b20f-6f67b96acd43
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3885071005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3885071005
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.49158971
Short name T1661
Test name
Test status
Simulation time 4151573497 ps
CPU time 17.11 seconds
Started Jul 17 07:55:42 PM PDT 24
Finished Jul 17 07:56:03 PM PDT 24
Peak memory 206660 kb
Host smart-6227851a-8bfc-4c88-bdca-3381d0d83254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49158
971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.49158971
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1429148275
Short name T484
Test name
Test status
Simulation time 202785688 ps
CPU time 0.82 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:55:38 PM PDT 24
Peak memory 206328 kb
Host smart-2472ec3b-5439-43e1-9c01-b65c5cd9754d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14291
48275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1429148275
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3883697213
Short name T485
Test name
Test status
Simulation time 23292053944 ps
CPU time 24.32 seconds
Started Jul 17 07:55:49 PM PDT 24
Finished Jul 17 07:56:20 PM PDT 24
Peak memory 206400 kb
Host smart-0807d84f-a495-4b74-80f1-5f8ddd2d96bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38836
97213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3883697213
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3283564474
Short name T2682
Test name
Test status
Simulation time 3324198376 ps
CPU time 3.77 seconds
Started Jul 17 07:55:33 PM PDT 24
Finished Jul 17 07:55:38 PM PDT 24
Peak memory 206536 kb
Host smart-701a5f1d-bcc1-44e8-844c-3e988e68111d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32835
64474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3283564474
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3879884739
Short name T2351
Test name
Test status
Simulation time 9291271903 ps
CPU time 87.14 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:57:04 PM PDT 24
Peak memory 206732 kb
Host smart-bdad78fc-4d64-4fdb-ad46-e860534c44c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38798
84739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3879884739
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3243049226
Short name T841
Test name
Test status
Simulation time 4867201076 ps
CPU time 35.96 seconds
Started Jul 17 07:55:42 PM PDT 24
Finished Jul 17 07:56:21 PM PDT 24
Peak memory 206640 kb
Host smart-2e3ce96c-9f8e-4b4c-a394-1270ac56acbe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3243049226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3243049226
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.4149853997
Short name T1312
Test name
Test status
Simulation time 245683036 ps
CPU time 0.95 seconds
Started Jul 17 07:55:34 PM PDT 24
Finished Jul 17 07:55:36 PM PDT 24
Peak memory 206444 kb
Host smart-6e875046-4040-49a9-aa11-857057c78168
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4149853997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.4149853997
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1284126869
Short name T1657
Test name
Test status
Simulation time 206684493 ps
CPU time 0.9 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:55:37 PM PDT 24
Peak memory 206456 kb
Host smart-5e4a7b9c-880c-4b9d-a9cf-b4f15736f0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841
26869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1284126869
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.867400138
Short name T1189
Test name
Test status
Simulation time 5108858638 ps
CPU time 36.25 seconds
Started Jul 17 07:55:42 PM PDT 24
Finished Jul 17 07:56:22 PM PDT 24
Peak memory 206668 kb
Host smart-ca5446ad-7fe5-4272-a222-b01c2a553a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86740
0138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.867400138
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.892183926
Short name T1965
Test name
Test status
Simulation time 5540090704 ps
CPU time 148.91 seconds
Started Jul 17 07:55:33 PM PDT 24
Finished Jul 17 07:58:03 PM PDT 24
Peak memory 206680 kb
Host smart-e3681a1a-bb9c-43a6-8db3-fa1f40a3771a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=892183926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.892183926
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.661164000
Short name T341
Test name
Test status
Simulation time 152951046 ps
CPU time 0.83 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 206452 kb
Host smart-8694cda2-02be-494f-b69c-94c0b46bbdd0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=661164000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.661164000
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3492435355
Short name T1306
Test name
Test status
Simulation time 148585760 ps
CPU time 0.81 seconds
Started Jul 17 07:55:45 PM PDT 24
Finished Jul 17 07:55:51 PM PDT 24
Peak memory 206460 kb
Host smart-13678150-ae60-49ca-a892-21dec3811397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34924
35355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3492435355
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1309595389
Short name T116
Test name
Test status
Simulation time 194465183 ps
CPU time 0.85 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:55:43 PM PDT 24
Peak memory 206628 kb
Host smart-5b8a98ee-9dcb-431e-8ed7-345756622d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
95389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1309595389
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2796116241
Short name T909
Test name
Test status
Simulation time 225626245 ps
CPU time 0.92 seconds
Started Jul 17 07:55:41 PM PDT 24
Finished Jul 17 07:55:45 PM PDT 24
Peak memory 206452 kb
Host smart-dcff0c7c-885c-425b-93b4-4f21c089d828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27961
16241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2796116241
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1729249332
Short name T673
Test name
Test status
Simulation time 188825649 ps
CPU time 0.88 seconds
Started Jul 17 07:55:46 PM PDT 24
Finished Jul 17 07:55:53 PM PDT 24
Peak memory 206456 kb
Host smart-580057f7-67d2-4753-a5e7-2e6ffcfb204b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17292
49332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1729249332
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1677395151
Short name T2724
Test name
Test status
Simulation time 181421523 ps
CPU time 0.82 seconds
Started Jul 17 07:55:41 PM PDT 24
Finished Jul 17 07:55:45 PM PDT 24
Peak memory 206460 kb
Host smart-dd1146b9-f3a5-424b-b19f-b8f16c615ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16773
95151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1677395151
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3606651180
Short name T1451
Test name
Test status
Simulation time 156974974 ps
CPU time 0.78 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:55:56 PM PDT 24
Peak memory 206456 kb
Host smart-e800a984-080e-443f-9339-6f937c5f6fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36066
51180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3606651180
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2804190912
Short name T49
Test name
Test status
Simulation time 209176022 ps
CPU time 1.01 seconds
Started Jul 17 07:55:42 PM PDT 24
Finished Jul 17 07:55:46 PM PDT 24
Peak memory 206464 kb
Host smart-8d64631b-544e-471b-a648-a24a81222d3a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2804190912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2804190912
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2741083369
Short name T332
Test name
Test status
Simulation time 144413177 ps
CPU time 0.74 seconds
Started Jul 17 07:55:39 PM PDT 24
Finished Jul 17 07:55:42 PM PDT 24
Peak memory 206400 kb
Host smart-dfcabb63-6987-447c-9743-d5efc71811e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27410
83369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2741083369
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1711182368
Short name T2533
Test name
Test status
Simulation time 37547853 ps
CPU time 0.66 seconds
Started Jul 17 07:55:46 PM PDT 24
Finished Jul 17 07:55:54 PM PDT 24
Peak memory 206432 kb
Host smart-b31c2ae5-6a1d-4c9f-b3c0-ce5cebd40687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17111
82368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1711182368
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2893328572
Short name T1497
Test name
Test status
Simulation time 22991847269 ps
CPU time 53.14 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:56:36 PM PDT 24
Peak memory 206676 kb
Host smart-0d3b8430-a495-4ec5-b610-eb7f2ae9338c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28933
28572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2893328572
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1183942957
Short name T2305
Test name
Test status
Simulation time 196202417 ps
CPU time 0.91 seconds
Started Jul 17 07:55:34 PM PDT 24
Finished Jul 17 07:55:36 PM PDT 24
Peak memory 206464 kb
Host smart-b1c7085d-5d1c-400d-bbb5-b5213c803cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11839
42957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1183942957
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1386939897
Short name T2061
Test name
Test status
Simulation time 179273584 ps
CPU time 0.85 seconds
Started Jul 17 07:55:42 PM PDT 24
Finished Jul 17 07:55:46 PM PDT 24
Peak memory 206400 kb
Host smart-d3abf58d-0e5e-4bac-8a66-52792ffa6ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13869
39897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1386939897
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.18903682
Short name T2235
Test name
Test status
Simulation time 6706108228 ps
CPU time 162.46 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:58:20 PM PDT 24
Peak memory 206632 kb
Host smart-860de5b9-2e52-42c8-b046-b19b763ed47f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=18903682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.18903682
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1638400893
Short name T163
Test name
Test status
Simulation time 9283070112 ps
CPU time 150.6 seconds
Started Jul 17 07:55:48 PM PDT 24
Finished Jul 17 07:58:26 PM PDT 24
Peak memory 206724 kb
Host smart-e605c478-e261-4590-b2dc-9bbde3f05890
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1638400893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1638400893
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2431550924
Short name T830
Test name
Test status
Simulation time 12565403701 ps
CPU time 90.47 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:57:21 PM PDT 24
Peak memory 206700 kb
Host smart-36fe7c8a-8b73-40e6-9ac5-daaea1e8c3a7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2431550924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2431550924
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1956217323
Short name T1732
Test name
Test status
Simulation time 185111739 ps
CPU time 0.81 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:55:44 PM PDT 24
Peak memory 206448 kb
Host smart-eca5425c-916e-4eec-9a01-b656ff5f2c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19562
17323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1956217323
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.106638043
Short name T1670
Test name
Test status
Simulation time 223434468 ps
CPU time 0.82 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:55:38 PM PDT 24
Peak memory 206444 kb
Host smart-b8c937c2-38de-4fdd-96e7-8108f6591df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10663
8043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.106638043
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3685618283
Short name T797
Test name
Test status
Simulation time 177018762 ps
CPU time 0.83 seconds
Started Jul 17 07:55:40 PM PDT 24
Finished Jul 17 07:55:44 PM PDT 24
Peak memory 206432 kb
Host smart-54f43617-4dc6-4d42-83fd-b6fc5c95c114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36856
18283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3685618283
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2122753077
Short name T952
Test name
Test status
Simulation time 203991340 ps
CPU time 0.82 seconds
Started Jul 17 07:55:35 PM PDT 24
Finished Jul 17 07:55:38 PM PDT 24
Peak memory 206436 kb
Host smart-8e0df6a8-5829-498a-bf0c-6008aad3621e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21227
53077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2122753077
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.551544887
Short name T1853
Test name
Test status
Simulation time 151080288 ps
CPU time 0.76 seconds
Started Jul 17 07:55:43 PM PDT 24
Finished Jul 17 07:55:47 PM PDT 24
Peak memory 206440 kb
Host smart-9c163c9c-421b-4beb-9cc3-360d2b952986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55154
4887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.551544887
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2061455484
Short name T2729
Test name
Test status
Simulation time 237385498 ps
CPU time 1.08 seconds
Started Jul 17 07:55:34 PM PDT 24
Finished Jul 17 07:55:36 PM PDT 24
Peak memory 206456 kb
Host smart-ff897d57-e440-475e-82db-6db2ad5aac37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
55484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2061455484
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.362751943
Short name T2189
Test name
Test status
Simulation time 6151618069 ps
CPU time 56.97 seconds
Started Jul 17 07:55:44 PM PDT 24
Finished Jul 17 07:56:45 PM PDT 24
Peak memory 206672 kb
Host smart-6649312e-7589-4ce2-a3fc-3888b4a6862e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=362751943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.362751943
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1537213179
Short name T813
Test name
Test status
Simulation time 178888359 ps
CPU time 0.8 seconds
Started Jul 17 07:55:39 PM PDT 24
Finished Jul 17 07:55:42 PM PDT 24
Peak memory 206464 kb
Host smart-d411c306-4018-4843-9330-aed717b73a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15372
13179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1537213179
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3896110739
Short name T1647
Test name
Test status
Simulation time 167654765 ps
CPU time 0.83 seconds
Started Jul 17 07:55:41 PM PDT 24
Finished Jul 17 07:55:45 PM PDT 24
Peak memory 206452 kb
Host smart-a94f80aa-a966-43ec-92bc-368ac526e939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38961
10739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3896110739
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.768350449
Short name T1023
Test name
Test status
Simulation time 1272195690 ps
CPU time 2.5 seconds
Started Jul 17 07:55:45 PM PDT 24
Finished Jul 17 07:55:54 PM PDT 24
Peak memory 206664 kb
Host smart-af829f0f-2f8f-42ae-9f8e-19d688066d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76835
0449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.768350449
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3009075353
Short name T828
Test name
Test status
Simulation time 5749299562 ps
CPU time 40.82 seconds
Started Jul 17 07:55:41 PM PDT 24
Finished Jul 17 07:56:25 PM PDT 24
Peak memory 206700 kb
Host smart-65f89c9a-0645-4255-becc-adcda7ffd94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30090
75353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3009075353
Directory /workspace/9.usbdev_streaming_out/latest
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