Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	90634	1		T1	4		T2	2		T3	2
all_values[1]	90634	1		T1	4		T2	2		T3	2
all_values[2]	90634	1		T1	4		T2	2		T3	2
all_values[3]	90634	1		T1	4		T2	2		T3	2
all_values[4]	90634	1		T1	4		T2	2		T3	2
all_values[5]	90634	1		T1	4		T2	2		T3	2
all_values[6]	90634	1		T1	4		T2	2		T3	2
all_values[7]	90634	1		T1	4		T2	2		T3	2
all_values[8]	90634	1		T1	4		T2	2		T3	2
all_values[9]	90634	1		T1	4		T2	2		T3	2
all_values[10]	90634	1		T1	4		T2	2		T3	2
all_values[11]	90634	1		T1	4		T2	2		T3	2
all_values[12]	90634	1		T1	4		T2	2		T3	2
all_values[13]	90634	1		T1	4		T2	2		T3	2
all_values[14]	90634	1		T1	4		T2	2		T3	2
all_values[15]	90634	1		T1	4		T2	2		T3	2
all_values[16]	90634	1		T1	4		T2	2		T3	2
all_values[17]	90634	1		T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1624556	1		T1	70		T2	36		T3	36
auto[1]	6856	1		T1	2		T17	3		T46	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1626490	1		T1	72		T2	36		T3	36
auto[1]	4922	1		T200	120		T197	123		T198	79

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	89664	1		T1	4		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	125	1		T197	2		T198	1		T201	4
all_values[0]	auto[1]	auto[0]	688	1		T46	3		T48	3		T49	3
all_values[0]	auto[1]	auto[1]	157	1		T200	3		T197	6		T198	4
all_values[1]	auto[0]	auto[0]	88831	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	131	1		T200	1		T197	1		T198	1
all_values[1]	auto[1]	auto[0]	1526	1		T1	2		T17	3		T50	3
all_values[1]	auto[1]	auto[1]	146	1		T200	5		T197	5		T198	3
all_values[2]	auto[0]	auto[0]	90230	1		T1	4		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	128	1		T200	2		T197	2		T198	4
all_values[2]	auto[1]	auto[0]	138	1		T36	2		T41	2		T42	2
all_values[2]	auto[1]	auto[1]	138	1		T200	6		T197	3		T198	1
all_values[3]	auto[0]	auto[0]	88912	1		T1	4		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	125	1		T200	4		T197	4		T198	4
all_values[3]	auto[1]	auto[0]	1455	1		T64	1429		T197	2		T199	1
all_values[3]	auto[1]	auto[1]	142	1		T200	4		T198	1		T201	4
all_values[4]	auto[0]	auto[0]	90332	1		T1	4		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	129	1		T200	3		T197	2		T198	1
all_values[4]	auto[1]	auto[0]	27	1		T65	2		T201	2		T199	2
all_values[4]	auto[1]	auto[1]	146	1		T200	5		T197	6		T198	4
all_values[5]	auto[0]	auto[0]	90326	1		T1	4		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	173	1		T200	6		T197	3		T201	1
all_values[5]	auto[1]	auto[0]	10	1		T200	1		T198	1		T266	2
all_values[5]	auto[1]	auto[1]	125	1		T200	1		T197	5		T198	3
all_values[6]	auto[0]	auto[0]	90330	1		T1	4		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	159	1		T200	6		T197	1		T199	6
all_values[6]	auto[1]	auto[0]	33	1		T198	5		T201	4		T199	1
all_values[6]	auto[1]	auto[1]	112	1		T200	2		T197	4		T199	1
all_values[7]	auto[0]	auto[0]	90318	1		T1	4		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	135	1		T200	2		T197	2		T198	1
all_values[7]	auto[1]	auto[0]	39	1		T51	2		T52	2		T53	2
all_values[7]	auto[1]	auto[1]	142	1		T200	6		T197	4		T198	4
all_values[8]	auto[0]	auto[0]	90329	1		T1	4		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	129	1		T200	3		T197	7		T201	4
all_values[8]	auto[1]	auto[0]	36	1		T56	11		T267	3		T268	1
all_values[8]	auto[1]	auto[1]	140	1		T200	5		T197	1		T198	4
all_values[9]	auto[0]	auto[0]	90297	1		T1	4		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	149	1		T200	5		T197	4		T198	3
all_values[9]	auto[1]	auto[0]	49	1		T47	5		T62	5		T63	5
all_values[9]	auto[1]	auto[1]	139	1		T200	3		T197	4		T198	1
all_values[10]	auto[0]	auto[0]	90342	1		T1	4		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	123	1		T197	5		T198	3		T201	3
all_values[10]	auto[1]	auto[0]	24	1		T200	3		T197	1		T265	1
all_values[10]	auto[1]	auto[1]	145	1		T197	1		T198	2		T201	2
all_values[11]	auto[0]	auto[0]	90226	1		T1	4		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	113	1		T200	3		T197	4		T198	1
all_values[11]	auto[1]	auto[0]	120	1		T69	2		T70	2		T71	2
all_values[11]	auto[1]	auto[1]	175	1		T200	4		T197	4		T198	4
all_values[12]	auto[0]	auto[0]	90317	1		T1	4		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	132	1		T200	6		T197	2		T198	1
all_values[12]	auto[1]	auto[0]	37	1		T75	3		T76	3		T77	3
all_values[12]	auto[1]	auto[1]	148	1		T200	1		T197	6		T198	4
all_values[13]	auto[0]	auto[0]	90333	1		T1	4		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	146	1		T200	5		T197	7		T198	5
all_values[13]	auto[1]	auto[0]	31	1		T200	1		T201	1		T269	1
all_values[13]	auto[1]	auto[1]	124	1		T200	1		T197	1		T201	4
all_values[14]	auto[0]	auto[0]	90332	1		T1	4		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	149	1		T200	1		T197	4		T201	1
all_values[14]	auto[1]	auto[0]	29	1		T200	1		T197	2		T265	3
all_values[14]	auto[1]	auto[1]	124	1		T200	5		T197	2		T198	4
all_values[15]	auto[0]	auto[0]	90342	1		T1	4		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	122	1		T200	6		T197	5		T198	1
all_values[15]	auto[1]	auto[0]	36	1		T197	1		T201	1		T265	2
all_values[15]	auto[1]	auto[1]	134	1		T200	1		T197	1		T198	4
all_values[16]	auto[0]	auto[0]	90306	1		T1	4		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	152	1		T200	1		T197	6		T198	2
all_values[16]	auto[1]	auto[0]	49	1		T66	8		T67	8		T68	8
all_values[16]	auto[1]	auto[1]	127	1		T200	6		T197	2		T198	3
all_values[17]	auto[0]	auto[0]	90351	1		T1	4		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	118	1		T200	3		T197	1		T198	2
all_values[17]	auto[1]	auto[0]	45	1		T58	2		T265	1		T270	2
all_values[17]	auto[1]	auto[1]	120	1		T200	5		T197	6		T198	3