Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	90634	1		T1	4		T2	2		T3	2
all_pins[1]	90634	1		T1	4		T2	2		T3	2
all_pins[2]	90634	1		T1	4		T2	2		T3	2
all_pins[3]	90634	1		T1	4		T2	2		T3	2
all_pins[4]	90634	1		T1	4		T2	2		T3	2
all_pins[5]	90634	1		T1	4		T2	2		T3	2
all_pins[6]	90634	1		T1	4		T2	2		T3	2
all_pins[7]	90634	1		T1	4		T2	2		T3	2
all_pins[8]	90634	1		T1	4		T2	2		T3	2
all_pins[9]	90634	1		T1	4		T2	2		T3	2
all_pins[10]	90634	1		T1	4		T2	2		T3	2
all_pins[11]	90634	1		T1	4		T2	2		T3	2
all_pins[12]	90634	1		T1	4		T2	2		T3	2
all_pins[13]	90634	1		T1	4		T2	2		T3	2
all_pins[14]	90634	1		T1	4		T2	2		T3	2
all_pins[15]	90634	1		T1	4		T2	2		T3	2
all_pins[16]	90634	1		T1	4		T2	2		T3	2
all_pins[17]	90634	1		T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1629137	1		T1	71		T2	36		T3	36
values[0x1]	2275	1		T1	1		T17	1		T50	1
transitions[0x0=>0x1]	1981	1		T1	1		T17	1		T50	1
transitions[0x1=>0x0]	1990	1		T1	1		T17	1		T50	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	90524	1		T1	4		T2	2		T3	2
all_pins[0]	values[0x1]	110	1		T271	1		T272	1		T273	1
all_pins[0]	transitions[0x0=>0x1]	98	1		T271	1		T272	1		T273	1
all_pins[0]	transitions[0x1=>0x0]	995	1		T1	1		T17	1		T50	1
all_pins[1]	values[0x0]	89627	1		T1	3		T2	2		T3	2
all_pins[1]	values[0x1]	1007	1		T1	1		T17	1		T50	1
all_pins[1]	transitions[0x0=>0x1]	995	1		T1	1		T17	1		T50	1
all_pins[1]	transitions[0x1=>0x0]	114	1		T36	1		T41	1		T42	1
all_pins[2]	values[0x0]	90508	1		T1	4		T2	2		T3	2
all_pins[2]	values[0x1]	126	1		T36	1		T41	1		T42	1
all_pins[2]	transitions[0x0=>0x1]	108	1		T36	1		T41	1		T42	1
all_pins[2]	transitions[0x1=>0x0]	41	1		T64	1		T200	2		T198	1
all_pins[3]	values[0x0]	90575	1		T1	4		T2	2		T3	2
all_pins[3]	values[0x1]	59	1		T64	1		T200	2		T198	1
all_pins[3]	transitions[0x0=>0x1]	42	1		T64	1		T200	1		T198	1
all_pins[3]	transitions[0x1=>0x0]	54	1		T65	1		T197	2		T198	3
all_pins[4]	values[0x0]	90563	1		T1	4		T2	2		T3	2
all_pins[4]	values[0x1]	71	1		T65	1		T200	1		T197	2
all_pins[4]	transitions[0x0=>0x1]	53	1		T65	1		T200	1		T198	1
all_pins[4]	transitions[0x1=>0x0]	39	1		T200	1		T197	1		T199	1
all_pins[5]	values[0x0]	90577	1		T1	4		T2	2		T3	2
all_pins[5]	values[0x1]	57	1		T200	1		T197	3		T198	2
all_pins[5]	transitions[0x0=>0x1]	40	1		T200	1		T197	3		T198	2
all_pins[5]	transitions[0x1=>0x0]	43	1		T200	1		T197	1		T264	2
all_pins[6]	values[0x0]	90574	1		T1	4		T2	2		T3	2
all_pins[6]	values[0x1]	60	1		T200	1		T197	1		T199	1
all_pins[6]	transitions[0x0=>0x1]	43	1		T197	1		T199	1		T264	1
all_pins[6]	transitions[0x1=>0x0]	47	1		T51	1		T52	1		T53	1
all_pins[7]	values[0x0]	90570	1		T1	4		T2	2		T3	2
all_pins[7]	values[0x1]	64	1		T51	1		T52	1		T53	1
all_pins[7]	transitions[0x0=>0x1]	44	1		T51	1		T52	1		T53	1
all_pins[7]	transitions[0x1=>0x0]	37	1		T56	1		T200	1		T197	1
all_pins[8]	values[0x0]	90577	1		T1	4		T2	2		T3	2
all_pins[8]	values[0x1]	57	1		T56	1		T200	1		T197	1
all_pins[8]	transitions[0x0=>0x1]	39	1		T56	1		T198	2		T199	1
all_pins[8]	transitions[0x1=>0x0]	51	1		T47	2		T62	2		T63	2
all_pins[9]	values[0x0]	90565	1		T1	4		T2	2		T3	2
all_pins[9]	values[0x1]	69	1		T47	2		T62	2		T63	2
all_pins[9]	transitions[0x0=>0x1]	55	1		T47	2		T62	2		T63	2
all_pins[9]	transitions[0x1=>0x0]	64	1		T197	1		T198	2		T201	2
all_pins[10]	values[0x0]	90556	1		T1	4		T2	2		T3	2
all_pins[10]	values[0x1]	78	1		T197	1		T198	2		T201	2
all_pins[10]	transitions[0x0=>0x1]	51	1		T197	1		T198	2		T201	2
all_pins[10]	transitions[0x1=>0x0]	108	1		T69	1		T70	1		T71	1
all_pins[11]	values[0x0]	90499	1		T1	4		T2	2		T3	2
all_pins[11]	values[0x1]	135	1		T69	1		T70	1		T71	1
all_pins[11]	transitions[0x0=>0x1]	117	1		T69	1		T70	1		T71	1
all_pins[11]	transitions[0x1=>0x0]	57	1		T75	1		T76	1		T77	1
all_pins[12]	values[0x0]	90559	1		T1	4		T2	2		T3	2
all_pins[12]	values[0x1]	75	1		T75	1		T76	1		T77	1
all_pins[12]	transitions[0x0=>0x1]	59	1		T75	1		T76	1		T77	1
all_pins[12]	transitions[0x1=>0x0]	37	1		T200	1		T197	1		T201	1
all_pins[13]	values[0x0]	90581	1		T1	4		T2	2		T3	2
all_pins[13]	values[0x1]	53	1		T200	1		T197	1		T201	1
all_pins[13]	transitions[0x0=>0x1]	35	1		T197	1		T199	3		T264	1
all_pins[13]	transitions[0x1=>0x0]	48	1		T200	1		T197	1		T198	3
all_pins[14]	values[0x0]	90568	1		T1	4		T2	2		T3	2
all_pins[14]	values[0x1]	66	1		T200	2		T197	1		T198	3
all_pins[14]	transitions[0x0=>0x1]	49	1		T200	2		T197	1		T198	2
all_pins[14]	transitions[0x1=>0x0]	47	1		T199	1		T266	2		T269	3
all_pins[15]	values[0x0]	90570	1		T1	4		T2	2		T3	2
all_pins[15]	values[0x1]	64	1		T198	1		T199	2		T266	3
all_pins[15]	transitions[0x0=>0x1]	49	1		T198	1		T199	2		T269	5
all_pins[15]	transitions[0x1=>0x0]	62	1		T66	4		T67	4		T68	4
all_pins[16]	values[0x0]	90557	1		T1	4		T2	2		T3	2
all_pins[16]	values[0x1]	77	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x0=>0x1]	71	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x1=>0x0]	41	1		T58	1		T200	1		T197	2
all_pins[17]	values[0x0]	90587	1		T1	4		T2	2		T3	2
all_pins[17]	values[0x1]	47	1		T58	1		T200	1		T197	3
all_pins[17]	transitions[0x0=>0x1]	33	1		T58	1		T200	1		T197	2
all_pins[17]	transitions[0x1=>0x0]	105	1		T271	1		T272	1		T273	1